diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 18 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 19 |
3 files changed, 38 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index c6f2c51bc39d..cabe4ef693d6 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -17,7 +17,7 @@ conn_subsys: bus@5b000000 { }; usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; @@ -28,11 +28,13 @@ conn_subsys: bus@5b000000 { assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; usdhc2: mmc@5b020000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b020000 0x10000>; @@ -49,7 +51,7 @@ conn_subsys: bus@5b000000 { }; usdhc3: mmc@5b030000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b030000 0x10000>; @@ -60,6 +62,8 @@ conn_subsys: bus@5b000000 { assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 6660964ffee8..ae408b67d707 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -77,8 +77,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; @@ -87,8 +89,10 @@ }; &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; @@ -147,6 +151,14 @@ >; }; + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 48190d2ff3b3..26656539b9a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -248,8 +248,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; @@ -258,8 +260,10 @@ }; &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; @@ -462,6 +466,15 @@ >; }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |