diff options
51 files changed, 1124 insertions, 355 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 7c7f475e213e..6abafb6f1844 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -19,38 +19,28 @@ */ #ifdef DEBUG -#include <asm/arch/debug-macro.S> - #if defined(CONFIG_DEBUG_ICEDCC) .macro loadsp, rb .endm - .macro writeb, ch, rb + .macro writeb, ch, rb mcr p14, 0, \ch, c0, c1, 0 .endm #else + +#include <asm/arch/debug-macro.S> + .macro writeb, ch, rb senduart \ch, \rb .endm -#if defined(CONFIG_FOOTBRIDGE) || \ - defined(CONFIG_ARCH_RPC) || \ - defined(CONFIG_ARCH_INTEGRATOR) || \ - defined(CONFIG_ARCH_PXA) || \ - defined(CONFIG_ARCH_IXP4XX) || \ - defined(CONFIG_ARCH_IXP2000) || \ - defined(CONFIG_ARCH_LH7A40X) || \ - defined(CONFIG_ARCH_OMAP) - .macro loadsp, rb - addruart \rb - .endm -#elif defined(CONFIG_ARCH_SA1100) +#if defined(CONFIG_ARCH_SA1100) .macro loadsp, rb mov \rb, #0x80000000 @ physical base address -# if defined(CONFIG_DEBUG_LL_SER3) +#ifdef CONFIG_DEBUG_LL_SER3 add \rb, \rb, #0x00050000 @ Ser3 -# else +#else add \rb, \rb, #0x00010000 @ Ser1 -# endif +#endif .endm #elif defined(CONFIG_ARCH_IOP331) .macro loadsp, rb @@ -64,7 +54,9 @@ add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT .endm #else -#error no serial architecture defined + .macro loadsp, rb + addruart \rb + .endm #endif #endif #endif diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 39a6eea300a2..d0d6e6d2d649 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <asm/irq.h> #include <asm/mach/irq.h> +#include <asm/sizes.h> #include <asm/hardware/sa1111.h> @@ -132,6 +133,17 @@ static struct sa1111_dev_info sa1111_devices[] = { }, }; +void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes) +{ + unsigned int sz = SZ_1M >> PAGE_SHIFT; + + if (node != 0) + sz = 0; + + size[1] = size[0] - sz; + size[0] = sz; +} + /* * SA1111 interrupt support. Since clearing an IRQ while there are * active IRQs causes the interrupt output to pulse, the upper levels diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 756348bf5170..3f97590c91f2 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-git8 -# Thu Sep 8 19:24:02 2005 +# Linux kernel version: 2.6.15-rc1 +# Sun Nov 13 17:41:24 2005 # CONFIG_ARM=y CONFIG_MMU=y @@ -62,6 +62,23 @@ CONFIG_OBSOLETE_MODPARM=y CONFIG_KMOD=y # +# Block layer +# + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# # System Type # # CONFIG_ARCH_CLPS7500 is not set @@ -83,6 +100,7 @@ CONFIG_ARCH_S3C2410=y # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_IMX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_AAEC2000 is not set @@ -108,6 +126,7 @@ CONFIG_CPU_S3C2440=y # S3C2410 Boot # # CONFIG_S3C2410_BOOT_WATCHDOG is not set +# CONFIG_S3C2410_BOOT_ERROR_RESET is not set # # S3C2410 Setup @@ -142,6 +161,7 @@ CONFIG_CPU_TLB_V4WBI=y # # Bus support # +CONFIG_ISA=y CONFIG_ISA_DMA_API=y # @@ -152,7 +172,6 @@ CONFIG_ISA_DMA_API=y # # Kernel Features # -# CONFIG_SMP is not set # CONFIG_PREEMPT is not set # CONFIG_NO_IDLE_HZ is not set # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set @@ -163,6 +182,7 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 CONFIG_ALIGNMENT_TRAP=y # @@ -253,6 +273,10 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set # CONFIG_NET_CLS_ROUTE is not set @@ -260,7 +284,6 @@ CONFIG_TCP_CONG_BIC=y # Network testing # # CONFIG_NET_PKTGEN is not set -# CONFIG_NETFILTER_NETLINK is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set @@ -300,6 +323,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set # # RAM/ROM/Flash chip drivers @@ -335,7 +359,6 @@ CONFIG_MTD_ROM=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set # CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_IMPA7 is not set CONFIG_MTD_BAST=y CONFIG_MTD_BAST_MAXSIZE=4 @@ -370,6 +393,11 @@ CONFIG_MTD_NAND_S3C2410=y # CONFIG_MTD_NAND_NANDSIM is not set # +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# # Parallel port support # CONFIG_PARPORT=y @@ -381,10 +409,12 @@ CONFIG_PARPORT_1284=y # # Plug and Play support # +# CONFIG_PNP is not set # # Block devices # +# CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y @@ -395,14 +425,6 @@ CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_INITRD=y # CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y CONFIG_ATA_OVER_ETH=m # @@ -428,6 +450,7 @@ CONFIG_BLK_DEV_IDEFLOPPY=m CONFIG_IDE_GENERIC=y # CONFIG_IDE_ARM is not set CONFIG_BLK_DEV_IDE_BAST=y +# CONFIG_IDE_CHIPSETS is not set # CONFIG_BLK_DEV_IDEDMA is not set # CONFIG_IDEDMA_AUTO is not set # CONFIG_BLK_DEV_HD is not set @@ -467,6 +490,11 @@ CONFIG_NETDEVICES=y # CONFIG_TUN is not set # +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# # PHY device support # # CONFIG_PHYLIB is not set @@ -475,9 +503,19 @@ CONFIG_NETDEVICES=y # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set # CONFIG_SMC91X is not set -CONFIG_DM9000=m +CONFIG_DM9000=y +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) @@ -490,6 +528,7 @@ CONFIG_DM9000=m # # Token Ring devices # +# CONFIG_TR is not set # # Wireless LAN (non-hamradio) @@ -542,6 +581,9 @@ CONFIG_KEYBOARD_ATKBD=y CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y # CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -568,6 +610,7 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set +# CONFIG_ESPSERIAL is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set @@ -590,6 +633,10 @@ CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set +# CONFIG_SERIAL_8250_FOURPORT is not set +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +# CONFIG_SERIAL_8250_HUB6 is not set # # Non-8250 serial port support @@ -622,6 +669,13 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_S3C2410_WATCHDOG=y + +# +# ISA-based Watchdog Cards +# +# CONFIG_PCWATCHDOG is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_WDT is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set CONFIG_S3C2410_RTC=y @@ -636,6 +690,7 @@ CONFIG_S3C2410_RTC=y # # TPM devices # +# CONFIG_TELCLOCK is not set # # I2C support @@ -653,6 +708,7 @@ CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support # +# CONFIG_I2C_ELEKTOR is not set CONFIG_I2C_ISA=m # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set @@ -671,6 +727,7 @@ CONFIG_SENSORS_EEPROM=m # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set # CONFIG_SENSORS_MAX6875 is not set +# CONFIG_RTC_X1205_I2C is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -737,22 +794,28 @@ CONFIG_SENSORS_LM85=m # Graphics support # CONFIG_FB=y -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_SOFT_CURSOR is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_MACMODES is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S3C2410=y +# CONFIG_FB_S3C2410_DEBUG is not set # CONFIG_FB_VIRTUAL is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y # # Logo configuration @@ -773,6 +836,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB is not set # +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -798,10 +865,6 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set - -# -# XFS support -# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=y @@ -810,6 +873,7 @@ CONFIG_INOTIFY=y CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems @@ -854,6 +918,7 @@ CONFIG_JFFS_FS_VERBOSE=0 CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y @@ -884,6 +949,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -959,7 +1025,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # CONFIG_PRINTK_TIME is not set CONFIG_DEBUG_KERNEL=y -# CONFIG_MAGIC_SYSRQ is not set +CONFIG_MAGIC_SYSRQ=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_SCHEDSTATS is not set @@ -970,7 +1036,9 @@ CONFIG_DETECT_SOFTLOCKUP=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set CONFIG_FRAME_POINTER=y +# CONFIG_RCU_TORTURE_TEST is not set CONFIG_DEBUG_USER=y # CONFIG_DEBUG_WAITQ is not set # CONFIG_DEBUG_ERRORS is not set @@ -998,6 +1066,7 @@ CONFIG_DEBUG_S3C2410_UART=0 # Library routines # # CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index 698eb06545c4..6dbcaf114ad7 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -22,7 +22,7 @@ #include <linux/string.h> #include <asm/arch/akita.h> #include <asm/arch/corgi.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/arch/pxa-regs.h> #include <asm/arch/sharpsl.h> #include <asm/arch/spitz.h> diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index d83e8bad2038..c06e6041df41 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -26,8 +26,6 @@ #include <asm/leds.h> #include <asm/io.h> -#define __io_address(n) __io(IO_ADDRESS(n)) - extern struct sys_timer realview_timer; #define AMBA_DEVICE(name,busid,base,plat) \ diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index 5e917e37d095..c9d7c596b200 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -21,8 +21,6 @@ #include <asm/io.h> #include <asm/irq.h> -#include "core.h" - #define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \ ((cpu) * REALVIEW_TWD_SIZE)) diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 0c7d4ac9a7b3..a8fbd76d8be5 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -17,8 +17,7 @@ #include <asm/cacheflush.h> #include <asm/hardware/arm_scu.h> #include <asm/hardware.h> - -#include "core.h" +#include <asm/io.h> extern void realview_secondary_startup(void); diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 1be2567a7486..4d962717fdf7 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -203,7 +203,7 @@ static struct s3c24xx_uart_clksrc bast_serial_clocks[] = { .name = "pclk", .divisor = 1, .min_baud = 0, - .max_baud = 0. + .max_baud = 0, } }; @@ -216,7 +216,7 @@ static struct s3c2410_uartcfg bast_uartcfgs[] = { .ulcon = ULCON, .ufcon = UFCON, .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks) + .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, [1] = { .hwport = 1, @@ -225,7 +225,7 @@ static struct s3c2410_uartcfg bast_uartcfgs[] = { .ulcon = ULCON, .ufcon = UFCON, .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks) + .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, /* port 2 is not actually used */ [2] = { @@ -235,7 +235,7 @@ static struct s3c2410_uartcfg bast_uartcfgs[] = { .ulcon = ULCON, .ufcon = UFCON, .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks) + .clocks_size = ARRAY_SIZE(bast_serial_clocks), } }; @@ -268,7 +268,7 @@ static struct mtd_partition bast_default_nand_part[] = { [0] = { .name = "Boot Agent", .size = SZ_16K, - .offset = 0 + .offset = 0, }, [1] = { .name = "/boot", @@ -296,28 +296,28 @@ static struct s3c2410_nand_set bast_nand_sets[] = { .nr_chips = 1, .nr_map = smartmedia_map, .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part + .partitions = bast_default_nand_part, }, [1] = { .name = "chip0", .nr_chips = 1, .nr_map = chip0_map, .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part + .partitions = bast_default_nand_part, }, [2] = { .name = "chip1", .nr_chips = 1, .nr_map = chip1_map, .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part + .partitions = bast_default_nand_part, }, [3] = { .name = "chip2", .nr_chips = 1, .nr_map = chip2_map, .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part + .partitions = bast_default_nand_part, } }; @@ -355,17 +355,17 @@ static struct resource bast_dm9k_resource[] = { [0] = { .start = S3C2410_CS5 + BAST_PA_DM9000, .end = S3C2410_CS5 + BAST_PA_DM9000 + 3, - .flags = IORESOURCE_MEM + .flags = IORESOURCE_MEM, }, [1] = { .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40, .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f, - .flags = IORESOURCE_MEM + .flags = IORESOURCE_MEM, }, [2] = { .start = IRQ_DM9000, .end = IRQ_DM9000, - .flags = IORESOURCE_IRQ + .flags = IORESOURCE_IRQ, } }; @@ -375,7 +375,7 @@ static struct resource bast_dm9k_resource[] = { */ static struct dm9000_plat_data bast_dm9k_platdata = { - .flags = DM9000_PLATF_16BITONLY + .flags = DM9000_PLATF_16BITONLY, }; static struct platform_device bast_device_dm9k = { @@ -492,7 +492,7 @@ static struct s3c24xx_board bast_board __initdata = { .devices = bast_devices, .devices_count = ARRAY_SIZE(bast_devices), .clocks = bast_clocks, - .clocks_count = ARRAY_SIZE(bast_clocks) + .clocks_count = ARRAY_SIZE(bast_clocks), }; static void __init bast_map_io(void) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index a1468d7326eb..38d7ebf87920 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -26,7 +26,7 @@ */ #include <linux/init.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/arch/dmtimer.h> #include <asm/io.h> #include <asm/arch/irqs.h> diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/plat-omap/ocpi.c index 2ede2ee8cae4..b86148227480 100644 --- a/arch/arm/plat-omap/ocpi.c +++ b/arch/arm/plat-omap/ocpi.c @@ -34,7 +34,7 @@ #include <asm/io.h> #include <asm/hardware/clock.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #define OCPI_BASE 0xfffec320 #define OCPI_FAULT (OCPI_BASE + 0x00) diff --git a/arch/arm/plat-omap/pm.c b/arch/arm/plat-omap/pm.c index 966cca031ca7..1a24e2c10714 100644 --- a/arch/arm/plat-omap/pm.c +++ b/arch/arm/plat-omap/pm.c @@ -509,7 +509,7 @@ static void omap_pm_init_proc(void) * @state: suspend state we're entering. * */ -//#include <asm/arch/hardware.h> +//#include <asm/hardware.h> static int omap_pm_prepare(suspend_state_t state) { diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/plat-omap/sram-fn.S index 4bea36964a00..66414cc8e6e3 100644 --- a/arch/arm/plat-omap/sram-fn.S +++ b/arch/arm/plat-omap/sram-fn.S @@ -12,7 +12,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> .text diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c index b0d195d1721a..5e7c7e944c9d 100644 --- a/drivers/net/wireless/ipw2200.c +++ b/drivers/net/wireless/ipw2200.c @@ -1110,8 +1110,7 @@ static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv) error->elem_len = elem_len; error->log_len = log_len; error->elem = (struct ipw_error_elem *)error->payload; - error->log = (struct ipw_event *)(error->elem + - (sizeof(*error->elem) * elem_len)); + error->log = (struct ipw_event *)(error->elem + elem_len); ipw_capture_event_log(priv, log_len, error->log); @@ -8926,6 +8925,10 @@ static int ipw_request_direct_scan(struct ipw_priv *priv, char *essid, struct ipw_scan_request_ext scan; int err = 0, scan_type; + if (!(priv->status & STATUS_INIT) || + (priv->status & STATUS_EXIT_PENDING)) + return 0; + down(&priv->sem); if (priv->status & STATUS_RF_KILL_MASK) { diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 84c42c44e04d..20dd85a77813 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -497,7 +497,7 @@ config SCSI_ATA_PIIX If unsure, say N. config SCSI_SATA_MV - tristate "Marvell SATA support" + tristate "Marvell SATA support (HIGHLY EXPERIMENTAL)" depends on SCSI_SATA && PCI && EXPERIMENTAL help This option enables support for the Marvell Serial ATA family. diff --git a/drivers/scsi/ahci.c b/drivers/scsi/ahci.c index 894e7113e0b3..83467a05dc8e 100644 --- a/drivers/scsi/ahci.c +++ b/drivers/scsi/ahci.c @@ -48,7 +48,7 @@ #include <asm/io.h> #define DRV_NAME "ahci" -#define DRV_VERSION "1.01" +#define DRV_VERSION "1.2" enum { @@ -558,23 +558,25 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc) pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16); } -static void ahci_intr_error(struct ata_port *ap, u32 irq_stat) +static void ahci_restart_port(struct ata_port *ap, u32 irq_stat) { void __iomem *mmio = ap->host_set->mmio_base; void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); u32 tmp; int work; - printk(KERN_WARNING "ata%u: port reset, " - "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n", - ap->id, - irq_stat, - readl(mmio + HOST_IRQ_STAT), - readl(port_mmio + PORT_IRQ_STAT), - readl(port_mmio + PORT_CMD), - readl(port_mmio + PORT_TFDATA), - readl(port_mmio + PORT_SCR_STAT), - readl(port_mmio + PORT_SCR_ERR)); + if ((ap->device[0].class != ATA_DEV_ATAPI) || + ((irq_stat & PORT_IRQ_TF_ERR) == 0)) + printk(KERN_WARNING "ata%u: port reset, " + "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n", + ap->id, + irq_stat, + readl(mmio + HOST_IRQ_STAT), + readl(port_mmio + PORT_IRQ_STAT), + readl(port_mmio + PORT_CMD), + readl(port_mmio + PORT_TFDATA), + readl(port_mmio + PORT_SCR_STAT), + readl(port_mmio + PORT_SCR_ERR)); /* stop DMA */ tmp = readl(port_mmio + PORT_CMD); @@ -632,7 +634,7 @@ static void ahci_eng_timeout(struct ata_port *ap) printk(KERN_ERR "ata%u: BUG: timeout without command\n", ap->id); } else { - ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT)); + ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT)); /* hack alert! We cannot use the supplied completion * function from inside the ->eh_strategy_handler() thread. @@ -677,7 +679,7 @@ static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc) err_mask = AC_ERR_HOST_BUS; /* command processing has stopped due to error; restart */ - ahci_intr_error(ap, status); + ahci_restart_port(ap, status); if (qc) ata_qc_complete(qc, err_mask); diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c index 855428ff37e9..333d69dd84ef 100644 --- a/drivers/scsi/ata_piix.c +++ b/drivers/scsi/ata_piix.c @@ -50,7 +50,7 @@ #include <linux/libata.h> #define DRV_NAME "ata_piix" -#define DRV_VERSION "1.04" +#define DRV_VERSION "1.05" enum { PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c index ba1eb8b38e00..665ae79e1fd6 100644 --- a/drivers/scsi/libata-core.c +++ b/drivers/scsi/libata-core.c @@ -1046,6 +1046,30 @@ static unsigned int ata_pio_modes(const struct ata_device *adev) return modes; } +static int ata_qc_wait_err(struct ata_queued_cmd *qc, + struct completion *wait) +{ + int rc = 0; + + if (wait_for_completion_timeout(wait, 30 * HZ) < 1) { + /* timeout handling */ + unsigned int err_mask = ac_err_mask(ata_chk_status(qc->ap)); + + if (!err_mask) { + printk(KERN_WARNING "ata%u: slow completion (cmd %x)\n", + qc->ap->id, qc->tf.command); + } else { + printk(KERN_WARNING "ata%u: qc timeout (cmd %x)\n", + qc->ap->id, qc->tf.command); + rc = -EIO; + } + + ata_qc_complete(qc, err_mask); + } + + return rc; +} + /** * ata_dev_identify - obtain IDENTIFY x DEVICE page * @ap: port on which device we wish to probe resides @@ -1125,7 +1149,7 @@ retry: if (rc) goto err_out; else - wait_for_completion(&wait); + ata_qc_wait_err(qc, &wait); spin_lock_irqsave(&ap->host_set->lock, flags); ap->ops->tf_read(ap, &qc->tf); @@ -1570,11 +1594,13 @@ int ata_timing_compute(struct ata_device *adev, unsigned short speed, /* * Find the mode. - */ + */ if (!(s = ata_timing_find_mode(speed))) return -EINVAL; + memcpy(t, s, sizeof(*s)); + /* * If the drive is an EIDE drive, it can tell us it needs extended * PIO/MW_DMA cycle timing. @@ -1595,7 +1621,7 @@ int ata_timing_compute(struct ata_device *adev, unsigned short speed, * Convert the timing to bus clock counts. */ - ata_timing_quantize(s, t, T, UT); + ata_timing_quantize(t, t, T, UT); /* * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T @@ -2267,7 +2293,7 @@ static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev) if (rc) ata_port_disable(ap); else - wait_for_completion(&wait); + ata_qc_wait_err(qc, &wait); DPRINTK("EXIT\n"); } @@ -2315,7 +2341,7 @@ static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev) if (rc) goto err_out; - wait_for_completion(&wait); + ata_qc_wait_err(qc, &wait); swap_buf_le16(dev->id, ATA_ID_WORDS); @@ -2371,7 +2397,7 @@ static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev) if (rc) ata_port_disable(ap); else - wait_for_completion(&wait); + ata_qc_wait_err(qc, &wait); DPRINTK("EXIT\n"); } diff --git a/drivers/scsi/libata.h b/drivers/scsi/libata.h index 74a84e0ec0a4..8ebaa694d18e 100644 --- a/drivers/scsi/libata.h +++ b/drivers/scsi/libata.h @@ -29,7 +29,7 @@ #define __LIBATA_H__ #define DRV_NAME "libata" -#define DRV_VERSION "1.12" /* must be exactly four chars */ +#define DRV_VERSION "1.20" /* must be exactly four chars */ struct ata_scsi_args { u16 *id; diff --git a/drivers/scsi/sata_mv.c b/drivers/scsi/sata_mv.c index 257c128f4aaa..ac184e60797e 100644 --- a/drivers/scsi/sata_mv.c +++ b/drivers/scsi/sata_mv.c @@ -1,7 +1,7 @@ /* * sata_mv.c - Marvell SATA support * - * Copyright 2005: EMC Corporation, all rights reserved. + * Copyright 2005: EMC Corporation, all rights reserved. * * Please ALWAYS copy linux-ide@vger.kernel.org on emails. * @@ -50,6 +50,9 @@ enum { MV_PCI_REG_BASE = 0, MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ MV_SATAHC0_REG_BASE = 0x20000, + MV_FLASH_CTL = 0x1046c, + MV_GPIO_PORT_CTL = 0x104f0, + MV_RESET_CFG = 0x180d8, MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, @@ -72,11 +75,6 @@ enum { MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), - /* Our DMA boundary is determined by an ePRD being unable to handle - * anything larger than 64KB - */ - MV_DMA_BOUNDARY = 0xffffU, - MV_PORTS_PER_HC = 4, /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ MV_PORT_HC_SHIFT = 2, @@ -86,16 +84,9 @@ enum { /* Host Flags */ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ - MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */ MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO), - MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE | - MV_FLAG_GLBL_SFT_RST), - - chip_504x = 0, - chip_508x = 1, - chip_604x = 2, - chip_608x = 3, + MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, CRQB_FLAG_READ = (1 << 0), CRQB_TAG_SHIFT = 1, @@ -116,8 +107,19 @@ enum { PCI_MASTER_EMPTY = (1 << 3), GLOB_SFT_RST = (1 << 4), - PCI_IRQ_CAUSE_OFS = 0x1d58, - PCI_IRQ_MASK_OFS = 0x1d5c, + MV_PCI_MODE = 0xd00, + MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, + MV_PCI_DISC_TIMER = 0xd04, + MV_PCI_MSI_TRIGGER = 0xc38, + MV_PCI_SERR_MASK = 0xc28, + MV_PCI_XBAR_TMOUT = 0x1d04, + MV_PCI_ERR_LOW_ADDRESS = 0x1d40, + MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, + MV_PCI_ERR_ATTRIBUTE = 0x1d48, + MV_PCI_ERR_COMMAND = 0x1d50, + + PCI_IRQ_CAUSE_OFS = 0x1d58, + PCI_IRQ_MASK_OFS = 0x1d5c, PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, @@ -134,7 +136,7 @@ enum { SELF_INT = (1 << 23), TWSI_INT = (1 << 24), HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ - HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | + HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | HC_MAIN_RSVD), @@ -153,6 +155,15 @@ enum { /* SATA registers */ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ SATA_ACTIVE_OFS = 0x350, + PHY_MODE3 = 0x310, + PHY_MODE4 = 0x314, + PHY_MODE2 = 0x330, + MV5_PHY_MODE = 0x74, + MV5_LT_MODE = 0x30, + MV5_PHY_CTL = 0x0C, + SATA_INTERFACE_CTL = 0x050, + + MV_M2_PREAMP_MASK = 0x7e0, /* Port registers */ EDMA_CFG_OFS = 0, @@ -182,17 +193,16 @@ enum { EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), EDMA_ERR_LNK_DATA_TX = (0x1f << 26), EDMA_ERR_TRANS_PROTO = (1 << 31), - EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | + EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | - EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | + EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | EDMA_ERR_LNK_DATA_RX | - EDMA_ERR_LNK_DATA_TX | + EDMA_ERR_LNK_DATA_TX | EDMA_ERR_TRANS_PROTO), EDMA_REQ_Q_BASE_HI_OFS = 0x10, EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ - EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, EDMA_REQ_Q_OUT_PTR_OFS = 0x18, EDMA_REQ_Q_PTR_SHIFT = 5, @@ -200,7 +210,6 @@ enum { EDMA_RSP_Q_BASE_HI_OFS = 0x1c, EDMA_RSP_Q_IN_PTR_OFS = 0x20, EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ - EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, EDMA_RSP_Q_PTR_SHIFT = 3, EDMA_CMD_OFS = 0x28, @@ -208,14 +217,44 @@ enum { EDMA_DS = (1 << 1), ATA_RST = (1 << 2), + EDMA_IORDY_TMOUT = 0x34, + EDMA_ARB_CFG = 0x38, + /* Host private flags (hp_flags) */ MV_HP_FLAG_MSI = (1 << 0), + MV_HP_ERRATA_50XXB0 = (1 << 1), + MV_HP_ERRATA_50XXB2 = (1 << 2), + MV_HP_ERRATA_60X1B2 = (1 << 3), + MV_HP_ERRATA_60X1C0 = (1 << 4), + MV_HP_50XX = (1 << 5), /* Port private flags (pp_flags) */ MV_PP_FLAG_EDMA_EN = (1 << 0), MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), }; +#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) +#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) + +enum { + /* Our DMA boundary is determined by an ePRD being unable to handle + * anything larger than 64KB + */ + MV_DMA_BOUNDARY = 0xffffU, + + EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, + + EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, +}; + +enum chip_type { + chip_504x, + chip_508x, + chip_5080, + chip_604x, + chip_608x, +}; + /* Command ReQuest Block: 32B */ struct mv_crqb { u32 sg_addr; @@ -252,14 +291,37 @@ struct mv_port_priv { u32 pp_flags; }; +struct mv_port_signal { + u32 amps; + u32 pre; +}; + +struct mv_host_priv; +struct mv_hw_ops { + void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port); + void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); + void (*read_preamp)(struct mv_host_priv *hpriv, int idx, + void __iomem *mmio); + int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int n_hc); + void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); + void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); +}; + struct mv_host_priv { u32 hp_flags; + struct mv_port_signal signal[8]; + const struct mv_hw_ops *ops; }; static void mv_irq_clear(struct ata_port *ap); static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); +static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); +static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); static void mv_phy_reset(struct ata_port *ap); +static void __mv_phy_reset(struct ata_port *ap, int can_sleep); static void mv_host_stop(struct ata_host_set *host_set); static int mv_port_start(struct ata_port *ap); static void mv_port_stop(struct ata_port *ap); @@ -270,6 +332,29 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance, static void mv_eng_timeout(struct ata_port *ap); static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); +static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port); +static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); +static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, + void __iomem *mmio); +static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int n_hc); +static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); +static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio); + +static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port); +static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); +static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, + void __iomem *mmio); +static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int n_hc); +static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); +static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio); +static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port_no); +static void mv_stop_and_reset(struct ata_port *ap); + static struct scsi_host_template mv_sht = { .module = THIS_MODULE, .name = DRV_NAME, @@ -278,7 +363,7 @@ static struct scsi_host_template mv_sht = { .eh_strategy_handler = ata_scsi_error, .can_queue = MV_USE_Q_DEPTH, .this_id = ATA_SHT_THIS_ID, - .sg_tablesize = MV_MAX_SG_CT, + .sg_tablesize = MV_MAX_SG_CT / 2, .max_sectors = ATA_MAX_SECTORS, .cmd_per_lun = ATA_SHT_CMD_PER_LUN, .emulated = ATA_SHT_EMULATED, @@ -290,7 +375,34 @@ static struct scsi_host_template mv_sht = { .ordered_flush = 1, }; -static const struct ata_port_operations mv_ops = { +static const struct ata_port_operations mv5_ops = { + .port_disable = ata_port_disable, + + .tf_load = ata_tf_load, + .tf_read = ata_tf_read, + .check_status = ata_check_status, + .exec_command = ata_exec_command, + .dev_select = ata_std_dev_select, + + .phy_reset = mv_phy_reset, + + .qc_prep = mv_qc_prep, + .qc_issue = mv_qc_issue, + + .eng_timeout = mv_eng_timeout, + + .irq_handler = mv_interrupt, + .irq_clear = mv_irq_clear, + + .scr_read = mv5_scr_read, + .scr_write = mv5_scr_write, + + .port_start = mv_port_start, + .port_stop = mv_port_stop, + .host_stop = mv_host_stop, +}; + +static const struct ata_port_operations mv6_ops = { .port_disable = ata_port_disable, .tf_load = ata_tf_load, @@ -322,37 +434,44 @@ static struct ata_port_info mv_port_info[] = { .sht = &mv_sht, .host_flags = MV_COMMON_FLAGS, .pio_mask = 0x1f, /* pio0-4 */ - .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ - .port_ops = &mv_ops, + .udma_mask = 0x7f, /* udma0-6 */ + .port_ops = &mv5_ops, }, { /* chip_508x */ .sht = &mv_sht, .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), .pio_mask = 0x1f, /* pio0-4 */ - .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ - .port_ops = &mv_ops, + .udma_mask = 0x7f, /* udma0-6 */ + .port_ops = &mv5_ops, + }, + { /* chip_5080 */ + .sht = &mv_sht, + .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), + .pio_mask = 0x1f, /* pio0-4 */ + .udma_mask = 0x7f, /* udma0-6 */ + .port_ops = &mv5_ops, }, { /* chip_604x */ .sht = &mv_sht, .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), .pio_mask = 0x1f, /* pio0-4 */ .udma_mask = 0x7f, /* udma0-6 */ - .port_ops = &mv_ops, + .port_ops = &mv6_ops, }, { /* chip_608x */ .sht = &mv_sht, - .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | + .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | MV_FLAG_DUAL_HC), .pio_mask = 0x1f, /* pio0-4 */ .udma_mask = 0x7f, /* udma0-6 */ - .port_ops = &mv_ops, + .port_ops = &mv6_ops, }, }; static const struct pci_device_id mv_pci_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, - {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x}, + {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080}, {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, @@ -371,6 +490,24 @@ static struct pci_driver mv_pci_driver = { .remove = ata_pci_remove_one, }; +static const struct mv_hw_ops mv5xxx_ops = { + .phy_errata = mv5_phy_errata, + .enable_leds = mv5_enable_leds, + .read_preamp = mv5_read_preamp, + .reset_hc = mv5_reset_hc, + .reset_flash = mv5_reset_flash, + .reset_bus = mv5_reset_bus, +}; + +static const struct mv_hw_ops mv6xxx_ops = { + .phy_errata = mv6_phy_errata, + .enable_leds = mv6_enable_leds, + .read_preamp = mv6_read_preamp, + .reset_hc = mv6_reset_hc, + .reset_flash = mv6_reset_flash, + .reset_bus = mv_reset_pci_bus, +}; + /* * Functions */ @@ -386,11 +523,27 @@ static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); } +static inline unsigned int mv_hc_from_port(unsigned int port) +{ + return port >> MV_PORT_HC_SHIFT; +} + +static inline unsigned int mv_hardport_from_port(unsigned int port) +{ + return port & MV_PORT_MASK; +} + +static inline void __iomem *mv_hc_base_from_port(void __iomem *base, + unsigned int port) +{ + return mv_hc_base(base, mv_hc_from_port(port)); +} + static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) { - return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) + - MV_SATAHC_ARBTR_REG_SZ + - ((port & MV_PORT_MASK) * MV_PORT_REG_SZ)); + return mv_hc_base_from_port(base, port) + + MV_SATAHC_ARBTR_REG_SZ + + (mv_hardport_from_port(port) * MV_PORT_REG_SZ); } static inline void __iomem *mv_ap_base(struct ata_port *ap) @@ -398,9 +551,9 @@ static inline void __iomem *mv_ap_base(struct ata_port *ap) return mv_port_base(ap->host_set->mmio_base, ap->port_no); } -static inline int mv_get_hc_count(unsigned long hp_flags) +static inline int mv_get_hc_count(unsigned long host_flags) { - return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1); + return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1); } static void mv_irq_clear(struct ata_port *ap) @@ -452,7 +605,7 @@ static void mv_stop_dma(struct ata_port *ap) } else { assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); } - + /* now properly wait for the eDMA to stop */ for (i = 1000; i > 0; i--) { reg = readl(port_mmio + EDMA_CMD_OFS); @@ -503,7 +656,7 @@ static void mv_dump_all_regs(void __iomem *mmio_base, int port, struct pci_dev *pdev) { #ifdef ATA_DEBUG - void __iomem *hc_base = mv_hc_base(mmio_base, + void __iomem *hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT); void __iomem *port_base; int start_port, num_ports, p, start_hc, num_hcs, hc; @@ -517,7 +670,7 @@ static void mv_dump_all_regs(void __iomem *mmio_base, int port, start_port = port; num_ports = num_hcs = 1; } - DPRINTK("All registers for port(s) %u-%u:\n", start_port, + DPRINTK("All registers for port(s) %u-%u:\n", start_port, num_ports > 1 ? num_ports - 1 : start_port); if (NULL != pdev) { @@ -585,70 +738,6 @@ static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) } /** - * mv_global_soft_reset - Perform the 6xxx global soft reset - * @mmio_base: base address of the HBA - * - * This routine only applies to 6xxx parts. - * - * LOCKING: - * Inherited from caller. - */ -static int mv_global_soft_reset(void __iomem *mmio_base) -{ - void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS; - int i, rc = 0; - u32 t; - - /* Following procedure defined in PCI "main command and status - * register" table. - */ - t = readl(reg); - writel(t | STOP_PCI_MASTER, reg); - - for (i = 0; i < 1000; i++) { - udelay(1); - t = readl(reg); - if (PCI_MASTER_EMPTY & t) { - break; - } - } - if (!(PCI_MASTER_EMPTY & t)) { - printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); - rc = 1; - goto done; - } - - /* set reset */ - i = 5; - do { - writel(t | GLOB_SFT_RST, reg); - t = readl(reg); - udelay(1); - } while (!(GLOB_SFT_RST & t) && (i-- > 0)); - - if (!(GLOB_SFT_RST & t)) { - printk(KERN_ERR DRV_NAME ": can't set global reset\n"); - rc = 1; - goto done; - } - - /* clear reset and *reenable the PCI master* (not mentioned in spec) */ - i = 5; - do { - writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); - t = readl(reg); - udelay(1); - } while ((GLOB_SFT_RST & t) && (i-- > 0)); - - if (GLOB_SFT_RST & t) { - printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); - rc = 1; - } -done: - return rc; -} - -/** * mv_host_stop - Host specific cleanup/stop routine. * @host_set: host data structure * @@ -701,7 +790,7 @@ static int mv_port_start(struct ata_port *ap) goto err_out; memset(pp, 0, sizeof(*pp)); - mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, + mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); if (!mem) goto err_out_pp; @@ -711,7 +800,7 @@ static int mv_port_start(struct ata_port *ap) if (rc) goto err_out_priv; - /* First item in chunk of DMA memory: + /* First item in chunk of DMA memory: * 32-slot command request table (CRQB), 32 bytes each in size */ pp->crqb = mem; @@ -719,7 +808,7 @@ static int mv_port_start(struct ata_port *ap) mem += MV_CRQB_Q_SZ; mem_dma += MV_CRQB_Q_SZ; - /* Second item: + /* Second item: * 32-slot command response table (CRPB), 8 bytes each in size */ pp->crpb = mem; @@ -733,18 +822,18 @@ static int mv_port_start(struct ata_port *ap) pp->sg_tbl = mem; pp->sg_tbl_dma = mem_dma; - writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT | + writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS); writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); - writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, + writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); - writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, + writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); pp->req_producer = pp->rsp_consumer = 0; @@ -805,20 +894,30 @@ static void mv_fill_sg(struct ata_queued_cmd *qc) struct scatterlist *sg; ata_for_each_sg(sg, qc) { - u32 sg_len; dma_addr_t addr; + u32 sg_len, len, offset; addr = sg_dma_address(sg); sg_len = sg_dma_len(sg); - pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); - pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); - assert(0 == (sg_len & ~MV_DMA_BOUNDARY)); - pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len); - if (ata_sg_is_last(sg, qc)) - pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); + while (sg_len) { + offset = addr & MV_DMA_BOUNDARY; + len = sg_len; + if ((offset + sg_len) > 0x10000) + len = 0x10000 - offset; + + pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); + pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); + pp->sg_tbl[i].flags_size = cpu_to_le32(len); + + sg_len -= len; + addr += len; + + if (!sg_len && ata_sg_is_last(sg, qc)) + pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); - i++; + i++; + } } } @@ -859,7 +958,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc) } /* the req producer index should be the same as we remember it */ - assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> + assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == pp->req_producer); @@ -871,9 +970,9 @@ static void mv_qc_prep(struct ata_queued_cmd *qc) assert(MV_MAX_Q_DEPTH > qc->tag); flags |= qc->tag << CRQB_TAG_SHIFT; - pp->crqb[pp->req_producer].sg_addr = + pp->crqb[pp->req_producer].sg_addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); - pp->crqb[pp->req_producer].sg_addr_hi = + pp->crqb[pp->req_producer].sg_addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags); @@ -896,7 +995,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc) #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ case ATA_CMD_FPDMA_READ: case ATA_CMD_FPDMA_WRITE: - mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); + mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); break; #endif /* FIXME: remove this line when NCQ added */ @@ -962,7 +1061,7 @@ static int mv_qc_issue(struct ata_queued_cmd *qc) pp->req_producer); /* until we do queuing, the queue should be empty at this point */ assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == - ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> + ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); mv_inc_q_index(&pp->req_producer); /* now incr producer index */ @@ -999,15 +1098,15 @@ static u8 mv_get_crpb_status(struct ata_port *ap) out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); /* the response consumer index should be the same as we remember it */ - assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == + assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == pp->rsp_consumer); /* increment our consumer index... */ pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer); - + /* and, until we do NCQ, there should only be 1 CRPB waiting */ - assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> - EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == + assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> + EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == pp->rsp_consumer); /* write out our inc'd consumer index so EDMA knows we're caught up */ @@ -1055,7 +1154,7 @@ static void mv_err_intr(struct ata_port *ap) /* check for fatal here and recover if needed */ if (EDMA_ERR_FATAL & edma_err_cause) { - mv_phy_reset(ap); + mv_stop_and_reset(ap); } } @@ -1120,6 +1219,10 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, handled++; } + if (ap && + (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) + continue; + err_mask = ac_err_mask(ata_status); shift = port << 1; /* (port * 2) */ @@ -1131,14 +1234,15 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, err_mask |= AC_ERR_OTHER; handled++; } - + if (handled && ap) { qc = ata_qc_from_tag(ap, ap->active_tag); if (NULL != qc) { VPRINTK("port %u IRQ found for qc, " "ata_status 0x%x\n", port,ata_status); /* mark qc status appropriately */ - ata_qc_complete(qc, err_mask); + if (!(qc->tf.ctl & ATA_NIEN)) + ata_qc_complete(qc, err_mask); } } } @@ -1146,7 +1250,7 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, } /** - * mv_interrupt - + * mv_interrupt - * @irq: unused * @dev_instance: private data; in this case the host structure * @regs: unused @@ -1156,7 +1260,7 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, * routine to handle. Also check for PCI errors which are only * reported here. * - * LOCKING: + * LOCKING: * This routine holds the host_set lock while processing pending * interrupts. */ @@ -1202,8 +1306,422 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance, return IRQ_RETVAL(handled); } +static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) +{ + void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); + unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; + + return hc_mmio + ofs; +} + +static unsigned int mv5_scr_offset(unsigned int sc_reg_in) +{ + unsigned int ofs; + + switch (sc_reg_in) { + case SCR_STATUS: + case SCR_ERROR: + case SCR_CONTROL: + ofs = sc_reg_in * sizeof(u32); + break; + default: + ofs = 0xffffffffU; + break; + } + return ofs; +} + +static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) +{ + void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); + unsigned int ofs = mv5_scr_offset(sc_reg_in); + + if (ofs != 0xffffffffU) + return readl(mmio + ofs); + else + return (u32) ofs; +} + +static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) +{ + void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); + unsigned int ofs = mv5_scr_offset(sc_reg_in); + + if (ofs != 0xffffffffU) + writelfl(val, mmio + ofs); +} + +static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) +{ + u8 rev_id; + int early_5080; + + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); + + early_5080 = (pdev->device == 0x5080) && (rev_id == 0); + + if (!early_5080) { + u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); + tmp |= (1 << 0); + writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); + } + + mv_reset_pci_bus(pdev, mmio); +} + +static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) +{ + writel(0x0fcfffff, mmio + MV_FLASH_CTL); +} + +static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, + void __iomem *mmio) +{ + void __iomem *phy_mmio = mv5_phy_base(mmio, idx); + u32 tmp; + + tmp = readl(phy_mmio + MV5_PHY_MODE); + + hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ + hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ +} + +static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) +{ + u32 tmp; + + writel(0, mmio + MV_GPIO_PORT_CTL); + + /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ + + tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); + tmp |= ~(1 << 0); + writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); +} + +static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port) +{ + void __iomem *phy_mmio = mv5_phy_base(mmio, port); + const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); + u32 tmp; + int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); + + if (fix_apm_sq) { + tmp = readl(phy_mmio + MV5_LT_MODE); + tmp |= (1 << 19); + writel(tmp, phy_mmio + MV5_LT_MODE); + + tmp = readl(phy_mmio + MV5_PHY_CTL); + tmp &= ~0x3; + tmp |= 0x1; + writel(tmp, phy_mmio + MV5_PHY_CTL); + } + + tmp = readl(phy_mmio + MV5_PHY_MODE); + tmp &= ~mask; + tmp |= hpriv->signal[port].pre; + tmp |= hpriv->signal[port].amps; + writel(tmp, phy_mmio + MV5_PHY_MODE); +} + + +#undef ZERO +#define ZERO(reg) writel(0, port_mmio + (reg)) +static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port) +{ + void __iomem *port_mmio = mv_port_base(mmio, port); + + writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); + + mv_channel_reset(hpriv, mmio, port); + + ZERO(0x028); /* command */ + writel(0x11f, port_mmio + EDMA_CFG_OFS); + ZERO(0x004); /* timer */ + ZERO(0x008); /* irq err cause */ + ZERO(0x00c); /* irq err mask */ + ZERO(0x010); /* rq bah */ + ZERO(0x014); /* rq inp */ + ZERO(0x018); /* rq outp */ + ZERO(0x01c); /* respq bah */ + ZERO(0x024); /* respq outp */ + ZERO(0x020); /* respq inp */ + ZERO(0x02c); /* test control */ + writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); +} +#undef ZERO + +#define ZERO(reg) writel(0, hc_mmio + (reg)) +static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int hc) +{ + void __iomem *hc_mmio = mv_hc_base(mmio, hc); + u32 tmp; + + ZERO(0x00c); + ZERO(0x010); + ZERO(0x014); + ZERO(0x018); + + tmp = readl(hc_mmio + 0x20); + tmp &= 0x1c1c1c1c; + tmp |= 0x03030303; + writel(tmp, hc_mmio + 0x20); +} +#undef ZERO + +static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int n_hc) +{ + unsigned int hc, port; + + for (hc = 0; hc < n_hc; hc++) { + for (port = 0; port < MV_PORTS_PER_HC; port++) + mv5_reset_hc_port(hpriv, mmio, + (hc * MV_PORTS_PER_HC) + port); + + mv5_reset_one_hc(hpriv, mmio, hc); + } + + return 0; +} + +#undef ZERO +#define ZERO(reg) writel(0, mmio + (reg)) +static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) +{ + u32 tmp; + + tmp = readl(mmio + MV_PCI_MODE); + tmp &= 0xff00ffff; + writel(tmp, mmio + MV_PCI_MODE); + + ZERO(MV_PCI_DISC_TIMER); + ZERO(MV_PCI_MSI_TRIGGER); + writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); + ZERO(HC_MAIN_IRQ_MASK_OFS); + ZERO(MV_PCI_SERR_MASK); + ZERO(PCI_IRQ_CAUSE_OFS); + ZERO(PCI_IRQ_MASK_OFS); + ZERO(MV_PCI_ERR_LOW_ADDRESS); + ZERO(MV_PCI_ERR_HIGH_ADDRESS); + ZERO(MV_PCI_ERR_ATTRIBUTE); + ZERO(MV_PCI_ERR_COMMAND); +} +#undef ZERO + +static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) +{ + u32 tmp; + + mv5_reset_flash(hpriv, mmio); + + tmp = readl(mmio + MV_GPIO_PORT_CTL); + tmp &= 0x3; + tmp |= (1 << 5) | (1 << 6); + writel(tmp, mmio + MV_GPIO_PORT_CTL); +} + +/** + * mv6_reset_hc - Perform the 6xxx global soft reset + * @mmio: base address of the HBA + * + * This routine only applies to 6xxx parts. + * + * LOCKING: + * Inherited from caller. + */ +static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int n_hc) +{ + void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; + int i, rc = 0; + u32 t; + + /* Following procedure defined in PCI "main command and status + * register" table. + */ + t = readl(reg); + writel(t | STOP_PCI_MASTER, reg); + + for (i = 0; i < 1000; i++) { + udelay(1); + t = readl(reg); + if (PCI_MASTER_EMPTY & t) { + break; + } + } + if (!(PCI_MASTER_EMPTY & t)) { + printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); + rc = 1; + goto done; + } + + /* set reset */ + i = 5; + do { + writel(t | GLOB_SFT_RST, reg); + t = readl(reg); + udelay(1); + } while (!(GLOB_SFT_RST & t) && (i-- > 0)); + + if (!(GLOB_SFT_RST & t)) { + printk(KERN_ERR DRV_NAME ": can't set global reset\n"); + rc = 1; + goto done; + } + + /* clear reset and *reenable the PCI master* (not mentioned in spec) */ + i = 5; + do { + writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); + t = readl(reg); + udelay(1); + } while ((GLOB_SFT_RST & t) && (i-- > 0)); + + if (GLOB_SFT_RST & t) { + printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); + rc = 1; + } +done: + return rc; +} + +static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, + void __iomem *mmio) +{ + void __iomem *port_mmio; + u32 tmp; + + tmp = readl(mmio + MV_RESET_CFG); + if ((tmp & (1 << 0)) == 0) { + hpriv->signal[idx].amps = 0x7 << 8; + hpriv->signal[idx].pre = 0x1 << 5; + return; + } + + port_mmio = mv_port_base(mmio, idx); + tmp = readl(port_mmio + PHY_MODE2); + + hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ + hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ +} + +static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) +{ + writel(0x00000060, mmio + MV_GPIO_PORT_CTL); +} + +static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port) +{ + void __iomem *port_mmio = mv_port_base(mmio, port); + + u32 hp_flags = hpriv->hp_flags; + int fix_phy_mode2 = + hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); + int fix_phy_mode4 = + hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); + u32 m2, tmp; + + if (fix_phy_mode2) { + m2 = readl(port_mmio + PHY_MODE2); + m2 &= ~(1 << 16); + m2 |= (1 << 31); + writel(m2, port_mmio + PHY_MODE2); + + udelay(200); + + m2 = readl(port_mmio + PHY_MODE2); + m2 &= ~((1 << 16) | (1 << 31)); + writel(m2, port_mmio + PHY_MODE2); + + udelay(200); + } + + /* who knows what this magic does */ + tmp = readl(port_mmio + PHY_MODE3); + tmp &= ~0x7F800000; + tmp |= 0x2A800000; + writel(tmp, port_mmio + PHY_MODE3); + + if (fix_phy_mode4) { + u32 m4; + + m4 = readl(port_mmio + PHY_MODE4); + + if (hp_flags & MV_HP_ERRATA_60X1B2) + tmp = readl(port_mmio + 0x310); + + m4 = (m4 & ~(1 << 1)) | (1 << 0); + + writel(m4, port_mmio + PHY_MODE4); + + if (hp_flags & MV_HP_ERRATA_60X1B2) + writel(tmp, port_mmio + 0x310); + } + + /* Revert values of pre-emphasis and signal amps to the saved ones */ + m2 = readl(port_mmio + PHY_MODE2); + + m2 &= ~MV_M2_PREAMP_MASK; + m2 |= hpriv->signal[port].amps; + m2 |= hpriv->signal[port].pre; + m2 &= ~(1 << 16); + + writel(m2, port_mmio + PHY_MODE2); +} + +static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port_no) +{ + void __iomem *port_mmio = mv_port_base(mmio, port_no); + + writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); + + if (IS_60XX(hpriv)) { + u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); + ifctl |= (1 << 12) | (1 << 7); + writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); + } + + udelay(25); /* allow reset propagation */ + + /* Spec never mentions clearing the bit. Marvell's driver does + * clear the bit, however. + */ + writelfl(0, port_mmio + EDMA_CMD_OFS); + + hpriv->ops->phy_errata(hpriv, mmio, port_no); + + if (IS_50XX(hpriv)) + mdelay(1); +} + +static void mv_stop_and_reset(struct ata_port *ap) +{ + struct mv_host_priv *hpriv = ap->host_set->private_data; + void __iomem *mmio = ap->host_set->mmio_base; + + mv_stop_dma(ap); + + mv_channel_reset(hpriv, mmio, ap->port_no); + + __mv_phy_reset(ap, 0); +} + +static inline void __msleep(unsigned int msec, int can_sleep) +{ + if (can_sleep) + msleep(msec); + else + mdelay(msec); +} + /** - * mv_phy_reset - Perform eDMA reset followed by COMRESET + * __mv_phy_reset - Perform eDMA reset followed by COMRESET * @ap: ATA channel to manipulate * * Part of this is taken from __sata_phy_reset and modified to @@ -1213,41 +1731,47 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance, * Inherited from caller. This is coded to safe to call at * interrupt level, i.e. it does not sleep. */ -static void mv_phy_reset(struct ata_port *ap) +static void __mv_phy_reset(struct ata_port *ap, int can_sleep) { + struct mv_port_priv *pp = ap->private_data; + struct mv_host_priv *hpriv = ap->host_set->private_data; void __iomem *port_mmio = mv_ap_base(ap); struct ata_taskfile tf; struct ata_device *dev = &ap->device[0]; unsigned long timeout; + int retry = 5; + u32 sstatus; VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); - mv_stop_dma(ap); - - writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); - udelay(25); /* allow reset propagation */ - - /* Spec never mentions clearing the bit. Marvell's driver does - * clear the bit, however. - */ - writelfl(0, port_mmio + EDMA_CMD_OFS); - - VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " + DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); - /* proceed to init communications via the scr_control reg */ + /* Issue COMRESET via SControl */ +comreset_retry: scr_write_flush(ap, SCR_CONTROL, 0x301); - mdelay(1); + __msleep(1, can_sleep); + scr_write_flush(ap, SCR_CONTROL, 0x300); - timeout = jiffies + (HZ * 1); + __msleep(20, can_sleep); + + timeout = jiffies + msecs_to_jiffies(200); do { - mdelay(10); - if ((scr_read(ap, SCR_STATUS) & 0xf) != 1) + sstatus = scr_read(ap, SCR_STATUS) & 0x3; + if ((sstatus == 3) || (sstatus == 0)) break; + + __msleep(1, can_sleep); } while (time_before(jiffies, timeout)); - VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " + /* work around errata */ + if (IS_60XX(hpriv) && + (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && + (retry-- > 0)) + goto comreset_retry; + + DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); @@ -1261,6 +1785,21 @@ static void mv_phy_reset(struct ata_port *ap) } ap->cbl = ATA_CBL_SATA; + /* even after SStatus reflects that device is ready, + * it seems to take a while for link to be fully + * established (and thus Status no longer 0x80/0x7F), + * so we poll a bit for that, here. + */ + retry = 20; + while (1) { + u8 drv_stat = ata_check_status(ap); + if ((drv_stat != 0x80) && (drv_stat != 0x7f)) + break; + __msleep(500, can_sleep); + if (retry-- <= 0) + break; + } + tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); @@ -1271,9 +1810,19 @@ static void mv_phy_reset(struct ata_port *ap) VPRINTK("Port disabled post-sig: No device present.\n"); ata_port_disable(ap); } + + writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); + + pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; + VPRINTK("EXIT\n"); } +static void mv_phy_reset(struct ata_port *ap) +{ + __mv_phy_reset(ap, 1); +} + /** * mv_eng_timeout - Routine called by libata when SCSI times out I/O * @ap: ATA channel to manipulate @@ -1291,16 +1840,16 @@ static void mv_eng_timeout(struct ata_port *ap) printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id); DPRINTK("All regs @ start of eng_timeout\n"); - mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, + mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, to_pci_dev(ap->host_set->dev)); qc = ata_qc_from_tag(ap, ap->active_tag); printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", - ap->host_set->mmio_base, ap, qc, qc->scsicmd, + ap->host_set->mmio_base, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd); mv_err_intr(ap); - mv_phy_reset(ap); + mv_stop_and_reset(ap); if (!qc) { printk(KERN_ERR "ata%u: BUG: timeout without command\n", @@ -1336,17 +1885,17 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; unsigned serr_ofs; - /* PIO related setup + /* PIO related setup */ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); - port->error_addr = + port->error_addr = port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); - port->status_addr = + port->status_addr = port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); /* special case: control/altstatus doesn't have ATA_REG_ address */ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; @@ -1362,14 +1911,92 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) /* unmask all EDMA error interrupts */ writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); - VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", + VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", readl(port_mmio + EDMA_CFG_OFS), readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); } +static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv, + unsigned int board_idx) +{ + u8 rev_id; + u32 hp_flags = hpriv->hp_flags; + + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); + + switch(board_idx) { + case chip_5080: + hpriv->ops = &mv5xxx_ops; + hp_flags |= MV_HP_50XX; + + switch (rev_id) { + case 0x1: + hp_flags |= MV_HP_ERRATA_50XXB0; + break; + case 0x3: + hp_flags |= MV_HP_ERRATA_50XXB2; + break; + default: + dev_printk(KERN_WARNING, &pdev->dev, + "Applying 50XXB2 workarounds to unknown rev\n"); + hp_flags |= MV_HP_ERRATA_50XXB2; + break; + } + break; + + case chip_504x: + case chip_508x: + hpriv->ops = &mv5xxx_ops; + hp_flags |= MV_HP_50XX; + + switch (rev_id) { + case 0x0: + hp_flags |= MV_HP_ERRATA_50XXB0; + break; + case 0x3: + hp_flags |= MV_HP_ERRATA_50XXB2; + break; + default: + dev_printk(KERN_WARNING, &pdev->dev, + "Applying B2 workarounds to unknown rev\n"); + hp_flags |= MV_HP_ERRATA_50XXB2; + break; + } + break; + + case chip_604x: + case chip_608x: + hpriv->ops = &mv6xxx_ops; + + switch (rev_id) { + case 0x7: + hp_flags |= MV_HP_ERRATA_60X1B2; + break; + case 0x9: + hp_flags |= MV_HP_ERRATA_60X1C0; + break; + default: + dev_printk(KERN_WARNING, &pdev->dev, + "Applying B2 workarounds to unknown rev\n"); + hp_flags |= MV_HP_ERRATA_60X1B2; + break; + } + break; + + default: + printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); + return 1; + } + + hpriv->hp_flags = hp_flags; + + return 0; +} + /** - * mv_host_init - Perform some early initialization of the host. + * mv_init_host - Perform some early initialization of the host. + * @pdev: host PCI device * @probe_ent: early data struct representing the host * * If possible, do an early global reset of the host. Then do @@ -1378,23 +2005,48 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) * LOCKING: * Inherited from caller. */ -static int mv_host_init(struct ata_probe_ent *probe_ent) +static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, + unsigned int board_idx) { int rc = 0, n_hc, port, hc; void __iomem *mmio = probe_ent->mmio_base; - void __iomem *port_mmio; + struct mv_host_priv *hpriv = probe_ent->private_data; - if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) && - mv_global_soft_reset(probe_ent->mmio_base)) { - rc = 1; + /* global interrupt mask */ + writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); + + rc = mv_chip_id(pdev, hpriv, board_idx); + if (rc) goto done; - } n_hc = mv_get_hc_count(probe_ent->host_flags); probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; + for (port = 0; port < probe_ent->n_ports; port++) + hpriv->ops->read_preamp(hpriv, port, mmio); + + rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); + if (rc) + goto done; + + hpriv->ops->reset_flash(hpriv, mmio); + hpriv->ops->reset_bus(pdev, mmio); + hpriv->ops->enable_leds(hpriv, mmio); + for (port = 0; port < probe_ent->n_ports; port++) { - port_mmio = mv_port_base(mmio, port); + if (IS_60XX(hpriv)) { + void __iomem *port_mmio = mv_port_base(mmio, port); + + u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); + ifctl |= (1 << 12); + writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); + } + + hpriv->ops->phy_errata(hpriv, mmio, port); + } + + for (port = 0; port < probe_ent->n_ports; port++) { + void __iomem *port_mmio = mv_port_base(mmio, port); mv_port_init(&probe_ent->port[port], port_mmio); } @@ -1418,11 +2070,12 @@ static int mv_host_init(struct ata_probe_ent *probe_ent) writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " - "PCI int cause/mask=0x%08x/0x%08x\n", + "PCI int cause/mask=0x%08x/0x%08x\n", readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), readl(mmio + HC_MAIN_IRQ_MASK_OFS), readl(mmio + PCI_IRQ_CAUSE_OFS), readl(mmio + PCI_IRQ_MASK_OFS)); + done: return rc; } @@ -1458,7 +2111,7 @@ static void mv_print_info(struct ata_probe_ent *probe_ent) dev_printk(KERN_INFO, &pdev->dev, "%u slots %u ports %s mode IRQ via %s\n", - (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, + (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); } @@ -1528,7 +2181,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) probe_ent->private_data = hpriv; /* initialize adapter */ - rc = mv_host_init(probe_ent); + rc = mv_init_host(pdev, probe_ent, board_idx); if (rc) { goto err_out_hpriv; } diff --git a/drivers/scsi/sata_promise.c b/drivers/scsi/sata_promise.c index 242d906987ad..8a8e3e3ef0ed 100644 --- a/drivers/scsi/sata_promise.c +++ b/drivers/scsi/sata_promise.c @@ -46,7 +46,7 @@ #include "sata_promise.h" #define DRV_NAME "sata_promise" -#define DRV_VERSION "1.02" +#define DRV_VERSION "1.03" enum { diff --git a/drivers/scsi/sata_qstor.c b/drivers/scsi/sata_qstor.c index 4a6d3067d23c..a8987f5ff5cc 100644 --- a/drivers/scsi/sata_qstor.c +++ b/drivers/scsi/sata_qstor.c @@ -41,7 +41,7 @@ #include <linux/libata.h> #define DRV_NAME "sata_qstor" -#define DRV_VERSION "0.04" +#define DRV_VERSION "0.05" enum { QS_PORTS = 4, diff --git a/drivers/scsi/sata_sil24.c b/drivers/scsi/sata_sil24.c index 55e744d6db88..cb1933a3bd55 100644 --- a/drivers/scsi/sata_sil24.c +++ b/drivers/scsi/sata_sil24.c @@ -139,6 +139,7 @@ enum { PORT_CS_DEV_RST = (1 << 1), /* device reset */ PORT_CS_INIT = (1 << 2), /* port initialize */ PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ + PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ PORT_CS_RESUME = (1 << 6), /* port resume */ PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ @@ -188,11 +189,29 @@ enum { PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ + /* bits of PRB control field */ + PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ + PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ + PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ + PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ + PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ + + /* PRB protocol field */ + PRB_PROT_PACKET = (1 << 0), + PRB_PROT_TCQ = (1 << 1), + PRB_PROT_NCQ = (1 << 2), + PRB_PROT_READ = (1 << 3), + PRB_PROT_WRITE = (1 << 4), + PRB_PROT_TRANSPARENT = (1 << 5), + /* * Other constants */ SGE_TRM = (1 << 31), /* Last SGE in chain */ - PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */ + SGE_LNK = (1 << 30), /* linked list + Points to SGT, not SGE */ + SGE_DRD = (1 << 29), /* discard data read (/dev/null) + data address ignored */ /* board id */ BID_SIL3124 = 0, diff --git a/drivers/scsi/sata_svw.c b/drivers/scsi/sata_svw.c index 57e5a9d964c3..6e7f7c83a75a 100644 --- a/drivers/scsi/sata_svw.c +++ b/drivers/scsi/sata_svw.c @@ -54,7 +54,7 @@ #endif /* CONFIG_PPC_OF */ #define DRV_NAME "sata_svw" -#define DRV_VERSION "1.06" +#define DRV_VERSION "1.07" /* Taskfile registers offsets */ #define K2_SATA_TF_CMD_OFFSET 0x00 diff --git a/drivers/scsi/sata_sx4.c b/drivers/scsi/sata_sx4.c index b4bbe48acab0..dcc3ad9a9d6e 100644 --- a/drivers/scsi/sata_sx4.c +++ b/drivers/scsi/sata_sx4.c @@ -46,7 +46,7 @@ #include "sata_promise.h" #define DRV_NAME "sata_sx4" -#define DRV_VERSION "0.7" +#define DRV_VERSION "0.8" enum { diff --git a/drivers/scsi/sata_vsc.c b/drivers/scsi/sata_vsc.c index 77a6e4b9262d..fcfa486965b4 100644 --- a/drivers/scsi/sata_vsc.c +++ b/drivers/scsi/sata_vsc.c @@ -47,7 +47,7 @@ #include <linux/libata.h> #define DRV_NAME "sata_vsc" -#define DRV_VERSION "1.0" +#define DRV_VERSION "1.1" /* Interrupt register offsets (from chip base address) */ #define VSC_SATA_INT_STAT_OFFSET 0x00 diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h index 7d0ab791b16c..9fc4bcfa1681 100644 --- a/include/asm-arm/arch-clps711x/uncompress.h +++ b/include/asm-arm/arch-clps711x/uncompress.h @@ -19,7 +19,7 @@ */ #include <linux/config.h> #include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/hardware/clps7111.h> #undef CLPS7111_BASE diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h index d33ad6a93749..fdfe0e6848f8 100644 --- a/include/asm-arm/arch-epxa10db/uncompress.h +++ b/include/asm-arm/arch-epxa10db/uncompress.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "asm/arch/platform.h" -#include "asm/arch/hardware.h" +#include "asm/hardware.h" #define UART00_TYPE (volatile unsigned int*) #include "asm/arch/uart00.h" diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h index 2fffacf85a01..9535764bcc71 100644 --- a/include/asm-arm/arch-h720x/uncompress.h +++ b/include/asm-arm/arch-h720x/uncompress.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #define LSR 0x14 #define TEMPTY 0x40 diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h index 238197cfb9d9..f195542898e0 100644 --- a/include/asm-arm/arch-imx/irqs.h +++ b/include/asm-arm/arch-imx/irqs.h @@ -23,7 +23,7 @@ #define __ARM_IRQS_H__ /* Use the imx definitions */ -#include <asm/arch/hardware.h> +#include <asm/hardware.h> /* * IMX Interrupt numbers diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h index d65ab3cd5d5d..8c91674706b1 100644 --- a/include/asm-arm/arch-imx/timex.h +++ b/include/asm-arm/arch-imx/timex.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_TIMEX_H #define __ASM_ARCH_TIMEX_H -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #define CLOCK_TICK_RATE (CLK32) #endif diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h index 0ec7093f7c37..da6981efdc39 100644 --- a/include/asm-arm/arch-integrator/smp.h +++ b/include/asm-arm/arch-integrator/smp.h @@ -3,7 +3,7 @@ #include <linux/config.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/io.h> #define hard_smp_processor_id() \ diff --git a/include/asm-arm/arch-l7200/aux_reg.h b/include/asm-arm/arch-l7200/aux_reg.h index 762cbc76c501..5b4396de16a0 100644 --- a/include/asm-arm/arch-l7200/aux_reg.h +++ b/include/asm-arm/arch-l7200/aux_reg.h @@ -9,7 +9,7 @@ #ifndef _ASM_ARCH_AUXREG_H #define _ASM_ARCH_AUXREG_H -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #define l7200aux_reg *((volatile unsigned int *) (AUX_BASE)) diff --git a/include/asm-arm/arch-l7200/gp_timers.h b/include/asm-arm/arch-l7200/gp_timers.h index 6f20962df248..9c4804d13578 100644 --- a/include/asm-arm/arch-l7200/gp_timers.h +++ b/include/asm-arm/arch-l7200/gp_timers.h @@ -10,7 +10,7 @@ #ifndef _ASM_ARCH_GPTIMERS_H #define _ASM_ARCH_GPTIMERS_H -#include <asm/arch/hardware.h> +#include <asm/hardware.h> /* * Layout of L7200 general purpose timer registers diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h index 1b3885741ac1..f486b72070ea 100644 --- a/include/asm-arm/arch-omap/gpio.h +++ b/include/asm-arm/arch-omap/gpio.h @@ -26,7 +26,7 @@ #ifndef __ASM_ARCH_OMAP_GPIO_H #define __ASM_ARCH_OMAP_GPIO_H -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/arch/irqs.h> #include <asm/io.h> diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 9779686bdceb..4ffce1d77759 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -260,7 +260,7 @@ extern void omap_init_irq(void); * The definition of NR_IRQS is in board-specific header file, which is * included via hardware.h */ -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #ifndef NR_IRQS #define NR_IRQS IH_BOARD_BASE diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h index 305bdeb16ab8..e79d98ab2ab6 100644 --- a/include/asm-arm/arch-omap/mcbsp.h +++ b/include/asm-arm/arch-omap/mcbsp.h @@ -24,7 +24,7 @@ #ifndef __ASM_ARCH_OMAP_MCBSP_H #define __ASM_ARCH_OMAP_MCBSP_H -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #define OMAP730_MCBSP1_BASE 0xfffb1000 #define OMAP730_MCBSP2_BASE 0xfffb1800 diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h index b43cdd2a3874..9af415d2944a 100644 --- a/include/asm-arm/arch-omap/system.h +++ b/include/asm-arm/arch-omap/system.h @@ -7,7 +7,7 @@ #include <linux/config.h> #include <asm/mach-types.h> #include <asm/hardware/clock.h> -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/arch/prcm.h> #ifndef CONFIG_MACH_VOICEBLUE diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h index 67879cdb6ef2..9ca76dc3a7af 100644 --- a/include/asm-arm/arch-realview/hardware.h +++ b/include/asm-arm/arch-realview/hardware.h @@ -27,5 +27,6 @@ /* macro to get at IO space when running virtually */ #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) +#define __io_address(n) __io(IO_ADDRESS(n)) #endif diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h index 9f8fcbca0869..6f3d0ce0ca1e 100644 --- a/include/asm-arm/arch-realview/system.h +++ b/include/asm-arm/arch-realview/system.h @@ -36,7 +36,7 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { - unsigned int hdr_ctrl = (IO_ADDRESS(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET); + void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET; unsigned int val; /* diff --git a/include/asm-arm/arch-rpc/system.h b/include/asm-arm/arch-rpc/system.h index ca3277d1d5ea..729c2ae4b513 100644 --- a/include/asm-arm/arch-rpc/system.h +++ b/include/asm-arm/arch-rpc/system.h @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #include <asm/hardware/iomd.h> #include <asm/io.h> diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h index 0fc555b4c912..018a9f0e3986 100644 --- a/include/asm-arm/arch-sa1100/memory.h +++ b/include/asm-arm/arch-sa1100/memory.h @@ -18,20 +18,10 @@ #ifndef __ASSEMBLY__ #ifdef CONFIG_SA1111 -static inline void -__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) -{ - unsigned int sz = SZ_1M >> PAGE_SHIFT; - - if (node != 0) - sz = 0; - - size[1] = size[0] - sz; - size[0] = sz; -} +void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); #define arch_adjust_zones(node, size, holes) \ - __arch_adjust_zones(node, size, holes) + sa1111_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h index 75b802719723..d586f65c8228 100644 --- a/include/asm-arm/atomic.h +++ b/include/asm-arm/atomic.h @@ -12,6 +12,7 @@ #define __ASM_ARM_ATOMIC_H #include <linux/config.h> +#include <linux/compiler.h> typedef struct { volatile int counter; } atomic_t; @@ -82,11 +83,12 @@ static inline int atomic_sub_return(int i, atomic_t *v) static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) { - u32 oldval, res; + unsigned long oldval, res; do { __asm__ __volatile__("@ atomic_cmpxchg\n" "ldrex %1, [%2]\n" + "mov %0, #0\n" "teq %1, %3\n" "strexeq %0, %4, [%2]\n" : "=&r" (res), "=&r" (oldval) diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index e007dd990da5..7399d431edfe 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ +#include <linux/compiler.h> #include <asm/system.h> #define smp_mb__before_clear_bit() mb() diff --git a/include/asm-arm/hardware/dec21285.h b/include/asm-arm/hardware/dec21285.h index 9049f0ddaecf..6685e3fb97b1 100644 --- a/include/asm-arm/hardware/dec21285.h +++ b/include/asm-arm/hardware/dec21285.h @@ -20,7 +20,7 @@ #include <linux/config.h> #ifndef __ASSEMBLY__ -#include <asm/arch/hardware.h> +#include <asm/hardware.h> #define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x))) #else #define DC21285_IO(x) (x) diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 3d4b810d8c38..81c59facea3b 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARM_MMU_CONTEXT_H #define __ASM_ARM_MMU_CONTEXT_H +#include <linux/compiler.h> #include <asm/cacheflush.h> #include <asm/proc-fns.h> diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 8efa4ebdcacb..5621d61ebc07 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -93,8 +93,6 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), int sig, const char *name); -#include <asm/proc-fns.h> - #define xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) @@ -102,6 +100,8 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, extern asmlinkage void __backtrace(void); extern asmlinkage void c_backtrace(unsigned long fp, int pmode); + +struct mm_struct; extern void show_pte(struct mm_struct *mm, unsigned long addr); extern void __show_regs(struct pt_regs *); diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index 8252a4cd860f..7c98557b717f 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -12,6 +12,7 @@ #ifdef __KERNEL__ +#include <linux/compiler.h> #include <asm/fpstate.h> #define THREAD_SIZE_ORDER 1 diff --git a/include/asm-i386/signal.h b/include/asm-i386/signal.h index cbb47d34aa31..76524b4052ac 100644 --- a/include/asm-i386/signal.h +++ b/include/asm-i386/signal.h @@ -159,14 +159,37 @@ typedef struct sigaltstack { #define __HAVE_ARCH_SIG_BITOPS -static __inline__ void sigaddset(sigset_t *set, int _sig) +#define sigaddset(set,sig) \ + (__builtin_constant_p(sig) ? \ + __const_sigaddset((set),(sig)) : \ + __gen_sigaddset((set),(sig))) + +static __inline__ void __gen_sigaddset(sigset_t *set, int _sig) { - __asm__("btsl %1,%0" : "=m"(*set) : "Ir"(_sig - 1) : "cc"); + __asm__("btsl %1,%0" : "+m"(*set) : "Ir"(_sig - 1) : "cc"); } -static __inline__ void sigdelset(sigset_t *set, int _sig) +static __inline__ void __const_sigaddset(sigset_t *set, int _sig) { - __asm__("btrl %1,%0" : "=m"(*set) : "Ir"(_sig - 1) : "cc"); + unsigned long sig = _sig - 1; + set->sig[sig / _NSIG_BPW] |= 1 << (sig % _NSIG_BPW); +} + +#define sigdelset(set,sig) \ + (__builtin_constant_p(sig) ? \ + __const_sigdelset((set),(sig)) : \ + __gen_sigdelset((set),(sig))) + + +static __inline__ void __gen_sigdelset(sigset_t *set, int _sig) +{ + __asm__("btrl %1,%0" : "+m"(*set) : "Ir"(_sig - 1) : "cc"); +} + +static __inline__ void __const_sigdelset(sigset_t *set, int _sig) +{ + unsigned long sig = _sig - 1; + set->sig[sig / _NSIG_BPW] &= ~(1 << (sig % _NSIG_BPW)); } static __inline__ int __const_sigismember(sigset_t *set, int _sig) diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c index e7d26d9943c2..8ce0ce2ee48e 100644 --- a/net/ipv4/ip_fragment.c +++ b/net/ipv4/ip_fragment.c @@ -71,7 +71,7 @@ struct ipfrag_skb_cb /* Describe an entry in the "incomplete datagrams" queue. */ struct ipq { - struct ipq *next; /* linked list pointers */ + struct hlist_node list; struct list_head lru_list; /* lru list member */ u32 user; u32 saddr; @@ -89,7 +89,6 @@ struct ipq { spinlock_t lock; atomic_t refcnt; struct timer_list timer; /* when will this queue expire? */ - struct ipq **pprev; int iif; struct timeval stamp; }; @@ -99,7 +98,7 @@ struct ipq { #define IPQ_HASHSZ 64 /* Per-bucket lock is easy to add now. */ -static struct ipq *ipq_hash[IPQ_HASHSZ]; +static struct hlist_head ipq_hash[IPQ_HASHSZ]; static DEFINE_RWLOCK(ipfrag_lock); static u32 ipfrag_hash_rnd; static LIST_HEAD(ipq_lru_list); @@ -107,9 +106,7 @@ int ip_frag_nqueues = 0; static __inline__ void __ipq_unlink(struct ipq *qp) { - if(qp->next) - qp->next->pprev = qp->pprev; - *qp->pprev = qp->next; + hlist_del(&qp->list); list_del(&qp->lru_list); ip_frag_nqueues--; } @@ -139,27 +136,18 @@ static void ipfrag_secret_rebuild(unsigned long dummy) get_random_bytes(&ipfrag_hash_rnd, sizeof(u32)); for (i = 0; i < IPQ_HASHSZ; i++) { struct ipq *q; + struct hlist_node *p, *n; - q = ipq_hash[i]; - while (q) { - struct ipq *next = q->next; + hlist_for_each_entry_safe(q, p, n, &ipq_hash[i], list) { unsigned int hval = ipqhashfn(q->id, q->saddr, q->daddr, q->protocol); if (hval != i) { - /* Unlink. */ - if (q->next) - q->next->pprev = q->pprev; - *q->pprev = q->next; + hlist_del(&q->list); /* Relink to new hash chain. */ - if ((q->next = ipq_hash[hval]) != NULL) - q->next->pprev = &q->next; - ipq_hash[hval] = q; - q->pprev = &ipq_hash[hval]; + hlist_add_head(&q->list, &ipq_hash[hval]); } - - q = next; } } write_unlock(&ipfrag_lock); @@ -310,14 +298,16 @@ out: static struct ipq *ip_frag_intern(unsigned int hash, struct ipq *qp_in) { struct ipq *qp; - +#ifdef CONFIG_SMP + struct hlist_node *n; +#endif write_lock(&ipfrag_lock); #ifdef CONFIG_SMP /* With SMP race we have to recheck hash table, because * such entry could be created on other cpu, while we * promoted read lock to write lock. */ - for(qp = ipq_hash[hash]; qp; qp = qp->next) { + hlist_for_each_entry(qp, n, &ipq_hash[hash], list) { if(qp->id == qp_in->id && qp->saddr == qp_in->saddr && qp->daddr == qp_in->daddr && @@ -337,10 +327,7 @@ static struct ipq *ip_frag_intern(unsigned int hash, struct ipq *qp_in) atomic_inc(&qp->refcnt); atomic_inc(&qp->refcnt); - if((qp->next = ipq_hash[hash]) != NULL) - qp->next->pprev = &qp->next; - ipq_hash[hash] = qp; - qp->pprev = &ipq_hash[hash]; + hlist_add_head(&qp->list, &ipq_hash[hash]); INIT_LIST_HEAD(&qp->lru_list); list_add_tail(&qp->lru_list, &ipq_lru_list); ip_frag_nqueues++; @@ -392,9 +379,10 @@ static inline struct ipq *ip_find(struct iphdr *iph, u32 user) __u8 protocol = iph->protocol; unsigned int hash = ipqhashfn(id, saddr, daddr, protocol); struct ipq *qp; + struct hlist_node *n; read_lock(&ipfrag_lock); - for(qp = ipq_hash[hash]; qp; qp = qp->next) { + hlist_for_each_entry(qp, n, &ipq_hash[hash], list) { if(qp->id == id && qp->saddr == saddr && qp->daddr == daddr && diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c index e4fe9ee484dd..5d316cb72ec9 100644 --- a/net/ipv6/reassembly.c +++ b/net/ipv6/reassembly.c @@ -74,7 +74,7 @@ struct ip6frag_skb_cb struct frag_queue { - struct frag_queue *next; + struct hlist_node list; struct list_head lru_list; /* lru list member */ __u32 id; /* fragment id */ @@ -95,14 +95,13 @@ struct frag_queue #define FIRST_IN 2 #define LAST_IN 1 __u16 nhoffset; - struct frag_queue **pprev; }; /* Hash table. */ #define IP6Q_HASHSZ 64 -static struct frag_queue *ip6_frag_hash[IP6Q_HASHSZ]; +static struct hlist_head ip6_frag_hash[IP6Q_HASHSZ]; static DEFINE_RWLOCK(ip6_frag_lock); static u32 ip6_frag_hash_rnd; static LIST_HEAD(ip6_frag_lru_list); @@ -110,9 +109,7 @@ int ip6_frag_nqueues = 0; static __inline__ void __fq_unlink(struct frag_queue *fq) { - if(fq->next) - fq->next->pprev = fq->pprev; - *fq->pprev = fq->next; + hlist_del(&fq->list); list_del(&fq->lru_list); ip6_frag_nqueues--; } @@ -163,28 +160,21 @@ static void ip6_frag_secret_rebuild(unsigned long dummy) get_random_bytes(&ip6_frag_hash_rnd, sizeof(u32)); for (i = 0; i < IP6Q_HASHSZ; i++) { struct frag_queue *q; + struct hlist_node *p, *n; - q = ip6_frag_hash[i]; - while (q) { - struct frag_queue *next = q->next; + hlist_for_each_entry_safe(q, p, n, &ip6_frag_hash[i], list) { unsigned int hval = ip6qhashfn(q->id, &q->saddr, &q->daddr); if (hval != i) { - /* Unlink. */ - if (q->next) - q->next->pprev = q->pprev; - *q->pprev = q->next; + hlist_del(&q->list); /* Relink to new hash chain. */ - if ((q->next = ip6_frag_hash[hval]) != NULL) - q->next->pprev = &q->next; - ip6_frag_hash[hval] = q; - q->pprev = &ip6_frag_hash[hval]; - } + hlist_add_head(&q->list, + &ip6_frag_hash[hval]); - q = next; + } } } write_unlock(&ip6_frag_lock); @@ -337,10 +327,13 @@ static struct frag_queue *ip6_frag_intern(unsigned int hash, struct frag_queue *fq_in) { struct frag_queue *fq; +#ifdef CONFIG_SMP + struct hlist_node *n; +#endif write_lock(&ip6_frag_lock); #ifdef CONFIG_SMP - for (fq = ip6_frag_hash[hash]; fq; fq = fq->next) { + hlist_for_each_entry(fq, n, &ip6_frag_hash[hash], list) { if (fq->id == fq_in->id && ipv6_addr_equal(&fq_in->saddr, &fq->saddr) && ipv6_addr_equal(&fq_in->daddr, &fq->daddr)) { @@ -358,10 +351,7 @@ static struct frag_queue *ip6_frag_intern(unsigned int hash, atomic_inc(&fq->refcnt); atomic_inc(&fq->refcnt); - if((fq->next = ip6_frag_hash[hash]) != NULL) - fq->next->pprev = &fq->next; - ip6_frag_hash[hash] = fq; - fq->pprev = &ip6_frag_hash[hash]; + hlist_add_head(&fq->list, &ip6_frag_hash[hash]); INIT_LIST_HEAD(&fq->lru_list); list_add_tail(&fq->lru_list, &ip6_frag_lru_list); ip6_frag_nqueues++; @@ -401,10 +391,11 @@ static __inline__ struct frag_queue * fq_find(u32 id, struct in6_addr *src, struct in6_addr *dst) { struct frag_queue *fq; + struct hlist_node *n; unsigned int hash = ip6qhashfn(id, src, dst); read_lock(&ip6_frag_lock); - for(fq = ip6_frag_hash[hash]; fq; fq = fq->next) { + hlist_for_each_entry(fq, n, &ip6_frag_hash[hash], list) { if (fq->id == id && ipv6_addr_equal(src, &fq->saddr) && ipv6_addr_equal(dst, &fq->daddr)) { diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index ea094b231d62..1da678303d78 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -387,7 +387,7 @@ nf_ct_invert_tuple(struct nf_conntrack_tuple *inverse, static void nf_ct_unlink_expect(struct nf_conntrack_expect *exp) { ASSERT_WRITE_LOCK(&nf_conntrack_lock); - NF_CT_ASSERT(!timer_pending(&exp_timeout)); + NF_CT_ASSERT(!timer_pending(&exp->timeout)); list_del(&exp->list); NF_CT_STAT_INC(expect_delete); exp->master->expecting--; |