diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx95-verdin.dtsi | 10 | ||||
| -rw-r--r-- | drivers/firmware/imx/se_fw.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 42 | ||||
| -rw-r--r-- | drivers/iio/adc/imx93_adc.c | 21 |
5 files changed, 73 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index d3f46e761bee..57cf5c01d4bf 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -150,6 +150,12 @@ #size-cells = <2>; ranges; + ele_reserved: memory@9c300000 { + compatible = "shared-dma-pool"; + reg = <0 0x9c300000 0 0x100000>; + no-map; + }; + linux_cma: linux,cma { compatible = "shared-dma-pool"; reusable; @@ -174,6 +180,10 @@ status = "disabled"; }; +&ele_fw2 { + memory-region = <&ele_reserved>; +}; + /* SMARC GBE0 */ &enetc_port0 { pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi index 653055e4527d..14bcdd146300 100644 --- a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi @@ -141,6 +141,12 @@ #size-cells = <2>; ranges; + ele_reserved: memory@9c300000 { + compatible = "shared-dma-pool"; + reg = <0 0x9c300000 0 0x100000>; + no-map; + }; + linux_cma: linux,cma { compatible = "shared-dma-pool"; reusable; @@ -162,6 +168,10 @@ status = "okay"; }; +&ele_fw2 { + memory-region = <&ele_reserved>; +}; + /* Verdin ETH_1 (On-module PHY) */ &enetc_port0 { pinctrl-names = "default"; diff --git a/drivers/firmware/imx/se_fw.c b/drivers/firmware/imx/se_fw.c index ab5cbbaef1ff..15b8dc0f1565 100644 --- a/drivers/firmware/imx/se_fw.c +++ b/drivers/firmware/imx/se_fw.c @@ -370,7 +370,7 @@ static struct imx_info_list imx95_info = { .mbox_tx_name = "tx", .mbox_rx_name = "rx", .pool_name = NULL, - .reserved_dma_ranges = false, + .reserved_dma_ranges = true, .pre_if_config = false, .post_if_config = ele_init_fw, .v2x_state_check = true, diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 4c46b8074393..f00ba0fb6b41 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -85,7 +85,12 @@ #define ENABLE_CMD_MODE BIT(0) #define DSI_VID_MODE_CFG 0x38 -#define ENABLE_LOW_POWER (0x3f << 8) +#define ENABLE_LOW_POWER_HFP (0x20 << 8) +#define ENABLE_LOW_POWER_HBP (0x10 << 8) +#define ENABLE_LOW_POWER_VACT (0x8 << 8) +#define ENABLE_LOW_POWER_VFP (0x4 << 8) +#define ENABLE_LOW_POWER_VBP (0x2 << 8) +#define ENABLE_LOW_POWER_VSA (0x1 << 8) #define ENABLE_LOW_POWER_MASK (0x3f << 8) #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 @@ -593,14 +598,21 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) * enabling low power is panel-dependent, we should use the * panel configuration here... */ - val = ENABLE_LOW_POWER; + val = ENABLE_LOW_POWER_VACT | ENABLE_LOW_POWER_VFP | ENABLE_LOW_POWER_VSA | + ENABLE_LOW_POWER_VBP; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - val |= VID_MODE_TYPE_BURST; - else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; - else + val |= VID_MODE_TYPE_BURST | ENABLE_LOW_POWER_HFP | ENABLE_LOW_POWER_HBP; + else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES | ENABLE_LOW_POWER_HFP | + ENABLE_LOW_POWER_HBP; + } else { val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) + val |= ENABLE_LOW_POWER_HFP; + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) + val |= ENABLE_LOW_POWER_HBP; + } #ifdef CONFIG_DEBUG_FS if (dsi->vpg_defs.vpg) { @@ -815,6 +827,24 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); + /* + * This timing fixup allows the HFP to go into low power mode for + * 720p60. There is a line size mismatch between DPI and MIPI + * domain for four lanes using 24 bits per pixel. Forcing the HFP + * into low power mode allows the line timer to be reset, thus + * preserving the DPI timing. Without this adjustment, the MIPI + * domain timing drifts from the DPI domain corrupting the video. + * Most other MIPI controllers have workarounds for this mode's + * behavior. + */ + if (mode->htotal == 1650 && mode->vtotal == 750 && + dsi->lanes == 4 && dsi->format == MIPI_DSI_FMT_RGB888 && + (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) && + !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) && + !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) && + !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) + hbp = hbp - min(32, hbp); + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); } diff --git a/drivers/iio/adc/imx93_adc.c b/drivers/iio/adc/imx93_adc.c index 512d7b95b08e..6c32faf65f4f 100644 --- a/drivers/iio/adc/imx93_adc.c +++ b/drivers/iio/adc/imx93_adc.c @@ -38,6 +38,7 @@ #define IMX93_ADC_PCDR6 0x118 #define IMX93_ADC_PCDR7 0x11c #define IMX93_ADC_CALSTAT 0x39C +#define IMX93_ADC_CALCFG0 0X3A0 /* ADC bit shift */ #define IMX93_ADC_MCR_MODE_MASK BIT(29) @@ -58,6 +59,8 @@ #define IMX93_ADC_IMR_ECH_MASK BIT(0) #define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0) +#define IMX93_ADC_CALCFG0_LDFAIL_MASK BIT(4) + /* ADC status */ #define IMX93_ADC_MSR_ADCSTATUS_IDLE 0 #define IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN 1 @@ -145,7 +148,7 @@ static void imx93_adc_config_ad_clk(struct imx93_adc *adc) static int imx93_adc_calibration(struct imx93_adc *adc) { - u32 mcr, msr; + u32 mcr, msr, calcfg; int ret; /* make sure ADC in power down mode */ @@ -158,6 +161,11 @@ static int imx93_adc_calibration(struct imx93_adc *adc) imx93_adc_power_up(adc); + /* Enable loading of calibrated values even in fail condition */ + calcfg = readl(adc->regs + IMX93_ADC_CALCFG0); + calcfg |= IMX93_ADC_CALCFG0_LDFAIL_MASK; + writel(calcfg, adc->regs + IMX93_ADC_CALCFG0); + /* * TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR, * can add the setting of these bit if need in future. @@ -179,11 +187,14 @@ static int imx93_adc_calibration(struct imx93_adc *adc) /* check whether calbration is success or not */ msr = readl(adc->regs + IMX93_ADC_MSR); - if (msr & IMX93_ADC_MSR_CALFAIL_MASK) { + if (msr & IMX93_ADC_MSR_CALFAIL_MASK) + /* + * Only give warning here, this means the noise of the + * reference voltage do not meet the requirement: + * ADC reference voltage Noise < 1.8V * 1/2^ENOB + * And the reault of ADC is not that accurate. + */ dev_warn(adc->dev, "ADC calibration failed!\n"); - imx93_adc_power_down(adc); - return -EAGAIN; - } return 0; } |