diff options
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index f43dbb75ad4d..5ddb7e9438cf 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -281,6 +281,7 @@ struct fsl_qspi { u32 clk_rate; unsigned int chip_base_addr; /* We may support two chips. */ bool has_second_chip; + u32 ddr_smp; struct mutex lock; struct pm_qos_request pm_qos_req; }; @@ -702,7 +703,8 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) /* Set the Sampling Register for DDR */ reg2 = readl(q->iobase + QUADSPI_SMPR); reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK; - reg2 |= (2 << QUADSPI_SMPR_DDRSMP_SHIFT); + reg2 |= ((q->ddr_smp << QUADSPI_SMPR_DDRSMP_SHIFT) & + QUADSPI_SMPR_DDRSMP_MASK); writel(reg2, q->iobase + QUADSPI_SMPR); /* Enable the module again (enable the DDR too) */ @@ -1028,6 +1030,12 @@ static int fsl_qspi_probe(struct platform_device *pdev) if (IS_ERR(q->clk)) return PTR_ERR(q->clk); + /* find ddrsmp value */ + ret = of_property_read_u32(dev->of_node, "ddrsmp", + &q->ddr_smp); + if (ret) + q->ddr_smp = 0; + ret = fsl_qspi_clk_prep_enable(q); if (ret) { dev_err(dev, "can not enable the clock\n"); |