diff options
84 files changed, 803 insertions, 43674 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7afa9b43e604..ba799ea324ea 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -196,13 +196,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra114-dalmore.dtb \ - tegra114-dalmore-e1611-1000-a00-00.dtb \ - tegra114-dalmore-e1611-1001-a00-00.dtb \ - tegra114-macallan.dtb \ - tegra114-roth.dtb \ tegra114-pluto.dtb \ - tegra114-pluto-powerconfig.dtb \ - tegra114-pismo.dtb \ tegra124-bonaire_sim.dtb \ tegra124-bonaire.dtb \ tegra124-ardbeg.dtb \ diff --git a/arch/arm/boot/dts/panel-l-720p-5.dts b/arch/arm/boot/dts/panel-l-720p-5.dts deleted file mode 100644 index a074691c6c81..000000000000 --- a/arch/arm/boot/dts/panel-l-720p-5.dts +++ /dev/null @@ -1,60 +0,0 @@ -/ { - host1x { - dsi { - panel-l-720p-5 { - compatible = "lg,720p-5"; - nvidia,n-data-lanes = <4>; - nvidia,pixel-format = <3>; - nvidia,refresh-rate = <60>; - nvidia,video-data-type = <0>; - nvidia,video-clock-mode = <0>; - nvidia,video-burst-mode = <1>; - nvidia,controller-vs = <1>; - nvidia,virtual-channel = <0>; - nvidia,panel-reset = <1>; - nvidia,power-saving-suspend = <1>; - nvidia,dsi-init-cmd = <0x0 0x29 0x6 0x0 0x0 0xe0 0x43 0x0 0x80 0x0 0x0 0x0 0x0>, - <0x0 0x29 0x6 0x0 0x0 0xb5 0x34 0x20 0x40 0x0 0x20 0x0 0x0>, - <0x0 0x29 0x6 0x0 0x0 0xb6 0x04 0x74 0x0f 0x16 0x13 0x0 0x0>, - <0x0 0x29 0x3 0x0 0x0 0xc0 0x01 0x08 0x0 0x0>, - <0x0 0x23 0xc1 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xc3 0x0 0x09 0x10 0x02 0x0 0x66 0x20 0x13 0x0 0x0 0x0>, - <0x0 0x29 0x6 0x0 0x0 0xc4 0x23 0x24 0x17 0x17 0x59 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xd0 0x21 0x13 0x67 0x37 0x0c 0x06 0x62 0x23 0x03 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xd1 0x32 0x13 0x66 0x37 0x02 0x06 0x62 0x23 0x03 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xd2 0x41 0x14 0x56 0x37 0x0c 0x06 0x62 0x23 0x03 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xd3 0x52 0x14 0x55 0x37 0x02 0x06 0x62 0x23 0x03 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xd4 0x41 0x14 0x56 0x37 0x0c 0x06 0x62 0x23 0x03 0x0 0x0>, - <0x0 0x29 0xa 0x0 0x0 0xd5 0x52 0x14 0x55 0x37 0x02 0x06 0x62 0x23 0x03 0x0 0x0>, - <0x0 0x15 0x36 0x8 0x0>, - <0x0 0x23 0xf9 0x0 0x0>, - <0x0 0x23 0x70 0x0 0x0>, - <0x0 0x29 0x5 0x0 0x0 0x71 0x0 0x0 0x01 0x01 0x0 0x0>, - <0x0 0x29 0x3 0x0 0x0 0x72 0x01 0x0e 0x0 0x0>, - <0x0 0x29 0x4 0x0 0x0 0x73 0x34 0x52 0x0 0x0 0x0>, - <0x0 0x29 0x4 0x0 0x0 0x74 0x05 0x0 0x06 0x0 0x0>, - <0x0 0x29 0x4 0x0 0x0 0x75 0x03 0x0 0x07 0x0 0x0>, - <0x0 0x29 0x4 0x0 0x0 0x76 0x07 0x0 0x06 0x0 0x0>, - <0x0 0x29 0x9 0x0 0x0 0x77 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f 0x0 0x0>, - <0x0 0x29 0x9 0x0 0x0 0x78 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x0 0x0>, - <0x0 0x29 0x9 0x0 0x0 0x79 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x0 0x0>, - <0x0 0x29 0x9 0x0 0x0 0x7a 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, - <0x0 0x29 0x9 0x0 0x0 0x7b 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, - <0x0 0x29 0x9 0x0 0x0 0x7c 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, - <0x0 0x23 0xc2 0x2 0x0>, - <1 20>, - <0x0 0x23 0xc2 0x6 0x0>, - <1 20>, - <0x0 0x23 0xc2 0x4e 0x0>, - <1 100>, - <0x0 0x5 0x11 0x0 0x0>, - <1 20>, - <0x0 0x23 0xf9 0x80 0x0>, - <1 20>, - <0x0 0x5 0x29 0x0 0x0>; - nvidia,n-init-cmd = <39>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-dalmore-e1611-1000-a00-00.dts b/arch/arm/boot/dts/tegra114-dalmore-e1611-1000-a00-00.dts deleted file mode 100644 index 21a8eee749e8..000000000000 --- a/arch/arm/boot/dts/tegra114-dalmore-e1611-1000-a00-00.dts +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; - -#include <tegra114-platforms/tegra114-dalmore-io-e1611.dtsi> -#include <tegra114-platforms/tegra114-dalmore-e1611-gpio-default.dtsi> -#include <tegra114-platforms/tegra114-dalmore-e1611-pinmux.dtsi> -#include <tegra114-platforms/tegra114-dalmore-powermon.dtsi> - -/ { - model = "NVIDIA Tegra114 dalmore evaluation board"; - compatible = "nvidia,dalmore", "nvidia,tegra114"; - nvidia,dtsfilename = __FILE__; - - pinmux { - default { - gmi_iordy_pi5 { - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-dalmore-e1611-1001-a00-00.dts b/arch/arm/boot/dts/tegra114-dalmore-e1611-1001-a00-00.dts deleted file mode 100644 index 5ad539409356..000000000000 --- a/arch/arm/boot/dts/tegra114-dalmore-e1611-1001-a00-00.dts +++ /dev/null @@ -1,20 +0,0 @@ -/dts-v1/; - -#include <tegra114-platforms/tegra114-dalmore-io-e1611.dtsi> -#include <tegra114-platforms/tegra114-dalmore-e1611-gpio-default.dtsi> -#include <tegra114-platforms/tegra114-dalmore-e1611-pinmux.dtsi> -#include <tegra114-platforms/tegra114-dalmore-powermon.dtsi> - -/ { - model = "NVIDIA Tegra114 dalmore evaluation board"; - compatible = "nvidia,dalmore", "nvidia,tegra114"; - nvidia,dtsfilename = __FILE__; - - pinmux { - default { - kb_col1_pq1 { - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index b05b5b437554..367b1015552c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1,16 +1,748 @@ -/* - * arch/arm/boot/dts/tegra114-dalmore.dts - * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include "tegra114-dalmore-e1611-1000-a00-00.dts" +/dts-v1/; + +/include/ "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra114 Dalmore evaluation board"; + compatible = "nvidia,dalmore", "nvidia,tegra114"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "ulpi"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "ulpi"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,open-drain = <0>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + nvidia,lock = <0>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,open-drain = <0>; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "uartd"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5", + "gmi_cs6_n_pi3", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "spi4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1", + "dap3_sclk_pp3"; + nvidia,function = "displayb"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <0>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <0>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,open-drain = <0>; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,open-drain = <0>; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,open-drain = <0>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,rcv-sel = <1>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "usb"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + nvidia,lock = <0>; + nvidia,open-drain = <1>; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + nvidia,enable-input = <1>; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd4"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb5", + "pbb6", + "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + pcc1 { + nvidia,pins = "pcc1", + "pcc2"; + nvidia,function = "rsvd4"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "gmi"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad13_ph5", + "gmi_ad8_ph0", + "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "gmi"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0", + "gmi_cs0_n_pj0", + "gmi_cs2_n_pk3", + "gmi_cs4_n_pk2", + "gmi_cs7_n_pi6", + "gmi_dqs_p_pj3", + "gmi_iordy_pi5", + "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row4_pr4", + "kb_row6_pr6", + "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "displayb"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <0>; + }; + pu5 { + nvidia,pins = "pu5", + "pu6"; + nvidia,function = "displayb"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + nvidia,enable-input = <1>; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd4"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + nvidia,enable-input = <0>; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <1>; + nvidia,schmitt = <0>; + nvidia,low-power-mode = <3>; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <2>; + nvidia,slew-rate-falling = <2>; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <1>; + nvidia,schmitt = <0>; + nvidia,low-power-mode = <3>; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <0>; + nvidia,slew-rate-falling = <0>; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <1>; + nvidia,schmitt = <0>; + nvidia,low-power-mode = <3>; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <1>; + nvidia,slew-rate-rising = <0>; + nvidia,slew-rate-falling = <0>; + nvidia,drive-type = <1>; + }; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pmc { + nvidia,invert-interrupt; + }; + + sdhci@78000400 { + cd-gpios = <&gpio 170 1>; /* gpio PV2 */ + bus-width = <4>; + status = "okay"; + }; + + sdhci@78000600 { + bus-width = <8>; + status = "okay"; + non-removable; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra114-macallan.dts b/arch/arm/boot/dts/tegra114-macallan.dts deleted file mode 100644 index 74798e433482..000000000000 --- a/arch/arm/boot/dts/tegra114-macallan.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * arch/arm/boot/dts/tegra114-macallan.dts - * - * Copyright (C) 2013-2014 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/dts-v1/; - -/include/ "tegra114.dtsi" -#include "tegra114-platforms/tegra114-macallan-e1645-gpio-default.dtsi" -#include "tegra114-platforms/tegra114-macallan-e1645-pinmux.dtsi" -#include "tegra114-platforms/tegra114-macallan-powermon.dtsi" - -/ { - model = "NVIDIA Tegra114 macallan evaluation board"; - compatible = "nvidia,macallan", "nvidia,tegra114"; - - host1x { - hdmi { - status = "okay"; - }; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - }; - - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - nvidia,dma-request-selector = <&apbdma 0>; - }; - - pmc { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <300>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <2000>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - sdhci@78000600 { - tap-delay = <5>; - trim-delay = <3>; - ddr-clk-limit = <41000000>; - base-clk = <104000000>; - mmc-ocr-mask = <0>; - bus-width = <8>; - built-in; - status = "okay"; - }; - sdhci@78000400 { - cd-gpios = <&gpio 170 0>; /* gpio PV2 */ - tap-delay = <3>; - trim-delay = <3>; - ddr-clk-limit = <41000000>; - base-clk = <208000000>; - bus-width = <4>; - status = "okay"; - }; - sdhci@78000000 { - status = "okay"; - }; - - camera { - status = "okay"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-pismo.dts b/arch/arm/boot/dts/tegra114-pismo.dts deleted file mode 100644 index ec3a6d44c88b..000000000000 --- a/arch/arm/boot/dts/tegra114-pismo.dts +++ /dev/null @@ -1,15 +0,0 @@ -/dts-v1/; - -/include/ "tegra114.dtsi" -#include <tegra114-platforms/tegra114-pismo-gpio-default.dtsi> -#include <tegra114-platforms/tegra114-pismo-pinmux.dtsi> -#include <tegra114-platforms/tegra114-pismo-powermon.dtsi> - -/ { - model = "NVIDIA Tegra114 Pismo evaluation board"; - compatible = "nvidia,pismo", "nvidia,tegra114"; - - i2c@7000d000 { - nvidia,bit-banging-xfer-after-shutdown; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-e1611-gpio-default.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-e1611-gpio-default.dtsi deleted file mode 100644 index e85d57e8be5b..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-e1611-gpio-default.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -#include <dt-bindings/gpio/tegra-gpio.h> - -/ { - gpio: gpio { - gpio-init-names = "default"; - gpio-init-0 = <&gpio_default>; - - gpio_default: default { - gpio-input = <TEGRA_GPIO(X, 5) - TEGRA_GPIO(X, 6) - TEGRA_GPIO(W, 2) - TEGRA_GPIO(W, 3) - TEGRA_GPIO(X, 1) - TEGRA_GPIO(X, 3) - TEGRA_GPIO(V, 0) - TEGRA_GPIO(V, 1) - TEGRA_GPIO(CC, 1) - TEGRA_GPIO(CC, 2) - TEGRA_GPIO(H, 4) - TEGRA_GPIO(H, 7) - TEGRA_GPIO(G, 2) - TEGRA_GPIO(G, 3) - TEGRA_GPIO(K, 0) - TEGRA_GPIO(J, 0) - TEGRA_GPIO(K, 3) - TEGRA_GPIO(K, 2) - TEGRA_GPIO(I, 6) - TEGRA_GPIO(J, 3) - TEGRA_GPIO(I, 4) - TEGRA_GPIO(C, 7) - TEGRA_GPIO(Q, 5) - TEGRA_GPIO(R, 3) - TEGRA_GPIO(R, 4) - TEGRA_GPIO(R, 6) - TEGRA_GPIO(R, 7) - TEGRA_GPIO(S, 0) - TEGRA_GPIO(U, 1) - TEGRA_GPIO(U, 2) - TEGRA_GPIO(U, 5) - TEGRA_GPIO(U, 6) - TEGRA_GPIO(N, 7) - TEGRA_GPIO(K, 5)>; - - gpio-output-low = <TEGRA_GPIO(X, 4) - TEGRA_GPIO(X, 7) - TEGRA_GPIO(P, 1) - TEGRA_GPIO(P, 2) - TEGRA_GPIO(P, 0) - TEGRA_GPIO(P, 3) - TEGRA_GPIO(BB, 3) - TEGRA_GPIO(BB, 5) - TEGRA_GPIO(BB, 6) - TEGRA_GPIO(K, 4) - TEGRA_GPIO(BB, 7) - TEGRA_GPIO(G, 0) - TEGRA_GPIO(G, 1) - TEGRA_GPIO(H, 2) - TEGRA_GPIO(H, 3) - TEGRA_GPIO(H, 5) - TEGRA_GPIO(H, 6) - TEGRA_GPIO(G, 4) - TEGRA_GPIO(H, 0) - TEGRA_GPIO(K, 1) - TEGRA_GPIO(I, 7) - TEGRA_GPIO(CC, 5) - TEGRA_GPIO(V, 3) - TEGRA_GPIO(Q, 3) - TEGRA_GPIO(Q, 6) - TEGRA_GPIO(Q, 7) - TEGRA_GPIO(R, 5) - TEGRA_GPIO(EE, 1) - TEGRA_GPIO(U, 0) - TEGRA_GPIO(U, 3) - TEGRA_GPIO(U, 4)>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-e1611-pinmux.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-e1611-pinmux.dtsi deleted file mode 100644 index e3c7580ab43d..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-e1611-pinmux.dtsi +++ /dev/null @@ -1,1395 +0,0 @@ -#include <dt-bindings/pinctrl/pinctrl-tegra.h> - -/ { - pinmux: pinmux { - pinctrl-names = "default", "drive", "unused"; - pinctrl-0 = <&pinmux_default>; - pinctrl-1 = <&drive_default>; - pinctrl-2 = <&pinmux_unused_lowpower>; - - pinmux_default: default { - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_dqs_p_pj3 { - nvidia,pins = "gmi_dqs_p_pj3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - }; - - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - - drive_default: drive { - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; - }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; - - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,drive-type = <1>; - }; - }; - - pinmux_unused_lowpower: unused_lowpower { - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-io-e1611.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-io-e1611.dtsi deleted file mode 100644 index ec2feea11343..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-io-e1611.dtsi +++ /dev/null @@ -1,184 +0,0 @@ -/include/ "tegra114.dtsi" - -/ { - host1x { - hdmi { - status = "okay"; - }; - }; - - serial@70006000 { - compatible = "nvidia,tegra114-hsuart"; - status = "okay"; - }; - - serial@70006040 { - compatible = "nvidia,tegra114-hsuart"; - status = "okay"; - }; - - serial@70006200 { - compatible = "nvidia,tegra114-hsuart"; - status = "okay"; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - - imx091@36 { - compatible = "nvidia,imx091"; - reg = <0x36>; - - nvidia,num = <0>; - nvidia,sync = <0>; - nvidia,dev_name = "camera"; - - /* imx091 gpios */ - reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ - power-gpios = <&gpio 221 0>; /* gpio PBB5 */ - gp1-gpios = <&gpio 225 0>; /* gpio PCC1 */ - - /* imx091 caps */ - nvidia,identifier = "IMX091"; - nvidia,sensor_nvc_interface = <3>; - nvidia,pixel_types = <0x100>; - nvidia,orientation = <0>; - nvidia,direction = <0>; - nvidia,initial_clock_rate_khz = <6000>; - nvidia,h_sync_edge = <0>; - nvidia,v_sync_edge = <0>; - nvidia,mclk_on_vgp0 = <0>; - nvidia,csi_port = <0>; - nvidia,data_lanes = <4>; - nvidia,virtual_channel_id = <0>; - nvidia,discontinuous_clk_mode = <1>; - nvidia,cil_threshold_settle = <0x0>; - nvidia,min_blank_time_width = <16>; - nvidia,min_blank_time_height = <16>; - nvidia,preferred_mode_index = <0>; - nvidia,external_clock_khz_0 = <24000>; - nvidia,clock_multiplier_0 = <850000>; - nvidia,external_clock_khz_1 = <0>; - nvidia,clock_multiplier_1 = <0>; - - /* flash caps */ - nvidia,sdo_trigger_enabled; - nvidia,adjustable_flash_timing; - - status = "okay"; - - }; - - ov9772@10 { - compatible = "nvidia,ov9772"; - reg = <0x10>; - nvidia,num = <1>; - - nvidia,vcm_vdd; /* extra regulator needed */ - - /* ov9772 gpios */ - reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ - power-gpios = <&gpio 222 0>; /* gpio PBB6 */ - - nvidia,dev_name = "camera"; - status = "okay"; - }; - - ad5816@0E { - compatible = "nvidia,ad5816"; - reg = <0x0E>; - nvidia,cfg = <0>; - nvidia,num = <0>; - nvidia,sync = <0>; - nvidia,dev_name = "focuser"; - status = "okay"; - }; - }; - - i2c@7000d000 { - - tps51632 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6000>; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - nvidia,dma-request-selector = <&apbdma 0>; - }; - - camera { - status = "okay"; - }; - - pmc { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <2000>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - sdhci@78000000 { - status = "disabled"; - }; - - sdhci@78000400 { - cd-gpios = <&gpio 170 0>; /* gpio PV2 */ - tap-delay = <3>; - trim-delay = <3>; - ddr-clk-limit = <41000000>; - base-clk = <208000000>; - bus-width = <4>; - status = "disabled"; - }; - - sdhci@78000600 { - tap-delay = <5>; - trim-delay = <3>; - ddr-clk-limit = <41000000>; - base-clk = <104000000>; - mmc-ocr-mask = <0>; - bus-width = <8>; - built-in; - status = "disabled"; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - }; - - xusb@70090000 { - /* nvidia,uses_external_pmic; - nvidia,gpio_controls_muxed_ss_lanes; */ - nvidia,gpio_ss1_sata = <0>; - nvidia,portmap = <0x301>; /* SSP0, USB2P0, USB2P1 */ - nvidia,ss_portmap = <0x1>; /* SSP0 on USB2P1 */ - nvidia,lane_owner = <0>; /* NULL */ - nvidia,ulpicap = <0>; /* No ulpi support. can we remove */ - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-powermon.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-powermon.dtsi deleted file mode 100644 index 3a2855e7f012..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-dalmore-powermon.dtsi +++ /dev/null @@ -1,211 +0,0 @@ -/ { - i2c@7000c400 { - ina219@40{ - compatible = "ina219x"; - reg = <0x40>; - ti,rail-name = "VDD_12V_DCIN_RS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xAEC0>; - ti,power-lsb = <1831>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@41{ - compatible = "ina219x"; - reg = <0x41>; - ti,rail-name = "VDD_AC_BAT_VIN1"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@42{ - compatible = "ina219x"; - reg = <0x42>; - ti,rail-name = "VDD_5V0_SYS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <2500>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <5>; - ti,precision-multiplier = <1000>; - }; - - ina219@43{ - compatible = "ina219x"; - reg = <0x43>; - ti,rail-name = "VDD_3V3_SYS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <2500>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <5>; - ti,precision-multiplier = <1000>; - }; - - ina219@44{ - compatible = "ina219x"; - reg = <0x44>; - ti,rail-name = "VDD_3V3_SYS_VIN4_5_7"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@45{ - compatible = "ina219x"; - reg = <0x45>; - ti,rail-name = "AVDD_USB_HDMI"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@46{ - compatible = "ina219x"; - reg = <0x46>; - ti,rail-name = "VDD_AC_BAT_D1"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0x7CD2>; - ti,power-lsb = <2563>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@47{ - compatible = "ina219x"; - reg = <0x47>; - ti,rail-name = "VDD_AO_SMPS12_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xAEC0>; - ti,power-lsb = <1831>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@48{ - compatible = "ina219x"; - reg = <0x48>; - ti,rail-name = "VDD_3V3_SYS_SMPS45_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@49{ - compatible = "ina219x"; - reg = <0x49>; - ti,rail-name = "VDD_AO_SMPS2_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4a{ - compatible = "ina219x"; - reg = <0x4a>; - ti,rail-name = "VDDIO_HV_AP"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4b{ - compatible = "ina219x"; - reg = <0x4b>; - ti,rail-name = "VDD_1V8_LDO3_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4c{ - compatible = "ina219x"; - reg = <0x4c>; - ti,rail-name = "VDD_3V3_SYS_LDO4_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4d{ - compatible = "ina219x"; - reg = <0x4d>; - ti,rail-name = "VDD_AO_LDO8_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4e{ - compatible = "ina219x"; - reg = <0x4e>; - ti,rail-name = "VDD_1V8_AP"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4f{ - compatible = "ina219x"; - reg = <0x4f>; - ti,rail-name = "VDD_1V8_DSM"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-e1645-gpio-default.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-e1645-gpio-default.dtsi deleted file mode 100644 index eddaf2d7743a..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-e1645-gpio-default.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -#include <dt-bindings/gpio/tegra-gpio.h> - -/ { - gpio: gpio { - gpio-init-names = "default"; - gpio-init-0 = <&gpio_default>; - - gpio_default: default { - gpio-input = < TEGRA_GPIO(X, 5) - TEGRA_GPIO(X, 6) - TEGRA_GPIO(W, 2) - TEGRA_GPIO(W, 3) - TEGRA_GPIO(X, 1) - TEGRA_GPIO(X, 3) - TEGRA_GPIO(V, 0) - TEGRA_GPIO(V, 1) - TEGRA_GPIO(O, 3) - TEGRA_GPIO(O, 4) - TEGRA_GPIO(O, 5) - TEGRA_GPIO(CC, 1) - TEGRA_GPIO(CC, 2) - TEGRA_GPIO(G, 2) - TEGRA_GPIO(G, 3) - TEGRA_GPIO(K, 0) - TEGRA_GPIO(J, 0) - TEGRA_GPIO(K, 3) - TEGRA_GPIO(K, 2) - TEGRA_GPIO(I, 6) - TEGRA_GPIO(J, 3) - TEGRA_GPIO(I, 5) - TEGRA_GPIO(C, 7) - TEGRA_GPIO(Q, 0) - TEGRA_GPIO(Q, 1) - TEGRA_GPIO(Q, 2) - TEGRA_GPIO(Q, 5) - TEGRA_GPIO(R, 0) - TEGRA_GPIO(R, 1) - TEGRA_GPIO(R, 2) - TEGRA_GPIO(R, 3) - TEGRA_GPIO(R, 4) - TEGRA_GPIO(R, 7) - TEGRA_GPIO(U, 1) - TEGRA_GPIO(U, 2) - TEGRA_GPIO(U, 5) - TEGRA_GPIO(U, 6) - TEGRA_GPIO(N, 7)>; - - gpio-output-low = < TEGRA_GPIO(X, 4) - TEGRA_GPIO(X, 7) - TEGRA_GPIO(P, 1) - TEGRA_GPIO(P, 2) - TEGRA_GPIO(P, 0) - TEGRA_GPIO(P, 3) - TEGRA_GPIO(BB, 3) - TEGRA_GPIO(BB, 4) - TEGRA_GPIO(BB, 5) - TEGRA_GPIO(BB, 6) - TEGRA_GPIO(BB, 7) - TEGRA_GPIO(G, 0) - TEGRA_GPIO(G, 1) - TEGRA_GPIO(H, 2) - TEGRA_GPIO(H, 3) - TEGRA_GPIO(H, 4) - TEGRA_GPIO(H, 5) - TEGRA_GPIO(H, 6) - TEGRA_GPIO(H, 0) - TEGRA_GPIO(K, 1) - TEGRA_GPIO(K, 4) - TEGRA_GPIO(I, 4) - TEGRA_GPIO(I, 7) - TEGRA_GPIO(CC, 5) - TEGRA_GPIO(V, 3) - TEGRA_GPIO(Q, 3) - TEGRA_GPIO(Q, 6) - TEGRA_GPIO(Q, 7) - TEGRA_GPIO(R, 5) - TEGRA_GPIO(EE, 1) - TEGRA_GPIO(U, 0) - TEGRA_GPIO(U, 3) - TEGRA_GPIO(U, 4) - TEGRA_GPIO(K, 6)>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-e1645-pinmux.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-e1645-pinmux.dtsi deleted file mode 100644 index a16a851065a7..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-e1645-pinmux.dtsi +++ /dev/null @@ -1,1518 +0,0 @@ -#include <dt-bindings/pinctrl/pinctrl-tegra.h> - -/ { - pinmux: pinmux { - pinctrl-names = "default", "drive", "unused", "suspend"; - pinctrl-0 = <&pinmux_default>; - pinctrl-1 = <&drive_default>; - pinctrl-2 = <&pinmux_unused_lowpower>; - pinctrl-3 = <&pinmux_suspend>; - - pinmux_default: default { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - }; - - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; - }; - - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - }; - - drive_default: drive { - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; - }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; - - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,drive-type = <1>; - }; - }; - - pinmux_unused_lowpower: unused_pins { - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_ad15_ph7 { - nvidia,pins = "gmi_ad15_ph7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_dqs_p_pj3 { - nvidia,pins = "gmi_dqs_p_pj3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - - pinmux_suspend: suspend_pins { - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-powermon.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-powermon.dtsi deleted file mode 100644 index 7dd53df302d5..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-macallan-powermon.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -/ { - i2c@7000c400 { - ina219@40{ - compatible = "ina219x"; - reg = <0x40>; - ti,rail-name = "VD_CPU"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0x7CD2>; - ti,power-lsb = <2563>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <1>; - ti,precision-multiplier = <1000>; - }; - - ina219@41{ - compatible = "ina219x"; - reg = <0x41>; - ti,rail-name = "VD_SOC"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0x7CD2>; - ti,power-lsb = <2563>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <1>; - ti,precision-multiplier = <1000>; - }; - - ina219@42{ - compatible = "ina219x"; - reg = <0x42>; - ti,rail-name = "VS_DDR0"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@43{ - compatible = "ina219x"; - reg = <0x43>; - ti,rail-name = "VS_DDR1"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@44{ - compatible = "ina219x"; - reg = <0x44>; - ti,rail-name = ""; - ti,continuous-config = <0x0000>; - ti,trigger-config = <0x0000>; - ti,calibration-data = <0x4C4C4543>; - ti,divisor = <17494>; - }; - - ina219@45{ - compatible = "ina219x"; - reg = <0x45>; - ti,rail-name = "VD_LCD_HV"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@46{ - compatible = "ina219x"; - reg = <0x46>; - ti,rail-name = "VS_SYS_1V8"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0x7CD2>; - ti,power-lsb = <2563>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@47{ - compatible = "ina219x"; - reg = <0x47>; - ti,rail-name = "VD_AP_1V8"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@48{ - compatible = "ina219x"; - reg = <0x48>; - ti,rail-name = "VD_AP_RTC"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@49{ - compatible = "ina219x"; - reg = <0x49>; - ti,rail-name = "VS_AUD_SYS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4a{ - compatible = "ina219x"; - reg = <0x4a>; - ti,rail-name = "VD_DDR0"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xAEC0>; - ti,power-lsb = <1831>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4b{ - compatible = "ina219x"; - reg = <0x4b>; - ti,rail-name = "VD_DDR1"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xAEC0>; - ti,power-lsb = <1831>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4c{ - compatible = "ina219x"; - reg = <0x4c>; - ti,rail-name = "VD_AP_VBUS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <200>; - ti,precision-multiplier = <1000>; - }; - - ina219@4d{ - compatible = "ina219x"; - reg = <0x4d>; - ti,rail-name = "VS_SYS_2V9"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4e{ - compatible = "ina219x"; - reg = <0x4e>; - ti,rail-name = "VA_PLLX"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4f{ - compatible = "ina219x"; - reg = <0x4f>; - ti,rail-name = "VA_AP_1V2"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-gpio-default.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-gpio-default.dtsi deleted file mode 100644 index 3f1846a21be1..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-gpio-default.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -#include <dt-bindings/gpio/tegra-gpio.h> - -/ { - gpio: gpio { - gpio-init-names = "default"; - gpio-init-0 = <&gpio_default>; - - gpio_default: default { - gpio-input = < TEGRA_GPIO(X, 5) - TEGRA_GPIO(X, 6) - TEGRA_GPIO(W, 2) - TEGRA_GPIO(W, 3) - TEGRA_GPIO(X, 1) - TEGRA_GPIO(X, 3) - TEGRA_GPIO(V, 0) - TEGRA_GPIO(V, 1) - TEGRA_GPIO(CC, 1) - TEGRA_GPIO(CC, 2) - TEGRA_GPIO(H, 4) - TEGRA_GPIO(H, 7) - TEGRA_GPIO(G, 2) - TEGRA_GPIO(G, 3) - TEGRA_GPIO(K, 0) - TEGRA_GPIO(J, 0) - TEGRA_GPIO(K, 3) - TEGRA_GPIO(K, 2) - TEGRA_GPIO(I, 6) - TEGRA_GPIO(J, 3) - TEGRA_GPIO(I, 5) - TEGRA_GPIO(I, 4) - TEGRA_GPIO(C, 7) - TEGRA_GPIO(Q, 5) - TEGRA_GPIO(R, 3) - TEGRA_GPIO(R, 4) - TEGRA_GPIO(R, 6) - TEGRA_GPIO(R, 7) - TEGRA_GPIO(S, 0) - TEGRA_GPIO(U, 1) - TEGRA_GPIO(U, 2) - TEGRA_GPIO(U, 5) - TEGRA_GPIO(U, 6) - TEGRA_GPIO(N, 7) - TEGRA_GPIO(K, 5)>; - - gpio-output-low = < TEGRA_GPIO(X, 4) - TEGRA_GPIO(X, 7) - TEGRA_GPIO(P, 1) - TEGRA_GPIO(P, 2) - TEGRA_GPIO(P, 0) - TEGRA_GPIO(P, 3) - TEGRA_GPIO(BB, 3) - TEGRA_GPIO(BB, 5) - TEGRA_GPIO(BB, 6) - TEGRA_GPIO(BB, 7) - TEGRA_GPIO(G, 0) - TEGRA_GPIO(G, 1) - TEGRA_GPIO(H, 2) - TEGRA_GPIO(H, 3) - TEGRA_GPIO(H, 5) - TEGRA_GPIO(H, 6) - TEGRA_GPIO(G, 4) - TEGRA_GPIO(H, 0) - TEGRA_GPIO(K, 1) - TEGRA_GPIO(K, 4) - TEGRA_GPIO(I, 7) - TEGRA_GPIO(CC, 5) - TEGRA_GPIO(V, 3) - TEGRA_GPIO(Q, 3) - TEGRA_GPIO(Q, 6) - TEGRA_GPIO(Q, 7) - TEGRA_GPIO(R, 5) - TEGRA_GPIO(EE, 1) - TEGRA_GPIO(U, 0) - TEGRA_GPIO(U, 3) - TEGRA_GPIO(U, 4)>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-pinmux.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-pinmux.dtsi deleted file mode 100644 index 21a035086ec2..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-pinmux.dtsi +++ /dev/null @@ -1,1393 +0,0 @@ -#include <dt-bindings/pinctrl/pinctrl-tegra.h> - -/ { - pinmux: pinmux { - pinctrl-names = "default", "drive", "unused"; - pinctrl-0 = <&pinmux_default>; - pinctrl-1 = <&drive_default>; - pinctrl-2 = <&pinmux_unused_lowpower>; - - pinmux_default: default { - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "rsvd1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_dqs_p_pj3 { - nvidia,pins = "gmi_dqs_p_pj3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "safe"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "safe"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "safe"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - }; - - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - - drive_default: drive_pins { - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; - }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; - - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,drive-type = <1>; - }; - }; - - pinmux_unused_lowpower: unused_pins { - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-powermon.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-powermon.dtsi deleted file mode 100644 index 3a2855e7f012..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-pismo-powermon.dtsi +++ /dev/null @@ -1,211 +0,0 @@ -/ { - i2c@7000c400 { - ina219@40{ - compatible = "ina219x"; - reg = <0x40>; - ti,rail-name = "VDD_12V_DCIN_RS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xAEC0>; - ti,power-lsb = <1831>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@41{ - compatible = "ina219x"; - reg = <0x41>; - ti,rail-name = "VDD_AC_BAT_VIN1"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@42{ - compatible = "ina219x"; - reg = <0x42>; - ti,rail-name = "VDD_5V0_SYS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <2500>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <5>; - ti,precision-multiplier = <1000>; - }; - - ina219@43{ - compatible = "ina219x"; - reg = <0x43>; - ti,rail-name = "VDD_3V3_SYS"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <2500>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <5>; - ti,precision-multiplier = <1000>; - }; - - ina219@44{ - compatible = "ina219x"; - reg = <0x44>; - ti,rail-name = "VDD_3V3_SYS_VIN4_5_7"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@45{ - compatible = "ina219x"; - reg = <0x45>; - ti,rail-name = "AVDD_USB_HDMI"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@46{ - compatible = "ina219x"; - reg = <0x46>; - ti,rail-name = "VDD_AC_BAT_D1"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0x7CD2>; - ti,power-lsb = <2563>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@47{ - compatible = "ina219x"; - reg = <0x47>; - ti,rail-name = "VDD_AO_SMPS12_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xAEC0>; - ti,power-lsb = <1831>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@48{ - compatible = "ina219x"; - reg = <0x48>; - ti,rail-name = "VDD_3V3_SYS_SMPS45_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@49{ - compatible = "ina219x"; - reg = <0x49>; - ti,rail-name = "VDD_AO_SMPS2_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4a{ - compatible = "ina219x"; - reg = <0x4a>; - ti,rail-name = "VDDIO_HV_AP"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4b{ - compatible = "ina219x"; - reg = <0x4b>; - ti,rail-name = "VDD_1V8_LDO3_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4c{ - compatible = "ina219x"; - reg = <0x4c>; - ti,rail-name = "VDD_3V3_SYS_LDO4_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4d{ - compatible = "ina219x"; - reg = <0x4d>; - ti,rail-name = "VDD_AO_LDO8_IN"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4e{ - compatible = "ina219x"; - reg = <0x4e>; - ti,rail-name = "VDD_1V8_AP"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - - ina219@4f{ - compatible = "ina219x"; - reg = <0x4f>; - ti,rail-name = "VDD_1V8_DSM"; - ti,continuous-config = <0x3FFF>; - ti,trigger-config = <0x01DB>; - ti,calibration-data = <0xFFFE>; - ti,power-lsb = <1250>; - ti,divisor = <20>; - ti,shunt-resistor-mohm = <10>; - ti,precision-multiplier = <1000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-e1580-gpio-default.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-e1580-gpio-default.dtsi deleted file mode 100644 index c4913bbcf3b9..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-e1580-gpio-default.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -#include <dt-bindings/gpio/tegra-gpio.h> - -/ { - gpio: gpio { - gpio-init-names = "default"; - gpio-init-0 = <&gpio_default>; - - gpio_default: default { - gpio-input = < TEGRA_GPIO(X, 5) - TEGRA_GPIO(X, 6) - TEGRA_GPIO(W, 2) - TEGRA_GPIO(W, 3) - TEGRA_GPIO(X, 3) - TEGRA_GPIO(V, 0) - TEGRA_GPIO(V, 1) - TEGRA_GPIO(O, 4) - TEGRA_GPIO(O, 5) - TEGRA_GPIO(O, 7) - TEGRA_GPIO(O, 0) - TEGRA_GPIO(CC, 1) - TEGRA_GPIO(CC, 2) - TEGRA_GPIO(G, 2) - TEGRA_GPIO(G, 3) - TEGRA_GPIO(K, 0) - TEGRA_GPIO(J, 0) - TEGRA_GPIO(K, 2) - TEGRA_GPIO(I, 6) - TEGRA_GPIO(I, 5) - TEGRA_GPIO(C, 7) - TEGRA_GPIO(Q, 4) - TEGRA_GPIO(Q, 5) - TEGRA_GPIO(R, 4) - TEGRA_GPIO(R, 7) - TEGRA_GPIO(S, 0) - TEGRA_GPIO(U, 5) - TEGRA_GPIO(U, 6) - TEGRA_GPIO(N, 7)>; - - gpio-output-low = < TEGRA_GPIO(X, 4) - TEGRA_GPIO(X, 7) - TEGRA_GPIO(O, 1) - TEGRA_GPIO(O, 2) - TEGRA_GPIO(O, 3) - TEGRA_GPIO(O, 6) - TEGRA_GPIO(BB, 3) - TEGRA_GPIO(BB, 5) - TEGRA_GPIO(BB, 6) - TEGRA_GPIO(BB, 7) - TEGRA_GPIO(G, 0) - TEGRA_GPIO(G, 1) - TEGRA_GPIO(H, 2) - TEGRA_GPIO(H, 4) - TEGRA_GPIO(H, 5) - TEGRA_GPIO(G, 4) - TEGRA_GPIO(K, 1) - TEGRA_GPIO(K, 3) - TEGRA_GPIO(K, 4) - TEGRA_GPIO(J, 3) - TEGRA_GPIO(I, 4) - TEGRA_GPIO(CC, 5) - TEGRA_GPIO(V, 3) - TEGRA_GPIO(Q, 3) - TEGRA_GPIO(Q, 6) - TEGRA_GPIO(Q, 7) - TEGRA_GPIO(R, 3) - TEGRA_GPIO(R, 5) - TEGRA_GPIO(EE, 1) - TEGRA_GPIO(U, 4) - TEGRA_GPIO(K, 5)>; - gpio-output-high = < TEGRA_GPIO(N, 4)>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-e1580-pinmux.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-e1580-pinmux.dtsi deleted file mode 100644 index 815de98a20da..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-e1580-pinmux.dtsi +++ /dev/null @@ -1,1649 +0,0 @@ -#include <dt-bindings/pinctrl/pinctrl-tegra.h> - -/ { - pinmux: pinmux { - pinctrl-names = "default", "drive", "unused", "suspend"; - pinctrl-0 = <&pinmux_default>; - pinctrl-1 = <&drive_default>; - pinctrl-2 = <&pinmux_unused_lowpower>; - pinctrl-3 = <&pinmux_suspend>; - - pinmux_default: common { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "pwm3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad15_ph7 { - nvidia,pins = "gmi_ad15_ph7"; - nvidia,function = "dtv"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "dtv"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - -pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - }; - - pinmux_unused_lowpower: unused_lowpower { - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - - drive_default: drive { - drive_dap2 { - nvidia,pins = "drive_dap2"; - nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; - nvidia,schmitt = <TEGRA_PIN_ENABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; - }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; - - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,drive-type = <1>; - }; - }; - - pinmux_suspend: suspend { - gmi_ad15_ph7 { - nvidia,pins = "gmi_ad15_ph7"; - nvidia,function = "dtv"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "dtv"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-powermon.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-powermon.dtsi deleted file mode 100644 index b158fe5c7505..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-pluto-powermon.dtsi +++ /dev/null @@ -1,228 +0,0 @@ -/ { - i2c@7000c400 { - - pca9546@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - i2c-mux,deselect-on-exit; - }; - - i2c@1 { - reg = <1>; - i2c-mux,deselect-on-exit; - #address-cells = <1>; - #size-cells = <0>; - - ina230@40{ - compatible = "ina230x"; - reg = <0x40>; - ti,rail-name = "VDD_SYS_SUM"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x369C>; - ti,power-lsb = <3051>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@41{ - compatible = "ina230x"; - reg = <0x41>; - ti,rail-name = "VDD_SYS_SMPS123"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x2BB0>; - ti,power-lsb = <2288>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@42{ - compatible = "ina230x"; - reg = <0x42>; - ti,rail-name = "VDD_SYS_SMPS45"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x4188>; - ti,power-lsb = <1525>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@43{ - compatible = "ina230x"; - reg = <0x43>; - ti,rail-name = "VDD_SYS_SMPS6"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x2BB0>; - ti,power-lsb = <381>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@44{ - compatible = "ina230x"; - reg = <0x44>; - ti,rail-name = "VDD_SYS_SMPS7"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,resistor = <50>; - ti,calibration-data = <0x2BB0>; - ti,power-lsb = <228>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@45{ - compatible = "ina230x"; - reg = <0x45>; - ti,rail-name = "VDD_SYS_SMPS8"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x2BB0>; - ti,power-lsb = <228>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@46{ - compatible = "ina230x"; - reg = <0x46>; - ti,rail-name = "VDD_SYS_BL"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x4188>; - ti,power-lsb = <152>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@47{ - compatible = "ina230x"; - reg = <0x47>; - ti,rail-name = "VDD_SYS_LDO8"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x2D82>; - ti,power-lsb = <54>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@48{ - compatible = "ina230x"; - reg = <0x48>; - ti,rail-name = "VDD_MMC_LDO9"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x51EA>; - ti,power-lsb = <30>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@49{ - compatible = "ina230x"; - reg = <0x49>; - ti,rail-name = "VDD_5V0_LDOUSB"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x2F7D>; - ti,power-lsb = <52>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@4b{ - compatible = "ina230x"; - reg = <0x4b>; - ti,rail-name = "VDD_1V8_AP"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x4FEB>; - ti,power-lsb = <125>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@4c{ - compatible = "ina230x"; - reg = <0x4c>; - ti,rail-name = "VDD_MMC_LCD"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x346D>; - ti,power-lsb = <47>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@4e{ - compatible = "ina230x"; - reg = <0x4e>; - ti,rail-name = "VDDIO_HSIC_BB"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x6D39>; - ti,power-lsb = <9>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@4f{ - compatible = "ina230x"; - reg = <0x4f>; - ti,rail-name = "AVDD_PLL_BB"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x7FFF>; - ti,power-lsb = <7>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - }; - - i2c@2 { - reg = <2>; - i2c-mux,deselect-on-exit; - #address-cells = <1>; - #size-cells = <0>; - ina230@49{ - compatible = "ina230x"; - reg = <0x49>; - ti,rail-name = "AVDD_1V05_LDO1"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x7FFF>; - ti,power-lsb = <195>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - - ina230@4c{ - compatible = "ina230x"; - reg = <0x4c>; - ti,rail-name = "VDDIO_1V8_BB"; - ti,continuous-config = <0x0407>; - ti,trigger-config = <0x0403>; - ti,calibration-data = <0x7FFF>; - ti,power-lsb = <78>; - ti,divisor = <25>; - ti,precision-multiplier = <1000>; - }; - }; - - i2c@3 { - reg = <3>; - i2c-mux,deselect-on-exit; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-gpio-default.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-gpio-default.dtsi deleted file mode 100644 index a631cd97c8e2..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-gpio-default.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -#include <dt-bindings/gpio/tegra-gpio.h> - -/ { - gpio: gpio { - gpio-init-names = "default"; - gpio-init-0 = <&gpio_default>; - - gpio_default: default { - gpio-input = < TEGRA_GPIO(X, 5) - TEGRA_GPIO(X, 6) - TEGRA_GPIO(W, 2) - TEGRA_GPIO(W, 3) - TEGRA_GPIO(X, 3) - TEGRA_GPIO(X, 4) - TEGRA_GPIO(V, 0) - TEGRA_GPIO(V, 1) - TEGRA_GPIO(CC, 1) - TEGRA_GPIO(CC, 2) - TEGRA_GPIO(G, 2) - TEGRA_GPIO(G, 3) - TEGRA_GPIO(K, 3) - TEGRA_GPIO(K, 2) - TEGRA_GPIO(K, 5) - TEGRA_GPIO(I, 6) - TEGRA_GPIO(J, 3) - TEGRA_GPIO(I, 5) - TEGRA_GPIO(C, 7) - TEGRA_GPIO(R, 3) - TEGRA_GPIO(R, 4) - TEGRA_GPIO(Q, 5) - TEGRA_GPIO(R, 6) - TEGRA_GPIO(R, 7) - TEGRA_GPIO(U, 2) - TEGRA_GPIO(U, 5) - TEGRA_GPIO(U, 6) - TEGRA_GPIO(N, 7)>; - - gpio-output-low = < TEGRA_GPIO(P, 1) - TEGRA_GPIO(P, 2) - TEGRA_GPIO(P, 0) - TEGRA_GPIO(P, 3) - TEGRA_GPIO(BB, 3) - TEGRA_GPIO(BB, 5) - TEGRA_GPIO(BB, 6) - TEGRA_GPIO(BB, 7) - TEGRA_GPIO(G, 0) - TEGRA_GPIO(G, 1) - TEGRA_GPIO(H, 4) - TEGRA_GPIO(H, 5) - TEGRA_GPIO(H, 6) - TEGRA_GPIO(H, 7) - TEGRA_GPIO(G, 4) - TEGRA_GPIO(H, 0) - TEGRA_GPIO(K, 1) - TEGRA_GPIO(K, 3) - TEGRA_GPIO(K, 4) - TEGRA_GPIO(I, 7) - TEGRA_GPIO(CC, 5) - TEGRA_GPIO(V, 3) - TEGRA_GPIO(Q, 3) - TEGRA_GPIO(Q, 6) - TEGRA_GPIO(Q, 7) - TEGRA_GPIO(R, 5) - TEGRA_GPIO(EE, 1) - TEGRA_GPIO(U, 0) - TEGRA_GPIO(U, 4) - TEGRA_GPIO(U, 1)>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-pinmux.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-pinmux.dtsi deleted file mode 100644 index 6dc1295659a6..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-pinmux.dtsi +++ /dev/null @@ -1,1436 +0,0 @@ -#include <dt-bindings/pinctrl/pinctrl-tegra.h> - -/ { - pinmux: pinmux { - pinctrl-names = "default", "drive", "unused"; - pinctrl-0 = <&pinmux_default>; - pinctrl-1 = <&drive_default>; - pinctrl-2 = <&pinmux_unused_lowpower>; - - pinmux_default: default { - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad15_ph7 { - nvidia,pins = "gmi_ad15_ph7"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs4_n_pk2 { - nvidia,pins = "gmi_cs4_n_pk2"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_dqs_p_pj3 { - nvidia,pins = "gmi_dqs_p_pj3"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "pwm2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs6_n_pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "nand"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - }; - - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,lock = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "safe"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - }; - }; - - drive_default: drive_pins { - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; - }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - }; - - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; - nvidia,drive-type = <1>; - }; - }; - - pinmux_unused_lowpower: unused_pins { - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd3"; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - }; - }; - }; -}; - diff --git a/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-powermon.dtsi b/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-powermon.dtsi deleted file mode 100644 index c221b2daf61f..000000000000 --- a/arch/arm/boot/dts/tegra114-platforms/tegra114-roth-powermon.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/ { - i2c@7000c400 { - ina3221x@40 { - compatible = "ti,ina3221x"; - reg = <0x40>; - ti,trigger-config = <0x7003>; - ti,continuous-config = <0x7727>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - ti,rail-name = "VDD_SYS_DDR_IN"; - ti,shunt-resistor-mohm = <10>; - }; - - channel@1 { - reg = <0x1>; - ti,rail-name = "VDD_SYS_SOC_IN"; - ti,shunt-resistor-mohm = <10>; - }; - - channel@2 { - reg = <0x2>; - ti,rail-name = "VDD_SYS_CPU_IN"; - ti,shunt-resistor-mohm = <10>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-pluto-powerconfig.dts b/arch/arm/boot/dts/tegra114-pluto-powerconfig.dts deleted file mode 100644 index d26fc201ca65..000000000000 --- a/arch/arm/boot/dts/tegra114-pluto-powerconfig.dts +++ /dev/null @@ -1,54 +0,0 @@ -#include "tegra114-pluto.dts" - -/ { - i2c@7000c400 { - pca9546@71 { - pca9546_i2c1: i2c@1 { - ina230@40{ - ti,calibration-data = <0x0426>; - ti,power-lsb = <1205>; - }; - - ina230@41{ - ti,calibration-data = <0x2134>; - ti,power-lsb = <301>; - }; - - ina230@42{ - ti,calibration-data = <0x2134>; - ti,power-lsb = <301>; - }; - - ina230@43{ - ti,calibration-data = <0x3756>; - ti,power-lsb = <180>; - }; - - ina230@44{ - ti,calibration-data = <0x084D>; - ti,power-lsb = <120>; - }; - - ina230@45{ - ti,calibration-data = <0x14C0>; - ti,power-lsb = <240>; - }; - - ina230@47{ - ti,calibration-data = <0x18E7>; - ti,power-lsb = <40>; - }; - - ina230@48{ - ti,calibration-data = <0x0EAD>; - ti,power-lsb = <68>; - }; - - ina230@4c{ - ti,calibration-data = <0x1E95>; - ti,power-lsb = <81>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts index 76a2c76727fc..6bbc8efae9c0 100644 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ b/arch/arm/boot/dts/tegra114-pluto.dts @@ -1,207 +1,21 @@ -/* - * arch/arm/boot/dts/tegra114-pluto.dts - * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - /dts-v1/; /include/ "tegra114.dtsi" -/include/ "panel-l-720p-5.dts" -#include <tegra114-platforms/tegra114-pluto-e1580-gpio-default.dtsi> -#include <tegra114-platforms/tegra114-pluto-e1580-pinmux.dtsi> -#include <tegra114-platforms/tegra114-pluto-powermon.dtsi> / { - model = "NVIDIA Tegra114 pluto evaluation board"; + model = "NVIDIA Tegra114 Pluto evaluation board"; compatible = "nvidia,pluto", "nvidia,tegra114"; - host1x { - dsi { - nvidia,controller-vs = <1>; - status = "disabled"; - panel-l-720p-5 { - nvidia,dsi-panel-rst-gpio = <&gpio 61 0>; /* PH5 */ - nvidia,dsi-panel-bl-en-gpio = <&gpio 58 0>; /* PH2 */ - nvidia,dsi-panel-bl-pwm-gpio = <&gpio 57 0>; /* PH1 */ - }; - }; - - hdmi { - status = "okay"; - }; - }; - - keyboard: keyboard@7000e200 { - compatible = "nvidia,tegra114-kbc"; - reg = <0x7000e200 0x100>; - interrupts = <0 85 0x04>; - nvidia,ghost-filter; - nvidia,wakeup-source; - nvidia,debounce-delay-ms = <640>; - nvidia,kbc-row-pins = <0 1 2>; /* pin 0, 1, 2 as rows */ - nvidia,kbc-col-pins = <11 12 13>; /* pin 11, 12, 13 as columns */ - linux,keymap = <0x00000074 - 0x00010073 - 0x00020072 - 0x010000D9 - 0x010100D4 - 0x010200D2 - 0x02000066 - 0x0201009E - 0x0202008B>; - status = "disable"; - }; - - serial@70006000 { - compatible = "nvidia,tegra114-hsuart"; - status = "okay"; - }; - - serial@70006040 { - compatible = "nvidia,tegra114-hsuart"; - status = "okay"; - }; - - serial@70006200 { - compatible = "nvidia,tegra114-hsuart"; - status = "okay"; - }; - - i2c@7000c500 { - - imx091@10 { - compatible = "nvidia,imx091"; - reg = <0x10>; - nvidia,vcm_vdd; /* flag for vcm_vdd extra regulator */ - nvidia,i2c_vdd; /* flag for i2c_vdd extra regulator */ - - - nvidia,num = <0>; - nvidia,sync = <0>; - nvidia,dev_name = "camera"; - - /* edpc config */ - nvidia,imx091_estates = <876 656 220 0>; - nvidia,num_states = <4>; - nvidia,e0_index = <0>; - nvidia,priority = <1>; - - /* imx091 gpios */ - reset-gpios = <&gpio 219 0>; /* gpio PBB3 */ - power-gpios = <&gpio 221 0>; /* gpio PBB6 */ - gp1-gpios = <&gpio 225 0>; /* gpio PCC1 */ - - /* imx091 caps */ - nvidia,identifier = "IMX091"; - nvidia,sensor_nvc_interface = <3>; - nvidia,pixel_types = <0x100>; - nvidia,orientation = <0>; - nvidia,direction = <0>; - nvidia,initial_clock_rate_khz = <6000>; - nvidia,h_sync_edge = <0>; - nvidia,v_sync_edge = <0>; - nvidia,mclk_on_vgp0 = <0>; - nvidia,csi_port = <0>; - nvidia,data_lanes = <4>; - nvidia,virtual_channel_id = <0>; - nvidia,discontinuous_clk_mode = <1>; - nvidia,cil_threshold_settle = <0x0>; - nvidia,min_blank_time_width = <16>; - nvidia,min_blank_time_height = <16>; - nvidia,preferred_mode_index = <0>; - nvidia,external_clock_khz_0 = <24000>; - nvidia,clock_multiplier_0 = <850000>; - nvidia,external_clock_khz_1 = <0>; - nvidia,clock_multiplier_1 = <0>; - - /* flash caps */ - nvidia,sdo_trigger_enabled; - nvidia,adjustable_flash_timing; - - status = "okay"; - - }; - - imx132@36 { - compatible = "nvidia,imx132"; - cam2_gpios = <&gpio 222 0>; /* gpio PBB6 */ - reg = <0x36>; - nvidia,ext_reg; /* Extra power-regulators needed */ - status = "okay"; - }; - - ad5816@0E { - compatible = "nvidia,ad5816"; - reg = <0x0E>; - nvidia,cfg = <0>; - nvidia,num = <0>; - nvidia,sync = <0>; - nvidia,dev_name = "focuser"; - status = "okay"; - }; - }; - - i2c@7000d000 { - nvidia,bit-banging-xfer-after-shutdown; + memory { + reg = <0x80000000 0x40000000>; }; - spi@7000da00 { + serial@70006300 { status = "okay"; - spi-max-frequency = <25000000>; - nvidia,dma-request-selector = <&apbdma 0>; }; pmc { - status = "okay"; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <300>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <2000>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - sdhci@78000600 { - tap-delay = <5>; - trim-delay = <3>; - ddr-clk-limit = <41000000>; - base-clk = <104000000>; - mmc-ocr-mask = <0>; - bus-width = <8>; - built-in; - edp_support; - edp_states = <966 0>; - status = "disabled"; - }; - sdhci@78000400 { - cd-gpios = <&gpio 170 0>; /* gpio PV2 */ - tap-delay = <3>; - trim-delay = <3>; - ddr-clk-limit = <41000000>; - base-clk = <208000000>; - edp_support; - edp_states = <966 0>; - bus-width = <4>; - status = "disabled"; - }; - sdhci@78000000 { - status = "disabled"; - }; - - camera { - status = "okay"; + nvidia,invert-interrupt; }; clocks { @@ -216,15 +30,4 @@ clock-frequency = <32768>; }; }; - - xusb@70090000 { - nvidia,uses_external_pmic; - /* nvidia,gpio_controls_muxed_ss_lanes; */ - nvidia,gpio_ss1_sata = <0>; - nvidia,portmap = <0x101>; /* SSP0, USB2P0 */ - nvidia,ss_portmap = <0x0>; /* SSP0 on USB2P0 */ - nvidia,lane_owner = <0>; /* NULL */ - nvidia,ulpicap = <0>; /* No ulpi support. can we remove */ - status = "okay"; - }; }; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts deleted file mode 100644 index 3b7600a2a31c..000000000000 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * arch/arm/boot/dts/tegra114-roth.dts - * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/dts-v1/; - -/include/ "tegra114.dtsi" -#include <tegra114-platforms/tegra114-roth-gpio-default.dtsi> -#include <tegra114-platforms/tegra114-roth-pinmux.dtsi> -#include <tegra114-platforms/tegra114-roth-powermon.dtsi> - -/ { - model = "NVIDIA Tegra114 roth evaluation board"; - compatible = "nvidia,roth", "nvidia,tegra114"; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - host1x { - hdmi { - status = "okay"; - }; - }; - - i2c@7000c400 { - nvidia,clock-always-on; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - nvidia,dma-request-selector = <&apbdma 0>; - }; - - pmc { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <2000>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; -}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 07b36ed260cc..629415ffd8dc 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -5,131 +5,12 @@ interrupt-parent = <&gic>; aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - spi5 = &spi5; serial0 = &uarta; serial1 = &uartb; serial2 = &uartc; serial3 = &uartd; }; - host1x { - compatible = "nvidia,tegra114-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - nvidia,memory-clients = <6>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x01000000>, - <0x60001000 0x60001000 0x0000e200>; - - vi { - compatible = "nvidia,tegra114-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - nvidia,memory-clients = <18>; - }; - - epp { - compatible = "nvidia,tegra114-epp"; - reg = <0x540c0000 0x00040000>; - nvidia,memory-clients = <4>; - }; - - isp { - compatible = "nvidia,tegra114-isp"; - reg = <0x54100000 0x00040000>; - nvidia,memory-clients = <8>; - }; - - gr2d { - compatible = "nvidia,tegra114-gr2d"; - reg = <0x54140000 0x00040000>; - nvidia,memory-clients = <5>; - }; - - gr3d { - compatible = "nvidia,tegra114-gr3d"; - reg = <0x54180000 0x00040000>; - nvidia,memory-clients = <12>; - }; - - dc@54200000 { - compatible = "nvidia,tegra114-dc"; - reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - nvidia,memory-clients = <2>; - status = "disabled"; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra114-dc"; - reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - nvidia,memory-clients = <3>; - status = "disabled"; - - rgb { - status = "disabled"; - }; - }; - - hdmi { - compatible = "nvidia,tegra114-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - status = "disabled"; - }; - - tvo { - compatible = "nvidia,tegra114-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - status = "disabled"; - }; - - dsi { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54300000 0x00040000>, - <0x54400000 0x00040000>; - status = "disabled"; - }; - - msenc { - compatible = "nvidia,tegra114-msenc"; - reg = <0x544c0000 0x00040000>; - nvidia,memory-clients = <11>; - }; - - tsec { - compatible = "nvidia,tegra114-tsec"; - reg = <0x54500000 0x00040000>; - nvidia,memory-clients = <23>; - }; - - nvavp { - compatible = "nvidia,tegra114-nvavp"; - interrupts = <0 4 0x04>; /* mailbox AVP IRQ */ - reg = <0x60001000 0x0000e200>; - }; - }; - gic: interrupt-controller { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -141,29 +22,14 @@ interrupts = <1 9 0xf04>; }; - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra-gic"; - interrupt-controller; - reg = <0x60004000 0x40>, - <0x60004100 0x40>, - <0x60004200 0x40>, - <0x60004300 0x40>, - <0x60004400 0x40>; - }; - timer@60005000 { - compatible = "nvidia,tegra-nvtimer"; + compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; interrupts = <0 0 0x04 0 1 0x04 0 41 0x04 0 42 0x04 0 121 0x04 - 0 151 0x04 - 0 152 0x04 - 0 153 0x04 - 0 154 0x04 - 0 155 0x04 0 122 0x04>; clocks = <&tegra_car 5>; }; @@ -210,7 +76,6 @@ 0 142 0x04 0 143 0x04>; clocks = <&tegra_car 34>; - #dma-cells = <1>; }; ahb: ahb { @@ -235,13 +100,7 @@ interrupt-controller; }; - vde { - reg = <0x6001a000 0x3bff>; - compatible = "nvidia,tegra114-vde"; - nvidia,memory-clients = <17>; - }; - - pinmux { + pinmux: pinmux { compatible = "nvidia,tegra114-pinmux"; reg = <0x70000868 0x148 /* Pad control registers */ 0x70003000 0x40c>; /* Mux registers */ @@ -263,8 +122,6 @@ nvidia,dma-request-selector = <&apbdma 8>; status = "disabled"; clocks = <&tegra_car 6>; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; }; uartb: serial@70006040 { @@ -275,43 +132,37 @@ nvidia,dma-request-selector = <&apbdma 9>; status = "disabled"; clocks = <&tegra_car 192>; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; }; uartc: serial@70006200 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x40>; + reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; nvidia,dma-request-selector = <&apbdma 10>; status = "disabled"; clocks = <&tegra_car 55>; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; }; uartd: serial@70006300 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x40>; + reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; nvidia,dma-request-selector = <&apbdma 19>; status = "disabled"; clocks = <&tegra_car 65>; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; }; - pwm: pwm@7000a000 { - compatible = "nvidia,tegra114-pwm"; + pwm: pwm { + compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car 17>; - status = "okay"; + status = "disabled"; }; - i2c1: i2c@7000c000 { + i2c@7000c000 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c000 0x100>; interrupts = <0 38 0x04>; @@ -319,20 +170,10 @@ #size-cells = <0>; clocks = <&tegra_car 12>; clock-names = "div-clk"; - scl-gpio = <&gpio 20 0>; /* gpio PC4 */ - sda-gpio = <&gpio 21 0>; /* gpio PC5 */ - clock-frequency = <100000>; - status = "okay"; - }; - - pmc { - compatible = "nvidia,tegra114-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car 261>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; + status = "disabled"; }; - i2c2: i2c@7000c400 { + i2c@7000c400 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c400 0x100>; interrupts = <0 84 0x04>; @@ -340,13 +181,10 @@ #size-cells = <0>; clocks = <&tegra_car 54>; clock-names = "div-clk"; - scl-gpio = <&gpio 157 0>; /* gpio PT5 */ - sda-gpio = <&gpio 158 0>; /* gpio PT6 */ - clock-frequency = <100000>; - status = "okay"; + status = "disabled"; }; - i2c3: i2c@7000c500 { + i2c@7000c500 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c500 0x100>; interrupts = <0 92 0x04>; @@ -354,13 +192,10 @@ #size-cells = <0>; clocks = <&tegra_car 67>; clock-names = "div-clk"; - scl-gpio = <&gpio 217 0>; /* gpio PBB1 */ - sda-gpio = <&gpio 218 0>; /* gpio PBB2 */ - clock-frequency = <100000>; - status = "okay"; + status = "disabled"; }; - i2c4: i2c@7000c700 { + i2c@7000c700 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c700 0x100>; interrupts = <0 120 0x04>; @@ -368,13 +203,10 @@ #size-cells = <0>; clocks = <&tegra_car 103>; clock-names = "div-clk"; - scl-gpio = <&gpio 172 0>; /* gpio PV4 */ - sda-gpio = <&gpio 173 0>; /* gpio PV5 */ - clock-frequency = <100000>; - status = "okay"; + status = "disabled"; }; - i2c5: i2c@7000d000 { + i2c@7000d000 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000d000 0x100>; interrupts = <0 53 0x04>; @@ -382,14 +214,10 @@ #size-cells = <0>; clocks = <&tegra_car 47>; clock-names = "div-clk"; - nvidia,require-cldvfs-clock; - scl-gpio = <&gpio 206 0>; /* gpio PZ6 */ - sda-gpio = <&gpio 207 0>; /* gpio PZ7 */ - clock-frequency = <400000>; - status = "okay"; + status = "disabled"; }; - spi0: spi@7000d400 { + spi@7000d400 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; interrupts = <0 59 0x04>; @@ -398,12 +226,10 @@ #size-cells = <0>; clocks = <&tegra_car 41>; clock-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; status = "disabled"; }; - spi1: spi@7000d600 { + spi@7000d600 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d600 0x200>; interrupts = <0 82 0x04>; @@ -412,12 +238,10 @@ #size-cells = <0>; clocks = <&tegra_car 44>; clock-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; status = "disabled"; }; - spi2: spi@7000d800 { + spi@7000d800 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d800 0x200>; interrupts = <0 83 0x04>; @@ -426,12 +250,10 @@ #size-cells = <0>; clocks = <&tegra_car 46>; clock-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; status = "disabled"; }; - spi3: spi@7000da00 { + spi@7000da00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000da00 0x200>; interrupts = <0 93 0x04>; @@ -440,12 +262,10 @@ #size-cells = <0>; clocks = <&tegra_car 68>; clock-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; status = "disabled"; }; - spi4: spi@7000dc00 { + spi@7000dc00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000dc00 0x200>; interrupts = <0 94 0x04>; @@ -454,12 +274,10 @@ #size-cells = <0>; clocks = <&tegra_car 104>; clock-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; status = "disabled"; }; - spi5: spi@7000de00 { + spi@7000de00 { compatible = "nvidia,tegra114-spi"; reg = <0x7000de00 0x200>; interrupts = <0 79 0x04>; @@ -468,13 +286,11 @@ #size-cells = <0>; clocks = <&tegra_car 105>; clock-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; status = "disabled"; }; rtc { - compatible = "nvidia,tegra-rtc"; + compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; clocks = <&tegra_car 4>; @@ -495,11 +311,6 @@ clock-names = "pclk", "clk32k_in"; }; - efuse@7000f800 { - compatible = "nvidia,tegra114-efuse"; - reg = <0x7000f800 0x400>; - }; - iommu { compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; reg = <0x7000f010 0x02c @@ -511,87 +322,11 @@ nvidia,ahb = <&ahb>; }; - ahub { - compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 - 0x70080200 0x100>; - interrupts = <0 103 0x04>; - nvidia,dma-request-selector = <&apbdma 1>; - status = "disabled"; - - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - status = "disabled"; - }; - - tegra_dam0: dam@70080800 { - compatible = "nvidia,tegra30-dam"; - reg = <0x70080800 0x100>; - nvidia,ahub-dam-id = <0>; - status = "disabled"; - }; - - tegra_dam1: dam@70080900 { - compatible = "nvidia,tegra30-dam"; - reg = <0x70080900 0x100>; - nvidia,ahub-dam-id = <1>; - status = "disabled"; - }; - - tegra_dam2: dam@70080A00 { - compatible = "nvidia,tegra30-dam"; - reg = <0x70080A00 0x100>; - nvidia,ahub-dam-id = <2>; - status = "disabled"; - }; - - tegra_spdif: spdif@70080B00 { - compatible = "nvidia,tegra30-spdif"; - reg = <0x70080B00 0x100>; - status = "disabled"; - }; - }; - sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = <0 14 0x04>; clocks = <&tegra_car 14>; - nvidia,memory-clients = <14>; status = "disable"; }; @@ -600,7 +335,6 @@ reg = <0x78000200 0x200>; interrupts = <0 15 0x04>; clocks = <&tegra_car 9>; - nvidia,memory-clients = <14>; status = "disable"; }; @@ -609,7 +343,6 @@ reg = <0x78000400 0x200>; interrupts = <0 19 0x04>; clocks = <&tegra_car 69>; - nvidia,memory-clients = <14>; status = "disable"; }; @@ -618,7 +351,6 @@ reg = <0x78000600 0x200>; interrupts = <0 31 0x04>; clocks = <&tegra_car 15>; - nvidia,memory-clients = <14>; status = "disable"; }; @@ -654,45 +386,8 @@ timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>, - <1 14 0xf08>; - clock-frequency = <12000000>; - }; - - camera { - compatible = "nvidia,tegra114-camera", "nvidia,tegra20-camera"; - reg = <0x0 0x0>; - status = "disable"; - }; - - mipical { - compatible = "nvidia,tegra114-mipical"; - reg = <0x700e3000 0x00000100>; - }; - - xusb@70090000 { - compatible = "nvidia,tegra114-xhci"; - reg = <0x70090000 0x8000 - 0x70098000 0x1000 - 0x70099000 0x1000 - 0x7009F000 0x1000>; - interrupts = <0 39 0x04 - 0 40 0x04 - 0 49 0x04 - 0 97 0x04 - 0 21 0x04>; - status = "disable"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; }; }; diff --git a/arch/arm/configs/tegra11_android_defconfig b/arch/arm/configs/tegra11_android_defconfig deleted file mode 100644 index 323ec876aa8b..000000000000 --- a/arch/arm/configs/tegra11_android_defconfig +++ /dev/null @@ -1,581 +0,0 @@ -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_ELF_CORE is not set -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_TEGRA=y -CONFIG_GPIO_PCA953X=y -CONFIG_ARCH_TEGRA_11x_SOC=y -CONFIG_MACH_DALMORE=y -CONFIG_MACH_MACALLAN=y -CONFIG_MACH_TEGRA_PLUTO=y -CONFIG_MACH_ROTH=y -CONFIG_TEGRA_EMC_SCALING_ENABLE=y -CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y -CONFIG_TEGRA_EDP_LIMITS=y -CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ=1400 -CONFIG_TEGRA_DYNAMIC_PWRDET=y -CONFIG_TEGRA_WAKEUP_MONITOR=y -CONFIG_TEGRA_INTERNAL_USB_CABLE_WAKE_SUPPORT=y -CONFIG_TEGRA_BB_XMM_POWER=y -CONFIG_TEGRA_BB_XMM_POWER2=m -CONFIG_TEGRA_PREPOWER_WIFI=y -CONFIG_TEGRA_SKIN_THROTTLE=y -CONFIG_TEGRA_LP1_LOW_COREVOLTAGE=y -CONFIG_TEGRA_PLLM_SCALED=y -CONFIG_TEGRA_MC_DOMAINS=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_SMP=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_HIGHMEM=y -CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_INTERACTIVE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPUQUIET_FRAMEWORK=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_RUNTIME=y -CONFIG_SUSPEND_TIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_INET_ESP=y -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -CONFIG_IPV6=y -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_TUNNEL=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_LOG=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_SIP=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NETFILTER_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_TARGET_REJECT_SKERR=y -CONFIG_NF_NAT_IPV4=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_TARGET_REJECT_SKERR=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_MHI=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_U32=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_BT=y -CONFIG_BT_HIDP=y -CONFIG_CFG80211=m -CONFIG_NL80211_TESTMODE=y -CONFIG_MAC80211=m -CONFIG_RFKILL=y -CONFIG_RFKILL_GPIO=y -CONFIG_CAIF=y -CONFIG_NFC=y -CONFIG_BCM2079X_NFC=y -CONFIG_DEBUG_DEVRES=y -CONFIG_CMA=y -CONFIG_PLATFORM_ENABLE_IOMMU=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_AD525X_DPOT=y -CONFIG_AD525X_DPOT_I2C=y -CONFIG_APDS9802ALS=y -CONFIG_SENSORS_NCT1008=y -CONFIG_UID_STAT=y -CONFIG_TEGRA_CRYPTO_DEV=y -CONFIG_MAX1749_VIBRATOR=y -CONFIG_THERM_EST=y -CONFIG_FAN_THERM_EST=y -CONFIG_BLUEDROID_PM=y -CONFIG_EEPROM_AT24=y -CONFIG_TI_ST=y -CONFIG_ST_GPS=m -CONFIG_ST_HCI=y -CONFIG_ST_HOST_WAKE=y -CONFIG_TEGRA_BB_SUPPORT=y -CONFIG_TEGRA_USB_MODEM_POWER=y -CONFIG_TEGRA_BB_POWER=y -CONFIG_TEGRA_BB_OEM1=y -CONFIG_TEGRA_CEC_SUPPORT=y -CONFIG_ISSP=y -CONFIG_TEGRA_PROFILER=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_UEVENT=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_R8169=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_SMSC95XX=y -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_BELKIN is not set -# CONFIG_USB_ARMLINUX is not set -# CONFIG_USB_NET_ZAURUS is not set -CONFIG_USB_NET_RAW_IP=m -CONFIG_WIFI_CONTROL_FUNC=y -CONFIG_BCMDHD=m -CONFIG_BCM43241=y -CONFIG_BCM43341=y -CONFIG_BCMDHD_FW_PATH="/data/misc/wifi/firmware/fw_bcmdhd.bin" -CONFIG_BCMDHD_NVRAM_PATH="/data/misc/wifi/firmware/nvram.txt" -CONFIG_BCMDHD_HW_OOB=y -CONFIG_BCMDHD_INSMOD_NO_FW_LOAD=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -CONFIG_INPUT_CFBOOST=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_TEGRA=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_TOUCHSCREEN_RM31080A=y -CONFIG_TOUCHSCREEN_SYN_RMI4_SPI=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_KEYCHORD=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -CONFIG_INV_AK8975=m -CONFIG_INV_MPU=m -CONFIG_INV_BMP180=m -CONFIG_SERIO_LIBPS2=y -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_TEGRA=y -CONFIG_SPI=y -CONFIG_SPI_TEGRA114=y -CONFIG_PINMUX=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MAX77660=y -CONFIG_PINCTRL_PALMAS=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_MAX77663=y -CONFIG_GPIO_RC5T583=y -CONFIG_GPIO_PALMAS=y -CONFIG_GPIO_MAX77660=y -CONFIG_POWER_SUPPLY_EXTCON=y -CONFIG_CHARGER_BQ2419X=y -CONFIG_CHARGER_MAX77665=y -CONFIG_BATTERY_SBS=y -CONFIG_BATTERY_BQ27x00=y -CONFIG_CHARGER_TPS8003X=y -CONFIG_BATTERY_GAUGE_TPS8003X=y -CONFIG_CHARGER_TPS65090=y -CONFIG_CHARGER_SMB349=y -CONFIG_BATTERY_MAX17042=y -CONFIG_BATTERY_MAX17048=y -CONFIG_CHARGER_GPIO=y -CONFIG_CHARGER_EXTCON_MAX77660=y -CONFIG_POWER_RESET=y -CONFIG_POWER_OFF_PALMAS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_GOV_PID=y -CONFIG_GENERIC_ADC_THERMAL=y -CONFIG_PWM_FAN=y -CONFIG_PALMAS_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_PALMAS_WATCHDOG=y -CONFIG_MAX77660_SYSTEM_WATCHDOG=y -CONFIG_GPADC_TPS80031=y -CONFIG_CHARGER_BQ2419X=y -CONFIG_AIC3XXX_CORE=y -CONFIG_MFD_RC5T583=y -CONFIG_MFD_MAX8831=y -CONFIG_MFD_PALMAS=y -CONFIG_MFD_AS3722=y -CONFIG_MFD_MAX77663=y -CONFIG_MFD_TPS65090=y -CONFIG_MFD_TPS6586X=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_TPS80031=y -CONFIG_MFD_RICOH583=y -CONFIG_MFD_MAX77660=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_VIRTUAL_CONSUMER=y -CONFIG_REGULATOR_USERSPACE_CONSUMER=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_AS3722=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MAX77663=y -CONFIG_REGULATOR_RC5T583=y -CONFIG_REGULATOR_PALMAS=y -CONFIG_REGULATOR_TPS51632=y -CONFIG_REGULATOR_TPS62360=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_REGULATOR_TPS6586X=y -CONFIG_REGULATOR_TPS65910=y -CONFIG_REGULATOR_TPS80031=y -CONFIG_REGULATOR_TPS6238X0=y -CONFIG_REGULATOR_RICOH583=y -CONFIG_REGULATOR_MAX77660=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_TEGRA_MEDIASERVER is not set -CONFIG_TEGRA_NVAVP=y -CONFIG_TEGRA_NVAVP_AUDIO=y -CONFIG_VIDEO_CAMERA=y -CONFIG_VIDEO_OV5650=y -CONFIG_VIDEO_IMX091=y -CONFIG_VIDEO_IMX135=y -CONFIG_VIDEO_AR0261=y -CONFIG_VIDEO_IMX132=y -CONFIG_VIDEO_OV9772=y -CONFIG_TORCH_SSL3250A=y -CONFIG_MAX77665_FLASH=y -CONFIG_TORCH_MAX77387=y -CONFIG_TORCH_AS364X=y -CONFIG_VIDEO_AD5816=y -CONFIG_VIDEO_DW9718=y -CONFIG_VIDEO_AR0833=y -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -CONFIG_TEGRA_GRHOST=y -CONFIG_TEGRA_GRHOST_VI=y -CONFIG_TEGRA_DC=y -CONFIG_TEGRA_DSI=y -CONFIG_TEGRA_DSI2EDP_SN65DSI86=y -CONFIG_TEGRA_NVHDCP=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_PWM=y -CONFIG_BACKLIGHT_TEGRA_PWM=y -CONFIG_BACKLIGHT_MAX8831=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_PCI is not set -CONFIG_SND_HDA_INTEL=y -CONFIG_SND_HDA_PLATFORM_DRIVER=y -CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA=y -CONFIG_SND_HDA_POWER_SAVE_DEFAULT=10 -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_TEGRA=y -CONFIG_SND_SOC_TEGRA_RT5639=y -CONFIG_SND_SOC_TEGRA_RT5640=y -CONFIG_UHID=y -CONFIG_HID_A4TECH=y -CONFIG_HID_ACRUX=y -CONFIG_HID_ACRUX_FF=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_PRODIKEYS=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_DRAGONRISE=y -CONFIG_DRAGONRISE_FF=y -CONFIG_HID_EMS_FF=y -CONFIG_HID_ELECOM=y -CONFIG_HID_EZKEY=y -CONFIG_HID_HOLTEK=y -CONFIG_HOLTEK_FF=y -CONFIG_HID_KEYTOUCH=y -CONFIG_HID_KYE=y -CONFIG_HID_UCLOGIC=y -CONFIG_HID_WALTOP=y -CONFIG_HID_GYRATION=y -CONFIG_HID_TWINHAN=y -CONFIG_HID_KENSINGTON=y -CONFIG_HID_LCPOWER=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_LOGITECH_DJ=y -CONFIG_LOGITECH_FF=y -CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_LOGIG940_FF=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_MULTITOUCH=y -CONFIG_HID_NTRIG=y -CONFIG_HID_ORTEK=y -CONFIG_HID_PANTHERLORD=y -CONFIG_PANTHERLORD_FF=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_PICOLCD=y -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PRIMAX=y -CONFIG_HID_ROCCAT=y -CONFIG_HID_SAITEK=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SPEEDLINK=y -CONFIG_HID_SUNPLUS=y -CONFIG_HID_GREENASIA=y -CONFIG_GREENASIA_FF=y -CONFIG_HID_SMARTJOYPLUS=y -CONFIG_SMARTJOYPLUS_FF=y -CONFIG_HID_TIVO=y -CONFIG_HID_TOPSEED=y -CONFIG_HID_THRUSTMASTER=y -CONFIG_THRUSTMASTER_FF=y -CONFIG_HID_WACOM=y -CONFIG_HID_WIIMOTE=y -CONFIG_HID_ZEROPLUS=y -CONFIG_ZEROPLUS_FF=y -CONFIG_HID_ZYDACRON=y -CONFIG_I2C_HID=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_XHCI_HCD=y -CONFIG_TEGRA_XUSB_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_WDM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_PL2303=y -CONFIG_USB_SERIAL_OPTION=y -CONFIG_USB_SERIAL_BASEBAND=m -CONFIG_USB_RENESAS_MODEM=y -CONFIG_USB_OTG_WAKELOCK=y -CONFIG_USB_TEGRA_OTG=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_TEGRA=y -CONFIG_USB_G_ANDROID=y -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_MAX8831=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_SWITCH=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AS3722=y -CONFIG_RTC_DRV_MAX77663=y -CONFIG_RTC_DRV_TPS6586X=y -CONFIG_RTC_DRV_TPS80031=y -CONFIG_RTC_DRV_RC5T583=y -CONFIG_RTC_DRV_PALMAS=y -CONFIG_RTC_DRV_MAX77660=y -CONFIG_DMADEVICES=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_STAGING=y -CONFIG_MAX77660_ADC=y -CONFIG_PALMAS_GPADC=y -CONFIG_SENSORS_CM3218=y -CONFIG_SENSORS_ISL29028=y -CONFIG_SENSORS_MAX44005=y -CONFIG_SENSORS_CM3217=y -CONFIG_INA219=y -CONFIG_INA230=y -CONFIG_INA3221=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ASHMEM=y -CONFIG_ANDROID_LOGGER=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y -CONFIG_ANDROID_INTF_ALARM_DEV=y -CONFIG_PASR=y -CONFIG_CLK_PALMAS=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_PM_DEVFREQ=y -CONFIG_EXTCON=y -CONFIG_EXTCON_MAX77665=y -CONFIG_EXTCON_PALMAS=y -CONFIG_IIO=y -CONFIG_PWM=y -CONFIG_PWM_TEGRA=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -# CONFIG_DNOTIFY is not set -CONFIG_FUSE_FS=y -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_LOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_VM=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAILSLAB=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_FUNCTION_TRACER=y -# CONFIG_FUNCTION_GRAPH_TRACER is not set -CONFIG_DYNAMIC_DEBUG=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_DEV_TEGRA_SE=y -CONFIG_ANDROID_PARANOID_NETWORK=y diff --git a/arch/arm/configs/tegra11_defconfig b/arch/arm/configs/tegra11_defconfig deleted file mode 100644 index 02f1e97d6431..000000000000 --- a/arch/arm/configs/tegra11_defconfig +++ /dev/null @@ -1,565 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_TEGRA=y -CONFIG_GPIO_PCA953X=y -CONFIG_ARCH_TEGRA_11x_SOC=y -CONFIG_MACH_DALMORE=y -CONFIG_MACH_PISMO=y -CONFIG_MACH_TEGRA_PLUTO=y -CONFIG_TEGRA_EMC_SCALING_ENABLE=y -CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y -CONFIG_TEGRA_EDP_LIMITS=y -CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ=1400 -CONFIG_TEGRA_DYNAMIC_PWRDET=y -CONFIG_TEGRA_BB_XMM_POWER=y -CONFIG_TEGRA_BB_XMM_POWER2=m -CONFIG_TEGRA_PREPOWER_WIFI=y -CONFIG_TEGRA_LP1_LOW_COREVOLTAGE=y -CONFIG_TEGRA_PLLM_SCALED=y -CONFIG_TEGRA_MC_DOMAINS=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_SMP=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_HIGHMEM=y -CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_INTERACTIVE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPUQUIET_FRAMEWORK=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_TEGRA_INTERNAL_USB_CABLE_WAKE_SUPPORT=y -CONFIG_PM_RUNTIME=y -CONFIG_SUSPEND_TIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_CUBIC=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_IPV6=y -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_TUNNEL=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_LOG=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_SIP=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NETFILTER_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_TARGET_REJECT_SKERR=y -CONFIG_NF_NAT_IPV4=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_TARGET_REJECT_SKERR=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_U32=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_BT=y -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_HIDP=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_LL=y -CONFIG_CFG80211=m -CONFIG_NL80211_TESTMODE=y -CONFIG_MAC80211=m -CONFIG_RFKILL=y -CONFIG_RFKILL_GPIO=y -CONFIG_CAIF=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_CMA=y -CONFIG_PLATFORM_ENABLE_IOMMU=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_SENSORS_NCT1008=y -CONFIG_TEGRA_CRYPTO_DEV=y -CONFIG_BLUEDROID_PM=m -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_UEVENT=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_R8169=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_CATC=y -CONFIG_USB_KAWETH=y -CONFIG_USB_PEGASUS=y -CONFIG_USB_RTL8150=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_DM9601=y -CONFIG_USB_NET_SMSC75XX=y -CONFIG_USB_NET_SMSC95XX=y -# CONFIG_USB_NET_NET1080 is not set -CONFIG_USB_NET_MCS7830=y -# CONFIG_USB_NET_ZAURUS is not set -CONFIG_USB_NET_RAW_IP=m -CONFIG_WIFI_CONTROL_FUNC=y -CONFIG_BCMDHD=m -CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcm43241/fw_bcmdhd.bin" -CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/nvram_43241.txt" -CONFIG_BCMDHD_HW_OOB=y -CONFIG_BCMDHD_INSMOD_NO_FW_LOAD=y -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_TEGRA=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_TOUCHSCREEN_SYN_RMI4_SPI=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_KEYCHORD=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -CONFIG_INV_AK8975=m -CONFIG_INV_MPU=m -CONFIG_SERIO_LIBPS2=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_TEGRA=y -CONFIG_SPI=y -CONFIG_SPI_TEGRA114=y -CONFIG_PINMUX=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MAX77660=y -CONFIG_PINCTRL_PALMAS=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_MAX77663=y -CONFIG_GPIO_RC5T583=y -CONFIG_GPIO_PALMAS=y -CONFIG_GPIO_MAX77660=y -CONFIG_POWER_SUPPLY_EXTCON=y -CONFIG_CHARGER_MAX77665=y -CONFIG_TEST_POWER=y -CONFIG_BATTERY_SBS=y -CONFIG_BATTERY_BQ27x00=y -CONFIG_CHARGER_TPS8003X=y -CONFIG_BATTERY_GAUGE_TPS8003X=y -CONFIG_CHARGER_TPS65090=y -CONFIG_CHARGER_SMB349=y -CONFIG_BATTERY_MAX17042=y -CONFIG_BATTERY_MAX17048=y -CONFIG_CHARGER_GPIO=y -CONFIG_CHARGER_EXTCON_MAX77660=y -CONFIG_POWER_RESET=y -CONFIG_POWER_OFF_PALMAS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_GOV_PID=y -CONFIG_GENERIC_ADC_THERMAL=y -CONFIG_PWM_FAN=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_PALMAS_WATCHDOG=y -CONFIG_MAX77660_SYSTEM_WATCHDOG=y -CONFIG_GPADC_TPS80031=y -CONFIG_AIC3XXX_CORE=y -CONFIG_MFD_RC5T583=y -CONFIG_MFD_MAX8831=y -CONFIG_MFD_PALMAS=y -CONFIG_MFD_MAX77663=y -CONFIG_MFD_TPS65090=y -CONFIG_MFD_TPS6586X=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_TPS80031=y -CONFIG_MFD_RICOH583=y -CONFIG_MFD_MAX77660=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_VIRTUAL_CONSUMER=y -CONFIG_REGULATOR_USERSPACE_CONSUMER=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MAX77663=y -CONFIG_REGULATOR_RC5T583=y -CONFIG_REGULATOR_PALMAS=y -CONFIG_REGULATOR_TPS51632=y -CONFIG_REGULATOR_TPS62360=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_REGULATOR_TPS6586X=y -CONFIG_REGULATOR_TPS65910=y -CONFIG_REGULATOR_TPS80031=y -CONFIG_REGULATOR_TPS6238X0=y -CONFIG_REGULATOR_RICOH583=y -CONFIG_REGULATOR_MAX77660=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_TEGRA_MEDIASERVER is not set -CONFIG_TEGRA_NVAVP=y -CONFIG_TEGRA_NVAVP_AUDIO=y -CONFIG_VIDEO_CAMERA=y -CONFIG_VIDEO_OV5650=y -CONFIG_VIDEO_IMX091=y -CONFIG_VIDEO_IMX135=y -CONFIG_VIDEO_IMX132=y -CONFIG_VIDEO_OV9772=y -CONFIG_TORCH_SSL3250A=y -CONFIG_MAX77665_FLASH=y -CONFIG_TORCH_MAX77387=y -CONFIG_TORCH_AS364X=y -CONFIG_VIDEO_AD5816=y -CONFIG_VIDEO_DW9718=y -CONFIG_VIDEO_AR0833=y -# CONFIG_VGA_ARB is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -CONFIG_TEGRA_GRHOST=y -# CONFIG_TEGRA_GRHOST_SYNC is not set -CONFIG_TEGRA_DC=y -CONFIG_TEGRA_DSI=y -CONFIG_TEGRA_DSI2EDP_SN65DSI86=y -CONFIG_TEGRA_NVHDCP=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_PWM=y -CONFIG_BACKLIGHT_TEGRA_PWM=y -CONFIG_BACKLIGHT_MAX8831=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC_TEGRA=y -CONFIG_SND_SOC_TEGRA_RT5639=y -CONFIG_SND_SOC_TEGRA_RT5640=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_UHID=y -CONFIG_HID_A4TECH=m -CONFIG_HID_ACRUX=m -CONFIG_HID_ACRUX_FF=y -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_PRODIKEYS=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DRAGONRISE=m -CONFIG_DRAGONRISE_FF=y -CONFIG_HID_EMS_FF=m -CONFIG_HID_ELECOM=m -CONFIG_HID_EZKEY=m -CONFIG_HID_HOLTEK=m -CONFIG_HOLTEK_FF=y -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_GYRATION=m -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LCPOWER=m -CONFIG_HID_LOGITECH=m -CONFIG_HID_LOGITECH_DJ=m -CONFIG_LOGITECH_FF=y -CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_LOGIG940_FF=y -CONFIG_HID_MAGICMOUSE=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NTRIG=m -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_PANTHERLORD_FF=y -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PRIMAX=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_GREENASIA=m -CONFIG_GREENASIA_FF=y -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_SMARTJOYPLUS_FF=y -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_THRUSTMASTER_FF=y -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -CONFIG_HID_ZEROPLUS=m -CONFIG_ZEROPLUS_FF=y -CONFIG_HID_ZYDACRON=m -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_XHCI_HCD=y -CONFIG_TEGRA_XUSB_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_WDM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_PL2303=y -CONFIG_USB_SERIAL_OPTION=y -CONFIG_USB_SERIAL_BASEBAND=m -CONFIG_USB_TEGRA_OTG=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_TEGRA=y -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_MMC_EMBEDDED_SDIO=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_MAX8831=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_SWITCH=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MAX77663=y -CONFIG_RTC_DRV_TPS6586X=y -CONFIG_RTC_DRV_TPS80031=y -CONFIG_RTC_DRV_RC5T583=y -CONFIG_RTC_DRV_PALMAS=y -CONFIG_RTC_DRV_MAX77660=y -CONFIG_DMADEVICES=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_STAGING=y -CONFIG_MAX77660_ADC=y -CONFIG_SENSORS_CM3218=y -CONFIG_SENSORS_ISL29028=y -CONFIG_SENSORS_MAX44005=y -CONFIG_SENSORS_CM3217=y -CONFIG_INA219=y -CONFIG_INA230=y -CONFIG_INA3221=y -CONFIG_CLK_PALMAS=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_PM_DEVFREQ=y -CONFIG_EXTCON=y -CONFIG_EXTCON_PALMAS=y -CONFIG_IIO=y -CONFIG_PWM=y -CONFIG_PWM_TEGRA=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -# CONFIG_DNOTIFY is not set -CONFIG_FUSE_FS=y -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_CIFS=m -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=m -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_LOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_VM=y -CONFIG_DEBUG_SG=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAILSLAB=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_FUNCTION_TRACER=y -# CONFIG_FUNCTION_GRAPH_TRACER is not set -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_TWOFISH=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_DEV_TEGRA_SE=y diff --git a/arch/arm/configs/tegra_dalmore_mods_defconfig b/arch/arm/configs/tegra_dalmore_mods_defconfig deleted file mode 100644 index e3428b924502..000000000000 --- a/arch/arm/configs/tegra_dalmore_mods_defconfig +++ /dev/null @@ -1,249 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_RESOURCE_COUNTERS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_ELF_CORE is not set -CONFIG_EMBEDDED=y -CONFIG_SLAB=y -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_TEGRA=y -CONFIG_GPIO_PCA953X=y -CONFIG_ARCH_TEGRA_11x_SOC=y -CONFIG_MACH_DALMORE=y -CONFIG_MACH_TEGRA_PLUTO=y -CONFIG_TEGRA_PWM=y -CONFIG_TEGRA_EMC_SCALING_ENABLE=y -# CONFIG_TEGRA_CPU_DVFS is not set -CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y -CONFIG_USB_HOTPLUG=y -CONFIG_TEGRA_DYNAMIC_PWRDET=y -CONFIG_TEGRA_PLLM_RESTRICTED=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIEASPM_POWERSAVE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_SMP=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_HIGHMEM=y -CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_INET_ESP=y -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_R8169=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_TEGRA=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -CONFIG_INV_AK8975=m -CONFIG_INV_MPU=m -CONFIG_SERIO_LIBPS2=y -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_TEGRA=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_MAX77663=y -CONFIG_GPIO_RC5T583=y -CONFIG_GPIO_PALMAS=y -CONFIG_POWER_SUPPLY=y -CONFIG_BATTERY_SBS=y -CONFIG_BATTERY_BQ27x00=y -CONFIG_CHARGER_TPS8003X=y -CONFIG_BATTERY_GAUGE_TPS8003X=y -CONFIG_CHARGER_SMB349=y -CONFIG_BATTERY_MAX17048=y -CONFIG_CHARGER_GPIO=y -CONFIG_SENSORS_CM3217=y -CONFIG_INA219=y -CONFIG_INA230=y -CONFIG_INA3221=y -CONFIG_THERMAL=y -CONFIG_MFD_TPS6586X=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_MAX8831=y -CONFIG_MFD_MAX77663=y -CONFIG_MFD_TPS65090=y -CONFIG_MFD_TPS6591X=y -CONFIG_MFD_RC5T583=y -CONFIG_MFD_TPS80031=y -CONFIG_GPADC_TPS80031=y -CONFIG_MFD_RICOH583=y -CONFIG_MFD_PALMAS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_VIRTUAL_CONSUMER=y -CONFIG_REGULATOR_USERSPACE_CONSUMER=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_MAX77663=y -CONFIG_REGULATOR_RC5T583=y -CONFIG_REGULATOR_PALMAS=y -CONFIG_REGULATOR_TPS62360=y -CONFIG_REGULATOR_TPS6586X=y -CONFIG_REGULATOR_TPS65910=y -CONFIG_REGULATOR_TPS51632=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_REGULATOR_TPS6238X0=y -CONFIG_REGULATOR_TPS6591X=y -CONFIG_REGULATOR_TPS80031=y -CONFIG_REGULATOR_RICOH583=y -CONFIG_VIDEO_OUTPUT_CONTROL=y -# CONFIG_TEGRA_GRHOST_USE_NVMAP is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_MMC_EMBEDDED_SDIO=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MAX77663=y -CONFIG_RTC_DRV_TPS6586X=y -CONFIG_RTC_DRV_TPS6591x=y -CONFIG_RTC_DRV_TPS80031=y -CONFIG_RTC_DRV_PALMAS=y -CONFIG_RTC_DRV_RC5T583=y -CONFIG_CLK_PALMAS=y -CONFIG_TEGRA_IOMMU_SMMU=y -CONFIG_PM_DEVFREQ=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_REISERFS_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y -CONFIG_FSCACHE=y -CONFIG_CACHEFILES=y -CONFIG_REPORT_PRESENT_CPUS=y -CONFIG_TMPFS=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NFS_FSCACHE=y -CONFIG_CIFS=y -CONFIG_CIFS_FSCACHE=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_LOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK is not set -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_VM=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAILSLAB=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_FUNCTION_TRACER=y -# CONFIG_FUNCTION_GRAPH_TRACER is not set -CONFIG_TRACEDUMP=y -CONFIG_TRACEDUMP_PROCFS=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -CONFIG_LIBCRC32C=y -CONFIG_AVERAGE=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index ca7f58710b5b..54b67ba15732 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -89,7 +89,6 @@ CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y CONFIG_ICS932S401=y CONFIG_APDS9802ALS=y -CONFIG_SENSORS_NCT1008=y CONFIG_ISL29003=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 198cbfeb69f7..39e8dc14299b 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -18,16 +18,8 @@ comment "NVIDIA Tegra options" config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - depends on !ARCH_TEGRA_3x_SOC - depends on !ARCH_TEGRA_11x_SOC depends on !ARCH_TEGRA_12x_SOC - depends on !ARCH_TEGRA_14x_SOC select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP - select ARCH_SUPPORTS_MSI if PCI_TEGRA - select ARCH_TEGRA_HAS_ARM_SCU - select ARCH_TEGRA_HAS_PCIE - select ARM_CPU_SUSPEND if PM - select ARM_ERRATA_716044 select ARM_ERRATA_720789 select ARM_ERRATA_742230 if SMP select ARM_ERRATA_751472 @@ -35,21 +27,13 @@ config ARCH_TEGRA_2x_SOC select ARM_ERRATA_761320 if SMP select ARM_ERRATA_764369 if SMP select ARM_GIC - select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP select COMMON_CLK - select CPA select CPU_FREQ_TABLE if CPU_FREQ select CPU_V7 - select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select PCI_MSI if PCI_TEGRA select PINCTRL select PINCTRL_TEGRA20 - select POWER_RESET - select SYSTEM_PMIC + select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 - select PM_GENERIC_DOMAINS if PM - select SOC_BUS select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB_PHY select USB_ULPI_VIEWPORT if USB_PHY @@ -59,42 +43,20 @@ config ARCH_TEGRA_2x_SOC config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" - depends on !ARCH_TEGRA_11x_SOC depends on !ARCH_TEGRA_12x_SOC - depends on !ARCH_TEGRA_14x_SOC - select ARCH_SUPPORTS_MSI if PCI_TEGRA - select ARCH_TEGRA_HAS_ARM_SCU - select ARCH_TEGRA_HAS_PCIE - select ARCH_TEGRA_HAS_SATA - select ARCH_TEGRA_HAS_DUAL_3D - select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS - select ARM_CPU_SUSPEND if PM select ARM_ERRATA_743622 select ARM_ERRATA_751472 select ARM_ERRATA_754322 select ARM_ERRATA_761320 if SMP select ARM_ERRATA_764369 if SMP select ARM_GIC - select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP select COMMON_CLK - select CPA select CPU_FREQ_TABLE if CPU_FREQ select CPU_V7 - select GIC_SET_MULTIPLE_CPUS if SMP - select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select PCI_MSI if PCI_TEGRA select PINCTRL select PINCTRL_TEGRA30 - select POWER_RESET - select SYSTEM_PMIC select PL310_ERRATA_727915 select PL310_ERRATA_769419 if CACHE_L2X0 - select PM_GENERIC_DOMAINS if PM - select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG - select SOC_BUS - select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU - select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB_PHY select USB_ULPI_VIEWPORT if USB_PHY @@ -102,54 +64,8 @@ config ARCH_TEGRA_3x_SOC Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller -config ARCH_TEGRA_11x_SOC - bool "Tegra 11x family SOC" - depends on !ARCH_TEGRA_12x_SOC - depends on !ARCH_TEGRA_14x_SOC - select ARCH_HAS_PASR - select ARCH_TEGRA_4GB_MEMORY - select ARCH_TEGRA_HAS_CL_DVFS - select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS - select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE - select ARM_CPU_SUSPEND if PM - select ARM_ERRATA_798181 - select ARM_ERRATA_799270 - select ARM_GIC - select ARM_L1_CACHE_SHIFT_6 - select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP - select CPU_V7 - select HAVE_ARM_ARCH_TIMER - select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP - select PINCTRL - select PINCTRL_TEGRA114 - select POWER_RESET - select SYSTEM_PMIC - select PM_GENERIC_DOMAINS if PM - select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG - select SOC_BUS - select TEGRA_DUAL_CBUS - select TEGRA_CORE_EDP_LIMITS - select TEGRA_ERRATA_977223 - select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU - select TEGRA_ERRATA_1157520 - select TEGRA_ISOMGR - select TEGRA_ISOMGR_SYSFS - select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS - select TEGRA_MC_PTSA if !TEGRA_FPGA_PLATFORM - select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_EHCI_TEGRA if USB_SUPPORT - select USB_ULPI if USB_SUPPORT - select USB_ULPI_VIEWPORT if USB_SUPPORT - select PROC_DEVICETREE - help - Support for NVIDIA Tegra 11x family of SoCs, based upon the - ARM Cortex-A15MP CPU - config ARCH_TEGRA_12x_SOC bool "Tegra 12x family SOC" - depends on !ARCH_TEGRA_14x_SOC select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS if !ARM64 select ARCH_TEGRA_HAS_PCIE select CPU_V7 @@ -197,48 +113,6 @@ config ARCH_TEGRA_12x_SOC Support for NVIDIA Tegra 12x family of SoCs, based upon the ARM Cortex-A15MP CPU -config ARCH_TEGRA_14x_SOC - bool "Tegra 14x family SOC" - select ARCH_HAS_PASR - select ARCH_TEGRA_HAS_ARM_SCU - select ARCH_TEGRA_HAS_CL_DVFS - select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE - select ARM_CPU_SUSPEND if PM - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP - select ARM_GIC - select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP - select PINCTRL - select POWER_RESET - select SYSTEM_PMIC - select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP - select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS - select CPA - select CPU_V7 - select GIC_SET_MULTIPLE_CPUS if SMP - select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP - select PM_GENERIC_DOMAINS if PM - select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG - select SOC_BUS - select TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE - select TEGRA_DUAL_CBUS - select TEGRA_ERRATA_977223 - select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU - select TEGRA_ERRATA_1213083 - select TEGRA_ERRATA_1252872 - select TEGRA_ISOMGR - select TEGRA_ISOMGR_SYSFS - select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS - select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_EHCI_TEGRA if USB_SUPPORT - select USB_ULPI if USB_SUPPORT - select USB_ULPI_VIEWPORT if USB_SUPPORT - help - Support for NVIDIA Tegra 14x family of SoCs, based upon the - ARM CortexA9MP CPU and the ARM PL310 L2 cache controller - config TEGRA_NO_CARVEOUT bool "Disable Tegra carveout" default n @@ -320,47 +194,6 @@ config MACH_LAGUNA help Support for NVIDIA LAGUNA Development platform -config MACH_DALMORE - bool "Dalmore board" - depends on ARCH_TEGRA_11x_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC - help - Support for NVIDIA DALMORE development platform - -config MACH_PISMO - bool "Pismo board" - depends on ARCH_TEGRA_11x_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC - help - Support for NVIDIA PISMO development platform - -config MACH_MACALLAN - bool "Macallan board" - depends on ARCH_TEGRA_11x_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC - help - Support for NVIDIA MACALLAN development platform - -config MACH_TEGRA_PLUTO - bool "Pluto board" - depends on ARCH_TEGRA_11x_SOC - select MACH_HAS_SND_SOC_TEGRA_CS42L73 if SND_SOC - select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC - help - Support for NVIDIA PLUTO development platform - -config MACH_ROTH - bool "Thor board" - depends on ARCH_TEGRA_11x_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC - select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC - select TEGRA_CPU_FREQ_GOVERNOR_KERNEL_START - help - Support for NVIDIA THOR development platform - choice prompt "Tegra platform type" default TEGRA_SILICON_PLATFORM diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 6e3b40bc1d26..101192d8ba04 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -28,25 +28,13 @@ obj-y += sleep-t30.o obj-$(CONFIG_DEBUG_FS) += clocks_stats.o obj-y += tegra_core_volt_cap.o obj-$(CONFIG_TEGRA_USE_SIMON) += tegra_simon.o -ifeq ($(CONFIG_ARCH_TEGRA_3x_SOC),y) -obj-$(CONFIG_PM_SLEEP) += wakeups-t3.o -endif -ifeq ($(CONFIG_ARCH_TEGRA_14x_SOC),y) -obj-$(CONFIG_PM_SLEEP) += wakeups-t14x.o -endif -ifeq ($(CONFIG_ARCH_TEGRA_11x_SOC),y) -obj-$(CONFIG_PM_SLEEP) += wakeups-t11x.o -endif ifeq ($(CONFIG_ARCH_TEGRA_12x_SOC),y) obj-$(CONFIG_PM_SLEEP) += wakeups-t12x.o endif ifeq ($(CONFIG_CPU_IDLE),y) ifeq ($(CONFIG_PM_SLEEP),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-t3.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += cpuidle-t11x.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += cpuidle-t11x.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += cpuidle-t14x.o endif endif endif @@ -69,35 +57,23 @@ obj-y += powergate-ops-txx.o obj-y += powergate-ops-t1xx.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate-t20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += powergate-t30.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += powergate-t11x.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += powergate-t14x.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += powergate-t12x.o obj-y += apbio.o obj-$(CONFIG_TEGRA_ARB_SEMAPHORE) += arb_sema.o obj-y += dvfs.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_dvfs.o ifeq ($(CONFIG_ARCH_TEGRA_13x_SOC),y) obj-y += tegra13_dvfs.o else obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12_dvfs.o endif -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14_dvfs.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra_emc_therm.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra_emc_therm.o obj-y += latency_allowance.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_la.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11x_la.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14x_la.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12x_la.o obj-$(CONFIG_TEGRA_EDP_LIMITS) += edp.o obj-$(CONFIG_TEGRA_CORE_EDP_LIMITS) += edp_core.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_edp.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14_edp.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12_edp.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_speedo.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14_speedo.o ifeq ($(CONFIG_ARCH_TEGRA_13x_SOC),y) obj-y += tegra13_speedo.o else @@ -109,10 +85,7 @@ obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra3_actmon.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra3_actmon.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_emc.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_emc.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12_emc.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14_emc.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra_emc_dt_parse.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra_emc_dt_parse.o obj-y += tegra_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o @@ -121,32 +94,22 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-y += flowctrl.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_IDLE) += sleep.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_clocks.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12_clocks.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14_clocks.o obj-$(CONFIG_SMP) += platsmp.o obj-y += reset.o obj-y += headsmp.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o ifeq ($(CONFIG_TEGRA_AUTO_HOTPLUG),y) ifeq ($(CONFIG_TEGRA_CPUQUIET),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuquiet.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += cpuquiet.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += cpuquiet.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += cpuquiet.o else obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpu-tegra3.o endif endif ifeq ($(CONFIG_TEGRA_SOCTHERM),y) -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_soctherm.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra11_soctherm.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra11_soctherm.o endif ifeq ($(CONFIG_TEGRA_THERMAL_THROTTLE),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_throttle.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra3_throttle.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra3_throttle.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra3_throttle.o endif obj-$(CONFIG_DEBUG_ICEDCC) += sysfs-dcc.o @@ -156,7 +119,6 @@ obj-$(CONFIG_ARCH_TEGRA_HAS_CL_DVFS) += tegra_cl_dvfs.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += board-dt-tegra148.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o diff --git a/arch/arm/mach-tegra/board-dt-tegra148.c b/arch/arm/mach-tegra/board-dt-tegra148.c deleted file mode 100644 index 81d3ed273981..000000000000 --- a/arch/arm/mach-tegra/board-dt-tegra148.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dt-tegra148.c - * - * NVIDIA Tegra148 device tree board support - * - * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/of.h> -#include <linux/irqchip.h> - -#include <asm/mach/arch.h> - -#include "board.h" -#include "clock.h" -#include "common.h" - -#ifdef CONFIG_USE_OF - -static void __init tegra148_dt_init(void) -{ -} - -static const char * const tegra148_dt_board_compat[] = { - "nvidia,tegra148", - NULL -}; - -DT_MACHINE_START(TEGRA148_DT, "NVIDIA Tegra148 (Flattened Device Tree)") - .smp = smp_ops(tegra_smp_ops), - .map_io = tegra_map_common_io, - .init_early = tegra14x_init_early, - .init_irq = irqchip_init, - .init_time = tegra_init_timer, - .init_machine = tegra148_dt_init, - .restart = tegra_assert_system_reset, - .dt_compat = tegra148_dt_board_compat, -MACHINE_END - -#endif diff --git a/arch/arm/mach-tegra/board-panel.h b/arch/arm/mach-tegra/board-panel.h index 77688f207267..eef84fff1ce7 100644 --- a/arch/arm/mach-tegra/board-panel.h +++ b/arch/arm/mach-tegra/board-panel.h @@ -62,9 +62,6 @@ extern struct tegra_panel_ops dsi_p_wuxga_10_1_ops; extern struct tegra_panel_ops dsi_lgd_wxga_7_0_ops; extern struct tegra_panel_ops dsi_s_wqxga_10_1_ops; -extern struct tegra_panel dsi_l_720p_5; -extern struct tegra_panel dsi_j_720p_4_7; -extern struct tegra_panel dsi_s_1080p_5; extern struct tegra_panel dsi_p_wuxga_10_1; extern struct tegra_panel dsi_a_1080p_11_6; extern struct tegra_panel dsi_s_wqxga_10_1; diff --git a/arch/arm/mach-tegra/cpuidle-t14x.c b/arch/arm/mach-tegra/cpuidle-t14x.c deleted file mode 100644 index 3af1eece7441..000000000000 --- a/arch/arm/mach-tegra/cpuidle-t14x.c +++ /dev/null @@ -1,792 +0,0 @@ -/* - * arch/arm/mach-tegra/cpuidle-t14x.c - * - * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/cpu.h> -#include <linux/cpuidle.h> -#include <linux/debugfs.h> -#include <linux/delay.h> -#include <linux/hrtimer.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/ratelimit.h> -#include <linux/sched.h> -#include <linux/seq_file.h> -#include <linux/slab.h> -#include <linux/smp.h> -#include <linux/suspend.h> -#include <linux/tick.h> -#include <linux/clk.h> -#include <linux/cpu_pm.h> -#include <linux/module.h> -#include <linux/tegra-soc.h> -#include <linux/irqchip/tegra.h> - -#include <asm/cacheflush.h> -#include <asm/localtimer.h> -#include <asm/suspend.h> -#include <asm/smp_twd.h> -#include <asm/cputype.h> - -#include <mach/irqs.h> - -#include <trace/events/nvpower.h> - -#include "clock.h" -#include "cpuidle.h" -#include "dvfs.h" -#include "iomap.h" -#include "pm.h" -#include "reset.h" -#include "sleep.h" -#include "timer.h" - -#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x470) -#define PMC_POWERGATE_STATUS \ - (IO_ADDRESS(TEGRA_PMC_BASE) + 0x038) - -#ifdef CONFIG_SMP -static s64 tegra_cpu_wake_by_time[4] = { - LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX }; -#endif - -static ulong cpu_power_gating_in_idle __read_mostly = 0x1f; -module_param(cpu_power_gating_in_idle, ulong, 0644); - -static bool slow_cluster_power_gating_noncpu __read_mostly; -module_param(slow_cluster_power_gating_noncpu, bool, 0644); - -static uint fast_cluster_power_down_mode __read_mostly; -module_param(fast_cluster_power_down_mode, uint, 0644); - -static bool stop_mc_clk_in_idle __read_mostly; -module_param(stop_mc_clk_in_idle, bool, 0644); - -static struct clk *cpu_clk_for_dvfs; -#ifdef CONFIG_HAVE_ARM_TWD -static struct clk *twd_clk; -#endif - -static int pd_exit_latencies[5]; - -static struct { - unsigned int cpu_ready_count[5]; - unsigned int tear_down_count[5]; - unsigned long long cpu_wants_pd_time[5]; - unsigned long long cpu_pg_time[5]; - unsigned long long rail_pd_time; - unsigned long long c0nc_pg_time; - unsigned long long c1nc_pg_time; - unsigned long long mc_clk_stop_time; - unsigned int rail_gating_count; - unsigned int rail_gating_bin[32]; - unsigned int rail_gating_done_count; - unsigned int rail_gating_done_count_bin[32]; - unsigned int c0nc_gating_count; - unsigned int c0nc_gating_bin[32]; - unsigned int c0nc_gating_done_count; - unsigned int c0nc_gating_done_count_bin[32]; - unsigned int c1nc_gating_count; - unsigned int c1nc_gating_bin[32]; - unsigned int c1nc_gating_done_count; - unsigned int c1nc_gating_done_count_bin[32]; - unsigned int mc_clk_stop_count; - unsigned int mc_clk_stop_bin[32]; - unsigned int mc_clk_stop_done_count; - unsigned int mc_clk_stop_done_count_bin[32]; - unsigned int pd_int_count[NR_IRQS]; - unsigned int last_pd_int_count[NR_IRQS]; - unsigned int clk_gating_vmin; -} idle_stats; - -static inline unsigned int time_to_bin(unsigned int time) -{ - return fls(time); -} - -static inline void tegra_irq_unmask(int irq) -{ - struct irq_data *data = irq_get_irq_data(irq); - data->chip->irq_unmask(data); -} - -static inline unsigned int cpu_number(unsigned int n) -{ - return is_lp_cluster() ? 4 : n; -} - -void tegra14x_cpu_idle_stats_pd_ready(unsigned int cpu) -{ - idle_stats.cpu_ready_count[cpu_number(cpu)]++; -} - -void tegra14x_cpu_idle_stats_pd_time(unsigned int cpu, s64 us) -{ - idle_stats.cpu_wants_pd_time[cpu_number(cpu)] += us; -} - -/* Allow rail off only if all secondary CPUs are power gated, and no - rail update is in progress */ -static bool tegra_rail_off_is_allowed(void) -{ - u32 rst = readl(CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); - u32 pg = readl(PMC_POWERGATE_STATUS) >> 8; - - if (((rst & 0xE) != 0xE) || ((pg & 0xE) != 0)) - return false; - - if (tegra_dvfs_rail_updating(cpu_clk_for_dvfs)) - return false; - - return true; -} - -bool tegra14x_pd_is_allowed(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - s64 request; - - if (!cpumask_test_cpu(cpu_number(dev->cpu), - to_cpumask(&cpu_power_gating_in_idle))) - return false; - - request = ktime_to_us(tick_nohz_get_sleep_length()); - if (state->exit_latency != pd_exit_latencies[cpu_number(dev->cpu)]) { - /* possible on the 1st entry after cluster switch*/ - state->exit_latency = pd_exit_latencies[cpu_number(dev->cpu)]; - tegra_pd_update_target_residency(state); - } - if (request < state->target_residency) { - /* Not enough time left to enter LP2 */ - return false; - } - - return true; -} - -static inline void tegra14_irq_restore_affinity(void) -{ -#ifdef CONFIG_SMP - /* Disable the distributor. */ - tegra_gic_dist_disable(); - - /* Restore the other CPU's interrupt affinity. */ - tegra_gic_restore_affinity(); - - /* Re-enable the distributor. */ - tegra_gic_dist_enable(); -#endif -} - -static bool tegra_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_state *state, s64 request) -{ - ktime_t entry_time; - ktime_t exit_time; - bool sleep_completed = false; - bool multi_cpu_entry = false; - int bin; - unsigned int flag = 0; - s64 sleep_time; - - /* LP2 entry time */ - entry_time = ktime_get(); - - if (request < state->target_residency) { - /* Not enough time left to enter LP2 */ - cpu_do_idle(); - return false; - } - -#ifdef CONFIG_SMP - multi_cpu_entry = !is_lp_cluster() && (num_online_cpus() > 1); - if (multi_cpu_entry) { - s64 wake_time; - unsigned int i; - - /* Disable the distributor -- this is the only way to - prevent the other CPUs from responding to interrupts - and potentially fiddling with the distributor - registers while we're fiddling with them. */ - tegra_gic_dist_disable(); - - /* Did an interrupt come in for another CPU before we - could disable the distributor? */ - if (!tegra_rail_off_is_allowed()) { - /* Yes, re-enable the distributor and clock gating. */ - tegra_gic_dist_enable(); - cpu_do_idle(); - return false; - } - - /* LP2 initial targeted wake time */ - wake_time = ktime_to_us(entry_time) + request; - - /* CPU0 must wake up before any of the other CPUs. */ - smp_rmb(); - for (i = 1; i < CONFIG_NR_CPUS; i++) - wake_time = min_t(s64, wake_time, - tegra_cpu_wake_by_time[i]); - - /* LP2 actual targeted wake time */ - request = wake_time - ktime_to_us(entry_time); - BUG_ON(wake_time < 0LL); - - if (request < state->target_residency) { - /* Not enough time left to enter LP2 */ - tegra_gic_dist_enable(); - cpu_do_idle(); - return false; - } - - /* Cancel power gating wake timers for all secondary CPUs */ - tegra_pd_timer_cancel_secondary(); - - /* Save and disable the affinity setting for the other - CPUs and route all interrupts to CPU0. */ - tegra_gic_disable_affinity(); - - /* Re-enable the distributor. */ - tegra_gic_dist_enable(); - } -#endif - cpu_pm_enter(); - - sleep_time = request - - pd_exit_latencies[cpu_number(dev->cpu)]; - - bin = time_to_bin((u32)request / 1000); - idle_stats.tear_down_count[cpu_number(dev->cpu)]++; - - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); - if (is_lp_cluster()) { - /* here we are not supporting emulation mode, for now */ - flag = TEGRA_POWER_CLUSTER_PART_NONCPU; - idle_stats.c1nc_gating_count++; - idle_stats.c1nc_gating_bin[bin]++; - } else { - tegra_dvfs_rail_off(tegra_cpu_rail, entry_time); - flag = (fast_cluster_power_down_mode - << TEGRA_POWER_CLUSTER_PART_SHIFT) - & TEGRA_POWER_CLUSTER_PART_MASK; - if ((request < tegra_min_residency_crail()) && - (flag != TEGRA_POWER_CLUSTER_PART_MASK)) - flag = TEGRA_POWER_CLUSTER_PART_NONCPU; - - if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL) { - idle_stats.rail_gating_count++; - idle_stats.rail_gating_bin[bin]++; - } else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) { - idle_stats.c0nc_gating_count++; - idle_stats.c0nc_gating_bin[bin]++; - } - } - - if (stop_mc_clk_in_idle && (state->power_usage == 0) && - (request > tegra_mc_clk_stop_min_residency())) { - flag |= TEGRA_POWER_STOP_MC_CLK; - - trace_nvmc_clk_stop_rcuidle(NVPOWER_MC_CLK_STOP_ENTRY, - sleep_time); - idle_stats.mc_clk_stop_count++; - idle_stats.mc_clk_stop_bin[bin]++; - - tegra_mc_clk_prepare(); - } - - if (tegra_idle_power_down_last(sleep_time, flag) == 0) - sleep_completed = true; - else { - int irq = tegra_gic_pending_interrupt(); - idle_stats.pd_int_count[irq]++; - } - - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); - exit_time = ktime_get(); - - if (flag & TEGRA_POWER_STOP_MC_CLK) - tegra_mc_clk_finish(); - - if (!is_lp_cluster()) - tegra_dvfs_rail_on(tegra_cpu_rail, exit_time); - - if (flag & TEGRA_POWER_STOP_MC_CLK) - idle_stats.mc_clk_stop_time += - ktime_to_us(ktime_sub(exit_time, entry_time)); - else if (flag & TEGRA_POWER_CLUSTER_PART_CRAIL) - idle_stats.rail_pd_time += - ktime_to_us(ktime_sub(exit_time, entry_time)); - else if (flag & TEGRA_POWER_CLUSTER_PART_NONCPU) { - if (is_lp_cluster()) - idle_stats.c1nc_pg_time += - ktime_to_us(ktime_sub(exit_time, entry_time)); - else - idle_stats.c0nc_pg_time += - ktime_to_us(ktime_sub(exit_time, entry_time)); - } - - if (multi_cpu_entry) - tegra14_irq_restore_affinity(); - - if (sleep_completed) { - /* - * Stayed in LP2 for the full time until the next tick, - * adjust the exit latency based on measurement - */ - int offset = ktime_to_us(ktime_sub(exit_time, entry_time)) - - request; - int latency = pd_exit_latencies[cpu_number(dev->cpu)] + - offset / 16; - latency = clamp(latency, 0, 10000); - pd_exit_latencies[cpu_number(dev->cpu)] = latency; - state->exit_latency = latency; /* for idle governor */ - smp_wmb(); - - if (flag & TEGRA_POWER_STOP_MC_CLK) { - trace_nvmc_clk_stop_rcuidle(NVPOWER_MC_CLK_STOP_EXIT, - sleep_time); - idle_stats.mc_clk_stop_done_count++; - idle_stats.mc_clk_stop_done_count_bin[bin]++; - } else if (flag & TEGRA_POWER_CLUSTER_PART_CRAIL) { - idle_stats.rail_gating_done_count++; - idle_stats.rail_gating_done_count_bin[bin]++; - } else if (flag & TEGRA_POWER_CLUSTER_PART_NONCPU) { - if (is_lp_cluster()) { - idle_stats.c1nc_gating_done_count++; - idle_stats.c1nc_gating_done_count_bin[bin]++; - } else { - idle_stats.c0nc_gating_done_count++; - idle_stats.c0nc_gating_done_count_bin[bin]++; - } - } - - pr_debug("%lld %lld %d %d\n", request, - ktime_to_us(ktime_sub(exit_time, entry_time)), - offset, bin); - } - - cpu_pm_exit(); - - return true; -} - -static bool tegra_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_state *state, s64 request) -{ -#ifdef CONFIG_SMP - s64 sleep_time; - ktime_t entry_time; -#ifdef CONFIG_HAVE_ARM_TWD - struct tegra_twd_context twd_context; -#endif - bool sleep_completed = false; - struct tick_sched *ts = tick_get_tick_sched(dev->cpu); -#ifdef CONFIG_HAVE_ARM_TWD -#if defined(CONFIG_TEGRA_LP2_CPU_TIMER) - void __iomem *twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); -#endif - - if (!tegra_twd_get_state(&twd_context)) { - unsigned long twd_rate = clk_get_rate(twd_clk); - - if ((twd_context.twd_ctrl & TWD_TIMER_CONTROL_ENABLE) && - (twd_context.twd_ctrl & TWD_TIMER_CONTROL_IT_ENABLE)) { - request = div_u64((u64)twd_context.twd_cnt * 1000000, - twd_rate); -#ifdef CONFIG_TEGRA_LP2_CPU_TIMER - if (request >= state->target_residency) { - twd_context.twd_cnt -= state->exit_latency * - (twd_rate / 1000000); - writel(twd_context.twd_cnt, - twd_base + TWD_TIMER_COUNTER); - } -#endif - } - } -#endif - - if (!tegra_is_cpu_wake_timer_ready(dev->cpu) || - (request < state->target_residency) || - (!ts) || (ts->nohz_mode == NOHZ_MODE_INACTIVE)) { - /* - * Not enough time left to enter LP2, or wake timer not ready - */ - cpu_do_idle(); - return false; - } - - cpu_pm_enter(); - -#if !defined(CONFIG_TEGRA_LP2_CPU_TIMER) - sleep_time = request - state->exit_latency; - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); -#ifdef CONFIG_HAVE_ARM_TWD - tegra_twd_suspend(&twd_context); -#endif - tegra_pd_set_trigger(sleep_time); -#endif - idle_stats.tear_down_count[cpu_number(dev->cpu)]++; - - entry_time = ktime_get(); - - /* Save time this CPU must be awakened by. */ - tegra_cpu_wake_by_time[dev->cpu] = ktime_to_us(entry_time) + request; - smp_wmb(); - -#ifdef CONFIG_TRUSTED_LITTLE_KERNEL - if (dev->cpu == 0) { - tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4, - (TEGRA_RESET_HANDLER_BASE + - tegra_cpu_reset_handler_offset)); - } -#endif - cpu_suspend(0, tegra3_sleep_cpu_secondary_finish); - - tegra_cpu_wake_by_time[dev->cpu] = LLONG_MAX; - -#ifdef CONFIG_TEGRA_LP2_CPU_TIMER -#ifdef CONFIG_HAVE_ARM_TWD - if (!tegra_twd_get_state(&twd_context)) - sleep_completed = (twd_context.twd_cnt == 0); -#endif -#else - sleep_completed = !tegra_pd_timer_remain(); - tegra_pd_set_trigger(0); -#ifdef CONFIG_HAVE_ARM_TWD - tegra_twd_resume(&twd_context); -#endif - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); -#endif - sleep_time = ktime_to_us(ktime_sub(ktime_get(), entry_time)); - idle_stats.cpu_pg_time[cpu_number(dev->cpu)] += sleep_time; - if (sleep_completed) { - /* - * Stayed in LP2 for the full time until timer expires, - * adjust the exit latency based on measurement - */ - int offset = sleep_time - request; - int latency = pd_exit_latencies[cpu_number(dev->cpu)] + - offset / 16; - latency = clamp(latency, 0, 10000); - pd_exit_latencies[cpu_number(dev->cpu)] = latency; - state->exit_latency = latency; /* for idle governor */ - smp_wmb(); - } -#endif - cpu_pm_exit(); - - return true; -} - -bool tegra14x_idle_power_down(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - bool power_down; - bool cpu_gating_only = false; - bool clkgt_at_vmin = false; - bool power_gating_cpu_only = true; - unsigned long rate; - int status = -1; - s64 request = ktime_to_us(tick_nohz_get_sleep_length()); - - tegra_set_cpu_in_pd(dev->cpu); - cpu_gating_only = (((fast_cluster_power_down_mode - << TEGRA_POWER_CLUSTER_PART_SHIFT) - & TEGRA_POWER_CLUSTER_PART_MASK) == 0); - - if (is_lp_cluster()) { - if (slow_cluster_power_gating_noncpu && - (request > tegra_min_residency_ncpu())) - power_gating_cpu_only = false; - else - power_gating_cpu_only = true; - } else { - if (num_online_cpus() > 1) - power_gating_cpu_only = true; - else { - if (tegra_dvfs_rail_updating(cpu_clk_for_dvfs)) - clkgt_at_vmin = false; - else if (tegra_force_clkgt_at_vmin == - TEGRA_CPUIDLE_FORCE_DO_CLKGT_VMIN) - clkgt_at_vmin = true; - else if (tegra_force_clkgt_at_vmin == - TEGRA_CPUIDLE_FORCE_NO_CLKGT_VMIN) - clkgt_at_vmin = false; - else if ((request >= tegra_min_residency_vmin_fmin()) && - ((request < tegra_min_residency_ncpu()) || - cpu_gating_only)) - clkgt_at_vmin = true; - - if (!cpu_gating_only && tegra_rail_off_is_allowed()) { - if (fast_cluster_power_down_mode & - TEGRA_POWER_CLUSTER_FORCE_MASK) - power_gating_cpu_only = false; - else if (request > - tegra_min_residency_ncpu()) - power_gating_cpu_only = false; - else - power_gating_cpu_only = true; - } else - power_gating_cpu_only = true; - } - } - - if (clkgt_at_vmin) { - rate = 0; - status = tegra_cpu_g_idle_rate_exchange(&rate); - if (!status) { - idle_stats.clk_gating_vmin++; - cpu_do_idle(); - tegra_cpu_g_idle_rate_exchange(&rate); - power_down = true; - } else { - power_down = tegra_cpu_core_power_down(dev, state, - request); - } - } else if (power_gating_cpu_only) - power_down = tegra_cpu_core_power_down(dev, state, request); - else { - if (is_lp_cluster()) { - rate = ULONG_MAX; - status = tegra_cpu_lp_idle_rate_exchange(&rate); - } - - power_down = tegra_cpu_cluster_power_down(dev, state, request); - - /* restore cpu clock after cluster power ungating */ - if (status == 0) - tegra_cpu_lp_idle_rate_exchange(&rate); - } - - tegra_clear_cpu_in_pd(dev->cpu); - - return power_down; -} - -#ifdef CONFIG_DEBUG_FS -int tegra14x_pd_debug_show(struct seq_file *s, void *data) -{ - int bin; - int i; - unsigned long long total_c0cpu0_pg_time = 0; - unsigned long long total_c1cpu0_pg_time = 0; - - seq_printf(s, " cpu0 cpu1 cpu2 cpu3 cpulp\n"); - seq_printf(s, "-----------------------------------------------------------------------------\n"); - seq_printf(s, "cpu ready: %8u %8u %8u %8u %8u\n", - idle_stats.cpu_ready_count[0], - idle_stats.cpu_ready_count[1], - idle_stats.cpu_ready_count[2], - idle_stats.cpu_ready_count[3], - idle_stats.cpu_ready_count[4]); - seq_printf(s, "tear down: %8u %8u %8u %8u %8u\n", - idle_stats.tear_down_count[0], - idle_stats.tear_down_count[1], - idle_stats.tear_down_count[2], - idle_stats.tear_down_count[3], - idle_stats.tear_down_count[4]); - seq_printf(s, "clk gating @ Vmin count: %8u\n", - idle_stats.clk_gating_vmin); - seq_printf(s, "rail gating count: %8u\n", - idle_stats.rail_gating_count); - seq_printf(s, "rail gating completed: %8u %7u%%\n", - idle_stats.rail_gating_done_count, - idle_stats.rail_gating_done_count * 100 / - (idle_stats.rail_gating_count ?: 1)); - - seq_printf(s, "c0nc gating count: %8u\n", - idle_stats.c0nc_gating_count); - seq_printf(s, "c0nc gating completed: %8u %7u%%\n", - idle_stats.c0nc_gating_done_count, - idle_stats.c0nc_gating_done_count * 100 / - (idle_stats.c0nc_gating_count ?: 1)); - - seq_printf(s, "c1nc gating count: %8u\n", - idle_stats.c1nc_gating_count); - seq_printf(s, "c1nc gating completed: %8u %7u%%\n", - idle_stats.c1nc_gating_done_count, - idle_stats.c1nc_gating_done_count * 100 / - (idle_stats.c1nc_gating_count ?: 1)); - - seq_printf(s, "mc clk stop count: %8u\n", - idle_stats.mc_clk_stop_count); - seq_printf(s, "mc_clk_stop completed: %8u %7u%%\n", - idle_stats.mc_clk_stop_done_count, - idle_stats.mc_clk_stop_done_count * 100 / - (idle_stats.mc_clk_stop_count ?: 1)); - - seq_printf(s, "\n"); - seq_printf(s, "cpu ready time: " \ - "%8llu %8llu %8llu %8llu %8llu ms\n", - div64_u64(idle_stats.cpu_wants_pd_time[0], 1000), - div64_u64(idle_stats.cpu_wants_pd_time[1], 1000), - div64_u64(idle_stats.cpu_wants_pd_time[2], 1000), - div64_u64(idle_stats.cpu_wants_pd_time[3], 1000), - div64_u64(idle_stats.cpu_wants_pd_time[4], 1000)); - - total_c0cpu0_pg_time = idle_stats.cpu_pg_time[0] + \ - idle_stats.c0nc_pg_time + \ - idle_stats.rail_pd_time; - total_c1cpu0_pg_time = idle_stats.cpu_pg_time[4] + \ - idle_stats.c1nc_pg_time; - - seq_printf(s, "cpu power gating time: " \ - "%8llu %8llu %8llu %8llu %8llu ms\n", - div64_u64(total_c0cpu0_pg_time, 1000), - div64_u64(idle_stats.cpu_pg_time[1], 1000), - div64_u64(idle_stats.cpu_pg_time[2], 1000), - div64_u64(idle_stats.cpu_pg_time[3], 1000), - div64_u64(total_c1cpu0_pg_time, 1000)); - - seq_printf(s, "power gated %%: " \ - "%7d%% %7d%% %7d%% %7d%% %7d%%\n", - (int)(idle_stats.cpu_wants_pd_time[0] ? - div64_u64(total_c0cpu0_pg_time * 100, - idle_stats.cpu_wants_pd_time[0]) : 0), - (int)(idle_stats.cpu_wants_pd_time[1] ? - div64_u64(idle_stats.cpu_pg_time[1] * 100, - idle_stats.cpu_wants_pd_time[1]) : 0), - (int)(idle_stats.cpu_wants_pd_time[2] ? - div64_u64(idle_stats.cpu_pg_time[2] * 100, - idle_stats.cpu_wants_pd_time[2]) : 0), - (int)(idle_stats.cpu_wants_pd_time[3] ? - div64_u64(idle_stats.cpu_pg_time[3] * 100, - idle_stats.cpu_wants_pd_time[3]) : 0), - (int)(idle_stats.cpu_wants_pd_time[4] ? - div64_u64(total_c1cpu0_pg_time * 100, - idle_stats.cpu_wants_pd_time[4]) : 0)); - - seq_printf(s, "\n"); - seq_printf(s, "rail gating time c0nc gating time c1nc gating time\n"); - seq_printf(s, "%8llu ms %8llu ms %8llu ms\n", - div64_u64(idle_stats.rail_pd_time, 1000), - div64_u64(idle_stats.c0nc_pg_time, 1000), - div64_u64(idle_stats.c1nc_pg_time, 1000)); - seq_printf(s, "%8d%% %8d%% %8d%%\n", - (int)(idle_stats.cpu_wants_pd_time[0] ? - div64_u64(idle_stats.rail_pd_time * 100, - idle_stats.cpu_wants_pd_time[0]) : 0), - (int)(idle_stats.cpu_wants_pd_time[0] ? - div64_u64(idle_stats.c0nc_pg_time * 100, - idle_stats.cpu_wants_pd_time[0]) : 0), - (int)(idle_stats.cpu_wants_pd_time[4] ? - div64_u64(idle_stats.c1nc_pg_time * 100, - idle_stats.cpu_wants_pd_time[4]) : 0)); - - seq_printf(s, "\n"); - - seq_printf(s, "%19s %8s %8s %8s\n", "", "rail gating", "comp", "%"); - seq_printf(s, "-------------------------------------------------\n"); - for (bin = 0; bin < 32; bin++) { - if (idle_stats.rail_gating_bin[bin] == 0) - continue; - seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n", - 1 << (bin - 1), 1 << bin, - idle_stats.rail_gating_bin[bin], - idle_stats.rail_gating_done_count_bin[bin], - idle_stats.rail_gating_done_count_bin[bin] * 100 / - idle_stats.rail_gating_bin[bin]); - } - seq_printf(s, "\n"); - - seq_printf(s, "%19s %8s %8s %8s\n", "", "c0nc gating", "comp", "%"); - seq_printf(s, "-------------------------------------------------\n"); - for (bin = 0; bin < 32; bin++) { - if (idle_stats.c0nc_gating_bin[bin] == 0) - continue; - seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n", - 1 << (bin - 1), 1 << bin, - idle_stats.c0nc_gating_bin[bin], - idle_stats.c0nc_gating_done_count_bin[bin], - idle_stats.c0nc_gating_done_count_bin[bin] * 100 / - idle_stats.c0nc_gating_bin[bin]); - } - seq_printf(s, "\n"); - - seq_printf(s, "%19s %8s %8s %8s\n", "", "c1nc gating", "comp", "%"); - seq_printf(s, "-------------------------------------------------\n"); - for (bin = 0; bin < 32; bin++) { - if (idle_stats.c1nc_gating_bin[bin] == 0) - continue; - seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n", - 1 << (bin - 1), 1 << bin, - idle_stats.c1nc_gating_bin[bin], - idle_stats.c1nc_gating_done_count_bin[bin], - idle_stats.c1nc_gating_done_count_bin[bin] * 100 / - idle_stats.c1nc_gating_bin[bin]); - } - seq_printf(s, "\n"); - - seq_printf(s, "%19s %8s %8s %8s\n", "", "mc clk stop", "comp", "%"); - seq_printf(s, "-------------------------------------------------\n"); - for (bin = 0; bin < 32; bin++) { - if (idle_stats.mc_clk_stop_bin[bin] == 0) - continue; - seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n", - 1 << (bin - 1), 1 << bin, - idle_stats.mc_clk_stop_bin[bin], - idle_stats.mc_clk_stop_done_count_bin[bin], - idle_stats.mc_clk_stop_done_count_bin[bin] * 100 / - idle_stats.mc_clk_stop_bin[bin]); - } - - seq_printf(s, "\n"); - seq_printf(s, "%3s %20s %6s %10s\n", - "int", "name", "count", "last count"); - seq_printf(s, "--------------------------------------------\n"); - for (i = 0; i < NR_IRQS; i++) { - if (idle_stats.pd_int_count[i] == 0) - continue; - seq_printf(s, "%3d %20s %6d %10d\n", - i, irq_to_desc(i)->action ? - irq_to_desc(i)->action->name ?: "???" : "???", - idle_stats.pd_int_count[i], - idle_stats.pd_int_count[i] - - idle_stats.last_pd_int_count[i]); - idle_stats.last_pd_int_count[i] = idle_stats.pd_int_count[i]; - }; - return 0; -} -#endif - -int __init tegra14x_cpuidle_init_soc(struct tegra_cpuidle_ops *idle_ops) -{ - int i; - struct tegra_cpuidle_ops ops = { - tegra14x_idle_power_down, - tegra14x_cpu_idle_stats_pd_ready, - tegra14x_cpu_idle_stats_pd_time, - tegra14x_pd_is_allowed, -#ifdef CONFIG_DEBUG_FS - tegra14x_pd_debug_show -#endif - }; - - cpu_clk_for_dvfs = tegra_get_clock_by_name("cpu_g"); -#ifdef CONFIG_HAVE_ARM_TWD - twd_clk = tegra_get_clock_by_name("twd"); -#endif - - for (i = 0; i < ARRAY_SIZE(pd_exit_latencies); i++) - pd_exit_latencies[i] = tegra_pg_exit_latency; - - *idle_ops = ops; - - return 0; -} diff --git a/arch/arm/mach-tegra/cpuidle-t3.c b/arch/arm/mach-tegra/cpuidle-t3.c deleted file mode 100644 index 7ec29a069535..000000000000 --- a/arch/arm/mach-tegra/cpuidle-t3.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * arch/arm/mach-tegra/cpuidle-t3.c - * - * CPU idle driver for Tegra3 CPUs - * - * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/cpu.h> -#include <linux/cpuidle.h> -#include <linux/debugfs.h> -#include <linux/delay.h> -#include <linux/hrtimer.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/ratelimit.h> -#include <linux/sched.h> -#include <linux/seq_file.h> -#include <linux/slab.h> -#include <linux/smp.h> -#include <linux/suspend.h> -#include <linux/tick.h> -#include <linux/clk.h> -#include <linux/cpu_pm.h> -#include <linux/module.h> -#include <linux/tegra-soc.h> -#include <linux/irqchip/tegra.h> - -#include <asm/cacheflush.h> -#include <asm/localtimer.h> -#include <asm/suspend.h> -#include <asm/smp_twd.h> -#include <asm/cputype.h> - -#include <mach/irqs.h> - -#include <trace/events/power.h> - -#include "clock.h" -#include "cpuidle.h" -#include "dvfs.h" -#include "iomap.h" -#include "pm.h" -#include "reset.h" -#include "sleep.h" -#include "timer.h" - -#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x470) -#define PMC_POWERGATE_STATUS \ - (IO_ADDRESS(TEGRA_PMC_BASE) + 0x038) - -#ifdef CONFIG_SMP -static s64 tegra_cpu_wake_by_time[4] = { - LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX }; -#endif - -static bool lp2_0_in_idle = true; -module_param(lp2_0_in_idle, bool, 0644); - -static bool lp2_n_in_idle = true; -module_param(lp2_n_in_idle, bool, 0644); - -static struct clk *cpu_clk_for_dvfs; -static struct clk *twd_clk; - -static int lp2_exit_latencies[5]; - -static struct { - unsigned int cpu_ready_count[5]; - unsigned int tear_down_count[5]; - unsigned long long cpu_wants_lp2_time[5]; - unsigned long long in_lp2_time[5]; - unsigned int lp2_count; - unsigned int lp2_completed_count; - unsigned int lp2_count_bin[32]; - unsigned int lp2_completed_count_bin[32]; - unsigned int lp2_int_count[NR_IRQS]; - unsigned int last_lp2_int_count[NR_IRQS]; -} idle_stats; - -static inline unsigned int time_to_bin(unsigned int time) -{ - return fls(time); -} - -static inline void tegra_irq_unmask(int irq) -{ - struct irq_data *data = irq_get_irq_data(irq); - data->chip->irq_unmask(data); -} - -static inline unsigned int cpu_number(unsigned int n) -{ - return is_lp_cluster() ? 4 : n; -} - -void tegra3_cpu_idle_stats_lp2_ready(unsigned int cpu) -{ - idle_stats.cpu_ready_count[cpu_number(cpu)]++; -} - -void tegra3_cpu_idle_stats_lp2_time(unsigned int cpu, s64 us) -{ - idle_stats.cpu_wants_lp2_time[cpu_number(cpu)] += us; -} - -/* Allow rail off only if all secondary CPUs are power gated, and no - rail update is in progress */ -static bool tegra_rail_off_is_allowed(void) -{ - u32 rst = readl(CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); - u32 pg = readl(PMC_POWERGATE_STATUS) >> 8; - - if (((rst & 0xE) != 0xE) || ((pg & 0xE) != 0)) - return false; - - if (tegra_dvfs_rail_updating(cpu_clk_for_dvfs)) - return false; - - return true; -} - -bool tegra3_lp2_is_allowed(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - s64 request; - - if (!tegra_all_cpus_booted) - return false; - - if ((!lp2_0_in_idle && !dev->cpu) || (!lp2_n_in_idle && dev->cpu)) - return false; - -#ifndef CONFIG_TEGRA_RAIL_OFF_MULTIPLE_CPUS - /* FIXME: All CPU's entering LP2 is not working. - * Don't let CPU0 enter LP2 when any secondary CPU is online. - */ - if ((dev->cpu == 0) && (num_online_cpus() > 1)) - return false; -#endif - if ((dev->cpu == 0) && (!tegra_rail_off_is_allowed())) - return false; - - request = ktime_to_us(tick_nohz_get_sleep_length()); - if (state->exit_latency != lp2_exit_latencies[cpu_number(dev->cpu)]) { - /* possible on the 1st entry after cluster switch*/ - state->exit_latency = lp2_exit_latencies[cpu_number(dev->cpu)]; - tegra_pd_update_target_residency(state); - } - if (request < state->target_residency) { - /* Not enough time left to enter LP2 */ - return false; - } - - return true; -} - -static inline void tegra3_lp2_restore_affinity(void) -{ -#ifdef CONFIG_SMP - /* Disable the distributor. */ - tegra_gic_dist_disable(); - - /* Restore the other CPU's interrupt affinity. */ - tegra_gic_restore_affinity(); - - /* Re-enable the distributor. */ - tegra_gic_dist_enable(); -#endif -} - -static bool tegra_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_state *state, s64 request) -{ - ktime_t entry_time; - ktime_t exit_time; - bool sleep_completed = false; - bool multi_cpu_entry = false; - int bin; - s64 sleep_time; - - /* LP2 entry time */ - entry_time = ktime_get(); - - if (request < state->target_residency) { - /* Not enough time left to enter LP2 */ - cpu_do_idle(); - return false; - } - -#ifdef CONFIG_SMP - multi_cpu_entry = !is_lp_cluster() && (num_online_cpus() > 1); - if (multi_cpu_entry) { - s64 wake_time; - unsigned int i; - - /* Disable the distributor -- this is the only way to - prevent the other CPUs from responding to interrupts - and potentially fiddling with the distributor - registers while we're fiddling with them. */ - tegra_gic_dist_disable(); - - /* Did an interrupt come in for another CPU before we - could disable the distributor? */ - if (!tegra_rail_off_is_allowed()) { - /* Yes, re-enable the distributor and clock gating. */ - tegra_gic_dist_enable(); - cpu_do_idle(); - return false; - } - - /* LP2 initial targeted wake time */ - wake_time = ktime_to_us(entry_time) + request; - - /* CPU0 must wake up before any of the other CPUs. */ - smp_rmb(); - for (i = 1; i < CONFIG_NR_CPUS; i++) - wake_time = min_t(s64, wake_time, - tegra_cpu_wake_by_time[i]); - - /* LP2 actual targeted wake time */ - request = wake_time - ktime_to_us(entry_time); - BUG_ON(wake_time < 0LL); - - if (request < state->target_residency) { - /* Not enough time left to enter LP2 */ - tegra_gic_dist_enable(); - cpu_do_idle(); - return false; - } - - /* Cancel LP2 wake timers for all secondary CPUs */ - tegra_pd_timer_cancel_secondary(); - - /* Save and disable the affinity setting for the other - CPUs and route all interrupts to CPU0. */ - tegra_gic_disable_affinity(); - - /* Re-enable the distributor. */ - tegra_gic_dist_enable(); - } -#endif - cpu_pm_enter(); - - sleep_time = request - - lp2_exit_latencies[cpu_number(dev->cpu)]; - - bin = time_to_bin((u32)request / 1000); - idle_stats.tear_down_count[cpu_number(dev->cpu)]++; - idle_stats.lp2_count++; - idle_stats.lp2_count_bin[bin]++; - - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); - if (!is_lp_cluster()) - tegra_dvfs_rail_off(tegra_cpu_rail, entry_time); - - if (tegra_idle_power_down_last(sleep_time, 0) == 0) - sleep_completed = true; - else { - int irq = tegra_gic_pending_interrupt(); - idle_stats.lp2_int_count[irq]++; - } - - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); - exit_time = ktime_get(); - if (!is_lp_cluster()) - tegra_dvfs_rail_on(tegra_cpu_rail, exit_time); - - idle_stats.in_lp2_time[cpu_number(dev->cpu)] += - ktime_to_us(ktime_sub(exit_time, entry_time)); - - if (multi_cpu_entry) - tegra3_lp2_restore_affinity(); - - if (sleep_completed) { - /* - * Stayed in LP2 for the full time until the next tick, - * adjust the exit latency based on measurement - */ - int offset = ktime_to_us(ktime_sub(exit_time, entry_time)) - - request; - int latency = lp2_exit_latencies[cpu_number(dev->cpu)] + - offset / 16; - latency = clamp(latency, 0, 10000); - lp2_exit_latencies[cpu_number(dev->cpu)] = latency; - state->exit_latency = latency; /* for idle governor */ - smp_wmb(); - - idle_stats.lp2_completed_count++; - idle_stats.lp2_completed_count_bin[bin]++; - - pr_debug("%lld %lld %d %d\n", request, - ktime_to_us(ktime_sub(exit_time, entry_time)), - offset, bin); - } - - cpu_pm_exit(); - - return true; -} - -static bool tegra_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_state *state, s64 request) -{ -#ifdef CONFIG_SMP - s64 sleep_time; - ktime_t entry_time; - struct tegra_twd_context twd_context; - bool sleep_completed = false; - struct tick_sched *ts = tick_get_tick_sched(dev->cpu); -#if defined(CONFIG_TEGRA_LP2_CPU_TIMER) - void __iomem *twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); -#endif - - if (!tegra_twd_get_state(&twd_context)) { - unsigned long twd_rate = clk_get_rate(twd_clk); - - if ((twd_context.twd_ctrl & TWD_TIMER_CONTROL_ENABLE) && - (twd_context.twd_ctrl & TWD_TIMER_CONTROL_IT_ENABLE)) { - request = div_u64((u64)twd_context.twd_cnt * 1000000, - twd_rate); -#ifdef CONFIG_TEGRA_LP2_CPU_TIMER - if (request >= state->target_residency) { - twd_context.twd_cnt -= state->exit_latency * - (twd_rate / 1000000); - writel(twd_context.twd_cnt, - twd_base + TWD_TIMER_COUNTER); - } -#endif - } - } - - if (!tegra_is_cpu_wake_timer_ready(dev->cpu) || - (request < state->target_residency) || - (!ts) || (ts->nohz_mode == NOHZ_MODE_INACTIVE)) { - /* - * Not enough time left to enter LP2, or wake timer not ready - */ - cpu_do_idle(); - return false; - } - - cpu_pm_enter(); - -#if !defined(CONFIG_TEGRA_LP2_CPU_TIMER) - sleep_time = request - state->exit_latency; - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); - tegra_twd_suspend(&twd_context); - tegra_pd_set_trigger(sleep_time); -#endif - idle_stats.tear_down_count[cpu_number(dev->cpu)]++; - - entry_time = ktime_get(); - - /* Save time this CPU must be awakened by. */ - tegra_cpu_wake_by_time[dev->cpu] = ktime_to_us(entry_time) + request; - smp_wmb(); - - cpu_suspend(0, tegra3_sleep_cpu_secondary_finish); - - tegra_cpu_wake_by_time[dev->cpu] = LLONG_MAX; - -#ifdef CONFIG_TEGRA_LP2_CPU_TIMER - if (!tegra_twd_get_state(&twd_context)) - sleep_completed = (twd_context.twd_cnt == 0); -#else - sleep_completed = !tegra_pd_timer_remain(); - tegra_pd_set_trigger(0); - tegra_twd_resume(&twd_context); - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); -#endif - sleep_time = ktime_to_us(ktime_sub(ktime_get(), entry_time)); - idle_stats.in_lp2_time[cpu_number(dev->cpu)] += sleep_time; - if (sleep_completed) { - /* - * Stayed in LP2 for the full time until timer expires, - * adjust the exit latency based on measurement - */ - int offset = sleep_time - request; - int latency = lp2_exit_latencies[cpu_number(dev->cpu)] + - offset / 16; - latency = clamp(latency, 0, 10000); - lp2_exit_latencies[cpu_number(dev->cpu)] = latency; - state->exit_latency = latency; /* for idle governor */ - smp_wmb(); - } -#endif - cpu_pm_exit(); - - return true; -} - -bool tegra3_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - s64 request = ktime_to_us(tick_nohz_get_sleep_length()); - bool last_cpu = tegra_set_cpu_in_pd(dev->cpu); - bool entered_lp2; - - if ((dev->cpu == 0) && last_cpu) - entered_lp2 = tegra_cpu_cluster_power_down(dev, state, request); - else if (dev->cpu) - entered_lp2 = tegra_cpu_core_power_down(dev, state, request); - else { - cpu_do_idle(); - entered_lp2 = false; - } - - tegra_clear_cpu_in_pd(dev->cpu); - - return entered_lp2; -} - -#ifdef CONFIG_DEBUG_FS -int tegra3_lp2_debug_show(struct seq_file *s, void *data) -{ - int bin; - int i; - seq_printf(s, " cpu0 cpu1 cpu2 cpu3 cpulp\n"); - seq_printf(s, "-----------------------------------------------------------------------------\n"); - seq_printf(s, "cpu ready: %8u %8u %8u %8u %8u\n", - idle_stats.cpu_ready_count[0], - idle_stats.cpu_ready_count[1], - idle_stats.cpu_ready_count[2], - idle_stats.cpu_ready_count[3], - idle_stats.cpu_ready_count[4]); - seq_printf(s, "tear down: %8u %8u %8u %8u %8u\n", - idle_stats.tear_down_count[0], - idle_stats.tear_down_count[1], - idle_stats.tear_down_count[2], - idle_stats.tear_down_count[3], - idle_stats.tear_down_count[4]); - seq_printf(s, "lp2: %8u\n", idle_stats.lp2_count); - seq_printf(s, "lp2 completed: %8u %7u%%\n", - idle_stats.lp2_completed_count, - idle_stats.lp2_completed_count * 100 / - (idle_stats.lp2_count ?: 1)); - - seq_printf(s, "\n"); - seq_printf(s, "cpu ready time: %8llu %8llu %8llu %8llu %8llu ms\n", - div64_u64(idle_stats.cpu_wants_lp2_time[0], 1000), - div64_u64(idle_stats.cpu_wants_lp2_time[1], 1000), - div64_u64(idle_stats.cpu_wants_lp2_time[2], 1000), - div64_u64(idle_stats.cpu_wants_lp2_time[3], 1000), - div64_u64(idle_stats.cpu_wants_lp2_time[4], 1000)); - - seq_printf(s, "lp2 time: %8llu %8llu %8llu %8llu %8llu ms\n", - div64_u64(idle_stats.in_lp2_time[0], 1000), - div64_u64(idle_stats.in_lp2_time[1], 1000), - div64_u64(idle_stats.in_lp2_time[2], 1000), - div64_u64(idle_stats.in_lp2_time[3], 1000), - div64_u64(idle_stats.in_lp2_time[4], 1000)); - - seq_printf(s, "lp2 %%: %7d%% %7d%% %7d%% %7d%% %7d%%\n", - (int)(idle_stats.cpu_wants_lp2_time[0] ? - div64_u64(idle_stats.in_lp2_time[0] * 100, - idle_stats.cpu_wants_lp2_time[0]) : 0), - (int)(idle_stats.cpu_wants_lp2_time[1] ? - div64_u64(idle_stats.in_lp2_time[1] * 100, - idle_stats.cpu_wants_lp2_time[1]) : 0), - (int)(idle_stats.cpu_wants_lp2_time[2] ? - div64_u64(idle_stats.in_lp2_time[2] * 100, - idle_stats.cpu_wants_lp2_time[2]) : 0), - (int)(idle_stats.cpu_wants_lp2_time[3] ? - div64_u64(idle_stats.in_lp2_time[3] * 100, - idle_stats.cpu_wants_lp2_time[3]) : 0), - (int)(idle_stats.cpu_wants_lp2_time[4] ? - div64_u64(idle_stats.in_lp2_time[4] * 100, - idle_stats.cpu_wants_lp2_time[4]) : 0)); - seq_printf(s, "\n"); - - seq_printf(s, "%19s %8s %8s %8s\n", "", "lp2", "comp", "%"); - seq_printf(s, "-------------------------------------------------\n"); - for (bin = 0; bin < 32; bin++) { - if (idle_stats.lp2_count_bin[bin] == 0) - continue; - seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n", - 1 << (bin - 1), 1 << bin, - idle_stats.lp2_count_bin[bin], - idle_stats.lp2_completed_count_bin[bin], - idle_stats.lp2_completed_count_bin[bin] * 100 / - idle_stats.lp2_count_bin[bin]); - } - - seq_printf(s, "\n"); - seq_printf(s, "%3s %20s %6s %10s\n", - "int", "name", "count", "last count"); - seq_printf(s, "--------------------------------------------\n"); - for (i = 0; i < NR_IRQS; i++) { - if (idle_stats.lp2_int_count[i] == 0) - continue; - seq_printf(s, "%3d %20s %6d %10d\n", - i, irq_to_desc(i)->action ? - irq_to_desc(i)->action->name ?: "???" : "???", - idle_stats.lp2_int_count[i], - idle_stats.lp2_int_count[i] - - idle_stats.last_lp2_int_count[i]); - idle_stats.last_lp2_int_count[i] = idle_stats.lp2_int_count[i]; - }; - return 0; -} -#endif - -int __init tegra3_cpuidle_init_soc(struct tegra_cpuidle_ops *idle_ops) -{ - int i; - struct tegra_cpuidle_ops ops = { - tegra3_idle_lp2, - tegra3_cpu_idle_stats_lp2_ready, - tegra3_cpu_idle_stats_lp2_time, - tegra3_lp2_is_allowed, -#ifdef CONFIG_DEBUG_FS - tegra3_lp2_debug_show -#endif - }; - - cpu_clk_for_dvfs = tegra_get_clock_by_name("cpu_g"); - twd_clk = tegra_get_clock_by_name("twd"); - - for (i = 0; i < ARRAY_SIZE(lp2_exit_latencies); i++) - lp2_exit_latencies[i] = tegra_pg_exit_latency; - - *idle_ops = ops; - - return 0; -} diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index ab166e98117c..6e0dbd61c7d3 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -62,21 +62,6 @@ static void init_chip_specific(void) cid = tegra_get_chipid(); switch (cid) { -#if defined(CONFIG_ARCH_TEGRA_3x_SOC) - case TEGRA_CHIPID_TEGRA3: - tegra_la_get_t3_specific(&cs); - break; -#endif -#if defined(CONFIG_ARCH_TEGRA_11x_SOC) - case TEGRA_CHIPID_TEGRA11: - tegra_la_get_t11x_specific(&cs); - break; -#endif -#if defined(CONFIG_ARCH_TEGRA_14x_SOC) - case TEGRA_CHIPID_TEGRA14: - tegra_la_get_t14x_specific(&cs); - break; -#endif #if defined(CONFIG_ARCH_TEGRA_12x_SOC) case TEGRA_CHIPID_TEGRA12: case TEGRA_CHIPID_TEGRA13: @@ -243,14 +228,6 @@ void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick) cs.scaling_info[i].la_set = la; } spin_unlock(&cs.lock); - -#if defined(CONFIG_ARCH_TEGRA_3x_SOC) - /* Re-scale G2PR, G2SR, G2DR, G2DW with updated ns_per_tick */ - tegra_set_latency_allowance(TEGRA_LA_G2PR, 20); - tegra_set_latency_allowance(TEGRA_LA_G2SR, 20); - tegra_set_latency_allowance(TEGRA_LA_G2DR, 20); - tegra_set_latency_allowance(TEGRA_LA_G2DW, 20); -#endif } } @@ -392,12 +369,6 @@ static int __init tegra_latency_allowance_init(void) la_to_set); } } -#if defined(CONFIG_ARCH_TEGRA_3x_SOC) - tegra_set_latency_allowance(TEGRA_LA_G2PR, 20); - tegra_set_latency_allowance(TEGRA_LA_G2SR, 20); - tegra_set_latency_allowance(TEGRA_LA_G2DR, 20); - tegra_set_latency_allowance(TEGRA_LA_G2DW, 20); -#endif if (cs.init_ptsa) cs.init_ptsa(); diff --git a/arch/arm/mach-tegra/panel-j-720p-4-7.c b/arch/arm/mach-tegra/panel-j-720p-4-7.c deleted file mode 100644 index 56f6195ff868..000000000000 --- a/arch/arm/mach-tegra/panel-j-720p-4-7.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - * arch/arm/mach-tegra/panel-j-720p-4-7.c - * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <mach/dc.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/max8831_backlight.h> -#include <linux/leds.h> -#include <linux/ioport.h> -#include <linux/export.h> - -#include "gpio-names.h" -#include "board-panel.h" -#include "devices.h" - -#define DSI_PANEL_RESET 0 - -#define DC_CTRL_MODE (TEGRA_DC_OUT_ONE_SHOT_MODE | \ - TEGRA_DC_OUT_ONE_SHOT_LP_MODE) - -static struct regulator *vdd_lcd_s_1v8; -static struct regulator *vdd_sys_bl_3v7; -static struct regulator *avdd_lcd_3v0_2v8; - - -static bool dsi_j_720p_4_7_reg_requested; -static bool dsi_j_720p_4_7_gpio_requested; -static bool is_bl_powered; -static struct platform_device *disp_device; - -static struct tegra_dc_sd_settings dsi_j_720p_4_7_sd_settings = { - .enable = 1, /* enabled by default */ - .use_auto_pwm = false, - .hw_update_delay = 0, - .bin_width = -1, - .aggressiveness = 5, - .use_vid_luma = false, - .phase_in_adjustments = 0, - .k_limit_enable = true, - .k_limit = 180, - .sd_window_enable = false, - .soft_clipping_enable = true, - /* Low soft clipping threshold to compensate for aggressive k_limit */ - .soft_clipping_threshold = 128, - .smooth_k_enable = true, - .smooth_k_incr = 4, - /* Default video coefficients */ - .coeff = {5, 9, 2}, - .fc = {0, 0}, - /* Immediate backlight changes */ - .blp = {1024, 255}, - /* Gammas: R: 2.2 G: 2.2 B: 2.2 */ - /* Default BL TF */ - .bltf = { - { - {57, 65, 73, 82}, - {92, 103, 114, 125}, - {138, 150, 164, 178}, - {193, 208, 224, 241}, - }, - }, - /* Default LUT */ - .lut = { - { - {255, 255, 255}, - {199, 199, 199}, - {153, 153, 153}, - {116, 116, 116}, - {85, 85, 85}, - {59, 59, 59}, - {36, 36, 36}, - {17, 17, 17}, - {0, 0, 0}, - }, - }, - .sd_brightness = &sd_brightness, - .use_vpulse2 = true, -}; - -static tegra_dc_bl_output dsi_j_720p_4_7_bl_response_curve = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 18, 19, 20, 21, 22, 23, 25, - 26, 27, 28, 30, 31, 32, 33, 35, - 36, 38, 39, 41, 42, 43, 45, 46, - 48, 49, 51, 52, 54, 55, 57, 58, - 60, 61, 63, 64, 66, 67, 68, 70, - 71, 72, 74, 75, 77, 78, 79, 80, - 81, 82, 83, 85, 86, 87, 88, 89, - 90, 90, 91, 92, 93, 93, 94, 95, - 96, 96, 96, 97, 97, 97, 97, 98, - 98, 98, 98, 99, 100, 101, 101, 102, - 103, 104, 104, 105, 106, 107, 108, 109, - 110, 112, 113, 114, 115, 116, 117, 119, - 120, 121, 122, 123, 125, 126, 127, 128, - 129, 131, 132, 133, 134, 135, 136, 137, - 138, 140, 141, 142, 142, 143, 144, 145, - 146, 147, 148, 149, 149, 150, 151, 152, - 153, 154, 154, 155, 156, 157, 158, 159, - 160, 162, 163, 164, 165, 167, 168, 169, - 170, 171, 172, 173, 173, 174, 175, 176, - 176, 177, 178, 179, 179, 180, 181, 182, - 182, 183, 184, 184, 185, 186, 186, 187, - 188, 188, 189, 189, 190, 190, 191, 192, - 193, 194, 195, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 203, 204, 205, 206, - 207, 208, 209, 210, 211, 212, 213, 213, - 214, 215, 216, 217, 218, 219, 220, 221, - 222, 224, 225, 226, 227, 228, 229, 230, - 231, 232, 233, 234, 235, 236, 237, 238, - 239, 240, 241, 242, 243, 244, 246, 247, - 248, 249, 250, 251, 252, 253, 254, 255 -}; - -static int __maybe_unused dsi_j_720p_4_7_bl_notify(struct device *unused, - int brightness) -{ - int cur_sd_brightness = atomic_read(&sd_brightness); - - /* SD brightness is a percentage */ - brightness = (brightness * cur_sd_brightness) / 255; - - /* Apply any backlight response curve */ - if (brightness > 255) - pr_info("Error: Brightness > 255!\n"); - else - brightness = dsi_j_720p_4_7_bl_response_curve[brightness]; - - return brightness; -} - -static int __maybe_unused dsi_j_720p_4_7_check_fb(struct device *dev, - struct fb_info *info) -{ - return info->device == &disp_device->dev; -} - -/* - JDI uses Platform blacklight device -*/ - -static struct platform_pwm_backlight_data dsi_j_720p_4_7_bl_data = { -#ifdef CONFIG_ARCH_TEGRA_11x_SOC - .pwm_id = 1, -#else - .pwm_id = 0, -#endif - .max_brightness = 255, - .dft_brightness = 77, - .pwm_period_ns = 40000, - .pwm_gpio = TEGRA_GPIO_INVALID, - .notify = dsi_j_720p_4_7_bl_notify, - .check_fb = dsi_j_720p_4_7_check_fb, -}; - -static struct platform_device dsi_j_720p_4_7_bl_device = { - .name = "pwm-backlight", - .id = -1, - .dev = { - .platform_data = &dsi_j_720p_4_7_bl_data, - }, -}; - -static struct tegra_dsi_out dsi_j_720p_4_7_pdata; - -static int dsi_j_720p_4_7_register_bl_dev(void) -{ - int err = 0; - - err = platform_device_register(&dsi_j_720p_4_7_bl_device); - if (err) { - pr_err("disp1 bl device registration failed"); - return err; - } - - err = gpio_request(dsi_j_720p_4_7_pdata.dsi_panel_bl_pwm_gpio, - "panel pwm"); - if (err < 0) { - pr_err("panel backlight pwm gpio request failed\n"); - return err; - } - gpio_free(dsi_j_720p_4_7_pdata.dsi_panel_bl_pwm_gpio); - return err; -} -struct tegra_dc_mode dsi_j_720p_4_7_modes[] = { - { - .pclk = 62625000, - .h_ref_to_sync = 2, - .v_ref_to_sync = 1, - .h_sync_width = 2, - .v_sync_width = 2, - .h_back_porch = 84, - .v_back_porch = 2, - .h_active = 720, - .v_active = 1280, - .h_front_porch = 4, - .v_front_porch = 4, - }, -}; -static int dsi_j_720p_4_7_reg_get(void) -{ - int err = 0; - - if (dsi_j_720p_4_7_reg_requested) - return 0; - - avdd_lcd_3v0_2v8 = regulator_get(NULL, "avdd_lcd"); - if (IS_ERR(avdd_lcd_3v0_2v8)) { - pr_err("avdd_lcd regulator get failed\n"); - err = PTR_ERR(avdd_lcd_3v0_2v8); - avdd_lcd_3v0_2v8 = NULL; - goto fail; - } - - vdd_lcd_s_1v8 = regulator_get(NULL, "vdd_lcd_1v8_s"); - if (IS_ERR(vdd_lcd_s_1v8)) { - pr_err("vdd_lcd_1v8_s regulator get failed\n"); - err = PTR_ERR(vdd_lcd_s_1v8); - vdd_lcd_s_1v8 = NULL; - goto fail; - } - - vdd_sys_bl_3v7 = regulator_get(NULL, "vdd_sys_bl"); - if (IS_ERR(vdd_sys_bl_3v7)) { - pr_err("vdd_sys_bl regulator get failed\n"); - err = PTR_ERR(vdd_sys_bl_3v7); - vdd_sys_bl_3v7 = NULL; - goto fail; - } - - dsi_j_720p_4_7_reg_requested = true; - return 0; -fail: - return err; -} - -static int dsi_j_720p_4_7_gpio_get(void) -{ - int err = 0; - - if (dsi_j_720p_4_7_gpio_requested) - return 0; - - err = gpio_request(dsi_j_720p_4_7_pdata.dsi_panel_rst_gpio, - "panel rst"); - if (err < 0) { - pr_err("panel reset gpio request failed\n"); - goto fail; - } - - err = gpio_request(dsi_j_720p_4_7_pdata.dsi_panel_bl_en_gpio, - "panel backlight"); - if (err < 0) { - pr_err("panel backlight gpio request failed\n"); - goto fail; - } - - - - dsi_j_720p_4_7_gpio_requested = true; - return 0; -fail: - return err; -} - -static int dsi_j_720p_4_7_enable(struct device *dev) -{ - int err = 0; - - err = dsi_j_720p_4_7_reg_get(); - if (err < 0) { - pr_err("dsi regulator get failed\n"); - goto fail; - } - - err = dsi_j_720p_4_7_gpio_get(); - if (err < 0) { - pr_err("dsi gpio request failed\n"); - goto fail; - } - gpio_direction_output(dsi_j_720p_4_7_pdata.dsi_panel_rst_gpio, 0); - - if (avdd_lcd_3v0_2v8) { - err = regulator_enable(avdd_lcd_3v0_2v8); - if (err < 0) { - pr_err("avdd_lcd regulator enable failed\n"); - goto fail; - } - regulator_set_voltage(avdd_lcd_3v0_2v8, 3000000, 3000000); - } - - usleep_range(3000, 5000); - - if (vdd_lcd_s_1v8) { - err = regulator_enable(vdd_lcd_s_1v8); - if (err < 0) { - pr_err("vdd_lcd_1v8_s regulator enable failed\n"); - goto fail; - } - } - usleep_range(3000, 5000); - - if (vdd_sys_bl_3v7) { - err = regulator_enable(vdd_sys_bl_3v7); - if (err < 0) { - pr_err("vdd_sys_bl regulator enable failed\n"); - goto fail; - } - } - usleep_range(3000, 5000); - -#if DSI_PANEL_RESET - gpio_set_value(dsi_j_720p_4_7_pdata.dsi_panel_rst_gpio, 1); - usleep_range(1000, 5000); - gpio_set_value(dsi_j_720p_4_7_pdata.dsi_panel_rst_gpio, 0); - usleep_range(1000, 5000); - gpio_set_value(dsi_j_720p_4_7_pdata.dsi_panel_rst_gpio, 1); - msleep(20); -#endif - - gpio_direction_output(dsi_j_720p_4_7_pdata.dsi_panel_bl_en_gpio, 1); - is_bl_powered = true; - return 0; -fail: - return err; -} - -static struct tegra_dsi_cmd dsi_j_720p_4_7_init_cmd[] = { - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFF, 0xEE), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x26, 0x08), - DSI_DLY_MS(10), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x26, 0x00), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFF, 0x00), - DSI_DLY_MS(15), - DSI_GPIO_SET(0, 1), /* use dummy gpio */ - DSI_DLY_MS(10), - DSI_GPIO_SET(0, 0), /* use dummy gpio */ - DSI_DLY_MS(20), - DSI_GPIO_SET(0, 1), /* use dummy gpio */ - DSI_DLY_MS(100), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xBA, 0x02), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xC2, 0x08), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFF, 0x04), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x09, 0x00), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x0A, 0x00), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFB, 0x01), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFF, 0xEE), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x12, 0x53), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x13, 0x05), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x6A, 0x60), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFB, 0x01), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0xFF, 0x00), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, 0x3A, 0x77), - DSI_DLY_MS(5), - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x00), - DSI_DLY_MS(100), -#if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE) - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_TEARING_EFFECT_ON, 0), -#endif - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x00), - DSI_DLY_MS(150), -}; - -static struct tegra_dsi_out dsi_j_720p_4_7_pdata = { - .n_data_lanes = 3, - - .rated_refresh_rate = 60, - .refresh_rate = 60, - .suspend_aggr = DSI_HOST_SUSPEND_LV2, - .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, - .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_TX_ONLY, - .controller_vs = DSI_VS_1, - .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P, - .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0, - - .panel_reset = DSI_PANEL_RESET, - .power_saving_suspend = true, - .dsi_init_cmd = dsi_j_720p_4_7_init_cmd, - .n_init_cmd = ARRAY_SIZE(dsi_j_720p_4_7_init_cmd), -}; - -static int dsi_j_720p_4_7_disable(void) -{ - gpio_set_value(dsi_j_720p_4_7_pdata.dsi_panel_bl_en_gpio, 0); - is_bl_powered = false; - if (vdd_sys_bl_3v7) - regulator_disable(vdd_sys_bl_3v7); - - if (vdd_lcd_s_1v8) - regulator_disable(vdd_lcd_s_1v8); - - if (avdd_lcd_3v0_2v8) - regulator_disable(avdd_lcd_3v0_2v8); - - return 0; -} - -static void dsi_j_720p_4_7_set_disp_device( - struct platform_device *pluto_display_device) -{ - disp_device = pluto_display_device; -} - -static void dsi_j_720p_4_7_dc_out_init(struct tegra_dc_out *dc) -{ - dc->dsi = &dsi_j_720p_4_7_pdata; - dc->parent_clk = "pll_d_out0"; - dc->modes = dsi_j_720p_4_7_modes; - dc->n_modes = ARRAY_SIZE(dsi_j_720p_4_7_modes); - dc->enable = dsi_j_720p_4_7_enable; - dc->disable = dsi_j_720p_4_7_disable; - dc->width = 58; - dc->height = 103; - dc->flags = DC_CTRL_MODE; -} -static void dsi_j_720p_4_7_fb_data_init(struct tegra_fb_data *fb) -{ - fb->xres = dsi_j_720p_4_7_modes[0].h_active; - fb->yres = dsi_j_720p_4_7_modes[0].v_active; -} - -static void dsi_j_720p_4_7_sd_settings_init -(struct tegra_dc_sd_settings *settings) -{ - *settings = dsi_j_720p_4_7_sd_settings; - settings->bl_device_name = "pwm-backlight"; -} - - -struct tegra_panel __initdata dsi_j_720p_4_7 = { - .init_sd_settings = dsi_j_720p_4_7_sd_settings_init, - .init_dc_out = dsi_j_720p_4_7_dc_out_init, - .init_fb_data = dsi_j_720p_4_7_fb_data_init, - .set_disp_device = dsi_j_720p_4_7_set_disp_device, - .register_bl_dev = dsi_j_720p_4_7_register_bl_dev, -}; -EXPORT_SYMBOL(dsi_j_720p_4_7); diff --git a/arch/arm/mach-tegra/panel-l-720p-5.c b/arch/arm/mach-tegra/panel-l-720p-5.c deleted file mode 100644 index aa967ee1fbe9..000000000000 --- a/arch/arm/mach-tegra/panel-l-720p-5.c +++ /dev/null @@ -1,822 +0,0 @@ -/* - * arch/arm/mach-tegra/panel-l-720p-5.c - * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <mach/dc.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/mfd/max8831.h> -#include <linux/max8831_backlight.h> -#include <linux/leds.h> -#include <linux/ioport.h> -#include <linux/lm3528.h> -#include <linux/export.h> - -#include "gpio-names.h" -#include "board-panel.h" -#include "board.h" - -#define DSI_PANEL_RESET 1 - -#define DC_CTRL_MODE TEGRA_DC_OUT_CONTINUOUS_MODE - -static struct regulator *vdd_lcd_s_1v8; -static struct regulator *vdd_sys_bl_3v7; -static struct regulator *avdd_lcd_3v0_2v8; - -static bool dsi_l_720p_5_reg_requested; -static bool dsi_l_720p_5_gpio_requested; -static bool is_bl_powered; - -static struct tegra_dc_sd_settings dsi_l_720p_5_sd_settings = { - .enable = 1, /* enabled by default */ - .use_auto_pwm = false, - .hw_update_delay = 0, - .bin_width = -1, - .aggressiveness = 5, - .use_vid_luma = false, - .phase_in_adjustments = 0, - .k_limit_enable = true, - .k_limit = 180, - .sd_window_enable = false, - .soft_clipping_enable = true, - /* Low soft clipping threshold to compensate for aggressive k_limit */ - .soft_clipping_threshold = 128, - .smooth_k_enable = true, - .smooth_k_incr = 4, - /* Default video coefficients */ - .coeff = {5, 9, 2}, - .fc = {0, 0}, - /* Immediate backlight changes */ - .blp = {1024, 255}, - /* Gammas: R: 2.2 G: 2.2 B: 2.2 */ - /* Default BL TF */ - .bltf = { - { - {57, 65, 73, 82}, - {92, 103, 114, 125}, - {138, 150, 164, 178}, - {193, 208, 224, 241}, - }, - }, - /* Default LUT */ - .lut = { - { - {255, 255, 255}, - {199, 199, 199}, - {153, 153, 153}, - {116, 116, 116}, - {85, 85, 85}, - {59, 59, 59}, - {36, 36, 36}, - {17, 17, 17}, - {0, 0, 0}, - }, - }, - .sd_brightness = &sd_brightness, - .use_vpulse2 = true, -}; - -#ifdef CONFIG_TEGRA_DC_CMU -static struct tegra_dc_cmu dsi_l_720p_5_cmu = { - /* lut1 maps sRGB to linear space. */ - { - 0, 1, 2, 4, 5, 6, 7, 9, - 10, 11, 12, 14, 15, 16, 18, 20, - 21, 23, 25, 27, 29, 31, 33, 35, - 37, 40, 42, 45, 48, 50, 53, 56, - 59, 62, 66, 69, 72, 76, 79, 83, - 87, 91, 95, 99, 103, 107, 112, 116, - 121, 126, 131, 136, 141, 146, 151, 156, - 162, 168, 173, 179, 185, 191, 197, 204, - 210, 216, 223, 230, 237, 244, 251, 258, - 265, 273, 280, 288, 296, 304, 312, 320, - 329, 337, 346, 354, 363, 372, 381, 390, - 400, 409, 419, 428, 438, 448, 458, 469, - 479, 490, 500, 511, 522, 533, 544, 555, - 567, 578, 590, 602, 614, 626, 639, 651, - 664, 676, 689, 702, 715, 728, 742, 755, - 769, 783, 797, 811, 825, 840, 854, 869, - 884, 899, 914, 929, 945, 960, 976, 992, - 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125, - 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267, - 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420, - 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582, - 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755, - 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939, - 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133, - 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339, - 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555, - 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783, - 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022, - 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272, - 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535, - 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809, - 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095, - }, - /* csc */ - { - 0x10D, 0x3F3, 0x000, /* 1.05036053 -0.05066457 0.00030404 */ - 0x000, 0x0FC, 0x003, /* -0.00012137 0.98659651 0.01352485 */ - 0x002, 0x001, 0x0FC, /* 0.00722989 0.00559134 0.98717878 */ - }, - /* lut2 maps linear space to sRGB */ - { - 0, 1, 2, 2, 3, 4, 5, 6, - 6, 7, 8, 9, 10, 10, 11, 12, - 13, 13, 14, 15, 15, 16, 16, 17, - 18, 18, 19, 19, 20, 20, 21, 21, - 22, 22, 23, 23, 23, 24, 24, 25, - 25, 25, 26, 26, 27, 27, 27, 28, - 28, 29, 29, 29, 30, 30, 30, 31, - 31, 31, 32, 32, 32, 33, 33, 33, - 34, 34, 34, 34, 35, 35, 35, 36, - 36, 36, 37, 37, 37, 37, 38, 38, - 38, 38, 39, 39, 39, 40, 40, 40, - 40, 41, 41, 41, 41, 42, 42, 42, - 42, 43, 43, 43, 43, 43, 44, 44, - 44, 44, 45, 45, 45, 45, 46, 46, - 46, 46, 46, 47, 47, 47, 47, 48, - 48, 48, 48, 48, 49, 49, 49, 49, - 49, 50, 50, 50, 50, 50, 51, 51, - 51, 51, 51, 52, 52, 52, 52, 52, - 53, 53, 53, 53, 53, 54, 54, 54, - 54, 54, 55, 55, 55, 55, 55, 55, - 56, 56, 56, 56, 56, 57, 57, 57, - 57, 57, 57, 58, 58, 58, 58, 58, - 58, 59, 59, 59, 59, 59, 59, 60, - 60, 60, 60, 60, 60, 61, 61, 61, - 61, 61, 61, 62, 62, 62, 62, 62, - 62, 63, 63, 63, 63, 63, 63, 64, - 64, 64, 64, 64, 64, 64, 65, 65, - 65, 65, 65, 65, 66, 66, 66, 66, - 66, 66, 66, 67, 67, 67, 67, 67, - 67, 67, 68, 68, 68, 68, 68, 68, - 68, 69, 69, 69, 69, 69, 69, 69, - 70, 70, 70, 70, 70, 70, 70, 71, - 71, 71, 71, 71, 71, 71, 72, 72, - 72, 72, 72, 72, 72, 72, 73, 73, - 73, 73, 73, 73, 73, 74, 74, 74, - 74, 74, 74, 74, 74, 75, 75, 75, - 75, 75, 75, 75, 75, 76, 76, 76, - 76, 76, 76, 76, 77, 77, 77, 77, - 77, 77, 77, 77, 78, 78, 78, 78, - 78, 78, 78, 78, 78, 79, 79, 79, - 79, 79, 79, 79, 79, 80, 80, 80, - 80, 80, 80, 80, 80, 81, 81, 81, - 81, 81, 81, 81, 81, 81, 82, 82, - 82, 82, 82, 82, 82, 82, 83, 83, - 83, 83, 83, 83, 83, 83, 83, 84, - 84, 84, 84, 84, 84, 84, 84, 84, - 85, 85, 85, 85, 85, 85, 85, 85, - 85, 86, 86, 86, 86, 86, 86, 86, - 86, 86, 87, 87, 87, 87, 87, 87, - 87, 87, 87, 88, 88, 88, 88, 88, - 88, 88, 88, 88, 88, 89, 89, 89, - 89, 89, 89, 89, 89, 89, 90, 90, - 90, 90, 90, 90, 90, 90, 90, 90, - 91, 91, 91, 91, 91, 91, 91, 91, - 91, 91, 92, 92, 92, 92, 92, 92, - 92, 92, 92, 92, 93, 93, 93, 93, - 93, 93, 93, 93, 93, 93, 94, 94, - 94, 94, 94, 94, 94, 94, 94, 94, - 95, 95, 95, 95, 95, 95, 95, 95, - 95, 95, 96, 96, 96, 96, 96, 96, - 96, 96, 96, 96, 96, 97, 97, 97, - 97, 97, 97, 97, 97, 97, 97, 98, - 98, 98, 98, 98, 98, 98, 98, 98, - 98, 98, 99, 99, 99, 99, 99, 99, - 99, 100, 101, 101, 102, 103, 103, 104, - 105, 105, 106, 107, 107, 108, 109, 109, - 110, 111, 111, 112, 113, 113, 114, 115, - 115, 116, 116, 117, 118, 118, 119, 119, - 120, 120, 121, 122, 122, 123, 123, 124, - 124, 125, 126, 126, 127, 127, 128, 128, - 129, 129, 130, 130, 131, 131, 132, 132, - 133, 133, 134, 134, 135, 135, 136, 136, - 137, 137, 138, 138, 139, 139, 140, 140, - 141, 141, 142, 142, 143, 143, 144, 144, - 145, 145, 145, 146, 146, 147, 147, 148, - 148, 149, 149, 150, 150, 150, 151, 151, - 152, 152, 153, 153, 153, 154, 154, 155, - 155, 156, 156, 156, 157, 157, 158, 158, - 158, 159, 159, 160, 160, 160, 161, 161, - 162, 162, 162, 163, 163, 164, 164, 164, - 165, 165, 166, 166, 166, 167, 167, 167, - 168, 168, 169, 169, 169, 170, 170, 170, - 171, 171, 172, 172, 172, 173, 173, 173, - 174, 174, 174, 175, 175, 176, 176, 176, - 177, 177, 177, 178, 178, 178, 179, 179, - 179, 180, 180, 180, 181, 181, 182, 182, - 182, 183, 183, 183, 184, 184, 184, 185, - 185, 185, 186, 186, 186, 187, 187, 187, - 188, 188, 188, 189, 189, 189, 189, 190, - 190, 190, 191, 191, 191, 192, 192, 192, - 193, 193, 193, 194, 194, 194, 195, 195, - 195, 196, 196, 196, 196, 197, 197, 197, - 198, 198, 198, 199, 199, 199, 200, 200, - 200, 200, 201, 201, 201, 202, 202, 202, - 202, 203, 203, 203, 204, 204, 204, 205, - 205, 205, 205, 206, 206, 206, 207, 207, - 207, 207, 208, 208, 208, 209, 209, 209, - 209, 210, 210, 210, 211, 211, 211, 211, - 212, 212, 212, 213, 213, 213, 213, 214, - 214, 214, 214, 215, 215, 215, 216, 216, - 216, 216, 217, 217, 217, 217, 218, 218, - 218, 219, 219, 219, 219, 220, 220, 220, - 220, 221, 221, 221, 221, 222, 222, 222, - 223, 223, 223, 223, 224, 224, 224, 224, - 225, 225, 225, 225, 226, 226, 226, 226, - 227, 227, 227, 227, 228, 228, 228, 228, - 229, 229, 229, 229, 230, 230, 230, 230, - 231, 231, 231, 231, 232, 232, 232, 232, - 233, 233, 233, 233, 234, 234, 234, 234, - 235, 235, 235, 235, 236, 236, 236, 236, - 237, 237, 237, 237, 238, 238, 238, 238, - 239, 239, 239, 239, 240, 240, 240, 240, - 240, 241, 241, 241, 241, 242, 242, 242, - 242, 243, 243, 243, 243, 244, 244, 244, - 244, 244, 245, 245, 245, 245, 246, 246, - 246, 246, 247, 247, 247, 247, 247, 248, - 248, 248, 248, 249, 249, 249, 249, 249, - 250, 250, 250, 250, 251, 251, 251, 251, - 251, 252, 252, 252, 252, 253, 253, 253, - 253, 253, 254, 254, 254, 254, 255, 255, - }, -}; -#endif - -static tegra_dc_bl_output dsi_l_720p_5_max8831_bl_response_curve = { - 0, 1, 3, 5, 7, 9, 11, 13, - 15, 17, 19, 21, 22, 23, 25, 26, - 28, 29, 30, 32, 33, 34, 36, 37, - 39, 40, 42, 43, 45, 46, 48, 49, - 50, 51, 52, 53, 54, 55, 56, 57, - 58, 59, 60, 61, 62, 63, 64, 65, - 66, 67, 68, 70, 71, 72, 73, 74, - 75, 77, 78, 79, 80, 81, 82, 83, - 84, 85, 86, 87, 88, 89, 90, 91, - 92, 93, 94, 95, 96, 97, 98, 99, - 100, 101, 101, 102, 102, 103, 103, 104, - 105, 105, 106, 107, 108, 108, 109, 110, - 111, 112, 113, 114, 115, 116, 117, 118, - 119, 120, 121, 121, 122, 123, 124, 125, - 126, 127, 128, 129, 130, 131, 132, 133, - 134, 135, 135, 136, 137, 138, 139, 140, - 141, 142, 143, 144, 145, 146, 147, 148, - 149, 150, 151, 152, 153, 154, 155, 156, - 156, 157, 158, 159, 160, 161, 162, 162, - 163, 163, 164, 164, 165, 165, 166, 167, - 167, 168, 169, 170, 171, 172, 173, 173, - 174, 175, 176, 177, 178, 179, 180, 181, - 182, 183, 184, 185, 186, 187, 188, 188, - 189, 190, 191, 192, 193, 194, 194, 195, - 196, 197, 198, 199, 200, 201, 202, 203, - 204, 204, 205, 206, 206, 207, 207, 208, - 209, 209, 210, 211, 212, 213, 214, 215, - 216, 217, 218, 219, 220, 221, 222, 223, - 223, 224, 225, 226, 227, 228, 229, 230, - 231, 232, 233, 234, 235, 236, 237, 238, - 239, 240, 241, 242, 243, 244, 245, 246, - 247, 247, 248, 250, 251, 252, 253, 255 -}; - -static tegra_dc_bl_output dsi_l_720p_5_lm3528_bl_response_curve = { - 1, 33, 61, 77, 88, 97, 105, 111, - 116, 121, 125, 129, 132, 136, 139, 141, - 144, 146, 149, 151, 153, 155, 157, 158, - 160, 162, 163, 165, 166, 168, 169, 170, - 172, 173, 174, 175, 176, 177, 178, 180, - 181, 182, 182, 183, 184, 185, 186, 187, - 188, 189, 189, 190, 191, 192, 193, 193, - 194, 195, 195, 196, 197, 197, 198, 199, - 199, 200, 201, 201, 202, 202, 203, 203, - 204, 205, 205, 206, 206, 207, 207, 208, - 208, 209, 209, 210, 210, 211, 211, 212, - 212, 212, 213, 213, 214, 214, 215, 215, - 216, 216, 216, 217, 217, 218, 218, 218, - 219, 219, 219, 220, 220, 221, 221, 221, - 222, 222, 222, 223, 223, 223, 224, 224, - 224, 225, 225, 225, 226, 226, 226, 227, - 227, 227, 228, 228, 228, 229, 229, 229, - 229, 230, 230, 230, 231, 231, 231, 231, - 232, 232, 232, 233, 233, 233, 233, 234, - 234, 234, 234, 235, 235, 235, 235, 236, - 236, 236, 236, 237, 237, 237, 237, 238, - 238, 238, 238, 239, 239, 239, 239, 240, - 240, 240, 240, 240, 241, 241, 241, 241, - 242, 242, 242, 242, 242, 243, 243, 243, - 243, 243, 244, 244, 244, 244, 244, 245, - 245, 245, 245, 245, 246, 246, 246, 246, - 246, 247, 247, 247, 247, 247, 248, 248, - 248, 248, 248, 248, 249, 249, 249, 249, - 249, 250, 250, 250, 250, 250, 250, 251, - 251, 251, 251, 251, 251, 252, 252, 252, - 252, 252, 252, 253, 253, 253, 253, 253, - 253, 254, 254, 254, 254, 254, 254, 255 -}; - -static p_tegra_dc_bl_output dsi_l_720p_5_bl_response_curve; - -static int __maybe_unused dsi_l_720p_5_bl_notify(struct device *unused, - int brightness) -{ - int cur_sd_brightness = atomic_read(&sd_brightness); - - /* SD brightness is a percentage */ - brightness = (brightness * cur_sd_brightness) / 255; - - /* Apply any backlight response curve */ - if (brightness > 255) - pr_info("Error: Brightness > 255!\n"); - else - brightness = dsi_l_720p_5_bl_response_curve[brightness]; - - return brightness; -} -static bool __maybe_unused dsi_l_720p_5_check_bl_power(void) -{ - return is_bl_powered; -} - -/* - LG uses I2C max8831 blacklight device -*/ -static struct led_info dsi_l_720p_5_max8831_leds[] = { - [MAX8831_ID_LED3] = { - .name = "max8831:red:pluto", - }, - [MAX8831_ID_LED4] = { - .name = "max8831:green:pluto", - }, - [MAX8831_ID_LED5] = { - .name = "max8831:blue:pluto", - }, -}; - -static struct platform_max8831_backlight_data dsi_l_720p_5_max8831_bl_data = { - .id = -1, - .name = "pluto_display_bl", - .max_brightness = MAX8831_BL_LEDS_MAX_CURR, - .dft_brightness = 100, - .notify = dsi_l_720p_5_bl_notify, - .is_powered = dsi_l_720p_5_check_bl_power, -}; - -static struct max8831_subdev_info dsi_l_720p_5_max8831_subdevs[] = { - { - .id = MAX8831_ID_LED3, - .name = "max8831_led_bl", - .platform_data = &dsi_l_720p_5_max8831_leds[MAX8831_ID_LED3], - .pdata_size = sizeof( - dsi_l_720p_5_max8831_leds[MAX8831_ID_LED3]), - }, { - .id = MAX8831_ID_LED4, - .name = "max8831_led_bl", - .platform_data = &dsi_l_720p_5_max8831_leds[MAX8831_ID_LED4], - .pdata_size = sizeof( - dsi_l_720p_5_max8831_leds[MAX8831_ID_LED4]), - }, { - .id = MAX8831_ID_LED5, - .name = "max8831_led_bl", - .platform_data = &dsi_l_720p_5_max8831_leds[MAX8831_ID_LED5], - .pdata_size = sizeof( - dsi_l_720p_5_max8831_leds[MAX8831_ID_LED5]), - }, { - .id = MAX8831_BL_LEDS, - .name = "max8831_display_bl", - .platform_data = &dsi_l_720p_5_max8831_bl_data, - .pdata_size = sizeof(dsi_l_720p_5_max8831_bl_data), - }, -}; - -static struct max8831_platform_data dsi_l_720p_5_max8831 = { - .num_subdevs = ARRAY_SIZE(dsi_l_720p_5_max8831_subdevs), - .subdevs = dsi_l_720p_5_max8831_subdevs, -}; - -static struct i2c_board_info dsi_l_720p_5_i2c_led_info = { - .type = "max8831", - .addr = 0x4d, - .platform_data = &dsi_l_720p_5_max8831, -}; - -static struct lm3528_platform_data lm3528_pdata = { - .dft_brightness = 100, - .is_powered = dsi_l_720p_5_check_bl_power, - .notify = dsi_l_720p_5_bl_notify, -}; - -static struct i2c_board_info lm3528_dsi_l_720p_5_i2c_led_info = { - .type = "lm3528_display_bl", - .addr = 0x36, - .platform_data = &lm3528_pdata, -}; - -static int __init dsi_l_720p_5_register_bl_dev(void) -{ - struct i2c_board_info *bl_info; - struct board_info board_info; - tegra_get_board_info(&board_info); - - switch (board_info.board_id) { - case BOARD_E1670: /* Atlantis ERS */ - case BOARD_E1671: /* Atlantis POP Socket */ - bl_info = &lm3528_dsi_l_720p_5_i2c_led_info; - dsi_l_720p_5_bl_response_curve = - dsi_l_720p_5_lm3528_bl_response_curve; - break; - case BOARD_E1680: /* Ceres ERS */ - case BOARD_E1681: /* Ceres DSC Socket */ - bl_info = &dsi_l_720p_5_i2c_led_info; - dsi_l_720p_5_bl_response_curve = - dsi_l_720p_5_max8831_bl_response_curve; - break; - case BOARD_E1580: /* Pluto */ - /* fall through */ - default: - bl_info = &dsi_l_720p_5_i2c_led_info; - dsi_l_720p_5_bl_response_curve = - dsi_l_720p_5_max8831_bl_response_curve; - break; - } - - return i2c_register_board_info(1, bl_info, 1); -} - -struct tegra_dc_mode dsi_l_720p_5_modes[] = { - { - .pclk = 66700000, - .h_ref_to_sync = 4, - .v_ref_to_sync = 1, - .h_sync_width = 4, - .v_sync_width = 4, - .h_back_porch = 112, - .v_back_porch = 7, - .h_active = 720, - .v_active = 1280, - .h_front_porch = 12, - .v_front_porch = 20, - }, -}; -static int dsi_l_720p_5_reg_get(void) -{ - int err = 0; - - if (dsi_l_720p_5_reg_requested) - return 0; - - avdd_lcd_3v0_2v8 = regulator_get(NULL, "avdd_lcd"); - - if (IS_ERR(avdd_lcd_3v0_2v8)) { - pr_err("avdd_lcd regulator get failed\n"); - err = PTR_ERR(avdd_lcd_3v0_2v8); - avdd_lcd_3v0_2v8 = NULL; - goto fail; - } - - vdd_lcd_s_1v8 = regulator_get(NULL, "vdd_lcd_1v8_s"); - if (IS_ERR(vdd_lcd_s_1v8)) { - pr_err("vdd_lcd_1v8_s regulator get failed\n"); - err = PTR_ERR(vdd_lcd_s_1v8); - vdd_lcd_s_1v8 = NULL; - goto fail; - } - - vdd_sys_bl_3v7 = regulator_get(NULL, "vdd_sys_bl"); - if (IS_ERR(vdd_sys_bl_3v7)) { - pr_err("vdd_sys_bl regulator get failed\n"); - err = PTR_ERR(vdd_sys_bl_3v7); - vdd_sys_bl_3v7 = NULL; - goto fail; - } - - dsi_l_720p_5_reg_requested = true; - return 0; -fail: - return err; -} - -static struct tegra_dsi_out dsi_l_720p_5_pdata; -static int dsi_l_720p_5_gpio_get(void) -{ - int err = 0; - - if (dsi_l_720p_5_gpio_requested) - return 0; - - err = gpio_request(dsi_l_720p_5_pdata.dsi_panel_rst_gpio, - "panel rst"); - if (err < 0) { - pr_err("panel reset gpio request failed\n"); - goto fail; - } - - err = gpio_request(dsi_l_720p_5_pdata.dsi_panel_bl_en_gpio, - "panel backlight"); - if (err < 0) { - pr_err("panel backlight gpio request failed\n"); - goto fail; - } - - err = gpio_request(dsi_l_720p_5_pdata.dsi_panel_bl_pwm_gpio, - "panel pwm"); - if (err < 0) { - pr_err("panel backlight pwm gpio request failed\n"); - goto fail; - } - - dsi_l_720p_5_gpio_requested = true; - return 0; -fail: - return err; -} - -static int dsi_l_720p_5_enable(struct device *dev) -{ - int err = 0; - - err = dsi_l_720p_5_reg_get(); - if (err < 0) { - pr_err("dsi regulator get failed\n"); - goto fail; - } - - err = tegra_panel_gpio_get_dt("lg,720p-5", &panel_of); - if (err < 0) { - /* try to request gpios from board file */ - err = dsi_l_720p_5_gpio_get(); - if (err < 0) { - pr_err("dsi gpio request failed\n"); - goto fail; - } - } - - if (gpio_is_valid(panel_of.panel_gpio[TEGRA_GPIO_RESET])) - gpio_direction_output( - panel_of.panel_gpio[TEGRA_GPIO_RESET], 0); - else - gpio_direction_output( - dsi_l_720p_5_pdata.dsi_panel_rst_gpio, 0); - - if (avdd_lcd_3v0_2v8) { - err = regulator_enable(avdd_lcd_3v0_2v8); - if (err < 0) { - pr_err("avdd_lcd regulator enable failed\n"); - goto fail; - } - regulator_set_voltage(avdd_lcd_3v0_2v8, 2800000, 2800000); - } - - usleep_range(3000, 5000); - - if (vdd_lcd_s_1v8) { - err = regulator_enable(vdd_lcd_s_1v8); - if (err < 0) { - pr_err("vdd_lcd_1v8_s regulator enable failed\n"); - goto fail; - } - } - usleep_range(3000, 5000); - - if (vdd_sys_bl_3v7) { - err = regulator_enable(vdd_sys_bl_3v7); - if (err < 0) { - pr_err("vdd_sys_bl regulator enable failed\n"); - goto fail; - } - } - usleep_range(3000, 5000); - -#if DSI_PANEL_RESET - err = tegra_panel_reset(&panel_of, 20); - if (err < 0) { - /* use platform data */ - gpio_set_value(dsi_l_720p_5_pdata.dsi_panel_rst_gpio, 1); - usleep_range(1000, 5000); - gpio_set_value(dsi_l_720p_5_pdata.dsi_panel_rst_gpio, 0); - usleep_range(1000, 5000); - gpio_set_value(dsi_l_720p_5_pdata.dsi_panel_rst_gpio, 1); - msleep(20); - } -#endif - if (gpio_is_valid(panel_of.panel_gpio[TEGRA_GPIO_BL_ENABLE])) - gpio_direction_output( - panel_of.panel_gpio[TEGRA_GPIO_BL_ENABLE], 1); - else - gpio_direction_output( - dsi_l_720p_5_pdata.dsi_panel_bl_en_gpio, 1); - - is_bl_powered = true; - return 0; -fail: - return err; -} - -static u8 panel_dsi_config[] = {0xe0, 0x43, 0x0, 0x80, 0x0, 0x0}; -static u8 panel_disp_ctrl1[] = {0xb5, 0x34, 0x20, 0x40, 0x0, 0x20}; -static u8 panel_disp_ctrl2[] = {0xb6, 0x04, 0x74, 0x0f, 0x16, 0x13}; -static u8 panel_internal_clk[] = {0xc0, 0x01, 0x08}; -static u8 panel_pwr_ctrl3[] = { - 0xc3, 0x0, 0x09, 0x10, 0x02, 0x0, 0x66, 0x20, 0x13, 0x0}; -static u8 panel_pwr_ctrl4[] = {0xc4, 0x23, 0x24, 0x17, 0x17, 0x59}; -static u8 panel_positive_gamma_red[] = { - 0xd0, 0x21, 0x13, 0x67, 0x37, 0x0c, 0x06, 0x62, 0x23, 0x03}; -static u8 panel_negetive_gamma_red[] = { - 0xd1, 0x32, 0x13, 0x66, 0x37, 0x02, 0x06, 0x62, 0x23, 0x03}; -static u8 panel_positive_gamma_green[] = { - 0xd2, 0x41, 0x14, 0x56, 0x37, 0x0c, 0x06, 0x62, 0x23, 0x03}; -static u8 panel_negetive_gamma_green[] = { - 0xd3, 0x52, 0x14, 0x55, 0x37, 0x02, 0x06, 0x62, 0x23, 0x03}; -static u8 panel_positive_gamma_blue[] = { - 0xd4, 0x41, 0x14, 0x56, 0x37, 0x0c, 0x06, 0x62, 0x23, 0x03}; -static u8 panel_negetive_gamma_blue[] = { - 0xd5, 0x52, 0x14, 0x55, 0x37, 0x02, 0x06, 0x62, 0x23, 0x03}; -static u8 panel_ce2[] = {0x71, 0x0, 0x0, 0x01, 0x01}; -static u8 panel_ce3[] = {0x72, 0x01, 0x0e}; -static u8 panel_ce4[] = {0x73, 0x34, 0x52, 0x0}; -static u8 panel_ce5[] = {0x74, 0x05, 0x0, 0x06}; -static u8 panel_ce6[] = {0x75, 0x03, 0x0, 0x07}; -static u8 panel_ce7[] = {0x76, 0x07, 0x0, 0x06}; -static u8 panel_ce8[] = {0x77, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f}; -static u8 panel_ce9[] = {0x78, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; -static u8 panel_ce10[] = { - 0x79, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; -static u8 panel_ce11[] = {0x7a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; -static u8 panel_ce12[] = {0x7b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; -static u8 panel_ce13[] = {0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - -static struct tegra_dsi_cmd dsi_l_720p_5_init_cmd[] = { - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_dsi_config), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl1), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl2), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal_clk), - - /* panel power control 1 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x0), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl3), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl4), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_red), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_red), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_green), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_green), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_blue), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_blue), - - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_ADDR_MODE, 0x08), - - /* panel OTP 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x0), - - /* panel CE 1 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x70, 0x0), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce2), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce3), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce4), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce5), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce6), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce7), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce8), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce9), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce10), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce11), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce12), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce13), - - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x02), - DSI_DLY_MS(15), - - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x06), - DSI_DLY_MS(15), - - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x4e), - DSI_DLY_MS(85), - - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0), - DSI_DLY_MS(15), - - /* panel OTP 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x80), - DSI_DLY_MS(15), - - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0), -}; - -static struct tegra_dsi_out dsi_l_720p_5_pdata = { - .n_data_lanes = 4, - - .refresh_rate = 60, - .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, - .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS, - .video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END, - - .controller_vs = DSI_VS_1, - .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P, - .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0, - - .panel_reset = DSI_PANEL_RESET, - .power_saving_suspend = true, - .dsi_init_cmd = dsi_l_720p_5_init_cmd, - .n_init_cmd = ARRAY_SIZE(dsi_l_720p_5_init_cmd), -}; - -static int dsi_l_720p_5_disable(void) -{ - if (gpio_is_valid(panel_of.panel_gpio[TEGRA_GPIO_BL_ENABLE])) - gpio_direction_output( - panel_of.panel_gpio[TEGRA_GPIO_BL_ENABLE], 0); - else - gpio_direction_output( - dsi_l_720p_5_pdata.dsi_panel_bl_en_gpio, 0); - - is_bl_powered = false; - - if (gpio_is_valid(panel_of.panel_gpio[TEGRA_GPIO_RESET])) - gpio_direction_output( - panel_of.panel_gpio[TEGRA_GPIO_RESET], 0); - else - gpio_direction_output( - dsi_l_720p_5_pdata.dsi_panel_rst_gpio, 0); - - if (vdd_sys_bl_3v7) - regulator_disable(vdd_sys_bl_3v7); - - if (vdd_lcd_s_1v8) - regulator_disable(vdd_lcd_s_1v8); - - if (avdd_lcd_3v0_2v8) - regulator_disable(avdd_lcd_3v0_2v8); - - return 0; -} - -static void dsi_l_720p_5_dc_out_init(struct tegra_dc_out *dc) -{ - dc->dsi = &dsi_l_720p_5_pdata; - dc->parent_clk = "pll_d_out0"; - dc->modes = dsi_l_720p_5_modes; - dc->n_modes = ARRAY_SIZE(dsi_l_720p_5_modes); - dc->enable = dsi_l_720p_5_enable; - dc->disable = dsi_l_720p_5_disable; - dc->width = 62; - dc->height = 110; - dc->flags = DC_CTRL_MODE; -} -static void dsi_l_720p_5_fb_data_init(struct tegra_fb_data *fb) -{ - fb->xres = dsi_l_720p_5_modes[0].h_active; - fb->yres = dsi_l_720p_5_modes[0].v_active; -} - -static void dsi_l_720p_5_sd_settings_init(struct tegra_dc_sd_settings *settings) -{ - struct board_info bi; - tegra_get_display_board_info(&bi); - - *settings = dsi_l_720p_5_sd_settings; - - if (bi.board_id == BOARD_E1563) - settings->bl_device_name = "lm3528_display_bl"; - else - settings->bl_device_name = "max8831_display_bl"; -} - -#ifdef CONFIG_TEGRA_DC_CMU -static void dsi_l_720p_5_cmu_init(struct tegra_dc_platform_data *pdata) -{ - pdata->cmu = &dsi_l_720p_5_cmu; -} -#endif - -struct tegra_panel __initdata dsi_l_720p_5 = { - .init_sd_settings = dsi_l_720p_5_sd_settings_init, - .init_dc_out = dsi_l_720p_5_dc_out_init, - .init_fb_data = dsi_l_720p_5_fb_data_init, - .register_bl_dev = dsi_l_720p_5_register_bl_dev, -#ifdef CONFIG_TEGRA_DC_CMU - .init_cmu_data = dsi_l_720p_5_cmu_init, -#endif -}; -EXPORT_SYMBOL(dsi_l_720p_5); diff --git a/arch/arm/mach-tegra/panel-p-wuxga-10-1.c b/arch/arm/mach-tegra/panel-p-wuxga-10-1.c index fb34711fc9a9..cb77f4720229 100644 --- a/arch/arm/mach-tegra/panel-p-wuxga-10-1.c +++ b/arch/arm/mach-tegra/panel-p-wuxga-10-1.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/panel-p-wuxga-10-1.c * - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,8 +27,6 @@ #include <linux/ioport.h> #include <linux/export.h> -#include <generated/mach-types.h> - #include "board.h" #include "board-panel.h" #include "devices.h" @@ -263,69 +261,11 @@ fail: return err; } -static int macallan_dsi_regulator_get(struct device *dev) -{ - int err = 0; - - if (reg_requested) - return 0; - avdd_lcd_3v3 = regulator_get(dev, "avdd_lcd"); - if (IS_ERR(avdd_lcd_3v3)) { - pr_err("avdd_lcd regulator get failed\n"); - err = PTR_ERR(avdd_lcd_3v3); - avdd_lcd_3v3 = NULL; - goto fail; - } - - vdd_lcd_bl_en = regulator_get(dev, "vdd_lcd_bl_en"); - if (IS_ERR(vdd_lcd_bl_en)) { - pr_err("vdd_lcd_bl_en regulator get failed\n"); - err = PTR_ERR(vdd_lcd_bl_en); - vdd_lcd_bl_en = NULL; - goto fail; - } - reg_requested = true; - return 0; -fail: - return err; -} - -static int macallan_dsi_gpio_get(void) -{ - int err = 0; - - if (gpio_requested) - return 0; - - err = gpio_request(dsi_p_wuxga_10_1_pdata.dsi_panel_rst_gpio, - "panel rst"); - if (err < 0) { - pr_err("panel reset gpio request failed\n"); - goto fail; - } - - /* free pwm GPIO */ - err = gpio_request(dsi_p_wuxga_10_1_pdata.dsi_panel_bl_pwm_gpio, - "panel pwm"); - if (err < 0) { - pr_err("panel pwm gpio request failed\n"); - goto fail; - } - gpio_free(dsi_p_wuxga_10_1_pdata.dsi_panel_bl_pwm_gpio); - gpio_requested = true; - return 0; -fail: - return err; -} - static int dsi_p_wuxga_10_1_enable(struct device *dev) { int err = 0; - if (machine_is_macallan()) - err = macallan_dsi_regulator_get(dev); - else - err = dalmore_dsi_regulator_get(dev); + err = dalmore_dsi_regulator_get(dev); if (err < 0) { pr_err("dsi regulator get failed\n"); goto fail; @@ -334,10 +274,7 @@ static int dsi_p_wuxga_10_1_enable(struct device *dev) err = tegra_panel_gpio_get_dt("p,wuxga-10-1", &panel_of); if (err < 0) { /* try to request gpios from board file */ - if (machine_is_macallan()) - err = macallan_dsi_gpio_get(); - else - err = dalmore_dsi_gpio_get(); + err = dalmore_dsi_gpio_get(); if (err < 0) { pr_err("dsi gpio request failed\n"); goto fail; @@ -677,9 +614,9 @@ static int __init dsi_p_wuxga_10_1_register_bl_dev(void) } static void dsi_p_wuxga_10_1_set_disp_device( - struct platform_device *display_device) + struct platform_device *dalmore_display_device) { - disp_device = display_device; + disp_device = dalmore_display_device; } static void dsi_p_wuxga_10_1_dc_out_init(struct tegra_dc_out *dc) diff --git a/arch/arm/mach-tegra/panel-s-1080p-5.c b/arch/arm/mach-tegra/panel-s-1080p-5.c deleted file mode 100644 index 82c23ee91e12..000000000000 --- a/arch/arm/mach-tegra/panel-s-1080p-5.c +++ /dev/null @@ -1,697 +0,0 @@ -/* - * arch/arm/mach-tegra/panel-s-1080p-5.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <mach/dc.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/mfd/max8831.h> -#include <linux/max8831_backlight.h> -#include <linux/leds.h> -#include <linux/ioport.h> -#include <linux/lm3528.h> -#include <linux/export.h> - -#include "gpio-names.h" -#include "board-panel.h" -#include "board.h" - -#define DSI_PANEL_RESET 1 - -#define DC_CTRL_MODE TEGRA_DC_OUT_CONTINUOUS_MODE - -static struct regulator *vdd_lcd_s_1v8; -static struct regulator *vdd_sys_bl_3v7; - -static bool dsi_s_1080p_5_reg_requested; -static bool dsi_s_1080p_5_gpio_requested; -static bool is_bl_powered; - -static struct tegra_dc_sd_settings dsi_s_1080p_5_sd_settings = { - .enable = 1, /* enabled by default */ - .use_auto_pwm = false, - .hw_update_delay = 0, - .bin_width = -1, - .aggressiveness = 5, - .use_vid_luma = false, - .phase_in_adjustments = 0, - .k_limit_enable = true, - .k_limit = 180, - .sd_window_enable = false, - .soft_clipping_enable = true, - /* Low soft clipping threshold to compensate for aggressive k_limit */ - .soft_clipping_threshold = 128, - .smooth_k_enable = true, - .smooth_k_incr = 4, - /* Default video coefficients */ - .coeff = {5, 9, 2}, - .fc = {0, 0}, - /* Immediate backlight changes */ - .blp = {1024, 255}, - /* Gammas: R: 2.2 G: 2.2 B: 2.2 */ - /* Default BL TF */ - .bltf = { - { - {57, 65, 73, 82}, - {92, 103, 114, 125}, - {138, 150, 164, 178}, - {193, 208, 224, 241}, - }, - }, - /* Default LUT */ - .lut = { - { - {255, 255, 255}, - {199, 199, 199}, - {153, 153, 153}, - {116, 116, 116}, - {85, 85, 85}, - {59, 59, 59}, - {36, 36, 36}, - {17, 17, 17}, - {0, 0, 0}, - }, - }, - .sd_brightness = &sd_brightness, - .use_vpulse2 = true, -}; - -#ifdef CONFIG_TEGRA_DC_CMU -static struct tegra_dc_cmu dsi_s_1080p_5_cmu = { - /* lut1 maps sRGB to linear space. */ - { - 0, 1, 2, 4, 5, 6, 7, 9, - 10, 11, 12, 14, 15, 16, 18, 20, - 21, 23, 25, 27, 29, 31, 33, 35, - 37, 40, 42, 45, 48, 50, 53, 56, - 59, 62, 66, 69, 72, 76, 79, 83, - 87, 91, 95, 99, 103, 107, 112, 116, - 121, 126, 131, 136, 141, 146, 151, 156, - 162, 168, 173, 179, 185, 191, 197, 204, - 210, 216, 223, 230, 237, 244, 251, 258, - 265, 273, 280, 288, 296, 304, 312, 320, - 329, 337, 346, 354, 363, 372, 381, 390, - 400, 409, 419, 428, 438, 448, 458, 469, - 479, 490, 500, 511, 522, 533, 544, 555, - 567, 578, 590, 602, 614, 626, 639, 651, - 664, 676, 689, 702, 715, 728, 742, 755, - 769, 783, 797, 811, 825, 840, 854, 869, - 884, 899, 914, 929, 945, 960, 976, 992, - 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125, - 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267, - 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420, - 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582, - 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755, - 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939, - 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133, - 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339, - 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555, - 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783, - 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022, - 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272, - 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535, - 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809, - 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095, - }, - /* csc */ - { - 0x0FE, 0x001, 0x3FF, - 0x3FF, 0x0E3, 0x004, - 0x000, 0x003, 0x0D9, - }, - /* lut2 maps linear space to sRGB */ - { - 0, 3, 6, 8, 11, 13, 15, 17, - 19, 21, 22, 24, 25, 26, 27, 28, - 29, 29, 30, 30, 31, 31, 31, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 31, 31, 32, 32, 32, 32, - 32, 32, 32, 33, 33, 33, 33, 34, - 34, 34, 35, 35, 36, 36, 36, 37, - 37, 38, 38, 39, 39, 40, 40, 41, - 41, 42, 42, 43, 43, 44, 45, 45, - 46, 46, 47, 47, 47, 48, 48, 49, - 49, 50, 50, 51, 51, 51, 52, 52, - 52, 53, 53, 53, 54, 54, 54, 55, - 55, 55, 55, 56, 56, 56, 56, 57, - 57, 57, 57, 58, 58, 58, 58, 58, - 59, 59, 59, 59, 59, 60, 60, 60, - 60, 60, 60, 61, 61, 61, 61, 61, - 61, 62, 62, 62, 62, 62, 62, 63, - 63, 63, 63, 63, 63, 64, 64, 64, - 64, 64, 65, 65, 65, 65, 65, 66, - 66, 66, 66, 66, 67, 67, 67, 67, - 68, 68, 68, 68, 68, 69, 69, 69, - 69, 70, 70, 70, 70, 71, 71, 71, - 71, 72, 72, 72, 72, 72, 73, 73, - 73, 73, 74, 74, 74, 74, 75, 75, - 75, 75, 76, 76, 76, 76, 77, 77, - 77, 77, 78, 78, 78, 78, 78, 79, - 79, 79, 79, 79, 80, 80, 80, 80, - 81, 81, 81, 81, 81, 82, 82, 82, - 82, 82, 82, 83, 83, 83, 83, 83, - 83, 84, 84, 84, 84, 84, 84, 85, - 85, 85, 85, 85, 85, 85, 86, 86, - 86, 86, 86, 86, 86, 87, 87, 87, - 87, 87, 87, 87, 87, 88, 88, 88, - 88, 88, 88, 88, 88, 88, 89, 89, - 89, 89, 89, 89, 89, 89, 89, 90, - 90, 90, 90, 90, 90, 90, 90, 90, - 90, 90, 90, 91, 91, 91, 91, 91, - 91, 91, 91, 91, 91, 91, 91, 92, - 92, 92, 92, 92, 92, 92, 92, 92, - 92, 92, 92, 92, 92, 93, 93, 93, - 93, 93, 93, 93, 93, 93, 93, 93, - 93, 93, 93, 93, 93, 94, 94, 94, - 94, 94, 94, 94, 94, 94, 94, 94, - 94, 94, 94, 94, 94, 94, 95, 95, - 95, 95, 95, 95, 95, 95, 95, 95, - 95, 95, 95, 95, 95, 96, 96, 96, - 96, 96, 96, 96, 96, 96, 96, 96, - 96, 96, 96, 96, 97, 97, 97, 97, - 97, 97, 97, 97, 97, 97, 97, 97, - 97, 98, 98, 98, 98, 98, 98, 98, - 98, 98, 98, 98, 98, 98, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 100, 100, 100, 100, 100, 100, 100, - 100, 100, 100, 100, 100, 101, 101, 101, - 101, 101, 101, 101, 101, 101, 101, 101, - 102, 102, 102, 102, 102, 102, 102, 102, - 102, 102, 102, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 104, 104, 104, - 104, 104, 104, 104, 104, 104, 104, 104, - 105, 105, 105, 105, 105, 105, 105, 105, - 105, 105, 105, 106, 106, 106, 106, 106, - 106, 106, 106, 106, 106, 107, 107, 107, - 107, 107, 107, 107, 107, 107, 107, 107, - 108, 108, 108, 108, 108, 108, 108, 108, - 109, 110, 110, 111, 112, 113, 113, 114, - 114, 115, 116, 116, 117, 117, 118, 119, - 119, 120, 120, 121, 121, 122, 122, 123, - 123, 123, 124, 124, 125, 125, 126, 126, - 127, 127, 128, 128, 129, 129, 130, 130, - 131, 131, 132, 132, 133, 133, 134, 134, - 135, 135, 136, 137, 137, 138, 138, 139, - 139, 140, 140, 141, 141, 142, 142, 143, - 143, 143, 144, 144, 145, 145, 146, 146, - 146, 147, 147, 148, 148, 148, 149, 149, - 150, 150, 150, 151, 151, 151, 152, 152, - 152, 153, 153, 153, 154, 154, 155, 155, - 155, 156, 156, 156, 157, 157, 158, 158, - 158, 159, 159, 160, 160, 160, 161, 161, - 162, 162, 163, 163, 164, 164, 164, 165, - 165, 166, 166, 167, 167, 168, 168, 169, - 169, 170, 170, 171, 171, 172, 172, 173, - 173, 174, 174, 175, 175, 176, 176, 176, - 177, 177, 178, 178, 179, 179, 180, 180, - 180, 181, 181, 182, 182, 182, 183, 183, - 184, 184, 184, 185, 185, 185, 186, 186, - 187, 187, 187, 188, 188, 188, 189, 189, - 189, 190, 190, 190, 190, 191, 191, 191, - 192, 192, 192, 193, 193, 193, 193, 194, - 194, 194, 195, 195, 195, 195, 196, 196, - 196, 196, 197, 197, 197, 197, 198, 198, - 198, 198, 199, 199, 199, 199, 199, 200, - 200, 200, 200, 201, 201, 201, 201, 202, - 202, 202, 202, 202, 203, 203, 203, 203, - 204, 204, 204, 204, 204, 205, 205, 205, - 205, 205, 206, 206, 206, 206, 207, 207, - 207, 207, 208, 208, 208, 208, 208, 209, - 209, 209, 209, 210, 210, 210, 210, 211, - 211, 211, 211, 212, 212, 212, 212, 213, - 213, 213, 213, 214, 214, 214, 214, 215, - 215, 215, 215, 216, 216, 216, 216, 217, - 217, 217, 218, 218, 218, 218, 219, 219, - 219, 219, 220, 220, 220, 220, 221, 221, - 221, 221, 222, 222, 222, 223, 223, 223, - 223, 224, 224, 224, 224, 225, 225, 225, - 225, 226, 226, 226, 227, 227, 227, 227, - 228, 228, 228, 228, 229, 229, 229, 229, - 230, 230, 230, 230, 231, 231, 231, 231, - 232, 232, 232, 232, 233, 233, 233, 233, - 234, 234, 234, 234, 235, 235, 235, 235, - 236, 236, 236, 236, 237, 237, 237, 237, - 238, 238, 238, 238, 239, 239, 239, 239, - 240, 240, 240, 240, 241, 241, 241, 241, - 241, 242, 242, 242, 242, 243, 243, 243, - 243, 244, 244, 244, 244, 245, 245, 245, - 245, 245, 246, 246, 246, 246, 247, 247, - 247, 247, 248, 248, 248, 248, 248, 249, - 249, 249, 249, 250, 250, 250, 250, 250, - 251, 251, 251, 251, 252, 252, 252, 252, - 252, 253, 253, 253, 253, 253, 254, 254, - 254, 254, 254, 255, 255, 255, 255, 255, - }, -}; -#endif - -static tegra_dc_bl_output dsi_s_1080p_5_max8831_bl_response_curve = { - 0, 2, 5, 7, 10, 13, 15, 18, - 20, 23, 26, 27, 29, 30, 31, 33, - 34, 36, 37, 39, 40, 41, 42, 44, - 45, 46, 47, 48, 50, 51, 52, 53, - 54, 55, 56, 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 68, 69, - 70, 71, 73, 74, 75, 76, 78, 79, - 80, 82, 83, 84, 86, 86, 87, 88, - 89, 89, 90, 91, 92, 92, 93, 94, - 95, 96, 97, 98, 99, 100, 101, 102, - 103, 104, 105, 106, 107, 107, 108, 109, - 110, 111, 112, 112, 113, 114, 114, 115, - 115, 116, 117, 117, 118, 119, 120, 121, - 121, 122, 123, 124, 125, 126, 127, 128, - 129, 130, 131, 132, 133, 134, 135, 136, - 136, 138, 139, 140, 141, 142, 143, 144, - 145, 146, 147, 148, 149, 150, 151, 152, - 153, 154, 155, 155, 156, 157, 158, 159, - 161, 162, 163, 164, 165, 166, 167, 167, - 167, 167, 168, 168, 168, 168, 168, 169, - 169, 170, 171, 172, 172, 173, 174, 175, - 176, 177, 178, 179, 180, 181, 182, 183, - 184, 184, 185, 186, 187, 188, 189, 190, - 191, 192, 193, 194, 195, 195, 196, 197, - 198, 199, 200, 201, 202, 203, 204, 205, - 206, 206, 207, 207, 208, 208, 209, 209, - 210, 211, 211, 212, 213, 213, 214, 215, - 216, 216, 217, 218, 219, 220, 221, 222, - 223, 224, 225, 226, 227, 228, 229, 230, - 231, 232, 233, 235, 236, 237, 238, 239, - 240, 241, 242, 243, 244, 245, 246, 247, - 248, 249, 250, 251, 252, 253, 254, 255 -}; - -static tegra_dc_bl_output dsi_s_1080p_5_lm3528_bl_response_curve = { - 0, 26, 55, 72, 83, 93, 100, 107, - 112, 117, 121, 125, 129, 132, 135, 138, - 141, 143, 146, 148, 150, 152, 154, 156, - 157, 159, 161, 162, 164, 165, 167, 168, - 169, 171, 172, 173, 174, 175, 176, 177, - 179, 180, 181, 182, 182, 183, 184, 185, - 186, 187, 188, 189, 189, 190, 191, 192, - 192, 193, 194, 195, 195, 196, 197, 197, - 198, 199, 199, 200, 200, 201, 202, 202, - 203, 203, 204, 205, 205, 206, 206, 207, - 207, 208, 208, 209, 209, 210, 210, 211, - 211, 212, 212, 212, 213, 213, 214, 214, - 215, 215, 216, 216, 216, 217, 217, 218, - 218, 218, 219, 219, 220, 220, 220, 221, - 221, 221, 222, 222, 223, 223, 223, 224, - 224, 224, 225, 225, 225, 226, 226, 226, - 227, 227, 227, 228, 228, 228, 228, 229, - 229, 229, 230, 230, 230, 231, 231, 231, - 231, 232, 232, 232, 233, 233, 233, 233, - 234, 234, 234, 234, 235, 235, 235, 236, - 236, 236, 236, 237, 237, 237, 237, 238, - 238, 238, 238, 239, 239, 239, 239, 240, - 240, 240, 240, 240, 241, 241, 241, 241, - 242, 242, 242, 242, 242, 243, 243, 243, - 243, 244, 244, 244, 244, 244, 245, 245, - 245, 245, 245, 246, 246, 246, 246, 246, - 247, 247, 247, 247, 247, 248, 248, 248, - 248, 248, 249, 249, 249, 249, 249, 250, - 250, 250, 250, 250, 250, 251, 251, 251, - 251, 251, 252, 252, 252, 252, 252, 252, - 253, 253, 253, 253, 253, 253, 254, 254, - 254, 254, 254, 254, 255, 255, 255, 255 -}; - -static p_tegra_dc_bl_output dsi_s_1080p_5_bl_response_curve; - -static int __maybe_unused dsi_s_1080p_5_bl_notify(struct device *unused, - int brightness) -{ - int cur_sd_brightness = atomic_read(&sd_brightness); - - /* SD brightness is a percentage */ - brightness = (brightness * cur_sd_brightness) / 255; - - /* Apply any backlight response curve */ - if (brightness > 255) - pr_info("Error: Brightness > 255!\n"); - else - brightness = dsi_s_1080p_5_bl_response_curve[brightness]; - - return brightness; -} -static bool __maybe_unused dsi_s_1080p_5_check_bl_power(void) -{ - return is_bl_powered; -} - -/* - Sharp uses I2C max8831 blacklight device -*/ -static struct led_info dsi_s_1080p_5_max8831_leds[] = { - [MAX8831_ID_LED3] = { - .name = "max8831:red:pluto", - }, - [MAX8831_ID_LED4] = { - .name = "max8831:green:pluto", - }, - [MAX8831_ID_LED5] = { - .name = "max8831:blue:pluto", - }, -}; - -static struct platform_max8831_backlight_data dsi_s_1080p_5_max8831_bl_data = { - .id = -1, - .name = "pluto_display_bl", - .max_brightness = MAX8831_BL_LEDS_MAX_CURR, - .dft_brightness = 100, - .notify = dsi_s_1080p_5_bl_notify, - .is_powered = dsi_s_1080p_5_check_bl_power, -}; - -static struct max8831_subdev_info dsi_s_1080p_5_max8831_subdevs[] = { - { - .id = MAX8831_ID_LED3, - .name = "max8831_led_bl", - .platform_data = &dsi_s_1080p_5_max8831_leds[MAX8831_ID_LED3], - .pdata_size = sizeof( - dsi_s_1080p_5_max8831_leds[MAX8831_ID_LED3]), - }, { - .id = MAX8831_ID_LED4, - .name = "max8831_led_bl", - .platform_data = &dsi_s_1080p_5_max8831_leds[MAX8831_ID_LED4], - .pdata_size = sizeof( - dsi_s_1080p_5_max8831_leds[MAX8831_ID_LED4]), - }, { - .id = MAX8831_ID_LED5, - .name = "max8831_led_bl", - .platform_data = &dsi_s_1080p_5_max8831_leds[MAX8831_ID_LED5], - .pdata_size = sizeof( - dsi_s_1080p_5_max8831_leds[MAX8831_ID_LED5]), - }, { - .id = MAX8831_BL_LEDS, - .name = "max8831_display_bl", - .platform_data = &dsi_s_1080p_5_max8831_bl_data, - .pdata_size = sizeof(dsi_s_1080p_5_max8831_bl_data), - }, -}; - -static struct max8831_platform_data dsi_s_1080p_5_max8831 = { - .num_subdevs = ARRAY_SIZE(dsi_s_1080p_5_max8831_subdevs), - .subdevs = dsi_s_1080p_5_max8831_subdevs, -}; - -static __maybe_unused struct i2c_board_info dsi_s_1080p_5_i2c_led_info = { - .type = "max8831", - .addr = 0x4d, - .platform_data = &dsi_s_1080p_5_max8831, -}; - -static struct lm3528_platform_data lm3528_pdata = { - .dft_brightness = 200, - .is_powered = dsi_s_1080p_5_check_bl_power, - .notify = dsi_s_1080p_5_bl_notify, -}; - -static __maybe_unused struct i2c_board_info - lm3528_dsi_s_1080p_5_i2c_led_info = { - .type = "lm3528_display_bl", - .addr = 0x36, - .platform_data = &lm3528_pdata, -}; - -static int __init dsi_s_1080p_5_register_bl_dev(void) -{ - struct i2c_board_info *bl_info; - struct board_info board_info; - tegra_get_board_info(&board_info); - - switch (board_info.board_id) { - case BOARD_E1670: /* Atlantis ERS */ - case BOARD_E1671: /* Atlantis POP Socket */ - case BOARD_E1740: /* Atlantis FFD */ - bl_info = &lm3528_dsi_s_1080p_5_i2c_led_info; - dsi_s_1080p_5_bl_response_curve = - dsi_s_1080p_5_lm3528_bl_response_curve; - break; - case BOARD_E1680: /* Ceres ERS */ - case BOARD_E1681: /* Ceres DSC Socket */ - case BOARD_E1690: /* Ceres FFD */ - bl_info = &dsi_s_1080p_5_i2c_led_info; - dsi_s_1080p_5_bl_response_curve = - dsi_s_1080p_5_max8831_bl_response_curve; - break; - case BOARD_E1580: /* Pluto */ - /* fall through */ - default: - bl_info = &dsi_s_1080p_5_i2c_led_info; - dsi_s_1080p_5_bl_response_curve = - dsi_s_1080p_5_max8831_bl_response_curve; - break; - } - - return i2c_register_board_info(1, bl_info, 1); -} - -struct tegra_dc_mode dsi_s_1080p_5_modes[] = { - /* 1080x1920@60Hz */ - { - .pclk = 143700000, - .h_ref_to_sync = 4, - .v_ref_to_sync = 1, - .h_sync_width = 10, - .v_sync_width = 2, - .h_back_porch = 50, - .v_back_porch = 4, - .h_active = 1080, - .v_active = 1920, - .h_front_porch = 100, - .v_front_porch = 4, - }, -}; -static int dsi_s_1080p_5_reg_get(void) -{ - int err = 0; - - if (dsi_s_1080p_5_reg_requested) - return 0; - - vdd_lcd_s_1v8 = regulator_get(NULL, "vdd_lcd_1v8_s"); - if (IS_ERR(vdd_lcd_s_1v8)) { - pr_err("vdd_lcd_1v8_s regulator get failed\n"); - err = PTR_ERR(vdd_lcd_s_1v8); - vdd_lcd_s_1v8 = NULL; - goto fail; - } - - vdd_sys_bl_3v7 = regulator_get(NULL, "vdd_sys_bl"); - if (IS_ERR(vdd_sys_bl_3v7)) { - pr_err("vdd_sys_bl regulator get failed\n"); - err = PTR_ERR(vdd_sys_bl_3v7); - vdd_sys_bl_3v7 = NULL; - goto fail; - } - - dsi_s_1080p_5_reg_requested = true; - return 0; -fail: - return err; -} - -static struct tegra_dsi_out dsi_s_1080p_5_pdata; -static int dsi_s_1080p_5_gpio_get(void) -{ - int err = 0; - - if (dsi_s_1080p_5_gpio_requested) - return 0; - - err = gpio_request(dsi_s_1080p_5_pdata.dsi_panel_rst_gpio, "panel rst"); - if (err < 0) { - pr_err("panel reset gpio request failed\n"); - goto fail; - } - - err = gpio_request(dsi_s_1080p_5_pdata.dsi_panel_bl_en_gpio, - "panel backlight"); - if (err < 0) { - pr_err("panel backlight gpio request failed\n"); - goto fail; - } - - - - dsi_s_1080p_5_gpio_requested = true; - return 0; -fail: - return err; -} - -static int dsi_s_1080p_5_enable(struct device *dev) -{ - int err = 0; - err = dsi_s_1080p_5_reg_get(); - if (err < 0) { - pr_err("dsi regulator get failed\n"); - goto fail; - } - - err = dsi_s_1080p_5_gpio_get(); - if (err < 0) { - pr_err("dsi gpio request failed\n"); - goto fail; - } - gpio_direction_output(dsi_s_1080p_5_pdata.dsi_panel_rst_gpio, 0); - - if (vdd_lcd_s_1v8) { - err = regulator_enable(vdd_lcd_s_1v8); - if (err < 0) { - pr_err("vdd_lcd_1v8_s regulator enable failed\n"); - goto fail; - } - } - usleep_range(3000, 5000); - - if (vdd_sys_bl_3v7) { - err = regulator_enable(vdd_sys_bl_3v7); - if (err < 0) { - pr_err("vdd_sys_bl regulator enable failed\n"); - goto fail; - } - } - gpio_direction_output(dsi_s_1080p_5_pdata.dsi_panel_bl_en_gpio, 1); - mdelay(50); - -#if DSI_PANEL_RESET - gpio_set_value(dsi_s_1080p_5_pdata.dsi_panel_rst_gpio, 1); - msleep(20); -#endif - is_bl_powered = true; - - return 0; -fail: - return err; -} - -static u8 panel_internal[] = {0x51, 0x0f, 0xff}; - -static struct tegra_dsi_cmd dsi_s_1080p_5_init_cmd[] = { - - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xb0, 0x04), - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0), - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0), - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xd6, 0x01), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal), - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x53, 0x04), - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0), - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0), -}; - -static struct tegra_dsi_cmd dsi_s_1080p_5_suspend_cmd[] = { - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0), - DSI_DLY_MS(50), - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0), -}; - -static struct tegra_dsi_out dsi_s_1080p_5_pdata = { - .n_data_lanes = 4, - - .refresh_rate = 60, - .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, - .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS, - .video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END, - .controller_vs = DSI_VS_1, - .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P, - .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0, - - .panel_reset = DSI_PANEL_RESET, - .power_saving_suspend = true, - - .dsi_init_cmd = dsi_s_1080p_5_init_cmd, - .n_init_cmd = ARRAY_SIZE(dsi_s_1080p_5_init_cmd), - - .dsi_suspend_cmd = dsi_s_1080p_5_suspend_cmd, - .n_suspend_cmd = ARRAY_SIZE(dsi_s_1080p_5_suspend_cmd), -}; - -static int dsi_s_1080p_5_disable(void) -{ - /* delay between sleep in and reset low */ - msleep(100); - - gpio_set_value(dsi_s_1080p_5_pdata.dsi_panel_rst_gpio, 0); - usleep_range(3000, 5000); - - gpio_set_value(dsi_s_1080p_5_pdata.dsi_panel_bl_en_gpio, 0); - if (vdd_sys_bl_3v7) - regulator_disable(vdd_sys_bl_3v7); - is_bl_powered = false; - usleep_range(3000, 5000); - - if (vdd_lcd_s_1v8) - regulator_disable(vdd_lcd_s_1v8); - - return 0; -} - -static void dsi_s_1080p_5_dc_out_init(struct tegra_dc_out *dc) -{ - dc->dsi = &dsi_s_1080p_5_pdata; - dc->parent_clk = "pll_d_out0"; - dc->modes = dsi_s_1080p_5_modes; - dc->n_modes = ARRAY_SIZE(dsi_s_1080p_5_modes); - dc->enable = dsi_s_1080p_5_enable; - dc->disable = dsi_s_1080p_5_disable; - dc->width = 62; - dc->height = 110; - dc->flags = DC_CTRL_MODE; -} -static void dsi_s_1080p_5_fb_data_init(struct tegra_fb_data *fb) -{ - fb->xres = dsi_s_1080p_5_modes[0].h_active; - fb->yres = dsi_s_1080p_5_modes[0].v_active; -} - -static void dsi_s_1080p_5_sd_settings_init -(struct tegra_dc_sd_settings *settings) -{ - struct board_info bi; - struct board_info board_info; - tegra_get_display_board_info(&bi); - tegra_get_board_info(&board_info); - - *settings = dsi_s_1080p_5_sd_settings; - - if ((bi.board_id == BOARD_E1563) || (board_info.board_id == BOARD_E1740)) - settings->bl_device_name = "lm3528_display_bl"; - else - settings->bl_device_name = "max8831_display_bl"; -} - -#ifdef CONFIG_TEGRA_DC_CMU -static void dsi_s_1080p_5_cmu_init(struct tegra_dc_platform_data *pdata) -{ - pdata->cmu = &dsi_s_1080p_5_cmu; -} -#endif - -struct tegra_panel __initdata dsi_s_1080p_5 = { - .init_sd_settings = dsi_s_1080p_5_sd_settings_init, - .init_dc_out = dsi_s_1080p_5_dc_out_init, - .init_fb_data = dsi_s_1080p_5_fb_data_init, - .register_bl_dev = dsi_s_1080p_5_register_bl_dev, -#ifdef CONFIG_TEGRA_DC_CMU - .init_cmu_data = dsi_s_1080p_5_cmu_init, -#endif -}; -EXPORT_SYMBOL(dsi_s_1080p_5); diff --git a/arch/arm/mach-tegra/powergate-t11x.c b/arch/arm/mach-tegra/powergate-t11x.c deleted file mode 100644 index 954d3a396106..000000000000 --- a/arch/arm/mach-tegra/powergate-t11x.c +++ /dev/null @@ -1,724 +0,0 @@ -/* - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/tegra-powergate.h> - -#include <asm/atomic.h> - -#include "powergate-priv.h" -#include "powergate-ops-txx.h" -#include "powergate-ops-t1xx.h" - -enum mc_client { - MC_CLIENT_AVPC = 1, - MC_CLIENT_DC = 2, - MC_CLIENT_DCB = 3, - MC_CLIENT_EPP = 4, - MC_CLIENT_G2 = 5, - MC_CLIENT_HC = 6, - MC_CLIENT_HDA = 7, - MC_CLIENT_ISP = 8, - MC_CLIENT_MPCORE = 9, - MC_CLIENT_MPCORELP = 10, - MC_CLIENT_MSENC = 11, - MC_CLIENT_NV = 12, - MC_CLIENT_PPCS = 14, - MC_CLIENT_VDE = 16, - MC_CLIENT_VI = 17, - MC_CLIENT_XUSB_HOST = 19, - MC_CLIENT_XUSB_DEV = 20, - MC_CLIENT_EMUCIF = 21, - MC_CLIENT_TSEC = 22, - MC_CLIENT_LAST = -1, - MC_CLIENT_AFI = MC_CLIENT_LAST, - MC_CLIENT_MPE = MC_CLIENT_LAST, - MC_CLIENT_NV2 = MC_CLIENT_LAST, - MC_CLIENT_SATA = MC_CLIENT_LAST, -}; - -struct tegra11x_powergate_mc_client_info { - enum mc_client hot_reset_clients[MAX_HOTRESET_CLIENT_NUM]; -}; - -static struct tegra11x_powergate_mc_client_info tegra11x_pg_mc_info[] = { - [TEGRA_POWERGATE_CRAIL] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_3D] = { - .hot_reset_clients = { - [0] = MC_CLIENT_NV, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_VDEC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_VDE, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_MPE] = { - .hot_reset_clients = { - [0] = MC_CLIENT_MSENC, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_VENC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_ISP, - [1] = MC_CLIENT_VI, - [2] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_HEG] = { - .hot_reset_clients = { - [0] = MC_CLIENT_G2, - [1] = MC_CLIENT_EPP, - [2] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU1] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU2] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU3] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CELP] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU0] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_C0NC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_C1NC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_DISA] = { - .hot_reset_clients = { - [0] = MC_CLIENT_DC, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_DISB] = { - .hot_reset_clients = { - [0] = MC_CLIENT_DCB, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_XUSBA] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_XUSBB] = { - .hot_reset_clients = { - [0] = MC_CLIENT_XUSB_DEV, - [1] = MC_CLIENT_LAST - }, - }, - [TEGRA_POWERGATE_XUSBC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_XUSB_HOST, - [1] = MC_CLIENT_LAST, - }, - }, -}; - -static struct powergate_partition_info tegra11x_powergate_partition_info[] = { - [TEGRA_POWERGATE_CRAIL] = { .name = "crail" }, - [TEGRA_POWERGATE_3D] = { - .name = "3d", - .clk_info = { - [0] = { .clk_name = "3d", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_VDEC] = { - .name = "vde", - .clk_info = { - [0] = { .clk_name = "vde", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_MPE] = { - .name = "mpe", - .clk_info = { - [0] = { .clk_name = "msenc.cbus", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_VENC] = { - .name = "ve", - .clk_info = { - [0] = { .clk_name = "isp", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "vi", .clk_type = CLK_AND_RST }, - [2] = { .clk_name = "csi", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_HEG] = { - .name = "heg", - .clk_info = { - [0] = { .clk_name = "2d.cbus", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "epp.cbus", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_CPU1] = { .name = "cpu1" }, - [TEGRA_POWERGATE_CPU2] = { .name = "cpu2" }, - [TEGRA_POWERGATE_CPU3] = { .name = "cpu3" }, - [TEGRA_POWERGATE_CELP] = { .name = "celp" }, - [TEGRA_POWERGATE_CPU0] = { .name = "cpu0" }, - [TEGRA_POWERGATE_C0NC] = { .name = "c0nc" }, - [TEGRA_POWERGATE_C1NC] = { .name = "c1nc" }, - [TEGRA_POWERGATE_DISA] = { - .name = "disa", - .clk_info = { - [0] = { .clk_name = "disp1", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "dsia", .clk_type = CLK_AND_RST }, - [2] = { .clk_name = "dsib", .clk_type = CLK_AND_RST }, - [3] = { .clk_name = "csi", .clk_type = CLK_AND_RST }, - [4] = { .clk_name = "mipi-cal", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_DISB] = { - .name = "disb", - .clk_info = { - [0] = { .clk_name = "disp2", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "hdmi", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_XUSBA] = { - .name = "xusba", - .clk_info = { - [0] = { .clk_name = "xusb_ss", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_XUSBB] = { - .name = "xusbb", - .clk_info = { - [0] = { .clk_name = "xusb_dev", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_XUSBC] = { - .name = "xusbc", - .clk_info = { - [0] = { .clk_name = "xusb_host", .clk_type = CLK_AND_RST }, - }, - }, -}; - -static atomic_t ref_count_a = ATOMIC_INIT(1); /* for TEGRA_POWERGATE_DISA */ -static atomic_t ref_count_b = ATOMIC_INIT(1); /* for TEGRA_POWERGATE_DISB */ - -static void __iomem *mipi_cal = IO_ADDRESS(TEGRA_MIPI_CAL_BASE); -static u32 mipi_cal_read(unsigned long reg) -{ - return readl(mipi_cal + reg); -} - -static void mipi_cal_write(u32 val, unsigned long reg) -{ - writel_relaxed(val, mipi_cal + reg); -} - -#define MC_CLIENT_HOTRESET_CTRL 0x200 -#define MC_CLIENT_HOTRESET_STAT 0x204 - -static DEFINE_SPINLOCK(tegra11x_powergate_lock); - -/* Forward Declarations */ -int tegra11x_powergate_mc_flush(int id); -int tegra11x_powergate_mc_flush_done(int id); -int tegra11x_unpowergate_partition_with_clk_on(int id); -int tegra11x_powergate_partition_with_clk_off(int id); - -bool tegra11x_powergate_check_clamping(int id) -{ - u32 mask; - /* - * PCIE and VDE clamping masks are swapped with respect to their - * partition ids - */ - if (id == TEGRA_POWERGATE_VDEC) - mask = (1 << TEGRA_POWERGATE_PCIE); - else if (id == TEGRA_POWERGATE_PCIE) - mask = (1 << TEGRA_POWERGATE_VDEC); - else - mask = (1 << id); - - return !!(pmc_read(PWRGATE_CLAMP_STATUS) & mask); -} - -#define HOTRESET_READ_COUNT 5 -static bool tegra11x_stable_hotreset_check(u32 *stat) -{ - int i; - u32 cur_stat; - u32 prv_stat; - unsigned long flags; - - spin_lock_irqsave(&tegra11x_powergate_lock, flags); - prv_stat = mc_read(MC_CLIENT_HOTRESET_STAT); - for (i = 0; i < HOTRESET_READ_COUNT; i++) { - cur_stat = mc_read(MC_CLIENT_HOTRESET_STAT); - if (cur_stat != prv_stat) { - spin_unlock_irqrestore(&tegra11x_powergate_lock, flags); - return false; - } - } - *stat = cur_stat; - spin_unlock_irqrestore(&tegra11x_powergate_lock, flags); - return true; -} - -/* - * FIXME: sw war for mipi-cal calibration when unpowergating DISA partition - */ -static void tegra11x_mipical_calibrate(int id) -{ - struct reg_offset_val { - u32 offset; - u32 por_value; - }; - u32 status; - unsigned long flags; - -#define MIPI_CAL_MIPI_CAL_CTRL_0 0x0 -#define MIPI_CAL_CIL_MIPI_CAL_STATUS_0 0x8 -#define MIPI_CAL_CILA_MIPI_CAL_CONFIG_0 0x14 -#define MIPI_CAL_CILB_MIPI_CAL_CONFIG_0 0x18 -#define MIPI_CAL_CILC_MIPI_CAL_CONFIG_0 0x1c -#define MIPI_CAL_CILD_MIPI_CAL_CONFIG_0 0x20 -#define MIPI_CAL_CILE_MIPI_CAL_CONFIG_0 0x24 -#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0 0x38 -#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0 0x3c -#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0 0x40 -#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_0 0x44 - - static struct reg_offset_val mipi_cal_por_values[] = { - { MIPI_CAL_MIPI_CAL_CTRL_0, 0x2a000000 }, - { MIPI_CAL_CILA_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILB_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILC_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILD_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILE_MIPI_CAL_CONFIG_0, 0x00000000 }, - { MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_DSID_MIPI_CAL_CONFIG_0, 0x00200000 }, - }; - int i; - - if (id != TEGRA_POWERGATE_DISA) - return; - - spin_lock_irqsave(&tegra11x_powergate_lock, flags); - - /* mipi cal por restore */ - for (i = 0; i < ARRAY_SIZE(mipi_cal_por_values); i++) { - mipi_cal_write(mipi_cal_por_values[i].por_value, - mipi_cal_por_values[i].offset); - } - - /* mipi cal status clear */ - status = mipi_cal_read(MIPI_CAL_CIL_MIPI_CAL_STATUS_0); - mipi_cal_write(status, MIPI_CAL_CIL_MIPI_CAL_STATUS_0); - - /* mipi cal status read - to flush writes */ - status = mipi_cal_read(MIPI_CAL_CIL_MIPI_CAL_STATUS_0); - - spin_unlock_irqrestore(&tegra11x_powergate_lock, flags); -} - -static int tegra11x_powergate_partition_internal(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - if (tegra_powergate_is_powered(id)) { - ret = is_partition_clk_disabled(pg_info); - if (ret < 0) { - /* clock enabled */ - ret = tegra11x_powergate_partition_with_clk_off(id); - if (ret < 0) - return ret; - } else { - ret = tegra_powergate_partition(id); - if (ret < 0) - return ret; - } - } - return 0; -} - -static int tegra11x_unpowergate_partition_internal(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - if (!tegra_powergate_is_powered(id)) { - ret = is_partition_clk_disabled(pg_info); - if (ret) { - /* clock disabled */ - ret = tegra11x_unpowergate_partition_with_clk_on(id); - if (ret < 0) - return ret; - } else { - ret = tegra_unpowergate_partition(id); - if (ret < 0) - return ret; - } - } - return 0; -} - -/* - * Tegra11x has powergate dependencies between partitions. - * This function captures the dependencies. - */ -static int tegra11x_check_partition_pg_seq(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - if (id == TEGRA_POWERGATE_DISA) { - ret = tegra11x_powergate_partition_internal(TEGRA_POWERGATE_VENC, - pg_info); - if (ret < 0) - return ret; - - ret = tegra11x_powergate_partition_internal(TEGRA_POWERGATE_DISB, - pg_info); - if (ret < 0) - return ret; - } - - return 0; -} - -/* - * This function captures power-ungate dependencies between tegra11x partitions - */ -static int tegra11x_check_partition_pug_seq(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - switch (id) { - case TEGRA_POWERGATE_DISB: - case TEGRA_POWERGATE_VENC: - ret = tegra11x_unpowergate_partition_internal(TEGRA_POWERGATE_DISA, - pg_info); - if (ret < 0) - return ret; - - break; - } - return 0; -} - -int tegra11x_powergate_mc_enable(int id) -{ - return 0; -} - -int tegra11x_powergate_mc_disable(int id) -{ - return 0; -} - -int tegra11x_powergate_mc_flush(int id) -{ - u32 idx, rst_ctrl, rst_stat; - enum mc_client mcClientBit; - unsigned long flags; - bool ret; - - for (idx = 0; idx < MAX_HOTRESET_CLIENT_NUM; idx++) { - mcClientBit = - tegra11x_pg_mc_info[id].hot_reset_clients[idx]; - if (mcClientBit == MC_CLIENT_LAST) - break; - - spin_lock_irqsave(&tegra11x_powergate_lock, flags); - rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL); - rst_ctrl |= (1 << mcClientBit); - mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL); - - spin_unlock_irqrestore(&tegra11x_powergate_lock, flags); - - do { - udelay(10); - rst_stat = 0; - ret = tegra11x_stable_hotreset_check(&rst_stat); - if (!ret) - continue; - } while (!(rst_stat & (1 << mcClientBit))); - } - - return 0; -} - -int tegra11x_powergate_mc_flush_done(int id) -{ - u32 idx, rst_ctrl; - enum mc_client mcClientBit; - unsigned long flags; - - for (idx = 0; idx < MAX_HOTRESET_CLIENT_NUM; idx++) { - mcClientBit = - tegra11x_pg_mc_info[id].hot_reset_clients[idx]; - if (mcClientBit == MC_CLIENT_LAST) - break; - - spin_lock_irqsave(&tegra11x_powergate_lock, flags); - - rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL); - rst_ctrl &= ~(1 << mcClientBit); - mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL); - mc_read(MC_CLIENT_HOTRESET_CTRL); - - spin_unlock_irqrestore(&tegra11x_powergate_lock, flags); - } - - wmb(); - - return 0; -} - -static int tegra11x_unpowergate(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - /* If first clk_ptr is null, fill clk info for the partition */ - if (!pg_info->clk_info[0].clk_ptr) - get_clk_info(pg_info); - - if (tegra_powergate_is_powered(id)) - return tegra_powergate_reset_module(pg_info); - - ret = tegra_powergate_set(id, true); - if (ret) - goto err_power; - - udelay(10); - - powergate_partition_assert_reset(pg_info); - - udelay(10); - - /* Un-Powergating fails if all clks are not enabled */ - ret = partition_clk_enable(pg_info); - if (ret) - goto err_clk_on; - - udelay(10); - - ret = tegra_powergate_remove_clamping(id); - if (ret) - goto err_clamp; - - udelay(10); - - tegra11x_mipical_calibrate(id); - - powergate_partition_deassert_reset(pg_info); - - udelay(10); - - tegra_powergate_mc_flush_done(id); - - udelay(10); - - /* Disable all clks enabled earlier. Drivers should enable clks */ - partition_clk_disable(pg_info); - - return 0; - -err_clamp: - partition_clk_disable(pg_info); -err_clk_on: - powergate_module(id); -err_power: - WARN(1, "Could not Un-Powergate %d", id); - return ret; -} - -void tegra11x_powergate_dis_partition(void) -{ - tegra1xx_powergate(TEGRA_POWERGATE_DISB, - &tegra11x_powergate_partition_info[TEGRA_POWERGATE_DISB]); - - tegra11x_powergate_partition_internal(TEGRA_POWERGATE_VENC, - &tegra11x_powergate_partition_info[TEGRA_POWERGATE_DISA]); - - tegra1xx_powergate(TEGRA_POWERGATE_DISA, - &tegra11x_powergate_partition_info[TEGRA_POWERGATE_DISA]); -} - -/* The logic manages the ref-count for dis partitions. The dependency between - * disa and disb is hided from client. */ -bool tegra11x_powergate_check_dis_refcount(int id, int op) -{ - WARN_ONCE(atomic_read(&ref_count_a) < 0, "dis ref a count underflow"); - WARN_ONCE(atomic_read(&ref_count_b) < 0, "dis ref b count underflow"); - - if (op && id == TEGRA_POWERGATE_DISA) { - if (atomic_inc_return(&ref_count_a) != 1) - return 0; - } else if (op && id == TEGRA_POWERGATE_DISB) { - if (tegra_powergate_is_powered(TEGRA_POWERGATE_DISA)) - atomic_inc(&ref_count_a); - if (atomic_inc_return(&ref_count_b) != 1) - return 0; - } else if (!op && id == TEGRA_POWERGATE_DISA) { - if (atomic_dec_return(&ref_count_a) != 0) - return 0; - } else if (!op && id == TEGRA_POWERGATE_DISB) { - atomic_dec(&ref_count_a); - if (atomic_dec_return(&ref_count_b) != 0) { - return 0; - } else if (atomic_read(&ref_count_a) == 0) { - tegra11x_powergate_dis_partition(); - return 0; - } - } - - return 1; -} - -int tegra11x_powergate_partition(int id) -{ - int ret; - - if ((id == TEGRA_POWERGATE_DISA || id == TEGRA_POWERGATE_DISB) && - !tegra11x_powergate_check_dis_refcount(id, 0)) - return 0; - - ret = tegra11x_check_partition_pg_seq(id, - &tegra11x_powergate_partition_info[id]); - if (ret) - return ret; - - /* call common power-gate API for t1xx */ - ret = tegra1xx_powergate(id, - &tegra11x_powergate_partition_info[id]); - - return ret; -} - -int tegra11x_unpowergate_partition(int id) -{ - int ret; - - if ((id == TEGRA_POWERGATE_DISA || id == TEGRA_POWERGATE_DISB) && - !tegra11x_powergate_check_dis_refcount(id, 1)) - return 0; - - ret = tegra11x_check_partition_pug_seq(id, - &tegra11x_powergate_partition_info[id]); - if (ret) - return ret; - - /* t11x needs to calibrate mipi in un-power-gate sequence - * hence it cannot use common un-power-gate api tegra1xx_unpowergate */ - ret = tegra11x_unpowergate(id, - &tegra11x_powergate_partition_info[id]); - - return ret; -} - -int tegra11x_powergate_partition_with_clk_off(int id) -{ - return tegraxx_powergate_partition_with_clk_off(id, - &tegra11x_powergate_partition_info[id]); -} - -int tegra11x_unpowergate_partition_with_clk_on(int id) -{ - return tegraxx_unpowergate_partition_with_clk_on(id, - &tegra11x_powergate_partition_info[id]); -} - -const char *tegra11x_get_powergate_domain_name(int id) -{ - return tegra11x_powergate_partition_info[id].name; -} - -spinlock_t *tegra11x_get_powergate_lock(void) -{ - return &tegra11x_powergate_lock; -} - -int tegra11x_powergate_init_refcount(void) -{ - if (tegra_powergate_is_powered(TEGRA_POWERGATE_DISA)) - atomic_set(&ref_count_a, 1); - else - atomic_set(&ref_count_a, 0); - - if (tegra_powergate_is_powered(TEGRA_POWERGATE_DISB)) - atomic_set(&ref_count_b, 1); - else - atomic_set(&ref_count_b, 0); - return 0; -} - -static struct powergate_ops tegra11x_powergate_ops = { - .soc_name = "tegra11x", - - .num_powerdomains = TEGRA_NUM_POWERGATE, - - .get_powergate_lock = tegra11x_get_powergate_lock, - .get_powergate_domain_name = tegra11x_get_powergate_domain_name, - - .powergate_partition = tegra11x_powergate_partition, - .unpowergate_partition = tegra11x_unpowergate_partition, - - .powergate_partition_with_clk_off = tegra11x_powergate_partition_with_clk_off, - .unpowergate_partition_with_clk_on = tegra11x_unpowergate_partition_with_clk_on, - - .powergate_mc_enable = tegra11x_powergate_mc_enable, - .powergate_mc_disable = tegra11x_powergate_mc_disable, - - .powergate_mc_flush = tegra11x_powergate_mc_flush, - .powergate_mc_flush_done = tegra11x_powergate_mc_flush_done, - - .powergate_init_refcount = tegra11x_powergate_init_refcount, - .powergate_check_clamping = tegra11x_powergate_check_clamping, -}; - -struct powergate_ops *tegra11x_powergate_init_chip_support(void) -{ - return &tegra11x_powergate_ops; -} diff --git a/arch/arm/mach-tegra/powergate-t14x.c b/arch/arm/mach-tegra/powergate-t14x.c deleted file mode 100644 index 2ee85b593e35..000000000000 --- a/arch/arm/mach-tegra/powergate-t14x.c +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/tegra-powergate.h> - -#include <asm/atomic.h> - -#include "powergate-priv.h" -#include "powergate-ops-txx.h" -#include "powergate-ops-t1xx.h" - -enum mc_client { - MC_CLIENT_AVPC = 1, - MC_CLIENT_DC = 2, - MC_CLIENT_DCB = 3, - MC_CLIENT_EPP = 4, - MC_CLIENT_G2 = 5, - MC_CLIENT_HC = 6, - MC_CLIENT_HDA = 7, - MC_CLIENT_ISP = 8, - MC_CLIENT_MPCORE = 9, - MC_CLIENT_MPCORELP = 10, - MC_CLIENT_MSENC = 11, - MC_CLIENT_NV = 12, - MC_CLIENT_PPCS = 14, - MC_CLIENT_VDE = 16, - MC_CLIENT_VI = 17, - MC_CLIENT_EMUCIF = 21, - MC_CLIENT_TSEC = 22, - MC_CLIENT_LAST = -1, - MC_CLIENT_AFI = MC_CLIENT_LAST, - MC_CLIENT_MPE = MC_CLIENT_LAST, - MC_CLIENT_NV2 = MC_CLIENT_LAST, - MC_CLIENT_SATA = MC_CLIENT_LAST, -}; - -struct tegra14x_powergate_mc_client_info { - enum mc_client hot_reset_clients[MAX_HOTRESET_CLIENT_NUM]; -}; - -static struct tegra14x_powergate_mc_client_info - tegra14x_pg_mc_info[TEGRA_NUM_POWERGATE] = { - [TEGRA_POWERGATE_CRAIL] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_3D] = { - .hot_reset_clients = { - [0] = MC_CLIENT_NV, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_VDEC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_VDE, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_MPE] = { - .hot_reset_clients = { - [0] = MC_CLIENT_MSENC, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_VENC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_ISP, - [1] = MC_CLIENT_VI, - [2] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_HEG] = { - .hot_reset_clients = { - [0] = MC_CLIENT_G2, - [1] = MC_CLIENT_EPP, - [2] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU1] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU2] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU3] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CELP] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_CPU0] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_C0NC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_C1NC] = { - .hot_reset_clients = { - [0] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_DISA] = { - .hot_reset_clients = { - [0] = MC_CLIENT_DC, - [1] = MC_CLIENT_LAST, - }, - }, - [TEGRA_POWERGATE_DISB] = { - .hot_reset_clients = { - [0] = MC_CLIENT_DCB, - [1] = MC_CLIENT_LAST, - }, - }, -}; - -static struct powergate_partition_info - tegra14x_powergate_partition_info[TEGRA_NUM_POWERGATE] = { - [TEGRA_POWERGATE_CRAIL] = { .name = "crail" }, - [TEGRA_POWERGATE_3D] = { - .name = "3d", - .clk_info = { - [0] = { .clk_name = "3d", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_VDEC] = { - .name = "vde", - .clk_info = { - [0] = { .clk_name = "vde", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_MPE] = { - .name = "mpe", - .clk_info = { - [0] = { .clk_name = "msenc.cbus", - .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_VENC] = { - .name = "ve", - .clk_info = { - [0] = { .clk_name = "isp", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "vi", .clk_type = CLK_AND_RST }, - [2] = { .clk_name = "csi", .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_HEG] = { - .name = "heg", - .clk_info = { - [0] = { .clk_name = "2d.cbus", - .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "epp.cbus", - .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_CPU1] = { .name = "cpu1" }, - [TEGRA_POWERGATE_CPU2] = { .name = "cpu2" }, - [TEGRA_POWERGATE_CPU3] = { .name = "cpu3" }, - [TEGRA_POWERGATE_CELP] = { .name = "celp" }, - [TEGRA_POWERGATE_CPU0] = { .name = "cpu0" }, - [TEGRA_POWERGATE_C0NC] = { .name = "c0nc" }, - [TEGRA_POWERGATE_C1NC] = { .name = "c1nc" }, - [TEGRA_POWERGATE_DISA] = { - .name = "disa", - .clk_info = { - [0] = { .clk_name = "disp1", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "dsia", .clk_type = CLK_AND_RST }, - [2] = { .clk_name = "dsib", .clk_type = CLK_AND_RST }, - [3] = { .clk_name = "csi", .clk_type = CLK_AND_RST }, - [4] = { .clk_name = "mipi-cal", - .clk_type = CLK_AND_RST }, - }, - }, - [TEGRA_POWERGATE_DISB] = { - .name = "disb", - .clk_info = { - [0] = { .clk_name = "disp2", .clk_type = CLK_AND_RST }, - [1] = { .clk_name = "hdmi", .clk_type = CLK_AND_RST }, - }, - }, -}; - -static atomic_t ref_count_a = ATOMIC_INIT(1); /* for TEGRA_POWERGATE_DISA */ -static atomic_t ref_count_b = ATOMIC_INIT(1); /* for TEGRA_POWERGATE_DISB */ - -static void __iomem *mipi_cal = IO_ADDRESS(TEGRA_MIPI_CAL_BASE); -static u32 mipi_cal_read(unsigned long reg) -{ - return readl(mipi_cal + reg); -} - -static void mipi_cal_write(u32 val, unsigned long reg) -{ - writel_relaxed(val, mipi_cal + reg); -} - -#define MC_CLIENT_HOTRESET_CTRL 0x200 -#define MC_CLIENT_HOTRESET_STAT 0x204 - -static DEFINE_SPINLOCK(tegra14x_powergate_lock); - -/* Forward Declarations */ -static int tegra14x_powergate_mc_flush(int id); -static int tegra14x_powergate_mc_flush_done(int id); -static int tegra14x_unpowergate_partition_with_clk_on(int id); -static int tegra14x_powergate_partition_with_clk_off(int id); - -#define HOTRESET_READ_COUNT 5 -static bool tegra14x_stable_hotreset_check(u32 *stat) -{ - int i; - u32 cur_stat; - u32 prv_stat; - unsigned long flags; - - spin_lock_irqsave(&tegra14x_powergate_lock, flags); - prv_stat = mc_read(MC_CLIENT_HOTRESET_STAT); - for (i = 0; i < HOTRESET_READ_COUNT; i++) { - cur_stat = mc_read(MC_CLIENT_HOTRESET_STAT); - if (cur_stat != prv_stat) { - spin_unlock_irqrestore(&tegra14x_powergate_lock, flags); - return false; - } - } - *stat = cur_stat; - spin_unlock_irqrestore(&tegra14x_powergate_lock, flags); - return true; -} - -/* - * FIXME: sw war for mipi-cal calibration when unpowergating DISA partition - */ -static void tegra14x_mipical_calibrate(int id) -{ - struct reg_offset_val { - u32 offset; - u32 por_value; - }; - u32 status; - unsigned long flags; - -#define MIPI_CAL_MIPI_CAL_CTRL_0 0x0 -#define MIPI_CAL_CIL_MIPI_CAL_STATUS_0 0x8 -#define MIPI_CAL_CILA_MIPI_CAL_CONFIG_0 0x14 -#define MIPI_CAL_CILB_MIPI_CAL_CONFIG_0 0x18 -#define MIPI_CAL_CILC_MIPI_CAL_CONFIG_0 0x1c -#define MIPI_CAL_CILD_MIPI_CAL_CONFIG_0 0x20 -#define MIPI_CAL_CILE_MIPI_CAL_CONFIG_0 0x24 -#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0 0x38 -#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0 0x3c -#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0 0x40 -#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_0 0x44 - - static struct reg_offset_val mipi_cal_por_values[] = { - { MIPI_CAL_MIPI_CAL_CTRL_0, 0x2a000000 }, - { MIPI_CAL_CILA_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILB_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILC_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILD_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_CILE_MIPI_CAL_CONFIG_0, 0x00000000 }, - { MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0, 0x00200000 }, - { MIPI_CAL_DSID_MIPI_CAL_CONFIG_0, 0x00200000 }, - }; - int i; - - if (id != TEGRA_POWERGATE_DISA) - return; - - spin_lock_irqsave(&tegra14x_powergate_lock, flags); - - /* mipi cal por restore */ - for (i = 0; i < ARRAY_SIZE(mipi_cal_por_values); i++) { - mipi_cal_write(mipi_cal_por_values[i].por_value, - mipi_cal_por_values[i].offset); - } - - /* mipi cal status clear */ - status = mipi_cal_read(MIPI_CAL_CIL_MIPI_CAL_STATUS_0); - mipi_cal_write(status, MIPI_CAL_CIL_MIPI_CAL_STATUS_0); - - /* mipi cal status read - to flush writes */ - status = mipi_cal_read(MIPI_CAL_CIL_MIPI_CAL_STATUS_0); - - spin_unlock_irqrestore(&tegra14x_powergate_lock, flags); -} - -static int tegra14x_powergate_partition_internal(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - if (tegra_powergate_is_powered(id)) { - ret = is_partition_clk_disabled(pg_info); - if (ret < 0) { - /* clock enabled */ - ret = tegra14x_powergate_partition_with_clk_off(id); - if (ret < 0) - return ret; - } else { - ret = tegra_powergate_partition(id); - if (ret < 0) - return ret; - } - } - return 0; -} - -static int tegra14x_unpowergate_partition_internal(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - if (!tegra_powergate_is_powered(id)) { - ret = is_partition_clk_disabled(pg_info); - if (ret) { - /* clock disabled */ - ret = tegra14x_unpowergate_partition_with_clk_on(id); - if (ret < 0) - return ret; - } else { - ret = tegra_unpowergate_partition(id); - if (ret < 0) - return ret; - } - } - return 0; -} - -/* - * Tegra14x has powergate dependencies between partitions. - * This function captures the dependencies. - */ -static int tegra14x_check_partition_pg_seq(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - if (id == TEGRA_POWERGATE_DISA) { - ret = tegra14x_powergate_partition_internal( - TEGRA_POWERGATE_VENC, pg_info); - if (ret < 0) - return ret; - - ret = tegra14x_powergate_partition_internal( - TEGRA_POWERGATE_DISB, pg_info); - if (ret < 0) - return ret; - } - - return 0; -} - -/* - * This function captures power-ungate dependencies between tegra14x partitions - */ -static int tegra14x_check_partition_pug_seq(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - switch (id) { - case TEGRA_POWERGATE_DISB: - case TEGRA_POWERGATE_VENC: - ret = tegra14x_unpowergate_partition_internal( - TEGRA_POWERGATE_DISA, pg_info); - if (ret < 0) - return ret; - - break; - } - return 0; -} - -int tegra14x_powergate_mc_enable(int id) -{ - return 0; -} - -int tegra14x_powergate_mc_disable(int id) -{ - return 0; -} - -int tegra14x_powergate_mc_flush(int id) -{ - u32 idx, rst_ctrl, rst_stat; - enum mc_client mcClientBit; - unsigned long flags; - bool ret; - - for (idx = 0; idx < MAX_HOTRESET_CLIENT_NUM; idx++) { - mcClientBit = - tegra14x_pg_mc_info[id].hot_reset_clients[idx]; - if (mcClientBit == MC_CLIENT_LAST) - break; - - spin_lock_irqsave(&tegra14x_powergate_lock, flags); - rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL); - rst_ctrl |= (1 << mcClientBit); - mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL); - - spin_unlock_irqrestore(&tegra14x_powergate_lock, flags); - - do { -#ifdef CONFIG_TEGRA_ERRATA_1213083 - udelay(10); -#endif - rst_stat = 0; - ret = tegra14x_stable_hotreset_check(&rst_stat); - if (!ret) - continue; - } while (!(rst_stat & (1 << mcClientBit))); - } - - return 0; -} - -int tegra14x_powergate_mc_flush_done(int id) -{ - u32 idx, rst_ctrl; - enum mc_client mcClientBit; - unsigned long flags; - - for (idx = 0; idx < MAX_HOTRESET_CLIENT_NUM; idx++) { - mcClientBit = - tegra14x_pg_mc_info[id].hot_reset_clients[idx]; - if (mcClientBit == MC_CLIENT_LAST) - break; - - spin_lock_irqsave(&tegra14x_powergate_lock, flags); - - rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL); - rst_ctrl &= ~(1 << mcClientBit); - mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL); - mc_read(MC_CLIENT_HOTRESET_CTRL); - - spin_unlock_irqrestore(&tegra14x_powergate_lock, flags); - } - - wmb(); - - return 0; -} - -static int tegra14x_unpowergate(int id, - struct powergate_partition_info *pg_info) -{ - int ret; - - /* If first clk_ptr is null, fill clk info for the partition */ - if (!pg_info->clk_info[0].clk_ptr) - get_clk_info(pg_info); - - if (tegra_powergate_is_powered(id)) - return tegra_powergate_reset_module(pg_info); - - ret = tegra_powergate_set(id, true); - if (ret) - goto err_power; - - udelay(10); - - powergate_partition_assert_reset(pg_info); - - udelay(10); - - /* Un-Powergating fails if all clks are not enabled */ - ret = partition_clk_enable(pg_info); - if (ret) - goto err_clk_on; - - udelay(10); - - ret = tegra_powergate_remove_clamping(id); - if (ret) - goto err_clamp; - - udelay(10); - - tegra14x_mipical_calibrate(id); - - powergate_partition_deassert_reset(pg_info); - - udelay(10); - - tegra_powergate_mc_flush_done(id); - - udelay(10); - - /* Disable all clks enabled earlier. Drivers should enable clks */ - partition_clk_disable(pg_info); - - return 0; - -err_clamp: - partition_clk_disable(pg_info); -err_clk_on: - powergate_module(id); -err_power: - WARN(1, "Could not Un-Powergate %d", id); - return ret; -} - -void tegra14x_powergate_dis_partition(void) -{ - tegra1xx_powergate(TEGRA_POWERGATE_DISB, - &tegra14x_powergate_partition_info[TEGRA_POWERGATE_DISB]); - - tegra14x_powergate_partition_internal(TEGRA_POWERGATE_VENC, - &tegra14x_powergate_partition_info[TEGRA_POWERGATE_DISA]); - - tegra1xx_powergate(TEGRA_POWERGATE_DISA, - &tegra14x_powergate_partition_info[TEGRA_POWERGATE_DISA]); -} - -/* The logic manages the ref-count for dis partitions. The dependency between - * disa and disb is hided from client. */ -bool tegra14x_powergate_check_dis_refcount(int id, int op) -{ - WARN_ONCE(atomic_read(&ref_count_a) < 0, "dis ref a count underflow"); - WARN_ONCE(atomic_read(&ref_count_b) < 0, "dis ref b count underflow"); - - if (op && id == TEGRA_POWERGATE_DISA) { - if (atomic_inc_return(&ref_count_a) != 1) - return 0; - } else if (op && id == TEGRA_POWERGATE_DISB) { - if (tegra_powergate_is_powered(TEGRA_POWERGATE_DISA)) - atomic_inc(&ref_count_a); - if (atomic_inc_return(&ref_count_b) != 1) - return 0; - } else if (!op && id == TEGRA_POWERGATE_DISA) { - if (atomic_dec_return(&ref_count_a) != 0) - return 0; - } else if (!op && id == TEGRA_POWERGATE_DISB) { - atomic_dec(&ref_count_a); - if (atomic_dec_return(&ref_count_b) != 0) { - return 0; - } else if (atomic_read(&ref_count_a) == 0) { - tegra14x_powergate_dis_partition(); - return 0; - } - } - - return 1; -} - -int tegra14x_powergate_partition(int id) -{ - int ret; - - if ((id == TEGRA_POWERGATE_DISA || id == TEGRA_POWERGATE_DISB) && - !tegra14x_powergate_check_dis_refcount(id, 0)) - return 0; - - ret = tegra14x_check_partition_pg_seq(id, - &tegra14x_powergate_partition_info[id]); - if (ret) - return ret; - - /* call common power-gate API for t1xx */ - ret = tegra1xx_powergate(id, - &tegra14x_powergate_partition_info[id]); - - return ret; -} - -int tegra14x_unpowergate_partition(int id) -{ - int ret; - - if ((id == TEGRA_POWERGATE_DISA || id == TEGRA_POWERGATE_DISB) && - !tegra14x_powergate_check_dis_refcount(id, 1)) - return 0; - - ret = tegra14x_check_partition_pug_seq(id, - &tegra14x_powergate_partition_info[id]); - if (ret) - return ret; - - /* t14x needs to calibrate mipi in un-power-gate sequence - * hence it cannot use common un-power-gate api tegra1xx_unpowergate */ - ret = tegra14x_unpowergate(id, - &tegra14x_powergate_partition_info[id]); - - return ret; -} - -int tegra14x_powergate_partition_with_clk_off(int id) -{ - return tegraxx_powergate_partition_with_clk_off(id, - &tegra14x_powergate_partition_info[id]); -} - -int tegra14x_unpowergate_partition_with_clk_on(int id) -{ - return tegraxx_unpowergate_partition_with_clk_on(id, - &tegra14x_powergate_partition_info[id]); -} - -const char *tegra14x_get_powergate_domain_name(int id) -{ - return tegra14x_powergate_partition_info[id].name; -} - -spinlock_t *tegra14x_get_powergate_lock(void) -{ - return &tegra14x_powergate_lock; -} - -int tegra14x_powergate_init_refcount(void) -{ - if (tegra_powergate_is_powered(TEGRA_POWERGATE_DISA)) - atomic_set(&ref_count_a, 1); - else - atomic_set(&ref_count_a, 0); - - if (tegra_powergate_is_powered(TEGRA_POWERGATE_DISB)) - atomic_set(&ref_count_b, 1); - else - atomic_set(&ref_count_b, 0); - return 0; -} - -static struct powergate_ops tegra14x_powergate_ops = { - .soc_name = "tegra14x", - - .num_powerdomains = TEGRA_NUM_POWERGATE, - - .get_powergate_lock = tegra14x_get_powergate_lock, - .get_powergate_domain_name = tegra14x_get_powergate_domain_name, - - .powergate_partition = tegra14x_powergate_partition, - .unpowergate_partition = tegra14x_unpowergate_partition, - - .powergate_partition_with_clk_off = - tegra14x_powergate_partition_with_clk_off, - .unpowergate_partition_with_clk_on = - tegra14x_unpowergate_partition_with_clk_on, - - .powergate_mc_enable = tegra14x_powergate_mc_enable, - .powergate_mc_disable = tegra14x_powergate_mc_disable, - - .powergate_mc_flush = tegra14x_powergate_mc_flush, - .powergate_mc_flush_done = tegra14x_powergate_mc_flush_done, - - .powergate_init_refcount = tegra14x_powergate_init_refcount, -}; - -struct powergate_ops *tegra14x_powergate_init_chip_support(void) -{ - return &tegra14x_powergate_ops; -} diff --git a/arch/arm/mach-tegra/tegra-board-id.h b/arch/arm/mach-tegra/tegra-board-id.h index 048d9b03a354..2d324aa34065 100644 --- a/arch/arm/mach-tegra/tegra-board-id.h +++ b/arch/arm/mach-tegra/tegra-board-id.h @@ -22,27 +22,10 @@ #define _MACH_TEGRA_BOARD_ID_H /* Processor Board ID */ -#define BOARD_E1545 0x0609 -#define BOARD_E1575 0x0627 -#define BOARD_E1577 0x0629 -#define BOARD_E1580 0x062C -#define BOARD_E1582 0x062E #define BOARD_E1611 0x064B #define BOARD_E1612 0x064C #define BOARD_E1613 0x064D -#define BOARD_E1614 0x064E -#define BOARD_E1641 0x0669 -#define BOARD_P2454 0x0996 -#define BOARD_PM347 0x015B -#define BOARD_E1545 0x0609 -#define BOARD_E1569 0x0621 -#define BOARD_E1680 0x0690 -#define BOARD_E1681 0x0691 -#define BOARD_E1670 0x0686 -#define BOARD_E1671 0x0687 -#define BOARD_E1690 0x069A -#define BOARD_E1740 0x06CC -#define BOARD_P2560 0x0A00 +#define BOARD_E1580 0x062C #define BOARD_E1780 0x06F4 #define BOARD_E1781 0x06F5 #define BOARD_E1792 0x0700 @@ -71,8 +54,6 @@ #define BOARD_SKU_0 0x0000 #define BOARD_SKU_100 0x0064 /* Panel board ID */ -#define BOARD_E1605 0x0645 - #define BOARD_E1627 0x065b #define BOARD_E1639 0x0667 #define BOARD_E1631 0x065f diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c deleted file mode 100644 index 4f28c5e172c6..000000000000 --- a/arch/arm/mach-tegra/tegra11_clocks.c +++ /dev/null @@ -1,8100 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11_clocks.c - * - * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/cpufreq.h> -#include <linux/syscore_ops.h> -#include <linux/platform_device.h> -#include <linux/clk/tegra.h> -#include <linux/tegra-soc.h> -#include <linux/tegra-powergate.h> - -#include <asm/clkdev.h> - -#include <mach/edp.h> -#include <mach/mc.h> - -#include "clock.h" -#include "iomap.h" -#include "dvfs.h" -#include "pm.h" -#include "sleep.h" -#include "devices.h" -#include "tegra11_emc.h" -#include "tegra_cl_dvfs.h" - -#define RST_DEVICES_L 0x004 -#define RST_DEVICES_H 0x008 -#define RST_DEVICES_U 0x00C -#define RST_DEVICES_V 0x358 -#define RST_DEVICES_W 0x35C -#define RST_DEVICES_X 0x28C -#define RST_DEVICES_SET_L 0x300 -#define RST_DEVICES_CLR_L 0x304 -#define RST_DEVICES_SET_V 0x430 -#define RST_DEVICES_CLR_V 0x434 -#define RST_DEVICES_SET_X 0x290 -#define RST_DEVICES_CLR_X 0x294 -#define RST_DEVICES_NUM 6 - -#define CLK_OUT_ENB_L 0x010 -#define CLK_OUT_ENB_H 0x014 -#define CLK_OUT_ENB_U 0x018 -#define CLK_OUT_ENB_V 0x360 -#define CLK_OUT_ENB_W 0x364 -#define CLK_OUT_ENB_X 0x280 -#define CLK_OUT_ENB_SET_L 0x320 -#define CLK_OUT_ENB_CLR_L 0x324 -#define CLK_OUT_ENB_SET_V 0x440 -#define CLK_OUT_ENB_CLR_V 0x444 -#define CLK_OUT_ENB_SET_X 0x284 -#define CLK_OUT_ENB_CLR_X 0x288 -#define CLK_OUT_ENB_NUM 6 - -#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */ -#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) - -#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) -#define PERIPH_CLK_TO_RST_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4) -#define PERIPH_CLK_TO_RST_SET_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \ - RST_DEVICES_SET_X, 8) -#define PERIPH_CLK_TO_RST_CLR_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \ - RST_DEVICES_CLR_X, 8) - -#define PERIPH_CLK_TO_ENB_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4) -#define PERIPH_CLK_TO_ENB_SET_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \ - CLK_OUT_ENB_SET_X, 8) -#define PERIPH_CLK_TO_ENB_CLR_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \ - CLK_OUT_ENB_CLR_X, 8) - -#define CLK_MASK_ARM 0x44 -#define MISC_CLK_ENB 0x48 - -#define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) -#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) -#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) -#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) -#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) -#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) -#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) -#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) -#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) -#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) - -#define PERIPH_CLK_SOURCE_I2S1 0x100 -#define PERIPH_CLK_SOURCE_EMC 0x19c -#define PERIPH_CLK_SOURCE_OSC 0x1fc -#define PERIPH_CLK_SOURCE_NUM1 \ - ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) - -#define PERIPH_CLK_SOURCE_G3D2 0x3b0 -#define PERIPH_CLK_SOURCE_SE 0x42c -#define PERIPH_CLK_SOURCE_NUM2 \ - ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) - -#define AUDIO_DLY_CLK 0x49c -#define AUDIO_SYNC_CLK_SPDIF 0x4b4 -#define PERIPH_CLK_SOURCE_NUM3 \ - ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) - -#define SPARE_REG 0x55c -#define PERIPH_CLK_SOURCE_XUSB_HOST 0x600 -#define PERIPH_CLK_SOURCE_SOC_THERM 0x644 -#define PERIPH_CLK_SOURCE_NUM4 \ - ((PERIPH_CLK_SOURCE_SOC_THERM - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1) - -#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ - PERIPH_CLK_SOURCE_NUM2 + \ - PERIPH_CLK_SOURCE_NUM3 + \ - PERIPH_CLK_SOURCE_NUM4) - -#define CPU_SOFTRST_CTRL 0x380 -#define CPU_SOFTRST_CTRL1 0x384 -#define CPU_SOFTRST_CTRL2 0x388 - -#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF -#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF -#define PERIPH_CLK_SOURCE_DIV_SHIFT 0 -#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 -#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 -#define PERIPH_CLK_UART_DIV_ENB (1<<24) -#define PERIPH_CLK_VI_SEL_EX_SHIFT 24 -#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) -#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) -#define PERIPH_CLK_DTV_POLARITY_INV (1<<25) - -#define AUDIO_SYNC_SOURCE_MASK 0x0F -#define AUDIO_SYNC_DISABLE_BIT 0x10 -#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) - -/* PLL common */ -#define PLL_BASE 0x0 -#define PLL_BASE_BYPASS (1<<31) -#define PLL_BASE_ENABLE (1<<30) -#define PLL_BASE_REF_ENABLE (1<<29) -#define PLL_BASE_OVERRIDE (1<<28) -#define PLL_BASE_LOCK (1<<27) -#define PLL_BASE_DIVP_MASK (0x7<<20) -#define PLL_BASE_DIVP_SHIFT 20 -#define PLL_BASE_DIVN_MASK (0x3FF<<8) -#define PLL_BASE_DIVN_SHIFT 8 -#define PLL_BASE_DIVM_MASK (0x1F) -#define PLL_BASE_DIVM_SHIFT 0 - -#define PLL_BASE_PARSE(pll, cfg, b) \ - do { \ - (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \ - (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \ - (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \ - } while (0) - -#define PLL_OUT_RATIO_MASK (0xFF<<8) -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_OVERRIDE (1<<2) -#define PLL_OUT_CLKEN (1<<1) -#define PLL_OUT_RESET_DISABLE (1<<0) - -#define PLL_MISC(c) \ - (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) -#define PLL_MISCN(c, n) \ - ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c)) -#define PLL_MISC_LOCK_ENABLE(c) \ - (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) - -#define PLL_MISC_DCCON_SHIFT 20 -#define PLL_MISC_CPCON_SHIFT 8 -#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) -#define PLL_MISC_LFCON_SHIFT 4 -#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) -#define PLL_MISC_VCOCON_SHIFT 0 -#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) - -#define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1) - -/* PLLU */ -#define PLLU_BASE_OVERRIDE (1<<24) -#define PLLU_BASE_POST_DIV (1<<20) - -/* PLLD */ -#define PLLD_BASE_CSI_CLKENABLE (1<<26) -#define PLLD_BASE_DSI_MUX_SHIFT 25 -#define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT) -#define PLLD_BASE_CSI_CLKSOURCE (1<<24) - -#define PLLD_MISC_DSI_CLKENABLE (1<<30) -#define PLLD_MISC_DIV_RST (1<<23) -#define PLLD_MISC_DCCON_SHIFT 12 - -#define PLLDU_LFCON 2 - -/* PLLC2 and PLLC3 (PLLCX) */ -#define PLLCX_USE_DYN_RAMP 0 -#define PLLCX_BASE_PHASE_LOCK (1<<26) -#define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT) -#define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT) -#define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT) -#define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) -#define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8)) - -#define PLLCX_MISC_STROBE (1<<31) -#define PLLCX_MISC_RESET (1<<30) -#define PLLCX_MISC_SDM_DIV_SHIFT 28 -#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) -#define PLLCX_MISC_FILT_DIV_SHIFT 26 -#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) -#define PLLCX_MISC_ALPHA_SHIFT 18 -#define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT) -#define PLLCX_MISC_KB_SHIFT 9 -#define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT) -#define PLLCX_MISC_KA_SHIFT 2 -#define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT) -#define PLLCX_MISC_VCO_GAIN_SHIFT 0 -#define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT) - -#define PLLCX_MISC_KOEF_LOW_RANGE \ - ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) - -#define PLLCX_MISC_DIV_LOW_RANGE \ - ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) -#define PLLCX_MISC_DIV_HIGH_RANGE \ - ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) - -#define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \ - PLLCX_MISC_KOEF_LOW_RANGE | \ - (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ - PLLCX_MISC_DIV_LOW_RANGE | \ - PLLCX_MISC_RESET) -#define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308 -#define PLLCX_MISC2_DEFAULT_VALUE 0x30211200 -#define PLLCX_MISC3_DEFAULT_VALUE 0x200 - -/* PLLX and PLLC (PLLXC)*/ -#define PLLXC_USE_DYN_RAMP 0 -#define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT) -#define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT) -#define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT) - -/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w, - and s/w usage is limited to 5 */ -#define PLLXC_PDIV_MAX 14 -#define PLLXC_SW_PDIV_MAX 5 - -/* PLLX */ -#define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 -#define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) -#define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 -#define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) -#define PLLX_MISC2_NDIV_NEW_SHIFT 8 -#define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) -#define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) -#define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) -#define PLLX_MISC2_CLAMP_NDIV (0x1 << 1) -#define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) - -#define PLLX_MISC3_IDDQ (0x1 << 3) - -#define PLLX_HW_CTRL_CFG 0x548 -#define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) - -/* PLLC */ -#define PLLC_BASE_LOCK_OVERRIDE (1<<28) - -#define PLLC_MISC_IDDQ (0x1 << 26) -#define PLLC_MISC_LOCK_ENABLE (0x1 << 24) - -#define PLLC_MISC1_CLAMP_NDIV (0x1 << 26) -#define PLLC_MISC1_EN_DYNRAMP (0x1 << 25) -#define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17 -#define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT) -#define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9 -#define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT) -#define PLLC_MISC1_NDIV_NEW_SHIFT 1 -#define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT) -#define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0) - -/* PLLM */ -#define PLLM_BASE_DIVP_MASK (0x1 << PLL_BASE_DIVP_SHIFT) -#define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT) -#define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT) -#define PLLM_PDIV_MAX 1 - -#define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10) -#define PLLM_MISC_IDDQ (0x1 << 5) -#define PLLM_MISC_LOCK_DISABLE (0x1 << 4) -#define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3) - -#define PMC_PLLP_WB0_OVERRIDE 0xf8 -#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) -#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11) - -/* M, N layout for PLLM override and base registers are the same */ -#define PMC_PLLM_WB0_OVERRIDE 0x1dc - -#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 -#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0x1 << 27) - -/* PLLRE */ -#define PLLRE_BASE_DIVP_SHIFT 16 -#define PLLRE_BASE_DIVP_MASK (0xF << PLLRE_BASE_DIVP_SHIFT) -#define PLLRE_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT) -#define PLLRE_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT) - -/* PLLRE has 4-bit PDIV, but entry 15 is not allowed in h/w, - and s/w usage is limited to 5 */ -#define PLLRE_PDIV_MAX 14 -#define PLLRE_SW_PDIV_MAX 5 - -#define PLLRE_MISC_LOCK_ENABLE (0x1 << 30) -#define PLLRE_MISC_LOCK_OVERRIDE (0x1 << 29) -#define PLLRE_MISC_LOCK (0x1 << 24) -#define PLLRE_MISC_IDDQ (0x1 << 16) - -#define OUT_OF_TABLE_CPCON 0x8 - -#define SUPER_CLK_MUX 0x00 -#define SUPER_STATE_SHIFT 28 -#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) -#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) -#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) -#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) -#define SUPER_LP_DIV2_BYPASS (0x1 << 16) -#define SUPER_SOURCE_MASK 0xF -#define SUPER_FIQ_SOURCE_SHIFT 12 -#define SUPER_IRQ_SOURCE_SHIFT 8 -#define SUPER_RUN_SOURCE_SHIFT 4 -#define SUPER_IDLE_SOURCE_SHIFT 0 - -#define SUPER_CLK_DIVIDER 0x04 -#define SUPER_CLOCK_DIV_U71_SHIFT 16 -#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) - -#define BUS_CLK_DISABLE (1<<3) -#define BUS_CLK_DIV_MASK 0x3 - -#define PMC_CTRL 0x0 - #define PMC_CTRL_BLINK_ENB (1 << 7) - -#define PMC_DPD_PADS_ORIDE 0x1c - #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) - -#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 -#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff -#define PMC_BLINK_TIMER_ENB (1 << 15) -#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 -#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff - -#define UTMIP_PLL_CFG2 0x488 -#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) -#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25) - -#define UTMIP_PLL_CFG1 0x484 -#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) -#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) -#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15) -#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) -#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) -#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17) -#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) - -/* PLLE */ -#define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29) -#define PLLE_BASE_DIVCML_SHIFT 24 -#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT) -#define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT) -#define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT) - -/* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */ -#define PLLE_CMLDIV_MAX 14 - -#define PLLE_MISC_READY (1<<15) -#define PLLE_MISC_IDDQ_SW_CTRL (1<<14) -#define PLLE_MISC_IDDQ_SW_VALUE (1<<13) -#define PLLE_MISC_LOCK (1<<11) -#define PLLE_MISC_LOCK_ENABLE (1<<9) -#define PLLE_MISC_PLLE_PTS (1<<8) -#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 -#define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT) -#define PLLE_MISC_VREG_CTRL_SHIFT 2 -#define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT) - -#define PLLE_SS_CTRL 0x68 -#define PLLE_SS_INCINTRV_SHIFT 24 -#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT) -#define PLLE_SS_INC_SHIFT 16 -#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT) -#define PLLE_SS_CNTL_INVERT (0x1 << 15) -#define PLLE_SS_CNTL_CENTER (0x1 << 14) -#define PLLE_SS_CNTL_SSC_BYP (0x1 << 12) -#define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11) -#define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10) -#define PLLE_SS_MAX_SHIFT 0 -#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT) -#define PLLE_SS_COEFFICIENTS_MASK \ - (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) -#define PLLE_SS_COEFFICIENTS_VAL \ - ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ - (0x25<<PLLE_SS_MAX_SHIFT)) -#define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\ - PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS) - -#define PLLE_AUX 0x48c -#define PLLE_AUX_PLLRE_SEL (1<<28) -#define PLLE_AUX_SEQ_STATE_SHIFT 26 -#define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT) -#define PLLE_AUX_SEQ_START_STATE (1<<25) -#define PLLE_AUX_SEQ_ENABLE (1<<24) -#define PLLE_AUX_SS_SWCTL (1<<6) -#define PLLE_AUX_ENABLE_SWCTL (1<<4) -#define PLLE_AUX_USE_LOCKDET (1<<3) -#define PLLE_AUX_PLLP_SEL (1<<2) - -/* USB PLLs PD HW controls */ -#define XUSBIO_PLL_CFG0 0x51c -#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25) -#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24) -#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6) -#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2) -#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0) - -/* XUSB PLL PAD controls */ -#define XUSB_PADCTL_IOPHY_PLL0_CTL1 0x30 -#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD (1<<3) -#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ (1<<0) - -#define UTMIPLL_HW_PWRDN_CFG0 0x52c -#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25) -#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24) -#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6) -#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5) -#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4) -#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2) -#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1) -#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0) - -#define PLLU_HW_PWRDN_CFG0 0x530 -#define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25) -#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24) -#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6) -#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2) -#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0) - -#define USB_PLLS_SEQ_START_STATE (1<<25) -#define USB_PLLS_SEQ_ENABLE (1<<24) -#define USB_PLLS_USE_LOCKDET (1<<6) -#define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0)) - -/* CPU clock trimmers */ -#define CPU_FINETRIM_BYP 0x4d0 -#define CPU_FINETRIM_SELECT 0x4d4 -#define CPU_FINETRIM_DR 0x4d8 -#define CPU_FINETRIM_DF 0x4dc -#define CPU_FINETRIM_F 0x4e0 -#define CPU_FINETRIM_R 0x4e4 - -/* DFLL */ -#define DFLL_BASE 0x2f4 -#define DFLL_BASE_RESET (1<<0) - -#define LVL2_CLK_GATE_OVRE 0x554 - -#define ROUND_DIVIDER_UP 0 -#define ROUND_DIVIDER_DOWN 1 -#define DIVIDER_1_5_ALLOWED 0 - -/* Tegra CPU clock and reset control regs */ -#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c -#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 -#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 -#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c -#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 - -#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) -#define CPU_RESET(cpu) (0x111001ul << (cpu)) - -/* PLLP default fixed rate in h/w controlled mode */ -#define PLLP_DEFAULT_FIXED_RATE 216000000 - -/* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */ -#define USE_PLLE_INPUT_PLLRE 0 - -static bool tegra11_is_dyn_ramp(struct clk *c, - unsigned long rate, bool from_vco_min); -static void tegra11_pllp_init_dependencies(unsigned long pllp_rate); -static unsigned long tegra11_clk_shared_bus_update(struct clk *bus, - struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap); -static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus, - unsigned long rate, unsigned long ceiling); - -static bool detach_shared_bus; -module_param(detach_shared_bus, bool, 0644); - -static int use_dfll; - -/** -* Structure defining the fields for USB UTMI clocks Parameters. -*/ -struct utmi_clk_param -{ - /* Oscillator Frequency in KHz */ - u32 osc_frequency; - /* UTMIP PLL Enable Delay Count */ - u8 enable_delay_count; - /* UTMIP PLL Stable count */ - u8 stable_count; - /* UTMIP PLL Active delay count */ - u8 active_delay_count; - /* UTMIP PLL Xtal frequency count */ - u8 xtal_freq_count; -}; - -static const struct utmi_clk_param utmi_parameters[] = -{ -/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ - {13000000, 0x02, 0x33, 0x05, 0x7F}, - {19200000, 0x03, 0x4B, 0x06, 0xBB}, - {12000000, 0x02, 0x2F, 0x04, 0x76}, - {26000000, 0x04, 0x66, 0x09, 0xFE}, - {16800000, 0x03, 0x41, 0x0A, 0xA4}, -}; - -static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); -static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); -static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE); - -#define MISC_GP_TRANSACTOR_SCRATCH_0 0x864 -#define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1) -#define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2) -#define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3) - -/* - * Some peripheral clocks share an enable bit, so refcount the enable bits - * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates - * with lock - */ -static DEFINE_SPINLOCK(periph_refcount_lock); -static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; - -#define clk_writel(value, reg) \ - __raw_writel(value, reg_clk_base + (reg)) -#define clk_readl(reg) \ - __raw_readl(reg_clk_base + (reg)) -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) -#define xusb_padctl_writel(value, reg) \ - __raw_writel(value, reg_xusb_padctl_base + (reg)) -#define xusb_padctl_readl(reg) \ - __raw_readl(reg_xusb_padctl_base + (reg)) - -#define clk_writel_delay(value, reg) \ - do { \ - __raw_writel((value), reg_clk_base + (reg)); \ - __raw_readl(reg_clk_base + (reg)); \ - udelay(2); \ - } while (0) - -#define pll_writel_delay(value, reg) \ - do { \ - __raw_writel((value), reg_clk_base + (reg)); \ - __raw_readl(reg_clk_base + (reg)); \ - udelay(1); \ - } while (0) - - -static inline int clk_set_div(struct clk *c, u32 n) -{ - return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); -} - -static inline u32 periph_clk_to_reg( - struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs) -{ - u32 reg = c->u.periph.clk_num / 32; - BUG_ON(reg >= RST_DEVICES_NUM); - if (reg < 3) - reg = reg_L + (reg * offs); - else if (reg < 5) - reg = reg_V + ((reg - 3) * offs); - else - reg = reg_X; - return reg; -} - -static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate, - u32 max_x, - u32 flags, u32 round_mode) -{ - s64 divider_ux1 = parent_rate; - if (!rate) - return -EINVAL; - - if (!(flags & DIV_U71_INT)) - divider_ux1 *= 2; - if (round_mode == ROUND_DIVIDER_UP) - divider_ux1 += rate - 1; - do_div(divider_ux1, rate); - if (flags & DIV_U71_INT) - divider_ux1 *= 2; - - if (divider_ux1 - 2 < 0) - return 0; - - if (divider_ux1 - 2 > max_x) - return -EINVAL; - -#if !DIVIDER_1_5_ALLOWED - if (divider_ux1 == 3) - divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2; -#endif - return divider_ux1 - 2; -} - -static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, - u32 flags, u32 round_mode) -{ - return clk_div_x1_get_divider(parent_rate, rate, 0xFF, - flags, round_mode); -} - -static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate, - u32 flags, u32 round_mode) -{ - return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF, - flags, round_mode); -} - -static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) -{ - s64 divider_u16; - - divider_u16 = parent_rate; - if (!rate) - return -EINVAL; - divider_u16 += rate - 1; - do_div(divider_u16, rate); - - if (divider_u16 - 1 < 0) - return 0; - - if (divider_u16 - 1 > 0xFFFF) - return -EINVAL; - - return divider_u16 - 1; -} - -static inline bool bus_user_is_slower(struct clk *a, struct clk *b) -{ - return a->u.shared_bus_user.client->max_rate * a->div < - b->u.shared_bus_user.client->max_rate * b->div; -} - -static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b) -{ - return a->u.shared_bus_user.rate * a->div < - b->u.shared_bus_user.rate * b->div; -} - -/* clk_m functions */ -static unsigned long tegra11_clk_m_autodetect_rate(struct clk *c) -{ - u32 osc_ctrl = clk_readl(OSC_CTRL); - u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; - u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; - - c->rate = tegra_clk_measure_input_freq(); - switch (c->rate) { - case 12000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 13000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 19200000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 26000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 16800000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 38400000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); - break; - case 48000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); - break; - case 115200: /* fake 13M for QT */ - case 230400: /* fake 13M for QT */ - auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; - c->rate = 13000000; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - default: - pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); - BUG(); - } - clk_writel(auto_clock_control, OSC_CTRL); - return c->rate; -} - -static void tegra11_clk_m_init(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - tegra11_clk_m_autodetect_rate(c); -} - -static int tegra11_clk_m_enable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - return 0; -} - -static void tegra11_clk_m_disable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - WARN(1, "Attempting to disable main SoC clock\n"); -} - -static struct clk_ops tegra_clk_m_ops = { - .init = tegra11_clk_m_init, - .enable = tegra11_clk_m_enable, - .disable = tegra11_clk_m_disable, -}; - -static struct clk_ops tegra_clk_m_div_ops = { - .enable = tegra11_clk_m_enable, -}; - -/* PLL reference divider functions */ -static void tegra11_pll_ref_init(struct clk *c) -{ - u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; - pr_debug("%s on clock %s\n", __func__, c->name); - - switch (pll_ref_div) { - case OSC_CTRL_PLL_REF_DIV_1: - c->div = 1; - break; - case OSC_CTRL_PLL_REF_DIV_2: - c->div = 2; - break; - case OSC_CTRL_PLL_REF_DIV_4: - c->div = 4; - break; - default: - pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); - BUG(); - } - c->mul = 1; - c->state = ON; -} - -static struct clk_ops tegra_pll_ref_ops = { - .init = tegra11_pll_ref_init, - .enable = tegra11_clk_m_enable, - .disable = tegra11_clk_m_disable, -}; - -/* super clock functions */ -/* "super clocks" on tegra11x have two-stage muxes, fractional 7.1 divider and - * clock skipping super divider. We will ignore the clock skipping divider, - * since we can't lower the voltage when using the clock skip, but we can if - * we lower the PLL frequency. Note that skipping divider can and will be used - * by thermal control h/w for automatic throttling. There is also a 7.1 divider - * that most CPU super-clock inputs can be routed through. We will not use it - * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path - * and possible concurrency access issues with thermal h/w (7.1 divider setting - * share register with clock skipping divider) - */ -static void tegra11_super_clk_init(struct clk *c) -{ - u32 val; - int source; - int shift; - const struct clk_mux_sel *sel; - val = clk_readl(c->reg + SUPER_CLK_MUX); - c->state = ON; - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - source = (val >> shift) & SUPER_SOURCE_MASK; - - /* - * Enforce PLLX DIV2 bypass setting as early as possible. It is always - * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In - * case of booting on LP CPU, cclk_lp will be updated during the cpu - * rate change after boot, and cclk_g after the cluster switch.) - */ - if ((c->flags & DIV_U71) && (!is_lp_cluster())) { - val |= SUPER_LP_DIV2_BYPASS; - clk_writel_delay(val, c->reg); - } - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->value == source) - break; - } - BUG_ON(sel->input == NULL); - c->parent = sel->input; - - /* Update parent in case when LP CPU PLLX DIV2 bypassed */ - if ((c->flags & DIV_2) && (c->parent->flags & PLLX) && - (val & SUPER_LP_DIV2_BYPASS)) - c->parent = c->parent->parent; - - if (c->flags & DIV_U71) { - c->mul = 2; - c->div = 2; - - /* - * Make sure 7.1 divider is 1:1; clear h/w skipper control - - * it will be enabled by soctherm later - */ - val = clk_readl(c->reg + SUPER_CLK_DIVIDER); - BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK); - val = 0; - clk_writel(val, c->reg + SUPER_CLK_DIVIDER); - } - else - clk_writel(0, c->reg + SUPER_CLK_DIVIDER); -} - -static int tegra11_super_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra11_super_clk_disable(struct clk *c) -{ - /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and - geared up g-mode super clock - mode switch may request to disable - either of them; accept request with no affect on h/w */ -} - -static int tegra11_super_clk_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - const struct clk_mux_sel *sel; - int shift; - - val = clk_readl(c->reg + SUPER_CLK_MUX); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - /* For LP mode super-clock switch between PLLX direct - and divided-by-2 outputs is allowed only when other - than PLLX clock source is current parent */ - if ((c->flags & DIV_2) && (p->flags & PLLX) && - ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) { - if (c->parent->flags & PLLX) - return -EINVAL; - val ^= SUPER_LP_DIV2_BYPASS; - clk_writel_delay(val, c->reg); - } - val &= ~(SUPER_SOURCE_MASK << shift); - val |= (sel->value & SUPER_SOURCE_MASK) << shift; - - if (c->flags & DIV_U71) { - /* Make sure 7.1 divider is 1:1 */ - u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER); - BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK); - } - - if (c->refcnt) - clk_enable(p); - - clk_writel_delay(val, c->reg); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - return -EINVAL; -} - -/* - * Do not use super clocks "skippers", since dividing using a clock skipper - * does not allow the voltage to be scaled down. Instead adjust the rate of - * the parent clock. This requires that the parent of a super clock have no - * other children, otherwise the rate will change underneath the other - * children. - */ -static int tegra11_super_clk_set_rate(struct clk *c, unsigned long rate) -{ - /* In tegra11_cpu_clk_set_plls() and tegra11_sbus_cmplx_set_rate() - * this call is skipped by directly setting rate of source plls. If we - * ever use 7.1 divider at other than 1:1 setting, or exercise s/w - * skipper control, not only this function, but cpu and sbus set_rate - * APIs should be changed accordingly. - */ - return clk_set_rate(c->parent, rate); -} - -#ifdef CONFIG_PM_SLEEP -static void tegra11_super_clk_resume(struct clk *c, struct clk *backup, - u32 setting) -{ - u32 val; - const struct clk_mux_sel *sel; - int shift; - - /* For sclk and cclk_g super clock just restore saved value */ - if (!(c->flags & DIV_2)) { - clk_writel_delay(setting, c->reg); - return; - } - - /* - * For cclk_lp supper clock: switch to backup (= not PLLX) source, - * safely restore PLLX DIV2 bypass, and only then restore full - * setting - */ - val = clk_readl(c->reg); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == backup) { - val &= ~(SUPER_SOURCE_MASK << shift); - val |= (sel->value & SUPER_SOURCE_MASK) << shift; - - BUG_ON(backup->flags & PLLX); - clk_writel_delay(val, c->reg); - - val &= ~SUPER_LP_DIV2_BYPASS; - val |= (setting & SUPER_LP_DIV2_BYPASS); - clk_writel_delay(val, c->reg); - clk_writel_delay(setting, c->reg); - return; - } - } - BUG(); -} -#endif - -static struct clk_ops tegra_super_ops = { - .init = tegra11_super_clk_init, - .enable = tegra11_super_clk_enable, - .disable = tegra11_super_clk_disable, - .set_parent = tegra11_super_clk_set_parent, - .set_rate = tegra11_super_clk_set_rate, -}; - -/* virtual cpu clock functions */ -/* some clocks can not be stopped (cpu, memory bus) while the SoC is running. - To change the frequency of these clocks, the parent pll may need to be - reprogrammed, so the clock must be moved off the pll, the pll reprogrammed, - and then the clock moved back to the pll. To hide this sequence, a virtual - clock handles it. - */ -static void tegra11_cpu_clk_init(struct clk *c) -{ - c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF; -} - -static int tegra11_cpu_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra11_cpu_clk_disable(struct clk *c) -{ - /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock - and geared up g-mode clock - mode switch may request to disable - either of them; accept request with no affect on h/w */ -} - -static int tegra11_cpu_clk_set_plls(struct clk *c, unsigned long rate, - unsigned long old_rate) -{ - int ret = 0; - bool on_main = false; - unsigned long backup_rate, main_rate; - unsigned long vco_min = c->u.cpu.main->u.pll.vco_min; - - /* - * Take an extra reference to the main pll so it doesn't turn off when - * we move the cpu off of it. If possible, use main pll dynamic ramp - * to reach target rate in one shot. Otherwise, use dynamic ramp to - * lower current rate to pll VCO minimum level before switching to - * backup source. - */ - if (c->parent->parent == c->u.cpu.main) { - bool dramp = (rate > c->u.cpu.backup_rate) && - tegra11_is_dyn_ramp(c->u.cpu.main, rate, false); - clk_enable(c->u.cpu.main); - on_main = true; - - if (dramp || - ((old_rate > vco_min) && - tegra11_is_dyn_ramp(c->u.cpu.main, vco_min, false))) { - main_rate = dramp ? rate : vco_min; - ret = clk_set_rate(c->u.cpu.main, main_rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", main_rate, c->u.cpu.main->name); - goto out; - } - if (dramp) - goto out; - } else if (old_rate > vco_min) { -#if PLLXC_USE_DYN_RAMP - pr_warn("No dynamic ramp down: %s: %lu to %lu\n", - c->u.cpu.main->name, old_rate, vco_min); -#endif - } - } - - /* Switch to back-up source, and stay on it if target rate is below - backup rate */ - if (c->parent->parent != c->u.cpu.backup) { - ret = clk_set_parent(c->parent, c->u.cpu.backup); - if (ret) { - pr_err("Failed to switch cpu to %s\n", - c->u.cpu.backup->name); - goto out; - } - } - - backup_rate = min(rate, c->u.cpu.backup_rate); - if (backup_rate != clk_get_rate_locked(c)) { - ret = clk_set_rate(c->u.cpu.backup, backup_rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on backup source\n", - backup_rate); - goto out; - } - } - if (rate == backup_rate) - goto out; - - /* Switch from backup source to main at rate not exceeding pll VCO - minimum. Use dynamic ramp to reach target rate if it is above VCO - minimum. */ - main_rate = rate; - if (rate > vco_min) { - if (tegra11_is_dyn_ramp(c->u.cpu.main, rate, true)) - main_rate = vco_min; -#if PLLXC_USE_DYN_RAMP - else - pr_warn("No dynamic ramp up: %s: %lu to %lu\n", - c->u.cpu.main->name, vco_min, rate); -#endif - } - - ret = clk_set_rate(c->u.cpu.main, main_rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", main_rate, c->u.cpu.main->name); - goto out; - } - ret = clk_set_parent(c->parent, c->u.cpu.main); - if (ret) { - pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name); - goto out; - } - if (rate != main_rate) { - ret = clk_set_rate(c->u.cpu.main, rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", rate, c->u.cpu.main->name); - goto out; - } - } - -out: - if (on_main) - clk_disable(c->u.cpu.main); - - return ret; -} - -static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate, - unsigned long old_rate) -{ - int ret; - struct clk *dfll = c->u.cpu.dynamic; - unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min; - - /* dfll rate request */ - ret = clk_set_rate(dfll, rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", rate, dfll->name); - return ret; - } - - /* 1st time - switch to dfll */ - if (c->parent->parent != dfll) { - if (max(old_rate, rate) < dfll_rate_min) { - /* set interim cpu dvfs rate at dfll_rate_min to - prevent voltage drop below dfll Vmin */ - ret = tegra_dvfs_set_rate(c, dfll_rate_min); - if (ret) { - pr_err("Failed to set cpu dvfs rate %lu\n", - dfll_rate_min); - return ret; - } - } - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true); - ret = clk_set_parent(c->parent, dfll); - if (ret) { - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - pr_err("Failed to switch cpu to %s\n", dfll->name); - return ret; - } - ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate); - - /* prevent legacy dvfs voltage scaling */ - tegra_dvfs_dfll_mode_set(c->dvfs, rate); - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - } - return 0; -} - -static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate, - unsigned long old_rate) -{ - int ret; - struct clk *pll; - struct clk *dfll = c->u.cpu.dynamic; - unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min; - - rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost); - pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main; - dfll_rate_min = max(rate, dfll_rate_min); - - /* set target rate last time in dfll mode */ - if (old_rate != dfll_rate_min) { - ret = tegra_dvfs_set_rate(c, dfll_rate_min); - if (!ret) - ret = clk_set_rate(dfll, dfll_rate_min); - - if (ret) { - pr_err("Failed to set cpu rate %lu on source %s\n", - dfll_rate_min, dfll->name); - return ret; - } - } - - /* unlock dfll - release volatge rail control */ - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true); - ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0); - if (ret) { - pr_err("Failed to unlock %s\n", dfll->name); - goto back_to_dfll; - } - - /* restore legacy dvfs operations and set appropriate voltage */ - ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min); - if (ret) { - pr_err("Failed to set cpu rail for rate %lu\n", rate); - goto back_to_dfll; - } - - /* set pll to target rate and return to pll source */ - ret = clk_set_rate(pll, rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", rate, pll->name); - goto back_to_dfll; - } - ret = clk_set_parent(c->parent, pll); - if (ret) { - pr_err("Failed to switch cpu to %s\n", pll->name); - goto back_to_dfll; - } - - /* If going up, adjust voltage here (down path is taken care of by the - framework after set rate exit) */ - if (old_rate <= rate) - tegra_dvfs_set_rate(c, rate); - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - return 0; - -back_to_dfll: - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - tegra_dvfs_dfll_mode_set(c->dvfs, old_rate); - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - return ret; -} - -static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long old_rate = clk_get_rate_locked(c); - bool has_dfll = c->u.cpu.dynamic && - (c->u.cpu.dynamic->state != UNINITIALIZED); - bool is_dfll = c->parent->parent == c->u.cpu.dynamic; - - /* On SILICON allow CPU rate change only if cpu regulator is connected. - Ignore regulator connection on FPGA platforms. */ -#ifdef CONFIG_TEGRA_SILICON_PLATFORM - if (c->dvfs) { - if (!c->dvfs->dvfs_rail) - return -ENOSYS; - else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) && - (c->boot_rate < rate)) { - WARN(1, "Increasing CPU rate while regulator is not" - " ready is not allowed\n"); - return -ENOSYS; - } - } -#endif - if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) { - if (tegra_dvfs_is_dfll_range(c->dvfs, rate)) - return tegra11_cpu_clk_dfll_on(c, rate, old_rate); - else if (is_dfll) - return tegra11_cpu_clk_dfll_off(c, rate, old_rate); - } - return tegra11_cpu_clk_set_plls(c, rate, old_rate); -} - -static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate) -{ - unsigned long max_rate = c->max_rate; - - /* Remove dfll boost to maximum rate when running on PLL */ - if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate)) - max_rate -= c->dvfs->dfll_data.max_rate_boost; - - if (rate > max_rate) - rate = max_rate; - else if (rate < c->min_rate) - rate = c->min_rate; - return rate; -} - -static struct clk_ops tegra_cpu_ops = { - .init = tegra11_cpu_clk_init, - .enable = tegra11_cpu_clk_enable, - .disable = tegra11_cpu_clk_disable, - .set_rate = tegra11_cpu_clk_set_rate, - .round_rate = tegra11_cpu_clk_round_rate, -}; - - -static void tegra11_cpu_cmplx_clk_init(struct clk *c) -{ - int i = !!is_lp_cluster(); - - BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G); - BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP); - c->parent = c->inputs[i].input; -} - -/* cpu complex clock provides second level vitualization (on top of - cpu virtual cpu rate control) in order to hide the CPU mode switch - sequence */ -#if PARAMETERIZE_CLUSTER_SWITCH -static unsigned int switch_delay; -static unsigned int switch_flags; -static DEFINE_SPINLOCK(parameters_lock); - -void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags) -{ - spin_lock(¶meters_lock); - switch_delay = us; - switch_flags = flags; - spin_unlock(¶meters_lock); -} -#endif - -static int tegra11_cpu_cmplx_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra11_cpu_cmplx_clk_disable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - - /* oops - don't disable the CPU complex clock! */ - BUG(); -} - -static int tegra11_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long flags; - int ret; - struct clk *parent = c->parent; - - if (!parent->ops || !parent->ops->set_rate) - return -ENOSYS; - - clk_lock_save(parent, &flags); - - ret = clk_set_rate_locked(parent, rate); - - clk_unlock_restore(parent, &flags); - - return ret; -} - -static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) -{ - int ret; - unsigned int flags, delay; - const struct clk_mux_sel *sel; - unsigned long rate = clk_get_rate(c->parent); - struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic; - struct clk *p_source_old = NULL; - struct clk *p_source; - - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G)); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) - break; - } - if (!sel->input) - return -EINVAL; - -#if PARAMETERIZE_CLUSTER_SWITCH - spin_lock(¶meters_lock); - flags = switch_flags; - delay = switch_delay; - switch_flags = 0; - spin_unlock(¶meters_lock); - - if (flags) { - /* over/under-clocking after switch - allow, but update rate */ - if ((rate > p->max_rate) || (rate < p->min_rate)) { - rate = rate > p->max_rate ? p->max_rate : p->min_rate; - ret = clk_set_rate(c->parent, rate); - if (ret) { - pr_err("%s: Failed to set rate %lu for %s\n", - __func__, rate, p->name); - return ret; - } - } - } else -#endif - { - if (rate > p->max_rate) { /* over-clocking - no switch */ - pr_warn("%s: No %s mode switch to %s at rate %lu\n", - __func__, c->name, p->name, rate); - return -ECANCELED; - } - flags = TEGRA_POWER_CLUSTER_IMMEDIATE; - flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT; - delay = 0; - } - flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP : - TEGRA_POWER_CLUSTER_G; - - if (p == c->parent) { - if (flags & TEGRA_POWER_CLUSTER_FORCE) { - /* Allow parameterized switch to the same mode */ - ret = tegra_cluster_control(delay, flags); - if (ret) - pr_err("%s: Failed to force %s mode to %s\n", - __func__, c->name, p->name); - return ret; - } - return 0; /* already switched - exit */ - } - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true); - if (c->parent->parent->parent == dfll) { - /* G (DFLL selected as clock source) => LP switch: - * turn DFLL into open loop mode ("release" VDD_CPU rail) - * select target p_source for LP, and get its rate ready - */ - ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0); - if (ret) - goto abort; - - p_source = rate <= p->u.cpu.backup_rate ? - p->u.cpu.backup : p->u.cpu.main; - ret = clk_set_rate(p_source, rate); - if (ret) - goto abort; - } else if ((p->parent->parent == dfll) || - (p->dvfs && tegra_dvfs_is_dfll_range(p->dvfs, rate))) { - /* LP => G (DFLL selected as clock source) switch: - * set DFLL rate ready (DFLL is still disabled) - * (set target p_source as dfll, G source is already selected) - */ - p_source = dfll; - ret = clk_set_rate(dfll, - tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate : - max(rate, p->dvfs->dfll_data.use_dfll_rate_min)); - if (ret) - goto abort; - - ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail, dfll); - if (ret) - goto abort; - - } else - /* DFLL is not selected on either side of the switch: - * set target p_source equal to current clock source - */ - p_source = c->parent->parent->parent; - - /* Switch new parent to target clock source if necessary */ - if (p->parent->parent != p_source) { - clk_enable(p->parent->parent); - clk_enable(p->parent); - p_source_old = p->parent->parent; - ret = clk_set_parent(p->parent, p_source); - if (ret) { - pr_err("%s: Failed to set parent %s for %s\n", - __func__, p_source->name, p->name); - goto abort; - } - } - - /* Enabling new parent scales new mode voltage rail in advanvce - before the switch happens (if p_source is DFLL: open loop mode) */ - if (c->refcnt) - clk_enable(p); - - /* switch CPU mode */ - ret = tegra_cluster_control(delay, flags); - if (ret) { - if (c->refcnt) - clk_disable(p); - pr_err("%s: Failed to switch %s mode to %s\n", - __func__, c->name, p->name); - goto abort; - } - - /* - * Lock DFLL now (resume closed loop VDD_CPU control). - * G CPU operations are resumed on DFLL if it was the last G CPU - * clock source, or if resume rate is in DFLL usage range in case - * when auto-switch between PLL and DFLL is enabled. - */ - if (p_source == dfll) { - if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) { - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - } else { - clk_set_rate(dfll, rate); - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - tegra_dvfs_dfll_mode_set(p->dvfs, rate); - } - } - - /* Disabling old parent scales old mode voltage rail */ - if (c->refcnt) - clk_disable(c->parent); - if (p_source_old) { - clk_disable(p->parent); - clk_disable(p_source_old); - } - - clk_reparent(c, p); - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - return 0; - -abort: - /* Re-lock DFLL if necessary after aborted switch */ - if (c->parent->parent->parent == dfll) { - clk_set_rate(dfll, rate); - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - } - if (p_source_old) { - clk_disable(p->parent); - clk_disable(p_source_old); - } - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - - pr_err("%s: aborted switch from %s to %s\n", - __func__, c->parent->name, p->name); - return ret; -} - -static long tegra11_cpu_cmplx_round_rate(struct clk *c, - unsigned long rate) -{ - return clk_round_rate(c->parent, rate); -} - -static struct clk_ops tegra_cpu_cmplx_ops = { - .init = tegra11_cpu_cmplx_clk_init, - .enable = tegra11_cpu_cmplx_clk_enable, - .disable = tegra11_cpu_cmplx_clk_disable, - .set_rate = tegra11_cpu_cmplx_clk_set_rate, - .set_parent = tegra11_cpu_cmplx_clk_set_parent, - .round_rate = tegra11_cpu_cmplx_round_rate, -}; - -/* virtual cop clock functions. Used to acquire the fake 'cop' clock to - * reset the COP block (i.e. AVP) */ -static void tegra11_cop_clk_reset(struct clk *c, bool assert) -{ - unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L; - - pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); - clk_writel(1 << 1, reg); -} - -static struct clk_ops tegra_cop_ops = { - .reset = tegra11_cop_clk_reset, -}; - -/* bus clock functions */ -static void tegra11_bus_clk_init(struct clk *c) -{ - u32 val = clk_readl(c->reg); - c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; - c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; - c->mul = 1; -} - -static int tegra11_bus_clk_enable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - val &= ~(BUS_CLK_DISABLE << c->reg_shift); - clk_writel(val, c->reg); - return 0; -} - -static void tegra11_bus_clk_disable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - val |= BUS_CLK_DISABLE << c->reg_shift; - clk_writel(val, c->reg); -} - -static int tegra11_bus_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val = clk_readl(c->reg); - unsigned long parent_rate = clk_get_rate(c->parent); - int i; - for (i = 1; i <= 4; i++) { - if (rate >= parent_rate / i) { - val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); - val |= (i - 1) << c->reg_shift; - clk_writel(val, c->reg); - c->div = i; - c->mul = 1; - return 0; - } - } - return -EINVAL; -} - -static struct clk_ops tegra_bus_ops = { - .init = tegra11_bus_clk_init, - .enable = tegra11_bus_clk_enable, - .disable = tegra11_bus_clk_disable, - .set_rate = tegra11_bus_clk_set_rate, -}; - -/* Virtual system bus complex clock is used to hide the sequence of - changing sclk/hclk/pclk parents and dividers to configure requested - sclk target rate. */ -static void tegra11_sbus_cmplx_init(struct clk *c) -{ - unsigned long rate; - - c->max_rate = c->parent->max_rate; - c->min_rate = c->parent->min_rate; - - /* Threshold must be an exact proper factor of low range parent, - and both low/high range parents have 7.1 fractional dividers */ - rate = clk_get_rate(c->u.system.sclk_low->parent); - if (c->u.system.threshold) { - BUG_ON(c->u.system.threshold > rate) ; - BUG_ON((rate % c->u.system.threshold) != 0); - } - BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71)); - BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71)); -} - -/* This special sbus round function is implemented because: - * - * (a) sbus complex clock source is selected automatically based on rate - * - * (b) since sbus is a shared bus, and its frequency is set to the highest - * enabled shared_bus_user clock, the target rate should be rounded up divider - * ladder (if max limit allows it) - for pll_div and peripheral_div common is - * rounding down - special case again. - * - * Note that final rate is trimmed (not rounded up) to avoid spiraling up in - * recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before - * actually setting divider rate. - */ -static long tegra11_sbus_cmplx_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - int divider; - unsigned long source_rate, round_rate; - struct clk *new_parent; - - rate = max(rate, c->min_rate); - - new_parent = (rate <= c->u.system.threshold) ? - c->u.system.sclk_low : c->u.system.sclk_high; - source_rate = clk_get_rate(new_parent->parent); - - divider = clk_div71_get_divider(source_rate, rate, - new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP); - if (divider < 0) - return c->min_rate; - - if (divider == 1) - divider = 0; - - round_rate = source_rate * 2 / (divider + 2); - if (round_rate > c->max_rate) { - divider += new_parent->flags & DIV_U71_INT ? 2 : 1; -#if !DIVIDER_1_5_ALLOWED - divider = max(2, divider); -#endif - round_rate = source_rate * 2 / (divider + 2); - } - - if (new_parent == c->u.system.sclk_high) { - /* Prevent oscillation across threshold */ - if (round_rate <= c->u.system.threshold) - round_rate = c->u.system.threshold; - } - return round_rate; -} - -static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate) -{ - return tegra11_sbus_cmplx_round_updown(c, rate, true); -} - -static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - struct clk *new_parent; - - /* - select the appropriate sclk parent - - keep hclk at the same rate as sclk - - set pclk at 1:2 rate of hclk unless pclk minimum is violated, - in the latter case switch to 1:1 ratio */ - - if (rate >= c->u.system.pclk->min_rate * 2) { - ret = clk_set_div(c->u.system.pclk, 2); - if (ret) { - pr_err("Failed to set 1 : 2 pclk divider\n"); - return ret; - } - } - - new_parent = (rate <= c->u.system.threshold) ? - c->u.system.sclk_low : c->u.system.sclk_high; - - ret = clk_set_rate(new_parent, rate + 1); - if (ret) { - pr_err("Failed to set sclk source %s to %lu\n", - new_parent->name, rate); - return ret; - } - - if (new_parent != clk_get_parent(c->parent)) { - ret = clk_set_parent(c->parent, new_parent); - if (ret) { - pr_err("Failed to switch sclk source to %s\n", - new_parent->name); - return ret; - } - } - - if (rate < c->u.system.pclk->min_rate * 2) { - ret = clk_set_div(c->u.system.pclk, 1); - if (ret) { - pr_err("Failed to set 1 : 1 pclk divider\n"); - return ret; - } - } - - return 0; -} - -static int tegra11_clk_sbus_update(struct clk *bus) -{ - unsigned long rate, old_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(bus); - if (rate == old_rate) - return 0; - - return clk_set_rate_locked(bus, rate); -} - -static struct clk_ops tegra_sbus_cmplx_ops = { - .init = tegra11_sbus_cmplx_init, - .set_rate = tegra11_sbus_cmplx_set_rate, - .round_rate = tegra11_sbus_cmplx_round_rate, - .round_rate_updown = tegra11_sbus_cmplx_round_updown, - .shared_bus_update = tegra11_clk_sbus_update, -}; - -/* Blink output functions */ - -static void tegra11_blink_clk_init(struct clk *c) -{ - u32 val; - - val = pmc_readl(PMC_CTRL); - c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; - c->mul = 1; - val = pmc_readl(c->reg); - - if (val & PMC_BLINK_TIMER_ENB) { - unsigned int on_off; - - on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & - PMC_BLINK_TIMER_DATA_ON_MASK; - val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off += val; - /* each tick in the blink timer is 4 32KHz clocks */ - c->div = on_off * 4; - } else { - c->div = 1; - } -} - -static int tegra11_blink_clk_enable(struct clk *c) -{ - u32 val; - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); - - val = pmc_readl(PMC_CTRL); - pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); - - return 0; -} - -static void tegra11_blink_clk_disable(struct clk *c) -{ - u32 val; - - val = pmc_readl(PMC_CTRL); - pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); -} - -static int tegra11_blink_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(c->parent); - if (rate >= parent_rate) { - c->div = 1; - pmc_writel(0, c->reg); - } else { - unsigned int on_off; - u32 val; - - on_off = DIV_ROUND_UP(parent_rate / 8, rate); - c->div = on_off * 8; - - val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << - PMC_BLINK_TIMER_DATA_ON_SHIFT; - on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val |= on_off; - val |= PMC_BLINK_TIMER_ENB; - pmc_writel(val, c->reg); - } - - return 0; -} - -static struct clk_ops tegra_blink_clk_ops = { - .init = &tegra11_blink_clk_init, - .enable = &tegra11_blink_clk_enable, - .disable = &tegra11_blink_clk_disable, - .set_rate = &tegra11_blink_clk_set_rate, -}; - -/* PLL Functions */ -static int tegra11_pll_clk_wait_for_lock( - struct clk *c, u32 lock_reg, u32 lock_bits) -{ -#if USE_PLL_LOCK_BITS - int i; - u32 val = 0; - - for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) { - udelay(PLL_PRE_LOCK_DELAY); - val = clk_readl(lock_reg); - if ((val & lock_bits) == lock_bits) { - udelay(PLL_POST_LOCK_DELAY); - return 0; - } - } - - /* PLLCX lock bits may fluctuate after the lock - don't report timeout - in this case (phase lock bit happens to uniquely identify PLLCX) */ - if (lock_bits & PLLCX_BASE_PHASE_LOCK) { - pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n", - c->name, lock_reg, val); - return 0; - } else if ((c->flags & PLLD) && - tegra_powergate_check_clamping(TEGRA_POWERGATE_DISA)) { - pr_debug("Waiting for %s lock.\n", c->name); - } else { - pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n", - c->name, lock_reg, val); - return -ETIMEDOUT; - } -#endif - udelay(c->u.pll.lock_delay); - return 0; -} - -static void usb_plls_hw_control_enable(u32 reg) -{ - u32 val = clk_readl(reg); - val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE; - val &= ~USB_PLLS_ENABLE_SWCTL; - val |= USB_PLLS_SEQ_START_STATE; - pll_writel_delay(val, reg); - - val |= USB_PLLS_SEQ_ENABLE; - pll_writel_delay(val, reg); -} - -static void tegra11_utmi_param_configure(struct clk *c) -{ - u32 reg; - int i; - unsigned long main_rate = - clk_get_rate(c->parent->parent); - - for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { - if (main_rate == utmi_parameters[i].osc_frequency) { - break; - } - } - - if (i >= ARRAY_SIZE(utmi_parameters)) { - pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); - return; - } - - reg = clk_readl(UTMIP_PLL_CFG2); - - /* Program UTMIP PLL stable and active counts */ - /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ - reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); - reg |= UTMIP_PLL_CFG2_STABLE_COUNT( - utmi_parameters[i].stable_count); - - reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); - - reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( - utmi_parameters[i].active_delay_count); - - /* Remove power downs from UTMIP PLL control bits */ - reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; - reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; - reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP; - reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; - - clk_writel(reg, UTMIP_PLL_CFG2); - - /* Program UTMIP PLL delay and oscillator frequency counts */ - reg = clk_readl(UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); - - reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( - utmi_parameters[i].enable_delay_count); - - reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); - reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( - utmi_parameters[i].xtal_freq_count); - - /* Remove power downs from UTMIP PLL control bits */ - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; - clk_writel(reg, UTMIP_PLL_CFG1); - - /* Setup HW control of UTMIPLL */ - reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0); - reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; - reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; - reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; - clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0); - - reg = clk_readl(UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; - clk_writel(reg, UTMIP_PLL_CFG1); - - udelay(1); - - /* Setup SW override of UTMIPLL assuming USB2.0 - ports are assigned to USB2 */ - reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0); - reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; - reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; - clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0); - - udelay(1); - - /* Enable HW control UTMIPLL */ - reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0); - reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; - clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0); -} - -static void tegra11_pll_clk_init(struct clk *c) -{ - u32 val = clk_readl(c->reg + PLL_BASE); - - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { - const struct clk_pll_freq_table *sel; - unsigned long input_rate = clk_get_rate(c->parent); - c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE; - - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && - sel->output_rate == c->u.pll.fixed_rate) { - c->mul = sel->n; - c->div = sel->m * sel->p; - return; - } - } - pr_err("Clock %s has unknown fixed frequency\n", c->name); - BUG(); - } else if (val & PLL_BASE_BYPASS) { - c->mul = 1; - c->div = 1; - } else { - c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - if (c->flags & PLLU) - c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; - else - c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> - PLL_BASE_DIVP_SHIFT)); - } - - if (c->flags & PLL_FIXED) { - c->u.pll.fixed_rate = clk_get_rate_locked(c); - } - - if (c->flags & PLLU) { - /* Configure UTMI PLL power management */ - tegra11_utmi_param_configure(c); - - /* Put PLLU under h/w control */ - usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLLU_BASE_OVERRIDE; - clk_writel(val, c->reg + PLL_BASE); - - /* Set XUSB PLL pad pwr override and iddq */ - val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1); - val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD; - val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ; - xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1); - } -} - -static int tegra11_pll_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - -#if USE_PLL_LOCK_BITS - /* toggle lock enable bit to reset lock detection circuit (couple - register reads provide enough duration for reset pulse) */ - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLL_MISC_LOCK_ENABLE(c); - clk_writel(val, c->reg + PLL_MISC(c)); - val = clk_readl(c->reg + PLL_MISC(c)); - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLL_MISC_LOCK_ENABLE(c); - clk_writel(val, c->reg + PLL_MISC(c)); -#endif - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_BYPASS; - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - - return 0; -} - -static void tegra11_pll_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - clk_writel(val, c->reg); -} - -static u8 get_pll_cpcon(struct clk *c, u16 n) -{ - if (c->flags & PLLD) { - if (n >= 600) - return 12; - else if (n >= 300) - return 8; - else if (n >= 50) - return 3; - else - return 2; - } - return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON; -} - -/* Special comparison frequency selection for PLLD at 12MHz refrence rate */ -unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate, - unsigned long rate, unsigned long *vco) -{ - if (!(c->flags & PLLD) || (input_rate != 12000000)) - return 0; - - *vco = c->u.pll.vco_min; - - if (rate <= 250000000) - return 4000000; - else if (rate <= 500000000) - return 2000000; - else - return 1000000; -} - -/* Common comparison frequency selection */ -unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate, - unsigned long rate, unsigned long *vco) -{ - unsigned long cfreq = 0; - - switch (input_rate) { - case 12000000: - case 26000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; - break; - case 13000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; - break; - case 16800000: - case 19200000: - cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; - break; - default: - if (c->parent->flags & DIV_U71_FIXED) { - /* PLLP_OUT1 rate is not in PLLA table */ - pr_warn("%s: failed %s ref/out rates %lu/%lu\n", - __func__, c->name, input_rate, rate); - cfreq = input_rate/(input_rate/1000000); - break; - } - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - } - - /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */ - *vco = max(200 * cfreq, c->u.pll.vco_min); - return cfreq; -} - -static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, p_div, old_base; - unsigned long input_rate; - const struct clk_pll_freq_table *sel; - struct clk_pll_freq_table cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->flags & PLL_FIXED) { - int ret = 0; - if (rate != c->u.pll.fixed_rate) { - pr_err("%s: Can not change %s fixed rate %lu to %lu\n", - __func__, c->name, c->u.pll.fixed_rate, rate); - ret = -EINVAL; - } - return ret; - } - - p_div = 0; - input_rate = clk_get_rate(c->parent); - - /* Check if the target rate is tabulated */ - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - if (c->flags & PLLU) { - BUG_ON(sel->p < 1 || sel->p > 2); - if (sel->p == 1) - p_div = PLLU_BASE_POST_DIV; - } else { - BUG_ON(sel->p < 1); - for (val = sel->p; val > 1; val >>= 1, p_div++); - p_div <<= PLL_BASE_DIVP_SHIFT; - } - break; - } - } - - /* Configure out-of-table rate */ - if (sel->input_rate == 0) { - unsigned long cfreq, vco; - BUG_ON(c->flags & PLLU); - sel = &cfg; - - /* If available, use pll specific algorithm to select comparison - frequency, and vco target */ - cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco); - if (!cfreq) - cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco); - - for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++) - cfg.output_rate <<= 1; - - cfg.p = 0x1 << p_div; - cfg.m = input_rate / cfreq; - cfg.n = cfg.output_rate / cfreq; - cfg.cpcon = get_pll_cpcon(c, cfg.n); - - if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || - (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || - (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || - (cfg.output_rate > c->u.pll.vco_max)) { - pr_err("%s: Failed to set %s out-of-table rate %lu\n", - __func__, c->name, rate); - return -EINVAL; - } - p_div <<= PLL_BASE_DIVP_SHIFT; - } - - c->mul = sel->n; - c->div = sel->m * sel->p; - - old_base = val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | - ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; - if (val == old_base) - return 0; - - if (c->state == ON) { - tegra11_pll_clk_disable(c); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - } - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLL_HAS_CPCON) { - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLL_MISC_CPCON_MASK; - val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; - if (c->flags & (PLLU | PLLD)) { - val &= ~PLL_MISC_LFCON_MASK; - val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT; - } - clk_writel(val, c->reg + PLL_MISC(c)); - } - - if (c->state == ON) - tegra11_pll_clk_enable(c); - - return 0; -} - -static struct clk_ops tegra_pll_ops = { - .init = tegra11_pll_clk_init, - .enable = tegra11_pll_clk_enable, - .disable = tegra11_pll_clk_disable, - .set_rate = tegra11_pll_clk_set_rate, -}; - -static void tegra11_pllp_clk_init(struct clk *c) -{ - tegra11_pll_clk_init(c); - tegra11_pllp_init_dependencies(c->u.pll.fixed_rate); -} - -#ifdef CONFIG_PM_SLEEP -static void tegra11_pllp_clk_resume(struct clk *c) -{ - unsigned long rate = c->u.pll.fixed_rate; - tegra11_pll_clk_init(c); - BUG_ON(rate != c->u.pll.fixed_rate); -} -#endif - -static struct clk_ops tegra_pllp_ops = { - .init = tegra11_pllp_clk_init, - .enable = tegra11_pll_clk_enable, - .disable = tegra11_pll_clk_disable, - .set_rate = tegra11_pll_clk_set_rate, -}; - -static int -tegra11_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - u32 val, mask, reg; - - switch (p) { - case TEGRA_CLK_PLLD_CSI_OUT_ENB: - mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE; - reg = c->reg + PLL_BASE; - break; - case TEGRA_CLK_PLLD_DSI_OUT_ENB: - mask = PLLD_MISC_DSI_CLKENABLE; - reg = c->reg + PLL_MISC(c); - break; - case TEGRA_CLK_PLLD_MIPI_MUX_SEL: - mask = PLLD_BASE_DSI_MUX_MASK; - reg = c->reg + PLL_BASE; - break; - default: - return -EINVAL; - } - - val = clk_readl(reg); - if (setting) - val |= mask; - else - val &= ~mask; - clk_writel(val, reg); - return 0; -} - -static struct clk_ops tegra_plld_ops = { - .init = tegra11_pll_clk_init, - .enable = tegra11_pll_clk_enable, - .disable = tegra11_pll_clk_disable, - .set_rate = tegra11_pll_clk_set_rate, - .clk_cfg_ex = tegra11_plld_clk_cfg_ex, -}; - -/* - * Dynamic ramp PLLs: - * PLLC2 and PLLC3 (PLLCX) - * PLLX and PLLC (PLLXC) - * - * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that - * changes NDIV only. As a matter of policy we will make sure that switching - * between output rates above VCO minimum is always dynamic. The pre-requisite - * for the above guarantee is the following configuration convention: - * - pll configured with fixed MDIV - * - when output rate is above VCO minimum PDIV = 0 (p-value = 1) - * Switching between output rates below VCO minimum may or may not be dynamic, - * and switching across VCO minimum is never dynamic. - * - * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless - * output dividers. However dynamic ramp without overshoot is guaranteed only - * when output divisor is less or equal 8. - * - * Of course, dynamic ramp is applied provided PLL is already enabled. - */ - -/* - * Common configuration policy for dynamic ramp PLLs: - * - always set fixed M-value based on the reference rate - * - always set P-value value 1:1 for output rates above VCO minimum, and - * choose minimum necessary P-value for output rates below VCO minimum - * - calculate N-value based on selected M and P - */ -static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg, - unsigned long rate, unsigned long input_rate, u32 *pdiv) -{ - u32 p; - - if (!rate) - return -EINVAL; - - p = DIV_ROUND_UP(c->u.pll.vco_min, rate); - p = c->u.pll.round_p_to_pdiv(p, pdiv); - if (IS_ERR_VALUE(p)) - return -EINVAL; - - cfg->m = PLL_FIXED_MDIV(c, input_rate); - cfg->p = p; - cfg->output_rate = rate * cfg->p; - cfg->n = cfg->output_rate * cfg->m / input_rate; - - /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */ - if ((cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || - (cfg->output_rate > c->u.pll.vco_max)) - return -EINVAL; - - return 0; -} - -static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg, - unsigned long rate, unsigned long input_rate, u32 *pdiv) -{ - const struct clk_pll_freq_table *sel; - - /* Check if the target rate is tabulated */ - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv); - BUG_ON(IS_ERR_VALUE(p)); - BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate)); - *cfg = *sel; - return 0; - } - } - - /* Configure out-of-table rate */ - if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) { - pr_err("%s: Failed to set %s out-of-table rate %lu\n", - __func__, c->name, rate); - return -EINVAL; - } - return 0; -} - -static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set) -{ - u32 val = clk_readl(c->reg + offs); - if (set) - val |= iddq_bit; - else - val &= ~iddq_bit; - clk_writel_delay(val, c->reg + offs); -} - - -static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = { -/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */ -/* p: */ 1, 2, 3, 4, 6, 8, 12, 16 }; - -static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - int i; - - if (p) { - for (i = 0; i <= PLLCX_PDIV_MAX; i++) { - /* Do not use DIV3 p values - mapped to even PDIV */ - if (i && ((i & 0x1) == 0)) - continue; - - if (p <= pllcx_p[i]) { - if (pdiv) - *pdiv = i; - return pllcx_p[i]; - } - } - } - return -EINVAL; -} - -static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate, - u32 n) -{ - u32 val, n_threshold; - - switch (input_rate) { - case 12000000: - n_threshold = 70; - break; - case 13000000: - case 26000000: - n_threshold = 71; - break; - case 16800000: - n_threshold = 55; - break; - case 19200000: - n_threshold = 48; - break; - default: - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - return; - } - - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); - val |= n <= n_threshold ? - PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; - clk_writel(val, c->reg + PLL_MISC(c)); -} - -static void pllcx_strobe(struct clk *c) -{ - u32 reg = c->reg + PLL_MISC(c); - u32 val = clk_readl(reg); - - val |= PLLCX_MISC_STROBE; - pll_writel_delay(val, reg); - - val &= ~PLLCX_MISC_STROBE; - clk_writel(val, reg); -} - -static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n) -{ - clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c)); - clk_writel(PLLCX_MISC1_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 1)); - clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2)); - clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3)); - - pllcx_update_dynamic_koef(c, input_rate, n); -} - -static void tegra11_pllcx_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, n, p, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]); - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - /* - * PLLCX is not a boot PLL, it should be left disabled by boot-loader, - * and no enabled module clocks should use it as a source during clock - * init. - */ - BUG_ON(c->state == ON); - /* - * Most of PLLCX register fields are shadowed, and can not be read - * directly from PLL h/w. Hence, actual PLLCX boot state is unknown. - * Initialize PLL to default state: disabled, reset; shadow registers - * loaded with default parameters; dividers are preset for half of - * minimum VCO rate (the latter assured that shadowed divider settings - * are within supported range). - */ - m = PLL_FIXED_MDIV(c, input_rate); - n = m * c->u.pll.vco_min / input_rate; - p = pllcx_p[1]; - val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | - (1 << PLL_BASE_DIVP_SHIFT); - clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */ - - pllcx_set_defaults(c, input_rate, n); - - c->mul = n; - c->div = m * p; -} - -static int tegra11_pllcx_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_BYPASS; - val |= PLL_BASE_ENABLE; - pll_writel_delay(val, c->reg + PLL_BASE); - - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLLCX_MISC_RESET; - pll_writel_delay(val, c->reg + PLL_MISC(c)); - - pllcx_strobe(c); - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, - PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK); - return 0; -} - -static void tegra11_pllcx_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - clk_writel(val, c->reg); - - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLLCX_MISC_RESET; - pll_writel_delay(val, c->reg + PLL_MISC(c)); -} - -static int tegra11_pllcx_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, pdiv; - unsigned long input_rate; - struct clk_pll_freq_table cfg, old_cfg; - const struct clk_pll_freq_table *sel = &cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - input_rate = clk_get_rate(c->parent); - - if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv)) - return -EINVAL; - - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLCX, old_cfg, val); - old_cfg.p = pllcx_p[old_cfg.p]; - - BUG_ON(old_cfg.m != sel->m); - if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p)) - return 0; - -#if PLLCX_USE_DYN_RAMP - if (c->state == ON && ((sel->n == old_cfg.n) || - PLLCX_IS_DYN(sel->p, old_cfg.p))) { - /* - * Dynamic ramp if PLL is enabled, and M divider is unchanged: - * - Change P divider 1st if intermediate rate is below either - * old or new rate. - * - Change N divider with DFS strobe - target rate is either - * final new rate or below old rate - * - If divider has been changed, exit without waiting for lock. - * Otherwise, wait for lock and change divider. - */ - if (sel->p > old_cfg.p) { - val &= ~PLLCX_BASE_DIVP_MASK; - val |= pdiv << PLL_BASE_DIVP_SHIFT; - clk_writel(val, c->reg + PLL_BASE); - } - - if (sel->n != old_cfg.n) { - pllcx_update_dynamic_koef(c, input_rate, sel->n); - val &= ~PLLCX_BASE_DIVN_MASK; - val |= sel->n << PLL_BASE_DIVN_SHIFT; - pll_writel_delay(val, c->reg + PLL_BASE); - - pllcx_strobe(c); - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, - PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK); - } - - if (sel->p < old_cfg.p) { - val &= ~PLLCX_BASE_DIVP_MASK; - val |= pdiv << PLL_BASE_DIVP_SHIFT; - clk_writel(val, c->reg + PLL_BASE); - } - return 0; - } -#endif - - val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK); - val |= (sel->n << PLL_BASE_DIVN_SHIFT) | - (pdiv << PLL_BASE_DIVP_SHIFT); - - if (c->state == ON) { - tegra11_pllcx_clk_disable(c); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - } - pllcx_update_dynamic_koef(c, input_rate, sel->n); - clk_writel(val, c->reg + PLL_BASE); - if (c->state == ON) - tegra11_pllcx_clk_enable(c); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra11_pllcx_clk_resume_enable(struct clk *c) -{ - unsigned long rate = clk_get_rate_all_locked(c->parent); - u32 val = clk_readl(c->reg + PLL_BASE); - enum clk_state state = c->state; - - if (val & PLL_BASE_ENABLE) - return; /* already resumed */ - - /* Restore input divider */ - val &= ~PLLCX_BASE_DIVM_MASK; - val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT; - clk_writel(val, c->reg + PLL_BASE); - - /* temporarily sync h/w and s/w states, final sync happens - in tegra_clk_resume later */ - c->state = OFF; - pllcx_set_defaults(c, rate, c->mul); - - rate = clk_get_rate_all_locked(c); - tegra11_pllcx_clk_set_rate(c, rate); - tegra11_pllcx_clk_enable(c); - c->state = state; -} -#endif - -static struct clk_ops tegra_pllcx_ops = { - .init = tegra11_pllcx_clk_init, - .enable = tegra11_pllcx_clk_enable, - .disable = tegra11_pllcx_clk_disable, - .set_rate = tegra11_pllcx_clk_set_rate, -}; - - -/* non-monotonic mapping below is not a typo */ -static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = { -/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ -/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 }; - -static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - if (!p || (p > PLLXC_SW_PDIV_MAX + 1)) - return -EINVAL; - - if (pdiv) - *pdiv = p - 1; - return p; -} - -static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate, - u32 *step_a, u32 *step_b) -{ - switch (input_rate) { - case 12000000: - case 13000000: - case 26000000: - *step_a = 0x2B; - *step_b = 0x0B; - return; - case 16800000: - *step_a = 0x1A; - *step_b = 0x09; - return; - case 19200000: - *step_a = 0x12; - *step_b = 0x08; - return; - default: - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - } -} - -static void pllx_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val; - u32 step_a, step_b; - - /* Only s/w dyn ramp control is supported */ - val = clk_readl(PLLX_HW_CTRL_CFG); - BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL)); - - pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b); - val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; - val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; - - /* Get ready dyn ramp state machine, disable lock override */ - clk_writel(val, c->reg + PLL_MISCN(c, 2)); - - /* Enable outputs to CPUs and configure lock */ - val = 0; -#if USE_PLL_LOCK_BITS - val |= PLL_MISC_LOCK_ENABLE(c); -#endif - clk_writel(val, c->reg + PLL_MISC(c)); - - /* Check/set IDDQ */ - val = clk_readl(c->reg + PLL_MISCN(c, 3)); - if (c->state == ON) - BUG_ON(val & PLLX_MISC3_IDDQ); - else { - val |= PLLX_MISC3_IDDQ; - clk_writel(val, c->reg + PLL_MISCN(c, 3)); - } -} - -static void pllc_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val; - u32 step_a, step_b; - - /* Get ready dyn ramp state machine */ - pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b); - val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT; - val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT; - clk_writel(val, c->reg + PLL_MISCN(c, 1)); - - /* Configure lock and check/set IDDQ */ - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLLC_BASE_LOCK_OVERRIDE; - clk_writel(val, c->reg + PLL_BASE); - - val = clk_readl(c->reg + PLL_MISC(c)); -#if USE_PLL_LOCK_BITS - val |= PLLC_MISC_LOCK_ENABLE; -#else - val &= ~PLLC_MISC_LOCK_ENABLE; -#endif - clk_writel(val, c->reg + PLL_MISC(c)); - - if (c->state == ON) { - BUG_ON(val & PLLC_MISC_IDDQ); - } else { - val |= PLLC_MISC_IDDQ; - clk_writel(val, c->reg + PLL_MISC(c)); - } -} - -static void tegra11_pllxc_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, p, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = - DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]); - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; - BUG_ON(p > PLLXC_PDIV_MAX); - p = pllxc_p[p]; - - c->div = m * p; - c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - - if (c->flags & PLLX) - pllx_set_defaults(c, input_rate); - else - pllc_set_defaults(c, input_rate); -} - -static int tegra11_pllxc_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - if (c->flags & PLLX) - pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false); - else - pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false); - - val = clk_readl(c->reg + PLL_BASE); - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - - return 0; -} - -static void tegra11_pllxc_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLLX) - pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true); - else - pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true); - -} - -#define PLLXC_DYN_RAMP(pll_misc, reg) \ - do { \ - u32 misc = clk_readl((reg)); \ - \ - misc &= ~pll_misc##_NDIV_NEW_MASK; \ - misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \ - pll_writel_delay(misc, (reg)); \ - \ - misc |= pll_misc##_EN_DYNRAMP; \ - clk_writel(misc, (reg)); \ - tegra11_pll_clk_wait_for_lock(c, (reg), \ - pll_misc##_DYNRAMP_DONE); \ - \ - val &= ~PLLXC_BASE_DIVN_MASK; \ - val |= sel->n << PLL_BASE_DIVN_SHIFT; \ - pll_writel_delay(val, c->reg + PLL_BASE); \ - \ - misc &= ~pll_misc##_EN_DYNRAMP; \ - pll_writel_delay(misc, (reg)); \ - } while (0) - -static int tegra11_pllxc_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, pdiv; - unsigned long input_rate; - struct clk_pll_freq_table cfg, old_cfg; - const struct clk_pll_freq_table *sel = &cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - input_rate = clk_get_rate(c->parent); - - if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv)) - return -EINVAL; - - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLXC, old_cfg, val); - old_cfg.p = pllxc_p[old_cfg.p]; - - if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) && - (sel->p == old_cfg.p)) - return 0; - -#if PLLXC_USE_DYN_RAMP - /* - * Dynamic ramp can be used if M, P dividers are unchanged - * (coveres superset of conventional dynamic ramps) - */ - if ((c->state == ON) && (sel->m == old_cfg.m) && - (sel->p == old_cfg.p)) { - - if (c->flags & PLLX) { - u32 reg = c->reg + PLL_MISCN(c, 2); - PLLXC_DYN_RAMP(PLLX_MISC2, reg); - } else { - u32 reg = c->reg + PLL_MISCN(c, 1); - PLLXC_DYN_RAMP(PLLC_MISC1, reg); - } - - return 0; - } -#endif - if (c->state == ON) { - /* Use "ENABLE" pulse without placing PLL into IDDQ */ - val &= ~PLL_BASE_ENABLE; - pll_writel_delay(val, c->reg + PLL_BASE); - } - - val &= ~(PLLXC_BASE_DIVM_MASK | - PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT); - clk_writel(val, c->reg + PLL_BASE); - - if (c->state == ON) { - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, - PLL_BASE_LOCK); - } - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra11_pllxc_clk_resume_enable(struct clk *c) -{ - unsigned long rate = clk_get_rate_all_locked(c->parent); - enum clk_state state = c->state; - - if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE) - return; /* already resumed */ - - /* temporarily sync h/w and s/w states, final sync happens - in tegra_clk_resume later */ - c->state = OFF; - if (c->flags & PLLX) - pllx_set_defaults(c, rate); - else - pllc_set_defaults(c, rate); - - rate = clk_get_rate_all_locked(c); - tegra11_pllxc_clk_set_rate(c, rate); - tegra11_pllxc_clk_enable(c); - c->state = state; -} -#endif - -static struct clk_ops tegra_pllxc_ops = { - .init = tegra11_pllxc_clk_init, - .enable = tegra11_pllxc_clk_enable, - .disable = tegra11_pllxc_clk_disable, - .set_rate = tegra11_pllxc_clk_set_rate, -}; - - -/* FIXME: pllm suspend/resume */ - -static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - if (!p || (p > 2)) - return -EINVAL; - - if (pdiv) - *pdiv = p - 1; - return p; -} - -static void pllm_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val = clk_readl(c->reg + PLL_MISC(c)); - - val &= ~PLLM_MISC_LOCK_OVERRIDE; -#if USE_PLL_LOCK_BITS - val &= ~PLLM_MISC_LOCK_DISABLE; -#else - val |= PLLM_MISC_LOCK_DISABLE; -#endif - - if (c->state != ON) - val |= PLLM_MISC_IDDQ; - else - BUG_ON(val & PLLM_MISC_IDDQ); - - clk_writel(val, c->reg + PLL_MISC(c)); -} - -static void tegra11_pllm_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, p, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = - DIV_ROUND_UP(c->u.pll.vco_min, 2); - - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) { - c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF; - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2); - p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) ? 2 : 1; - - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); - } else { - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - p = (val & PLLM_BASE_DIVP_MASK) ? 2 : 1; - } - - m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - BUG_ON(m != PLL_FIXED_MDIV(c, input_rate)); - c->div = m * p; - c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - - pllm_set_defaults(c, input_rate); -} - -static int tegra11_pllm_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false); - - /* Just enable both base and override - one would work */ - val = clk_readl(c->reg + PLL_BASE); - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; - pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - return 0; -} - -static void tegra11_pllm_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - /* Just disable both base and override - one would work */ - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; - pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true); -} - -static int tegra11_pllm_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, pdiv; - unsigned long input_rate; - struct clk_pll_freq_table cfg; - const struct clk_pll_freq_table *sel = &cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->state == ON) { - if (rate != clk_get_rate_locked(c)) { - pr_err("%s: Can not change memory %s rate in flight\n", - __func__, c->name); - return -EINVAL; - } - return 0; - } - - input_rate = clk_get_rate(c->parent); - - if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv)) - return -EINVAL; - - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) { - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2); - val = pdiv ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) : - (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK); - pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2); - - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); - val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT); - pmc_writel(val, PMC_PLLM_WB0_OVERRIDE); - } else { - val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK | - PLLM_BASE_DIVP_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | - (pdiv ? PLLM_BASE_DIVP_MASK : 0); - clk_writel(val, c->reg + PLL_BASE); - } - - return 0; -} - -static struct clk_ops tegra_pllm_ops = { - .init = tegra11_pllm_clk_init, - .enable = tegra11_pllm_clk_enable, - .disable = tegra11_pllm_clk_disable, - .set_rate = tegra11_pllm_clk_set_rate, -}; - - -/* non-monotonic mapping below is not a typo */ -static u8 pllre_p[PLLRE_PDIV_MAX + 1] = { -/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ -/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 }; - -static u32 pllre_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - if (!p || (p > PLLRE_SW_PDIV_MAX + 1)) - return -EINVAL; - - if (pdiv) - *pdiv = p - 1; - return p; -} - -static void pllre_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val = clk_readl(c->reg + PLL_MISC(c)); - - val &= ~PLLRE_MISC_LOCK_OVERRIDE; -#if USE_PLL_LOCK_BITS - val |= PLLRE_MISC_LOCK_ENABLE; -#else - val &= ~PLLRE_MISC_LOCK_ENABLE; -#endif - - if (c->state != ON) - val |= PLLRE_MISC_IDDQ; - else - BUG_ON(val & PLLRE_MISC_IDDQ); - - clk_writel(val, c->reg + PLL_MISC(c)); -} - -static void tegra11_pllre_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = c->u.pll.vco_min; - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - if (!val) { - /* overwrite h/w por state with min setting */ - m = PLL_FIXED_MDIV(c, input_rate); - val = (m << PLL_BASE_DIVM_SHIFT) | - (c->min_rate / input_rate << PLL_BASE_DIVN_SHIFT); - clk_writel(val, c->reg + PLL_BASE); - } - - m = (val & PLLRE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - BUG_ON(m != PLL_FIXED_MDIV(c, input_rate)); - - c->div = m; - c->mul = (val & PLLRE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - - pllre_set_defaults(c, input_rate); -} - -static int tegra11_pllre_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, false); - - val = clk_readl(c->reg + PLL_BASE); - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK); - return 0; -} - -static void tegra11_pllre_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, true); -} - -static int tegra11_pllre_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, old_base; - unsigned long input_rate; - struct clk_pll_freq_table cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (rate < c->min_rate) { - pr_err("%s: Failed to set %s rate %lu\n", - __func__, c->name, rate); - return -EINVAL; - } - - input_rate = clk_get_rate(c->parent); - cfg.m = PLL_FIXED_MDIV(c, input_rate); - cfg.n = rate * cfg.m / input_rate; - - c->mul = cfg.n; - c->div = cfg.m; - - val = old_base = clk_readl(c->reg + PLL_BASE); - val &= ~(PLLRE_BASE_DIVM_MASK | PLLRE_BASE_DIVN_MASK); - val |= (cfg.m << PLL_BASE_DIVM_SHIFT) | (cfg.n << PLL_BASE_DIVN_SHIFT); - if (val == old_base) - return 0; - - if (c->state == ON) { - /* Use "ENABLE" pulse without placing PLL into IDDQ */ - val &= ~PLL_BASE_ENABLE; - old_base &= ~PLL_BASE_ENABLE; - pll_writel_delay(old_base, c->reg + PLL_BASE); - } - - clk_writel(val, c->reg + PLL_BASE); - - if (c->state == ON) { - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - tegra11_pll_clk_wait_for_lock( - c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK); - } - return 0; -} - -static struct clk_ops tegra_pllre_ops = { - .init = tegra11_pllre_clk_init, - .enable = tegra11_pllre_clk_enable, - .disable = tegra11_pllre_clk_disable, - .set_rate = tegra11_pllre_clk_set_rate, -}; - -static void tegra11_pllre_out_clk_init(struct clk *c) -{ - u32 p, val; - - val = clk_readl(c->reg); - p = (val & PLLRE_BASE_DIVP_MASK) >> PLLRE_BASE_DIVP_SHIFT; - BUG_ON(p > PLLRE_PDIV_MAX); - p = pllre_p[p]; - - c->div = p; - c->mul = 1; - c->state = c->parent->state; -} - -static int tegra11_pllre_out_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra11_pllre_out_clk_disable(struct clk *c) -{ -} - -static int tegra11_pllre_out_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, p, pdiv; - unsigned long input_rate, flags; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - clk_lock_save(c->parent, &flags); - input_rate = clk_get_rate_locked(c->parent); - - p = DIV_ROUND_UP(input_rate, rate); - p = c->parent->u.pll.round_p_to_pdiv(p, &pdiv); - if (IS_ERR_VALUE(p)) { - pr_err("%s: Failed to set %s rate %lu\n", - __func__, c->name, rate); - clk_unlock_restore(c->parent, &flags); - return -EINVAL; - } - c->div = p; - - val = clk_readl(c->reg); - val &= ~PLLRE_BASE_DIVP_MASK; - val |= pdiv << PLLRE_BASE_DIVP_SHIFT; - clk_writel(val, c->reg); - - clk_unlock_restore(c->parent, &flags); - return 0; -} - -static struct clk_ops tegra_pllre_out_ops = { - .init = tegra11_pllre_out_clk_init, - .enable = tegra11_pllre_out_clk_enable, - .disable = tegra11_pllre_out_clk_disable, - .set_rate = tegra11_pllre_out_clk_set_rate, -}; - -#ifdef CONFIG_PM_SLEEP -/* Resume both pllre_vco and pllre_out */ -static void tegra11_pllre_clk_resume_enable(struct clk *c) -{ - u32 pdiv; - u32 val = clk_readl(c->reg + PLL_BASE); - unsigned long rate = clk_get_rate_all_locked(c->parent->parent); - enum clk_state state = c->parent->state; - - if (val & PLL_BASE_ENABLE) - return; /* already resumed */ - - /* temporarily sync h/w and s/w states, final sync happens - in tegra_clk_resume later */ - c->parent->state = OFF; - pllre_set_defaults(c->parent, rate); - - /* restore PLLRE VCO feedback loop (m, n) */ - rate = clk_get_rate_all_locked(c->parent); - tegra11_pllre_clk_set_rate(c->parent, rate); - - /* restore PLLRE post-divider */ - c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv); - val = clk_readl(c->reg); - val &= ~PLLRE_BASE_DIVP_MASK; - val |= pdiv << PLLRE_BASE_DIVP_SHIFT; - clk_writel(val, c->reg); - - tegra11_pllre_clk_enable(c->parent); - c->parent->state = state; -} -#endif - -/* non-monotonic mapping below is not a typo */ -static u8 plle_p[PLLE_CMLDIV_MAX + 1] = { -/* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ -/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 }; - -static inline void select_pll_e_input(u32 aux_reg) -{ -#if USE_PLLE_INPUT_PLLRE - aux_reg |= PLLE_AUX_PLLRE_SEL; -#else - aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); -#endif - clk_writel(aux_reg, PLLE_AUX); -} - -static void tegra11_plle_clk_init(struct clk *c) -{ - u32 val, p; - struct clk *pll_ref = tegra_get_clock_by_name("pll_ref"); - struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco"); - struct clk *pllp = tegra_get_clock_by_name("pllp"); -#if USE_PLLE_INPUT_PLLRE - struct clk *ref = re_vco; -#else - struct clk *ref = pll_ref; -#endif - - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT; - c->div *= plle_p[p]; - - val = clk_readl(PLLE_AUX); - c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco : - (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref; - if (c->parent != ref) { - if (c->state == ON) { - WARN(1, "%s: pll_e is left enabled with %s input\n", - __func__, c->parent->name); - } else { - c->parent = ref; - select_pll_e_input(val); - } - } -} - -static void tegra11_plle_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - /* FIXME: do we need to restore other s/w controls ? */ - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; - pll_writel_delay(val, c->reg + PLL_MISC(c)); -} - -static int tegra11_plle_clk_enable(struct clk *c) -{ - u32 val; - const struct clk_pll_freq_table *sel; - unsigned long rate = c->u.pll.fixed_rate; - unsigned long input_rate = clk_get_rate(c->parent); - - if (c->state == ON) { - /* BL left plle enabled - don't change configuartion */ - pr_warn("%s: pll_e is already enabled\n", __func__); - return 0; - } - - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) - break; - } - - if (sel->input_rate == 0) { - pr_err("%s: %s input rate %lu is out-of-table\n", - __func__, c->name, input_rate); - return -EINVAL; - } - - /* setup locking configuration, s/w control of IDDQ and enable modes, - take pll out of IDDQ via s/w control, setup VREG */ - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLLE_BASE_LOCK_OVERRIDE; - clk_writel(val, c->reg + PLL_BASE); - - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLLE_MISC_LOCK_ENABLE; - val |= PLLE_MISC_IDDQ_SW_CTRL; - val &= ~PLLE_MISC_IDDQ_SW_VALUE; - val |= PLLE_MISC_PLLE_PTS; - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; - clk_writel(val, c->reg + PLL_MISC(c)); - udelay(5); - - /* configure dividers, disable SS */ - val = clk_readl(PLLE_SS_CTRL); - val |= PLLE_SS_DISABLE; - clk_writel(val, PLLE_SS_CTRL); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK | - PLLE_BASE_DIVCML_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | - (sel->cpcon << PLLE_BASE_DIVCML_SHIFT); - pll_writel_delay(val, c->reg + PLL_BASE); - c->mul = sel->n; - c->div = sel->m * sel->p; - - /* enable and lock pll */ - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - tegra11_pll_clk_wait_for_lock( - c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK); -#if USE_PLLE_SS - val = clk_readl(PLLE_SS_CTRL); - val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); - val &= ~PLLE_SS_COEFFICIENTS_MASK; - val |= PLLE_SS_COEFFICIENTS_VAL; - clk_writel(val, PLLE_SS_CTRL); - val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); - pll_writel_delay(val, PLLE_SS_CTRL); - val &= ~PLLE_SS_CNTL_INTERP_RESET; - pll_writel_delay(val, PLLE_SS_CTRL); -#endif -#if !USE_PLLE_SWCTL - /* switch pll under h/w control */ - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - clk_writel(val, c->reg + PLL_MISC(c)); - - val = clk_readl(PLLE_AUX); - val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE; - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel_delay(val, PLLE_AUX); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel_delay(val, PLLE_AUX); -#endif - /* clear XUSB PLL pad pwr override and iddq */ - val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1); - val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD; - val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ; - xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1); - - /* enable hw control of xusb brick pll */ - usb_plls_hw_control_enable(XUSBIO_PLL_CFG0); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra11_plle_clk_resume(struct clk *c) -{ - u32 val = clk_readl(c->reg + PLL_BASE); - if (val & PLL_BASE_ENABLE) - return; /* already resumed */ - - /* Restore parent */ - val = clk_readl(PLLE_AUX); - select_pll_e_input(val); -} -#endif - -static struct clk_ops tegra_plle_ops = { - .init = tegra11_plle_clk_init, - .enable = tegra11_plle_clk_enable, - .disable = tegra11_plle_clk_disable, -}; - -/* - * Tegra11 includes dynamic frequency lock loop (DFLL) with automatic voltage - * control as possible CPU clock source. It is included in the Tegra11 clock - * tree as "complex PLL" with standard Tegra clock framework APIs. However, - * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c - * module. Hence, DFLL operations, with the exception of initialization, are - * basically cl-dvfs wrappers. - */ - -/* DFLL operations */ -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static void tune_cpu_trimmers(bool trim_high) -{ - if (trim_high) { - clk_writel(0, CPU_FINETRIM_SELECT); - clk_writel(0, CPU_FINETRIM_DR); - clk_writel(0, CPU_FINETRIM_R); - } else { - clk_writel(0x3F, CPU_FINETRIM_SELECT); - clk_writel(0x3F, CPU_FINETRIM_DR); - clk_writel(0xFFF, CPU_FINETRIM_R); - } - wmb(); - clk_readl(CPU_FINETRIM_R); -} -#endif - -static void __init tegra11_dfll_cpu_late_init(struct clk *c) -{ -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - int ret; - struct clk *cpu = tegra_get_clock_by_name("cpu_g"); - - if (!cpu || !cpu->dvfs) { - pr_err("%s: CPU dvfs is not present\n", __func__); - return; - } - if (cpu->dvfs->speedo_id > 0) /* A01P and above parts */ - tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers); - -#ifdef CONFIG_TEGRA_FPGA_PLATFORM - u32 netlist, patchid; - tegra_get_netlist_revision(&netlist, &patchid); - if (netlist < 12) { - pr_err("%s: CL-DVFS is not available on net %d\n", - __func__, netlist); - return; - } -#endif - /* release dfll clock source reset, init cl_dvfs control logic, and - move dfll to initialized state, so it can be used as CPU source */ - tegra_periph_reset_deassert(c); - ret = tegra_init_cl_dvfs(); - if (!ret) { - c->state = OFF; - - use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE; - tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll); - tegra_cl_dvfs_debug_init(c); - pr_info("Tegra CPU DFLL is initialized\n"); - } -#endif -} - -static void tegra11_dfll_clk_init(struct clk *c) -{ - c->ops->init = tegra11_dfll_cpu_late_init; -} - -static int tegra11_dfll_clk_enable(struct clk *c) -{ - return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs); -} - -static void tegra11_dfll_clk_disable(struct clk *c) -{ - tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs); -} - -static int tegra11_dfll_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate); - - if (!ret) - c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs); - - return ret; -} - -static void tegra11_dfll_clk_reset(struct clk *c, bool assert) -{ - u32 val = assert ? DFLL_BASE_RESET : 0; - clk_writel_delay(val, c->reg); -} - -static int -tegra11_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_DFLL_LOCK) - return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) : - tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs); - return -EINVAL; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra11_dfll_clk_resume(struct clk *c) -{ - if (!(clk_readl(c->reg) & DFLL_BASE_RESET)) - return; /* already resumed */ - - if (c->state != UNINITIALIZED) { - tegra_periph_reset_deassert(c); - tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs); - } -} -#endif - -static struct clk_ops tegra_dfll_ops = { - .init = tegra11_dfll_clk_init, - .enable = tegra11_dfll_clk_enable, - .disable = tegra11_dfll_clk_disable, - .set_rate = tegra11_dfll_clk_set_rate, - .reset = tegra11_dfll_clk_reset, - .clk_cfg_ex = tegra11_dfll_clk_cfg_ex, -}; - -/* DFLL sysfs interface */ -static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp) -{ - int ret = 0; - unsigned long c_flags, p_flags; - unsigned int old_use_dfll; - struct clk *c = tegra_get_clock_by_name("cpu"); - struct clk *dfll = tegra_get_clock_by_name("dfll_cpu"); - - if (!c->parent || !c->parent->dvfs || !dfll) - return -ENOSYS; - - clk_lock_save(c, &c_flags); - if (dfll->state == UNINITIALIZED) { - pr_err("%s: DFLL is not initialized\n", __func__); - clk_unlock_restore(c, &c_flags); - return -ENOSYS; - } - if (c->parent->u.cpu.mode == MODE_LP) { - pr_err("%s: DFLL is not used on LP CPU\n", __func__); - clk_unlock_restore(c, &c_flags); - return -ENOSYS; - } - - clk_lock_save(c->parent, &p_flags); - old_use_dfll = use_dfll; - param_set_int(arg, kp); - - if (use_dfll != old_use_dfll) { - ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll); - if (ret) { - use_dfll = old_use_dfll; - } else { - ret = clk_set_rate_locked(c->parent, - clk_get_rate_locked(c->parent)); - if (ret) { - use_dfll = old_use_dfll; - tegra_dvfs_set_dfll_range( - c->parent->dvfs, use_dfll); - } - } - } - clk_unlock_restore(c->parent, &p_flags); - clk_unlock_restore(c, &c_flags); - tegra_recalculate_cpu_edp_limits(); - return ret; -} - -static struct kernel_param_ops tegra11_use_dfll_ops = { - .set = tegra11_use_dfll_cb, - .get = param_get_int, -}; -module_param_cb(use_dfll, &tegra11_use_dfll_ops, &use_dfll, 0644); - - -/* Clock divider ops (non-atomic shared register access) */ -static DEFINE_SPINLOCK(pll_div_lock); - -static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate); -static void tegra11_pll_div_clk_init(struct clk *c) -{ - if (c->flags & DIV_U71) { - u32 val, divu71; - if (c->parent->state == OFF) - c->ops->disable(c); - - val = clk_readl(c->reg); - val >>= c->reg_shift; - c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; - if (!(val & PLL_OUT_RESET_DISABLE)) - c->state = OFF; - - if (c->u.pll_div.default_rate) { - int ret = tegra11_pll_div_clk_set_rate( - c, c->u.pll_div.default_rate); - if (!ret) - return; - } - divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; - c->div = (divu71 + 2); - c->mul = 2; - } else if (c->flags & DIV_2) { - c->state = ON; - if (c->flags & (PLLD | PLLX)) { - c->div = 2; - c->mul = 1; - } - else - BUG(); - } else if (c->flags & PLLU) { - u32 val = clk_readl(c->reg); - c->state = val & (0x1 << c->reg_shift) ? ON : OFF; - } else { - c->state = ON; - c->div = 1; - c->mul = 1; - } -} - -static int tegra11_pll_div_clk_enable(struct clk *c) -{ - u32 val; - u32 new_val; - unsigned long flags; - - pr_debug("%s: %s\n", __func__, c->name); - if (c->flags & DIV_U71) { - spin_lock_irqsave(&pll_div_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - spin_unlock_irqrestore(&pll_div_lock, flags); - return 0; - } else if (c->flags & DIV_2) { - return 0; - } else if (c->flags & PLLU) { - clk_lock_save(c->parent, &flags); - val = clk_readl(c->reg) | (0x1 << c->reg_shift); - clk_writel_delay(val, c->reg); - clk_unlock_restore(c->parent, &flags); - return 0; - } - return -EINVAL; -} - -static void tegra11_pll_div_clk_disable(struct clk *c) -{ - u32 val; - u32 new_val; - unsigned long flags; - - pr_debug("%s: %s\n", __func__, c->name); - if (c->flags & DIV_U71) { - spin_lock_irqsave(&pll_div_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - spin_unlock_irqrestore(&pll_div_lock, flags); - } else if (c->flags & PLLU) { - clk_lock_save(c->parent, &flags); - val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); - clk_writel_delay(val, c->reg); - clk_unlock_restore(c->parent, &flags); - } -} - -static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val; - u32 new_val; - int divider_u71; - unsigned long parent_rate = clk_get_rate(c->parent); - unsigned long flags; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider_u71 >= 0) { - spin_lock_irqsave(&pll_div_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - if (c->flags & DIV_U71_FIXED) - new_val |= PLL_OUT_OVERRIDE; - new_val &= ~PLL_OUT_RATIO_MASK; - new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - c->div = divider_u71 + 2; - c->mul = 2; - spin_unlock_irqrestore(&pll_div_lock, flags); - return 0; - } - } else if (c->flags & DIV_2) - return clk_set_rate(c->parent, rate * 2); - - return -EINVAL; -} - -static long tegra11_pll_div_clk_round_rate(struct clk *c, unsigned long rate) -{ - int divider; - unsigned long parent_rate = clk_get_rate(c->parent); - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_2) - /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ - return rate; - - return -EINVAL; -} - -static struct clk_ops tegra_pll_div_ops = { - .init = tegra11_pll_div_clk_init, - .enable = tegra11_pll_div_clk_enable, - .disable = tegra11_pll_div_clk_disable, - .set_rate = tegra11_pll_div_clk_set_rate, - .round_rate = tegra11_pll_div_clk_round_rate, -}; - -/* Periph clk ops */ -static inline u32 periph_clk_source_mask(struct clk *c) -{ - if (c->u.periph.src_mask) - return c->u.periph.src_mask; - else if (c->flags & MUX8) - return 7 << 29; - else if (c->flags & MUX_PWM) - return 3 << 28; - else if (c->flags & MUX_CLK_OUT) - return 3 << (c->u.periph.clk_num + 4); - else if (c->flags & PLLD) - return PLLD_BASE_DSI_MUX_MASK; - else - return 3 << 30; -} - -static inline u32 periph_clk_source_shift(struct clk *c) -{ - if (c->u.periph.src_shift) - return c->u.periph.src_shift; - else if (c->flags & MUX8) - return 29; - else if (c->flags & MUX_PWM) - return 28; - else if (c->flags & MUX_CLK_OUT) - return c->u.periph.clk_num + 4; - else if (c->flags & PLLD) - return PLLD_BASE_DSI_MUX_SHIFT; - else - return 30; -} - -static void tegra11_periph_clk_init(struct clk *c) -{ - u32 val = clk_readl(c->reg); - const struct clk_mux_sel *mux = 0; - const struct clk_mux_sel *sel; - if (c->flags & MUX) { - for (sel = c->inputs; sel->input != NULL; sel++) { - if (((val & periph_clk_source_mask(c)) >> - periph_clk_source_shift(c)) == sel->value) - mux = sel; - } - BUG_ON(!mux); - - c->parent = mux->input; - } else { - if (c->flags & PLLU) { - /* for xusb_hs clock enforce SS div2 source */ - val &= ~periph_clk_source_mask(c); - clk_writel_delay(val, c->reg); - } - c->parent = c->inputs[0].input; - } - - /* if peripheral is left under reset - enforce safe rate */ - if (!(c->flags & PERIPH_NO_RESET) && - (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))) { - tegra_periph_clk_safe_rate_init(c); - val = clk_readl(c->reg); - } - - if (c->flags & DIV_U71) { - u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; - if (c->flags & DIV_U71_IDLE) { - val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << - PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); - val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << - PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); - clk_writel(val, c->reg); - } - c->div = divu71 + 2; - c->mul = 2; - } else if (c->flags & DIV_U151) { - u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; - if ((c->flags & DIV_U151_UART) && - (!(val & PERIPH_CLK_UART_DIV_ENB))) { - divu151 = 0; - } - c->div = divu151 + 2; - c->mul = 2; - } else if (c->flags & DIV_U16) { - u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; - c->div = divu16 + 1; - c->mul = 1; - } else { - c->div = 1; - c->mul = 1; - } - - if (c->flags & PERIPH_NO_ENB) { - c->state = c->parent->state; - return; - } - - c->state = ON; - - if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) - c->state = OFF; - if (!(c->flags & PERIPH_NO_RESET)) - if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) - c->state = OFF; -} - -static int tegra11_periph_clk_enable(struct clk *c) -{ - unsigned long flags; - pr_debug("%s on clock %s\n", __func__, c->name); - - if (c->flags & PERIPH_NO_ENB) - return 0; - - spin_lock_irqsave(&periph_refcount_lock, flags); - - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) { - spin_unlock_irqrestore(&periph_refcount_lock, flags); - return 0; - } - - clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); - if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) { - if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) { - udelay(RESET_PROPAGATION_DELAY); - clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c)); - } - } - spin_unlock_irqrestore(&periph_refcount_lock, flags); - return 0; -} - -static void tegra11_periph_clk_disable(struct clk *c) -{ - unsigned long val, flags; - pr_debug("%s on clock %s\n", __func__, c->name); - - if (c->flags & PERIPH_NO_ENB) - return; - - spin_lock_irqsave(&periph_refcount_lock, flags); - - if (c->refcnt) - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; - - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { - /* If peripheral is in the APB bus then read the APB bus to - * flush the write operation in apb bus. This will avoid the - * peripheral access after disabling clock*/ - if (c->flags & PERIPH_ON_APB) - val = tegra_read_chipid(); - - clk_writel_delay( - PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); - } - spin_unlock_irqrestore(&periph_refcount_lock, flags); -} - -static void tegra11_periph_clk_reset(struct clk *c, bool assert) -{ - unsigned long val; - pr_debug("%s %s on clock %s\n", __func__, - assert ? "assert" : "deassert", c->name); - - if (c->flags & PERIPH_NO_ENB) - return; - - if (!(c->flags & PERIPH_NO_RESET)) { - if (assert) { - /* If peripheral is in the APB bus then read the APB - * bus to flush the write operation in apb bus. This - * will avoid the peripheral access after disabling - * clock */ - if (c->flags & PERIPH_ON_APB) - val = tegra_read_chipid(); - - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_SET_REG(c)); - } else - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_CLR_REG(c)); - } -} - -static int tegra11_periph_clk_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - const struct clk_mux_sel *sel; - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - - if (!(c->flags & MUX)) - return (p == c->parent) ? 0 : (-EINVAL); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - val = clk_readl(c->reg); - val &= ~periph_clk_source_mask(c); - val |= (sel->value << periph_clk_source_shift(c)); - - if (c->refcnt) - clk_enable(p); - - clk_writel_delay(val, c->reg); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - - return -EINVAL; -} - -static int tegra11_periph_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val; - int divider; - unsigned long parent_rate = clk_get_rate(c->parent); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; - val |= divider; - clk_writel_delay(val, c->reg); - c->div = divider + 2; - c->mul = 2; - return 0; - } - } else if (c->flags & DIV_U151) { - divider = clk_div151_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; - val |= divider; - if (c->flags & DIV_U151_UART) { - if (divider) - val |= PERIPH_CLK_UART_DIV_ENB; - else - val &= ~PERIPH_CLK_UART_DIV_ENB; - } - clk_writel_delay(val, c->reg); - c->div = divider + 2; - c->mul = 2; - return 0; - } - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; - val |= divider; - clk_writel_delay(val, c->reg); - c->div = divider + 1; - c->mul = 1; - return 0; - } - } else if (parent_rate <= rate) { - c->div = 1; - c->mul = 1; - return 0; - } - return -EINVAL; -} - -static long tegra11_periph_clk_round_rate(struct clk *c, - unsigned long rate) -{ - int divider; - unsigned long parent_rate = clk_get_rate(c->parent); - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_U151) { - divider = clk_div151_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate, divider + 1); - } - return -EINVAL; -} - -static struct clk_ops tegra_periph_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_periph_clk_set_parent, - .set_rate = &tegra11_periph_clk_set_rate, - .round_rate = &tegra11_periph_clk_round_rate, - .reset = &tegra11_periph_clk_reset, -}; - -/* 1x shared bus ops */ -static long tegra11_1xbus_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - int divider; - unsigned long source_rate, round_rate; - struct clk *new_parent; - - rate = max(rate, c->min_rate); - - new_parent = (rate <= c->u.periph.threshold) ? - c->u.periph.pll_low : c->u.periph.pll_high; - source_rate = clk_get_rate(new_parent); - - divider = clk_div71_get_divider(source_rate, rate, c->flags, - up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP); - - if (divider < 0) - return c->min_rate; - - round_rate = source_rate * 2 / (divider + 2); - - if (round_rate > c->max_rate) { - divider += c->flags & DIV_U71_INT ? 2 : 1; -#if !DIVIDER_1_5_ALLOWED - divider = max(2, divider); -#endif - round_rate = source_rate * 2 / (divider + 2); - } - - if (new_parent == c->u.periph.pll_high) { - /* Prevent oscillation across threshold */ - if (round_rate <= c->u.periph.threshold) - round_rate = c->u.periph.threshold; - } - return round_rate; -} - -static long tegra11_1xbus_round_rate(struct clk *c, unsigned long rate) -{ - return tegra11_1xbus_round_updown(c, rate, true); -} - -static int tegra11_1xbus_set_rate(struct clk *c, unsigned long rate) -{ - /* Compensate rate truncating during rounding */ - return tegra11_periph_clk_set_rate(c, rate + 1); -} - -static int tegra11_clk_1xbus_update(struct clk *c) -{ - int ret; - struct clk *new_parent; - unsigned long rate, old_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra11_clk_shared_bus_update(c, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(c); - pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n", - c->name, old_rate, c->parent->name, rate); - if (rate == old_rate) - return 0; - - if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) { - unsigned long r, m = c->max_rate; - r = clk_get_rate(c->u.periph.pll_low); - c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul; - r = clk_get_rate(c->u.periph.pll_high); - c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul; - } - - new_parent = (rate <= c->u.periph.threshold) ? - c->u.periph.pll_low : c->u.periph.pll_high; - - /* - * The transition procedure below is guaranteed to switch to the target - * parent/rate without violation of max clock limits. It would attempt - * to switch without dip in bus rate if it is possible, but this cannot - * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with - * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz, - * and there is no way to avoid rate dip in this case). - */ - if (new_parent != c->parent) { - int interim_div = 0; - /* Switching to pll_high may over-clock bus if current divider - is too small - increase divider to safe value */ - if ((new_parent == c->u.periph.pll_high) && - (c->div < c->u.periph.min_div_high)) - interim_div = c->u.periph.min_div_high; - - /* Switching to pll_low may dip down rate if current divider - is too big - decrease divider as much as we can */ - if ((new_parent == c->u.periph.pll_low) && - (c->div > c->u.periph.min_div_low)) - interim_div = c->u.periph.min_div_low; - - if (interim_div) { - u64 interim_rate = old_rate * c->div; - do_div(interim_rate, interim_div); - ret = clk_set_rate_locked(c, interim_rate); - if (ret) { - pr_err("Failed to set %s rate to %lu\n", - c->name, (unsigned long)interim_rate); - return ret; - } - pr_debug("1xbus %s: rate %lu on parent %s\n", c->name, - clk_get_rate_locked(c), c->parent->name); - } - - ret = clk_set_parent_locked(c, new_parent); - if (ret) { - pr_err("Failed to set %s parent %s\n", - c->name, new_parent->name); - return ret; - } - - old_rate = clk_get_rate_locked(c); - pr_debug("1xbus %s: rate %lu on parent %s\n", c->name, - old_rate, c->parent->name); - if (rate == old_rate) - return 0; - } - - ret = clk_set_rate_locked(c, rate); - if (ret) { - pr_err("Failed to set %s rate to %lu\n", c->name, rate); - return ret; - } - pr_debug("1xbus %s: rate %lu on parent %s\n", c->name, - clk_get_rate_locked(c), c->parent->name); - return 0; - -} - -static struct clk_ops tegra_1xbus_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_periph_clk_set_parent, - .set_rate = &tegra11_1xbus_set_rate, - .round_rate = &tegra11_1xbus_round_rate, - .reset = &tegra11_periph_clk_reset, - .shared_bus_update = &tegra11_clk_1xbus_update, -}; - -/* msenc clock propagation WAR for bug 1005168 */ -static int tegra11_msenc_clk_enable(struct clk *c) -{ - int ret = tegra11_periph_clk_enable(c); - if (ret) - return ret; - - clk_writel(0, LVL2_CLK_GATE_OVRE); - clk_writel(0x00400000, LVL2_CLK_GATE_OVRE); - udelay(1); - clk_writel(0, LVL2_CLK_GATE_OVRE); - return 0; -} - -static struct clk_ops tegra_msenc_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_msenc_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_periph_clk_set_parent, - .set_rate = &tegra11_periph_clk_set_rate, - .round_rate = &tegra11_periph_clk_round_rate, - .reset = &tegra11_periph_clk_reset, -}; -/* Periph extended clock configuration ops */ -static int -tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_VI_INP_SEL) { - u32 val = clk_readl(c->reg); - val &= ~PERIPH_CLK_VI_SEL_EX_MASK; - val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & - PERIPH_CLK_VI_SEL_EX_MASK; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_vi_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_periph_clk_set_parent, - .set_rate = &tegra11_periph_clk_set_rate, - .round_rate = &tegra11_periph_clk_round_rate, - .clk_cfg_ex = &tegra11_vi_clk_cfg_ex, - .reset = &tegra11_periph_clk_reset, -}; - -static int -tegra11_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { - u32 val = clk_readl(c->reg); - if (setting) - val |= PERIPH_CLK_NAND_DIV_EX_ENB; - else - val &= ~PERIPH_CLK_NAND_DIV_EX_ENB; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_nand_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_periph_clk_set_parent, - .set_rate = &tegra11_periph_clk_set_rate, - .round_rate = &tegra11_periph_clk_round_rate, - .clk_cfg_ex = &tegra11_nand_clk_cfg_ex, - .reset = &tegra11_periph_clk_reset, -}; - - -static int -tegra11_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_DTV_INVERT) { - u32 val = clk_readl(c->reg); - if (setting) - val |= PERIPH_CLK_DTV_POLARITY_INV; - else - val &= ~PERIPH_CLK_DTV_POLARITY_INV; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_dtv_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_periph_clk_set_parent, - .set_rate = &tegra11_periph_clk_set_rate, - .round_rate = &tegra11_periph_clk_round_rate, - .clk_cfg_ex = &tegra11_dtv_clk_cfg_ex, - .reset = &tegra11_periph_clk_reset, -}; - -static int tegra11_dsi_clk_set_parent(struct clk *c, struct clk *p) -{ - const struct clk_mux_sel *sel; - struct clk *d = tegra_get_clock_by_name("pll_d"); - if (c->reg != d->reg) - d = tegra_get_clock_by_name("pll_d2"); - - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - if (c->refcnt) - clk_enable(p); - - /* The DSI parent selection bit is in PLLD base - register - can not do direct r-m-w, must be - protected by PLLD lock */ - tegra_clk_cfg_ex( - d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - - return -EINVAL; -} - -static struct clk_ops tegra_dsi_clk_ops = { - .init = &tegra11_periph_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_parent = &tegra11_dsi_clk_set_parent, - .set_rate = &tegra11_periph_clk_set_rate, - .round_rate = &tegra11_periph_clk_round_rate, - .reset = &tegra11_periph_clk_reset, -}; - -/* xusb common clock gate - enabled on init and never disabled */ -static void tegra11_xusb_gate_clk_init(struct clk *c) -{ - tegra11_periph_clk_enable(c); -} - -static struct clk_ops tegra_xusb_gate_clk_ops = { - .init = tegra11_xusb_gate_clk_init, -}; - -/* pciex clock support only reset function */ -static struct clk_ops tegra_pciex_clk_ops = { - .reset = tegra11_periph_clk_reset, -}; - -/* Output clock ops */ - -static DEFINE_SPINLOCK(clk_out_lock); - -static void tegra11_clk_out_init(struct clk *c) -{ - const struct clk_mux_sel *mux = 0; - const struct clk_mux_sel *sel; - u32 val = pmc_readl(c->reg); - - c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; - c->mul = 1; - c->div = 1; - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (((val & periph_clk_source_mask(c)) >> - periph_clk_source_shift(c)) == sel->value) - mux = sel; - } - BUG_ON(!mux); - c->parent = mux->input; -} - -static int tegra11_clk_out_enable(struct clk *c) -{ - u32 val; - unsigned long flags; - - pr_debug("%s on clock %s\n", __func__, c->name); - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val |= (0x1 << c->u.periph.clk_num); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); - - return 0; -} - -static void tegra11_clk_out_disable(struct clk *c) -{ - u32 val; - unsigned long flags; - - pr_debug("%s on clock %s\n", __func__, c->name); - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val &= ~(0x1 << c->u.periph.clk_num); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); -} - -static int tegra11_clk_out_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - unsigned long flags; - const struct clk_mux_sel *sel; - - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - if (c->refcnt) - clk_enable(p); - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val &= ~periph_clk_source_mask(c); - val |= (sel->value << periph_clk_source_shift(c)); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - return -EINVAL; -} - -static struct clk_ops tegra_clk_out_ops = { - .init = &tegra11_clk_out_init, - .enable = &tegra11_clk_out_enable, - .disable = &tegra11_clk_out_disable, - .set_parent = &tegra11_clk_out_set_parent, -}; - - -/* External memory controller clock ops */ -static void tegra11_emc_clk_init(struct clk *c) -{ - tegra11_periph_clk_init(c); - tegra_emc_dram_type_init(c); -} - -static long tegra11_emc_clk_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - unsigned long new_rate = max(rate, c->min_rate); - - new_rate = tegra_emc_round_rate_updown(new_rate, up); - if (IS_ERR_VALUE(new_rate)) - new_rate = c->max_rate; - - return new_rate; -} - -static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate) -{ - return tegra11_emc_clk_round_updown(c, rate, true); -} - -static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - u32 div_value; - struct clk *p; - - /* The tegra11x memory controller has an interlock with the clock - * block that allows memory shadowed registers to be updated, - * and then transfer them to the main registers at the same - * time as the clock update without glitches. During clock change - * operation both clock parent and divider may change simultaneously - * to achieve requested rate. */ - p = tegra_emc_predict_parent(rate, &div_value); - div_value += 2; /* emc has fractional DIV_U71 divider */ - if (IS_ERR_OR_NULL(p)) { - pr_err("%s: Failed to predict emc parent for rate %lu\n", - __func__, rate); - return -EINVAL; - } - - if (p == c->parent) { - if (div_value == c->div) - return 0; - } else if (c->refcnt) - clk_enable(p); - - ret = tegra_emc_set_rate(rate); - if (ret < 0) - return ret; - - if (p != c->parent) { - if(c->refcnt && c->parent) - clk_disable(c->parent); - clk_reparent(c, p); - } - c->div = div_value; - c->mul = 2; - return 0; -} - -static int tegra11_clk_emc_bus_update(struct clk *bus) -{ - struct clk *p = NULL; - unsigned long rate, old_rate, parent_rate, backup_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(bus); - if (rate == old_rate) - return 0; - - if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) { - if (bus->parent == p) { - /* need backup to re-lock current parent */ - int ret; - if (IS_ERR_VALUE(backup_rate)) { - pr_err("%s: No backup for %s rate %lu\n", - __func__, bus->name, rate); - return -EINVAL; - } - - /* set volatge for backup rate if going up */ - if (backup_rate > old_rate) { - ret = tegra_dvfs_set_rate(bus, backup_rate); - if (ret) { - pr_err("%s: dvfs failed on %s rate %lu\n", - __func__, bus->name, backup_rate); - return -EINVAL; - } - } - - trace_clock_set_rate(bus->name, backup_rate, 0); - ret = bus->ops->set_rate(bus, backup_rate); - if (ret) { - pr_err("%s: Failed to backup %s for rate %lu\n", - __func__, bus->name, rate); - return -EINVAL; - } - clk_rate_change_notify(bus, backup_rate); - } - if (p->refcnt) { - pr_err("%s: %s has other than emc child\n", - __func__, p->name); - return -EINVAL; - } - - if (clk_set_rate(p, parent_rate)) { - pr_err("%s: Failed to set %s rate %lu\n", - __func__, p->name, parent_rate); - return -EINVAL; - } - } - - return clk_set_rate_locked(bus, rate); -} - -static struct clk_ops tegra_emc_clk_ops = { - .init = &tegra11_emc_clk_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_rate = &tegra11_emc_clk_set_rate, - .round_rate = &tegra11_emc_clk_round_rate, - .round_rate_updown = &tegra11_emc_clk_round_updown, - .reset = &tegra11_periph_clk_reset, - .shared_bus_update = &tegra11_clk_emc_bus_update, -}; - -/* Clock doubler ops (non-atomic shared register access) */ -static DEFINE_SPINLOCK(doubler_lock); - -static void tegra11_clk_double_init(struct clk *c) -{ - u32 val = clk_readl(c->reg); - c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; - c->div = 1; - c->state = ON; - if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) - c->state = OFF; -}; - -static int tegra11_clk_double_set_rate(struct clk *c, unsigned long rate) -{ - u32 val; - unsigned long parent_rate = clk_get_rate(c->parent); - unsigned long flags; - - if (rate == parent_rate) { - spin_lock_irqsave(&doubler_lock, flags); - val = clk_readl(c->reg) | (0x1 << c->reg_shift); - clk_writel(val, c->reg); - c->mul = 1; - c->div = 1; - spin_unlock_irqrestore(&doubler_lock, flags); - return 0; - } else if (rate == 2 * parent_rate) { - spin_lock_irqsave(&doubler_lock, flags); - val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); - clk_writel(val, c->reg); - c->mul = 2; - c->div = 1; - spin_unlock_irqrestore(&doubler_lock, flags); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_clk_double_ops = { - .init = &tegra11_clk_double_init, - .enable = &tegra11_periph_clk_enable, - .disable = &tegra11_periph_clk_disable, - .set_rate = &tegra11_clk_double_set_rate, -}; - -/* Audio sync clock ops */ -static int tegra11_sync_source_set_rate(struct clk *c, unsigned long rate) -{ - c->rate = rate; - return 0; -} - -static struct clk_ops tegra_sync_source_ops = { - .set_rate = &tegra11_sync_source_set_rate, -}; - -static void tegra11_audio_sync_clk_init(struct clk *c) -{ - int source; - const struct clk_mux_sel *sel; - u32 val = clk_readl(c->reg); - c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; - source = val & AUDIO_SYNC_SOURCE_MASK; - for (sel = c->inputs; sel->input != NULL; sel++) - if (sel->value == source) - break; - BUG_ON(sel->input == NULL); - c->parent = sel->input; -} - -static int tegra11_audio_sync_clk_enable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); - return 0; -} - -static void tegra11_audio_sync_clk_disable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); -} - -static int tegra11_audio_sync_clk_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - const struct clk_mux_sel *sel; - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - val = clk_readl(c->reg); - val &= ~AUDIO_SYNC_SOURCE_MASK; - val |= sel->value; - - if (c->refcnt) - clk_enable(p); - - clk_writel(val, c->reg); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - - return -EINVAL; -} - -static struct clk_ops tegra_audio_sync_clk_ops = { - .init = tegra11_audio_sync_clk_init, - .enable = tegra11_audio_sync_clk_enable, - .disable = tegra11_audio_sync_clk_disable, - .set_parent = tegra11_audio_sync_clk_set_parent, -}; - - -/* cbus ops */ -/* - * Some clocks require dynamic re-locking of source PLL in order to - * achieve frequency scaling granularity that matches characterized - * core voltage steps. The cbus clock creates a shared bus that - * provides a virtual root for such clocks to hide and synchronize - * parent PLL re-locking as well as backup operations. -*/ - -static void tegra11_clk_cbus_init(struct clk *c) -{ - c->state = OFF; - c->set = true; -} - -static int tegra11_clk_cbus_enable(struct clk *c) -{ - return 0; -} - -/* select 5 steps below top rate as fine granularity region */ -#define CBUS_FINE_GRANULARITY 12000000 /* 12 MHz */ -#define CBUS_FINE_GRANULARITY_RANGE (5 * CBUS_FINE_GRANULARITY) - -static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - int i, n; - - if (!c->dvfs) { - if (!c->min_rate) - c->min_rate = c->parent->min_rate; - rate = max(rate, c->min_rate); - return rate; - } - - /* update min now, since no dvfs table was available during init - (skip placeholder entries set to 1 kHz) */ - if (!c->min_rate) { - for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { - if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) { - c->min_rate = c->dvfs->freqs[i]; - break; - } - } - BUG_ON(!c->min_rate); - } - rate = max(rate, c->min_rate); - - /* for top rates in fine granularity region don't clip to dvfs table */ - n = c->dvfs->num_freqs; - if ((n >= 2) && (c->dvfs->millivolts[n-1] <= c->dvfs->max_millivolts) && - (rate > c->dvfs->freqs[n-2])) { - unsigned long threshold = max(c->dvfs->freqs[n-1], - c->dvfs->freqs[n-2] + CBUS_FINE_GRANULARITY_RANGE); - threshold -= CBUS_FINE_GRANULARITY_RANGE; - - if (rate == threshold) - return threshold; - - if (rate < threshold) - return up ? threshold : c->dvfs->freqs[n-2]; - - rate = (up ? DIV_ROUND_UP(rate, CBUS_FINE_GRANULARITY) : - rate / CBUS_FINE_GRANULARITY) * CBUS_FINE_GRANULARITY; - rate = clamp(rate, threshold, c->dvfs->freqs[n-1]); - return rate; - } - - /* clip rate to dvfs table steps */ - for (i = 0; ; i++) { - unsigned long f = c->dvfs->freqs[i]; - int mv = c->dvfs->millivolts[i]; - if ((f >= rate) || (mv >= c->dvfs->max_millivolts) || - ((i + 1) >= c->dvfs->num_freqs)) { - if (!up && i && (f > rate)) - i--; - break; - } - } - return c->dvfs->freqs[i]; -} - -static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate) -{ - return tegra11_clk_cbus_round_updown(c, rate, true); -} - -static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort) -{ - int ret = 0; - - /* set new divider if it is bigger than the current one */ - if (c->div < c->mul * div) { - ret = clk_set_div(c, div); - if (ret) { - pr_err("%s: failed to set %s clock divider %u: %d\n", - __func__, c->name, div, ret); - if (abort) - return ret; - } - } - - if (c->parent != p) { - ret = clk_set_parent(c, p); - if (ret) { - pr_err("%s: failed to set %s clock parent %s: %d\n", - __func__, c->name, p->name, ret); - if (abort) - return ret; - } - } - - /* set new divider if it is smaller than the current one */ - if (c->div > c->mul * div) { - ret = clk_set_div(c, div); - if (ret) - pr_err("%s: failed to set %s clock divider %u: %d\n", - __func__, c->name, div, ret); - } - - return ret; -} - -static int cbus_backup(struct clk *c) -{ - int ret; - struct clk *user; - - list_for_each_entry(user, &c->shared_bus_list, - u.shared_bus_user.node) { - struct clk *client = user->u.shared_bus_user.client; - if (client && (client->state == ON) && - (client->parent == c->parent)) { - ret = cbus_switch_one(client, - c->shared_bus_backup.input, - c->shared_bus_backup.value * - user->div, true); - if (ret) - return ret; - } - } - return 0; -} - -static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - struct clk *user; - - list_for_each_entry(user, &c->shared_bus_list, - u.shared_bus_user.node) { - struct clk *client = user->u.shared_bus_user.client; - if (client && client->refcnt && (client->parent == c->parent)) { - ret = tegra_dvfs_set_rate(c, rate); - if (ret) - return ret; - } - } - return 0; -} - -static void cbus_restore(struct clk *c) -{ - struct clk *user; - - list_for_each_entry(user, &c->shared_bus_list, - u.shared_bus_user.node) { - if (user->u.shared_bus_user.client) - cbus_switch_one(user->u.shared_bus_user.client, - c->parent, c->div * user->div, false); - } -} - -static int get_next_backup_div(struct clk *c, unsigned long rate) -{ - u32 div = c->div; - unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input); - - rate = max(rate, clk_get_rate_locked(c)); - rate = rate - (rate >> 2); /* 25% margin for backup rate */ - if ((u64)rate * div < backup_rate) - div = DIV_ROUND_UP(backup_rate, rate); - - BUG_ON(!div); - return div; -} - -static int tegra11_clk_cbus_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - bool dramp; - - if (rate == 0) - return 0; - - ret = clk_enable(c->parent); - if (ret) { - pr_err("%s: failed to enable %s clock: %d\n", - __func__, c->name, ret); - return ret; - } - - dramp = tegra11_is_dyn_ramp(c->parent, rate * c->div, false); - if (!dramp) { - c->shared_bus_backup.value = get_next_backup_div(c, rate); - ret = cbus_backup(c); - if (ret) - goto out; - } - - ret = clk_set_rate(c->parent, rate * c->div); - if (ret) { - pr_err("%s: failed to set %s clock rate %lu: %d\n", - __func__, c->name, rate, ret); - goto out; - } - - /* Safe voltage setting is taken care of by cbus clock dvfs; the call - * below only records requirements for each enabled client. - */ - if (dramp) - ret = cbus_dvfs_set_rate(c, rate); - - cbus_restore(c); - -out: - clk_disable(c->parent); - return ret; -} - -static inline void cbus_move_enabled_user( - struct clk *user, struct clk *dst, struct clk *src) -{ - clk_enable(dst); - list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list); - clk_disable(src); - clk_reparent(user, dst); -} - -#ifdef CONFIG_TEGRA_DYNAMIC_CBUS -static int tegra11_clk_cbus_update(struct clk *bus) -{ - int ret, mv; - struct clk *slow = NULL; - struct clk *top = NULL; - unsigned long rate; - unsigned long old_rate; - unsigned long ceiling; - - if (detach_shared_bus) - return 0; - - rate = tegra11_clk_shared_bus_update(bus, &top, &slow, &ceiling); - - /* use dvfs table of the slowest enabled client as cbus dvfs table */ - if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) { - int i; - unsigned long *dest = &bus->dvfs->freqs[0]; - unsigned long *src = - &slow->u.shared_bus_user.client->dvfs->freqs[0]; - if (slow->div > 1) - for (i = 0; i < bus->dvfs->num_freqs; i++) - dest[i] = src[i] * slow->div; - else - memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs); - } - - /* update bus state variables and rate */ - bus->u.cbus.slow_user = slow; - bus->u.cbus.top_user = top; - - rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling); - mv = tegra_dvfs_predict_millivolts(bus, rate); - if (IS_ERR_VALUE(mv)) - return -EINVAL; - - if (bus->dvfs) { - mv -= bus->dvfs->cur_millivolts; - if (bus->refcnt && (mv > 0)) { - ret = tegra_dvfs_set_rate(bus, rate); - if (ret) - return ret; - } - } - - old_rate = clk_get_rate_locked(bus); - if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) { - ret = bus->ops->set_rate(bus, rate); - if (ret) - return ret; - } - - if (bus->dvfs) { - if (bus->refcnt && (mv <= 0)) { - ret = tegra_dvfs_set_rate(bus, rate); - if (ret) - return ret; - } - } - - clk_rate_change_notify(bus, rate); - return 0; -}; -#else -static int tegra11_clk_cbus_update(struct clk *bus) -{ - unsigned long rate, old_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(bus); - if (rate == old_rate) - return 0; - - return clk_set_rate_locked(bus, rate); -} -#endif - -static int tegra11_clk_cbus_migrate_users(struct clk *user) -{ -#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS - struct clk *src_bus, *dst_bus, *top_user, *c; - struct list_head *pos, *n; - - if (!user->u.shared_bus_user.client || !user->inputs) - return 0; - - /* Dual cbus on Tegra11 */ - src_bus = user->inputs[0].input; - dst_bus = user->inputs[1].input; - - if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user) - return 0; - - /* Make sure top user on the source bus is requesting highest rate */ - if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user && - bus_user_request_is_lower(src_bus->u.cbus.top_user, - dst_bus->u.cbus.top_user))) - swap(src_bus, dst_bus); - - /* If top user is the slow one on its own (source) bus, do nothing */ - top_user = src_bus->u.cbus.top_user; - BUG_ON(!top_user->u.shared_bus_user.client); - if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user)) - return 0; - - /* If source bus top user is slower than all users on destination bus, - move top user; otherwise move all users slower than the top one */ - if (!dst_bus->u.cbus.slow_user || - !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) { - cbus_move_enabled_user(top_user, dst_bus, src_bus); - } else { - list_for_each_safe(pos, n, &src_bus->shared_bus_list) { - c = list_entry(pos, struct clk, u.shared_bus_user.node); - if (c->u.shared_bus_user.enabled && - c->u.shared_bus_user.client && - bus_user_is_slower(c, top_user)) - cbus_move_enabled_user(c, dst_bus, src_bus); - } - } - - /* Update destination bus 1st (move clients), then source */ - tegra_clk_shared_bus_update(dst_bus); - tegra_clk_shared_bus_update(src_bus); -#endif - return 0; -} - -static struct clk_ops tegra_clk_cbus_ops = { - .init = tegra11_clk_cbus_init, - .enable = tegra11_clk_cbus_enable, - .set_rate = tegra11_clk_cbus_set_rate, - .round_rate = tegra11_clk_cbus_round_rate, - .round_rate_updown = tegra11_clk_cbus_round_updown, - .shared_bus_update = tegra11_clk_cbus_update, -}; - -/* shared bus ops */ -/* - * Some clocks may have multiple downstream users that need to request a - * higher clock rate. Shared bus clocks provide a unique shared_bus_user - * clock to each user. The frequency of the bus is set to the highest - * enabled shared_bus_user clock, with a minimum value set by the - * shared bus. - * - * Optionally shared bus may support users migration. Since shared bus and - * its * children (users) have reversed rate relations: user rates determine - * bus rate, * switching user from one parent/bus to another may change rates - * of both parents. Therefore we need a cross-bus lock on top of individual - * user and bus locks. For now, limit bus switch support to cbus only if - * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set. - */ - -static unsigned long tegra11_clk_shared_bus_update(struct clk *bus, - struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap) -{ - struct clk *c; - struct clk *slow = NULL; - struct clk *top = NULL; - - unsigned long override_rate = 0; - unsigned long top_rate = 0; - unsigned long rate = bus->min_rate; - unsigned long bw = 0; - unsigned long iso_bw = 0; - unsigned long ceiling = bus->max_rate; - unsigned long ceiling_but_iso = bus->max_rate; - u32 usage_flags = 0; - - list_for_each_entry(c, &bus->shared_bus_list, - u.shared_bus_user.node) { - /* - * Ignore requests from disabled floor and bw users, and from - * auto-users riding the bus. Always honor ceiling users, even - * if they are disabled - we do not want to keep enabled parent - * bus just because ceiling is set. - */ - if (c->u.shared_bus_user.enabled || - (c->u.shared_bus_user.mode == SHARED_CEILING) || - (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) { - unsigned long request_rate = c->u.shared_bus_user.rate * - (c->div ? : 1); - usage_flags |= c->u.shared_bus_user.usage_flag; - - switch (c->u.shared_bus_user.mode) { - case SHARED_ISO_BW: - iso_bw += request_rate; - if (iso_bw > bus->max_rate) - iso_bw = bus->max_rate; - /* fall thru */ - case SHARED_BW: - bw += request_rate; - if (bw > bus->max_rate) - bw = bus->max_rate; - break; - case SHARED_CEILING_BUT_ISO: - ceiling_but_iso = - min(request_rate, ceiling_but_iso); - break; - case SHARED_CEILING: - ceiling = min(request_rate, ceiling); - break; - case SHARED_OVERRIDE: - if (override_rate == 0) - override_rate = request_rate; - break; - case SHARED_AUTO: - break; - case SHARED_FLOOR: - default: - rate = max(request_rate, rate); - if (c->u.shared_bus_user.client - && request_rate) { - if (top_rate < request_rate) { - top_rate = request_rate; - top = c; - } else if ((top_rate == request_rate) && - bus_user_is_slower(c, top)) { - top = c; - } - } - } - if (c->u.shared_bus_user.client && - (!slow || bus_user_is_slower(c, slow))) - slow = c; - } - } - - if (bus->flags & PERIPH_EMC_ENB) - bw = tegra_emc_apply_efficiency( - bw, iso_bw, bus->max_rate, usage_flags, NULL); - - rate = override_rate ? : max(rate, bw); - ceiling = min(ceiling, ceiling_but_iso); - ceiling = override_rate ? bus->max_rate : ceiling; - - if (bus_top && bus_slow && rate_cap) { - /* If dynamic bus dvfs table, let the caller to complete - rounding and aggregation */ - *bus_top = top; - *bus_slow = slow; - *rate_cap = ceiling; - } else { - /* If satic bus dvfs table, complete rounding and aggregation */ - rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling); - } - - return rate; -}; - -static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus, - unsigned long rate, unsigned long ceiling) -{ - if (bus->ops && bus->ops->round_rate_updown) - ceiling = bus->ops->round_rate_updown(bus, ceiling, false); - - rate = min(rate, ceiling); - - if (bus->ops && bus->ops->round_rate) - rate = bus->ops->round_rate(bus, rate); - - return rate; -} - -static int tegra_clk_shared_bus_migrate_users(struct clk *user) -{ - if (detach_shared_bus) - return 0; - - /* Only cbus migration is supported */ - if (user->flags & PERIPH_ON_CBUS) - return tegra11_clk_cbus_migrate_users(user); - return -ENOSYS; -} - -static void tegra_clk_shared_bus_user_init(struct clk *c) -{ - c->max_rate = c->parent->max_rate; - c->u.shared_bus_user.rate = c->parent->max_rate; - c->state = OFF; - c->set = true; - - if ((c->u.shared_bus_user.mode == SHARED_CEILING) || - (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) { - c->state = ON; - c->refcnt++; - } - - if (c->u.shared_bus_user.client_id) { - c->u.shared_bus_user.client = - tegra_get_clock_by_name(c->u.shared_bus_user.client_id); - if (!c->u.shared_bus_user.client) { - pr_err("%s: could not find clk %s\n", __func__, - c->u.shared_bus_user.client_id); - return; - } - c->u.shared_bus_user.client->flags |= - c->parent->flags & PERIPH_ON_CBUS; - c->flags |= c->parent->flags & PERIPH_ON_CBUS; - c->div = c->u.shared_bus_user.client_div ? : 1; - c->mul = 1; - } - - list_add_tail(&c->u.shared_bus_user.node, - &c->parent->shared_bus_list); -} - -static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p) -{ - int ret; - const struct clk_mux_sel *sel; - - if (detach_shared_bus) - return 0; - - if (c->parent == p) - return 0; - - if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c))) - return -ENOSYS; - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) - break; - } - if (!sel->input) - return -EINVAL; - - if (c->refcnt) - clk_enable(p); - - list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list); - ret = tegra_clk_shared_bus_update(p); - if (ret) { - list_move_tail(&c->u.shared_bus_user.node, - &c->parent->shared_bus_list); - tegra_clk_shared_bus_update(c->parent); - clk_disable(p); - return ret; - } - - tegra_clk_shared_bus_update(c->parent); - - if (c->refcnt) - clk_disable(c->parent); - - clk_reparent(c, p); - - return 0; -} - -static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - - c->u.shared_bus_user.rate = rate; - ret = tegra_clk_shared_bus_update(c->parent); - - if (!ret && c->cross_clk_mutex && clk_cansleep(c)) - tegra_clk_shared_bus_migrate_users(c); - - return ret; -} - -static long tegra_clk_shared_bus_user_round_rate( - struct clk *c, unsigned long rate) -{ - /* Defer rounding requests until aggregated. BW users must not be - rounded at all, others just clipped to bus range (some clients - may use round api to find limits) */ - if ((c->u.shared_bus_user.mode != SHARED_BW) && - (c->u.shared_bus_user.mode != SHARED_ISO_BW)) { - if (c->div > 1) - rate *= c->div; - - if (rate > c->parent->max_rate) - rate = c->parent->max_rate; - else if (rate < c->parent->min_rate) - rate = c->parent->min_rate; - - if (c->div > 1) - rate /= c->div; - } - return rate; -} - -static int tegra_clk_shared_bus_user_enable(struct clk *c) -{ - int ret; - - c->u.shared_bus_user.enabled = true; - ret = tegra_clk_shared_bus_update(c->parent); - if (!ret && c->u.shared_bus_user.client) - ret = clk_enable(c->u.shared_bus_user.client); - - if (!ret && c->cross_clk_mutex && clk_cansleep(c)) - tegra_clk_shared_bus_migrate_users(c); - - return ret; -} - -static void tegra_clk_shared_bus_user_disable(struct clk *c) -{ - if (c->u.shared_bus_user.client) - clk_disable(c->u.shared_bus_user.client); - c->u.shared_bus_user.enabled = false; - tegra_clk_shared_bus_update(c->parent); - - if (c->cross_clk_mutex && clk_cansleep(c)) - tegra_clk_shared_bus_migrate_users(c); -} - -static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert) -{ - if (c->u.shared_bus_user.client) { - if (c->u.shared_bus_user.client->ops && - c->u.shared_bus_user.client->ops->reset) - c->u.shared_bus_user.client->ops->reset( - c->u.shared_bus_user.client, assert); - } -} - -static struct clk_ops tegra_clk_shared_bus_user_ops = { - .init = tegra_clk_shared_bus_user_init, - .enable = tegra_clk_shared_bus_user_enable, - .disable = tegra_clk_shared_bus_user_disable, - .set_parent = tegra_clk_shared_bus_user_set_parent, - .set_rate = tegra_clk_shared_bus_user_set_rate, - .round_rate = tegra_clk_shared_bus_user_round_rate, - .reset = tegra_clk_shared_bus_user_reset, -}; - -/* coupled gate ops */ -/* - * Some clocks may have common enable/disable control, but run at different - * rates, and have different dvfs tables. Coupled gate clock synchronize - * enable/disable operations for such clocks. - */ - -static int tegra11_clk_coupled_gate_enable(struct clk *c) -{ - int ret; - const struct clk_mux_sel *sel; - - BUG_ON(!c->inputs); - pr_debug("%s on clock %s\n", __func__, c->name); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == c->parent) - continue; - - ret = clk_enable(sel->input); - if (ret) { - while(sel != c->inputs) { - sel--; - if (sel->input == c->parent) - continue; - clk_disable(sel->input); - } - return ret; - } - } - - return tegra11_periph_clk_enable(c); -} - -static void tegra11_clk_coupled_gate_disable(struct clk *c) -{ - const struct clk_mux_sel *sel; - - BUG_ON(!c->inputs); - pr_debug("%s on clock %s\n", __func__, c->name); - - tegra11_periph_clk_disable(c); - - if (!c->refcnt) /* happens only on boot clean-up: don't propagate */ - return; - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == c->parent) - continue; - - if (sel->input->set) /* enforce coupling after boot only */ - clk_disable(sel->input); - } -} - -static struct clk_ops tegra_clk_coupled_gate_ops = { - .init = tegra11_periph_clk_init, - .enable = tegra11_clk_coupled_gate_enable, - .disable = tegra11_clk_coupled_gate_disable, - .reset = &tegra11_periph_clk_reset, -}; - - -/* Clock definitions */ -static struct clk tegra_clk_32k = { - .name = "clk_32k", - .rate = 32768, - .ops = NULL, - .max_rate = 32768, -}; - -static struct clk tegra_clk_m = { - .name = "clk_m", - .flags = ENABLE_ON_INIT, - .ops = &tegra_clk_m_ops, - .reg = 0x1fc, - .reg_shift = 28, - .max_rate = 48000000, -}; - -static struct clk tegra_clk_m_div2 = { - .name = "clk_m_div2", - .ops = &tegra_clk_m_div_ops, - .parent = &tegra_clk_m, - .mul = 1, - .div = 2, - .state = ON, - .max_rate = 24000000, -}; - -static struct clk tegra_clk_m_div4 = { - .name = "clk_m_div4", - .ops = &tegra_clk_m_div_ops, - .parent = &tegra_clk_m, - .mul = 1, - .div = 4, - .state = ON, - .max_rate = 12000000, -}; - -static struct clk tegra_pll_ref = { - .name = "pll_ref", - .flags = ENABLE_ON_INIT, - .ops = &tegra_pll_ref_ops, - .parent = &tegra_clk_m, - .max_rate = 26000000, -}; - -static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { - { 12000000, 624000000, 104, 1, 2}, - { 12000000, 600000000, 100, 1, 2}, - { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_c = { - .name = "pll_c", - .ops = &tegra_pllxc_ops, - .reg = 0x80, - .parent = &tegra_pll_ref, - .max_rate = 1400000000, - .u.pll = { - .input_min = 12000000, - .input_max = 800000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ - .vco_min = 600000000, - .vco_max = 1400000000, - .freq_table = tegra_pll_c_freq_table, - .lock_delay = 300, - .misc1 = 0x88 - 0x80, - .round_p_to_pdiv = pllxc_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_c_out1 = { - .name = "pll_c_out1", - .ops = &tegra_pll_div_ops, -#ifdef CONFIG_TEGRA_DUAL_CBUS - .flags = DIV_U71 | DIV_U71_INT, -#else - .flags = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS, -#endif - .parent = &tegra_pll_c, - .reg = 0x84, - .reg_shift = 0, - .max_rate = 700000000, -}; - -static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = { - { 12000000, 600000000, 100, 1, 2}, - { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_c2 = { - .name = "pll_c2", - .ops = &tegra_pllcx_ops, - .flags = PLL_ALT_MISC_REG, - .reg = 0x4e8, - .parent = &tegra_pll_ref, - .max_rate = 1200000000, - .u.pll = { - .input_min = 12000000, - .input_max = 48000000, - .cf_min = 12000000, - .cf_max = 19200000, - .vco_min = 624000000, - .vco_max = 1248000000, - .freq_table = tegra_pll_cx_freq_table, - .lock_delay = 300, - .misc1 = 0x4f0 - 0x4e8, - .round_p_to_pdiv = pllcx_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_c3 = { - .name = "pll_c3", - .ops = &tegra_pllcx_ops, - .flags = PLL_ALT_MISC_REG, - .reg = 0x4fc, - .parent = &tegra_pll_ref, - .max_rate = 1200000000, - .u.pll = { - .input_min = 12000000, - .input_max = 48000000, - .cf_min = 12000000, - .cf_max = 19200000, - .vco_min = 624000000, - .vco_max = 1248000000, - .freq_table = tegra_pll_cx_freq_table, - .lock_delay = 300, - .misc1 = 0x504 - 0x4fc, - .round_p_to_pdiv = pllcx_round_p_to_pdiv, - }, -}; - -static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { - { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */ - { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ - { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */ - { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */ - { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */ - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_m = { - .name = "pll_m", - .flags = PLLM, - .ops = &tegra_pllm_ops, - .reg = 0x90, - .parent = &tegra_pll_ref, - .max_rate = 1066000000, - .u.pll = { - .input_min = 12000000, - .input_max = 500000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ - .vco_min = 400000000, - .vco_max = 1066000000, - .freq_table = tegra_pll_m_freq_table, - .lock_delay = 300, - .misc1 = 0x98 - 0x90, - .round_p_to_pdiv = pllm_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_m_out1 = { - .name = "pll_m_out1", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_INT, - .parent = &tegra_pll_m, - .reg = 0x94, - .reg_shift = 0, - .max_rate = 1066000000, -}; - -static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { - { 12000000, 216000000, 432, 12, 2, 8}, - { 13000000, 216000000, 432, 13, 2, 8}, - { 16800000, 216000000, 360, 14, 2, 8}, - { 19200000, 216000000, 360, 16, 2, 8}, - { 26000000, 216000000, 432, 26, 2, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_p = { - .name = "pll_p", - .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, - .ops = &tegra_pllp_ops, - .reg = 0xa0, - .parent = &tegra_pll_ref, - .max_rate = 432000000, - .u.pll = { - .input_min = 2000000, - .input_max = 31000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 200000000, - .vco_max = 700000000, - .freq_table = tegra_pll_p_freq_table, - .lock_delay = 300, - }, -}; - -static struct clk tegra_pll_p_out1 = { - .name = "pll_p_out1", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED, - .parent = &tegra_pll_p, - .reg = 0xa4, - .reg_shift = 0, - .max_rate = 432000000, -}; - -static struct clk tegra_pll_p_out2 = { - .name = "pll_p_out2", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT, - .parent = &tegra_pll_p, - .reg = 0xa4, - .reg_shift = 16, - .max_rate = 432000000, -}; - -static struct clk tegra_pll_p_out3 = { - .name = "pll_p_out3", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED, - .parent = &tegra_pll_p, - .reg = 0xa8, - .reg_shift = 0, - .max_rate = 432000000, -}; - -static struct clk tegra_pll_p_out4 = { - .name = "pll_p_out4", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED, - .parent = &tegra_pll_p, - .reg = 0xa8, - .reg_shift = 16, - .max_rate = 432000000, -}; - -static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { - { 9600000, 282240000, 147, 5, 1, 4}, - { 9600000, 368640000, 192, 5, 1, 4}, - { 9600000, 240000000, 200, 8, 1, 8}, - - { 28800000, 282240000, 245, 25, 1, 8}, - { 28800000, 368640000, 320, 25, 1, 8}, - { 28800000, 240000000, 200, 24, 1, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_a = { - .name = "pll_a", - .flags = PLL_HAS_CPCON, - .ops = &tegra_pll_ops, - .reg = 0xb0, - .parent = &tegra_pll_p_out1, - .max_rate = 700000000, - .u.pll = { - .input_min = 2000000, - .input_max = 31000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 200000000, - .vco_max = 700000000, - .freq_table = tegra_pll_a_freq_table, - .lock_delay = 300, - }, -}; - -static struct clk tegra_pll_a_out0 = { - .name = "pll_a_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71, - .parent = &tegra_pll_a, - .reg = 0xb4, - .reg_shift = 0, - .max_rate = 100000000, -}; - -static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { - { 12000000, 216000000, 864, 12, 4, 12}, - { 13000000, 216000000, 864, 13, 4, 12}, - { 16800000, 216000000, 720, 14, 4, 12}, - { 19200000, 216000000, 720, 16, 4, 12}, - { 26000000, 216000000, 864, 26, 4, 12}, - - { 12000000, 594000000, 99, 1, 2, 15}, - { 13000000, 594000000, 594, 13, 1, 12}, - { 16800000, 594000000, 495, 14, 1, 12}, - { 19200000, 594000000, 495, 16, 1, 12}, - { 26000000, 594000000, 594, 26, 1, 12}, - - { 12000000, 1000000000, 1000, 12, 1, 12}, - { 13000000, 1000000000, 1000, 13, 1, 12}, - { 19200000, 1000000000, 625, 12, 1, 12}, - { 26000000, 1000000000, 1000, 26, 1, 12}, - - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_d = { - .name = "pll_d", - .flags = PLL_HAS_CPCON | PLLD, - .ops = &tegra_plld_ops, - .reg = 0xd0, - .parent = &tegra_pll_ref, - .max_rate = 1000000000, - .u.pll = { - .input_min = 2000000, - .input_max = 40000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 500000000, - .vco_max = 1000000000, - .freq_table = tegra_pll_d_freq_table, - .lock_delay = 1000, - }, -}; - -static struct clk tegra_pll_d_out0 = { - .name = "pll_d_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_2 | PLLD, - .parent = &tegra_pll_d, - .max_rate = 500000000, -}; - -static struct clk tegra_pll_d2 = { - .name = "pll_d2", - .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, - .ops = &tegra_plld_ops, - .reg = 0x4b8, - .parent = &tegra_pll_ref, - .max_rate = 1000000000, - .u.pll = { - .input_min = 2000000, - .input_max = 40000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 500000000, - .vco_max = 1000000000, - .freq_table = tegra_pll_d_freq_table, - .lock_delay = 1000, - }, -}; - -static struct clk tegra_pll_d2_out0 = { - .name = "pll_d2_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_2 | PLLD, - .parent = &tegra_pll_d2, - .max_rate = 500000000, -}; - -static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 2, 12}, - { 13000000, 480000000, 960, 13, 2, 12}, - { 16800000, 480000000, 400, 7, 2, 5}, - { 19200000, 480000000, 200, 4, 2, 3}, - { 26000000, 480000000, 960, 26, 2, 12}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_u = { - .name = "pll_u", - .flags = PLL_HAS_CPCON | PLLU, - .ops = &tegra_pll_ops, - .reg = 0xc0, - .parent = &tegra_pll_ref, - .max_rate = 480000000, - .u.pll = { - .input_min = 2000000, - .input_max = 40000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 480000000, - .vco_max = 960000000, - .freq_table = tegra_pll_u_freq_table, - .lock_delay = 1000, - .cpcon_default = 12, - }, -}; - -static struct clk tegra_pll_u_480M = { - .name = "pll_u_480M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 22, - .parent = &tegra_pll_u, - .mul = 1, - .div = 1, - .max_rate = 480000000, -}; - -static struct clk tegra_pll_u_60M = { - .name = "pll_u_60M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 23, - .parent = &tegra_pll_u, - .mul = 1, - .div = 8, - .max_rate = 60000000, -}; - -static struct clk tegra_pll_u_48M = { - .name = "pll_u_48M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 25, - .parent = &tegra_pll_u, - .mul = 1, - .div = 10, - .max_rate = 48000000, -}; - -static struct clk tegra_pll_u_12M = { - .name = "pll_u_12M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 21, - .parent = &tegra_pll_u, - .mul = 1, - .div = 40, - .max_rate = 12000000, -}; - -static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { - /* 1 GHz */ - { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */ - { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ - { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */ - { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */ - { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */ - - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_x = { - .name = "pll_x", - .flags = PLL_ALT_MISC_REG | PLLX, - .ops = &tegra_pllxc_ops, - .reg = 0xe0, - .parent = &tegra_pll_ref, - .max_rate = 1800000000, - .u.pll = { - .input_min = 12000000, - .input_max = 800000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ - .vco_min = 700000000, - .vco_max = 2400000000U, - .freq_table = tegra_pll_x_freq_table, - .lock_delay = 300, - .misc1 = 0x510 - 0xe0, - .round_p_to_pdiv = pllxc_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_x_out0 = { - .name = "pll_x_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_2 | PLLX, - .parent = &tegra_pll_x, - .max_rate = 700000000, -}; - -static struct clk tegra_dfll_cpu = { - .name = "dfll_cpu", - .flags = DFLL, - .ops = &tegra_dfll_ops, - .reg = 0x2f4, - .max_rate = 2000000000, -}; - -static struct clk tegra_pll_re_vco = { - .name = "pll_re_vco", - .flags = PLL_ALT_MISC_REG, - .ops = &tegra_pllre_ops, - .reg = 0x4c4, - .parent = &tegra_pll_ref, - .max_rate = 672000000, - .u.pll = { - .input_min = 12000000, - .input_max = 1000000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ - .vco_min = 300000000, - .vco_max = 672000000, - .lock_delay = 300, - .round_p_to_pdiv = pllre_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_re_out = { - .name = "pll_re_out", - .ops = &tegra_pllre_out_ops, - .parent = &tegra_pll_re_vco, - .reg = 0x4c4, - .max_rate = 672000000, -}; - -static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { - /* PLLE special case: use cpcon field to store cml divider value */ - { 336000000, 100000000, 100, 21, 16, 11}, - { 312000000, 100000000, 200, 26, 24, 13}, - { 12000000, 100000000, 200, 1, 24, 13}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_e = { - .name = "pll_e", - .flags = PLL_ALT_MISC_REG, - .ops = &tegra_plle_ops, - .reg = 0xe8, - .max_rate = 100000000, - .u.pll = { - .input_min = 12000000, - .input_max = 1000000000, - .cf_min = 12000000, - .cf_max = 75000000, - .vco_min = 1600000000, - .vco_max = 2400000000U, - .freq_table = tegra_pll_e_freq_table, - .lock_delay = 300, - .fixed_rate = 100000000, - }, -}; - -static struct clk tegra_pciex_clk = { - .name = "pciex", - .parent = &tegra_pll_e, - .ops = &tegra_pciex_clk_ops, - .max_rate = 100000000, - .u.periph = { - .clk_num = 74, - }, -}; - -/* Audio sync clocks */ -#define SYNC_SOURCE(_id, _dev) \ - { \ - .name = #_id "_sync", \ - .lookup = { \ - .dev_id = #_dev , \ - .con_id = "ext_audio_sync", \ - }, \ - .rate = 24000000, \ - .max_rate = 24000000, \ - .ops = &tegra_sync_source_ops \ - } -static struct clk tegra_sync_source_list[] = { - SYNC_SOURCE(spdif_in, tegra30-spdif), - SYNC_SOURCE(i2s0, tegra30-i2s.0), - SYNC_SOURCE(i2s1, tegra30-i2s.1), - SYNC_SOURCE(i2s2, tegra30-i2s.2), - SYNC_SOURCE(i2s3, tegra30-i2s.3), - SYNC_SOURCE(i2s4, tegra30-i2s.4), - SYNC_SOURCE(vimclk, vimclk), -}; - -static struct clk_mux_sel mux_d_audio_clk[] = { - { .input = &tegra_pll_a_out0, .value = 0}, - { .input = &tegra_pll_p, .value = 0x8000}, - { .input = &tegra_clk_m, .value = 0xc000}, - { .input = &tegra_sync_source_list[0], .value = 0xE000}, - { .input = &tegra_sync_source_list[1], .value = 0xE001}, - { .input = &tegra_sync_source_list[2], .value = 0xE002}, - { .input = &tegra_sync_source_list[3], .value = 0xE003}, - { .input = &tegra_sync_source_list[4], .value = 0xE004}, - { .input = &tegra_sync_source_list[5], .value = 0xE005}, - { .input = &tegra_pll_a_out0, .value = 0xE006}, - { .input = &tegra_sync_source_list[6], .value = 0xE007}, - { 0, 0 } -}; - -static struct clk_mux_sel mux_audio_sync_clk[] = -{ - { .input = &tegra_sync_source_list[0], .value = 0}, - { .input = &tegra_sync_source_list[1], .value = 1}, - { .input = &tegra_sync_source_list[2], .value = 2}, - { .input = &tegra_sync_source_list[3], .value = 3}, - { .input = &tegra_sync_source_list[4], .value = 4}, - { .input = &tegra_sync_source_list[5], .value = 5}, - { .input = &tegra_pll_a_out0, .value = 6}, - { .input = &tegra_sync_source_list[6], .value = 7}, - { 0, 0 } -}; - -#define AUDIO_SYNC_CLK(_id, _dev, _index) \ - { \ - .name = #_id, \ - .lookup = { \ - .dev_id = #_dev, \ - .con_id = "audio_sync", \ - }, \ - .inputs = mux_audio_sync_clk, \ - .reg = 0x4A0 + (_index) * 4, \ - .max_rate = 24000000, \ - .ops = &tegra_audio_sync_clk_ops \ - } -static struct clk tegra_clk_audio_list[] = { - AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0), - AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1), - AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2), - AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3), - AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4), - AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */ -}; - -#define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \ - { \ - .name = #_id "_2x", \ - .lookup = { \ - .dev_id = #_dev, \ - .con_id = "audio_sync_2x" \ - }, \ - .flags = PERIPH_NO_RESET, \ - .max_rate = 48000000, \ - .ops = &tegra_clk_double_ops, \ - .reg = 0x49C, \ - .reg_shift = 24 + (_index), \ - .parent = &tegra_clk_audio_list[(_index)], \ - .u.periph = { \ - .clk_num = 113 + (_index), \ - }, \ - } -static struct clk tegra_clk_audio_2x_list[] = { - AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0), - AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1), - AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2), - AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3), - AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4), - AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */ -}; - -#define MUX_I2S_SPDIF(_id, _index) \ -static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ - {.input = &tegra_pll_a_out0, .value = 0}, \ - {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ - {.input = &tegra_pll_p, .value = 2}, \ - {.input = &tegra_clk_m, .value = 3}, \ - { 0, 0}, \ -} -MUX_I2S_SPDIF(audio0, 0); -MUX_I2S_SPDIF(audio1, 1); -MUX_I2S_SPDIF(audio2, 2); -MUX_I2S_SPDIF(audio3, 3); -MUX_I2S_SPDIF(audio4, 4); -MUX_I2S_SPDIF(audio, 5); /* SPDIF */ - -/* External clock outputs (through PMC) */ -#define MUX_EXTERN_OUT(_id) \ -static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \ - {.input = &tegra_clk_m, .value = 0}, \ - {.input = &tegra_clk_m_div2, .value = 1}, \ - {.input = &tegra_clk_m_div4, .value = 2}, \ - {.input = NULL, .value = 3}, /* placeholder */ \ - { 0, 0}, \ -} -MUX_EXTERN_OUT(1); -MUX_EXTERN_OUT(2); -MUX_EXTERN_OUT(3); - -static struct clk_mux_sel *mux_extern_out_list[] = { - mux_clkm_clkm2_clkm4_extern1, - mux_clkm_clkm2_clkm4_extern2, - mux_clkm_clkm2_clkm4_extern3, -}; - -#define CLK_OUT_CLK(_id, _max_rate) \ - { \ - .name = "clk_out_" #_id, \ - .lookup = { \ - .dev_id = "clk_out_" #_id, \ - .con_id = "extern" #_id, \ - }, \ - .ops = &tegra_clk_out_ops, \ - .reg = 0x1a8, \ - .inputs = mux_clkm_clkm2_clkm4_extern##_id, \ - .flags = MUX_CLK_OUT, \ - .max_rate = _max_rate, \ - .u.periph = { \ - .clk_num = (_id - 1) * 8 + 2, \ - }, \ - } -static struct clk tegra_clk_out_list[] = { - CLK_OUT_CLK(1, 12288000), - CLK_OUT_CLK(2, 40800000), - CLK_OUT_CLK(3, 12288000), -}; - -/* called after peripheral external clocks are initialized */ -static void init_clk_out_mux(void) -{ - int i; - struct clk *c; - - /* output clock con_id is the name of peripheral - external clock connected to input 3 of the output mux */ - for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) { - c = tegra_get_clock_by_name( - tegra_clk_out_list[i].lookup.con_id); - if (!c) - pr_err("%s: could not find clk %s\n", __func__, - tegra_clk_out_list[i].lookup.con_id); - mux_extern_out_list[i][3].input = c; - } -} - -/* Peripheral muxes */ -static struct clk_mux_sel mux_cclk_g[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_clk_32k, .value = 2}, - { .input = &tegra_pll_m, .value = 3}, - { .input = &tegra_pll_p, .value = 4}, - { .input = &tegra_pll_p_out4, .value = 5}, - /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */ - /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */ - { .input = &tegra_pll_x, .value = 8}, - { .input = &tegra_dfll_cpu, .value = 15}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_cclk_lp[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_clk_32k, .value = 2}, - { .input = &tegra_pll_m, .value = 3}, - { .input = &tegra_pll_p, .value = 4}, - { .input = &tegra_pll_p_out4, .value = 5}, - /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */ - /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */ - { .input = &tegra_pll_x_out0, .value = 8}, - { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_sclk[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_c_out1, .value = 1}, - { .input = &tegra_pll_p_out4, .value = 2}, - { .input = &tegra_pll_p, .value = 3}, - { .input = &tegra_pll_p_out2, .value = 4}, - /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra11x */ - { .input = &tegra_clk_32k, .value = 6}, - { .input = &tegra_pll_m_out1, .value = 7}, - { 0, 0}, -}; - -static struct clk tegra_clk_cclk_g = { - .name = "cclk_g", - .flags = DIV_U71 | DIV_U71_INT | MUX, - .inputs = mux_cclk_g, - .reg = 0x368, - .ops = &tegra_super_ops, - .max_rate = 2000000000, -}; - -static struct clk tegra_clk_cclk_lp = { - .name = "cclk_lp", - .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX, - .inputs = mux_cclk_lp, - .reg = 0x370, - .ops = &tegra_super_ops, - .max_rate = 816000000, -}; - -static struct clk tegra_clk_sclk = { - .name = "sclk", - .inputs = mux_sclk, - .reg = 0x28, - .ops = &tegra_super_ops, - .max_rate = 384000000, - .min_rate = 12000000, -}; - -static struct clk tegra_clk_virtual_cpu_g = { - .name = "cpu_g", - .parent = &tegra_clk_cclk_g, - .ops = &tegra_cpu_ops, - .max_rate = 2000000000, - .u.cpu = { - .main = &tegra_pll_x, - .backup = &tegra_pll_p_out4, - .dynamic = &tegra_dfll_cpu, - .mode = MODE_G, - }, -}; - -static struct clk tegra_clk_virtual_cpu_lp = { - .name = "cpu_lp", - .parent = &tegra_clk_cclk_lp, - .ops = &tegra_cpu_ops, - .max_rate = 816000000, - .u.cpu = { - .main = &tegra_pll_x, - .backup = &tegra_pll_p_out4, - .mode = MODE_LP, - }, -}; - -static struct clk_mux_sel mux_cpu_cmplx[] = { - { .input = &tegra_clk_virtual_cpu_g, .value = 0}, - { .input = &tegra_clk_virtual_cpu_lp, .value = 1}, - { 0, 0}, -}; - -static struct clk tegra_clk_cpu_cmplx = { - .name = "cpu", - .inputs = mux_cpu_cmplx, - .ops = &tegra_cpu_cmplx_ops, - .max_rate = 2000000000, -}; - -static struct clk tegra_clk_cop = { - .name = "cop", - .parent = &tegra_clk_sclk, - .ops = &tegra_cop_ops, - .max_rate = 384000000, -}; - -static struct clk tegra_clk_hclk = { - .name = "hclk", - .flags = DIV_BUS, - .parent = &tegra_clk_sclk, - .reg = 0x30, - .reg_shift = 4, - .ops = &tegra_bus_ops, - .max_rate = 384000000, - .min_rate = 12000000, -}; - -static struct clk tegra_clk_pclk = { - .name = "pclk", - .flags = DIV_BUS, - .parent = &tegra_clk_hclk, - .reg = 0x30, - .reg_shift = 0, - .ops = &tegra_bus_ops, - .max_rate = 192000000, - .min_rate = 12000000, -}; - -static struct raw_notifier_head sbus_rate_change_nh; - -static struct clk tegra_clk_sbus_cmplx = { - .name = "sbus", - .parent = &tegra_clk_sclk, - .ops = &tegra_sbus_cmplx_ops, - .u.system = { - .pclk = &tegra_clk_pclk, - .hclk = &tegra_clk_hclk, - .sclk_low = &tegra_pll_p_out2, -#ifdef CONFIG_TEGRA_PLLM_SCALED - .sclk_high = &tegra_pll_c_out1, -#else - .sclk_high = &tegra_pll_m_out1, -#endif - }, - .rate_change_nh = &sbus_rate_change_nh, -}; - -static struct clk tegra_clk_blink = { - .name = "blink", - .parent = &tegra_clk_32k, - .reg = 0x40, - .ops = &tegra_blink_clk_ops, - .max_rate = 32768, -}; - - -/* Multimedia modules muxes */ -static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = { - { .input = &tegra_pll_m, .value = 0}, - { .input = &tegra_pll_c2, .value = 1}, - { .input = &tegra_pll_c, .value = 2}, - { .input = &tegra_pll_c3, .value = 3}, - { .input = &tegra_pll_p, .value = 4}, - { .input = &tegra_pll_a_out0, .value = 6}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { - { .input = &tegra_pll_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_pll_a_out0, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = { - { .input = &tegra_pll_a_out0, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -/* EMC muxes */ -/* FIXME: add EMC latency mux */ -static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { - { .input = &tegra_pll_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */ - { 0, 0}, -}; - - -/* Display subsystem muxes */ -static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_m, .value = 1}, - {.input = &tegra_pll_d_out0, .value = 2}, - {.input = &tegra_pll_a_out0, .value = 3}, - {.input = &tegra_pll_c, .value = 4}, - {.input = &tegra_pll_d2_out0, .value = 5}, - {.input = &tegra_clk_m, .value = 6}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plld_out0_plld2_out0[] = { - { .input = &tegra_pll_d_out0, .value = 0}, - { .input = &tegra_pll_d2_out0, .value = 1}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_clkm[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -/* Peripheral muxes */ -static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_pll_c2, .value = 1}, - { .input = &tegra_pll_c, .value = 2}, - { .input = &tegra_pll_c3, .value = 3}, - { .input = &tegra_pll_m, .value = 4}, - { .input = &tegra_clk_m, .value = 6}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_m, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_pllm[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_pll_m, .value = 2}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_clkm[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_clk_32k, .value = 2}, - {.input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_clk_m, .value = 2}, - {.input = &tegra_clk_32k, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = { - { .input = &tegra_pll_a_out0, .value = 0}, - { .input = &tegra_clk_32k, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { .input = &tegra_pll_e, .value = 4}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_p, .value = 1}, - { .input = &tegra_pll_c, .value = 3}, - { .input = &tegra_pll_re_vco, .value = 5}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_u_48M, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_pll_u_480M, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_re_vco, .value = 1}, - { .input = &tegra_clk_32k, .value = 2}, - { .input = &tegra_pll_u_480M, .value = 3}, - { .input = &tegra_pll_c, .value = 4}, - { .input = &tegra_pll_ref, .value = 7}, - { 0, 0}, -}; - -/* Single clock source ("fake") muxes */ -static struct clk_mux_sel mux_clk_m[] = { - { .input = &tegra_clk_m, .value = 0}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_out3[] = { - { .input = &tegra_pll_p_out3, .value = 0}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_clk_32k[] = { - { .input = &tegra_clk_32k, .value = 0}, - { 0, 0}, -}; - -static struct raw_notifier_head emc_rate_change_nh; - -static struct clk tegra_clk_emc = { - .name = "emc", - .ops = &tegra_emc_clk_ops, - .reg = 0x19c, - .max_rate = 1066000000, - .min_rate = 12750000, - .inputs = mux_pllm_pllc_pllp_clkm, - .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB, - .u.periph = { - .clk_num = 57, - }, - .rate_change_nh = &emc_rate_change_nh, -}; - -static struct raw_notifier_head host1x_rate_change_nh; - -static struct clk tegra_clk_host1x = { - .name = "host1x", - .lookup = { - .dev_id = "host1x", - }, - .ops = &tegra_1xbus_clk_ops, - .reg = 0x180, - .inputs = mux_pllm_pllc_pllp_plla, - .flags = MUX | DIV_U71 | DIV_U71_INT, - .max_rate = 384000000, - .min_rate = 12000000, - .u.periph = { - .clk_num = 28, - .pll_low = &tegra_pll_p, -#ifdef CONFIG_TEGRA_PLLM_SCALED - .pll_high = &tegra_pll_c, -#else - .pll_high = &tegra_pll_m, -#endif - }, - .rate_change_nh = &host1x_rate_change_nh, -}; - -#ifdef CONFIG_TEGRA_DUAL_CBUS - -static struct raw_notifier_head c2bus_rate_change_nh; -static struct raw_notifier_head c3bus_rate_change_nh; - -static struct clk tegra_clk_c2bus = { - .name = "c2bus", - .parent = &tegra_pll_c2, - .ops = &tegra_clk_cbus_ops, - .max_rate = 864000000, - .mul = 1, - .div = 1, - .flags = PERIPH_ON_CBUS, - .shared_bus_backup = { - .input = &tegra_pll_p, - }, - .rate_change_nh = &c2bus_rate_change_nh, -}; -static struct clk tegra_clk_c3bus = { - .name = "c3bus", - .parent = &tegra_pll_c3, - .ops = &tegra_clk_cbus_ops, - .max_rate = 700000000, - .mul = 1, - .div = 1, - .flags = PERIPH_ON_CBUS, - .shared_bus_backup = { - .input = &tegra_pll_p, - }, - .rate_change_nh = &c3bus_rate_change_nh, -}; - -#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS -static DEFINE_MUTEX(cbus_mutex); -#define CROSS_CBUS_MUTEX (&cbus_mutex) -#else -#define CROSS_CBUS_MUTEX NULL -#endif - - -static struct clk_mux_sel mux_clk_cbus[] = { - { .input = &tegra_clk_c2bus, .value = 0}, - { .input = &tegra_clk_c3bus, .value = 1}, - { 0, 0}, -}; - -#define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .inputs = mux_clk_cbus, \ - .flags = MUX, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - }, \ - .cross_clk_mutex = CROSS_CBUS_MUTEX, \ - } - -#else - -static struct raw_notifier_head cbus_rate_change_nh; - -static struct clk tegra_clk_cbus = { - .name = "cbus", - .parent = &tegra_pll_c, - .ops = &tegra_clk_cbus_ops, - .max_rate = 700000000, - .mul = 1, - .div = 2, - .flags = PERIPH_ON_CBUS, - .shared_bus_backup = { - .input = &tegra_pll_p, - }, - .rate_change_nh = &cbus_rate_change_nh, -}; -#endif - -static void tegra11_camera_mclk_init(struct clk *c) -{ - c->state = OFF; - c->set = true; - c->parent = tegra_get_clock_by_name("vi_sensor"); - c->max_rate = c->parent->max_rate; -} - -static int tegra11_camera_mclk_set_rate(struct clk *c, unsigned long rate) -{ - return clk_set_rate(c->parent, rate); -} - -static struct clk_ops tegra_camera_mclk_ops = { - .init = tegra11_camera_mclk_init, - .enable = tegra11_periph_clk_enable, - .disable = tegra11_periph_clk_disable, - .set_rate = tegra11_camera_mclk_set_rate, -}; - -static struct clk tegra_camera_mclk = { - .name = "mclk", - .ops = &tegra_camera_mclk_ops, - .u.periph = { - .clk_num = 92, /* csus */ - }, - .flags = PERIPH_NO_RESET, -}; - -#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_periph_clk_ops, \ - .reg = _reg, \ - .inputs = _inputs, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - }, \ - } - -#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \ - _flags, _ops) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = _ops, \ - .reg = _reg, \ - .inputs = _inputs, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - }, \ - } - -#define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_periph_clk_ops, \ - .reg = _reg, \ - .inputs = _inputs, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - .src_mask = 0xE01F << 16, \ - .src_shift = 16, \ - }, \ - } - -#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - }, \ - } -#define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - .usage_flag = _flag, \ - }, \ - } - -struct clk tegra_list_clks[] = { - PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0), - PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), - PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), - PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), - PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 24730000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24730000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops), - PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 250000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT), - PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 12000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2c1", "tegra11-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c2", "tegra11-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 64000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("uarta", "serial-tegra.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartb", "serial-tegra.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartc", "serial-tegra.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartd", "serial-tegra.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), - PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE), - PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), - PERIPH_CLK("vi_sensor", NULL, "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT), - PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops), - PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT), - PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops), - PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71), - PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), - PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), - PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0), - PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), - PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), - PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops), - PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops), - PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("csi", "vi", "csi", 52, 0, 102000000, mux_pllp_out3, 0), - PERIPH_CLK("isp", "vi", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ - PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), - PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - - PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71), - PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), - PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), - PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), - PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), - PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT), - PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), - PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), - PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB), - - PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - - SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sdmmc3.sclk", "sdhci-tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE), - - SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, - NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)), - SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, - NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)), - SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc", - &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)), - SHARED_EMC_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_2D)), - SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)), - SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("sdmmc3.emc", "sdhci-tegra.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)), - SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0), - SHARED_EMC_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("floor.profile.emc", "profile.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0), - -#ifdef CONFIG_TEGRA_DUAL_CBUS - DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0), - DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0), - DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0), - SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0), - SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE), - SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("battery.c2bus", "battery_edp", "gpu", &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0), - - DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0), - DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0), - DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0), - DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0), - SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0), - SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE), -#else - SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0), - SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0), - SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0), - SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0), - SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0), - SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0), - SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0), - SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), - SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE), - SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("battery.cbus", "battery_edp", "gpu", &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), -#endif - SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0), - SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0), - SHARED_CLK("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0), - SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE), - SHARED_CLK("floor.profile.host1x", "profile.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0), - - SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), -}; - - -/* XUSB clocks */ -#define XUSB_ID "tegra-xhci" - -static struct clk tegra_clk_xusb_gate = { - .name = "xusb_gate", - .flags = ENABLE_ON_INIT | PERIPH_NO_RESET, - .ops = &tegra_xusb_gate_clk_ops, - .rate = 12000000, - .max_rate = 48000000, - .u.periph = { - .clk_num = 143, - }, -}; - -static struct clk tegra_xusb_source_clks[] = { - PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB), - PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET), - PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET), - PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 122400000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET), - PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB), - SHARED_EMC_CLK("xusb.emc", XUSB_ID, "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, 0), -}; - -static struct clk tegra_xusb_ss_div2 = { - .name = "xusb_ss_div2", - .ops = &tegra_clk_m_div_ops, - .parent = &tegra_xusb_source_clks[3], - .mul = 1, - .div = 2, - .state = OFF, - .max_rate = 61200000, -}; - -static struct clk_mux_sel mux_ss_div2_pllu_60M[] = { - { .input = &tegra_xusb_ss_div2, .value = 0}, - { .input = &tegra_pll_u_60M, .value = 1}, - { 0, 0}, -}; - -static struct clk tegra_xusb_hs_src = { - .name = "xusb_hs_src", - .lookup = { - .dev_id = XUSB_ID, - .con_id = "hs_src", - }, - .ops = &tegra_periph_clk_ops, - .reg = 0x610, - .inputs = mux_ss_div2_pllu_60M, - .flags = PLLU | PERIPH_NO_ENB, - .max_rate = 61200000, - .u.periph = { - .src_mask = 0x1 << 25, - .src_shift = 25, - }, -}; - -static struct clk_mux_sel mux_xusb_host[] = { - { .input = &tegra_xusb_source_clks[0], .value = 0}, - { .input = &tegra_xusb_source_clks[1], .value = 1}, - { .input = &tegra_xusb_source_clks[2], .value = 2}, - { .input = &tegra_xusb_hs_src, .value = 5}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_xusb_ss[] = { - { .input = &tegra_xusb_source_clks[3], .value = 3}, - { .input = &tegra_xusb_source_clks[0], .value = 0}, - { .input = &tegra_xusb_source_clks[1], .value = 1}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_xusb_dev[] = { - { .input = &tegra_xusb_source_clks[4], .value = 4}, - { .input = &tegra_xusb_source_clks[2], .value = 2}, - { .input = &tegra_xusb_source_clks[3], .value = 3}, - { 0, 0}, -}; - -static struct clk tegra_xusb_coupled_clks[] = { - PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops), - PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops), - PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops), -}; - -#define CLK_DUPLICATE(_name, _dev, _con) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - } - -/* Some clocks may be used by different drivers depending on the board - * configuration. List those here to register them twice in the clock lookup - * table under two names. - */ -struct clk_duplicate tegra_clk_duplicates[] = { - CLK_DUPLICATE("uarta", "serial8250.0", NULL), - CLK_DUPLICATE("uartb", "serial8250.1", NULL), - CLK_DUPLICATE("uartc", "serial8250.2", NULL), - CLK_DUPLICATE("uartd", "serial8250.3", NULL), - CLK_DUPLICATE("uarte", "serial8250.4", NULL), - CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"), - CLK_DUPLICATE("usbd", "utmip-pad", NULL), - CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), - CLK_DUPLICATE("usbd", "tegra-otg", NULL), - CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL), - CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"), - CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL), - CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"), - CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), - CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), - CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), - CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), - CLK_DUPLICATE("dsiblp", "tegradc.0", "dsiblp"), - CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"), - CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"), - CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"), - CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"), - CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"), - CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"), - CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"), - CLK_DUPLICATE("cop", "tegra-avp", "cop"), - CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), - CLK_DUPLICATE("cop", "nvavp", "cop"), - CLK_DUPLICATE("bsev", "nvavp", "bsev"), - CLK_DUPLICATE("vde", "tegra-aes", "vde"), - CLK_DUPLICATE("bsea", "tegra-aes", "bsea"), - CLK_DUPLICATE("bsea", "nvavp", "bsea"), - CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"), - CLK_DUPLICATE("clk_m", NULL, "apb_pclk"), - CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL), - CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL), - CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL), - CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL), - CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL), - CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL), - CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL), - CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL), - CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL), - CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL), - CLK_DUPLICATE("sbc4", "tegra11-spi-slave.3", NULL), - CLK_DUPLICATE("sbc5", "tegra11-spi-slave.4", NULL), - CLK_DUPLICATE("sbc6", "tegra11-spi-slave.5", NULL), - CLK_DUPLICATE("vcp", "nvavp", "vcp"), - CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"), - CLK_DUPLICATE("avp.emc", "nvavp", "emc"), - CLK_DUPLICATE("vde.cbus", "nvavp", "vde"), - CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"), - CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"), - CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"), - CLK_DUPLICATE("i2s0", NULL, "i2s0"), - CLK_DUPLICATE("i2s1", NULL, "i2s1"), - CLK_DUPLICATE("i2s2", NULL, "i2s2"), - CLK_DUPLICATE("i2s3", NULL, "i2s3"), - CLK_DUPLICATE("i2s4", NULL, "i2s4"), - CLK_DUPLICATE("dam0", NULL, "dam0"), - CLK_DUPLICATE("dam1", NULL, "dam1"), - CLK_DUPLICATE("dam2", NULL, "dam2"), - CLK_DUPLICATE("spdif_in", NULL, "spdif_in"), - CLK_DUPLICATE("mclk", NULL, "default_mclk"), -}; - -struct clk *tegra_ptr_clks[] = { - &tegra_clk_32k, - &tegra_clk_m, - &tegra_clk_m_div2, - &tegra_clk_m_div4, - &tegra_pll_ref, - &tegra_pll_m, - &tegra_pll_m_out1, - &tegra_pll_c, - &tegra_pll_c_out1, - &tegra_pll_c2, - &tegra_pll_c3, - &tegra_pll_p, - &tegra_pll_p_out1, - &tegra_pll_p_out2, - &tegra_pll_p_out3, - &tegra_pll_p_out4, - &tegra_pll_a, - &tegra_pll_a_out0, - &tegra_pll_d, - &tegra_pll_d_out0, - &tegra_pll_d2, - &tegra_pll_d2_out0, - &tegra_clk_xusb_gate, - &tegra_pll_u, - &tegra_pll_u_480M, - &tegra_pll_u_60M, - &tegra_pll_u_48M, - &tegra_pll_u_12M, - &tegra_pll_x, - &tegra_pll_x_out0, - &tegra_dfll_cpu, - &tegra_pll_re_vco, - &tegra_pll_re_out, - &tegra_pll_e, - &tegra_pciex_clk, - &tegra_clk_cclk_g, - &tegra_clk_cclk_lp, - &tegra_clk_sclk, - &tegra_clk_hclk, - &tegra_clk_pclk, - &tegra_clk_virtual_cpu_g, - &tegra_clk_virtual_cpu_lp, - &tegra_clk_cpu_cmplx, - &tegra_clk_blink, - &tegra_clk_cop, - &tegra_clk_sbus_cmplx, - &tegra_clk_emc, - &tegra_clk_host1x, -#ifdef CONFIG_TEGRA_DUAL_CBUS - &tegra_clk_c2bus, - &tegra_clk_c3bus, -#else - &tegra_clk_cbus, -#endif -}; - -/* Return true from this function if the target rate can be locked without - switching pll clients to back-up source */ -static bool tegra11_is_dyn_ramp( - struct clk *c, unsigned long rate, bool from_vco_min) -{ -#if PLLCX_USE_DYN_RAMP - /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */ - if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) { - struct clk_pll_freq_table cfg, old_cfg; - unsigned long input_rate = clk_get_rate(c->parent); - - u32 val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLCX, old_cfg, val); - old_cfg.p = pllcx_p[old_cfg.p]; - - if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) { - if ((cfg.n == old_cfg.n) || - PLLCX_IS_DYN(cfg.p, old_cfg.p)) - return true; - } - } -#endif - -#if PLLXC_USE_DYN_RAMP - /* PPLX, PLLC support dynamic ramp when changing NDIV only */ - if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) { - struct clk_pll_freq_table cfg, old_cfg; - unsigned long input_rate = clk_get_rate(c->parent); - - if (from_vco_min) { - old_cfg.m = PLL_FIXED_MDIV(c, input_rate); - old_cfg.p = 1; - } else { - u32 val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLXC, old_cfg, val); - old_cfg.p = pllxc_p[old_cfg.p]; - } - - if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) { - if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p)) - return true; - } - } -#endif - return false; -} - -/* - * Backup pll is used as transitional CPU clock source while main pll is - * relocking; in addition all CPU rates below backup level are sourced from - * backup pll only. Target backup levels for each CPU mode are selected high - * enough to avoid voltage droop when CPU clock is switched between backup and - * main plls. Actual backup rates will be rounded to match backup source fixed - * frequency. Backup rates are also used as stay-on-backup thresholds, and must - * be kept the same in G and LP mode (will need to add a separate stay-on-backup - * parameter to allow different backup rates if necessary). - * - * Sbus threshold must be exact factor of pll_p rate. - */ -#define CPU_G_BACKUP_RATE_TARGET 200000000 -#define CPU_LP_BACKUP_RATE_TARGET 200000000 - -static void tegra11_pllp_init_dependencies(unsigned long pllp_rate) -{ - u32 div; - unsigned long backup_rate; - - switch (pllp_rate) { - case 216000000: - tegra_pll_p_out1.u.pll_div.default_rate = 28800000; - tegra_pll_p_out3.u.pll_div.default_rate = 72000000; - tegra_clk_sbus_cmplx.u.system.threshold = 108000000; - tegra_clk_host1x.u.periph.threshold = 108000000; - break; - case 408000000: - tegra_pll_p_out1.u.pll_div.default_rate = 9600000; - tegra_pll_p_out3.u.pll_div.default_rate = 102000000; - tegra_clk_sbus_cmplx.u.system.threshold = 204000000; - tegra_clk_host1x.u.periph.threshold = 204000000; - break; - case 204000000: - tegra_pll_p_out1.u.pll_div.default_rate = 4800000; - tegra_pll_p_out3.u.pll_div.default_rate = 102000000; - tegra_clk_sbus_cmplx.u.system.threshold = 204000000; - tegra_clk_host1x.u.periph.threshold = 204000000; - break; - default: - pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate); - BUG(); - } - pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate); - - div = pllp_rate / CPU_G_BACKUP_RATE_TARGET; - backup_rate = pllp_rate / div; - tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate; - - div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET; - backup_rate = pllp_rate / div; - tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate; -} - -static void tegra11_init_one_clock(struct clk *c) -{ - clk_init(c); - INIT_LIST_HEAD(&c->shared_bus_list); - if (!c->lookup.dev_id && !c->lookup.con_id) - c->lookup.con_id = c->name; - c->lookup.clk = c; - clkdev_add(&c->lookup); -} - -/* Direct access to CPU clock sources fot CPU idle driver */ -int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate) -{ - int ret = 0; - struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic; - unsigned long old_rate, new_rate, flags; - - if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) - return -EPERM; - - /* Clipping min to oscillator rate is pretty much arbitrary */ - new_rate = max(*rate, tegra_clk_m.rate); - - clk_lock_save(dfll, &flags); - - old_rate = clk_get_rate_locked(dfll); - *rate = old_rate; - if (new_rate != old_rate) - ret = clk_set_rate_locked(dfll, new_rate); - - clk_unlock_restore(dfll, &flags); - return ret; -} - -int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate) -{ - int ret = 0; - struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup; - unsigned long old_rate, flags; - unsigned long new_rate = min( - *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate); - - clk_lock_save(backup, &flags); - - old_rate = clk_get_rate_locked(backup); - *rate = old_rate; - if (new_rate != old_rate) - ret = clk_set_rate_locked(backup, new_rate); - - clk_unlock_restore(backup, &flags); - return ret; -} - -void tegra_edp_throttle_cpu_now(u8 factor) -{ - /* empty definition for tegra11 */ - return; -} - -bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p) -{ - /* - * Most of the Tegra11 multimedia and peripheral muxes include pll_c2 - * and pll_c3 as possible inputs. However, per clock policy these plls - * are allowed to be used only by handful devices aggregated on cbus. - * For all others, instead of enforcing policy at run-time in this - * function, we simply stripped out pll_c2 and pll_c3 options from the - * respective muxes statically. - */ - - /* - * In configuration with dual cbus pll_c can be used as a scaled clock - * source for EMC only when pll_m is fixed, or as a general fixed rate - * clock source for EMC and other peripherals if pll_m is scaled. In - * configuration with single cbus pll_c can be used as a scaled cbus - * clock source only. No direct use for pll_c by super clocks. - */ - if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) { - if (c->ops == &tegra_super_ops) - return false; -#ifdef CONFIG_TEGRA_DUAL_CBUS -#ifndef CONFIG_TEGRA_PLLM_SCALED - return c->flags & PERIPH_EMC_ENB; -#endif -#else - return c->flags & PERIPH_ON_CBUS; -#endif - } - - /* - * In any configuration pll_m must not be used as a clock source for - * cbus modules. If pll_m is scaled it can be used as EMC source only. - * Otherwise fixed rate pll_m can be used as clock source for EMC and - * other peripherals. No direct use for pll_m by super clocks. - */ - if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) { - if (c->ops == &tegra_super_ops) - return false; - - if (c->flags & PERIPH_ON_CBUS) - return false; -#ifdef CONFIG_TEGRA_PLLM_SCALED - return c->flags & PERIPH_EMC_ENB; -#endif - } - return true; -} - -/* Internal LA may request some clocks to be enabled on init via TRANSACTION - SCRATCH register settings */ -void __init tegra11x_clk_init_la(void) -{ - struct clk *c; - u32 reg = readl(misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0); - - if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE)) - return; - - c = tegra_get_clock_by_name("la"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - - if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) { - c = tegra_get_clock_by_name("dds"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - } - if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) { - c = tegra_get_clock_by_name("dp2"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - - c = tegra_get_clock_by_name("hdmi"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - } -} - -#ifdef CONFIG_CPU_FREQ - -/* - * Frequency table index must be sequential starting at 0 and frequencies - * must be ascending. - */ -#define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */ -#define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1) - -static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE]; -static struct tegra_cpufreq_table_data freq_table_data; - -struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) -{ - int i, j; - bool g_vmin_done = false; - unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq; - struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g"); - struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp"); - - /* Initialize once */ - if (freq_table_data.freq_table) - return &freq_table_data; - - /* Clean table */ - for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) { - freq_table[i].index = i; - freq_table[i].frequency = CPUFREQ_TABLE_END; - } - - lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000; - if (!lp_backup_freq) { - WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n", - __func__); - return NULL; - } - if (!cpu_clk_lp->dvfs) { - WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n", - __func__); - return NULL; - } - if (!cpu_clk_g->dvfs) { - WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n", - __func__); - return NULL; - } - g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000; - if (g_vmin_freq <= lp_backup_freq) { - WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate" - " exceeds G CPU rate at Vmin\n", __func__); - return NULL; - } - - /* Start with backup frequencies */ - i = 0; - freq = lp_backup_freq; - freq_table[i++].frequency = freq/4; - freq_table[i++].frequency = freq/2; - freq_table[i++].frequency = freq; - - /* Throttle low index at backup level*/ - freq_table_data.throttle_lowest_index = i - 1; - - /* - * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU - * dvfs rate at minimum voltage is not missed (if it happens to be below - * LP maximum rate) - */ - max_freq = cpu_clk_lp->max_rate / 1000; - for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) { - freq = cpu_clk_lp->dvfs->freqs[j] / 1000; - if (freq <= lp_backup_freq) - continue; - - if (!g_vmin_done && (freq >= g_vmin_freq)) { - g_vmin_done = true; - if (freq > g_vmin_freq) - freq_table[i++].frequency = g_vmin_freq; - } - freq_table[i++].frequency = freq; - - if (freq == max_freq) - break; - } - - /* Set G CPU min rate at least one table step below LP maximum */ - cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000; - - /* Suspend index at max LP CPU */ - freq_table_data.suspend_index = i - 1; - - /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs - ladder rate at minimum voltage */ - if (freq < g_vmin_freq) { - int n = (g_vmin_freq - freq) / CPU_FREQ_STEP; - for (j = 0; j <= n; j++) { - freq = g_vmin_freq - CPU_FREQ_STEP * (n - j); - freq_table[i++].frequency = freq; - } - } - - /* Now, step along the rest of G CPU dvfs ladder */ - g_start_freq = freq; - max_freq = cpu_clk_g->max_rate / 1000; - for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) { - freq = cpu_clk_g->dvfs->freqs[j] / 1000; - if (freq > g_start_freq) - freq_table[i++].frequency = freq; - if (freq == max_freq) - break; - } - - /* Throttle high index one step below maximum */ - BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE); - freq_table_data.throttle_highest_index = i - 2; - freq_table_data.freq_table = freq_table; - return &freq_table_data; -} - -unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate) -{ - static unsigned long emc_max_rate; - - if (emc_max_rate == 0) - emc_max_rate = clk_round_rate( - tegra_get_clock_by_name("emc"), ULONG_MAX); - - /* Vote on memory bus frequency based on cpu frequency; - cpu rate is in kHz, emc rate is in Hz */ - if (cpu_rate >= 1500000) - return emc_max_rate; /* cpu >= 1.5GHz, emc max */ - else if (cpu_rate >= 975000) - return 400000000; /* cpu >= 975 MHz, emc 400 MHz */ - else if (cpu_rate >= 725000) - return 200000000; /* cpu >= 725 MHz, emc 200 MHz */ - else if (cpu_rate >= 500000) - return 100000000; /* cpu >= 500 MHz, emc 100 MHz */ - else if (cpu_rate >= 275000) - return 50000000; /* cpu >= 275 MHz, emc 50 MHz */ - else - return 0; /* emc min */ -} - -int tegra_update_mselect_rate(unsigned long cpu_rate) -{ - static struct clk *mselect = NULL; - - unsigned long mselect_rate; - - if (!mselect) { - mselect = tegra_get_clock_by_name("mselect"); - if (!mselect) - return -ENODEV; - } - - /* Vote on mselect frequency based on cpu frequency: - keep mselect at half of cpu rate up to 102 MHz; - cpu rate is in kHz, mselect rate is in Hz */ - mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000; - mselect_rate = min(mselect_rate, 102000000UL); - - if (mselect_rate != clk_get_rate(mselect)) - return clk_set_rate(mselect, mselect_rate); - - return 0; -} -#endif - -#ifdef CONFIG_PM_SLEEP -static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + - PERIPH_CLK_SOURCE_NUM + 25]; - -static int tegra11_clk_suspend(void) -{ - unsigned long off; - u32 *ctx = clk_rst_suspend; - - *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; - *ctx++ = clk_readl(CPU_SOFTRST_CTRL); - *ctx++ = clk_readl(CPU_SOFTRST_CTRL1); - *ctx++ = clk_readl(CPU_SOFTRST_CTRL2); - - *ctx++ = clk_readl(tegra_pll_p_out1.reg); - *ctx++ = clk_readl(tegra_pll_p_out3.reg); - - *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); - *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); - *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); - *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); - *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE); - *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); - - *ctx++ = clk_readl(tegra_pll_m_out1.reg); - *ctx++ = clk_readl(tegra_pll_a_out0.reg); - *ctx++ = clk_readl(tegra_pll_c_out1.reg); - - *ctx++ = clk_readl(tegra_clk_cclk_lp.reg); - *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); - - *ctx++ = clk_readl(tegra_clk_sclk.reg); - *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); - *ctx++ = clk_readl(tegra_clk_pclk.reg); - - for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; - off += 4) { - if (off == PERIPH_CLK_SOURCE_EMC) - continue; - *ctx++ = clk_readl(off); - } - for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; - off+=4) { - *ctx++ = clk_readl(off); - } - for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { - *ctx++ = clk_readl(off); - } - for (off = PERIPH_CLK_SOURCE_XUSB_HOST; - off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4) - *ctx++ = clk_readl(off); - - *ctx++ = clk_readl(RST_DEVICES_L); - *ctx++ = clk_readl(RST_DEVICES_H); - *ctx++ = clk_readl(RST_DEVICES_U); - *ctx++ = clk_readl(RST_DEVICES_V); - *ctx++ = clk_readl(RST_DEVICES_W); - *ctx++ = clk_readl(RST_DEVICES_X); - - *ctx++ = clk_readl(CLK_OUT_ENB_L); - *ctx++ = clk_readl(CLK_OUT_ENB_H); - *ctx++ = clk_readl(CLK_OUT_ENB_U); - *ctx++ = clk_readl(CLK_OUT_ENB_V); - *ctx++ = clk_readl(CLK_OUT_ENB_W); - *ctx++ = clk_readl(CLK_OUT_ENB_X); - - *ctx++ = clk_readl(tegra_clk_cclk_g.reg); - *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); - - *ctx++ = clk_readl(SPARE_REG); - *ctx++ = clk_readl(MISC_CLK_ENB); - *ctx++ = clk_readl(CLK_MASK_ARM); - - return 0; -} - -static void tegra11_clk_resume(void) -{ - unsigned long off; - const u32 *ctx = clk_rst_suspend; - u32 val; - u32 plla_base; - u32 plld_base; - u32 plld2_base; - u32 pll_p_out12, pll_p_out34; - u32 pll_a_out0, pll_m_out1, pll_c_out1; - struct clk *p; - - /* FIXME: OSC_CTRL already restored by warm boot code? */ - val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; - val |= *ctx++; - clk_writel(val, OSC_CTRL); - clk_writel(*ctx++, CPU_SOFTRST_CTRL); - clk_writel(*ctx++, CPU_SOFTRST_CTRL1); - clk_writel(*ctx++, CPU_SOFTRST_CTRL2); - - /* Since we are going to reset devices and switch clock sources in this - * function, plls and secondary dividers is required to be enabled. The - * actual value will be restored back later. Note that boot plls: pllm, - * pllp, and pllu are already configured and enabled - */ - val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - val |= val << 16; - pll_p_out12 = *ctx++; - clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg); - pll_p_out34 = *ctx++; - clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg); - - tegra11_pllcx_clk_resume_enable(&tegra_pll_c2); - tegra11_pllcx_clk_resume_enable(&tegra_pll_c3); - tegra11_pllxc_clk_resume_enable(&tegra_pll_c); - tegra11_pllxc_clk_resume_enable(&tegra_pll_x); - tegra11_pllre_clk_resume_enable(&tegra_pll_re_out); - - plla_base = *ctx++; - clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); - clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE); - - plld_base = *ctx++; - clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); - clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE); - - plld2_base = *ctx++; - clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); - clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE); - - udelay(1000); - - val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - pll_m_out1 = *ctx++; - clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg); - pll_a_out0 = *ctx++; - clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg); - pll_c_out1 = *ctx++; - clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg); - - val = *ctx++; - tegra11_super_clk_resume(&tegra_clk_cclk_lp, - tegra_clk_virtual_cpu_lp.u.cpu.backup, val); - clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); - - clk_writel(*ctx++, tegra_clk_sclk.reg); - clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); - clk_writel(*ctx++, tegra_clk_pclk.reg); - - /* enable all clocks before configuring clock sources */ - clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L); - clk_writel(0xffddfff7ul, CLK_OUT_ENB_H); - clk_writel(0xfbfffbfeul, CLK_OUT_ENB_U); - clk_writel(0xfffffffful, CLK_OUT_ENB_V); - clk_writel(0xff7ffffful, CLK_OUT_ENB_W); - wmb(); - - for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; - off += 4) { - if (off == PERIPH_CLK_SOURCE_EMC) - continue; - clk_writel(*ctx++, off); - } - for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; - off += 4) { - clk_writel(*ctx++, off); - } - for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { - clk_writel(*ctx++, off); - } - for (off = PERIPH_CLK_SOURCE_XUSB_HOST; - off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4) - clk_writel(*ctx++, off); - - udelay(RESET_PROPAGATION_DELAY); - - clk_writel(*ctx++, RST_DEVICES_L); - clk_writel(*ctx++, RST_DEVICES_H); - clk_writel(*ctx++, RST_DEVICES_U); - clk_writel(*ctx++, RST_DEVICES_V); - clk_writel(*ctx++, RST_DEVICES_W); - clk_writel(*ctx++, RST_DEVICES_X); - wmb(); - - clk_writel(*ctx++, CLK_OUT_ENB_L); - clk_writel(*ctx++, CLK_OUT_ENB_H); - clk_writel(*ctx++, CLK_OUT_ENB_U); - - /* For LP0 resume, clk to lpcpu is required to be on */ - val = *ctx++; - val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN; - clk_writel(val, CLK_OUT_ENB_V); - - clk_writel(*ctx++, CLK_OUT_ENB_W); - clk_writel(*ctx++, CLK_OUT_ENB_X); - wmb(); - - /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */ - tegra11_dfll_clk_resume(&tegra_dfll_cpu); - - /* CPU G clock restored after DFLL and PLLs */ - clk_writel(*ctx++, tegra_clk_cclk_g.reg); - clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); - - clk_writel(*ctx++, SPARE_REG); - clk_writel(*ctx++, MISC_CLK_ENB); - clk_writel(*ctx++, CLK_MASK_ARM); - - /* Restore back the actual pll and secondary divider values */ - clk_writel(pll_p_out12, tegra_pll_p_out1.reg); - clk_writel(pll_p_out34, tegra_pll_p_out3.reg); - - p = &tegra_pll_c2; - if (p->state == OFF) - tegra11_pllcx_clk_disable(p); - p = &tegra_pll_c3; - if (p->state == OFF) - tegra11_pllcx_clk_disable(p); - p = &tegra_pll_c; - if (p->state == OFF) - tegra11_pllxc_clk_disable(p); - p = &tegra_pll_x; - if (p->state == OFF) - tegra11_pllxc_clk_disable(p); - p = &tegra_pll_re_vco; - if (p->state == OFF) - tegra11_pllre_clk_disable(p); - - clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE); - clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE); - clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE); - - clk_writel(pll_m_out1, tegra_pll_m_out1.reg); - clk_writel(pll_a_out0, tegra_pll_a_out0.reg); - clk_writel(pll_c_out1, tegra_pll_c_out1.reg); - - /* Since EMC clock is not restored, and may not preserve parent across - suspend, update current state, and mark EMC DFS as out of sync */ - p = tegra_clk_emc.parent; - tegra11_periph_clk_init(&tegra_clk_emc); - - /* Turn Off pll_m if it was OFF before suspend, and emc was not switched - to pll_m across suspend; re-init pll_m to sync s/w and h/w states */ - if ((tegra_pll_m.state == OFF) && - (&tegra_pll_m != tegra_clk_emc.parent)) - tegra11_pllm_clk_disable(&tegra_pll_m); - tegra11_pllm_clk_init(&tegra_pll_m); - - if (p != tegra_clk_emc.parent) { - pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)", - p->name, p->refcnt, tegra_clk_emc.parent->name, - tegra_clk_emc.parent->refcnt); - - /* emc switched to the new parent by low level code, but ref - count and s/w state need to be updated */ - clk_disable(p); - clk_enable(tegra_clk_emc.parent); - tegra_dvfs_set_rate(&tegra_clk_emc, - clk_get_rate_all_locked(&tegra_clk_emc)); - } - tegra_emc_timing_invalidate(); - - tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */ - tegra11_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */ - tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */ -} - -static struct syscore_ops tegra_clk_syscore_ops = { - .suspend = tegra11_clk_suspend, - .resume = tegra11_clk_resume, - .save = tegra11_clk_suspend, - .restore = tegra11_clk_resume, -}; -#endif - -/* Tegra11 CPU clock and reset control functions */ -static void tegra11_wait_cpu_in_reset(u32 cpu) -{ - unsigned int reg; - - do { - reg = readl(reg_clk_base + - TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); - cpu_relax(); - } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ - - return; -} - -static void tegra11_put_cpu_in_reset(u32 cpu) -{ - writel(CPU_RESET(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); - dmb(); -} - -static void tegra11_cpu_out_of_reset(u32 cpu) -{ - writel(CPU_RESET(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); - wmb(); -} - -static void tegra11_enable_cpu_clock(u32 cpu) -{ - unsigned int reg; - - writel(CPU_CLOCK(cpu), - reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); - reg = readl(reg_clk_base + - TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); -} -static void tegra11_disable_cpu_clock(u32 cpu) -{ -} - -static struct tegra_cpu_car_ops tegra11_cpu_car_ops = { - .wait_for_reset = tegra11_wait_cpu_in_reset, - .put_in_reset = tegra11_put_cpu_in_reset, - .out_of_reset = tegra11_cpu_out_of_reset, - .enable_clock = tegra11_enable_cpu_clock, - .disable_clock = tegra11_disable_cpu_clock, -}; - -static void __init tegra11_cpu_car_ops_init(void) -{ - tegra_cpu_car_ops = &tegra11_cpu_car_ops; -} - -static void tegra11_init_xusb_clocks(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++) - tegra11_init_one_clock(&tegra_xusb_source_clks[i]); - - tegra11_init_one_clock(&tegra_xusb_ss_div2); - tegra11_init_one_clock(&tegra_xusb_hs_src); - - for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++) - tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]); -} - -void __init tegra11x_init_clocks(void) -{ - int i; - struct clk *c; - - for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) - tegra11_init_one_clock(tegra_ptr_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) - tegra11_init_one_clock(&tegra_list_clks[i]); - - tegra11_init_one_clock(&tegra_camera_mclk); - - for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) - tegra11_init_one_clock(&tegra_sync_source_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) - tegra11_init_one_clock(&tegra_clk_audio_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) - tegra11_init_one_clock(&tegra_clk_audio_2x_list[i]); - - init_clk_out_mux(); - for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) - tegra11_init_one_clock(&tegra_clk_out_list[i]); - - tegra11_init_xusb_clocks(); - - for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { - c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); - if (!c) { - pr_err("%s: Unknown duplicate clock %s\n", __func__, - tegra_clk_duplicates[i].name); - continue; - } - - tegra_clk_duplicates[i].lookup.clk = c; - clkdev_add(&tegra_clk_duplicates[i].lookup); - } - - /* Initialize to default */ - tegra_init_cpu_edp_limits(0); - - tegra11_cpu_car_ops_init(); - -#ifdef CONFIG_PM_SLEEP - register_syscore_ops(&tegra_clk_syscore_ops); -#endif - -} - -static int __init tegra11x_clk_late_init(void) -{ - clk_disable(&tegra_pll_re_vco); - return 0; -} -late_initcall(tegra11x_clk_late_init); diff --git a/arch/arm/mach-tegra/tegra11_dvfs.c b/arch/arm/mach-tegra/tegra11_dvfs.c deleted file mode 100644 index 56238a2efd9c..000000000000 --- a/arch/arm/mach-tegra/tegra11_dvfs.c +++ /dev/null @@ -1,1012 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11_dvfs.c - * - * Copyright (c) 2012-2013 NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/string.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/kobject.h> -#include <linux/err.h> -#include <linux/tegra-fuse.h> - -#include "clock.h" -#include "dvfs.h" -#include "board.h" -#include "tegra_cl_dvfs.h" -#include "tegra_core_sysfs_limits.h" -#include "common.h" - -static bool tegra_dvfs_cpu_disabled; -static bool tegra_dvfs_core_disabled; - -#define KHZ 1000 -#define MHZ 1000000 - -#define TEGRA11_MIN_CORE_CURRENT 6000 -#define TEGRA11_CORE_VOLTAGE_CAP 1120 - -#define VDD_SAFE_STEP 100 - -static int vdd_core_vmin_trips_table[MAX_THERMAL_LIMITS] = { 20, }; -static int vdd_core_therm_floors_table[MAX_THERMAL_LIMITS] = { 950, }; - -static int vdd_cpu_vmax_trips_table[MAX_THERMAL_LIMITS] = { 70, }; -static int vdd_cpu_therm_caps_table[MAX_THERMAL_LIMITS] = { 1240, }; - -static struct tegra_cooling_device cpu_vmax_cdev = { - .cdev_type = "cpu_hot", -}; - -static struct tegra_cooling_device cpu_vmin_cdev = { - .cdev_type = "cpu_cold", -}; - -static struct tegra_cooling_device core_vmin_cdev = { - .cdev_type = "core_cold", -}; - -static struct dvfs_rail tegra11_dvfs_rail_vdd_cpu = { - .reg_id = "vdd_cpu", - .max_millivolts = 1400, - .min_millivolts = 800, - .step = VDD_SAFE_STEP, - .jmp_to_zero = true, - .vmin_cdev = &cpu_vmin_cdev, - .vmax_cdev = &cpu_vmax_cdev, -}; - -static struct dvfs_rail tegra11_dvfs_rail_vdd_core = { - .reg_id = "vdd_core", - .max_millivolts = 1400, - .min_millivolts = 800, - .step = VDD_SAFE_STEP, - .vmin_cdev = &core_vmin_cdev, -}; - -static struct dvfs_rail *tegra11_dvfs_rails[] = { - &tegra11_dvfs_rail_vdd_cpu, - &tegra11_dvfs_rail_vdd_core, -}; - -/* default cvb alignment on Tegra11 - 10mV */ -int __attribute__((weak)) tegra_get_cvb_alignment_uV(void) -{ - return 10000; -} - -/* CPU DVFS tables */ -static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { - { - .speedo_id = 0, - .process_id = -1, - .dfll_tune_data = { - .tune0 = 0x00b0019d, - .tune0_high_mv = 0x00b0019d, - .tune1 = 0x0000001f, - .droop_rate_min = 1000000, - .min_millivolts = 1000, - }, - .max_mv = 1250, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 100, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 306000, { 107330, -1569, 0}, { 90000, 0, 0} }, - { 408000, { 111250, -1666, 0}, { 90000, 0, 0} }, - { 510000, { 110000, -1460, 0}, { 94000, 0, 0} }, - { 612000, { 117290, -1745, 0}, { 94000, 0, 0} }, - { 714000, { 122700, -1910, 0}, { 99000, 0, 0} }, - { 816000, { 125620, -1945, 0}, { 99000, 0, 0} }, - { 918000, { 130560, -2076, 0}, { 103000, 0, 0} }, - {1020000, { 137280, -2303, 0}, { 103000, 0, 0} }, - {1122000, { 146440, -2660, 0}, { 109000, 0, 0} }, - {1224000, { 152190, -2825, 0}, { 109000, 0, 0} }, - {1326000, { 157520, -2953, 0}, { 112000, 0, 0} }, - {1428000, { 166100, -3261, 0}, { 140000, 0, 0} }, - {1530000, { 176410, -3647, 0}, { 140000, 0, 0} }, - {1632000, { 189620, -4186, 0}, { 140000, 0, 0} }, - {1734000, { 203190, -4725, 0}, { 140000, 0, 0} }, - {1836000, { 222670, -5573, 0}, { 140000, 0, 0} }, - {1938000, { 256210, -7165, 0}, { 140000, 0, 0} }, - {2040000, { 250050, -6544, 0}, { 140000, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20, }, - .therm_floors_table = { 1000, }, - }, - { - .speedo_id = 1, - .process_id = 0, - .dfll_tune_data = { - .tune0 = 0x00b0039d, - .tune0_high_mv = 0x00b0009d, - .tune1 = 0x0000001f, - .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1050, - .min_millivolts = 1000, - }, - .max_mv = 1320, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, - { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, - {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, - {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, - {1224000, { 2807010, -164171, 3576}, { 1090000, 0, 0} }, - {1326000, { 2885696, -166651, 3576}, { 1120000, 0, 0} }, - {1428000, { 2966422, -169131, 3576}, { 1400000, 0, 0} }, - {1530000, { 3049183, -171601, 3576}, { 1400000, 0, 0} }, - {1606500, { 3112179, -173451, 3576}, { 1400000, 0, 0} }, - {1708500, { 3198504, -175931, 3576}, { 1400000, 0, 0} }, - {1810500, { 3304747, -179126, 3576}, { 1400000, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20, }, - .therm_floors_table = { 1000, }, - }, - { - .speedo_id = 1, - .process_id = 1, - .dfll_tune_data = { - .tune0 = 0x00b0039d, - .tune0_high_mv = 0x00b0009d, - .tune1 = 0x0000001f, - .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1050, - .min_millivolts = 1000, - }, - .max_mv = 1320, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, - { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, - {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, - {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, - {1224000, { 2807010, -164171, 3576}, { 1090000, 0, 0} }, - {1326000, { 2885696, -166651, 3576}, { 1120000, 0, 0} }, - {1428000, { 2966422, -169131, 3576}, { 1400000, 0, 0} }, - {1530000, { 3049183, -171601, 3576}, { 1400000, 0, 0} }, - {1606500, { 3112179, -173451, 3576}, { 1400000, 0, 0} }, - {1708500, { 3198504, -175931, 3576}, { 1400000, 0, 0} }, - {1810500, { 3304747, -179126, 3576}, { 1400000, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20, }, - .therm_floors_table = { 1000, }, - }, - { - .speedo_id = 2, - .process_id = -1, - .dfll_tune_data = { - .tune0 = 0x00b0039d, - .tune0_high_mv = 0x00b0009d, - .tune1 = 0x0000001f, - .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1050, - .min_millivolts = 1000, - }, - .max_mv = 1320, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, - { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, - {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, - {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, - {1224000, { 2807010, -164171, 3576}, { 1090000, 0, 0} }, - {1326000, { 2885696, -166651, 3576}, { 1120000, 0, 0} }, - {1428000, { 2966422, -169131, 3576}, { 1400000, 0, 0} }, - {1530000, { 3049183, -171601, 3576}, { 1400000, 0, 0} }, - {1606500, { 3112179, -173451, 3576}, { 1400000, 0, 0} }, - {1708500, { 3198504, -175931, 3576}, { 1400000, 0, 0} }, - {1810500, { 3304747, -179126, 3576}, { 1400000, 0, 0} }, - {1912500, { 3395401, -181606, 3576}, { 1400000, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20, }, - .therm_floors_table = { 1000, }, - }, - { - .speedo_id = 3, - .process_id = -1, - .dfll_tune_data = { - .tune0 = 0x00b0039d, - .tune0_high_mv = 0x00b0009d, - .tune1 = 0x0000001f, - .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1050, - .min_millivolts = 1000, - }, - .max_mv = 1320, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, - { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, - {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, - {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, - {1224000, { 2807010, -164171, 3576}, { 1090000, 0, 0} }, - {1326000, { 2885696, -166651, 3576}, { 1120000, 0, 0} }, - {1428000, { 2966422, -169131, 3576}, { 1400000, 0, 0} }, - {1530000, { 3049183, -171601, 3576}, { 1400000, 0, 0} }, - {1606500, { 3112179, -173451, 3576}, { 1400000, 0, 0} }, - {1708500, { 3198504, -175931, 3576}, { 1400000, 0, 0} }, - {1810500, { 3304747, -179126, 3576}, { 1400000, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20, }, - .therm_floors_table = { 1000, }, - }, -}; - -static int cpu_millivolts[MAX_DVFS_FREQS]; -static int cpu_dfll_millivolts[MAX_DVFS_FREQS]; - -static struct dvfs cpu_dvfs = { - .clk_name = "cpu_g", - .millivolts = cpu_millivolts, - .dfll_millivolts = cpu_dfll_millivolts, - .auto_dvfs = true, - .dvfs_rail = &tegra11_dvfs_rail_vdd_cpu, -}; - -/* Core DVFS tables */ -/* FIXME: real data */ -static const int core_millivolts[MAX_DVFS_FREQS] = { - 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250, 1390}; - -#define CORE_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \ - { \ - .clk_name = _clk_name, \ - .speedo_id = _speedo_id, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .millivolts = core_millivolts, \ - .auto_dvfs = _auto, \ - .dvfs_rail = &tegra11_dvfs_rail_vdd_core, \ - } - -#define OVRRD_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \ - { \ - .clk_name = _clk_name, \ - .speedo_id = _speedo_id, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .millivolts = core_millivolts, \ - .auto_dvfs = _auto, \ - .can_override = true, \ - .dvfs_rail = &tegra11_dvfs_rail_vdd_core, \ - } - -static struct dvfs core_dvfs_table[] = { - /* Core voltages (mV): 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250, 1390 */ - /* Clock limits for internal blocks, PLLs */ - CORE_DVFS("emc", -1, -1, 1, KHZ, 1, 1, 1, 1, 800000, 800000, 933000, 933000, 1066000, 1066000), - - CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 228000, 306000, 396000, 510000, 648000, 696000, 696000, 696000, 696000, 696000), - CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 324000, 396000, 510000, 612000, 696000, 696000, 696000, 696000, 696000, 696000), - CORE_DVFS("cpu_lp", 1, 1, 1, KHZ, 324000, 396000, 510000, 612000, 768000, 816000, 816000, 816000, 816000, 816000), - - CORE_DVFS("sbus", 0, 0, 1, KHZ, 132000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000, 336000), - CORE_DVFS("sbus", 0, 1, 1, KHZ, 180000, 228000, 276000, 336000, 336000, 336000, 336000, 336000, 336000, 336000), - CORE_DVFS("sbus", 1, 1, 1, KHZ, 180000, 228000, 276000, 336000, 372000, 384000, 384000, 384000, 384000, 384000), - - CORE_DVFS("vi", -1, 0, 1, KHZ, 144000, 216000, 240000, 312000, 372000, 408000, 408000, 408000, 408000, 408000), - CORE_DVFS("vi", -1, 1, 1, KHZ, 144000, 216000, 240000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - - CORE_DVFS("2d", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000), - CORE_DVFS("3d", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000), - CORE_DVFS("epp", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000), - - CORE_DVFS("2d", -1, 1, 1, KHZ, 240000, 300000, 384000, 468000, 528000, 564000, 600000, 636000, 672000, 828000), - CORE_DVFS("3d", -1, 1, 1, KHZ, 240000, 300000, 384000, 468000, 528000, 564000, 600000, 636000, 672000, 828000), - CORE_DVFS("epp", -1, 1, 1, KHZ, 240000, 300000, 384000, 468000, 528000, 564000, 600000, 636000, 672000, 828000), - - CORE_DVFS("msenc", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("se", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("tsec", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("vde", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 432000, 480000, 480000, 480000, 480000), - - CORE_DVFS("msenc", 0, 1, 1, KHZ, 204000, 252000, 324000, 408000, 408000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("se", 0, 1, 1, KHZ, 204000, 252000, 324000, 408000, 408000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("tsec", 0, 1, 1, KHZ, 204000, 252000, 324000, 408000, 408000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("vde", 0, 1, 1, KHZ, 204000, 252000, 324000, 408000, 408000, 432000, 480000, 480000, 480000, 480000), - - CORE_DVFS("msenc", 1, 1, 1, KHZ, 204000, 252000, 324000, 408000, 456000, 480000, 480000, 480000, 480000, 480000), - CORE_DVFS("se", 1, 1, 1, KHZ, 204000, 252000, 324000, 408000, 456000, 480000, 480000, 480000, 480000, 480000), - CORE_DVFS("tsec", 1, 1, 1, KHZ, 204000, 252000, 324000, 408000, 456000, 480000, 480000, 480000, 480000, 480000), - CORE_DVFS("vde", 1, 1, 1, KHZ, 204000, 252000, 324000, 408000, 456000, 480000, 480000, 480000, 480000, 480000), - - CORE_DVFS("host1x", 0, 0, 1, KHZ, 144000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000, 336000), - CORE_DVFS("host1x", 0, 1, 1, KHZ, 180000, 228000, 276000, 336000, 336000, 336000, 336000, 336000, 336000, 336000), - CORE_DVFS("host1x", 1, 1, 1, KHZ, 180000, 228000, 276000, 336000, 372000, 384000, 384000, 384000, 384000, 384000), - -#ifdef CONFIG_TEGRA_DUAL_CBUS - CORE_DVFS("c2bus", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000), - CORE_DVFS("c2bus", -1, 1, 1, KHZ, 240000, 300000, 384000, 468000, 528000, 564000, 600000, 636000, 672000, 828000), - CORE_DVFS("c3bus", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("c3bus", 0, 1, 1, KHZ, 204000, 252000, 324000, 408000, 408000, 432000, 480000, 480000, 480000, 480000), - CORE_DVFS("c3bus", 1, 1, 1, KHZ, 204000, 252000, 324000, 408000, 456000, 480000, 480000, 480000, 480000, 480000), -#else - CORE_DVFS("cbus", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000), - CORE_DVFS("cbus", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - CORE_DVFS("cbus", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000), -#endif - - CORE_DVFS("pll_m", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000), - CORE_DVFS("pll_c", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000), - CORE_DVFS("pll_c2", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000), - CORE_DVFS("pll_c3", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000), - - /* Core voltages (mV): 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250, 1390 */ - /* Clock limits for I/O peripherals */ - CORE_DVFS("sbc1", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000), - CORE_DVFS("sbc2", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000), - CORE_DVFS("sbc3", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000), - CORE_DVFS("sbc4", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000), - CORE_DVFS("sbc5", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000), - CORE_DVFS("sbc6", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000), - - OVRRD_DVFS("sdmmc1", 0, 0, 1, KHZ, 1, 81600, 81600, 81600, 81600, 156000, 156000, 156000, 204000, 204000), - OVRRD_DVFS("sdmmc3", 0, 0, 1, KHZ, 1, 81600, 81600, 81600, 81600, 156000, 156000, 156000, 204000, 204000), - OVRRD_DVFS("sdmmc4", 0, 0, 1, KHZ, 1, 102000, 102000, 102000, 102000, 156000, 156000, 156000, 200000, 200000), - - OVRRD_DVFS("sdmmc1", 0, 1, 1, KHZ, 1, 81600, 81600, 81600, 81600, 156000, 204000, 204000, 204000, 204000), - OVRRD_DVFS("sdmmc3", 0, 1, 1, KHZ, 1, 81600, 81600, 81600, 81600, 156000, 204000, 204000, 204000, 204000), - OVRRD_DVFS("sdmmc4", 0, 1, 1, KHZ, 1, 102000, 102000, 102000, 102000, 156000, 200000, 200000, 200000, 200000), - - OVRRD_DVFS("sdmmc1", 1, 1, 1, KHZ, 1, 81600, 81600, 81600, 81600, 156000, 156000, 156000, 204000, 204000), - OVRRD_DVFS("sdmmc3", 1, 1, 1, KHZ, 1, 81600, 81600, 81600, 81600, 156000, 156000, 156000, 204000, 204000), - OVRRD_DVFS("sdmmc4", 1, 1, 1, KHZ, 1, 102000, 102000, 102000, 102000, 156000, 156000, 156000, 200000, 200000), - - CORE_DVFS("hdmi", -1, -1, 1, KHZ, 148500, 148500, 148500, 297000, 297000, 297000, 297000, 297000, 297000, 297000), - - /* - * The clock rate for the display controllers that determines the - * necessary core voltage depends on a divider that is internal - * to the display block. Disable auto-dvfs on the display clocks, - * and let the display driver call tegra_dvfs_set_rate manually - */ - CORE_DVFS("disp1", -1, -1, 0, KHZ, 166000, 166000, 166000, 297000, 297000, 297000, 297000, 297000, 297000, 297000), - CORE_DVFS("disp2", -1, -1, 0, KHZ, 166000, 166000, 166000, 297000, 297000, 297000, 297000, 297000, 297000, 297000), - - /* xusb clocks */ - CORE_DVFS("xusb_falcon_src", -1, -1, 1, KHZ, 1, 336000, 336000, 336000, 336000, 336000, 336000, 336000, 336000, 336000), - CORE_DVFS("xusb_host_src", -1, -1, 1, KHZ, 1, 112000, 112000, 112000, 112000, 112000, 112000, 112000, 112000, 112000), - CORE_DVFS("xusb_dev_src", -1, -1, 1, KHZ, 1, 58300, 58300, 112000, 112000, 112000, 112000, 112000, 112000, 112000), - CORE_DVFS("xusb_ss_src", -1, -1, 1, KHZ, 1, 122400, 122400, 122400, 122400, 122400, 122400, 122400, 122400, 122400), - CORE_DVFS("xusb_fs_src", -1, -1, 1, KHZ, 1, 48000, 48000, 48000, 48000, 48000, 48000, 48000, 48000, 48000), - CORE_DVFS("xusb_hs_src", -1, -1, 1, KHZ, 1, 61200, 61200, 61200, 61200, 61200, 61200, 61200, 61200, 61200), -}; - -int tegra_dvfs_disable_core_set(const char *arg, const struct kernel_param *kp) -{ - int ret; - - ret = param_set_bool(arg, kp); - if (ret) - return ret; - - if (tegra_dvfs_core_disabled) - tegra_dvfs_rail_disable(&tegra11_dvfs_rail_vdd_core); - else - tegra_dvfs_rail_enable(&tegra11_dvfs_rail_vdd_core); - - return 0; -} - -int tegra_dvfs_disable_cpu_set(const char *arg, const struct kernel_param *kp) -{ - int ret; - - ret = param_set_bool(arg, kp); - if (ret) - return ret; - - if (tegra_dvfs_cpu_disabled) - tegra_dvfs_rail_disable(&tegra11_dvfs_rail_vdd_cpu); - else - tegra_dvfs_rail_enable(&tegra11_dvfs_rail_vdd_cpu); - - return 0; -} - -int tegra_dvfs_disable_get(char *buffer, const struct kernel_param *kp) -{ - return param_get_bool(buffer, kp); -} - -static struct kernel_param_ops tegra_dvfs_disable_core_ops = { - .set = tegra_dvfs_disable_core_set, - .get = tegra_dvfs_disable_get, -}; - -static struct kernel_param_ops tegra_dvfs_disable_cpu_ops = { - .set = tegra_dvfs_disable_cpu_set, - .get = tegra_dvfs_disable_get, -}; - -module_param_cb(disable_core, &tegra_dvfs_disable_core_ops, - &tegra_dvfs_core_disabled, 0644); -module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops, - &tegra_dvfs_cpu_disabled, 0644); - -static bool __init can_update_max_rate(struct clk *c, struct dvfs *d) -{ - /* Don't update manual dvfs clocks */ - if (!d->auto_dvfs) - return false; - - /* - * Don't update EMC shared bus, since EMC dvfs is board dependent: max - * rate and EMC scaling frequencies are determined by tegra BCT (flashed - * together with the image) and board specific EMC DFS table; we will - * check the scaling ladder against nominal core voltage when the table - * is loaded (and if on particular board the table is not loaded, EMC - * scaling is disabled). - */ - if (c->ops->shared_bus_update && (c->flags & PERIPH_EMC_ENB)) - return false; - - /* - * Don't update shared cbus, and don't propagate common cbus dvfs - * limit down to shared users, but set maximum rate for each user - * equal to the respective client limit. - */ - if (c->ops->shared_bus_update && (c->flags & PERIPH_ON_CBUS)) { - struct clk *user; - unsigned long rate; - - list_for_each_entry( - user, &c->shared_bus_list, u.shared_bus_user.node) { - if (user->u.shared_bus_user.client) { - rate = user->u.shared_bus_user.client->max_rate; - user->max_rate = rate; - user->u.shared_bus_user.rate = rate; - } - } - return false; - } - - /* Other, than EMC and cbus, auto-dvfs clocks can be updated */ - return true; -} - -static void __init init_dvfs_one(struct dvfs *d, int max_freq_index) -{ - int ret; - struct clk *c = tegra_get_clock_by_name(d->clk_name); - - if (!c) { - pr_debug("tegra11_dvfs: no clock found for %s\n", - d->clk_name); - return; - } - - /* Update max rate for auto-dvfs clocks, with shared bus exceptions */ - if (can_update_max_rate(c, d)) { - BUG_ON(!d->freqs[max_freq_index]); - tegra_init_max_rate( - c, d->freqs[max_freq_index] * d->freqs_mult); - } - d->max_millivolts = d->dvfs_rail->nominal_millivolts; - - ret = tegra_enable_dvfs_on_clk(c, d); - if (ret) - pr_err("tegra11_dvfs: failed to enable dvfs on %s\n", c->name); -} - -static bool __init match_dvfs_one(struct dvfs *d, int speedo_id, int process_id) -{ - if ((d->process_id != -1 && d->process_id != process_id) || - (d->speedo_id != -1 && d->speedo_id != speedo_id)) { - pr_debug("tegra11_dvfs: rejected %s speedo %d," - " process %d\n", d->clk_name, d->speedo_id, - d->process_id); - return false; - } - return true; -} - -static bool __init match_cpu_cvb_one(struct cpu_cvb_dvfs *d, - int speedo_id, int process_id) -{ - if ((d->process_id != -1 && d->process_id != process_id) || - (d->speedo_id != -1 && d->speedo_id != speedo_id)) { - pr_debug("tegra11_dvfs: rejected cpu cvb speedo %d," - " process %d\n", d->speedo_id, d->process_id); - return false; - } - return true; -} - -/* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) / v_scale */ -static inline int get_cvb_voltage(int speedo, int s_scale, - struct cvb_dvfs_parameters *cvb) -{ - /* apply only speedo scale: output mv = cvb_mv * v_scale */ - int mv; - mv = DIV_ROUND_CLOSEST(cvb->c2 * speedo, s_scale); - mv = DIV_ROUND_CLOSEST((mv + cvb->c1) * speedo, s_scale) + cvb->c0; - return mv; -} - -static inline int round_cvb_voltage(int mv, int v_scale) -{ - /* combined: apply voltage scale and round to cvb alignment step */ - int cvb_align_step_uv = tegra_get_cvb_alignment_uV(); - - return DIV_ROUND_UP(mv * 1000, v_scale * cvb_align_step_uv) * - cvb_align_step_uv / 1000; -} - -static inline void override_min_millivolts(struct cpu_cvb_dvfs *d) -{ - /* override dfll min_millivolts if dfll Vmin designated fuse 61 set */ - if (tegra_spare_fuse(61)) - d->dfll_tune_data.min_millivolts = 900; - - /* - * override pll min_millivolts for T40DC sku (the only parameter - * that seprated it from all skus with speedo_id 1) - */ - if (tegra_get_sku_id() == 0x20) - d->cvb_table[0].cvb_pll_param.c0 = 940 * d->voltage_scale; -} - -static int __init set_cpu_dvfs_data( - struct cpu_cvb_dvfs *d, struct dvfs *cpu_dvfs, int *max_freq_index) -{ - int i, j, mv, dfll_mv, min_dfll_mv; - unsigned long fmax_at_vmin = 0; - unsigned long fmax_pll_mode = 0; - unsigned long fmin_use_dfll = 0; - struct cvb_dvfs_table *table = NULL; - int speedo = tegra_cpu_speedo_value(); - - override_min_millivolts(d); - min_dfll_mv = d->dfll_tune_data.min_millivolts; - BUG_ON(min_dfll_mv < tegra11_dvfs_rail_vdd_cpu.min_millivolts); - - /* - * Use CVB table to fill in CPU dvfs frequencies and voltages. Each - * CVB entry specifies CPU frequency and CVB coefficients to calculate - * the respective voltage when either DFLL or PLL is used as CPU clock - * source. - * - * Minimum voltage limit is applied only to DFLL source. For PLL source - * voltage can go as low as table specifies. Maximum voltage limit is - * applied to both sources, but differently: directly clip voltage for - * DFLL, and limit maximum frequency for PLL. - */ - for (i = 0, j = 0; i < MAX_DVFS_FREQS; i++) { - table = &d->cvb_table[i]; - if (!table->freq) - break; - - dfll_mv = get_cvb_voltage( - speedo, d->speedo_scale, &table->cvb_dfll_param); - dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale); - - mv = get_cvb_voltage( - speedo, d->speedo_scale, &table->cvb_pll_param); - mv = round_cvb_voltage(mv, d->voltage_scale); - - /* Check maximum frequency at minimum voltage for dfll source */ - dfll_mv = max(dfll_mv, min_dfll_mv); - if (dfll_mv > min_dfll_mv) { - if (!j) - break; /* 1st entry already above Vmin */ - if (!fmax_at_vmin) - fmax_at_vmin = cpu_dvfs->freqs[j - 1]; - } - - /* Clip maximum frequency at maximum voltage for pll source */ - if (mv > d->max_mv) { - if (!j) - break; /* 1st entry already above Vmax */ - if (!fmax_pll_mode) - fmax_pll_mode = cpu_dvfs->freqs[j - 1]; - } - - /* Minimum rate with pll source voltage above dfll Vmin */ - if ((mv >= min_dfll_mv) && (!fmin_use_dfll)) - fmin_use_dfll = table->freq; - - /* fill in dvfs tables */ - cpu_dvfs->freqs[j] = table->freq; - cpu_dfll_millivolts[j] = min(dfll_mv, d->max_mv); - cpu_millivolts[j] = mv; - j++; - - /* - * "Round-up" frequency list cut-off (keep first entry that - * exceeds max voltage - the voltage limit will be enforced - * anyway, so when requested this frequency dfll will settle - * at whatever high frequency it can on the particular chip) - */ - if (dfll_mv > d->max_mv) - break; - } - /* Table must not be empty and must have and at least one entry below, - and one entry above Vmin */ - if (!i || !j || !fmax_at_vmin) { - pr_err("tegra11_dvfs: invalid cpu dvfs table\n"); - return -ENOENT; - } - - /* Must have crossover between dfll and pll operating ranges */ - if (!fmin_use_dfll || (fmin_use_dfll > fmax_at_vmin)) { - pr_err("tegra11_dvfs: no crossover of dfll and pll voltages\n"); - return -EINVAL; - } - - /* dvfs tables are successfully populated - fill in the rest */ - cpu_dvfs->speedo_id = d->speedo_id; - cpu_dvfs->process_id = d->process_id; - cpu_dvfs->freqs_mult = d->freqs_mult; - cpu_dvfs->dvfs_rail->nominal_millivolts = min(d->max_mv, - max(cpu_millivolts[j - 1], cpu_dfll_millivolts[j - 1])); - *max_freq_index = j - 1; - - cpu_dvfs->dfll_data = d->dfll_tune_data; - cpu_dvfs->dfll_data.max_rate_boost = fmax_pll_mode ? - (cpu_dvfs->freqs[j - 1] - fmax_pll_mode) * d->freqs_mult : 0; - cpu_dvfs->dfll_data.out_rate_min = fmax_at_vmin * d->freqs_mult; - cpu_dvfs->dfll_data.use_dfll_rate_min = fmin_use_dfll * d->freqs_mult; - cpu_dvfs->dfll_data.min_millivolts = min_dfll_mv; - - return 0; -} - -static int __init get_core_nominal_mv_index(int speedo_id) -{ - int i; - int mv = tegra_core_speedo_mv(); - int core_edp_voltage = get_core_edp(); - int core_edp_current = get_maximum_core_current_supported(); - u32 tegra_sku_id; - - /* - * If core regulator current limit is below minimum required to reach - * nominal frequencies, cap core voltage, and through dvfs table all - * core domain frequencies at the respective limits. - * - * If core boot edp limit is not set, cap core voltage as well. - * - * Otherwise, leave nominal core voltage at chip bin level, and set - * all detach mode (boot, suspend, disable) limits same as boot edp - * (for now, still throttle nominal for other than T40T skus). - */ - if (core_edp_current < TEGRA11_MIN_CORE_CURRENT) { - core_edp_voltage = min(core_edp_voltage, - TEGRA11_CORE_VOLTAGE_CAP); - pr_warn("tegra11_dvfs: vdd core current limit %d mA\n" - " below min current requirements %d mA\n" - " !!!! CORE VOLTAGE IS CAPPED AT %d mV\n", - core_edp_current, TEGRA11_MIN_CORE_CURRENT, - TEGRA11_CORE_VOLTAGE_CAP); - } - - if (!core_edp_voltage) - core_edp_voltage = TEGRA11_CORE_VOLTAGE_CAP; - - tegra_sku_id = tegra_get_sku_id(); - if ((core_edp_voltage <= TEGRA11_CORE_VOLTAGE_CAP) || - ((tegra_sku_id != 0x4) && (tegra_sku_id != 0x8))) - mv = min(mv, core_edp_voltage); - - /* use boot edp limit as disable and suspend levels as well */ - tegra11_dvfs_rail_vdd_core.boot_millivolts = core_edp_voltage; - tegra11_dvfs_rail_vdd_core.suspend_millivolts = core_edp_voltage; - tegra11_dvfs_rail_vdd_core.disable_millivolts = core_edp_voltage; - - /* Round nominal level down to the nearest core scaling step */ - for (i = 0; i < MAX_DVFS_FREQS; i++) { - if ((core_millivolts[i] == 0) || (mv < core_millivolts[i])) - break; - } - - if (i == 0) { - pr_err("tegra11_dvfs: unable to adjust core dvfs table to" - " nominal voltage %d\n", mv); - return -ENOSYS; - } - return i - 1; -} - -int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, - bool before_clk_update, int cpu_event) -{ - /* empty definition for tegra11 */ - return 0; -} - -void __init tegra11x_init_dvfs(void) -{ - int cpu_speedo_id = tegra_cpu_speedo_id(); - int cpu_process_id = tegra_cpu_process_id(); - int soc_speedo_id = tegra_soc_speedo_id(); - int core_process_id = tegra_core_process_id(); - - int i, ret; - int core_nominal_mv_index; - int cpu_max_freq_index = 0; - -#ifndef CONFIG_TEGRA_CORE_DVFS - tegra_dvfs_core_disabled = true; -#endif -#ifndef CONFIG_TEGRA_CPU_DVFS - tegra_dvfs_cpu_disabled = true; -#endif - /* Setup rail bins */ - tegra11_dvfs_rail_vdd_cpu.stats.bin_uV = tegra_get_cvb_alignment_uV(); - tegra11_dvfs_rail_vdd_core.stats.bin_uV = tegra_get_cvb_alignment_uV(); - - /* - * Find nominal voltages for core (1st) and cpu rails before rail - * init. Nominal voltage index in core scaling ladder can also be - * used to determine max dvfs frequencies for all core clocks. In - * case of error disable core scaling and set index to 0, so that - * core clocks would not exceed rates allowed at minimum voltage. - */ - core_nominal_mv_index = get_core_nominal_mv_index(soc_speedo_id); - if (core_nominal_mv_index < 0) { - tegra11_dvfs_rail_vdd_core.disabled = true; - tegra_dvfs_core_disabled = true; - core_nominal_mv_index = 0; - } - tegra11_dvfs_rail_vdd_core.nominal_millivolts = - core_millivolts[core_nominal_mv_index]; - - /* - * Setup cpu dvfs and dfll tables from cvb data, determine nominal - * voltage for cpu rail, and cpu maximum frequency. Note that entire - * frequency range is guaranteed only when dfll is used as cpu clock - * source. Reaching maximum frequency with pll as cpu clock source - * may not be possible within nominal voltage range (dvfs mechanism - * would automatically fail frequency request in this case, so that - * voltage limit is not violated). Error when cpu dvfs table can not - * be constructed must never happen. - */ - for (ret = 0, i = 0; i < ARRAY_SIZE(cpu_cvb_dvfs_table); i++) { - struct cpu_cvb_dvfs *d = &cpu_cvb_dvfs_table[i]; - if (match_cpu_cvb_one(d, cpu_speedo_id, cpu_process_id)) { - ret = set_cpu_dvfs_data( - d, &cpu_dvfs, &cpu_max_freq_index); - break; - } - } - BUG_ON((i == ARRAY_SIZE(cpu_cvb_dvfs_table)) || ret); - - /* Init thermal limits */ - tegra_dvfs_rail_init_vmax_thermal_profile( - vdd_cpu_vmax_trips_table, vdd_cpu_therm_caps_table, - &tegra11_dvfs_rail_vdd_cpu, &cpu_dvfs.dfll_data); - tegra_dvfs_rail_init_vmin_thermal_profile( - cpu_cvb_dvfs_table[i].vmin_trips_table, - cpu_cvb_dvfs_table[i].therm_floors_table, - &tegra11_dvfs_rail_vdd_cpu, &cpu_dvfs.dfll_data); - tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table, - vdd_core_therm_floors_table, &tegra11_dvfs_rail_vdd_core, NULL); - - /* Init rail structures and dependencies */ - tegra_dvfs_init_rails(tegra11_dvfs_rails, - ARRAY_SIZE(tegra11_dvfs_rails)); - - /* Search core dvfs table for speedo/process matching entries and - initialize dvfs-ed clocks */ - for (i = 0; i < ARRAY_SIZE(core_dvfs_table); i++) { - struct dvfs *d = &core_dvfs_table[i]; - if (!match_dvfs_one(d, soc_speedo_id, core_process_id)) - continue; - init_dvfs_one(d, core_nominal_mv_index); - } - - /* Initialize matching cpu dvfs entry already found when nominal - voltage was determined */ - init_dvfs_one(&cpu_dvfs, cpu_max_freq_index); - - /* Finally disable dvfs on rails if necessary */ - if (tegra_dvfs_core_disabled) - tegra_dvfs_rail_disable(&tegra11_dvfs_rail_vdd_core); - if (tegra_dvfs_cpu_disabled) - tegra_dvfs_rail_disable(&tegra11_dvfs_rail_vdd_cpu); - - pr_info("tegra dvfs: VDD_CPU nominal %dmV, scaling %s\n", - tegra11_dvfs_rail_vdd_cpu.nominal_millivolts, - tegra_dvfs_cpu_disabled ? "disabled" : "enabled"); - pr_info("tegra dvfs: VDD_CORE nominal %dmV, scaling %s\n", - tegra11_dvfs_rail_vdd_core.nominal_millivolts, - tegra_dvfs_core_disabled ? "disabled" : "enabled"); -} - -int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail) -{ - return 0; -} - -int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail) -{ - return 0; -} - -/* Core voltage and bus cap object and tables */ -static struct kobject *cap_kobj; -static struct kobject *floor_kobj; -static struct kobject *gpu_kobj; - -static struct core_dvfs_cap_table tegra11_core_cap_table[] = { -#ifdef CONFIG_TEGRA_DUAL_CBUS - { .cap_name = "cap.c2bus" }, - { .cap_name = "cap.c3bus" }, -#else - { .cap_name = "cap.cbus" }, -#endif - { .cap_name = "cap.sclk" }, - { .cap_name = "cap.emc" }, - { .cap_name = "cap.host1x" }, -}; - -/* - * Keep sys file names the same for dual and single cbus configurations to - * avoid changes in user space GPU capping interface. - */ -static struct core_bus_limit_table tegra11_bus_cap_table[] = { -#ifdef CONFIG_TEGRA_DUAL_CBUS - { .limit_clk_name = "cap.profile.c2bus", - .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "cbus_cap_level", .mode = 0644} }, - }, -#else - { .limit_clk_name = "cap.profile.cbus", - .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "cbus_cap_level", .mode = 0644} }, - }, -#endif -}; - -static struct core_bus_limit_table tegra11_bus_floor_table[] = { - { .limit_clk_name = "floor.profile.host1x", - .refcnt_attr = {.attr = {.name = "h1x_floor_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "h1x_floor_level", .mode = 0644} }, - }, - { .limit_clk_name = "floor.profile.emc", - .refcnt_attr = {.attr = {.name = "emc_floor_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "emc_floor_level", .mode = 0644} }, - }, -#ifdef CONFIG_TEGRA_DUAL_CBUS - { .limit_clk_name = "floor.profile.c2bus", - .refcnt_attr = {.attr = {.name = "cbus_floor_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "cbus_floor_level", .mode = 0644} }, - }, -#else - { .limit_clk_name = "floor.profile.cbus", - .refcnt_attr = {.attr = {.name = "cbus_floor_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "cbus_floor_level", .mode = 0644} }, - }, -#endif -}; - -static struct core_bus_rates_table tegra11_gpu_rates_sysfs = { - .bus_clk_name = "c2bus", - .rate_attr = {.attr = {.name = "gpu_rate", .mode = 0444} }, - .available_rates_attr = { - .attr = {.name = "gpu_available_rates", .mode = 0444} }, -}; - -static int __init tegra11_dvfs_init_core_limits(void) -{ - int ret; - - cap_kobj = kobject_create_and_add("tegra_cap", kernel_kobj); - if (!cap_kobj) { - pr_err("tegra11_dvfs: failed to create sysfs cap object\n"); - return 0; - } - - ret = tegra_init_shared_bus_cap( - tegra11_bus_cap_table, ARRAY_SIZE(tegra11_bus_cap_table), - cap_kobj); - if (ret) { - pr_err("tegra11_dvfs: failed to init bus cap interface (%d)\n", - ret); - kobject_del(cap_kobj); - return 0; - } - - ret = tegra_init_core_cap( - tegra11_core_cap_table, ARRAY_SIZE(tegra11_core_cap_table), - core_millivolts, ARRAY_SIZE(core_millivolts), cap_kobj); - - if (ret) { - pr_err("tegra11_dvfs: failed to init core cap interface (%d)\n", - ret); - kobject_del(cap_kobj); - return 0; - } - pr_info("tegra dvfs: tegra sysfs cap interface is initialized\n"); - - floor_kobj = kobject_create_and_add("tegra_floor", kernel_kobj); - if (!floor_kobj) { - pr_err("tegra11_dvfs: failed to create sysfs floor object\n"); - return 0; - } - - ret = tegra_init_shared_bus_floor( - tegra11_bus_floor_table, ARRAY_SIZE(tegra11_bus_floor_table), - floor_kobj); - if (ret) { - pr_err("tegra11_dvfs: failed to init bus floor interface (%d)\n", - ret); - kobject_del(floor_kobj); - return 0; - } - pr_info("tegra dvfs: tegra sysfs floor interface is initialized\n"); - - gpu_kobj = kobject_create_and_add("tegra_gpu", kernel_kobj); - if (!gpu_kobj) { - pr_err("tegra11_dvfs: failed to create sysfs gpu object\n"); - return 0; - } - - ret = tegra_init_sysfs_shared_bus_rate(&tegra11_gpu_rates_sysfs, - 1, gpu_kobj); - if (ret) { - pr_err("tegra11_dvfs: failed to init gpu rates interface (%d)\n", - ret); - kobject_del(gpu_kobj); - return 0; - } - pr_info("tegra dvfs: tegra sysfs gpu interface is initialized\n"); - - return 0; -} -late_initcall(tegra11_dvfs_init_core_limits); diff --git a/arch/arm/mach-tegra/tegra11_edp.c b/arch/arm/mach-tegra/tegra11_edp.c deleted file mode 100644 index 281b05b6a3a9..000000000000 --- a/arch/arm/mach-tegra/tegra11_edp.c +++ /dev/null @@ -1,1020 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11_edp.c - * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/string.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/kobject.h> -#include <linux/err.h> -#include <linux/tegra-fuse.h> - -#include <mach/edp.h> - -#include "clock.h" -#include "common.h" - -#define CORE_MODULES_STATES 1 -#define TEMPERATURE_RANGES 4 -#define CAP_CLKS_NUM 2 -#define TOTAL_CAPS (CORE_EDP_PROFILES_NUM * CORE_MODULES_STATES *\ - TEMPERATURE_RANGES * CAP_CLKS_NUM) - -struct core_edp_entry { - int sku; - int process_id; - unsigned int cap_mA; - int mult; - unsigned long cap_scpu_on[CORE_EDP_PROFILES_NUM][ - CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM]; - unsigned long cap_scpu_off[CORE_EDP_PROFILES_NUM][ - CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM]; -}; - -static int temperatures[] = { 50, 70, 90, 105 }; - -#ifdef CONFIG_TEGRA_DUAL_CBUS -static char *cap_clks_names[] = { "edp.emc", "edp.c2bus" }; -#else -static char *cap_clks_names[] = { "edp.emc", "edp.cbus" }; -#endif -static struct clk *cap_clks[CAP_CLKS_NUM]; - -static struct core_edp_entry core_edp_table[] = { - /* SKU 3 */ - { - .sku = 0x3, /* SKU = 3 */ - .process_id = -1, /* any process id */ - .cap_mA = 6000, /* 6A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 636 }, - { 924, 612 }, - { 924, 564 }, - { 924, 384 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 792, 636 }, - { 792, 636 }, - { 792, 636 }, - { 792, 384 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 624, 672 }, - { 624, 672 }, - { 528, 672 }, - { 528, 384 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 648 }, - { 924, 636 }, - { 924, 516 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 792, 672 }, - { 792, 672 }, - { 792, 516 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 792, 672 }, - { 792, 672 }, - { 792, 516 }, - } - }, - }, - }, - { - .sku = 0x3, /* SKU = 3 */ - .process_id = -1, /* any process id */ - .cap_mA = 8000, /* 8A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 588 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 588 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 588 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 588 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 588 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 588 }, - } - }, - }, - }, - /* SKU 4 */ - { - .sku = 0x4, /* SKU = 4 */ - .process_id = -1, /* any process id */ - .cap_mA = 6000, /* 6A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 636 }, - { 924, 624 }, - { 924, 588 }, - { 924, 526 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 792, 672 }, - { 792, 636 }, - { 792, 636 }, - { 792, 576 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 792, 672 }, - { 624, 672 }, - { 624, 672 }, - { 624, 636 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 660 }, - { 924, 636 }, - { 924, 588 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 792, 672 }, - { 792, 672 }, - { 792, 648 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 792, 672 }, - { 792, 672 }, - { 792, 648 }, - } - }, - }, - }, - { - .sku = 0x4, /* SKU = 4 */ - .process_id = -1, /* any process id */ - .cap_mA = 8000, /* 8A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 648 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 648 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 648 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 648 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 924, 672 }, - { 924, 672 }, - { 924, 672 }, - { 924, 648 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 924, 828 }, - { 924, 816 }, - { 924, 804 }, - { 924, 648 }, - } - }, - }, - }, - /* SKU 5 */ - { - .sku = 0x5, /* SKU = 5 */ - .process_id = 0, /* bin 0 */ - .cap_mA = 4000, /* 4A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 336 }, - { 792, 336 }, - { 792, 300 }, - { 792, 240 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 624, 396 }, - { 660, 372 }, - { 660, 324 }, - { 660, 288 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 492 }, - { 408, 396 }, - { 408, 396 }, - { 408, 396 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 432 }, - { 792, 432 }, - { 792, 396 }, - { 792, 348 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 624, 492 }, - { 660, 492 }, - { 660, 444 }, - { 660, 384 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 516 }, - { 408, 516 }, - { 408, 516 }, - { 408, 492 }, - } - }, - }, - }, - { - .sku = 0x5, /* SKU = 5 */ - .process_id = 1, /* bin 1 */ - .cap_mA = 4000, /* 4A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 348 }, - { 792, 336 }, - { 792, 300 }, - { 792, 240 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 624, 420 }, - { 660, 372 }, - { 660, 324 }, - { 660, 288 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 528 }, - { 408, 492 }, - { 408, 420 }, - { 408, 420 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 432 }, - { 792, 432 }, - { 792, 396 }, - { 792, 348 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 624, 528 }, - { 660, 492 }, - { 660, 444 }, - { 660, 384 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 564 }, - { 408, 564 }, - { 408, 528 }, - { 408, 528 }, - } - }, - }, - }, - { - .sku = 0x5, /* SKU = 5 */ - .process_id = -1, /* any process id */ - .cap_mA = 6000, /* 6A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 792, 516 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 660, 600 }, - { 660, 564 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 660, 600 }, - { 528, 600 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 792, 600 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 624, 600 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 624, 600 }, - } - }, - }, - }, - /* SKU 6 */ - { - .sku = 0x6, /* SKU = 6 */ - .process_id = 0, /* bin 0 */ - .cap_mA = 4000, /* 4A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 348 }, - { 792, 348 }, - { 792, 312 }, - { 792, 264 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 660, 372 }, - { 660, 372 }, - { 660, 336 }, - { 660, 300 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 492 }, - { 408, 396 }, - { 408, 396 }, - { 408, 396 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 444 }, - { 792, 444 }, - { 792, 408 }, - { 792, 372 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 660, 492 }, - { 660, 492 }, - { 660, 456 }, - { 660, 408 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 552 }, - { 408, 516 }, - { 408, 516 }, - { 408, 516 }, - } - }, - }, - }, - { - .sku = 0x6, /* SKU = 6 */ - .process_id = 1, /* bin 1 */ - .cap_mA = 4000, /* 4A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 348 }, - { 792, 348 }, - { 792, 312 }, - { 792, 264 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 660, 420 }, - { 660, 372 }, - { 660, 336 }, - { 660, 300 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 528 }, - { 408, 492 }, - { 408, 420 }, - { 408, 420 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 444 }, - { 792, 444 }, - { 792, 408 }, - { 792, 372 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 660, 492 }, - { 660, 492 }, - { 660, 456 }, - { 660, 408 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 408, 564 }, - { 408, 564 }, - { 408, 564 }, - { 408, 528 }, - } - }, - }, - }, - { - .sku = 0x6, /* SKU = 6 */ - .process_id = -1, /* any process id */ - .cap_mA = 6000, /* 6A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 792, 516 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 660, 600 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 660, 600 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 792, 600 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 792, 600 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 792, 600 }, - { 792, 600 }, - { 792, 600 }, - { 792, 600 }, - } - }, - }, - }, - /* SKU 8 */ - { - .sku = 0x8, /* SKU = 8 */ - .process_id = -1, /* any process id */ - .cap_mA = 6000, /* 6A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 636 }, - { 744, 636 }, - { 744, 576 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 636 }, - { 744, 636 }, - { 744, 576 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 624, 672 }, - { 624, 672 }, - { 624, 636 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - } - }, - }, - }, - { - .sku = 0x8, /* SKU = 8 */ - .process_id = -1, /* any process id */ - .cap_mA = 8000, /* 8A cap */ - .mult = 1000000, /* MHZ */ - .cap_scpu_on = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - } - }, - }, - .cap_scpu_off = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 744, 672 }, - { 744, 672 }, - { 744, 672 }, - { 744, 648 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 792, 828 }, - { 792, 816 }, - { 792, 804 }, - { 792, 648 }, - } - }, - }, - }, -}; - -#ifdef CONFIG_TEGRA_EDP_LIMITS -#define LEAKAGE_CONSTS_IJK_COMMON \ - { \ - /* i = 0 */ \ - { { 13919916, -28721837, 7560552, -570495, }, \ - { -39991855, 87294629, -22972570, 1734058, }, \ - { 36869935, -86826110, 22833611, -1723750, }, \ - { -10611796, 28192235, -7407903, 559012, }, \ - }, \ - /* i = 1 */ \ - { { -37335213, 53397584, -16025243, 1341064, }, \ - { 111121782, -160756323, 48421377, -4049609, }, \ - { -107149149, 157911131, -47786861, 3994796, }, \ - { 32802647, -49872380, 15236453, -1268662, }, \ - }, \ - /* i = 2 */ \ - { { 3315214, -21010655, 7718286, -789185, }, \ - { -4336249, 59786076, -22312653, 2313754, }, \ - { -3346058, -54529998, 20777469, -2198700, }, \ - { 4810027, 15417133, -6086955, 665766, }, \ - }, \ - /* i = 3 */ \ - { { 4681958, -1470999, -232691, 73384, }, \ - { -15445149, 5487248, 422447, -201475, }, \ - { 16983482, -6716242, -65917, 174128, }, \ - { -6293336, 2756799, -140100, -44673, }, \ - }, \ - } - -#define LEAKAGE_PARAMS_COMMON_PART \ - .temp_scaled = 10, \ - .dyn_scaled = 1000000, \ - .dyn_consts_n = { 1410000, 2440000, 3450000, 4440000 }, \ - .consts_scaled = 1000000, \ - .leakage_consts_n = { 400000, 650000, 850000, 1050000 }, \ - .ijk_scaled = 10000, \ - .leakage_min = 30, \ - .volt_temp_cap = { 70, 1300 }, \ - .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON - -static struct tegra_edp_cpu_leakage_params t11x_leakage_params[] = { - { - .cpu_speedo_id = 0, /* A01 CPU */ - .max_current_cap = { /* values are from tegra4 datasheet */ - { .max_cur = 9000, .max_temp = 60, - { 1900000, 1900000, 1600000, 1600000 } - }, - { .max_cur = 9000, .max_temp = 75, - { 1900000, 1900000, 1530000, 1530000 } - }, - { .max_cur = 9000, .max_temp = 90, - { 1900000, 1900000, 1500000, 1500000 } - }, - { .max_cur = 12000, .max_temp = 90, - { 1900000, 1900000, 1700000, 1700000 } - }, - { .max_cur = 15000, .max_temp = 90, - { 1900000, 1900000, 1900000, 1900000 } - }, - }, - LEAKAGE_PARAMS_COMMON_PART, - }, - { - .cpu_speedo_id = 1, /* A01P+ CPU */ - .safety_cap = { 1810500, 1810500, 1606500, 1606500 }, - .max_current_cap = { /* values are from tegra4 datasheet */ - { .max_cur = 7500, .max_temp = 90, - { 1800000, 1700000, 1320000, 1320000 } - }, - { .max_cur = 7500, .max_temp = 75, - { 1800000, 1700000, 1420000, 1420000 } - }, - { .max_cur = 7500, .max_temp = 60, - { 1800000, 1800000, 1420000, 1420000 } - }, - { .max_cur = 7500, .max_temp = 45, - { 1800000, 1800000, 1530000, 1530000 } - }, - { .max_cur = 9000, .max_temp = 90, - { 1800000, 1800000, 1500000, 1500000 } - }, - { .max_cur = 9000, .max_temp = 75, - { 1800000, 1800000, 1530000, 1530000 } - }, - { .max_cur = 9000, .max_temp = 60, - { 1800000, 1800000, 1600000, 1600000 } - }, - { .max_cur = 12000, .max_temp = 45, - { 1800000, 1800000, 1600000, 1600000 } - }, - }, - LEAKAGE_PARAMS_COMMON_PART, - }, - { - .cpu_speedo_id = 2, /* A01P+ fast CPU */ - .safety_cap = { 1912500, 1912500, 1912500, 1912500 }, - .max_current_cap = { /* values are from tegra4 datasheet */ - { .max_cur = 9000, .max_temp = 90, - { 1900000, 1900000, 1500000, 1500000 } - }, - { .max_cur = 9000, .max_temp = 75, - { 1900000, 1900000, 1530000, 1530000 } - }, - { .max_cur = 9000, .max_temp = 60, - { 1900000, 1900000, 1600000, 1600000 } - }, - { .max_cur = 12000, .max_temp = 90, - { 1900000, 1900000, 1700000, 1700000 } - }, - { .max_cur = 15000, .max_temp = 90, - { 1900000, 1900000, 1900000, 1900000 } - }, - }, - LEAKAGE_PARAMS_COMMON_PART, - }, - { - .cpu_speedo_id = 3, - .safety_cap = { 1810500, 1810500, 1810500, 1810500 }, - .max_current_cap = { /* fixed values */ - { .max_cur = 9000, .max_temp = 105, - { 1810500, 1810500, 1530000, 1530000 } - }, - { .max_cur = 9000, .max_temp = 90, - { 1810500, 1810500, 1606500, 1606500 } - }, - { .max_cur = 12000, .max_temp = 105, - { 1810500, 1810500, 1708500, 1708500 } - }, - { .max_cur = 15000, .max_temp = 105, - { 1810500, 1810500, 1810500, 1810500 } - }, - }, - LEAKAGE_PARAMS_COMMON_PART, - }, -}; - -struct tegra_edp_cpu_leakage_params *tegra11x_get_leakage_params(int index, - unsigned int *sz) -{ - BUG_ON(index >= ARRAY_SIZE(t11x_leakage_params)); - if (sz) - *sz = ARRAY_SIZE(t11x_leakage_params); - return &t11x_leakage_params[index]; -} -#endif - -static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA) -{ - int i; - int pid = tegra_core_process_id(); - - if ((sku == 0x5) || (sku == 0x6)) { - if (regulator_mA >= 8000) - return NULL; /* no edp limits above 8A */ - } else if ((sku == 0x3) || (sku == 0x4) || (sku == 0x8)) { - if (regulator_mA >= 8000) - regulator_mA = 8000; /* apply 8A table above 8A */ - } else { - return NULL; /* no edp limits at all */ - } - - for (i = 0; i < ARRAY_SIZE(core_edp_table); i++) { - struct core_edp_entry *entry = &core_edp_table[i]; - if ((entry->sku == sku) && (entry->cap_mA == regulator_mA) && - ((entry->process_id == -1) || (entry->process_id == pid))) - return entry; - } - return ERR_PTR(-ENOENT); -} - -static unsigned long clip_cap_rate(struct clk *cap_clk, unsigned long rate) -{ - unsigned long floor, ceiling; - struct clk *p = clk_get_parent(cap_clk); - - if (!p || !p->ops || !p->ops->shared_bus_update) { - WARN(1, "%s: edp cap clk %s is not a shared bus user\n", - __func__, cap_clk->name); - return rate; - } - - /* - * Clip cap rate to shared bus possible rates (going up via shared - * bus * ladder since bus clocks always rounds up with resolution of - * at least 2kHz) - */ - ceiling = clk_round_rate(p, clk_get_min_rate(p)); - do { - floor = ceiling; - ceiling = clk_round_rate(p, floor + 2000); - if (IS_ERR_VALUE(ceiling)) { - pr_err("%s: failed to clip %lu to %s possible rates\n", - __func__, rate, p->name); - return rate; - } - } while ((floor < ceiling) && (ceiling <= rate)); - - if (floor > rate) - WARN(1, "%s: %s cap rate %lu is below %s floor %lu\n", - __func__, cap_clk->name, rate, p->name, floor); - return floor; -} - -int __init tegra11x_select_core_edp_table(unsigned int regulator_mA, - struct tegra_core_edp_limits *limits) -{ - int i; - int sku; - unsigned long *cap_rates; - struct core_edp_entry *edp_entry; - - BUG_ON(ARRAY_SIZE(temperatures) != TEMPERATURE_RANGES); - BUG_ON(ARRAY_SIZE(cap_clks_names) != CAP_CLKS_NUM); - for (i = 0; i < CAP_CLKS_NUM; i++) { - struct clk *c = tegra_get_clock_by_name(cap_clks_names[i]); - if (!c) { - pr_err("%s: failed to find edp cap clock %s\n", - __func__, cap_clks_names[i]); - return -ENODEV; - } - cap_clks[i] = c; - } - - sku = tegra_get_sku_id(); - edp_entry = find_edp_entry(sku, regulator_mA); - if (!edp_entry) { - pr_info("%s: no core edp table for sku %d, %d mA\n", - __func__, sku, regulator_mA); - return -ENODATA; - } else if (IS_ERR(edp_entry)) { - WARN(1, "%s: missing core edp table for sku %d, %d mA\n", - __func__, sku, regulator_mA); - return PTR_ERR(edp_entry); - } - - limits->sku = sku; - limits->cap_clocks = cap_clks; - limits->cap_clocks_num = CAP_CLKS_NUM; - limits->temperatures = temperatures; - limits->temperature_ranges = TEMPERATURE_RANGES; - limits->core_modules_states = CORE_MODULES_STATES; - - cap_rates = &edp_entry->cap_scpu_on[0][0][0][0]; - limits->cap_rates_scpu_on = cap_rates; - for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) { - unsigned long rate = *cap_rates * edp_entry->mult; - *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate); - } - - cap_rates = &edp_entry->cap_scpu_off[0][0][0][0]; - limits->cap_rates_scpu_off = cap_rates; - for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) { - unsigned long rate = *cap_rates * edp_entry->mult; - *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate); - } - - return 0; -} diff --git a/arch/arm/mach-tegra/tegra11_emc.c b/arch/arm/mach-tegra/tegra11_emc.c deleted file mode 100644 index 8557e3148f4c..000000000000 --- a/arch/arm/mach-tegra/tegra11_emc.c +++ /dev/null @@ -1,1722 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11_emc.c - * - * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/module.h> -#include <linux/delay.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/hrtimer.h> -#include <linux/pasr.h> -#include <linux/platform_device.h> -#include <linux/platform_data/tegra_emc_pdata.h> - -#include <asm/cputime.h> - -#include "clock.h" -#include "dvfs.h" -#include "board.h" -#include "iomap.h" -#include "tegra11_emc.h" -#include "tegra_emc_dt_parse.h" - -#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE -static bool emc_enable = true; -#else -static bool emc_enable; -#endif -module_param(emc_enable, bool, 0644); - -static int pasr_enable; - -static u32 bw_calc_freqs[] = { - 40, 60, 80, 100, 120, 140, 160, 180, 200, 220, 240, 260, 280, 300 -}; - -static u32 tegra11_lpddr3_emc_usage_share_default[] = { - 35, 38, 40, 41, 42, 43, 43, 45, 45, 45, 46, 47, 48, 48, 50 -}; - -static u32 tegra11_lpddr3_emc_usage_share_dc[] = { - 47, 52, 55, 57, 58, 59, 60, 62, 62, 63, 64, 66, 67, 68, 70 -}; - -static u8 iso_share_calc_t114_lpddr3_default(unsigned long iso_bw); -static u8 iso_share_calc_t114_lpddr3_dc(unsigned long iso_bw); - -u8 tegra_emc_bw_efficiency = 80; - -static struct emc_iso_usage tegra11_ddr3_emc_iso_usage[] = { - { BIT(EMC_USER_DC1), 80}, - { BIT(EMC_USER_DC2), 80}, - { BIT(EMC_USER_DC1) | BIT(EMC_USER_DC2), 45}, - { BIT(EMC_USER_DC1) | BIT(EMC_USER_VI), 45}, - { BIT(EMC_USER_DC2) | BIT(EMC_USER_VI), 45}, -}; - -static struct emc_iso_usage tegra11_lpddr3_emc_iso_usage[] = { - { - BIT(EMC_USER_DC1), - 80, iso_share_calc_t114_lpddr3_dc - }, - { - BIT(EMC_USER_DC2), - 80, iso_share_calc_t114_lpddr3_dc - }, - { - BIT(EMC_USER_DC1) | BIT(EMC_USER_DC2), - 45, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC1) | BIT(EMC_USER_VI), - 45, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC1) | BIT(EMC_USER_MSENC), - 50, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC1) | BIT(EMC_USER_3D), - 50, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC1) | BIT(EMC_USER_VDE), - 45, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC2) | BIT(EMC_USER_VI), - 45, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC2) | BIT(EMC_USER_MSENC), - 50, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC2) | BIT(EMC_USER_3D), - 50, iso_share_calc_t114_lpddr3_default - }, - { - BIT(EMC_USER_DC2) | BIT(EMC_USER_VDE), - 45, iso_share_calc_t114_lpddr3_default - }, -}; - -#define MHZ 1000000 -#define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM 14 -#define PLL_C_DIRECT_FLOOR 333500000 -#define EMC_STATUS_UPDATE_TIMEOUT 100 -#define TEGRA_EMC_TABLE_MAX_SIZE 16 - -#define TEGRA_EMC_MODE_REG_17 0x00110000 -#define TEGRA_EMC_MRW_DEV_SHIFT 30 -#define TEGRA_EMC_MRW_DEV1 2 -#define TEGRA_EMC_MRW_DEV2 1 - -enum { - DLL_CHANGE_NONE = 0, - DLL_CHANGE_ON, - DLL_CHANGE_OFF, -}; - -#define EMC_CLK_DIV_SHIFT 0 -#define EMC_CLK_DIV_MASK (0xFF << EMC_CLK_DIV_SHIFT) -#define EMC_CLK_SOURCE_SHIFT 29 -#define EMC_CLK_SOURCE_MASK (0x7 << EMC_CLK_SOURCE_SHIFT) -#define EMC_CLK_LOW_JITTER_ENABLE (0x1 << 31) -#define EMC_CLK_MC_SAME_FREQ (0x1 << 16) - -/* FIXME: actual Tegar11 list */ -#define BURST_REG_LIST \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RC), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC_SLR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RAS), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RP), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_R2W), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_W2R), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_R2P), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_W2P), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RD_RCD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WR_RCD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RRD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_REXT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WEXT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV_MASK), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_IBDLY), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM_EXTRA), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CDB_CNTL_2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QRST), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_MASK), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_REFRESH), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_BURST_REFRESH_NUM), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PRE_REFRESH_REQ_CNT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2WR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2RD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PCHG2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ACT2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AR2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RW2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSRDLL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKESR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TPD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TFAW), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TRPAB), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTABLE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTOP), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TREFBW), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE_EXTRA), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_WRITE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_READ), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL_PERIOD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS7), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE7), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS7), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQSPADCTRL2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQPADCTRL2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CLKPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2COMPPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DSR_VTTGEN_DRV), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TXDSRVTTGEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_SPARE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_TERM_CTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_INTERVAL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_WAIT_CNT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_DURATION), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DYN_SELF_REF_CONTROL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CA_TRAINING_TIMING_CNTL1), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CA_TRAINING_TIMING_CNTL2), \ - \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_CFG), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_OUTSTANDING_REQ), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RCD), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RP), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RC), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAS), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_FAW), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RRD), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAP2PRE), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_WAP2PRE), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2R), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2W), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2W), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2R), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_SEL_DPD_CTRL), - -#define BURST_UP_DOWN_REG_LIST \ - DEFINE_REG(TEGRA_MC_BASE, MC_PTSA_GRANT_DECREMENT), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_1), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_2), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_1), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_1), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_3), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_1), - -#define EMC_TRIMMERS_REG_LIST \ - DEFINE_REG(0, EMC_CDB_CNTL_1), \ - DEFINE_REG(0, EMC_FBIO_CFG6), \ - DEFINE_REG(0, EMC_QUSE), \ - DEFINE_REG(0, EMC_EINPUT), \ - DEFINE_REG(0, EMC_EINPUT_DURATION), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQS0), \ - DEFINE_REG(0, EMC_QSAFE), \ - DEFINE_REG(0, EMC_DLL_XFORM_QUSE0), \ - DEFINE_REG(0, EMC_RDV), \ - DEFINE_REG(0, EMC_XM2DQSPADCTRL4), \ - DEFINE_REG(0, EMC_XM2DQSPADCTRL3), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQ0), \ - DEFINE_REG(0, EMC_AUTO_CAL_CONFIG), \ - DEFINE_REG(0, EMC_DLL_XFORM_ADDR0), \ - DEFINE_REG(0, EMC_XM2CLKPADCTRL2), \ - DEFINE_REG(0, EMC_DLI_TRIM_TXDQS0), \ - DEFINE_REG(0, EMC_DLL_XFORM_ADDR1), \ - DEFINE_REG(0, EMC_DLL_XFORM_ADDR2), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQS1), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQS2), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQS3), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQ1), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQ2), \ - DEFINE_REG(0, EMC_DLL_XFORM_DQ3), \ - DEFINE_REG(0, EMC_DLI_TRIM_TXDQS1), \ - DEFINE_REG(0, EMC_DLI_TRIM_TXDQS2), \ - DEFINE_REG(0, EMC_DLI_TRIM_TXDQS3), \ - DEFINE_REG(0, EMC_DLL_XFORM_QUSE1), \ - DEFINE_REG(0, EMC_DLL_XFORM_QUSE2), \ - DEFINE_REG(0, EMC_DLL_XFORM_QUSE3), - - -#define DEFINE_REG(base, reg) ((base) ? (IO_ADDRESS((base)) + (reg)) : 0) -static void __iomem *burst_reg_addr[TEGRA11_EMC_MAX_NUM_REGS] = { - BURST_REG_LIST -}; -#ifndef EMULATE_CLOCK_SWITCH -static void __iomem *burst_up_down_reg_addr[TEGRA11_EMC_MAX_NUM_REGS] = { - BURST_UP_DOWN_REG_LIST -}; -#endif -#undef DEFINE_REG - - -#define DEFINE_REG(base, reg) (reg) -#ifndef EMULATE_CLOCK_SWITCH -static u32 emc_trimmer_offs[TEGRA11_EMC_MAX_NUM_REGS] = { - EMC_TRIMMERS_REG_LIST -}; -#endif -#undef DEFINE_REG - - -#define DEFINE_REG(base, reg) reg##_INDEX -enum { - BURST_REG_LIST -}; -#undef DEFINE_REG - -#define DEFINE_REG(base, reg) reg##_TRIM_INDEX -enum { - EMC_TRIMMERS_REG_LIST -}; -#undef DEFINE_REG - - -struct emc_sel { - struct clk *input; - u32 value; - unsigned long input_rate; -}; -static struct emc_sel tegra_emc_clk_sel[TEGRA_EMC_TABLE_MAX_SIZE]; -static struct tegra11_emc_table start_timing; -static const struct tegra11_emc_table *emc_timing; -static unsigned long dram_over_temp_state = DRAM_OVER_TEMP_NONE; - -static ktime_t clkchange_time; -static int clkchange_delay = 100; - -static const struct tegra11_emc_table *tegra_emc_table; -static int tegra_emc_table_size; - -static u32 dram_dev_num; -static u32 dram_type = -1; - -static struct clk *emc; - -static struct { - cputime64_t time_at_clock[TEGRA_EMC_TABLE_MAX_SIZE]; - int last_sel; - u64 last_update; - u64 clkchange_count; - spinlock_t spinlock; -} emc_stats; - -static DEFINE_SPINLOCK(emc_access_lock); - -static void __iomem *emc_base = IO_ADDRESS(TEGRA_EMC_BASE); -static void __iomem *emc0_base = IO_ADDRESS(TEGRA_EMC0_BASE); -static void __iomem *emc1_base = IO_ADDRESS(TEGRA_EMC1_BASE); -static void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE); -static void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); - -static inline void emc_writel(u32 val, unsigned long addr) -{ - writel(val, emc_base + addr); -} -static inline void emc0_writel(u32 val, unsigned long addr) -{ - writel(val, emc0_base + addr); -} -static inline void emc1_writel(u32 val, unsigned long addr) -{ - writel(val, emc1_base + addr); -} -static inline u32 emc_readl(unsigned long addr) -{ - return readl(emc_base + addr); -} -static inline void mc_writel(u32 val, unsigned long addr) -{ - writel(val, mc_base + addr); -} -static inline u32 mc_readl(unsigned long addr) -{ - return readl(mc_base + addr); -} - -static inline void ccfifo_writel(u32 val, unsigned long addr) -{ - writel(val, emc_base + EMC_CCFIFO_DATA); - writel(addr, emc_base + EMC_CCFIFO_ADDR); -} - -static int last_round_idx; -static inline int get_start_idx(unsigned long rate) -{ - if (tegra_emc_table[last_round_idx].rate == rate) - return last_round_idx; - return 0; -} - -static void emc_last_stats_update(int last_sel) -{ - unsigned long flags; - u64 cur_jiffies = get_jiffies_64(); - - spin_lock_irqsave(&emc_stats.spinlock, flags); - - if (emc_stats.last_sel < TEGRA_EMC_TABLE_MAX_SIZE) - emc_stats.time_at_clock[emc_stats.last_sel] = - emc_stats.time_at_clock[emc_stats.last_sel] + - (cur_jiffies - emc_stats.last_update); - - emc_stats.last_update = cur_jiffies; - - if (last_sel < TEGRA_EMC_TABLE_MAX_SIZE) { - emc_stats.clkchange_count++; - emc_stats.last_sel = last_sel; - } - spin_unlock_irqrestore(&emc_stats.spinlock, flags); -} - -static int wait_for_update(u32 status_reg, u32 bit_mask, bool updated_state) -{ - int i; - for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++) { - if (!!(emc_readl(status_reg) & bit_mask) == updated_state) - return 0; - udelay(1); - } - return -ETIMEDOUT; -} - -static inline void emc_timing_update(void) -{ - int err; - - emc_writel(0x1, EMC_TIMING_CONTROL); - err = wait_for_update(EMC_STATUS, - EMC_STATUS_TIMING_UPDATE_STALLED, false); - if (err) { - pr_err("%s: timing update error: %d", __func__, err); - BUG(); - } -} - -static inline void auto_cal_disable(void) -{ - int err; - - emc_writel(0, EMC_AUTO_CAL_INTERVAL); - err = wait_for_update(EMC_AUTO_CAL_STATUS, - EMC_AUTO_CAL_STATUS_ACTIVE, false); - if (err) { - pr_err("%s: disable auto-cal error: %d", __func__, err); - BUG(); - } -} - -static inline void set_over_temp_timing( - const struct tegra11_emc_table *next_timing, unsigned long state) -{ -#define REFRESH_SPEEDUP(val) \ - do { \ - val = ((val) & 0xFFFF0000) | (((val) & 0xFFFF) >> 2); \ - } while (0) - - u32 ref = next_timing->burst_regs[EMC_REFRESH_INDEX]; - u32 pre_ref = next_timing->burst_regs[EMC_PRE_REFRESH_REQ_CNT_INDEX]; - u32 dsr_cntrl = next_timing->burst_regs[EMC_DYN_SELF_REF_CONTROL_INDEX]; - - switch (state) { - case DRAM_OVER_TEMP_NONE: - break; - case DRAM_OVER_TEMP_REFRESH_X2: - case DRAM_OVER_TEMP_REFRESH_X4: - case DRAM_OVER_TEMP_THROTTLE: - REFRESH_SPEEDUP(ref); - REFRESH_SPEEDUP(pre_ref); - REFRESH_SPEEDUP(dsr_cntrl); - break; - default: - WARN(1, "%s: Failed to set dram over temp state %lu\n", - __func__, state); - return; - } - - __raw_writel(ref, burst_reg_addr[EMC_REFRESH_INDEX]); - __raw_writel(pre_ref, burst_reg_addr[EMC_PRE_REFRESH_REQ_CNT_INDEX]); - __raw_writel(dsr_cntrl, burst_reg_addr[EMC_DYN_SELF_REF_CONTROL_INDEX]); -} - -static inline bool dqs_preset(const struct tegra11_emc_table *next_timing, - const struct tegra11_emc_table *last_timing) -{ - bool ret = false; - -#define DQS_SET(reg, bit) \ - do { \ - if ((next_timing->burst_regs[EMC_##reg##_INDEX] & \ - EMC_##reg##_##bit##_ENABLE) && \ - (!(last_timing->burst_regs[EMC_##reg##_INDEX] & \ - EMC_##reg##_##bit##_ENABLE))) { \ - emc_writel(last_timing->burst_regs[EMC_##reg##_INDEX] \ - | EMC_##reg##_##bit##_ENABLE, EMC_##reg); \ - ret = true; \ - } \ - } while (0) - - -#define DQS_SET_TRIM(reg, bit, ch) \ - do { \ - if ((next_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX] \ - & EMC_##reg##_##bit##_ENABLE) && \ - (!(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX] \ - & EMC_##reg##_##bit##_ENABLE))) { \ - emc##ch##_writel(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX] \ - | EMC_##reg##_##bit##_ENABLE, EMC_##reg); \ - ret = true; \ - } \ - } while (0) - - DQS_SET(XM2DQSPADCTRL2, VREF); - - return ret; -} - -static inline void overwrite_mrs_wait_cnt( - const struct tegra11_emc_table *next_timing, - bool zcal_long) -{ - u32 reg; - u32 cnt = 512; - - /* For ddr3 when DLL is re-started: overwrite EMC DFS table settings - for MRS_WAIT_LONG with maximum of MRS_WAIT_SHORT settings and - expected operation length. Reduce the latter by the overlapping - zq-calibration, if any */ - if (zcal_long) - cnt -= dram_dev_num * 256; - - reg = (next_timing->burst_regs[EMC_MRS_WAIT_CNT_INDEX] & - EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) >> - EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT; - if (cnt < reg) - cnt = reg; - - reg = (next_timing->burst_regs[EMC_MRS_WAIT_CNT_INDEX] & - (~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK)); - reg |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) & - EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; - - emc_writel(reg, EMC_MRS_WAIT_CNT); -} - -static inline int get_dll_change(const struct tegra11_emc_table *next_timing, - const struct tegra11_emc_table *last_timing) -{ - bool next_dll_enabled = !(next_timing->emc_mode_1 & 0x1); - bool last_dll_enabled = !(last_timing->emc_mode_1 & 0x1); - - if (next_dll_enabled == last_dll_enabled) - return DLL_CHANGE_NONE; - else if (next_dll_enabled) - return DLL_CHANGE_ON; - else - return DLL_CHANGE_OFF; -} - -static inline void set_dram_mode(const struct tegra11_emc_table *next_timing, - const struct tegra11_emc_table *last_timing, - int dll_change) -{ - if (dram_type == DRAM_TYPE_DDR3) { - /* first mode_1, then mode_2, then mode_reset*/ - if (next_timing->emc_mode_1 != last_timing->emc_mode_1) - ccfifo_writel(next_timing->emc_mode_1, EMC_EMRS); - if (next_timing->emc_mode_2 != last_timing->emc_mode_2) - ccfifo_writel(next_timing->emc_mode_2, EMC_EMRS2); - - if ((next_timing->emc_mode_reset != - last_timing->emc_mode_reset) || - (dll_change == DLL_CHANGE_ON)) { - u32 reg = next_timing->emc_mode_reset & - (~EMC_MODE_SET_DLL_RESET); - if (dll_change == DLL_CHANGE_ON) { - reg |= EMC_MODE_SET_DLL_RESET; - reg |= EMC_MODE_SET_LONG_CNT; - } - ccfifo_writel(reg, EMC_MRS); - } - } else { - /* first mode_2, then mode_1; mode_reset is not applicable */ - if (next_timing->emc_mode_2 != last_timing->emc_mode_2) - ccfifo_writel(next_timing->emc_mode_2, EMC_MRW2); - if (next_timing->emc_mode_1 != last_timing->emc_mode_1) - ccfifo_writel(next_timing->emc_mode_1, EMC_MRW); - if (next_timing->emc_mode_4 != last_timing->emc_mode_4) - ccfifo_writel(next_timing->emc_mode_4, EMC_MRW4); - } -} - -static inline void do_clock_change(u32 clk_setting) -{ - int err; - - mc_readl(MC_EMEM_ADR_CFG); /* completes prev writes */ - writel(clk_setting, clk_base + emc->reg); - readl(clk_base + emc->reg);/* completes prev write */ - - err = wait_for_update(EMC_INTSTATUS, - EMC_INTSTATUS_CLKCHANGE_COMPLETE, true); - if (err) { - pr_err("%s: clock change completion error: %d", __func__, err); - BUG(); - } -} - -static noinline void emc_set_clock(const struct tegra11_emc_table *next_timing, - const struct tegra11_emc_table *last_timing, - u32 clk_setting) -{ -#ifndef EMULATE_CLOCK_SWITCH - int i, dll_change, pre_wait; - bool dyn_sref_enabled, zcal_long; - - u32 emc_cfg_reg = emc_readl(EMC_CFG); - - dyn_sref_enabled = emc_cfg_reg & EMC_CFG_DYN_SREF_ENABLE; - dll_change = get_dll_change(next_timing, last_timing); - zcal_long = (next_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0) && - (last_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0); - - /* FIXME: remove steps enumeration below? */ - - /* 1. clear clkchange_complete interrupts */ - emc_writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS); - - /* 2. disable dynamic self-refresh and preset dqs vref, then wait for - possible self-refresh entry/exit and/or dqs vref settled - waiting - before the clock change decreases worst case change stall time */ - pre_wait = 0; - if (dyn_sref_enabled) { - emc_cfg_reg &= ~EMC_CFG_DYN_SREF_ENABLE; - emc_writel(emc_cfg_reg, EMC_CFG); - pre_wait = 5; /* 5us+ for self-refresh entry/exit */ - } - - /* 2.5 check dq/dqs vref delay */ - if (dqs_preset(next_timing, last_timing)) { - if (pre_wait < 3) - pre_wait = 3; /* 3us+ for dqs vref settled */ - } - if (pre_wait) { - emc_timing_update(); - udelay(pre_wait); - } - - /* 3. disable auto-cal if vref mode is switching - removed */ - - /* 4. program burst shadow registers */ - for (i = 0; i < next_timing->burst_regs_num; i++) { - if (!burst_reg_addr[i]) - continue; - __raw_writel(next_timing->burst_regs[i], burst_reg_addr[i]); - } - for (i = 0; i < next_timing->emc_trimmers_num; i++) { - __raw_writel(next_timing->emc_trimmers_0[i], - emc0_base + emc_trimmer_offs[i]); - __raw_writel(next_timing->emc_trimmers_1[i], - emc1_base + emc_trimmer_offs[i]); - } - if ((dram_type == DRAM_TYPE_LPDDR2) && - (dram_over_temp_state != DRAM_OVER_TEMP_NONE)) - set_over_temp_timing(next_timing, dram_over_temp_state); - - emc_cfg_reg &= ~EMC_CFG_UPDATE_MASK; - emc_cfg_reg |= next_timing->emc_cfg & EMC_CFG_UPDATE_MASK; - emc_writel(emc_cfg_reg, EMC_CFG); - wmb(); - barrier(); - - /* 4.1 On ddr3 when DLL is re-started predict MRS long wait count and - overwrite DFS table setting */ - if ((dram_type == DRAM_TYPE_DDR3) && (dll_change == DLL_CHANGE_ON)) - overwrite_mrs_wait_cnt(next_timing, zcal_long); - - /* 5.2 disable auto-refresh to save time after clock change */ - ccfifo_writel(EMC_REFCTRL_DISABLE_ALL(dram_dev_num), EMC_REFCTRL); - - /* 6. turn Off dll and enter self-refresh on DDR3 */ - if (dram_type == DRAM_TYPE_DDR3) { - if (dll_change == DLL_CHANGE_OFF) - ccfifo_writel(next_timing->emc_mode_1, EMC_EMRS); - ccfifo_writel(DRAM_BROADCAST(dram_dev_num) | - EMC_SELF_REF_CMD_ENABLED, EMC_SELF_REF); - } - - /* 7. flow control marker 2 */ - ccfifo_writel(1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); - - /* 8. exit self-refresh on DDR3 */ - if (dram_type == DRAM_TYPE_DDR3) - ccfifo_writel(DRAM_BROADCAST(dram_dev_num), EMC_SELF_REF); - - /* 8.1 re-enable auto-refresh */ - ccfifo_writel(EMC_REFCTRL_ENABLE_ALL(dram_dev_num), EMC_REFCTRL); - - /* 9. set dram mode registers */ - set_dram_mode(next_timing, last_timing, dll_change); - - /* 10. issue zcal command if turning zcal On */ - if (zcal_long) { - ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); - if (dram_dev_num > 1) - ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV1, EMC_ZQ_CAL); - } - - /* 10.1 dummy write to RO register to remove stall after change */ - ccfifo_writel(0, EMC_CCFIFO_STATUS); - - /* 11.5 program burst_up_down registers if emc rate is going down */ - if (next_timing->rate < last_timing->rate) { - for (i = 0; i < next_timing->burst_up_down_regs_num; i++) - __raw_writel(next_timing->burst_up_down_regs[i], - burst_up_down_reg_addr[i]); - wmb(); - } - - /* 12-14. read any MC register to ensure the programming is done - change EMC clock source register wait for clk change completion */ - do_clock_change(clk_setting); - - /* 14.1 re-enable auto-refresh - moved to ccfifo in 8.1 */ - - /* 14.2 program burst_up_down registers if emc rate is going up */ - if (next_timing->rate > last_timing->rate) { - for (i = 0; i < next_timing->burst_up_down_regs_num; i++) - __raw_writel(next_timing->burst_up_down_regs[i], - burst_up_down_reg_addr[i]); - wmb(); - } - - /* 15. set auto-cal interval */ - if (next_timing->rev >= 0x42) - emc_writel(next_timing->emc_acal_interval, - EMC_AUTO_CAL_INTERVAL); - - /* 16. restore dynamic self-refresh */ - if (next_timing->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { - emc_cfg_reg |= EMC_CFG_DYN_SREF_ENABLE; - emc_writel(emc_cfg_reg, EMC_CFG); - } - - /* 17. set zcal wait count */ - emc_writel(next_timing->emc_zcal_cnt_long, EMC_ZCAL_WAIT_CNT); - - /* 18. update restored timing */ - udelay(2); - emc_timing_update(); -#else - /* FIXME: implement */ - pr_info("tegra11_emc: Configuring EMC rate %lu (setting: 0x%x)\n", - next_timing->rate, clk_setting); -#endif -} - -static inline void emc_get_timing(struct tegra11_emc_table *timing) -{ - int i; - - /* burst and trimmers updates depends on previous state; burst_up_down - are stateless */ - for (i = 0; i < timing->burst_regs_num; i++) { - if (burst_reg_addr[i]) - timing->burst_regs[i] = __raw_readl(burst_reg_addr[i]); - else - timing->burst_regs[i] = 0; - } - for (i = 0; i < timing->emc_trimmers_num; i++) { - timing->emc_trimmers_0[i] = - __raw_readl(emc0_base + emc_trimmer_offs[i]); - timing->emc_trimmers_1[i] = - __raw_readl(emc1_base + emc_trimmer_offs[i]); - } - timing->emc_acal_interval = 0; - timing->emc_zcal_cnt_long = 0; - timing->emc_mode_reset = 0; - timing->emc_mode_1 = 0; - timing->emc_mode_2 = 0; - timing->emc_mode_4 = 0; - timing->emc_cfg = emc_readl(EMC_CFG); - timing->rate = clk_get_rate_locked(emc) / 1000; -} - -/* The EMC registers have shadow registers. When the EMC clock is updated - * in the clock controller, the shadow registers are copied to the active - * registers, allowing glitchless memory bus frequency changes. - * This function updates the shadow registers for a new clock frequency, - * and relies on the clock lock on the emc clock to avoid races between - * multiple frequency changes. In addition access lock prevents concurrent - * access to EMC registers from reading MRR registers */ -int tegra_emc_set_rate(unsigned long rate) -{ - int i; - u32 clk_setting; - const struct tegra11_emc_table *last_timing; - unsigned long flags; - s64 last_change_delay; - - if (!tegra_emc_table) - return -EINVAL; - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; /* invalid entry */ - - if (tegra_emc_table[i].rate == rate) - break; - } - - if (i >= tegra_emc_table_size) - return -EINVAL; - - if (!emc_timing) { - /* can not assume that boot timing matches dfs table even - if boot frequency matches one of the table nodes */ - emc_get_timing(&start_timing); - last_timing = &start_timing; - } - else - last_timing = emc_timing; - - clk_setting = tegra_emc_clk_sel[i].value; - - last_change_delay = ktime_us_delta(ktime_get(), clkchange_time); - if ((last_change_delay >= 0) && (last_change_delay < clkchange_delay)) - udelay(clkchange_delay - (int)last_change_delay); - - spin_lock_irqsave(&emc_access_lock, flags); - emc_set_clock(&tegra_emc_table[i], last_timing, clk_setting); - clkchange_time = ktime_get(); - emc_timing = &tegra_emc_table[i]; - spin_unlock_irqrestore(&emc_access_lock, flags); - - emc_last_stats_update(i); - - pr_debug("%s: rate %lu setting 0x%x\n", __func__, rate, clk_setting); - - return 0; -} - -long tegra_emc_round_rate_updown(unsigned long rate, bool up) -{ - int i; - unsigned long table_rate; - - if (!tegra_emc_table) - return clk_get_rate_locked(emc); /* no table - no rate change */ - - if (!emc_enable) - return -EINVAL; - - pr_debug("%s: %lu\n", __func__, rate); - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; /* invalid entry */ - - table_rate = tegra_emc_table[i].rate; - if (table_rate >= rate) { - if (!up && i && (table_rate > rate)) { - i--; - table_rate = tegra_emc_table[i].rate; - } - pr_debug("%s: using %lu\n", __func__, table_rate); - last_round_idx = i; - return table_rate * 1000; - } - } - - return -EINVAL; -} - -struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value) -{ - int i; - - if (!tegra_emc_table) { - if (rate == clk_get_rate_locked(emc)) { - *div_value = emc->div - 2; - return emc->parent; - } - return NULL; - } - - pr_debug("%s: %lu\n", __func__, rate); - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_table[i].rate == rate) { - struct clk *p = tegra_emc_clk_sel[i].input; - - if (p && (tegra_emc_clk_sel[i].input_rate == - clk_get_rate(p))) { - *div_value = (tegra_emc_clk_sel[i].value & - EMC_CLK_DIV_MASK) >> EMC_CLK_DIV_SHIFT; - return p; - } - } - } - return NULL; -} - -bool tegra_emc_is_parent_ready(unsigned long rate, struct clk **parent, - unsigned long *parent_rate, unsigned long *backup_rate) -{ - - int i; - struct clk *p = NULL; - unsigned long p_rate = 0; - - if (!tegra_emc_table) - return true; - - pr_debug("%s: %lu\n", __func__, rate); - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_table[i].rate == rate) { - p = tegra_emc_clk_sel[i].input; - if (!p) - continue; /* invalid entry */ - - p_rate = tegra_emc_clk_sel[i].input_rate; - if (p_rate == clk_get_rate(p)) - return true; - break; - } - } - - /* Table match not found - "non existing parent" is ready */ - if (!p) - return true; - -#ifdef CONFIG_TEGRA_PLLM_SCALED - /* - * Table match found, but parent is not ready - check if backup entry - * was found during initialization, and return the respective backup - * rate - */ - if (emc->shared_bus_backup.input && - (emc->shared_bus_backup.input != p)) { - *parent = p; - *parent_rate = p_rate; - *backup_rate = emc->shared_bus_backup.bus_rate; - return false; - } -#else - /* - * Table match found, but parent is not ready - continue search - * for backup rate: min rate above requested that has different - * parent source (since only pll_c is scaled and may not be ready, - * any other parent can provide backup) - */ - *parent = p; - *parent_rate = p_rate; - - for (i++; i < tegra_emc_table_size; i++) { - p = tegra_emc_clk_sel[i].input; - if (!p) - continue; /* invalid entry */ - - if (p != (*parent)) { - *backup_rate = tegra_emc_table[i].rate * 1000; - return false; - } - } -#endif - /* Parent is not ready, and no backup found */ - *backup_rate = -EINVAL; - return false; -} - -static inline const struct clk_mux_sel *get_emc_input(u32 val) -{ - const struct clk_mux_sel *sel; - - for (sel = emc->inputs; sel->input != NULL; sel++) { - if (sel->value == val) - break; - } - return sel; -} - -static int find_matching_input(const struct tegra11_emc_table *table, - struct clk *pll_c, struct emc_sel *emc_clk_sel) -{ - u32 div_value = (table->src_sel_reg & EMC_CLK_DIV_MASK) >> - EMC_CLK_DIV_SHIFT; - u32 src_value = (table->src_sel_reg & EMC_CLK_SOURCE_MASK) >> - EMC_CLK_SOURCE_SHIFT; - unsigned long input_rate = 0; - unsigned long table_rate = table->rate * 1000; /* table rate in kHz */ - const struct clk_mux_sel *sel = get_emc_input(src_value); - -#ifdef CONFIG_TEGRA_PLLM_SCALED - struct clk *scalable_pll = emc->parent; /* pll_m is a boot parent */ -#else - struct clk *scalable_pll = pll_c; -#endif - pr_info_once("tegra: %s is selected as scalable EMC clock source\n", - scalable_pll->name); - - if (div_value & 0x1) { - pr_warn("tegra: invalid odd divider for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - if (!sel->input) { - pr_warn("tegra: no matching input found for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - if (div_value && (table->src_sel_reg & EMC_CLK_LOW_JITTER_ENABLE)) { - pr_warn("tegra: invalid LJ path for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - if (!(table->src_sel_reg & EMC_CLK_MC_SAME_FREQ) != - !(MC_EMEM_ARB_MISC0_EMC_SAME_FREQ & - table->burst_regs[MC_EMEM_ARB_MISC0_INDEX])) { - pr_warn("tegra: ambiguous EMC to MC ratio for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - -#ifndef CONFIG_TEGRA_DUAL_CBUS - if (sel->input == pll_c) { - pr_warn("tegra: %s is cbus source: no EMC rate %lu support\n", - sel->input->name, table_rate); - return -EINVAL; - } -#endif - - if (sel->input == scalable_pll) { - input_rate = table_rate * (1 + div_value / 2); - } else { - /* all other sources are fixed, must exactly match the rate */ - input_rate = clk_get_rate(sel->input); - if (input_rate != (table_rate * (1 + div_value / 2))) { - pr_warn("tegra: EMC rate %lu does not match %s rate %lu\n", - table_rate, sel->input->name, input_rate); - return -EINVAL; - } - } - -#ifdef CONFIG_TEGRA_PLLM_SCALED - if (sel->input == pll_c) { - /* maybe overwritten in a loop - end up at max rate - from pll_c */ - emc->shared_bus_backup.input = pll_c; - emc->shared_bus_backup.bus_rate = table_rate; - } -#endif - /* Get ready emc clock selection settings for this table rate */ - emc_clk_sel->input = sel->input; - emc_clk_sel->input_rate = input_rate; - emc_clk_sel->value = table->src_sel_reg; - - return 0; -} - -static void adjust_emc_dvfs_table(const struct tegra11_emc_table *table, - int table_size) -{ - int i, j; - unsigned long rate; - - for (i = 0; i < MAX_DVFS_FREQS; i++) { - int mv = emc->dvfs->millivolts[i]; - if (!mv) - break; - - /* For each dvfs voltage find maximum supported rate; - use 1MHz placeholder if not found */ - for (rate = 1000, j = 0; j < table_size; j++) { - if (tegra_emc_clk_sel[j].input == NULL) - continue; /* invalid entry */ - - if ((mv >= table[j].emc_min_mv) && - (rate < table[j].rate)) - rate = table[j].rate; - } - /* Table entries specify rate in kHz */ - emc->dvfs->freqs[i] = rate * 1000; - } -} - -#ifdef CONFIG_TEGRA_PLLM_SCALED -/* When pll_m is scaled, pll_c must provide backup rate; - if not - remove rates that require pll_m scaling */ -static int purge_emc_table(unsigned long max_rate) -{ - int i; - int ret = 0; - - if (emc->shared_bus_backup.input) - return ret; - - pr_warn("tegra: selected pll_m scaling option but no backup source:\n"); - pr_warn(" removed not supported entries from the table:\n"); - - /* made all entries with non matching rate invalid */ - for (i = 0; i < tegra_emc_table_size; i++) { - struct emc_sel *sel = &tegra_emc_clk_sel[i]; - if (sel->input) { - if (clk_get_rate(sel->input) != sel->input_rate) { - pr_warn(" EMC rate %lu\n", - tegra_emc_table[i].rate * 1000); - sel->input = NULL; - sel->input_rate = 0; - sel->value = 0; - if (max_rate == tegra_emc_table[i].rate) - ret = -EINVAL; - } - } - } - return ret; -} -#else -/* When pll_m is fixed @ max EMC rate, it always provides backup for pll_c */ -#define purge_emc_table(max_rate) (0) -#endif - -static int init_emc_table(const struct tegra11_emc_table *table, int table_size) -{ - int i, mv; - u32 reg; - bool max_entry = false; - bool emc_max_dvfs_sel = get_emc_max_dvfs(); - unsigned long boot_rate, max_rate; - struct clk *pll_c = tegra_get_clock_by_name("pll_c"); - - emc_stats.clkchange_count = 0; - spin_lock_init(&emc_stats.spinlock); - emc_stats.last_update = get_jiffies_64(); - emc_stats.last_sel = TEGRA_EMC_TABLE_MAX_SIZE; - - if ((dram_type != DRAM_TYPE_DDR3) && (dram_type != DRAM_TYPE_LPDDR2)) { - pr_err("tegra: not supported DRAM type %u\n", dram_type); - return -ENODATA; - } - - if (emc->parent != tegra_get_clock_by_name("pll_m")) { - pr_err("tegra: boot parent %s is not supported by EMC DFS\n", - emc->parent->name); - return -ENODATA; - } - - if (!table || !table_size) { - pr_err("tegra: EMC DFS table is empty\n"); - return -ENODATA; - } - - boot_rate = clk_get_rate(emc) / 1000; - max_rate = clk_get_rate(emc->parent) / 1000; - - tegra_emc_table_size = min(table_size, TEGRA_EMC_TABLE_MAX_SIZE); - switch (table[0].rev) { - case 0x40: - case 0x41: - case 0x42: - start_timing.burst_regs_num = table[0].burst_regs_num; - start_timing.emc_trimmers_num = table[0].emc_trimmers_num; - break; - default: - pr_err("tegra: invalid EMC DFS table: unknown rev 0x%x\n", - table[0].rev); - return -ENODATA; - } - - /* Match EMC source/divider settings with table entries */ - for (i = 0; i < tegra_emc_table_size; i++) { - unsigned long table_rate = table[i].rate; - - /* Skip "no-rate" entry, or entry violating ascending order */ - if (!table_rate || - (i && (table_rate <= table[i-1].rate))) - continue; - - BUG_ON(table[i].rev != table[0].rev); - - if (find_matching_input(&table[i], pll_c, - &tegra_emc_clk_sel[i])) - continue; - - if (table_rate == boot_rate) - emc_stats.last_sel = i; - - if (emc_max_dvfs_sel) { - /* EMC max rate = max table entry above boot pll_m */ - if (table_rate >= max_rate) { - max_rate = table_rate; - max_entry = true; - } - } else if (table_rate == max_rate) { - /* EMC max rate = boot pll_m rate */ - max_entry = true; - break; - } - } - - /* Validate EMC rate and voltage limits */ - if (!max_entry) { - pr_err("tegra: invalid EMC DFS table: entry for max rate" - " %lu kHz is not found\n", max_rate); - return -ENODATA; - } - - tegra_emc_table = table; - - /* - * Purge rates that cannot be reached because table does not specify - * proper backup source. If maximum rate was purged, fall back on boot - * pll_m rate as maximum limit. In any case propagate new maximum limit - * down stream to shared users, and check it against nominal voltage. - */ - if (purge_emc_table(max_rate)) - max_rate = clk_get_rate(emc->parent) / 1000; - tegra_init_max_rate(emc, max_rate * 1000); - - if (emc->dvfs) { - adjust_emc_dvfs_table(tegra_emc_table, tegra_emc_table_size); - mv = tegra_dvfs_predict_peak_millivolts(emc, max_rate * 1000); - if ((mv <= 0) || (mv > emc->dvfs->max_millivolts)) { - tegra_emc_table = NULL; - pr_err("tegra: invalid EMC DFS table: maximum rate %lu" - " kHz does not match nominal voltage %d\n", - max_rate, emc->dvfs->max_millivolts); - return -ENODATA; - } - } - - pr_info("tegra: validated EMC DFS table\n"); - - /* Configure clock change mode according to dram type */ - reg = emc_readl(EMC_CFG_2) & (~EMC_CFG_2_MODE_MASK); - reg |= ((dram_type == DRAM_TYPE_LPDDR2) ? EMC_CFG_2_PD_MODE : - EMC_CFG_2_SREF_MODE) << EMC_CFG_2_MODE_SHIFT; - emc_writel(reg, EMC_CFG_2); - return 0; -} - -#ifdef CONFIG_PASR -/* Check if the attached memory device uses LPDDR3 protocol. - * Bit 8 (enable LPDDR3 write preamble toggle) of EMC_FBIO_SPARE is enabled - * for LPDDR3. - */ -static bool tegra11_is_lpddr3(void) -{ - return emc_readl(EMC_FBIO_SPARE) & BIT(8); -} - -static void tegra11_pasr_apply_mask(u16 *mem_reg, void *cookie) -{ - u32 val = 0; - int device = (int)cookie; - - val = TEGRA_EMC_MODE_REG_17 | *mem_reg; - val |= device << TEGRA_EMC_MRW_DEV_SHIFT; - - emc0_writel(val, EMC_MRW); - emc1_writel(val, EMC_MRW); - - pr_debug("%s: cookie = %d mem_reg = 0x%04x val = 0x%08x\n", __func__, - (int)cookie, *mem_reg, val); -} - -static int tegra11_pasr_enable(const char *arg, const struct kernel_param *kp) -{ - unsigned int old_pasr_enable; - void *cookie; - u16 mem_reg; - - if (!tegra11_is_lpddr3()) - return -ENOSYS; - - old_pasr_enable = pasr_enable; - param_set_int(arg, kp); - - if (old_pasr_enable == pasr_enable) - return 0; - - /* Cookie represents the device number to write to MRW register. - * 0x2 to for only dev0, 0x1 for dev1. - */ - if (pasr_enable == 0) { - mem_reg = 0; - - cookie = (void *)(int)TEGRA_EMC_MRW_DEV1; - if (!pasr_register_mask_function(TEGRA_DRAM_BASE, - NULL, cookie)) - tegra11_pasr_apply_mask(&mem_reg, cookie); - - cookie = (void *)(int)TEGRA_EMC_MRW_DEV2; - if (!pasr_register_mask_function(TEGRA_DRAM_BASE + SZ_1G, - NULL, cookie)) - tegra11_pasr_apply_mask(&mem_reg, cookie); - } else { - cookie = (void *)(int)2; - pasr_register_mask_function(0x80000000, - &tegra11_pasr_apply_mask, cookie); - - cookie = (void *)(int)1; - pasr_register_mask_function(0xC0000000, - &tegra11_pasr_apply_mask, cookie); - } - - return 0; -} - -static struct kernel_param_ops tegra11_pasr_enable_ops = { - .set = tegra11_pasr_enable, - .get = param_get_int, -}; -module_param_cb(pasr_enable, &tegra11_pasr_enable_ops, &pasr_enable, 0644); -#endif - -static int tegra11_emc_probe(struct platform_device *pdev) -{ - struct tegra11_emc_pdata *pdata; - struct resource *res; - - pasr_enable = 0; - - if (tegra_emc_table) - return -EINVAL; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "missing register base\n"); - return -ENOMEM; - } - - pdata = pdev->dev.platform_data; - - if (!pdata) - pdata = tegra_emc_dt_parse_pdata(pdev); - - if (!pdata) { - dev_err(&pdev->dev, "missing platform data\n"); - return -ENODATA; - } - - return init_emc_table(pdata->tables, pdata->num_tables); -} - -static struct of_device_id tegra11_emc_of_match[] = { - { .compatible = "nvidia,tegra11-emc", }, - { }, -}; - -static struct platform_driver tegra11_emc_driver = { - .driver = { - .name = "tegra-emc", - .owner = THIS_MODULE, - .of_match_table = tegra11_emc_of_match, - }, - .probe = tegra11_emc_probe, -}; - -int __init tegra11_emc_init(void) -{ - int ret = platform_driver_register(&tegra11_emc_driver); - if (!ret) { - if (dram_type == DRAM_TYPE_LPDDR2) - tegra_emc_iso_usage_table_init( - tegra11_lpddr3_emc_iso_usage, - ARRAY_SIZE(tegra11_lpddr3_emc_iso_usage)); - else if (dram_type == DRAM_TYPE_DDR3) - tegra_emc_iso_usage_table_init( - tegra11_ddr3_emc_iso_usage, - ARRAY_SIZE(tegra11_ddr3_emc_iso_usage)); - if (emc_enable) { - unsigned long rate = tegra_emc_round_rate_updown( - emc->boot_rate, false); - if (!IS_ERR_VALUE(rate)) - tegra_clk_preset_emc_monitor(rate); - } - } - return ret; -} - -void tegra_emc_timing_invalidate(void) -{ - emc_timing = NULL; -} - -void tegra_emc_dram_type_init(struct clk *c) -{ - emc = c; - - dram_type = (emc_readl(EMC_FBIO_CFG5) & - EMC_CFG5_TYPE_MASK) >> EMC_CFG5_TYPE_SHIFT; - - dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */ -} - -int tegra_emc_get_dram_type(void) -{ - return dram_type; -} - -static int emc_read_mrr(int dev, int addr) -{ - int ret; - u32 val; - - if (dram_type != DRAM_TYPE_LPDDR2) - return -ENODEV; - - ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, false); - if (ret) - return ret; - - val = dev ? DRAM_DEV_SEL_1 : DRAM_DEV_SEL_0; - val |= (addr << EMC_MRR_MA_SHIFT) & EMC_MRR_MA_MASK; - emc_writel(val, EMC_MRR); - - ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, true); - if (ret) - return ret; - - val = emc_readl(EMC_MRR) & EMC_MRR_DATA_MASK; - return val; -} - -int tegra_emc_get_dram_temperature(void) -{ - int mr4; - unsigned long flags; - - spin_lock_irqsave(&emc_access_lock, flags); - - mr4 = emc_read_mrr(0, 4); - if (IS_ERR_VALUE(mr4)) { - spin_unlock_irqrestore(&emc_access_lock, flags); - return mr4; - } - spin_unlock_irqrestore(&emc_access_lock, flags); - - mr4 = (mr4 & LPDDR2_MR4_TEMP_MASK) >> LPDDR2_MR4_TEMP_SHIFT; - return mr4; -} - -int tegra_emc_set_over_temp_state(unsigned long state) -{ - unsigned long flags; - - if (dram_type != DRAM_TYPE_LPDDR2) - return -ENODEV; - - if (state > DRAM_OVER_TEMP_THROTTLE) - return -EINVAL; - - spin_lock_irqsave(&emc_access_lock, flags); - - /* Update refresh timing if state changed */ - if (emc_timing && (dram_over_temp_state != state)) { - set_over_temp_timing(emc_timing, state); - emc_timing_update(); - if (state != DRAM_OVER_TEMP_NONE) - emc_writel(EMC_REF_FORCE_CMD, EMC_REF); - dram_over_temp_state = state; - } - spin_unlock_irqrestore(&emc_access_lock, flags); - return 0; -} - -static inline int bw_calc_get_freq_idx(unsigned long bw) -{ - int idx = 0; - - if (bw > bw_calc_freqs[TEGRA_EMC_ISO_USE_FREQ_MAX_NUM-1] * MHZ) - idx = TEGRA_EMC_ISO_USE_FREQ_MAX_NUM; - - for (; idx < TEGRA_EMC_ISO_USE_FREQ_MAX_NUM; idx++) { - u32 freq = bw_calc_freqs[idx] * MHZ; - if (bw < freq) { - if (idx) - idx--; - break; - } else if (bw == freq) - break; - } - - return idx; -} - -static u8 iso_share_calc_t114_lpddr3_default(unsigned long iso_bw) -{ - int freq_idx = bw_calc_get_freq_idx(iso_bw); - return tegra11_lpddr3_emc_usage_share_default[freq_idx]; -} - -static u8 iso_share_calc_t114_lpddr3_dc(unsigned long iso_bw) -{ - int freq_idx = bw_calc_get_freq_idx(iso_bw); - return tegra11_lpddr3_emc_usage_share_dc[freq_idx]; -} - -#ifdef CONFIG_DEBUG_FS - -static struct dentry *emc_debugfs_root; - -#define INFO_CALC_REV_OFFSET 1 -#define INFO_SCRIPT_REV_OFFSET 2 -#define INFO_FREQ_OFFSET 3 - -static int emc_table_info_show(struct seq_file *s, void *data) -{ - int i; - const u32 *info; - u32 freq, calc_rev, script_rev; - const struct tegra11_emc_table *entry; - bool found = false; - - if (!tegra_emc_table) { - seq_printf(s, "EMC DFS table is not installed\n"); - return 0; - } - - for (i = 0; i < tegra_emc_table_size; i++) { - entry = &tegra_emc_table[i]; - info = - &entry->burst_up_down_regs[entry->burst_up_down_regs_num]; - - seq_printf(s, "%s: ", tegra_emc_clk_sel[i].input != NULL ? - "accepted" : "rejected"); - - /* system validation tag for metadata */ - if (*info != 0x4E564441) { - seq_printf(s, "emc dvfs frequency %6lu\n", entry->rate); - continue; - } - - found = true; - - calc_rev = *(info + INFO_CALC_REV_OFFSET); - script_rev = *(info + INFO_SCRIPT_REV_OFFSET); - freq = *(info + INFO_FREQ_OFFSET); - - seq_printf(s, "emc dvfs frequency %6u: ", freq); - seq_printf(s, "calc_rev: %02u.%02u.%02u.%02u ", - (calc_rev >> 24) & 0xff, - (calc_rev >> 16) & 0xff, - (calc_rev >> 8) & 0xff, - (calc_rev >> 0) & 0xff); - seq_printf(s, "script_rev: %02u.%02u.%02u.%02u\n", - (script_rev >> 24) & 0xff, - (script_rev >> 16) & 0xff, - (script_rev >> 8) & 0xff, - (script_rev >> 0) & 0xff); - } - - if (!found) - seq_printf(s, "no metdata in EMC DFS table\n"); - - return 0; -} - -static int emc_table_info_open(struct inode *inode, struct file *file) -{ - return single_open(file, emc_table_info_show, inode->i_private); -} - -static const struct file_operations emc_table_info_fops = { - .open = emc_table_info_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int emc_stats_show(struct seq_file *s, void *data) -{ - int i; - - emc_last_stats_update(TEGRA_EMC_TABLE_MAX_SIZE); - - seq_printf(s, "%-10s %-10s \n", "rate kHz", "time"); - for (i = 0; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; /* invalid entry */ - - seq_printf(s, "%-10lu %-10llu \n", tegra_emc_table[i].rate, - cputime64_to_clock_t(emc_stats.time_at_clock[i])); - } - seq_printf(s, "%-15s %llu\n", "transitions:", - emc_stats.clkchange_count); - seq_printf(s, "%-15s %llu\n", "time-stamp:", - cputime64_to_clock_t(emc_stats.last_update)); - - return 0; -} - -static int emc_stats_open(struct inode *inode, struct file *file) -{ - return single_open(file, emc_stats_show, inode->i_private); -} - -static const struct file_operations emc_stats_fops = { - .open = emc_stats_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int dram_temperature_get(void *data, u64 *val) -{ - *val = tegra_emc_get_dram_temperature(); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(dram_temperature_fops, dram_temperature_get, - NULL, "%lld\n"); - -static int over_temp_state_get(void *data, u64 *val) -{ - *val = dram_over_temp_state; - return 0; -} -static int over_temp_state_set(void *data, u64 val) -{ - tegra_emc_set_over_temp_state(val); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(over_temp_state_fops, over_temp_state_get, - over_temp_state_set, "%llu\n"); - -static int efficiency_get(void *data, u64 *val) -{ - *val = tegra_emc_bw_efficiency; - return 0; -} -static int efficiency_set(void *data, u64 val) -{ - tegra_emc_bw_efficiency = (val > 100) ? 100 : val; - if (emc) - tegra_clk_shared_bus_update(emc); - - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(efficiency_fops, efficiency_get, - efficiency_set, "%llu\n"); - -static int __init tegra_emc_debug_init(void) -{ - emc_debugfs_root = debugfs_create_dir("tegra_emc", NULL); - if (!emc_debugfs_root) - return -ENOMEM; - - if (!debugfs_create_file( - "table_info", S_IRUGO, emc_debugfs_root, NULL, - &emc_table_info_fops)) - goto err_out; - - if (!tegra_emc_table) - return 0; - - if (!debugfs_create_file( - "stats", S_IRUGO, emc_debugfs_root, NULL, &emc_stats_fops)) - goto err_out; - - if (!debugfs_create_u32("clkchange_delay", S_IRUGO | S_IWUSR, - emc_debugfs_root, (u32 *)&clkchange_delay)) - goto err_out; - - if (!debugfs_create_file("dram_temperature", S_IRUGO, emc_debugfs_root, - NULL, &dram_temperature_fops)) - goto err_out; - - if (!debugfs_create_file("over_temp_state", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &over_temp_state_fops)) - goto err_out; - - if (!debugfs_create_file("efficiency", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &efficiency_fops)) - goto err_out; - - if (tegra_emc_iso_usage_debugfs_init(emc_debugfs_root)) - goto err_out; - - return 0; - -err_out: - debugfs_remove_recursive(emc_debugfs_root); - return -ENOMEM; -} - -late_initcall(tegra_emc_debug_init); -#endif diff --git a/arch/arm/mach-tegra/tegra11_emc.h b/arch/arm/mach-tegra/tegra11_emc.h deleted file mode 100644 index 244ac5fc414c..000000000000 --- a/arch/arm/mach-tegra/tegra11_emc.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11_emc.h - * - * Copyright (C) 2011-2014 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_TEGRA11_EMC_H -#define _MACH_TEGRA_TEGRA11_EMC_H - -#include <mach/tegra_emc.h> - -int tegra11_emc_init(void); - -enum { - DRAM_DEV_SEL_ALL = 0, - DRAM_DEV_SEL_0 = (2 << 30), - DRAM_DEV_SEL_1 = (1 << 30), -}; -#define DRAM_BROADCAST(num) \ - (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) - -#define EMC_INTSTATUS 0x0 -#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4) - -#define EMC_DBG 0x8 -#define EMC_DBG_WRITE_MUX_ACTIVE (0x1 << 1) - -#define EMC_CFG 0xc -#define EMC_CFG_DRAM_ACPD (0x1 << 29) -#define EMC_CFG_DYN_SREF_ENABLE (0x1 << 28) -#define EMC_CFG_PWR_MASK (0xF << 28) -#define EMC_CFG_PERIODIC_QRST (0x1 << 21) -#define EMC_CFG_EN_DYNAMIC_PUTERM (0x1 << 20) -#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (0x1 << 19) -#define EMC_CFG_DSR_VTTGEN_DRV_EN (0x1 << 18) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (0x1 << 1) -#define EMC_CFG_UPDATE_MASK \ - (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE | \ - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 | \ - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 | \ - EMC_CFG_DSR_VTTGEN_DRV_EN | \ - EMC_CFG_DLY_WR_DQ_HALF_CLOCK | \ - EMC_CFG_EN_DYNAMIC_PUTERM | \ - EMC_CFG_PERIODIC_QRST | \ - EMC_CFG_DRAM_ACPD) - -#define EMC_REFCTRL 0x20 -#define EMC_REFCTRL_DEV_SEL_SHIFT 0 -#define EMC_REFCTRL_DEV_SEL_MASK \ - (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT) -#define EMC_REFCTRL_ENABLE (0x1 << 31) -#define EMC_REFCTRL_ENABLE_ALL(num) \ - (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \ - | EMC_REFCTRL_ENABLE) -#define EMC_REFCTRL_DISABLE_ALL(num) \ - ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) - -#define EMC_TIMING_CONTROL 0x28 -#define EMC_RC 0x2c -#define EMC_RFC 0x30 -#define EMC_RAS 0x34 -#define EMC_RP 0x38 -#define EMC_R2W 0x3c -#define EMC_W2R 0x40 -#define EMC_R2P 0x44 -#define EMC_W2P 0x48 -#define EMC_RD_RCD 0x4c -#define EMC_WR_RCD 0x50 -#define EMC_RRD 0x54 -#define EMC_REXT 0x58 -#define EMC_WDV 0x5c -#define EMC_QUSE 0x60 -#define EMC_QRST 0x64 -#define EMC_QSAFE 0x68 -#define EMC_RDV 0x6c -#define EMC_REFRESH 0x70 -#define EMC_BURST_REFRESH_NUM 0x74 -#define EMC_PDEX2WR 0x78 -#define EMC_PDEX2RD 0x7c -#define EMC_PCHG2PDEN 0x80 -#define EMC_ACT2PDEN 0x84 -#define EMC_AR2PDEN 0x88 -#define EMC_RW2PDEN 0x8c -#define EMC_TXSR 0x90 -#define EMC_TCKE 0x94 -#define EMC_TFAW 0x98 -#define EMC_TRPAB 0x9c -#define EMC_TCLKSTABLE 0xa0 -#define EMC_TCLKSTOP 0xa4 -#define EMC_TREFBW 0xa8 -#define EMC_QUSE_EXTRA 0xac -#define EMC_ODT_WRITE 0xb0 -#define EMC_ODT_READ 0xb4 -#define EMC_WEXT 0xb8 -#define EMC_CTT 0xbc -#define EMC_RFC_SLR 0xc0 -#define EMC_MRS_WAIT_CNT2 0xc4 - -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) -#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 -#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) - -#define EMC_MRS 0xcc -#define EMC_MODE_SET_DLL_RESET (0x1 << 8) -#define EMC_MODE_SET_LONG_CNT (0x1 << 26) -#define EMC_EMRS 0xd0 -#define EMC_REF 0xd4 -#define EMC_REF_FORCE_CMD 1 -#define EMC_PRE 0xd8 -#define EMC_NOP 0xdc - -#define EMC_SELF_REF 0xe0 -#define EMC_SELF_REF_CMD_ENABLED (0x1 << 0) -#define EMC_SELF_REF_DEV_SEL_SHIFT 30 -#define EMC_SELF_REF_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) - -#define EMC_DPD 0xe4 -#define EMC_MRW 0xe8 - -#define EMC_MRR 0xec -#define EMC_MRR_DEV_SEL_SHIFT 30 -#define EMC_MRR_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_MRR_MA_SHIFT 16 -#define EMC_MRR_MA_MASK (0xFF << EMC_MRR_MA_SHIFT) -#define EMC_MRR_DATA_MASK ((0x1 << EMC_MRR_MA_SHIFT) - 1) -#define LPDDR2_MR4_TEMP_SHIFT 0 -#define LPDDR2_MR4_TEMP_MASK (0x7 << LPDDR2_MR4_TEMP_SHIFT) - -#define EMC_CMDQ 0xf0 -#define EMC_MC2EMCQ 0xf4 -#define EMC_XM2DQSPADCTRL3 0xf8 -#define EMC_XM2DQSPADCTRL3_VREF_ENABLE (0x1 << 5) -#define EMC_FBIO_SPARE 0x100 - -#define EMC_FBIO_CFG5 0x104 -#define EMC_CFG5_TYPE_SHIFT 0x0 -#define EMC_CFG5_TYPE_MASK (0x3 << EMC_CFG5_TYPE_SHIFT) -enum { - DRAM_TYPE_DDR3 = 0, - DRAM_TYPE_LPDDR2 = 2, -}; -#define EMC_CFG5_QUSE_MODE_SHIFT 13 -#define EMC_CFG5_QUSE_MODE_MASK \ - (0x7 << EMC_CFG5_QUSE_MODE_SHIFT) -enum { - EMC_CFG5_QUSE_MODE_NORMAL = 0, - EMC_CFG5_QUSE_MODE_ALWAYS_ON, - EMC_CFG5_QUSE_MODE_INTERNAL_LPBK, - EMC_CFG5_QUSE_MODE_PULSE_INTERN, - EMC_CFG5_QUSE_MODE_PULSE_EXTERN, - EMC_CFG5_QUSE_MODE_DIRECT_QUSE, -}; - -#define EMC_FBIO_WRPTR_EQ_2 0x108 -#define EMC_FBIO_CFG6 0x114 -#define EMC_CFG_RSV 0x120 -#define EMC_ACPD_CONTROL 0x124 -#define EMC_EMRS2 0x12c -#define EMC_EMRS3 0x130 -#define EMC_MRW2 0x134 -#define EMC_MRW3 0x138 -#define EMC_MRW4 0x13c -#define EMC_CLKEN_OVERRIDE 0x140 -#define EMC_R2R 0x144 -#define EMC_W2W 0x148 -#define EMC_EINPUT 0x14c -#define EMC_EINPUT_DURATION 0x150 -#define EMC_PUTERM_EXTRA 0x154 -#define EMC_TCKESR 0x158 -#define EMC_TPD 0x15c - -#define EMC_AUTO_CAL_CONFIG 0x2a4 -#define EMC_AUTO_CAL_INTERVAL 0x2a8 -#define EMC_AUTO_CAL_STATUS 0x2ac -#define EMC_AUTO_CAL_STATUS_ACTIVE (0x1 << 31) -#define EMC_REQ_CTRL 0x2b0 -#define EMC_STATUS 0x2b4 -#define EMC_STATUS_TIMING_UPDATE_STALLED (0x1 << 23) -#define EMC_STATUS_MRR_DIVLD (0x1 << 20) - -#define EMC_CFG_2 0x2b8 -#define EMC_CFG_2_MODE_SHIFT 0 -#define EMC_CFG_2_MODE_MASK (0x3 << EMC_CFG_2_MODE_SHIFT) -#define EMC_CFG_2_SREF_MODE 0x1 -#define EMC_CFG_2_PD_MODE 0x3 - -#define EMC_CFG_DIG_DLL 0x2bc -#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 -#define EMC_DIG_DLL_STATUS 0x2c8 -#define EMC_RDV_MASK 0x2cc -#define EMC_WDV_MASK 0x2d0 -#define EMC_CTT_DURATION 0x2d8 -#define EMC_CTT_TERM_CTRL 0x2dc -#define EMC_ZCAL_INTERVAL 0x2e0 -#define EMC_ZCAL_WAIT_CNT 0x2e4 -#define EMC_ZCAL_MRW_CMD 0x2e8 - -#define EMC_ZQ_CAL 0x2ec -#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30 -#define EMC_ZQ_CAL_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_ZQ_CAL_CMD (0x1 << 0) -#define EMC_ZQ_CAL_LONG (0x1 << 4) -#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ - (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) -#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ - (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) - -#define EMC_XM2CMDPADCTRL 0x2f0 -#define EMC_XM2CMDPADCTRL2 0x2f4 -#define EMC_XM2DQSPADCTRL 0x2f8 -#define EMC_XM2DQSPADCTRL2 0x2fc -#define EMC_XM2DQSPADCTRL2_VREF_ENABLE (0x1 << 5) -#define EMC_XM2DQPADCTRL 0x300 -#define EMC_XM2DQPADCTRL2 0x304 -#define EMC_XM2CLKPADCTRL 0x308 -#define EMC_XM2COMPPADCTRL 0x30c -#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (0x1 << 10) -#define EMC_XM2VTTGENPADCTRL 0x310 -#define EMC_XM2VTTGENPADCTRL2 0x314 -#define EMC_EMCPADEN 0x31c -#define EMC_XM2DQSPADCTRL4 0x320 -#define EMC_SCRATCH0 0x324 -#define EMC_DLL_XFORM_DQS0 0x328 -#define EMC_DLL_XFORM_DQS1 0x32c -#define EMC_DLL_XFORM_DQS2 0x330 -#define EMC_DLL_XFORM_DQS3 0x334 -#define EMC_DLL_XFORM_DQS4 0x338 -#define EMC_DLL_XFORM_DQS5 0x33c -#define EMC_DLL_XFORM_DQS6 0x340 -#define EMC_DLL_XFORM_DQS7 0x344 -#define EMC_DLL_XFORM_QUSE0 0x348 -#define EMC_DLL_XFORM_QUSE1 0x34c -#define EMC_DLL_XFORM_QUSE2 0x350 -#define EMC_DLL_XFORM_QUSE3 0x354 -#define EMC_DLL_XFORM_QUSE4 0x358 -#define EMC_DLL_XFORM_QUSE5 0x35c -#define EMC_DLL_XFORM_QUSE6 0x360 -#define EMC_DLL_XFORM_QUSE7 0x364 -#define EMC_DLL_XFORM_DQ0 0x368 -#define EMC_DLL_XFORM_DQ1 0x36c -#define EMC_DLL_XFORM_DQ2 0x370 -#define EMC_DLL_XFORM_DQ3 0x374 -#define EMC_DLI_RX_TRIM0 0x378 -#define EMC_DLI_RX_TRIM1 0x37c -#define EMC_DLI_RX_TRIM2 0x380 -#define EMC_DLI_RX_TRIM3 0x384 -#define EMC_DLI_RX_TRIM4 0x388 -#define EMC_DLI_RX_TRIM5 0x38c -#define EMC_DLI_RX_TRIM6 0x390 -#define EMC_DLI_RX_TRIM7 0x394 -#define EMC_DLI_TX_TRIM0 0x398 -#define EMC_DLI_TX_TRIM1 0x39c -#define EMC_DLI_TX_TRIM2 0x3a0 -#define EMC_DLI_TX_TRIM3 0x3a4 -#define EMC_DLI_TRIM_TXDQS0 0x3a8 -#define EMC_DLI_TRIM_TXDQS1 0x3ac -#define EMC_DLI_TRIM_TXDQS2 0x3b0 -#define EMC_DLI_TRIM_TXDQS3 0x3b4 -#define EMC_DLI_TRIM_TXDQS4 0x3b8 -#define EMC_DLI_TRIM_TXDQS5 0x3bc -#define EMC_DLI_TRIM_TXDQS6 0x3c0 -#define EMC_DLI_TRIM_TXDQS7 0x3c4 -#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc -#define EMC_AUTO_CAL_CLK_STATUS 0x3d4 -#define EMC_SEL_DPD_CTRL 0x3d8 -#define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE (0x1 << 9) -#define EMC_PRE_REFRESH_REQ_CNT 0x3dc -#define EMC_DYN_SELF_REF_CONTROL 0x3e0 -#define EMC_TXSRDLL 0x3e4 -#define EMC_CCFIFO_ADDR 0x3e8 -#define EMC_CCFIFO_DATA 0x3ec -#define EMC_CCFIFO_STATUS 0x3f0 -#define EMC_CDB_CNTL_1 0x3f4 -#define EMC_CDB_CNTL_2 0x3f8 -#define EMC_XM2CLKPADCTRL2 0x3fc -#define EMC_SWIZZLE_RANK0_BYTE_CFG 0x400 -#define EMC_SWIZZLE_RANK0_BYTE0 0x404 -#define EMC_SWIZZLE_RANK0_BYTE1 0x408 -#define EMC_SWIZZLE_RANK0_BYTE2 0x40c -#define EMC_SWIZZLE_RANK0_BYTE3 0x410 -#define EMC_SWIZZLE_RANK1_BYTE_CFG 0x414 -#define EMC_SWIZZLE_RANK1_BYTE0 0x418 -#define EMC_SWIZZLE_RANK1_BYTE1 0x41c -#define EMC_SWIZZLE_RANK1_BYTE2 0x420 -#define EMC_SWIZZLE_RANK1_BYTE3 0x424 -#define EMC_CA_TRAINING_START 0x428 -#define EMC_CA_TRAINING_BUSY 0x42c -#define EMC_CA_TRAINING_CFG 0x430 -#define EMC_CA_TRAINING_TIMING_CNTL1 0x434 -#define EMC_CA_TRAINING_TIMING_CNTL2 0x438 -#define EMC_CA_TRAINING_CA_LEAD_IN 0x43c -#define EMC_CA_TRAINING_CA 0x440 -#define EMC_CA_TRAINING_CA_LEAD_OUT 0x444 -#define EMC_CA_TRAINING_RESULT1 0x448 -#define EMC_CA_TRAINING_RESULT2 0x44c -#define EMC_CA_TRAINING_RESULT3 0x450 -#define EMC_CA_TRAINING_RESULT4 0x454 -#define EMC_AUTO_CAL_CONFIG2 0x458 -#define EMC_AUTO_CAL_CONFIG3 0x45c -#define EMC_AUTO_CAL_STATUS2 0x460 -#define EMC_XM2CMDPADCTRL3 0x464 -#define EMC_IBDLY 0x468 -#define EMC_DLL_XFORM_ADDR0 0x46c -#define EMC_DLL_XFORM_ADDR1 0x470 -#define EMC_DLL_XFORM_ADDR2 0x474 -#define EMC_DLI_ADDR_TRIM 0x478 -#define EMC_DSR_VTTGEN_DRV 0x47c -#define EMC_TXDSRVTTGEN 0x480 -#define EMC_XM2CMDPADCTRL4 0x484 -#define EMC_ADDR_SWIZZLE_STACK1A 0x488 -#define EMC_ADDR_SWIZZLE_STACK1B 0x48c -#define EMC_ADDR_SWIZZLE_STACK2A 0x490 -#define EMC_ADDR_SWIZZLE_STACK2B 0x494 -#define EMC_ADDR_SWIZZLE_STACK3 0x498 - -#define MC_EMEM_ADR_CFG 0x54 - -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 -#define MC_EMEM_ARB_TIMING_RCD 0x98 -#define MC_EMEM_ARB_TIMING_RP 0x9c -#define MC_EMEM_ARB_TIMING_RC 0xa0 -#define MC_EMEM_ARB_TIMING_RAS 0xa4 -#define MC_EMEM_ARB_TIMING_FAW 0xa8 -#define MC_EMEM_ARB_TIMING_RRD 0xac -#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 -#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 -#define MC_EMEM_ARB_TIMING_R2R 0xb8 -#define MC_EMEM_ARB_TIMING_W2W 0xbc -#define MC_EMEM_ARB_TIMING_R2W 0xc0 -#define MC_EMEM_ARB_TIMING_W2R 0xc4 -#define MC_EMEM_ARB_DA_TURNS 0xd0 -#define MC_EMEM_ARB_DA_COVERS 0xd4 -#define MC_EMEM_ARB_MISC0 0xd8 -#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ (0x1 << 27) -#define MC_EMEM_ARB_MISC1 0xdc -#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 -#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 -#define MC_EMEM_ARB_OVERRIDE 0xe8 -#define MC_EMEM_ARB_RSV 0xec - -#define MC_TIMING_CONTROL 0xfc - -#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 -#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 -#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec -#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 -#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 -#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 -#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc -#define MC_LATENCY_ALLOWANCE_EPP_0 0x300 -#define MC_LATENCY_ALLOWANCE_EPP_1 0x304 -#define MC_LATENCY_ALLOWANCE_G2_0 0x308 -#define MC_LATENCY_ALLOWANCE_G2_1 0x30c -#define MC_LATENCY_ALLOWANCE_HC_0 0x310 -#define MC_LATENCY_ALLOWANCE_HC_1 0x314 -#define MC_LATENCY_ALLOWANCE_HDA_0 0x318 -#define MC_LATENCY_ALLOWANCE_ISP_0 0x31c -#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 -#define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324 -#define MC_LATENCY_ALLOWANCE_MSENC_0 0x328 -#define MC_LATENCY_ALLOWANCE_NV_0 0x334 -#define MC_LATENCY_ALLOWANCE_NV_1 0x338 -#define MC_LATENCY_ALLOWANCE_NV2_0 0x33c -#define MC_LATENCY_ALLOWANCE_NV2_1 0x340 -#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 -#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 -#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c -#define MC_LATENCY_ALLOWANCE_VDE_0 0x354 -#define MC_LATENCY_ALLOWANCE_VDE_1 0x358 -#define MC_LATENCY_ALLOWANCE_VDE_2 0x35c -#define MC_LATENCY_ALLOWANCE_VDE_3 0x360 -#define MC_LATENCY_ALLOWANCE_VI_0 0x364 -#define MC_LATENCY_ALLOWANCE_VI_1 0x368 -#define MC_LATENCY_ALLOWANCE_VI_2 0x36c -#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c -#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 -#define MC_LATENCY_ALLOWANCE_NV_2 0x384 -#define MC_LATENCY_ALLOWANCE_NV_3 0x388 -#define MC_LATENCY_ALLOWANCE_EMUCIF_0 0x38c -#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 - -#define MC_RESERVED_RSV 0x3fc - -#define MC_PTSA_GRANT_DECREMENT 0x960 - -#endif diff --git a/arch/arm/mach-tegra/tegra11_speedo.c b/arch/arm/mach-tegra/tegra11_speedo.c deleted file mode 100644 index 2d6e917ee157..000000000000 --- a/arch/arm/mach-tegra/tegra11_speedo.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11_speedo.c - * - * Copyright (C) 2012-2013, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/bug.h> /* For BUG_ON. */ - -#include <linux/tegra-soc.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/tegra-fuse.h> - -#include "iomap.h" -#include "common.h" - -#define CORE_PROCESS_CORNERS_NUM 2 -#define CPU_PROCESS_CORNERS_NUM 2 - -#define FUSE_CPU_SPEEDO_0 0x114 -#define FUSE_CPU_SPEEDO_1 0x12c -#define FUSE_CPU_IDDQ 0x118 -#define FUSE_CORE_SPEEDO_0 0x134 -#define FUSE_CORE_SPEEDO_1 0x138 -#define FUSE_CORE_IDDQ 0x140 -#define FUSE_FT_REV 0x128 -#define FUSE_OPT_CPU23_DISABLE 0x26c -#define FUSE_OPT_CPU23_REENABLE 0x270 - -static int threshold_index; - -static int cpu_process_id; -static int core_process_id; -static int cpu_speedo_id; -static int cpu_speedo_value; -static int soc_speedo_id; -static int core_speedo_value; -static int package_id; -static int cpu_iddq_value; - -static int enable_app_profiles; - -static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { -/* proc_id 0, 1 */ - {1123, UINT_MAX}, /* [0]: threshold_index 0 */ - {0, UINT_MAX}, /* [1]: threshold_index 1 */ -}; - -static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { -/* proc_id 0, 1 */ - {1695, UINT_MAX}, /* [0]: threshold_index 0 */ - {0, UINT_MAX}, /* [1]: threshold_index 1 */ -}; - -static void rev_sku_to_speedo_ids(int rev, int sku) -{ - bool a01 = false; - cpu_speedo_id = 0; /* For A01 rev, regardless of SKU */ - - if (rev == TEGRA_REVISION_A01) { - u32 a01p = tegra_fuse_readl(FUSE_OPT_CPU23_REENABLE) << 1; - a01p |= tegra_fuse_readl(FUSE_OPT_CPU23_DISABLE); - if (a01p == 0) - a01 = true; - } - - switch (sku) { - case 0x00: /* Eng */ - case 0x10: /* Eng */ - case 0x05: /* T40S */ - case 0x06: /* AP40 */ - case 0x20: /* T40DC */ - if (!a01) - cpu_speedo_id = 1; - soc_speedo_id = 0; - threshold_index = 0; - break; - - case 0x03: /* T40X */ - case 0x04: /* T40T */ - if (!a01) - cpu_speedo_id = 2; - soc_speedo_id = 1; - threshold_index = 1; - break; - - case 0x08: /* AP40X */ - if (!a01) - cpu_speedo_id = 3; - soc_speedo_id = 1; - threshold_index = 1; - break; - - default: - /* FIXME: replace with BUG() when all SKU's valid */ - pr_err("Tegra11 Unknown SKU %d\n", sku); - cpu_speedo_id = 0; - soc_speedo_id = 0; - threshold_index = 0; - break; - } -} - -void tegra_init_speedo_data(void) -{ - int i; - u32 ft_rev, ft_rev_major, ft_rev_minor; - - cpu_speedo_value = 1024 + tegra_fuse_readl(FUSE_CPU_SPEEDO_1); - core_speedo_value = tegra_fuse_readl(FUSE_CORE_SPEEDO_0); - - cpu_iddq_value = tegra_fuse_readl(FUSE_CPU_IDDQ); - - ft_rev = tegra_fuse_readl(FUSE_FT_REV); - ft_rev_minor = ft_rev & 0x1f; - ft_rev_major = (ft_rev >> 5) & 0x3f; - - if ((ft_rev_minor < 5) && (ft_rev_major == 0)) { - /* Implement: cpu_iddq = max(1.3*fused_cpu_iddq, 2 Amps) */ - cpu_iddq_value *= 130; - cpu_iddq_value = cpu_iddq_value > 200000 ? - cpu_iddq_value : 200000; - cpu_iddq_value /= 100; - - pr_warn("Tegra11: CPU IDDQ and speedo may be bogus"); - } - - rev_sku_to_speedo_ids(tegra_revision, tegra_get_sku_id()); - - pr_info("Tegra11: CPU Speedo ID %d, Soc Speedo ID %d", - cpu_speedo_id, soc_speedo_id); - pr_info("Tegra11: CPU Speedo Value %d, Soc Speedo Value %d", - cpu_speedo_value, core_speedo_value); - - for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) { - if (cpu_speedo_value < - cpu_process_speedos[threshold_index][i]) { - break; - } - } - cpu_process_id = i; - - for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) { - if (core_speedo_value < - core_process_speedos[threshold_index][i]) { - break; - } - } - core_process_id = i; -} - -int tegra_cpu_process_id(void) -{ - return cpu_process_id; -} - -int tegra_core_process_id(void) -{ - return core_process_id; -} - -int tegra_cpu_speedo_id(void) -{ - return cpu_speedo_id; -} - -int tegra_soc_speedo_id(void) -{ - return soc_speedo_id; -} - -int tegra_package_id(void) -{ - return package_id; -} - -int tegra_cpu_speedo_value(void) -{ - return cpu_speedo_value; -} - -/* - * CPU and core nominal voltage levels as determined by chip SKU and speedo - * (not final - can be lowered by dvfs tables and rail dependencies; the - * latter is resolved by the dvfs code) - */ -int tegra_cpu_speedo_mv(void) -{ - /* Not applicable on Tegra11 */ - return -ENOSYS; -} - -int tegra_core_speedo_mv(void) -{ - u32 tegra_sku_id; - - tegra_sku_id = tegra_get_sku_id(); - switch (soc_speedo_id) { - case 0: - if (core_process_id == 1) - return 1170; - /* fall thru if core_process_id = 0 */ - case 1: - if ((tegra_sku_id == 0x4) || (tegra_sku_id == 0x8)) - return 1390; - return 1250; - default: - BUG(); - } -} - -int tegra_get_cpu_iddq_value() -{ - return cpu_iddq_value; -} - -static int get_enable_app_profiles(char *val, const struct kernel_param *kp) -{ - return param_get_uint(val, kp); -} - -static struct kernel_param_ops tegra_profiles_ops = { - .get = get_enable_app_profiles, -}; - -module_param_cb(tegra_enable_app_profiles, - &tegra_profiles_ops, &enable_app_profiles, 0444); diff --git a/arch/arm/mach-tegra/tegra11x_la.c b/arch/arm/mach-tegra/tegra11x_la.c deleted file mode 100644 index ae7e01a8b436..000000000000 --- a/arch/arm/mach-tegra/tegra11x_la.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra11x_la.c - * - * Copyright (C) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/stringify.h> -#include <linux/clk.h> -#include <linux/clk/tegra.h> -#include <linux/tegra-soc.h> -#include <asm/io.h> -#include <mach/latency_allowance.h> - -#include "iomap.h" -#include "la_priv.h" - -#define T11X_MC_LA_AVPC_ARM7_0 0x2e4 -#define T11X_MC_LA_DC_0 0x2e8 -#define T11X_MC_LA_DC_1 0x2ec -#define T11X_MC_LA_DC_2 0x2f0 -#define T11X_MC_LA_DCB_0 0x2f4 -#define T11X_MC_LA_DCB_1 0x2f8 -#define T11X_MC_LA_DCB_2 0x2fc -#define T11X_MC_LA_EPP_0 0x300 -#define T11X_MC_LA_EPP_1 0x304 -#define T11X_MC_LA_G2_0 0x308 -#define T11X_MC_LA_G2_1 0x30c -#define T11X_MC_LA_HC_0 0x310 -#define T11X_MC_LA_HC_1 0x314 -#define T11X_MC_LA_HDA_0 0x318 -#define T11X_MC_LA_ISP_0 0x31C -#define T11X_MC_LA_MPCORE_0 0x320 -#define T11X_MC_LA_MPCORELP_0 0x324 -#define T11X_MC_LA_MSENC_0 0x328 -#define T11X_MC_LA_NV_0 0x334 -#define T11X_MC_LA_NV_1 0x338 -#define T11X_MC_LA_NV2_0 0x33c -#define T11X_MC_LA_NV2_1 0x340 -#define T11X_MC_LA_PPCS_0 0x344 -#define T11X_MC_LA_PPCS_1 0x348 -#define T11X_MC_LA_PTC_0 0x34c - -#define T11X_MC_LA_VDE_0 0x354 -#define T11X_MC_LA_VDE_1 0x358 -#define T11X_MC_LA_VDE_2 0x35c -#define T11X_MC_LA_VDE_3 0x360 -#define T11X_MC_LA_VI_0 0x364 -#define T11X_MC_LA_VI_1 0x368 -#define T11X_MC_LA_VI_2 0x36c - -#define T11X_MC_LA_XUSB_0 0x37c /* T11x specific*/ -#define T11X_MC_LA_XUSB_1 0x380 /* T11x specific*/ -#define T11X_MC_LA_NV_2 0x384 /* T11x specific*/ -#define T11X_MC_LA_NV_3 0x388 /* T11x specific*/ - -#define T11X_MC_LA_EMUCIF_0 0x38c -#define T11X_MC_LA_TSEC_0 0x390 - -#define T11X_MC_DIS_PTSA_RATE_0 0x41c -#define T11X_MC_DIS_PTSA_MIN_0 0x420 -#define T11X_MC_DIS_PTSA_MAX_0 0x424 -#define T11X_MC_DISB_PTSA_RATE_0 0x428 -#define T11X_MC_DISB_PTSA_MIN_0 0x42c -#define T11X_MC_DISB_PTSA_MAX_0 0x430 -#define T11X_MC_VE_PTSA_RATE_0 0x434 -#define T11X_MC_VE_PTSA_MIN_0 0x438 -#define T11X_MC_VE_PTSA_MAX_0 0x43c -#define T11X_MC_RING2_PTSA_RATE_0 0x440 -#define T11X_MC_RING2_PTSA_MIN_0 0x444 -#define T11X_MC_RING2_PTSA_MAX_0 0x448 -#define T11X_MC_MLL_MPCORER_PTSA_RATE_0 0x44c -#define T11X_MC_MLL_MPCORER_PTSA_MIN_0 0x450 -#define T11X_MC_MLL_MPCORER_PTSA_MAX_0 0x454 -#define T11X_MC_SMMU_SMMU_PTSA_RATE_0 0x458 -#define T11X_MC_SMMU_SMMU_PTSA_MIN_0 0x45c -#define T11X_MC_SMMU_SMMU_PTSA_MAX_0 0x460 -#define T11X_MC_R0_DIS_PTSA_RATE_0 0x464 -#define T11X_MC_R0_DIS_PTSA_MIN_0 0x468 -#define T11X_MC_R0_DIS_PTSA_MAX_0 0x46c -#define T11X_MC_R0_DISB_PTSA_RATE_0 0x470 -#define T11X_MC_R0_DISB_PTSA_MIN_0 0x474 -#define T11X_MC_R0_DISB_PTSA_MAX_0 0x478 -#define T11X_MC_RING1_PTSA_RATE_0 0x47c -#define T11X_MC_RING1_PTSA_MIN_0 0x480 -#define T11X_MC_RING1_PTSA_MAX_0 0x484 - -#define T11X_MC_DIS_EXTRA_SNAP_LEVELS_0 0x2ac -#define T11X_MC_HEG_EXTRA_SNAP_LEVELS_0 0x2b0 -#define T11X_MC_EMEM_ARB_MISC0_0 0x0d8 -#define T11X_MC_PTSA_GRANT_DECREMENT_0 0x960 - -#define T11X_BASE_EMC_FREQ_MHZ 500 -#define T11X_MAX_CAMERA_BW_MHZ 528 - -/* maximum valid value for latency allowance */ -#define T11X_MC_LA_MAX_VALUE 255 - -#define T11X_MC_RA(r) \ - (IO_ADDRESS(TEGRA_MC_BASE) + (T11X_MC_##r)) -#define T11X_RA(r) \ - (IO_ADDRESS(TEGRA_MC_BASE) + (T11X_MC_LA_##r)) - -#define T11X_LA(f, e, a, r, i, ss, la) \ -{ \ - .fifo_size_in_atoms = f, \ - .expiration_in_ns = e, \ - .reg_addr = T11X_RA(a), \ - .mask = MASK(r), \ - .shift = SHIFT(r), \ - .id = ID(i), \ - .name = __stringify(i), \ - .scaling_supported = ss, \ - .init_la = la, \ -} - -/* - * The consensus for getting the fifo_size_in_atoms is: - * 1.If REORDER_DEPTH exists, use it(default is overridden). - * 2.Else if (write_client) use RFIFO_DEPTH. - * 3.Else (read client) use RDFIFO_DEPTH. - * Multiply the value by 2 for dual channel. - * Multiply the value by 2 for wide clients. - * A client is wide, if CMW is larger than MW. - * Refer to project.h file. - */ -struct la_client_info t11x_la_info_array[] = { - T11X_LA(3, 150, AVPC_ARM7_0, 7 : 0, AVPC_ARM7R, false, 0), - T11X_LA(3, 150, AVPC_ARM7_0, 23 : 16, AVPC_ARM7W, false, 0), - T11X_LA(256, 1050, DC_0, 7 : 0, DISPLAY_0A, true, 0), - T11X_LA(256, 1050, DC_0, 23 : 16, DISPLAY_0B, true, 0), - T11X_LA(256, 1050, DC_1, 7 : 0, DISPLAY_0C, true, 0), - T11X_LA(96, 1050, DC_2, 7 : 0, DISPLAY_HC, false, 0), - T11X_LA(256, 1050, DCB_0, 7 : 0, DISPLAY_0AB, true, 0), - T11X_LA(256, 1050, DCB_0, 23 : 16, DISPLAY_0BB, true, 0), - T11X_LA(256, 1050, DCB_1, 7 : 0, DISPLAY_0CB, true, 0), - T11X_LA(96, 1050, DCB_2, 7 : 0, DISPLAY_HCB, false, 0), - T11X_LA(16, 150, EPP_0, 7 : 0, EPPUP, false, 0), - T11X_LA(64, 150, EPP_0, 23 : 16, EPPU, false, 0), - T11X_LA(64, 150, EPP_1, 7 : 0, EPPV, false, 0), - T11X_LA(64, 150, EPP_1, 23 : 16, EPPY, false, 0), - T11X_LA(128, 150, G2_0, 7 : 0, G2PR, false, 0), - T11X_LA(128, 150, G2_0, 23 : 16, G2SR, false, 0), - T11X_LA(96, 150, G2_1, 7 : 0, G2DR, false, 0), - T11X_LA(256, 150, G2_1, 23 : 16, G2DW, false, 0), - T11X_LA(32, 150, HC_0, 7 : 0, HOST1X_DMAR, false, 0), - T11X_LA(16, 150, HC_0, 23 : 16, HOST1XR, false, 0), - T11X_LA(64, 150, HC_1, 7 : 0, HOST1XW, false, 0), - T11X_LA(32, 150, HDA_0, 7 : 0, HDAR, false, 0), - T11X_LA(32, 150, HDA_0, 23 : 16, HDAW, false, 0), - T11X_LA(128, 150, ISP_0, 7 : 0, ISPW, false, 0), - T11X_LA(96, 150, MPCORE_0, 7 : 0, MPCORER, false, 0), - T11X_LA(128, 150, MPCORE_0, 23 : 16, MPCOREW, false, 0), - T11X_LA(96, 150, MPCORELP_0, 7 : 0, MPCORE_LPR, false, 0), - T11X_LA(128, 150, MPCORELP_0, 23 : 16, MPCORE_LPW, false, 0), - T11X_LA(128, 150, NV_0, 7 : 0, FDCDRD, false, 0), - T11X_LA(256, 150, NV_0, 23 : 16, IDXSRD, false, 0), - T11X_LA(432, 150, NV_1, 7 : 0, TEXL2SRD, false, 0), - T11X_LA(128, 150, NV_1, 23 : 16, FDCDWR, false, 0), - T11X_LA(128, 150, NV2_0, 7 : 0, FDCDRD2, false, 0), - T11X_LA(128, 150, NV2_1, 7 : 0, FDCDWR2, false, 0), - T11X_LA(8, 150, PPCS_0, 7 : 0, PPCS_AHBDMAR, false, 0), - T11X_LA(80, 150, PPCS_0, 23 : 16, PPCS_AHBSLVR, false, 0), - T11X_LA(16, 150, PPCS_1, 7 : 0, PPCS_AHBDMAW, false, 0), - T11X_LA(80, 150, PPCS_1, 23 : 16, PPCS_AHBSLVW, false, 0), - T11X_LA(40, 150, PTC_0, 7 : 0, PTCR, false, 0), - T11X_LA(16, 150, VDE_0, 7 : 0, VDE_BSEVR, false, 131), - T11X_LA(8, 150, VDE_0, 23 : 16, VDE_MBER, false, 131), - T11X_LA(64, 150, VDE_1, 7 : 0, VDE_MCER, false, 50), - T11X_LA(32, 150, VDE_1, 23 : 16, VDE_TPER, false, 123), - T11X_LA(8, 150, VDE_2, 7 : 0, VDE_BSEVW, false, 131), - T11X_LA(32, 150, VDE_2, 23 : 16, VDE_DBGW, false, 131), - T11X_LA(16, 150, VDE_3, 7 : 0, VDE_MBEW, false, 70), - T11X_LA(32, 150, VDE_3, 23 : 16, VDE_TPMW, false, 76), - T11X_LA(128, 1050, VI_0, 7 : 0, VI_WSB, true, 0), - T11X_LA(128, 1050, VI_1, 7 : 0, VI_WU, true, 0), - T11X_LA(128, 1050, VI_1, 23 : 16, VI_WV, true, 0), - T11X_LA(128, 1050, VI_2, 7 : 0, VI_WY, true, 0), - - T11X_LA(128, 150, MSENC_0, 7 : 0, MSENCSRD, false, 128), - T11X_LA(32, 150, MSENC_0, 23 : 16, MSENCSWR, false, 41), - T11X_LA(160, 150, XUSB_0, 7 : 0, XUSB_HOSTR, false, 0), - T11X_LA(160, 150, XUSB_0, 23 : 16, XUSB_HOSTW, false, 0), - T11X_LA(160, 150, XUSB_1, 7 : 0, XUSB_DEVR, false, 0), - T11X_LA(160, 150, XUSB_1, 23 : 16, XUSB_DEVW, false, 0), - T11X_LA(128, 150, NV_2, 7 : 0, FDCDRD3, false, 0), - T11X_LA(128, 150, NV_2, 23 : 16, FDCDRD4, false, 0), - T11X_LA(128, 150, NV_3, 7 : 0, FDCDWR3, false, 0), - T11X_LA(128, 150, NV_3, 23 : 16, FDCDWR4, false, 0), - T11X_LA(28, 150, EMUCIF_0, 7 : 0, EMUCIFR, false, 0), - T11X_LA(48, 150, EMUCIF_0, 23 : 16, EMUCIFW, false, 0), - T11X_LA(32, 150, TSEC_0, 7 : 0, TSECSRD, false, 0), - T11X_LA(32, 150, TSEC_0, 23 : 16, TSECSWR, false, 0), - -/* end of list. */ - T11X_LA(0, 0, TSEC_0, 0 : 0, MAX_ID, false, 0) -}; - -static unsigned int t11x_get_ptsa_rate(unsigned int bw) -{ - /* 16 = 2 channels * 2 ddr * 4 bytes */ - unsigned int base_memory_bw = 16 * T11X_BASE_EMC_FREQ_MHZ; - unsigned int rate = 281 * bw / base_memory_bw; - if (rate > 255) - rate = 255; - return rate; -} - -static void t11x_init_ptsa(void) -{ - struct clk *emc_clk __attribute__((unused)); - unsigned long emc_freq __attribute__((unused)); - unsigned long same_freq __attribute__((unused)); - unsigned long grant_dec __attribute__((unused)); - unsigned long ring1_rate __attribute__((unused)); - - emc_clk = clk_get(NULL, "emc"); - la_debug("**** emc clk_rate=%luMHz", clk_get_rate(emc_clk)/1000000); - - emc_freq = clk_get_rate(emc_clk); - emc_freq /= 1000000; - /* Compute initial value for grant dec */ - same_freq = readl(T11X_MC_RA(EMEM_ARB_MISC0_0)); - same_freq = same_freq >> 27 & 1; - grant_dec = 256 * (same_freq ? 2 : 1) * emc_freq; - if (grant_dec > 511) - grant_dec = 511; - writel(grant_dec, T11X_MC_RA(PTSA_GRANT_DECREMENT_0)); - - writel(0x3d, T11X_MC_RA(DIS_PTSA_MIN_0)); - writel(0x14, T11X_MC_RA(DIS_PTSA_MAX_0)); - - writel(0x3d, T11X_MC_RA(DISB_PTSA_MIN_0)); - writel(0x14, T11X_MC_RA(DISB_PTSA_MAX_0)); - - writel(t11x_get_ptsa_rate(T11X_MAX_CAMERA_BW_MHZ), - T11X_MC_RA(VE_PTSA_RATE_0)); - writel(0x3d, T11X_MC_RA(VE_PTSA_MIN_0)); - writel(0x14, T11X_MC_RA(VE_PTSA_MAX_0)); - - writel(0x01, T11X_MC_RA(RING2_PTSA_RATE_0)); - writel(0x3f, T11X_MC_RA(RING2_PTSA_MIN_0)); - writel(0x05, T11X_MC_RA(RING2_PTSA_MAX_0)); - - writel(38 * emc_freq / T11X_BASE_EMC_FREQ_MHZ, - T11X_MC_RA(MLL_MPCORER_PTSA_RATE_0)); - writel(0x3f, T11X_MC_RA(MLL_MPCORER_PTSA_MIN_0)); - writel(0x05, T11X_MC_RA(MLL_MPCORER_PTSA_MAX_0)); - - writel(0x01, T11X_MC_RA(SMMU_SMMU_PTSA_RATE_0)); - writel(0x01, T11X_MC_RA(SMMU_SMMU_PTSA_MIN_0)); - writel(0x01, T11X_MC_RA(SMMU_SMMU_PTSA_MAX_0)); - - ring1_rate = readl(T11X_MC_RA(DIS_PTSA_RATE_0)) + - readl(T11X_MC_RA(DISB_PTSA_RATE_0)); -#if defined(CONFIG_TEGRA_ERRATA_977223) - ring1_rate /= 2; -#endif - ring1_rate += readl(T11X_MC_RA(VE_PTSA_RATE_0)) + - readl(T11X_MC_RA(RING2_PTSA_RATE_0)); - writel(ring1_rate, T11X_MC_RA(RING1_PTSA_RATE_0)); - writel(0x36, T11X_MC_RA(RING1_PTSA_MIN_0)); - writel(0x1f, T11X_MC_RA(RING1_PTSA_MAX_0)); - - writel(0x00, T11X_MC_RA(DIS_EXTRA_SNAP_LEVELS_0)); - writel(0x03, T11X_MC_RA(HEG_EXTRA_SNAP_LEVELS_0)); -} - -static void t11x_update_display_ptsa_rate(unsigned int *disp_bw_array) -{ - unsigned int num_active = (disp_bw_array[0] != 0) + - (disp_bw_array[1] != 0) + - (disp_bw_array[2] != 0); - unsigned int num_activeb = (disp_bw_array[5] != 0) + - (disp_bw_array[6] != 0) + - (disp_bw_array[7] != 0); - unsigned int max_bw = disp_bw_array[0]; - unsigned int max_bwb = disp_bw_array[5]; - unsigned int rate_dis; - unsigned int rate_disb; - unsigned long ring1_rate; - - max_bw = max(disp_bw_array[0], disp_bw_array[1]); - max_bw = max(max_bw, disp_bw_array[2]); - - max_bwb = max(disp_bw_array[5], disp_bw_array[6]); - max_bwb = max(max_bwb, disp_bw_array[7]); - - rate_dis = t11x_get_ptsa_rate(num_active * max_bw); - rate_disb = t11x_get_ptsa_rate(num_activeb * max_bwb); - - writel(rate_dis, T11X_MC_RA(DIS_PTSA_RATE_0)); - writel(rate_disb, T11X_MC_RA(DISB_PTSA_RATE_0)); - - ring1_rate = rate_dis + rate_disb; -#if defined(CONFIG_TEGRA_ERRATA_977223) - ring1_rate /= 2; -#endif - ring1_rate += readl(T11X_MC_RA(VE_PTSA_RATE_0)) + - readl(T11X_MC_RA(RING2_PTSA_RATE_0)); - writel(ring1_rate, T11X_MC_RA(RING1_PTSA_RATE_0)); -} - -void tegra_la_get_t11x_specific(struct la_chip_specific *cs) -{ - cs->ns_per_tick = 30; - cs->atom_size = 16; - cs->la_max_value = T11X_MC_LA_MAX_VALUE; - cs->la_info_array = t11x_la_info_array; - cs->la_info_array_size = ARRAY_SIZE(t11x_la_info_array); - cs->init_ptsa = t11x_init_ptsa; - cs->update_display_ptsa_rate = t11x_update_display_ptsa_rate; -} diff --git a/arch/arm/mach-tegra/tegra14_clocks.c b/arch/arm/mach-tegra/tegra14_clocks.c deleted file mode 100644 index 54106de3968a..000000000000 --- a/arch/arm/mach-tegra/tegra14_clocks.c +++ /dev/null @@ -1,7645 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14_clocks.c - * - * Copyright (c) 2013-2014 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/cpufreq.h> -#include <linux/syscore_ops.h> -#include <linux/platform_device.h> -#include <linux/tegra-soc.h> - -#include <asm/clkdev.h> - -#include <mach/edp.h> -#include <mach/mc.h> -#include <mach/tegra_bb.h> - -#include "clock.h" -#include "dvfs.h" -#include "iomap.h" -#include "pm.h" -#include "sleep.h" -#include "devices.h" -#include "tegra14_emc.h" -#include "tegra_cl_dvfs.h" -#include "tegra11_soctherm.h" - -#define RST_DEVICES_L 0x004 -#define RST_DEVICES_H 0x008 -#define RST_DEVICES_U 0x00C -#define RST_DEVICES_V 0x358 -#define RST_DEVICES_W 0x35C -#define RST_DEVICES_X 0x28C -#define RST_DEVICES_SET_L 0x300 -#define RST_DEVICES_CLR_L 0x304 -#define RST_DEVICES_SET_V 0x430 -#define RST_DEVICES_CLR_V 0x434 -#define RST_DEVICES_SET_X 0x290 -#define RST_DEVICES_CLR_X 0x294 -#define RST_DEVICES_NUM 6 - -#define CLK_OUT_ENB_L 0x010 -#define CLK_OUT_ENB_H 0x014 -#define CLK_OUT_ENB_U 0x018 -#define CLK_OUT_ENB_V 0x360 -#define CLK_OUT_ENB_W 0x364 -#define CLK_OUT_ENB_X 0x280 -#define CLK_OUT_ENB_SET_L 0x320 -#define CLK_OUT_ENB_CLR_L 0x324 -#define CLK_OUT_ENB_SET_V 0x440 -#define CLK_OUT_ENB_CLR_V 0x444 -#define CLK_OUT_ENB_SET_X 0x284 -#define CLK_OUT_ENB_CLR_X 0x288 -#define CLK_OUT_ENB_NUM 6 - -#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) - -#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) -#define PERIPH_CLK_TO_RST_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4) -#define PERIPH_CLK_TO_RST_SET_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \ - RST_DEVICES_SET_X, 8) -#define PERIPH_CLK_TO_RST_CLR_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \ - RST_DEVICES_CLR_X, 8) - -#define PERIPH_CLK_TO_ENB_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4) -#define PERIPH_CLK_TO_ENB_SET_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \ - CLK_OUT_ENB_SET_X, 8) -#define PERIPH_CLK_TO_ENB_CLR_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \ - CLK_OUT_ENB_CLR_X, 8) - -#define CLK_MASK_ARM 0x44 -#define MISC_CLK_ENB 0x48 - -#define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) -#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) -#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) -#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) -#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) -#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) -#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) -#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) -#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) -#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) - -#define PERIPH_CLK_SOURCE_I2S1 0x100 -#define PERIPH_CLK_SOURCE_EMC 0x19c -#define PERIPH_CLK_SOURCE_OSC 0x1fc -#define PERIPH_CLK_SOURCE_NUM1 \ - ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) - -#define PERIPH_CLK_SOURCE_G3D2 0x3b0 -#define PERIPH_CLK_SOURCE_SE 0x42c -#define PERIPH_CLK_SOURCE_NUM2 \ - ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) - -#define AUDIO_DLY_CLK 0x49c -#define AUDIO_SYNC_CLK_I2S4 0x4b0 -#define PERIPH_CLK_SOURCE_NUM3 \ - ((AUDIO_SYNC_CLK_I2S4 - AUDIO_DLY_CLK) / 4 + 1) - -#define SPARE_REG 0x55c -#define SPARE_REG_CLK_M_DIVISOR_SHIFT 2 -#define SPARE_REG_CLK_M_DIVISOR_MASK (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT) - -#define PERIPH_CLK_SOURCE_CILAB 0x614 -#define PERIPH_CLK_SOURCE_CLK72MHZ 0x66c -#define PERIPH_CLK_SOURCE_NUM4 \ - ((PERIPH_CLK_SOURCE_CLK72MHZ - PERIPH_CLK_SOURCE_CILAB) / 4 + 1) - -#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ - PERIPH_CLK_SOURCE_NUM2 + \ - PERIPH_CLK_SOURCE_NUM3 + \ - PERIPH_CLK_SOURCE_NUM4) - -#define CPU_SOFTRST_CTRL 0x380 -#define CPU_SOFTRST_CTRL1 0x384 -#define CPU_SOFTRST_CTRL2 0x388 - -#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF -#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF -#define PERIPH_CLK_SOURCE_DIV_SHIFT 0 -#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 -#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 -#define PERIPH_CLK_UART_DIV_ENB (1<<24) -#define PERIPH_CLK_VI_SEL_EX_SHIFT 24 -#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) -#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) -#define PERIPH_CLK_DTV_POLARITY_INV (1<<25) - -#define AUDIO_SYNC_SOURCE_MASK 0x0F -#define AUDIO_SYNC_DISABLE_BIT 0x10 -#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) - -/* PLL common */ -#define PLL_BASE 0x0 -#define PLL_BASE_BYPASS (1<<31) -#define PLL_BASE_ENABLE (1<<30) -#define PLL_BASE_REF_ENABLE (1<<29) -#define PLL_BASE_OVERRIDE (1<<28) -#define PLL_BASE_LOCK (1<<27) -#define PLL_BASE_DIVP_MASK (0x7<<20) -#define PLL_BASE_DIVP_SHIFT 20 -#define PLL_BASE_DIVN_MASK (0x3FF<<8) -#define PLL_BASE_DIVN_SHIFT 8 -#define PLL_BASE_DIVM_MASK (0x1F) -#define PLL_BASE_DIVM_SHIFT 0 - -#define PLL_BASE_PARSE(pll, cfg, b) \ - do { \ - (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \ - (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \ - (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \ - } while (0) - -#define PLL_OUT_RATIO_MASK (0xFF<<8) -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_OVERRIDE (1<<2) -#define PLL_OUT_CLKEN (1<<1) -#define PLL_OUT_RESET_DISABLE (1<<0) - -#define PLL_MISC(c) \ - (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) -#define PLL_MISCN(c, n) \ - ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c)) -#define PLL_MISC_LOCK_ENABLE(c) \ - (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) - -#define PLL_MISC_DCCON_SHIFT 20 -#define PLL_MISC_CPCON_SHIFT 8 -#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) -#define PLL_MISC_LFCON_SHIFT 4 -#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) -#define PLL_MISC_VCOCON_SHIFT 0 -#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) - -#define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1) - -/* PLLU */ -#define PLLU_BASE_OVERRIDE (1<<24) -#define PLLU_BASE_POST_DIV (1<<20) - -/* PLLD */ -#define PLLD_BASE_CSI_CLKENABLE (1<<26) -#define PLLD_BASE_DSI_MUX_SHIFT 25 -#define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT) -#define PLLD_BASE_CSI_CLKSOURCE (1<<24) - -#define PLLD_MISC_DSI_CLKENABLE (1<<30) -#define PLLD_MISC_DIV_RST (1<<23) -#define PLLD_MISC_DCCON_SHIFT 12 - -#define PLLDU_LFCON 2 - -/* PLLC2 and PLLC3 (PLLCX) */ -#define PLLCX_USE_DYN_RAMP 0 -#define PLLCX_BASE_PHASE_LOCK (1<<26) -#define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT) -#define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT) -#define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT) -#define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) -#define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8)) - -#define PLLCX_MISC_STROBE (1<<31) -#define PLLCX_MISC_RESET (1<<30) -#define PLLCX_MISC_SDM_DIV_SHIFT 28 -#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) -#define PLLCX_MISC_FILT_DIV_SHIFT 26 -#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) -#define PLLCX_MISC_ALPHA_SHIFT 18 -#define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT) -#define PLLCX_MISC_KB_SHIFT 9 -#define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT) -#define PLLCX_MISC_KA_SHIFT 2 -#define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT) -#define PLLCX_MISC_VCO_GAIN_SHIFT 0 -#define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT) - -#define PLLCX_MISC1_IDDQ (1<<27) - -#define PLLCX_MISC_KOEF_LOW_RANGE \ - ((26 << PLLCX_MISC_KA_SHIFT) | (80 << PLLCX_MISC_KB_SHIFT)) - -#define PLLCX_MISC_DIV_LOW_RANGE \ - ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) -#define PLLCX_MISC_DIV_HIGH_RANGE \ - ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) - -#define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \ - PLLCX_MISC_KOEF_LOW_RANGE | \ - (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ - PLLCX_MISC_DIV_LOW_RANGE | \ - PLLCX_MISC_RESET) -#define PLLCX_MISC1_DEFAULT_VALUE 0x080d2308 -#define PLLCX_MISC2_DEFAULT_VALUE 0x21312200 -#define PLLCX_MISC3_DEFAULT_VALUE 0x200 - -/* PLLX and PLLC (PLLXC)*/ -#define PLLXC_USE_DYN_RAMP 0 -#define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT) -#define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT) -#define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT) - -/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w, - and s/w usage is limited to 5 */ -#define PLLXC_PDIV_MAX 14 -#define PLLXC_SW_PDIV_MAX 5 - -/* PLLX */ -#define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 -#define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) -#define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 -#define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) -#define PLLX_MISC2_NDIV_NEW_SHIFT 8 -#define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) -#define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) -#define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) -#define PLLX_MISC2_CLAMP_NDIV (0x1 << 1) -#define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) - -#define PLLX_MISC3_IDDQ (0x1 << 3) - -#define PLLX_HW_CTRL_CFG 0x548 -#define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) - -/* PLLC */ -#define PLLC_BASE_LOCK_OVERRIDE (1<<28) - -#define PLLC_MISC_IDDQ (0x1 << 26) -#define PLLC_MISC_LOCK_ENABLE (0x1 << 24) - -#define PLLC_MISC1_CLAMP_NDIV (0x1 << 26) -#define PLLC_MISC1_EN_DYNRAMP (0x1 << 25) -#define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17 -#define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT) -#define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9 -#define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT) -#define PLLC_MISC1_NDIV_NEW_SHIFT 1 -#define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT) -#define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0) - -/* PLLM */ -#define PLLM_BASE_DIVP_MASK (0xF << PLL_BASE_DIVP_SHIFT) -#define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT) -#define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT) - -/* PLLM has 4-bit PDIV, but entry 15 is not allowed in h/w, - and s/w usage is limited to 5 */ -#define PLLM_PDIV_MAX 14 -#define PLLM_SW_PDIV_MAX 5 - -#define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10) -#define PLLM_MISC_IDDQ (0x1 << 5) -#define PLLM_MISC_LOCK_DISABLE (0x1 << 4) -#define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3) - -#define PMC_PLLP_WB0_OVERRIDE 0xf8 -#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) -#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11) - -/* M, N layout for PLLM override and base registers are the same */ -#define PMC_PLLM_WB0_OVERRIDE 0x1dc - -#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 -#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT 27 -#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0xF << 27) - -#define OUT_OF_TABLE_CPCON 0x8 - -#define SUPER_CLK_MUX 0x00 -#define SUPER_STATE_SHIFT 28 -#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) -#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) -#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) -#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) -#define SUPER_LP_DIV2_BYPASS (0x1 << 16) -#define SUPER_SOURCE_MASK 0xF -#define SUPER_FIQ_SOURCE_SHIFT 12 -#define SUPER_IRQ_SOURCE_SHIFT 8 -#define SUPER_RUN_SOURCE_SHIFT 4 -#define SUPER_IDLE_SOURCE_SHIFT 0 - -#define SUPER_CLK_DIVIDER 0x04 -#define SUPER_CLOCK_DIV_U71_SHIFT 16 -#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) - -#define BUS_CLK_DISABLE (1<<3) -#define BUS_CLK_DIV_MASK 0x3 - -#define PMC_CTRL 0x0 - #define PMC_CTRL_BLINK_ENB (1 << 7) - -#define PMC_DPD_PADS_ORIDE 0x1c - #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) - -#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 -#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff -#define PMC_BLINK_TIMER_ENB (1 << 15) -#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 -#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff - -#define UTMIP_PLL_CFG2 0x488 -#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) -#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) - -#define UTMIP_PLL_CFG1 0x484 -#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) -#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) -#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15) -#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) -#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) -#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17) -#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) - -#define UTMIPLL_HW_PWRDN_CFG0 0x52c -#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5) -#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4) -#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1) -#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0) - -#define USB_PLLS_SEQ_START_STATE (1<<25) -#define USB_PLLS_SEQ_ENABLE (1<<24) -#define USB_PLLS_USE_LOCKDET (1<<6) -#define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0)) - -/* DFLL */ -#define DFLL_BASE 0x2f4 -#define DFLL_BASE_RESET (1<<0) - -#define ROUND_DIVIDER_UP 0 -#define ROUND_DIVIDER_DOWN 1 -#define DIVIDER_1_5_ALLOWED 0 - -/* PLLP default fixed rate in h/w controlled mode */ -#define PLLP_DEFAULT_FIXED_RATE 408000000 - -static bool tegra14_is_dyn_ramp(struct clk *c, - unsigned long rate, bool from_vco_min); -static void tegra14_pllp_init_dependencies(unsigned long pllp_rate); -static unsigned long tegra14_clk_shared_bus_update(struct clk *bus, - struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap); -static unsigned long tegra14_clk_cap_shared_bus(struct clk *bus, - unsigned long rate, unsigned long ceiling); -static int cpu_lp_backup_boost_begin(unsigned long *rate, unsigned int *start); -static void cpu_lp_backup_boost_end(unsigned long rate, unsigned int start); - -static bool detach_shared_bus; -module_param(detach_shared_bus, bool, 0644); - -static int use_dfll; - -/** -* Structure defining the fields for USB UTMI clocks Parameters. -*/ -struct utmi_clk_param { - /* CLK_M Frequency in KHz */ - u32 clk_m_frequency; - /* UTMIP PLL Enable Delay Count */ - u8 enable_delay_count; - /* UTMIP PLL Stable count */ - u8 stable_count; - /* UTMIP PLL Active delay count */ - u8 active_delay_count; - /* UTMIP PLL Xtal frequency count */ - u16 xtal_freq_count; -}; - -static const struct utmi_clk_param utmi_parameters[] = { -/* CLK_M_FREQ, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ - {38400000, 0x05, 0x96, 0x0C, 0x177}, - {19200000, 0x03, 0x4B, 0x06, 0x0BC}, - {12800000, 0x02, 0x32, 0x04, 0x07D}, - {9600000, 0x02, 0x26, 0x03, 0x05E}, -}; - -static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); -static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); - -#define MISC_GP_TRANSACTOR_SCRATCH_0 0x864 -#define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1) -#define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2) -#define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3) - -/* - * Some peripheral clocks share an enable bit, so refcount the enable bits - * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates - * with lock - */ -static DEFINE_SPINLOCK(periph_refcount_lock); -static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; - -#define clk_writel(value, reg) \ - __raw_writel(value, reg_clk_base + (reg)) -#define clk_readl(reg) \ - __raw_readl(reg_clk_base + (reg)) -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) - -#define clk_writel_delay(value, reg) \ - do { \ - __raw_writel((value), reg_clk_base + (reg)); \ - udelay(2); \ - } while (0) - -#define pll_writel_delay(value, reg) \ - do { \ - __raw_writel((value), reg_clk_base + (reg)); \ - udelay(1); \ - } while (0) - - -static inline int clk_set_div(struct clk *c, u32 n) -{ - return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); -} - -static inline u32 periph_clk_to_reg( - struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs) -{ - u32 reg = c->u.periph.clk_num / 32; - BUG_ON(reg >= RST_DEVICES_NUM); - if (reg < 3) - reg = reg_L + (reg * offs); - else if (reg < 5) - reg = reg_V + ((reg - 3) * offs); - else - reg = reg_X; - return reg; -} - -static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate, - u32 max_x, - u32 flags, u32 round_mode) -{ - s64 divider_ux1 = parent_rate; - if (!rate) - return -EINVAL; - - if (!(flags & DIV_U71_INT)) - divider_ux1 *= 2; - if (round_mode == ROUND_DIVIDER_UP) - divider_ux1 += rate - 1; - do_div(divider_ux1, rate); - if (flags & DIV_U71_INT) - divider_ux1 *= 2; - - if (divider_ux1 - 2 < 0) - return 0; - - if (divider_ux1 - 2 > max_x) - return -EINVAL; - -#if !DIVIDER_1_5_ALLOWED - if (divider_ux1 == 3) - divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2; -#endif - return divider_ux1 - 2; -} - -static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, - u32 flags, u32 round_mode) -{ - return clk_div_x1_get_divider(parent_rate, rate, 0xFF, - flags, round_mode); -} - -static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate, - u32 flags, u32 round_mode) -{ - return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF, - flags, round_mode); -} - -static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) -{ - s64 divider_u16; - - divider_u16 = parent_rate; - if (!rate) - return -EINVAL; - divider_u16 += rate - 1; - do_div(divider_u16, rate); - - if (divider_u16 - 1 < 0) - return 0; - - if (divider_u16 - 1 > 0xFFFF) - return -EINVAL; - - return divider_u16 - 1; -} - -static inline bool bus_user_is_slower(struct clk *a, struct clk *b) -{ - return a->u.shared_bus_user.client->max_rate * a->div < - b->u.shared_bus_user.client->max_rate * b->div; -} - -static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b) -{ - return a->u.shared_bus_user.rate * a->div < - b->u.shared_bus_user.rate * b->div; -} - -/* osc functions */ -static unsigned long tegra14_osc_autodetect_rate(struct clk *c) -{ - u32 osc_ctrl = clk_readl(OSC_CTRL); - u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; - u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; - - u32 spare = clk_readl(SPARE_REG); - u32 divisor = (spare & SPARE_REG_CLK_M_DIVISOR_MASK) - >> SPARE_REG_CLK_M_DIVISOR_SHIFT; - u32 spare_update = spare & ~SPARE_REG_CLK_M_DIVISOR_MASK; - - c->rate = tegra_clk_measure_input_freq(); - switch (c->rate) { - case 12000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - BUG_ON(divisor != 0); - break; - case 13000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - BUG_ON(divisor != 0); - break; - case 19200000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - BUG_ON(divisor != 0); - break; - case 26000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - BUG_ON(divisor != 0); - break; - case 16800000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - BUG_ON(divisor != 0); - break; - case 38400000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); - BUG_ON(divisor != 1); - spare_update |= (1 << SPARE_REG_CLK_M_DIVISOR_SHIFT); - break; - case 48000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); - BUG_ON(divisor != 3); - spare_update |= (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT); - break; - case 115200: /* fake 13M for QT */ - case 230400: /* fake 13M for QT */ - auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; - c->rate = 13000000; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - BUG_ON(divisor != 0); - break; - default: - pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); - BUG(); - } - - clk_writel(auto_clock_control, OSC_CTRL); - clk_writel(spare_update, SPARE_REG); - - return c->rate; -} - -static void tegra14_osc_init(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - tegra14_osc_autodetect_rate(c); -} - -static int tegra14_osc_enable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - return 0; -} - -static void tegra14_osc_disable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - WARN(1, "Attempting to disable main SoC clock\n"); -} - -static struct clk_ops tegra_osc_ops = { - .init = tegra14_osc_init, - .enable = tegra14_osc_enable, - .disable = tegra14_osc_disable, -}; - -static struct clk_ops tegra_osc_div_ops = { - .enable = tegra14_osc_enable, -}; - -static void tegra14_clk_m_init(struct clk *c) -{ - u32 spare = clk_readl(SPARE_REG); - u32 divisor = (spare & SPARE_REG_CLK_M_DIVISOR_MASK) - >> SPARE_REG_CLK_M_DIVISOR_SHIFT; - - pr_debug("%s on clock %s\n", __func__, c->name); - - c->div = divisor + 1; - c->mul = 1; - c->state = ON; -} - -static int tegra14_clk_m_enable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - return 0; -} - -static void tegra14_clk_m_disable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - WARN(1, "Attempting to disable main SoC clock\n"); -} - -static struct clk_ops tegra_clk_m_ops = { - .init = tegra14_clk_m_init, - .enable = tegra14_clk_m_enable, - .disable = tegra14_clk_m_disable, -}; - -/* PLL reference divider functions */ -static void tegra14_pll_ref_init(struct clk *c) -{ - u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; - pr_debug("%s on clock %s\n", __func__, c->name); - - switch (pll_ref_div) { - case OSC_CTRL_PLL_REF_DIV_1: - c->div = 1; - break; - case OSC_CTRL_PLL_REF_DIV_2: - c->div = 2; - break; - case OSC_CTRL_PLL_REF_DIV_4: - c->div = 4; - break; - default: - pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); - BUG(); - } - c->mul = 1; - c->state = ON; -} - -static struct clk_ops tegra_pll_ref_ops = { - .init = tegra14_pll_ref_init, - .enable = tegra14_osc_enable, - .disable = tegra14_osc_disable, -}; - -/* super clock functions */ -/* "super clocks" on tegra14x have two-stage muxes, fractional 7.1 divider and - * clock skipping super divider. We will ignore the clock skipping divider, - * since we can't lower the voltage when using the clock skip, but we can if - * we lower the PLL frequency. Note that skipping divider can and will be used - * by thermal control h/w for automatic throttling. There is also a 7.1 divider - * that most CPU super-clock inputs can be routed through. We will not use it - * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path - * and possible concurrency access issues with thermal h/w (7.1 divider setting - * share register with clock skipping divider) - */ -static void tegra14_super_clk_init(struct clk *c) -{ - u32 val; - int source; - int shift; - const struct clk_mux_sel *sel; - val = clk_readl(c->reg + SUPER_CLK_MUX); - c->state = ON; - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - source = (val >> shift) & SUPER_SOURCE_MASK; - - /* - * Enforce PLLX DIV2 bypass setting as early as possible. It is always - * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In - * case of booting on LP CPU, cclk_lp will be updated during the cpu - * rate change after boot, and cclk_g after the cluster switch.) - */ - if ((c->flags & DIV_U71) && (!is_lp_cluster())) { - val |= SUPER_LP_DIV2_BYPASS; - clk_writel_delay(val, c->reg); - } - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->value == source) - break; - } - BUG_ON(sel->input == NULL); - c->parent = sel->input; - - /* Update parent in case when LP CPU PLLX DIV2 bypassed */ - if ((c->flags & DIV_2) && (c->parent->flags & PLLX) && - (val & SUPER_LP_DIV2_BYPASS)) - c->parent = c->parent->parent; - - if (c->flags & DIV_U71) { - c->mul = 2; - c->div = 2; - - /* Make sure 7.1 divider is 1:1, clear s/w skipper control */ - /* FIXME: set? preserve? thermal h/w skipper control */ - val = clk_readl(c->reg + SUPER_CLK_DIVIDER); - BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK); - val = 0; - clk_writel(val, c->reg + SUPER_CLK_DIVIDER); - } else - clk_writel(0, c->reg + SUPER_CLK_DIVIDER); -} - -static int tegra14_super_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra14_super_clk_disable(struct clk *c) -{ - /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and - geared up g-mode super clock - mode switch may request to disable - either of them; accept request with no affect on h/w */ -} - -static int tegra14_super_clk_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - const struct clk_mux_sel *sel; - int shift; - - val = clk_readl(c->reg + SUPER_CLK_MUX); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - /* For LP mode super-clock switch between PLLX direct - and divided-by-2 outputs is allowed only when other - than PLLX clock source is current parent */ - if ((c->flags & DIV_2) && (p->flags & PLLX) && - ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) { - if (c->parent->flags & PLLX) - return -EINVAL; - val ^= SUPER_LP_DIV2_BYPASS; - clk_writel_delay(val, c->reg); - } - val &= ~(SUPER_SOURCE_MASK << shift); - val |= (sel->value & SUPER_SOURCE_MASK) << shift; - - if (c->flags & DIV_U71) { - /* Make sure 7.1 divider is 1:1 */ - u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER); - BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK); - } - - if (c->refcnt) - clk_enable(p); - - clk_writel_delay(val, c->reg); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - return -EINVAL; -} - -/* - * Do not use super clocks "skippers", since dividing using a clock skipper - * does not allow the voltage to be scaled down. Instead adjust the rate of - * the parent clock. This requires that the parent of a super clock have no - * other children, otherwise the rate will change underneath the other - * children. - */ -static int tegra14_super_clk_set_rate(struct clk *c, unsigned long rate) -{ - /* In tegra14_cpu_clk_set_plls() and tegra14_sbus_cmplx_set_rate() - * this call is skipped by directly setting rate of source plls. If we - * ever use 7.1 divider at other than 1:1 setting, or exercise s/w - * skipper control, not only this function, but cpu and sbus set_rate - * APIs should be changed accordingly. - */ - return clk_set_rate(c->parent, rate); -} - -#ifdef CONFIG_PM_SLEEP -static void tegra14_super_clk_resume(struct clk *c, struct clk *backup, - u32 setting) -{ - u32 val; - const struct clk_mux_sel *sel; - int shift; - - /* For sclk and cclk_g super clock just restore saved value */ - if (!(c->flags & DIV_2)) { - clk_writel_delay(setting, c->reg); - return; - } - - /* - * For cclk_lp supper clock: switch to backup (= not PLLX) source, - * safely restore PLLX DIV2 bypass, and only then restore full - * setting - */ - val = clk_readl(c->reg); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == backup) { - val &= ~(SUPER_SOURCE_MASK << shift); - val |= (sel->value & SUPER_SOURCE_MASK) << shift; - - BUG_ON(backup->flags & PLLX); - clk_writel_delay(val, c->reg); - - val &= ~SUPER_LP_DIV2_BYPASS; - val |= (setting & SUPER_LP_DIV2_BYPASS); - clk_writel_delay(val, c->reg); - clk_writel_delay(setting, c->reg); - return; - } - } - BUG(); -} -#endif - -static struct clk_ops tegra_super_ops = { - .init = tegra14_super_clk_init, - .enable = tegra14_super_clk_enable, - .disable = tegra14_super_clk_disable, - .set_parent = tegra14_super_clk_set_parent, - .set_rate = tegra14_super_clk_set_rate, -}; - -static int tegra14_twd_clk_set_rate(struct clk *c, unsigned long rate) -{ - /* The input value 'rate' is the clock rate of the CPU complex. */ - c->rate = (rate * c->mul) / c->div; - return 0; -} - -static struct clk_ops tegra14_twd_ops = { - .set_rate = tegra14_twd_clk_set_rate, -}; - -static struct clk tegra14_clk_twd = { - /* NOTE: The twd clock must have *NO* parent. It's rate is directly - updated by tegra3_cpu_cmplx_clk_set_rate() because the - frequency change notifer for the twd is called in an - atomic context which cannot take a mutex. */ - .name = "twd", - .ops = &tegra14_twd_ops, - .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */ - .mul = 1, - .div = 2, -}; - -/* virtual cpu clock functions */ -/* some clocks can not be stopped (cpu, memory bus) while the SoC is running. - To change the frequency of these clocks, the parent pll may need to be - reprogrammed, so the clock must be moved off the pll, the pll reprogrammed, - and then the clock moved back to the pll. To hide this sequence, a virtual - clock handles it. - */ -static void tegra14_cpu_clk_init(struct clk *c) -{ - c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G)) ? ON : OFF; -} - -static int tegra14_cpu_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra14_cpu_clk_disable(struct clk *c) -{ - /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock - and geared up g-mode clock - mode switch may request to disable - either of them; accept request with no affect on h/w */ -} - -static int tegra14_cpu_clk_set_plls(struct clk *c, unsigned long rate, - unsigned long old_rate) -{ - int ret = 0; - bool on_main = false; - unsigned long backup_rate, main_rate; - unsigned long vco_min = c->u.cpu.main->u.pll.vco_min; - - /* - * Take an extra reference to the main pll so it doesn't turn off when - * we move the cpu off of it. If possible, use main pll dynamic ramp - * to reach target rate in one shot. Otherwise, use dynamic ramp to - * lower current rate to pll VCO minimum level before switching to - * backup source. - */ - if (c->parent->parent == c->u.cpu.main) { - bool dramp = (rate > c->u.cpu.backup_rate) && - tegra14_is_dyn_ramp(c->u.cpu.main, rate, false); - clk_enable(c->u.cpu.main); - on_main = true; - - if (dramp || - ((old_rate > vco_min) && - tegra14_is_dyn_ramp(c->u.cpu.main, vco_min, false))) { - main_rate = dramp ? rate : vco_min; - ret = clk_set_rate(c->u.cpu.main, main_rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", main_rate, c->u.cpu.main->name); - goto out; - } - if (dramp) - goto out; - } else if (old_rate > vco_min) { -#if PLLXC_USE_DYN_RAMP - pr_warn("No dynamic ramp down: %s: %lu to %lu\n", - c->u.cpu.main->name, old_rate, vco_min); -#endif - } - } - - /* Switch to back-up source, and stay on it if target rate is below - backup rate */ - if (c->parent->parent != c->u.cpu.backup) { - ret = clk_set_parent(c->parent, c->u.cpu.backup); - if (ret) { - pr_err("Failed to switch cpu to %s\n", - c->u.cpu.backup->name); - goto out; - } - } - - backup_rate = min(rate, c->u.cpu.backup_rate); - if (backup_rate != clk_get_rate_locked(c)) { - ret = clk_set_rate(c->u.cpu.backup, backup_rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on backup source\n", - backup_rate); - goto out; - } - } - if (rate == backup_rate) - goto out; - - /* Switch from backup source to main at rate not exceeding pll VCO - minimum. Use dynamic ramp to reach target rate if it is above VCO - minimum. */ - main_rate = rate; - if (rate > vco_min) { - if (tegra14_is_dyn_ramp(c->u.cpu.main, rate, true)) - main_rate = vco_min; -#if PLLXC_USE_DYN_RAMP - else - pr_warn("No dynamic ramp up: %s: %lu to %lu\n", - c->u.cpu.main->name, vco_min, rate); -#endif - } - - ret = clk_set_rate(c->u.cpu.main, main_rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", main_rate, c->u.cpu.main->name); - goto out; - } - ret = clk_set_parent(c->parent, c->u.cpu.main); - if (ret) { - pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name); - goto out; - } - if (rate != main_rate) { - ret = clk_set_rate(c->u.cpu.main, rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", rate, c->u.cpu.main->name); - goto out; - } - } - -out: - if (on_main) - clk_disable(c->u.cpu.main); - - return ret; -} - -static int tegra14_cpu_clk_dfll_on(struct clk *c, unsigned long rate, - unsigned long old_rate) -{ - int ret; - struct clk *dfll = c->u.cpu.dynamic; - unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min; - - /* dfll rate request */ - ret = clk_set_rate(dfll, rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", rate, dfll->name); - return ret; - } - - /* 1st time - switch to dfll */ - if (c->parent->parent != dfll) { - if (max(old_rate, rate) < dfll_rate_min) { - /* set interim cpu dvfs rate at dfll_rate_min to - prevent voltage drop below dfll Vmin */ - ret = tegra_dvfs_set_rate(c, dfll_rate_min); - if (ret) { - pr_err("Failed to set cpu dvfs rate %lu\n", - dfll_rate_min); - return ret; - } - } - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true); - ret = clk_set_parent(c->parent, dfll); - if (ret) { - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - pr_err("Failed to switch cpu to %s\n", dfll->name); - return ret; - } - ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate); - - /* prevent legacy dvfs voltage scaling */ - tegra_dvfs_dfll_mode_set(c->dvfs, rate); - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - } - return 0; -} - -static int tegra14_cpu_clk_dfll_off(struct clk *c, unsigned long rate, - unsigned long old_rate) -{ - int ret; - struct clk *pll; - struct clk *dfll = c->u.cpu.dynamic; - unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min; - - rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost); - pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main; - dfll_rate_min = max(rate, dfll_rate_min); - - /* set target rate last time in dfll mode */ - if (old_rate != dfll_rate_min) { - ret = tegra_dvfs_set_rate(c, dfll_rate_min); - if (!ret) - ret = clk_set_rate(dfll, dfll_rate_min); - - if (ret) { - pr_err("Failed to set cpu rate %lu on source %s\n", - dfll_rate_min, dfll->name); - return ret; - } - } - - /* unlock dfll - release volatge rail control */ - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true); - ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0); - if (ret) { - pr_err("Failed to unlock %s\n", dfll->name); - goto back_to_dfll; - } - - /* restore legacy dvfs operations and set appropriate voltage */ - ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min); - if (ret) { - pr_err("Failed to set cpu rail for rate %lu\n", rate); - goto back_to_dfll; - } - - /* set pll to target rate and return to pll source */ - ret = clk_set_rate(pll, rate); - if (ret) { - pr_err("Failed to set cpu rate %lu on source" - " %s\n", rate, pll->name); - goto back_to_dfll; - } - ret = clk_set_parent(c->parent, pll); - if (ret) { - pr_err("Failed to switch cpu to %s\n", pll->name); - goto back_to_dfll; - } - - /* If going up, adjust voltage here (down path is taken care of by the - framework after set rate exit) */ - if (old_rate <= rate) - tegra_dvfs_set_rate(c, rate); - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - return 0; - -back_to_dfll: - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - tegra_dvfs_dfll_mode_set(c->dvfs, old_rate); - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - return ret; -} - -static int tegra14_cpu_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - unsigned long old_rate = clk_get_rate_locked(c); - bool has_dfll = c->u.cpu.dynamic && - (c->u.cpu.dynamic->state != UNINITIALIZED); - bool is_dfll = c->parent->parent == c->u.cpu.dynamic; - - if (c->dvfs) { - if (!c->dvfs->dvfs_rail) - return -ENOSYS; - else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) && - (c->boot_rate < rate)) { - WARN(1, "Increasing CPU rate while regulator is not" - " ready is not allowed\n"); - return -ENOSYS; - } - } - if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) { - if (tegra_dvfs_is_dfll_range(c->dvfs, rate)) - return tegra14_cpu_clk_dfll_on(c, rate, old_rate); - else if (is_dfll) - return tegra14_cpu_clk_dfll_off(c, rate, old_rate); - } - - write_seqcount_begin(&c->u.cpu.backup_seqcnt); - ret = tegra14_cpu_clk_set_plls(c, rate, old_rate); - write_seqcount_end(&c->u.cpu.backup_seqcnt); - return ret; -} - -static long tegra14_cpu_clk_round_rate(struct clk *c, unsigned long rate) -{ - unsigned long max_rate = c->max_rate; - - /* Remove dfll boost to maximum rate when running on PLL */ - if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate)) - max_rate -= c->dvfs->dfll_data.max_rate_boost; - - if (rate > max_rate) - rate = max_rate; - else if (rate < c->min_rate) - rate = c->min_rate; - return rate; -} - -static struct clk_ops tegra_cpu_ops = { - .init = tegra14_cpu_clk_init, - .enable = tegra14_cpu_clk_enable, - .disable = tegra14_cpu_clk_disable, - .set_rate = tegra14_cpu_clk_set_rate, - .round_rate = tegra14_cpu_clk_round_rate, -}; - - -static void tegra14_cpu_cmplx_clk_init(struct clk *c) -{ - int i = !!is_lp_cluster(); - - BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G); - BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP); - c->parent = c->inputs[i].input; -} - -/* cpu complex clock provides second level vitualization (on top of - cpu virtual cpu rate control) in order to hide the CPU mode switch - sequence */ -#if PARAMETERIZE_CLUSTER_SWITCH -static unsigned int switch_delay; -static unsigned int switch_flags; -static DEFINE_SPINLOCK(parameters_lock); - -void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags) -{ - spin_lock(¶meters_lock); - switch_delay = us; - switch_flags = flags; - spin_unlock(¶meters_lock); -} -#endif - -static int tegra14_cpu_cmplx_clk_enable(struct clk *c) -{ - return 0; -} - -static void tegra14_cpu_cmplx_clk_disable(struct clk *c) -{ - pr_debug("%s on clock %s\n", __func__, c->name); - - /* oops - don't disable the CPU complex clock! */ - BUG(); -} - -static int tegra14_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long flags; - int ret; - struct clk *parent = c->parent; - - if (!parent->ops || !parent->ops->set_rate) - return -ENOSYS; - - clk_lock_save(parent, &flags); - - ret = clk_set_rate_locked(parent, rate); - - clk_unlock_restore(parent, &flags); - - return ret; -} - -static int tegra14_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) -{ - int ret; - unsigned int flags, delay; - const struct clk_mux_sel *sel; - unsigned long rate = clk_get_rate(c->parent); - struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic; - struct clk *p_source_old = NULL; - struct clk *p_source; - - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G)); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) - break; - } - if (!sel->input) - return -EINVAL; - -#if PARAMETERIZE_CLUSTER_SWITCH - spin_lock(¶meters_lock); - flags = switch_flags; - delay = switch_delay; - switch_flags = 0; - spin_unlock(¶meters_lock); - - if (flags) { - /* over/under-clocking after switch - allow, but update rate */ - if ((rate > p->max_rate) || (rate < p->min_rate)) { - rate = rate > p->max_rate ? p->max_rate : p->min_rate; - ret = clk_set_rate(c->parent, rate); - if (ret) { - pr_err("%s: Failed to set rate %lu for %s\n", - __func__, rate, p->name); - return ret; - } - } - } else -#endif - { - if (rate > p->max_rate) { /* over-clocking - no switch */ - pr_warn("%s: No %s mode switch to %s at rate %lu\n", - __func__, c->name, p->name, rate); - return -ECANCELED; - } - flags = TEGRA_POWER_CLUSTER_IMMEDIATE; - flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT; - delay = 0; - } - flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP : - TEGRA_POWER_CLUSTER_G; - - if (p == c->parent) { - if (flags & TEGRA_POWER_CLUSTER_FORCE) { - /* Allow parameterized switch to the same mode */ - ret = tegra_cluster_control(delay, flags); - if (ret) - pr_err("%s: Failed to force %s mode to %s\n", - __func__, c->name, p->name); - return ret; - } - return 0; /* already switched - exit */ - } - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true); - if (c->parent->parent->parent == dfll) { - /* G (DFLL selected as clock source) => LP switch: - * turn DFLL into open loop mode ("release" VDD_CPU rail) - * select target p_source for LP, and get its rate ready - */ - ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0); - if (ret) - goto abort; - - p_source = rate <= p->u.cpu.backup_rate ? - p->u.cpu.backup : p->u.cpu.main; - ret = clk_set_rate(p_source, rate); - if (ret) - goto abort; - } else if ((p->parent->parent == dfll) || - (p->dvfs && tegra_dvfs_is_dfll_range(p->dvfs, rate))) { - /* LP => G (DFLL selected as clock source) switch: - * set DFLL rate ready (DFLL is still disabled) - * (set target p_source as dfll, G source is already selected) - */ - p_source = dfll; - ret = clk_set_rate(dfll, - tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate : - max(rate, p->dvfs->dfll_data.use_dfll_rate_min)); - if (ret) - goto abort; - - ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail, dfll); - if (ret) - goto abort; - - } else - /* DFLL is not selected on either side of the switch: - * set target p_source equal to current clock source - */ - p_source = c->parent->parent->parent; - - /* Switch new parent to target clock source if necessary */ - if (p->parent->parent != p_source) { - clk_enable(p->parent->parent); - clk_enable(p->parent); - p_source_old = p->parent->parent; - ret = clk_set_parent(p->parent, p_source); - if (ret) { - pr_err("%s: Failed to set parent %s for %s\n", - __func__, p_source->name, p->name); - goto abort; - } - } - - /* Enabling new parent scales new mode voltage rail in advanvce - before the switch happens (if p_source is DFLL: open loop mode) */ - if (c->refcnt) - clk_enable(p); - - /* switch CPU mode */ - ret = tegra_cluster_control(delay, flags); - if (ret) { - if (c->refcnt) - clk_disable(p); - pr_err("%s: Failed to switch %s mode to %s\n", - __func__, c->name, p->name); - goto abort; - } - - /* - * Lock DFLL now (resume closed loop VDD_CPU control). - * G CPU operations are resumed on DFLL if it was the last G CPU - * clock source, or if resume rate is in DFLL usage range in case - * when auto-switch between PLL and DFLL is enabled. - */ - if (p_source == dfll) { - if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) { - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - } else { - clk_set_rate(dfll, rate); - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - tegra_dvfs_dfll_mode_set(p->dvfs, rate); - } - } - - /* Disabling old parent scales old mode voltage rail */ - if (c->refcnt) - clk_disable(c->parent); - if (p_source_old) { - clk_disable(p->parent); - clk_disable(p_source_old); - } - - clk_reparent(c, p); - - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - return 0; - -abort: - /* Re-lock DFLL if necessary after aborted switch */ - if (c->parent->parent->parent == dfll) { - clk_set_rate(dfll, rate); - tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1); - } - if (p_source_old) { - clk_disable(p->parent); - clk_disable(p_source_old); - } - tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false); - - pr_err("%s: aborted switch from %s to %s\n", - __func__, c->parent->name, p->name); - return ret; -} - -static long tegra14_cpu_cmplx_round_rate(struct clk *c, - unsigned long rate) -{ - return clk_round_rate(c->parent, rate); -} - -static struct clk_ops tegra_cpu_cmplx_ops = { - .init = tegra14_cpu_cmplx_clk_init, - .enable = tegra14_cpu_cmplx_clk_enable, - .disable = tegra14_cpu_cmplx_clk_disable, - .set_rate = tegra14_cpu_cmplx_clk_set_rate, - .set_parent = tegra14_cpu_cmplx_clk_set_parent, - .round_rate = tegra14_cpu_cmplx_round_rate, -}; - -/* virtual cop clock functions. Used to acquire the fake 'cop' clock to - * reset the COP block (i.e. AVP) */ -static void tegra14_cop_clk_reset(struct clk *c, bool assert) -{ - unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L; - - pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); - clk_writel(1 << 1, reg); -} - -static struct clk_ops tegra_cop_ops = { - .reset = tegra14_cop_clk_reset, -}; - -/* bus clock functions */ -static DEFINE_SPINLOCK(bus_clk_lock); - -static int bus_set_div(struct clk *c, int div) -{ - u32 val; - unsigned long flags; - - if (!div || (div > (BUS_CLK_DIV_MASK + 1))) - return -EINVAL; - - spin_lock_irqsave(&bus_clk_lock, flags); - val = clk_readl(c->reg); - val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); - val |= (div - 1) << c->reg_shift; - clk_writel(val, c->reg); - c->div = div; - spin_unlock_irqrestore(&bus_clk_lock, flags); - - return 0; -} - -static void tegra14_bus_clk_init(struct clk *c) -{ - u32 val = clk_readl(c->reg); - c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; - c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; - c->mul = 1; -} - -static int tegra14_bus_clk_enable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - val &= ~(BUS_CLK_DISABLE << c->reg_shift); - clk_writel(val, c->reg); - return 0; -} - -static void tegra14_bus_clk_disable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - val |= BUS_CLK_DISABLE << c->reg_shift; - clk_writel(val, c->reg); -} - -static int tegra14_bus_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(c->parent); - int i; - for (i = 1; i <= 4; i++) { - if (rate >= parent_rate / i) - return bus_set_div(c, i); - } - return -EINVAL; -} - -static struct clk_ops tegra_bus_ops = { - .init = tegra14_bus_clk_init, - .enable = tegra14_bus_clk_enable, - .disable = tegra14_bus_clk_disable, - .set_rate = tegra14_bus_clk_set_rate, -}; - -/* Virtual system bus complex clock is used to hide the sequence of - changing sclk/hclk/pclk parents and dividers to configure requested - sclk target rate. */ -static void tegra14_sbus_cmplx_init(struct clk *c) -{ - unsigned long rate; - - c->max_rate = c->parent->max_rate; - c->min_rate = c->parent->min_rate; - - /* Threshold must be an exact proper factor of low range parent, - and both low/high range parents have 7.1 fractional dividers */ - rate = clk_get_rate(c->u.system.sclk_low->parent); - if (c->u.system.threshold) { - BUG_ON(c->u.system.threshold > rate) ; - BUG_ON((rate % c->u.system.threshold) != 0); - } - BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71)); - BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71)); -} - -/* This special sbus round function is implemented because: - * - * (a) sbus complex clock source is selected automatically based on rate - * - * (b) since sbus is a shared bus, and its frequency is set to the highest - * enabled shared_bus_user clock, the target rate should be rounded up divider - * ladder (if max limit allows it) - for pll_div and peripheral_div common is - * rounding down - special case again. - * - * Note that final rate is trimmed (not rounded up) to avoid spiraling up in - * recursive calls. Lost 1Hz is added in tegra14_sbus_cmplx_set_rate before - * actually setting divider rate. - */ -static long tegra14_sbus_cmplx_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - int divider; - unsigned long source_rate, round_rate; - struct clk *new_parent; - - rate = max(rate, c->min_rate); - - new_parent = (rate <= c->u.system.threshold) ? - c->u.system.sclk_low : c->u.system.sclk_high; - source_rate = clk_get_rate(new_parent->parent); - - divider = clk_div71_get_divider(source_rate, rate, - new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP); - if (divider < 0) - return c->min_rate; - - if (divider == 1) - divider = 0; - - round_rate = source_rate * 2 / (divider + 2); - if (round_rate > c->max_rate) { - divider += new_parent->flags & DIV_U71_INT ? 2 : 1; -#if !DIVIDER_1_5_ALLOWED - divider = max(2, divider); -#endif - round_rate = source_rate * 2 / (divider + 2); - } - - if (new_parent == c->u.system.sclk_high) { - /* Prevent oscillation across threshold */ - if (round_rate <= c->u.system.threshold) - round_rate = c->u.system.threshold; - } - return round_rate; -} - -static long tegra14_sbus_cmplx_round_rate(struct clk *c, unsigned long rate) -{ - return tegra14_sbus_cmplx_round_updown(c, rate, true); -} - -/* - * Limitations on SCLK/HCLK/PCLK dividers: - * (A) H/w limitation: - * if SCLK >= 60MHz, SCLK:PCLK >= 2 - * (B) S/w policy limitation, in addition to (A): - * if any APB bus shared user request is enabled, HCLK:PCLK >= 2 - * Reason for (B): assuming APB bus shared user has requested X < 60MHz, - * HCLK = PCLK = X, and new AHB user is coming on-line requesting Y >= 60MHz, - * we can consider 2 paths depending on order of changing HCLK rate and - * HCLK:PCLK ratio - * (i) HCLK:PCLK = X:X => Y:Y* => Y:Y/2, (*) violates rule (A) - * (ii) HCLK:PCLK = X:X => X:X/2* => Y:Y/2, (*) under-clocks APB user - * In this case we can not guarantee safe transition from HCLK:PCLK = 1:1 - * below 60MHz to HCLK rate above 60MHz without under-clocking APB user. - * Hence, policy (B). - * - * Note: when there are no request from APB users, path (ii) can be used to - * increase HCLK above 60MHz, and HCLK:PCLK = 1:1 is allowed. - */ - -#define SCLK_PCLK_UNITY_RATIO_RATE_MAX 60000000 -#define BUS_AHB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL) -#define BUS_APB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL) - -static int tegra14_sbus_cmplx_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - struct clk *new_parent; - - /* - * Configure SCLK/HCLK/PCLK guranteed safe combination: - * - select the appropriate sclk parent - * - keep hclk at the same rate as sclk - * - set pclk at 1:2 rate of hclk - */ - bus_set_div(c->u.system.pclk, 2); - bus_set_div(c->u.system.hclk, 1); - c->child_bus->child_bus->div = 2; - c->child_bus->div = 1; - - if (rate == clk_get_rate_locked(c)) - return 0; - - new_parent = (rate <= c->u.system.threshold) ? - c->u.system.sclk_low : c->u.system.sclk_high; - - ret = clk_set_rate(new_parent, rate + 1); - if (ret) { - pr_err("Failed to set sclk source %s to %lu\n", - new_parent->name, rate); - return ret; - } - - if (new_parent != clk_get_parent(c->parent)) { - ret = clk_set_parent(c->parent, new_parent); - if (ret) { - pr_err("Failed to switch sclk source to %s\n", - new_parent->name); - return ret; - } - } - - return 0; -} - -static int tegra14_clk_sbus_update(struct clk *bus) -{ - int ret, div; - bool p_requested; - unsigned long s_rate, h_rate, p_rate, ceiling; - struct clk *ahb, *apb; - - if (detach_shared_bus) - return 0; - - s_rate = tegra14_clk_shared_bus_update(bus, &ahb, &apb, &ceiling); - if (bus->override_rate) - return clk_set_rate_locked(bus, s_rate); - - ahb = bus->child_bus; - apb = ahb->child_bus; - h_rate = ahb->u.shared_bus_user.rate; - p_rate = apb->u.shared_bus_user.rate; - p_requested = apb->refcnt > 1; - - /* Propagate ratio requirements up from PCLK to SCLK */ - if (p_requested) - h_rate = max(h_rate, p_rate * 2); - s_rate = max(s_rate, h_rate); - if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX) - s_rate = max(s_rate, p_rate * 2); - - /* Propagate cap requirements down from SCLK to PCLK */ - s_rate = tegra14_clk_cap_shared_bus(bus, s_rate, ceiling); - if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX) - p_rate = min(p_rate, s_rate / 2); - h_rate = min(h_rate, s_rate); - if (p_requested) - p_rate = min(p_rate, h_rate / 2); - - - /* Set new sclk rate in safe 1:1:2, rounded "up" configuration */ - ret = clk_set_rate_locked(bus, s_rate); - if (ret) - return ret; - - /* Finally settle new bus divider values */ - s_rate = clk_get_rate_locked(bus); - div = min(s_rate / h_rate, BUS_AHB_DIV_MAX); - if (div != 1) { - bus_set_div(bus->u.system.hclk, div); - ahb->div = div; - } - - h_rate = clk_get_rate(bus->u.system.hclk); - div = min(h_rate / p_rate, BUS_APB_DIV_MAX); - if (div != 2) { - bus_set_div(bus->u.system.pclk, div); - apb->div = div; - } - - return 0; -} - -static struct clk_ops tegra_sbus_cmplx_ops = { - .init = tegra14_sbus_cmplx_init, - .set_rate = tegra14_sbus_cmplx_set_rate, - .round_rate = tegra14_sbus_cmplx_round_rate, - .round_rate_updown = tegra14_sbus_cmplx_round_updown, - .shared_bus_update = tegra14_clk_sbus_update, -}; - -/* Blink output functions */ - -static void tegra14_blink_clk_init(struct clk *c) -{ - u32 val; - - val = pmc_readl(PMC_CTRL); - c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; - c->mul = 1; - val = pmc_readl(c->reg); - - if (val & PMC_BLINK_TIMER_ENB) { - unsigned int on_off; - - on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & - PMC_BLINK_TIMER_DATA_ON_MASK; - val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off += val; - /* each tick in the blink timer is 4 32KHz clocks */ - c->div = on_off * 4; - } else { - c->div = 1; - } -} - -static int tegra14_blink_clk_enable(struct clk *c) -{ - u32 val; - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); - - val = pmc_readl(PMC_CTRL); - pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); - - return 0; -} - -static void tegra14_blink_clk_disable(struct clk *c) -{ - u32 val; - - val = pmc_readl(PMC_CTRL); - pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); -} - -static int tegra14_blink_clk_set_rate(struct clk *c, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(c->parent); - if (rate >= parent_rate) { - c->div = 1; - pmc_writel(0, c->reg); - } else { - unsigned int on_off; - u32 val; - - on_off = DIV_ROUND_UP(parent_rate / 8, rate); - c->div = on_off * 8; - - val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << - PMC_BLINK_TIMER_DATA_ON_SHIFT; - on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val |= on_off; - val |= PMC_BLINK_TIMER_ENB; - pmc_writel(val, c->reg); - } - - return 0; -} - -static struct clk_ops tegra_blink_clk_ops = { - .init = &tegra14_blink_clk_init, - .enable = &tegra14_blink_clk_enable, - .disable = &tegra14_blink_clk_disable, - .set_rate = &tegra14_blink_clk_set_rate, -}; - -/* PLL Functions */ -static int tegra14_pll_clk_wait_for_lock( - struct clk *c, u32 lock_reg, u32 lock_bits) -{ -#if USE_PLL_LOCK_BITS - int i; - u32 val = 0; - - for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) { - udelay(PLL_PRE_LOCK_DELAY); - val = clk_readl(lock_reg); - if ((val & lock_bits) == lock_bits) { - udelay(PLL_POST_LOCK_DELAY); - return 0; - } - } - - /* PLLCX lock bits may fluctuate after the lock - do detailed reporting - at debug level (phase lock bit happens to uniquely identify PLLCX) */ - if (lock_bits & PLLCX_BASE_PHASE_LOCK) { - pr_debug("Timed out waiting %s locks: %s %s not set\n", c->name, - val & PLL_BASE_LOCK ? "" : "frequency_lock", - val & PLLCX_BASE_PHASE_LOCK ? "" : "phase_lock"); - pr_debug("base = 0x%x\n", val); - pr_debug("misc = 0x%x\n", clk_readl(c->reg + PLL_MISC(c))); - pr_debug("misc1 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 1))); - pr_debug("misc2 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 2))); - pr_debug("misc3 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 3))); - return -ETIMEDOUT; - } else { - pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n", - c->name, lock_reg, val); - return -ETIMEDOUT; - } -#endif - udelay(c->u.pll.lock_delay); - return 0; -} - -static void tegra14_utmi_param_configure(struct clk *c) -{ - u32 reg; - int i; - unsigned long main_rate = - clk_get_rate(tegra_get_clock_by_name("clk_m")); - - for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { - if (main_rate == utmi_parameters[i].clk_m_frequency) - break; - } - - if (i >= ARRAY_SIZE(utmi_parameters)) { - pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); - return; - } - - reg = clk_readl(UTMIP_PLL_CFG2); - - /* Program UTMIP PLL stable and active counts */ - /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ - reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); - reg |= UTMIP_PLL_CFG2_STABLE_COUNT( - utmi_parameters[i].stable_count); - - reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); - - reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( - utmi_parameters[i].active_delay_count); - - /* Remove power downs from UTMIP PLL control bits */ - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; - - clk_writel(reg, UTMIP_PLL_CFG2); - - /* Program UTMIP PLL delay and oscillator frequency counts */ - reg = clk_readl(UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); - - reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( - utmi_parameters[i].enable_delay_count); - - reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); - reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( - utmi_parameters[i].xtal_freq_count); - - /* Remove power downs from UTMIP PLL control bits */ - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; - clk_writel(reg, UTMIP_PLL_CFG1); - - reg = clk_readl(UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; - clk_writel(reg, UTMIP_PLL_CFG1); - - udelay(1); - - /* Setup SW override of UTMIPLL assuming USB2.0 - ports are assigned to USB2 */ - reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0); - reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; - reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; - clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0); - - udelay(1); -} - -static void tegra14_pll_clk_init(struct clk *c) -{ - u32 val = clk_readl(c->reg + PLL_BASE); - - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { - const struct clk_pll_freq_table *sel; - unsigned long input_rate = clk_get_rate(c->parent); - c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE; - - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && - sel->output_rate == c->u.pll.fixed_rate) { - c->mul = sel->n; - c->div = sel->m * sel->p; - return; - } - } - pr_err("Clock %s has unknown fixed frequency\n", c->name); - BUG(); - } else if (val & PLL_BASE_BYPASS) { - c->mul = 1; - c->div = 1; - } else { - c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - if (c->flags & PLLU) - c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; - else - c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> - PLL_BASE_DIVP_SHIFT)); - } - - if (c->flags & PLL_FIXED) - c->u.pll.fixed_rate = clk_get_rate_locked(c); - - if (c->flags & PLLU) { - /* Configure UTMI PLL power management */ - tegra14_utmi_param_configure(c); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLLU_BASE_OVERRIDE; - clk_writel(val, c->reg + PLL_BASE); - } -} - -static int tegra14_pll_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - -#if USE_PLL_LOCK_BITS - /* toggle lock enable bit to reset lock detection circuit (couple - register reads provide enough duration for reset pulse) */ - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLL_MISC_LOCK_ENABLE(c); - clk_writel(val, c->reg + PLL_MISC(c)); - val = clk_readl(c->reg + PLL_MISC(c)); - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLL_MISC_LOCK_ENABLE(c); - clk_writel(val, c->reg + PLL_MISC(c)); -#endif - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_BYPASS; - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - tegra14_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - - return 0; -} - -static void tegra14_pll_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - clk_writel(val, c->reg); -} - -static u8 get_pll_cpcon(struct clk *c, u16 n) -{ - if (c->flags & PLLD) { - if (n >= 1000) - return 15; - else if (n >= 600) - return 12; - else if (n >= 300) - return 8; - else if (n >= 50) - return 3; - else - return 2; - } - return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON; -} - -/* Special comparison frequency selection for PLLD at 19.2MHz reference rate */ -unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate, - unsigned long rate, unsigned long *vco) -{ - if (!(c->flags & PLLD) || (input_rate != 19200000)) - return 0; - - *vco = c->u.pll.vco_min; - - if (rate <= 250000000) - return 4800000; - else if (rate <= 500000000) - return 2400000; - else - return 1200000; -} - -/* Common comparison frequency selection */ -unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate, - unsigned long rate, unsigned long *vco) -{ - unsigned long cfreq = 0; - - switch (input_rate) { - case 12000000: - case 26000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; - break; - case 13000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; - break; - case 16800000: - case 19200000: - cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; - break; - default: - if (c->parent->flags & DIV_U71_FIXED) { - /* PLLP_OUT1 rate is not in PLLA table */ - pr_warn("%s: failed %s ref/out rates %lu/%lu\n", - __func__, c->name, input_rate, rate); - cfreq = input_rate/(input_rate/1000000); - break; - } - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - } - - /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */ - *vco = max(200 * cfreq, c->u.pll.vco_min); - return cfreq; -} - -static int tegra14_pll_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, p_div, old_base; - unsigned long input_rate; - const struct clk_pll_freq_table *sel; - struct clk_pll_freq_table cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->flags & PLL_FIXED) { - int ret = 0; - if (rate != c->u.pll.fixed_rate) { - pr_err("%s: Can not change %s fixed rate %lu to %lu\n", - __func__, c->name, c->u.pll.fixed_rate, rate); - ret = -EINVAL; - } - return ret; - } - - p_div = 0; - input_rate = clk_get_rate(c->parent); - - /* Check if the target rate is tabulated */ - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - if (c->flags & PLLU) { - BUG_ON(sel->p < 1 || sel->p > 2); - if (sel->p == 1) - p_div = PLLU_BASE_POST_DIV; - } else { - BUG_ON(sel->p < 1); - for (val = sel->p; val > 1; val >>= 1, p_div++) - ; - p_div <<= PLL_BASE_DIVP_SHIFT; - } - break; - } - } - - /* Configure out-of-table rate */ - if (sel->input_rate == 0) { - unsigned long cfreq, vco; - BUG_ON(c->flags & PLLU); - sel = &cfg; - - /* If available, use pll specific algorithm to select comparison - frequency, and vco target */ - cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco); - if (!cfreq) - cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco); - - /* Select output divider to get Vco rate above the target */ - for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++) - cfg.output_rate <<= 1; - - /* - * Below we rely on the fact that in either special, or common - * case input rate is an exact multiple of comparison rate. - * However, the same is not guaranteed for Vco rate. - */ - cfg.p = 0x1 << p_div; - cfg.m = input_rate / cfreq; - cfg.n = cfg.output_rate / cfreq; - if (cfg.n * cfreq < vco) { - cfg.n++; - cfg.output_rate = cfreq * cfg.n; - } - cfg.cpcon = get_pll_cpcon(c, cfg.n); - - if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || - (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || - (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || - (cfg.output_rate > c->u.pll.vco_max)) { - pr_err("%s: Failed to set %s out-of-table rate %lu\n", - __func__, c->name, rate); - return -EINVAL; - } - p_div <<= PLL_BASE_DIVP_SHIFT; - } - - c->mul = sel->n; - c->div = sel->m * sel->p; - - old_base = val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | - ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; - if (val == old_base) - return 0; - - if (c->state == ON) { - tegra14_pll_clk_disable(c); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - } - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLL_HAS_CPCON) { - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLL_MISC_CPCON_MASK; - val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; - if (c->flags & (PLLU | PLLD)) { - val &= ~PLL_MISC_LFCON_MASK; - val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT; - } - clk_writel(val, c->reg + PLL_MISC(c)); - } - - if (c->state == ON) - tegra14_pll_clk_enable(c); - - return 0; -} - -static struct clk_ops tegra_pll_ops = { - .init = tegra14_pll_clk_init, - .enable = tegra14_pll_clk_enable, - .disable = tegra14_pll_clk_disable, - .set_rate = tegra14_pll_clk_set_rate, -}; - -static void tegra14_pllp_clk_init(struct clk *c) -{ - tegra14_pll_clk_init(c); - tegra14_pllp_init_dependencies(c->u.pll.fixed_rate); -} - -#ifdef CONFIG_PM_SLEEP -static void tegra14_pllp_clk_resume(struct clk *c) -{ - unsigned long rate = c->u.pll.fixed_rate; - tegra14_pll_clk_init(c); - BUG_ON(rate != c->u.pll.fixed_rate); -} -#endif - -static struct clk_ops tegra_pllp_ops = { - .init = tegra14_pllp_clk_init, - .enable = tegra14_pll_clk_enable, - .disable = tegra14_pll_clk_disable, - .set_rate = tegra14_pll_clk_set_rate, -}; - -static int -tegra14_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - u32 val, mask, reg; - - switch (p) { - case TEGRA_CLK_PLLD_CSI_OUT_ENB: - mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE; - reg = c->reg + PLL_BASE; - break; - case TEGRA_CLK_PLLD_DSI_OUT_ENB: - mask = PLLD_MISC_DSI_CLKENABLE; - reg = c->reg + PLL_MISC(c); - break; - case TEGRA_CLK_PLLD_MIPI_MUX_SEL: - mask = PLLD_BASE_DSI_MUX_MASK; - reg = c->reg + PLL_BASE; - break; - default: - return -EINVAL; - } - - val = clk_readl(reg); - if (setting) - val |= mask; - else - val &= ~mask; - clk_writel(val, reg); - return 0; -} - -static struct clk_ops tegra_plld_ops = { - .init = tegra14_pll_clk_init, - .enable = tegra14_pll_clk_enable, - .disable = tegra14_pll_clk_disable, - .set_rate = tegra14_pll_clk_set_rate, - .clk_cfg_ex = tegra14_plld_clk_cfg_ex, -}; - -/* - * Dynamic ramp PLLs: - * PLLC2 and PLLC3 (PLLCX) - * PLLX and PLLC (PLLXC) - * - * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that - * changes NDIV only. As a matter of policy we will make sure that switching - * between output rates above VCO minimum is always dynamic. The pre-requisite - * for the above guarantee is the following configuration convention: - * - pll configured with fixed MDIV - * - when output rate is above VCO minimum PDIV = 0 (p-value = 1) - * Switching between output rates below VCO minimum may or may not be dynamic, - * and switching across VCO minimum is never dynamic. - * - * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless - * output dividers. However dynamic ramp without overshoot is guaranteed only - * when output divisor is less or equal 8. - * - * Of course, dynamic ramp is applied provided PLL is already enabled. - */ - -/* - * Common configuration policy for dynamic ramp PLLs: - * - always set fixed M-value based on the reference rate - * - always set P-value value 1:1 for output rates above VCO minimum, and - * choose minimum necessary P-value for output rates below VCO minimum - * - calculate N-value based on selected M and P - */ -static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg, - unsigned long rate, unsigned long input_rate, u32 *pdiv) -{ - u32 p; - - if (!rate) - return -EINVAL; - - p = DIV_ROUND_UP(c->u.pll.vco_min, rate); - p = c->u.pll.round_p_to_pdiv(p, pdiv); - if (IS_ERR_VALUE(p)) - return -EINVAL; - - cfg->m = PLL_FIXED_MDIV(c, input_rate); - cfg->p = p; - cfg->output_rate = rate * cfg->p; - cfg->n = cfg->output_rate * cfg->m / input_rate; - - /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */ - if ((cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || - (cfg->output_rate > c->u.pll.vco_max)) - return -EINVAL; - - return 0; -} - -static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg, - unsigned long rate, unsigned long input_rate, u32 *pdiv) -{ - const struct clk_pll_freq_table *sel; - - /* Check if the target rate is tabulated */ - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv); - BUG_ON(IS_ERR_VALUE(p)); - BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate)); - *cfg = *sel; - return 0; - } - } - - /* Configure out-of-table rate */ - if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) { - pr_err("%s: Failed to set %s out-of-table rate %lu\n", - __func__, c->name, rate); - return -EINVAL; - } - return 0; -} - -static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set) -{ - u32 val = clk_readl(c->reg + offs); - if (set) - val |= iddq_bit; - else - val &= ~iddq_bit; - clk_writel_delay(val, c->reg + offs); -} - - -static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = { -/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */ -/* p: */ 1, 2, 3, 4, 6, 8, 12, 16 }; - -static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - int i; - - if (p) { - for (i = 0; i <= PLLCX_PDIV_MAX; i++) { - /* Do not use DIV3 p values - mapped to even PDIV */ - if (i && ((i & 0x1) == 0)) - continue; - - if (p <= pllcx_p[i]) { - if (pdiv) - *pdiv = i; - return pllcx_p[i]; - } - } - } - return -EINVAL; -} - -static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate, - u32 n) -{ - u32 val, n_threshold; - - switch (input_rate) { - case 12000000: - n_threshold = 70; - break; - case 13000000: - case 26000000: - n_threshold = 71; - break; - case 16800000: - n_threshold = 55; - break; - case 19200000: - n_threshold = 44; - break; - default: - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - return; - } - - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); - val |= n <= n_threshold ? - PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; - clk_writel(val, c->reg + PLL_MISC(c)); -} - -static void pllcx_strobe(struct clk *c) -{ - u32 reg = c->reg + PLL_MISC(c); - u32 val = clk_readl(reg); - - val |= PLLCX_MISC_STROBE; - pll_writel_delay(val, reg); - - val &= ~PLLCX_MISC_STROBE; - clk_writel(val, reg); -} - -static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n) -{ - clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c)); - clk_writel(PLLCX_MISC1_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 1)); - clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2)); - clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3)); - - pllcx_update_dynamic_koef(c, input_rate, n); -} - -static void tegra14_pllcx_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, n, p, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]); - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - /* - * PLLCX is not a boot PLL, it should be left disabled by boot-loader, - * and no enabled module clocks should use it as a source during clock - * init. - */ - BUG_ON(c->state == ON); - /* - * Most of PLLCX register fields are shadowed, and can not be read - * directly from PLL h/w. Hence, actual PLLCX boot state is unknown. - * Initialize PLL to default state: disabled, reset; shadow registers - * loaded with default parameters; dividers are preset for half of - * minimum VCO rate (the latter assured that shadowed divider settings - * are within supported range). - */ - m = PLL_FIXED_MDIV(c, input_rate); - n = m * c->u.pll.vco_min / input_rate; - p = pllcx_p[1]; - val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | - (1 << PLL_BASE_DIVP_SHIFT); - clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */ - - pllcx_set_defaults(c, input_rate, n); - - c->mul = n; - c->div = m * p; -} - -static int tegra14_pllcx_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - pll_do_iddq(c, PLL_MISCN(c, 1), PLLCX_MISC1_IDDQ, false); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_BYPASS; - val |= PLL_BASE_ENABLE; - pll_writel_delay(val, c->reg + PLL_BASE); - - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLLCX_MISC_RESET; - pll_writel_delay(val, c->reg + PLL_MISC(c)); - - pllcx_strobe(c); - tegra14_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, - PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK); - return 0; -} - -static void tegra14_pllcx_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - clk_writel(val, c->reg); - - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLLCX_MISC_RESET; - pll_writel_delay(val, c->reg + PLL_MISC(c)); - - pll_do_iddq(c, PLL_MISCN(c, 1), PLLCX_MISC1_IDDQ, true); -} - -static int tegra14_pllcx_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, pdiv; - unsigned long input_rate; - struct clk_pll_freq_table cfg, old_cfg; - const struct clk_pll_freq_table *sel = &cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - input_rate = clk_get_rate(c->parent); - - if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv)) - return -EINVAL; - - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLCX, old_cfg, val); - old_cfg.p = pllcx_p[old_cfg.p]; - - BUG_ON(old_cfg.m != sel->m); - if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p)) - return 0; - -#if PLLCX_USE_DYN_RAMP - if (c->state == ON && ((sel->n == old_cfg.n) || - PLLCX_IS_DYN(sel->p, old_cfg.p))) { - /* - * Dynamic ramp if PLL is enabled, and M divider is unchanged: - * - Change P divider 1st if intermediate rate is below either - * old or new rate. - * - Change N divider with DFS strobe - target rate is either - * final new rate or below old rate - * - If divider has been changed, exit without waiting for lock. - * Otherwise, wait for lock and change divider. - */ - if (sel->p > old_cfg.p) { - val &= ~PLLCX_BASE_DIVP_MASK; - val |= pdiv << PLL_BASE_DIVP_SHIFT; - clk_writel(val, c->reg + PLL_BASE); - } - - if (sel->n != old_cfg.n) { - pllcx_update_dynamic_koef(c, input_rate, sel->n); - val &= ~PLLCX_BASE_DIVN_MASK; - val |= sel->n << PLL_BASE_DIVN_SHIFT; - pll_writel_delay(val, c->reg + PLL_BASE); - - pllcx_strobe(c); - tegra14_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, - PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK); - } - - if (sel->p < old_cfg.p) { - val &= ~PLLCX_BASE_DIVP_MASK; - val |= pdiv << PLL_BASE_DIVP_SHIFT; - clk_writel(val, c->reg + PLL_BASE); - } - return 0; - } -#endif - - val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK); - val |= (sel->n << PLL_BASE_DIVN_SHIFT) | - (pdiv << PLL_BASE_DIVP_SHIFT); - - if (c->state == ON) { - tegra14_pllcx_clk_disable(c); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - } - pllcx_update_dynamic_koef(c, input_rate, sel->n); - clk_writel(val, c->reg + PLL_BASE); - if (c->state == ON) - tegra14_pllcx_clk_enable(c); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra14_pllcx_clk_resume_enable(struct clk *c) -{ - unsigned long rate = clk_get_rate_all_locked(c->parent); - u32 val = clk_readl(c->reg + PLL_BASE); - enum clk_state state = c->state; - - if (val & PLL_BASE_ENABLE) - return; /* already resumed */ - - /* Restore input divider */ - val &= ~PLLCX_BASE_DIVM_MASK; - val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT; - clk_writel(val, c->reg + PLL_BASE); - - /* temporarily sync h/w and s/w states, final sync happens - in tegra_clk_resume later */ - c->state = OFF; - pllcx_set_defaults(c, rate, c->mul); - - rate = clk_get_rate_all_locked(c); - tegra14_pllcx_clk_set_rate(c, rate); - tegra14_pllcx_clk_enable(c); - c->state = state; -} -#endif - -static struct clk_ops tegra_pllcx_ops = { - .init = tegra14_pllcx_clk_init, - .enable = tegra14_pllcx_clk_enable, - .disable = tegra14_pllcx_clk_disable, - .set_rate = tegra14_pllcx_clk_set_rate, -}; - - -/* non-monotonic mapping below is not a typo */ -static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = { -/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ -/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 }; - -static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - if (!p || (p > PLLXC_SW_PDIV_MAX + 1)) - return -EINVAL; - - if (pdiv) - *pdiv = p - 1; - return p; -} - -static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate, - u32 *step_a, u32 *step_b) -{ - switch (input_rate) { - case 12000000: - case 13000000: - case 26000000: - *step_a = 0x2B; - *step_b = 0x0B; - return; - case 16800000: - *step_a = 0x1A; - *step_b = 0x09; - return; - case 19200000: - *step_a = 0x12; - *step_b = 0x08; - return; - default: - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - } -} - -static void pllx_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val; - u32 step_a, step_b; - - /* Only s/w dyn ramp control is supported */ - val = clk_readl(PLLX_HW_CTRL_CFG); - BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL)); - - pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b); - val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; - val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; - - /* Get ready dyn ramp state machine, disable lock override */ - clk_writel(val, c->reg + PLL_MISCN(c, 2)); - - /* Enable outputs to CPUs and configure lock */ - val = 0; -#if USE_PLL_LOCK_BITS - val |= PLL_MISC_LOCK_ENABLE(c); -#endif - clk_writel(val, c->reg + PLL_MISC(c)); - - /* Check/set IDDQ */ - val = clk_readl(c->reg + PLL_MISCN(c, 3)); - if (c->state == ON) { - BUG_ON(val & PLLX_MISC3_IDDQ); - } else { - val |= PLLX_MISC3_IDDQ; - clk_writel(val, c->reg + PLL_MISCN(c, 3)); - } -} - -static void pllc_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val; - u32 step_a, step_b; - - /* Get ready dyn ramp state machine */ - pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b); - val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT; - val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT; - clk_writel(val, c->reg + PLL_MISCN(c, 1)); - - /* Configure lock and check/set IDDQ */ - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLLC_BASE_LOCK_OVERRIDE; - clk_writel(val, c->reg + PLL_BASE); - - val = clk_readl(c->reg + PLL_MISC(c)); -#if USE_PLL_LOCK_BITS - val |= PLLC_MISC_LOCK_ENABLE; -#else - val &= ~PLLC_MISC_LOCK_ENABLE; -#endif - clk_writel(val, c->reg + PLL_MISC(c)); - - if (c->state == ON) - BUG_ON(val & PLLC_MISC_IDDQ); - else { - val |= PLLC_MISC_IDDQ; - clk_writel(val, c->reg + PLL_MISC(c)); - } -} - -static void tegra14_pllxc_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, p, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = - DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]); - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - - m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; - BUG_ON(p > PLLXC_PDIV_MAX); - p = pllxc_p[p]; - - c->div = m * p; - c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - - if (c->flags & PLLX) - pllx_set_defaults(c, input_rate); - else - pllc_set_defaults(c, input_rate); -} - -static int tegra14_pllxc_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - if (c->flags & PLLX) - pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false); - else - pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false); - - val = clk_readl(c->reg + PLL_BASE); - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - tegra14_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - - return 0; -} - -static void tegra14_pllxc_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLLX) - pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true); - else - pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true); - -} - -#define PLLXC_DYN_RAMP(pll_misc, reg) \ - do { \ - u32 misc = clk_readl((reg)); \ - \ - misc &= ~pll_misc##_NDIV_NEW_MASK; \ - misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \ - pll_writel_delay(misc, (reg)); \ - \ - misc |= pll_misc##_EN_DYNRAMP; \ - clk_writel(misc, (reg)); \ - tegra14_pll_clk_wait_for_lock(c, (reg), \ - pll_misc##_DYNRAMP_DONE); \ - \ - val &= ~PLLXC_BASE_DIVN_MASK; \ - val |= sel->n << PLL_BASE_DIVN_SHIFT; \ - pll_writel_delay(val, c->reg + PLL_BASE); \ - \ - misc &= ~pll_misc##_EN_DYNRAMP; \ - pll_writel_delay(misc, (reg)); \ - } while (0) - -static int tegra14_pllxc_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, pdiv; - unsigned long input_rate; - struct clk_pll_freq_table cfg, old_cfg; - const struct clk_pll_freq_table *sel = &cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - input_rate = clk_get_rate(c->parent); - - if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv)) - return -EINVAL; - - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLXC, old_cfg, val); - old_cfg.p = pllxc_p[old_cfg.p]; - - if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) && - (sel->p == old_cfg.p)) - return 0; - -#if PLLXC_USE_DYN_RAMP - /* - * Dynamic ramp can be used if M, P dividers are unchanged - * (coveres superset of conventional dynamic ramps) - */ - if ((c->state == ON) && (sel->m == old_cfg.m) && - (sel->p == old_cfg.p)) { - - if (c->flags & PLLX) { - u32 reg = c->reg + PLL_MISCN(c, 2); - PLLXC_DYN_RAMP(PLLX_MISC2, reg); - } else { - u32 reg = c->reg + PLL_MISCN(c, 1); - PLLXC_DYN_RAMP(PLLC_MISC1, reg); - } - - return 0; - } -#endif - if (c->state == ON) { - /* Use "ENABLE" pulse without placing PLL into IDDQ */ - val &= ~PLL_BASE_ENABLE; - pll_writel_delay(val, c->reg + PLL_BASE); - } - - val &= ~(PLLXC_BASE_DIVM_MASK | - PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT); - clk_writel(val, c->reg + PLL_BASE); - - if (c->state == ON) { - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - tegra14_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, - PLL_BASE_LOCK); - } - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra14_pllxc_clk_resume_enable(struct clk *c) -{ - unsigned long rate = clk_get_rate_all_locked(c->parent); - enum clk_state state = c->state; - - if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE) - return; /* already resumed */ - - /* temporarily sync h/w and s/w states, final sync happens - in tegra_clk_resume later */ - c->state = OFF; - if (c->flags & PLLX) - pllx_set_defaults(c, rate); - else - pllc_set_defaults(c, rate); - - rate = clk_get_rate_all_locked(c); - tegra14_pllxc_clk_set_rate(c, rate); - tegra14_pllxc_clk_enable(c); - c->state = state; -} -#endif - -static struct clk_ops tegra_pllxc_ops = { - .init = tegra14_pllxc_clk_init, - .enable = tegra14_pllxc_clk_enable, - .disable = tegra14_pllxc_clk_disable, - .set_rate = tegra14_pllxc_clk_set_rate, -}; - - -/* FIXME: pllm suspend/resume */ - -/* non-monotonic mapping below is not a typo */ -static u8 pllm_p[PLLM_PDIV_MAX + 1] = { -/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ -/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 }; - -static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv) -{ - if (!p || (p > PLLM_SW_PDIV_MAX + 1)) - return -EINVAL; - - if (pdiv) - *pdiv = p - 1; - return p; -} - -static void pllm_set_defaults(struct clk *c, unsigned long input_rate) -{ - u32 val = clk_readl(c->reg + PLL_MISC(c)); - - val &= ~PLLM_MISC_LOCK_OVERRIDE; -#if USE_PLL_LOCK_BITS - val &= ~PLLM_MISC_LOCK_DISABLE; -#else - val |= PLLM_MISC_LOCK_DISABLE; -#endif - - if (c->state != ON) - val |= PLLM_MISC_IDDQ; - else - BUG_ON(val & PLLM_MISC_IDDQ); - - clk_writel(val, c->reg + PLL_MISC(c)); -} - -static void tegra14_pllm_clk_init(struct clk *c) -{ - unsigned long input_rate = clk_get_rate(c->parent); - u32 m, p, val; - - /* clip vco_min to exact multiple of input rate to avoid crossover - by rounding */ - c->u.pll.vco_min = - DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate; - c->min_rate = - DIV_ROUND_UP(c->u.pll.vco_min, pllm_p[PLLM_SW_PDIV_MAX]); - - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) { - c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF; - - /* Tegra14 has bad default value of PMC_PLLM_WB0_OVERRIDE. - * If bootloader does not initialize PLLM, kernel has to - * initialize the register with sane value. */ - if (c->state == OFF) { - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); - m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - if (m != PLL_FIXED_MDIV(c, input_rate)) { - /* Copy DIVM and DIVN from PLLM_BASE */ - pr_info("%s: Fixing DIVM and DIVN\n", __func__); - val = clk_readl(c->reg + PLL_BASE); - val &= (PLLM_BASE_DIVM_MASK - | PLLM_BASE_DIVN_MASK); - pmc_writel(val, PMC_PLLM_WB0_OVERRIDE); - } - } - - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2); - p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) >> - PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT; - - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); - } else { - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - p = (val & PLLM_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; - } - - m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - BUG_ON(m != PLL_FIXED_MDIV(c, input_rate)); - c->div = m * pllm_p[p]; - c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - - pllm_set_defaults(c, input_rate); -} - -static int tegra14_pllm_clk_enable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false); - - /* Just enable both base and override - one would work */ - val = clk_readl(c->reg + PLL_BASE); - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; - pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - - tegra14_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - return 0; -} - -static void tegra14_pllm_clk_disable(struct clk *c) -{ - u32 val; - pr_debug("%s on clock %s\n", __func__, c->name); - - /* Just disable both base and override - one would work */ - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; - pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true); -} - -static int tegra14_pllm_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val, pdiv; - unsigned long input_rate; - struct clk_pll_freq_table cfg; - const struct clk_pll_freq_table *sel = &cfg; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->state == ON) { - if (rate != clk_get_rate_locked(c)) { - pr_err("%s: Can not change memory %s rate in flight\n", - __func__, c->name); - return -EINVAL; - } - return 0; - } - - input_rate = clk_get_rate(c->parent); - - if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv)) - return -EINVAL; - - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) { - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2); - val &= ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK; - val |= pdiv << PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT; - pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2); - - val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); - val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT); - pmc_writel(val, PMC_PLLM_WB0_OVERRIDE); - } else { - val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK | - PLLM_BASE_DIVP_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | - (pdiv << PLL_BASE_DIVP_SHIFT); - clk_writel(val, c->reg + PLL_BASE); - } - - return 0; -} - -static struct clk_ops tegra_pllm_ops = { - .init = tegra14_pllm_clk_init, - .enable = tegra14_pllm_clk_enable, - .disable = tegra14_pllm_clk_disable, - .set_rate = tegra14_pllm_clk_set_rate, -}; - -/* - * Tegra14 includes dynamic frequency lock loop (DFLL) with automatic voltage - * control as possible CPU clock source. It is included in the Tegra14 clock - * tree as "complex PLL" with standard Tegra clock framework APIs. However, - * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c - * module. Hence, DFLL operations, with the exception of initialization, are - * basically cl-dvfs wrappers. - */ - -/* DFLL operations */ -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static void tune_cpu_trimmers(bool trim_high) -{ - tegra_soctherm_adjust_cpu_zone(trim_high); -} -#endif - -static void __init tegra14_dfll_cpu_late_init(struct clk *c) -{ -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - int ret; - struct clk *cpu = tegra_get_clock_by_name("cpu_g"); - - if (!cpu || !cpu->dvfs) { - pr_err("%s: CPU dvfs is not present\n", __func__); - return; - } - tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers); - -#ifdef CONFIG_TEGRA_FPGA_PLATFORM - u32 netlist, patchid; - tegra_get_netlist_revision(&netlist, &patchid); - if (netlist < 12) { - pr_err("%s: CL-DVFS is not available on net %d\n", - __func__, netlist); - return; - } -#endif - /* release dfll clock source reset, init cl_dvfs control logic, and - move dfll to initialized state, so it can be used as CPU source */ - tegra_periph_reset_deassert(c); - ret = tegra_init_cl_dvfs(); - if (!ret) { - c->state = OFF; - - use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE; - tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll); - tegra_cl_dvfs_debug_init(c); - pr_info("Tegra CPU DFLL is initialized\n"); - } -#endif -} - -static void tegra14_dfll_clk_init(struct clk *c) -{ - c->ops->init = tegra14_dfll_cpu_late_init; -} - -static int tegra14_dfll_clk_enable(struct clk *c) -{ - return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs); -} - -static void tegra14_dfll_clk_disable(struct clk *c) -{ - tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs); -} - -static int tegra14_dfll_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate); - - if (!ret) - c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs); - - return ret; -} - -static void tegra14_dfll_clk_reset(struct clk *c, bool assert) -{ - u32 val = assert ? DFLL_BASE_RESET : 0; - clk_writel_delay(val, c->reg); -} - -static int -tegra14_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_DFLL_LOCK) - return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) : - tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs); - return -EINVAL; -} - -#ifdef CONFIG_PM_SLEEP -static void tegra14_dfll_clk_resume(struct clk *c) -{ - if (!(clk_readl(c->reg) & DFLL_BASE_RESET)) - return; /* already resumed */ - - if (c->state != UNINITIALIZED) { - tegra_periph_reset_deassert(c); - tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs); - } -} -#endif - -static struct clk_ops tegra_dfll_ops = { - .init = tegra14_dfll_clk_init, - .enable = tegra14_dfll_clk_enable, - .disable = tegra14_dfll_clk_disable, - .set_rate = tegra14_dfll_clk_set_rate, - .reset = tegra14_dfll_clk_reset, - .clk_cfg_ex = tegra14_dfll_clk_cfg_ex, -}; - -/* DFLL sysfs interface */ -static int tegra14_use_dfll_cb(const char *arg, const struct kernel_param *kp) -{ - int ret = 0; - unsigned long c_flags, p_flags; - unsigned int old_use_dfll; - struct clk *c = tegra_get_clock_by_name("cpu"); - struct clk *dfll = tegra_get_clock_by_name("dfll_cpu"); - - if (!c->parent || !c->parent->dvfs || !dfll) - return -ENOSYS; - - clk_lock_save(c, &c_flags); - if (dfll->state == UNINITIALIZED) { - pr_err("%s: DFLL is not initialized\n", __func__); - clk_unlock_restore(c, &c_flags); - return -ENOSYS; - } - if (c->parent->u.cpu.mode == MODE_LP) { - pr_err("%s: DFLL is not used on LP CPU\n", __func__); - clk_unlock_restore(c, &c_flags); - return -ENOSYS; - } - - clk_lock_save(c->parent, &p_flags); - old_use_dfll = use_dfll; - param_set_int(arg, kp); - - if (use_dfll != old_use_dfll) { - ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll); - if (ret) { - use_dfll = old_use_dfll; - } else { - ret = clk_set_rate_locked(c->parent, - clk_get_rate_locked(c->parent)); - if (ret) { - use_dfll = old_use_dfll; - tegra_dvfs_set_dfll_range( - c->parent->dvfs, use_dfll); - } - } - } - clk_unlock_restore(c->parent, &p_flags); - clk_unlock_restore(c, &c_flags); - tegra_recalculate_cpu_edp_limits(); - return ret; -} - -static struct kernel_param_ops tegra14_use_dfll_ops = { - .set = tegra14_use_dfll_cb, - .get = param_get_int, -}; -module_param_cb(use_dfll, &tegra14_use_dfll_ops, &use_dfll, 0644); - - -/* Clock divider ops (non-atomic shared register access) */ -static DEFINE_SPINLOCK(pll_div_lock); - -static int tegra14_pll_div_clk_set_rate(struct clk *c, unsigned long rate); -static void tegra14_pll_div_clk_init(struct clk *c) -{ - if (c->flags & DIV_U71) { - u32 val, divu71; - if (c->parent->state == OFF) - c->ops->disable(c); - - val = clk_readl(c->reg); - val >>= c->reg_shift; - c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; - if (!(val & PLL_OUT_RESET_DISABLE)) - c->state = OFF; - - if (c->u.pll_div.default_rate) { - int ret = tegra14_pll_div_clk_set_rate( - c, c->u.pll_div.default_rate); - if (!ret) - return; - } - divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; - c->div = (divu71 + 2); - c->mul = 2; - } else if (c->flags & DIV_2) { - c->state = ON; - if (c->flags & (PLLD | PLLX)) { - c->div = 2; - c->mul = 1; - } else - BUG(); - } else if (c->flags & PLLU) { - u32 val = clk_readl(c->reg); - c->state = val & (0x1 << c->reg_shift) ? ON : OFF; - } else { - c->state = ON; - c->div = 1; - c->mul = 1; - } -} - -static int tegra14_pll_div_clk_enable(struct clk *c) -{ - u32 val; - u32 new_val; - unsigned long flags; - - pr_debug("%s: %s\n", __func__, c->name); - if (c->flags & DIV_U71) { - spin_lock_irqsave(&pll_div_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - spin_unlock_irqrestore(&pll_div_lock, flags); - return 0; - } else if (c->flags & DIV_2) { - return 0; - } else if (c->flags & PLLU) { - clk_lock_save(c->parent, &flags); - val = clk_readl(c->reg) | (0x1 << c->reg_shift); - clk_writel_delay(val, c->reg); - clk_unlock_restore(c->parent, &flags); - return 0; - } - return -EINVAL; -} - -static void tegra14_pll_div_clk_disable(struct clk *c) -{ - u32 val; - u32 new_val; - unsigned long flags; - - pr_debug("%s: %s\n", __func__, c->name); - if (c->flags & DIV_U71) { - spin_lock_irqsave(&pll_div_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - spin_unlock_irqrestore(&pll_div_lock, flags); - } else if (c->flags & PLLU) { - clk_lock_save(c->parent, &flags); - val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); - clk_writel_delay(val, c->reg); - clk_unlock_restore(c->parent, &flags); - } -} - -static int tegra14_pll_div_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val; - u32 new_val; - int divider_u71; - unsigned long parent_rate = clk_get_rate(c->parent); - unsigned long flags; - - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider_u71 >= 0) { - spin_lock_irqsave(&pll_div_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - if (c->flags & DIV_U71_FIXED) - new_val |= PLL_OUT_OVERRIDE; - new_val &= ~PLL_OUT_RATIO_MASK; - new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - c->div = divider_u71 + 2; - c->mul = 2; - spin_unlock_irqrestore(&pll_div_lock, flags); - return 0; - } - } else if (c->flags & DIV_2) - return clk_set_rate(c->parent, rate * 2); - - return -EINVAL; -} - -static long tegra14_pll_div_clk_round_rate(struct clk *c, unsigned long rate) -{ - int divider; - unsigned long parent_rate = clk_get_rate(c->parent); - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_2) - /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ - return rate; - - return -EINVAL; -} - -static struct clk_ops tegra_pll_div_ops = { - .init = tegra14_pll_div_clk_init, - .enable = tegra14_pll_div_clk_enable, - .disable = tegra14_pll_div_clk_disable, - .set_rate = tegra14_pll_div_clk_set_rate, - .round_rate = tegra14_pll_div_clk_round_rate, -}; - -/* Periph clk ops */ -static inline u32 periph_clk_source_mask(struct clk *c) -{ - if (c->u.periph.src_mask) - return c->u.periph.src_mask; - else if (c->flags & MUX8) - return 7 << 29; - else if (c->flags & MUX_PWM) - return 3 << 28; - else if (c->flags & MUX_CLK_OUT) - return 3 << (c->u.periph.clk_num + 4); - else if (c->flags & PLLD) - return PLLD_BASE_DSI_MUX_MASK; - else - return 3 << 30; -} - -static inline u32 periph_clk_source_shift(struct clk *c) -{ - if (c->u.periph.src_shift) - return c->u.periph.src_shift; - else if (c->flags & MUX8) - return 29; - else if (c->flags & MUX_PWM) - return 28; - else if (c->flags & MUX_CLK_OUT) - return c->u.periph.clk_num + 4; - else if (c->flags & PLLD) - return PLLD_BASE_DSI_MUX_SHIFT; - else - return 30; -} - -static void tegra14_periph_clk_init(struct clk *c) -{ - u32 val = clk_readl(c->reg); - const struct clk_mux_sel *mux = 0; - const struct clk_mux_sel *sel; - if (c->flags & MUX) { - for (sel = c->inputs; sel->input != NULL; sel++) { - if (((val & periph_clk_source_mask(c)) >> - periph_clk_source_shift(c)) == sel->value) - mux = sel; - } - BUG_ON(!mux); - - c->parent = mux->input; - } else { - c->parent = c->inputs[0].input; - } - - /* if peripheral is left under reset - enforce safe rate */ - if (!(c->flags & PERIPH_NO_RESET) && - (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))) { - tegra_periph_clk_safe_rate_init(c); - val = clk_readl(c->reg); - } - - if (c->flags & DIV_U71) { - u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; - if (c->flags & DIV_U71_IDLE) { - val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << - PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); - val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << - PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); - clk_writel(val, c->reg); - } - c->div = divu71 + 2; - c->mul = 2; - } else if (c->flags & DIV_U151) { - u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; - if ((c->flags & DIV_U151_UART) && - (!(val & PERIPH_CLK_UART_DIV_ENB))) { - divu151 = 0; - } - c->div = divu151 + 2; - c->mul = 2; - } else if (c->flags & DIV_U16) { - u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; - c->div = divu16 + 1; - c->mul = 1; - } else { - c->div = 1; - c->mul = 1; - } - - if (c->flags & PERIPH_NO_ENB) { - c->state = c->parent->state; - return; - } - - c->state = ON; - - if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) - c->state = OFF; - if (!(c->flags & PERIPH_NO_RESET)) - if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) - c->state = OFF; -} - -static int tegra14_periph_clk_enable(struct clk *c) -{ - unsigned long flags; - pr_debug("%s on clock %s\n", __func__, c->name); - - if (c->flags & PERIPH_NO_ENB) - return 0; - - spin_lock_irqsave(&periph_refcount_lock, flags); - - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) { - spin_unlock_irqrestore(&periph_refcount_lock, flags); - return 0; - } - - clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); - if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) { - if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) { - udelay(RESET_PROPAGATION_DELAY); - clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c)); - } - } - spin_unlock_irqrestore(&periph_refcount_lock, flags); - return 0; -} - -static void tegra14_periph_clk_disable(struct clk *c) -{ - unsigned long val, flags; - pr_debug("%s on clock %s\n", __func__, c->name); - - if (c->flags & PERIPH_NO_ENB) - return; - - spin_lock_irqsave(&periph_refcount_lock, flags); - - if (c->refcnt) - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; - - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { - /* If peripheral is in the APB bus then read the APB bus to - * flush the write operation in apb bus. This will avoid the - * peripheral access after disabling clock*/ - if (c->flags & PERIPH_ON_APB) - val = tegra_read_chipid(); - - clk_writel_delay( - PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); - } - spin_unlock_irqrestore(&periph_refcount_lock, flags); -} - -static void tegra14_periph_clk_reset(struct clk *c, bool assert) -{ - unsigned long val; - pr_debug("%s %s on clock %s\n", __func__, - assert ? "assert" : "deassert", c->name); - - if (c->flags & PERIPH_NO_ENB) - return; - - if (!(c->flags & PERIPH_NO_RESET)) { - if (assert) { - /* If peripheral is in the APB bus then read the APB - * bus to flush the write operation in apb bus. This - * will avoid the peripheral access after disabling - * clock */ - if (c->flags & PERIPH_ON_APB) - val = tegra_read_chipid(); - - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_SET_REG(c)); - } else - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_CLR_REG(c)); - } -} - -static int tegra14_periph_clk_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - const struct clk_mux_sel *sel; - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - - if (!(c->flags & MUX)) - return (p == c->parent) ? 0 : (-EINVAL); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - val = clk_readl(c->reg); - val &= ~periph_clk_source_mask(c); - val |= (sel->value << periph_clk_source_shift(c)); - - if (c->refcnt) - clk_enable(p); - - clk_writel_delay(val, c->reg); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - - return -EINVAL; -} - -static int tegra14_periph_clk_set_rate(struct clk *c, unsigned long rate) -{ - u32 val; - int divider; - unsigned long parent_rate = clk_get_rate(c->parent); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; - val |= divider; - clk_writel_delay(val, c->reg); - c->div = divider + 2; - c->mul = 2; - return 0; - } - } else if (c->flags & DIV_U151) { - divider = clk_div151_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; - val |= divider; - if (c->flags & DIV_U151_UART) { - if (divider) - val |= PERIPH_CLK_UART_DIV_ENB; - else - val &= ~PERIPH_CLK_UART_DIV_ENB; - } - clk_writel_delay(val, c->reg); - c->div = divider + 2; - c->mul = 2; - return 0; - } - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; - val |= divider; - clk_writel_delay(val, c->reg); - c->div = divider + 1; - c->mul = 1; - return 0; - } - } else if (parent_rate <= rate) { - c->div = 1; - c->mul = 1; - return 0; - } - return -EINVAL; -} - -static long tegra14_periph_clk_round_rate(struct clk *c, - unsigned long rate) -{ - int divider; - unsigned long parent_rate = clk_get_rate(c->parent); - pr_debug("%s: %s %lu\n", __func__, c->name, rate); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_U151) { - divider = clk_div151_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate, divider + 1); - } - return -EINVAL; -} - -static struct clk_ops tegra_periph_clk_ops = { - .init = &tegra14_periph_clk_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_parent = &tegra14_periph_clk_set_parent, - .set_rate = &tegra14_periph_clk_set_rate, - .round_rate = &tegra14_periph_clk_round_rate, - .reset = &tegra14_periph_clk_reset, -}; - -/* 1x shared bus ops */ -static long _1x_round_updown(struct clk *c, struct clk *src, - unsigned long rate, bool up) -{ - int divider; - unsigned long source_rate, round_rate; - - source_rate = clk_get_rate(src); - - divider = clk_div71_get_divider(source_rate, rate + (up ? -1 : 1), - c->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP); - - if (divider < 0) - return c->min_rate; - - round_rate = source_rate * 2 / (divider + 2); - - if (round_rate > c->max_rate) { - divider += c->flags & DIV_U71_INT ? 2 : 1; -#if !DIVIDER_1_5_ALLOWED - divider = max(2, divider); -#endif - round_rate = source_rate * 2 / (divider + 2); - } - return round_rate; -} - -static long tegra14_1xbus_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - unsigned long pll_low_rate, pll_high_rate; - - rate = max(rate, c->min_rate); - - pll_low_rate = _1x_round_updown(c, c->u.periph.pll_low, rate, up); - if (rate <= c->u.periph.threshold) { - c->u.periph.pll_selected = c->u.periph.pll_low; - return pll_low_rate; - } - - pll_high_rate = _1x_round_updown(c, c->u.periph.pll_high, rate, up); - if (pll_high_rate <= c->u.periph.threshold) { - c->u.periph.pll_selected = c->u.periph.pll_low; - return pll_low_rate; /* prevent oscillation across threshold */ - } - - if (up) { - /* rounding up: both plls may hit max, and round down */ - if (pll_high_rate < rate) { - if (pll_low_rate < pll_high_rate) { - c->u.periph.pll_selected = c->u.periph.pll_high; - return pll_high_rate; - } - } else { - if ((pll_low_rate < rate) || - (pll_low_rate > pll_high_rate)) { - c->u.periph.pll_selected = c->u.periph.pll_high; - return pll_high_rate; - } - } - } else if (pll_low_rate < pll_high_rate) { - /* rounding down: to get here both plls able to round down */ - c->u.periph.pll_selected = c->u.periph.pll_high; - return pll_high_rate; - } - c->u.periph.pll_selected = c->u.periph.pll_low; - return pll_low_rate; -} - -static long tegra14_1xbus_round_rate(struct clk *c, unsigned long rate) -{ - return tegra14_1xbus_round_updown(c, rate, true); -} - -static int tegra14_1xbus_set_rate(struct clk *c, unsigned long rate) -{ - /* Compensate rate truncating during rounding */ - return tegra14_periph_clk_set_rate(c, rate + 1); -} - -static int tegra14_clk_1xbus_update(struct clk *c) -{ - int ret; - struct clk *new_parent; - unsigned long rate, old_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra14_clk_shared_bus_update(c, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(c); - pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n", - c->name, old_rate, c->parent->name, rate); - if (rate == old_rate) - return 0; - - if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) { - unsigned long r, m = c->max_rate; - r = clk_get_rate(c->u.periph.pll_low); - c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul; - r = clk_get_rate(c->u.periph.pll_high); - c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul; - } - - new_parent = c->u.periph.pll_selected; - - /* - * The transition procedure below is guaranteed to switch to the target - * parent/rate without violation of max clock limits. It would attempt - * to switch without dip in bus rate if it is possible, but this cannot - * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with - * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz, - * and there is no way to avoid rate dip in this case). - */ - if (new_parent != c->parent) { - int interim_div = 0; - /* Switching to pll_high may over-clock bus if current divider - is too small - increase divider to safe value */ - if ((new_parent == c->u.periph.pll_high) && - (c->div < c->u.periph.min_div_high)) - interim_div = c->u.periph.min_div_high; - - /* Switching to pll_low may dip down rate if current divider - is too big - decrease divider as much as we can */ - if ((new_parent == c->u.periph.pll_low) && - (c->div > c->u.periph.min_div_low) && - (c->div > c->u.periph.min_div_high)) - interim_div = c->u.periph.min_div_low; - - if (interim_div) { - u64 interim_rate = old_rate * c->div; - do_div(interim_rate, interim_div); - ret = clk_set_rate_locked(c, interim_rate); - if (ret) { - pr_err("Failed to set %s rate to %lu\n", - c->name, (unsigned long)interim_rate); - return ret; - } - pr_debug("1xbus %s: rate %lu on parent %s\n", c->name, - clk_get_rate_locked(c), c->parent->name); - } - - ret = clk_set_parent_locked(c, new_parent); - if (ret) { - pr_err("Failed to set %s parent %s\n", - c->name, new_parent->name); - return ret; - } - - old_rate = clk_get_rate_locked(c); - pr_debug("1xbus %s: rate %lu on parent %s\n", c->name, - old_rate, c->parent->name); - if (rate == old_rate) - return 0; - } - - ret = clk_set_rate_locked(c, rate); - if (ret) { - pr_err("Failed to set %s rate to %lu\n", c->name, rate); - return ret; - } - pr_debug("1xbus %s: rate %lu on parent %s\n", c->name, - clk_get_rate_locked(c), c->parent->name); - return 0; - -} - -static struct clk_ops tegra_1xbus_clk_ops = { - .init = &tegra14_periph_clk_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_parent = &tegra14_periph_clk_set_parent, - .set_rate = &tegra14_1xbus_set_rate, - .round_rate = &tegra14_1xbus_round_rate, - .round_rate_updown = &tegra14_1xbus_round_updown, - .reset = &tegra14_periph_clk_reset, - .shared_bus_update = &tegra14_clk_1xbus_update, -}; - -/* Periph extended clock configuration ops */ -static int -tegra14_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_VI_INP_SEL) { - u32 val = clk_readl(c->reg); - val &= ~PERIPH_CLK_VI_SEL_EX_MASK; - val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & - PERIPH_CLK_VI_SEL_EX_MASK; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_vi_clk_ops = { - .init = &tegra14_periph_clk_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_parent = &tegra14_periph_clk_set_parent, - .set_rate = &tegra14_periph_clk_set_rate, - .round_rate = &tegra14_periph_clk_round_rate, - .clk_cfg_ex = &tegra14_vi_clk_cfg_ex, - .reset = &tegra14_periph_clk_reset, -}; - -static int -tegra14_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - if (p == TEGRA_CLK_DTV_INVERT) { - u32 val = clk_readl(c->reg); - if (setting) - val |= PERIPH_CLK_DTV_POLARITY_INV; - else - val &= ~PERIPH_CLK_DTV_POLARITY_INV; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_dtv_clk_ops = { - .init = &tegra14_periph_clk_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_parent = &tegra14_periph_clk_set_parent, - .set_rate = &tegra14_periph_clk_set_rate, - .round_rate = &tegra14_periph_clk_round_rate, - .clk_cfg_ex = &tegra14_dtv_clk_cfg_ex, - .reset = &tegra14_periph_clk_reset, -}; - -static int tegra14_dsi_clk_set_parent(struct clk *c, struct clk *p) -{ - const struct clk_mux_sel *sel; - struct clk *d = tegra_get_clock_by_name("pll_d"); - if (c->reg != d->reg) - d = tegra_get_clock_by_name("pll_d2"); - - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - if (c->refcnt) - clk_enable(p); - - /* The DSI parent selection bit is in PLLD base - register - can not do direct r-m-w, must be - protected by PLLD lock */ - tegra_clk_cfg_ex( - d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - - return -EINVAL; -} - -static struct clk_ops tegra_dsi_clk_ops = { - .init = &tegra14_periph_clk_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_parent = &tegra14_dsi_clk_set_parent, - .set_rate = &tegra14_periph_clk_set_rate, - .round_rate = &tegra14_periph_clk_round_rate, - .reset = &tegra14_periph_clk_reset, -}; - -/* Output clock ops */ - -static DEFINE_SPINLOCK(clk_out_lock); - -static void tegra14_clk_out_init(struct clk *c) -{ - const struct clk_mux_sel *mux = 0; - const struct clk_mux_sel *sel; - u32 val = pmc_readl(c->reg); - - c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; - c->mul = 1; - c->div = 1; - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (((val & periph_clk_source_mask(c)) >> - periph_clk_source_shift(c)) == sel->value) - mux = sel; - } - BUG_ON(!mux); - c->parent = mux->input; -} - -static int tegra14_clk_out_enable(struct clk *c) -{ - u32 val; - unsigned long flags; - - pr_debug("%s on clock %s\n", __func__, c->name); - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val |= (0x1 << c->u.periph.clk_num); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); - - return 0; -} - -static void tegra14_clk_out_disable(struct clk *c) -{ - u32 val; - unsigned long flags; - - pr_debug("%s on clock %s\n", __func__, c->name); - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val &= ~(0x1 << c->u.periph.clk_num); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); -} - -static int tegra14_clk_out_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - unsigned long flags; - const struct clk_mux_sel *sel; - - pr_debug("%s: %s %s\n", __func__, c->name, p->name); - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - if (c->refcnt) - clk_enable(p); - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val &= ~periph_clk_source_mask(c); - val |= (sel->value << periph_clk_source_shift(c)); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - return -EINVAL; -} - -static struct clk_ops tegra_clk_out_ops = { - .init = &tegra14_clk_out_init, - .enable = &tegra14_clk_out_enable, - .disable = &tegra14_clk_out_disable, - .set_parent = &tegra14_clk_out_set_parent, -}; - - -/* External memory controller clock ops */ -static void tegra14_emc_clk_init(struct clk *c) -{ - tegra14_periph_clk_init(c); - tegra_emc_dram_type_init(c); -} - -static long tegra14_emc_clk_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - unsigned long new_rate = max(rate, c->min_rate); - - new_rate = tegra_emc_round_rate_updown(new_rate, up); - if (IS_ERR_VALUE(new_rate)) - new_rate = c->max_rate; - - return new_rate; -} - -static long tegra14_emc_clk_round_rate(struct clk *c, unsigned long rate) -{ - return tegra14_emc_clk_round_updown(c, rate, true); -} - -static int tegra14_emc_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - u32 div_value; - struct clk *p; - - /* The tegra14x memory controller has an interlock with the clock - * block that allows memory shadowed registers to be updated, - * and then transfer them to the main registers at the same - * time as the clock update without glitches. During clock change - * operation both clock parent and divider may change simultaneously - * to achieve requested rate. */ - p = tegra_emc_predict_parent(rate, &div_value); - div_value += 2; /* emc has fractional DIV_U71 divider */ - if (IS_ERR_OR_NULL(p)) { - pr_err("%s: Failed to predict emc parent for rate %lu\n", - __func__, rate); - return -EINVAL; - } - - if (p == c->parent) { - if (div_value == c->div) - return 0; - } else if (c->refcnt) - clk_enable(p); - - ret = tegra_emc_set_rate(rate); - if (ret < 0) - return ret; - - if (p != c->parent) { - if (c->refcnt && c->parent) - clk_disable(c->parent); - clk_reparent(c, p); - } - c->div = div_value; - c->mul = 2; - return 0; -} - -static int emc_bus_update(struct clk *bus) -{ - struct clk *p = NULL; - unsigned long rate, old_rate, parent_rate, backup_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra14_clk_shared_bus_update(bus, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(bus); - if (rate == old_rate) - return 0; - - if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) { - if (bus->parent == p) { - /* need backup to re-lock current parent */ - int ret; - if (IS_ERR_VALUE(backup_rate)) { - pr_err("%s: No backup for %s rate %lu\n", - __func__, bus->name, rate); - return -EINVAL; - } - - /* set voltage for backup rate if going up */ - if (backup_rate > old_rate) { - ret = tegra_dvfs_set_rate(bus, backup_rate); - if (ret) { - pr_err("%s: dvfs failed on %s rate %lu\n", - __func__, bus->name, backup_rate); - return -EINVAL; - } - } - - trace_clock_set_rate(bus->name, backup_rate, 0); - ret = bus->ops->set_rate(bus, backup_rate); - if (ret) { - pr_err("%s: Failed to backup %s for rate %lu\n", - __func__, bus->name, rate); - return -EINVAL; - } - clk_rate_change_notify(bus, backup_rate); - } - if (p->refcnt) { - pr_err("%s: %s has other than emc child\n", - __func__, p->name); - return -EINVAL; - } - - if (clk_set_rate(p, parent_rate)) { - pr_err("%s: Failed to set %s rate %lu\n", - __func__, p->name, parent_rate); - return -EINVAL; - } - } - - return clk_set_rate_locked(bus, rate); -} - -static int tegra14_clk_emc_bus_update(struct clk *bus) -{ - unsigned int seqcnt; - unsigned long cpu_rate = ULONG_MAX; - int ret, status = -EPERM; - - if (is_lp_cluster()) - status = cpu_lp_backup_boost_begin(&cpu_rate, &seqcnt); - ret = emc_bus_update(bus); - if (!status) - cpu_lp_backup_boost_end(cpu_rate, seqcnt); - return ret; -} - -#ifdef CONFIG_PM_SLEEP -static int emc_bus_set_rate(struct clk *bus, unsigned long rate) -{ - struct clk *p = NULL; - unsigned long parent_rate, backup_rate; - - if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) { - if (bus->parent == p) { - /* need backup to re-lock current parent */ - int ret; - if (IS_ERR_VALUE(backup_rate)) { - pr_err("%s: No backup for %s rate %lu\n", - __func__, bus->name, rate); - return -EINVAL; - } - - ret = bus->ops->set_rate(bus, backup_rate); - if (ret) { - pr_err("%s: Failed to backup %s for rate %lu\n", - __func__, bus->name, rate); - return -EINVAL; - } - } - if (p->refcnt) { - pr_err("%s: %s has other than emc child\n", - __func__, p->name); - return -EINVAL; - } - - if (p->ops->set_rate(p, parent_rate)) { - pr_err("%s: Failed to set %s rate %lu\n", - __func__, p->name, parent_rate); - return -EINVAL; - } - } - - return bus->ops->set_rate(bus, rate); -} - -static int tegra14_clk_emc_suspend(struct clk *c, u32 *ctx) -{ - int mv; - unsigned long rate = tegra_lp1bb_emc_min_rate_get(); - unsigned long old_rate = clk_get_rate_all_locked(c); - int floor_mv = tegra_dvfs_rail_get_thermal_floor(tegra_core_rail); - *ctx = old_rate; - - if (tegra_bb_check_bb2ap_ipc()) { - /* pending BB interrupt - keep EMC rate, request max voltage */ - mv = tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); - mv = max(mv, floor_mv); - tegra_lp1bb_suspend_mv_set(mv); - pr_debug("EMC suspend: BB IPC pending: voltage %d rate %lu\n", - mv, old_rate); - return 0; - } - - rate = tegra14_emc_clk_round_rate(c, rate); - - mv = tegra_dvfs_predict_peak_millivolts(c, rate); - mv = max(mv, floor_mv); - tegra_lp1bb_suspend_mv_set(mv); - pr_debug("EMC voltage requested before suspend: %d\n", mv); - - if (rate == old_rate) - return 0; - - pr_debug("EMC rate change before suspend: %lu => %lu\n", - old_rate, rate); - - return emc_bus_set_rate(c, rate); -} - -static void tegra14_clk_emc_resume(struct clk *c, const u32 *ctx) -{ - unsigned long rate = *ctx; - unsigned long old_rate = clk_get_rate_all_locked(c); - - if (rate == old_rate) - return; - - pr_debug("EMC rate change after suspend: %lu => %lu\n", - old_rate, rate); - pr_debug("µs timerafter suspend = %d", - readl(IO_ADDRESS(TEGRA_TMRUS_BASE))); - - emc_bus_set_rate(c, rate); -} -#endif - -static struct clk_ops tegra_emc_clk_ops = { - .init = &tegra14_emc_clk_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_rate = &tegra14_emc_clk_set_rate, - .round_rate = &tegra14_emc_clk_round_rate, - .round_rate_updown = &tegra14_emc_clk_round_updown, - .reset = &tegra14_periph_clk_reset, - .shared_bus_update = &tegra14_clk_emc_bus_update, -}; - -/* Clock doubler ops (non-atomic shared register access) */ -static DEFINE_SPINLOCK(doubler_lock); - -static void tegra14_clk_double_init(struct clk *c) -{ - u32 val = clk_readl(c->reg); - c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; - c->div = 1; - c->state = ON; - if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) - c->state = OFF; -}; - -static int tegra14_clk_double_set_rate(struct clk *c, unsigned long rate) -{ - u32 val; - unsigned long parent_rate = clk_get_rate(c->parent); - unsigned long flags; - - if (rate == parent_rate) { - spin_lock_irqsave(&doubler_lock, flags); - val = clk_readl(c->reg) | (0x1 << c->reg_shift); - clk_writel(val, c->reg); - c->mul = 1; - c->div = 1; - spin_unlock_irqrestore(&doubler_lock, flags); - return 0; - } else if (rate == 2 * parent_rate) { - spin_lock_irqsave(&doubler_lock, flags); - val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); - clk_writel(val, c->reg); - c->mul = 2; - c->div = 1; - spin_unlock_irqrestore(&doubler_lock, flags); - return 0; - } - return -EINVAL; -} - -static struct clk_ops tegra_clk_double_ops = { - .init = &tegra14_clk_double_init, - .enable = &tegra14_periph_clk_enable, - .disable = &tegra14_periph_clk_disable, - .set_rate = &tegra14_clk_double_set_rate, -}; - -/* Audio sync clock ops */ -static int tegra14_sync_source_set_rate(struct clk *c, unsigned long rate) -{ - c->rate = rate; - return 0; -} - -static struct clk_ops tegra_sync_source_ops = { - .set_rate = &tegra14_sync_source_set_rate, -}; - -static void tegra14_audio_sync_clk_init(struct clk *c) -{ - int source; - const struct clk_mux_sel *sel; - u32 val = clk_readl(c->reg); - c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; - source = val & AUDIO_SYNC_SOURCE_MASK; - for (sel = c->inputs; sel->input != NULL; sel++) - if (sel->value == source) - break; - BUG_ON(sel->input == NULL); - c->parent = sel->input; -} - -static int tegra14_audio_sync_clk_enable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); - return 0; -} - -static void tegra14_audio_sync_clk_disable(struct clk *c) -{ - u32 val = clk_readl(c->reg); - clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); -} - -static int tegra14_audio_sync_clk_set_parent(struct clk *c, struct clk *p) -{ - u32 val; - const struct clk_mux_sel *sel; - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) { - val = clk_readl(c->reg); - val &= ~AUDIO_SYNC_SOURCE_MASK; - val |= sel->value; - - if (c->refcnt) - clk_enable(p); - - clk_writel(val, c->reg); - - if (c->refcnt && c->parent) - clk_disable(c->parent); - - clk_reparent(c, p); - return 0; - } - } - - return -EINVAL; -} - -static struct clk_ops tegra_audio_sync_clk_ops = { - .init = tegra14_audio_sync_clk_init, - .enable = tegra14_audio_sync_clk_enable, - .disable = tegra14_audio_sync_clk_disable, - .set_parent = tegra14_audio_sync_clk_set_parent, -}; - - -/* cbus ops */ -/* - * Some clocks require dynamic re-locking of source PLL in order to - * achieve frequency scaling granularity that matches characterized - * core voltage steps. The cbus clock creates a shared bus that - * provides a virtual root for such clocks to hide and synchronize - * parent PLL re-locking as well as backup operations. -*/ - -static void tegra14_clk_cbus_init(struct clk *c) -{ - c->state = OFF; - c->set = true; -} - -static int tegra14_clk_cbus_enable(struct clk *c) -{ - return 0; -} - -static long tegra14_clk_cbus_round_updown(struct clk *c, unsigned long rate, - bool up) -{ - int i; - - if (!c->dvfs) { - if (!c->min_rate) - c->min_rate = c->parent->min_rate; - rate = max(rate, c->min_rate); - return rate; - } - - /* update min now, since no dvfs table was available during init - (skip placeholder entries set to 1 kHz) */ - if (!c->min_rate) { - for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { - if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) { - c->min_rate = c->dvfs->freqs[i]; - break; - } - } - BUG_ON(!c->min_rate); - } - rate = max(rate, c->min_rate); - - for (i = 0; ; i++) { - unsigned long f = c->dvfs->freqs[i]; - int mv = c->dvfs->millivolts[i]; - if ((f >= rate) || (mv >= c->dvfs->max_millivolts) || - ((i + 1) >= c->dvfs->num_freqs)) { - if (!up && i && (f > rate)) - i--; - break; - } - } - return c->dvfs->freqs[i]; -} - -static long tegra14_clk_cbus_round_rate(struct clk *c, unsigned long rate) -{ - return tegra14_clk_cbus_round_updown(c, rate, true); -} - -static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort) -{ - int ret = 0; - - /* set new divider if it is bigger than the current one */ - if (c->div < c->mul * div) { - ret = clk_set_div(c, div); - if (ret) { - pr_err("%s: failed to set %s clock divider %u: %d\n", - __func__, c->name, div, ret); - if (abort) - return ret; - } - } - - if (c->parent != p) { - ret = clk_set_parent(c, p); - if (ret) { - pr_err("%s: failed to set %s clock parent %s: %d\n", - __func__, c->name, p->name, ret); - if (abort) - return ret; - } - } - - /* set new divider if it is smaller than the current one */ - if (c->div > c->mul * div) { - ret = clk_set_div(c, div); - if (ret) - pr_err("%s: failed to set %s clock divider %u: %d\n", - __func__, c->name, div, ret); - } - - return ret; -} - -static int cbus_backup(struct clk *c) -{ - int ret; - struct clk *user; - - list_for_each_entry(user, &c->shared_bus_list, - u.shared_bus_user.node) { - struct clk *client = user->u.shared_bus_user.client; - if (client && (client->state == ON) && - (client->parent == c->parent)) { - ret = cbus_switch_one(client, - c->shared_bus_backup.input, - c->shared_bus_backup.value * - user->div, true); - if (ret) - return ret; - } - } - return 0; -} - -static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - struct clk *user; - - list_for_each_entry(user, &c->shared_bus_list, - u.shared_bus_user.node) { - struct clk *client = user->u.shared_bus_user.client; - if (client && client->refcnt && (client->parent == c->parent)) { - ret = tegra_dvfs_set_rate(c, rate); - if (ret) - return ret; - } - } - return 0; -} - -static void cbus_restore(struct clk *c) -{ - struct clk *user; - - list_for_each_entry(user, &c->shared_bus_list, - u.shared_bus_user.node) { - if (user->u.shared_bus_user.client) - cbus_switch_one(user->u.shared_bus_user.client, - c->parent, c->div * user->div, false); - } -} - -static int get_next_backup_div(struct clk *c, unsigned long rate) -{ - u32 div = c->div; - unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input); - - rate = max(rate, clk_get_rate_locked(c)); - rate = rate - (rate >> 2); /* 25% margin for backup rate */ - if ((u64)rate * div < backup_rate) - div = DIV_ROUND_UP(backup_rate, rate); - - BUG_ON(!div); - return div; -} - -static int tegra14_clk_cbus_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - bool dramp; - - if (rate == 0) - return 0; - - ret = clk_enable(c->parent); - if (ret) { - pr_err("%s: failed to enable %s clock: %d\n", - __func__, c->name, ret); - return ret; - } - - dramp = tegra14_is_dyn_ramp(c->parent, rate * c->div, false); - if (!dramp) { - c->shared_bus_backup.value = get_next_backup_div(c, rate); - ret = cbus_backup(c); - if (ret) - goto out; - } - - ret = clk_set_rate(c->parent, rate * c->div); - if (ret) { - pr_err("%s: failed to set %s clock rate %lu: %d\n", - __func__, c->name, rate, ret); - goto out; - } - - /* Safe voltage setting is taken care of by cbus clock dvfs; the call - * below only records requirements for each enabled client. - */ - if (dramp) - ret = cbus_dvfs_set_rate(c, rate); - - cbus_restore(c); - -out: - clk_disable(c->parent); - return ret; -} - -static inline void cbus_move_enabled_user( - struct clk *user, struct clk *dst, struct clk *src) -{ - clk_enable(dst); - list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list); - clk_disable(src); - clk_reparent(user, dst); -} - -#ifdef CONFIG_TEGRA_DYNAMIC_CBUS -static int tegra14_clk_cbus_update(struct clk *bus) -{ - int ret, mv; - struct clk *slow = NULL; - struct clk *top = NULL; - unsigned long rate; - unsigned long old_rate; - unsigned long ceiling; - - if (detach_shared_bus) - return 0; - - rate = tegra14_clk_shared_bus_update(bus, &top, &slow, &ceiling); - - /* use dvfs table of the slowest enabled client as cbus dvfs table */ - if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) { - int i; - unsigned long *dest = &bus->dvfs->freqs[0]; - unsigned long *src = - &slow->u.shared_bus_user.client->dvfs->freqs[0]; - if (slow->div > 1) - for (i = 0; i < bus->dvfs->num_freqs; i++) - dest[i] = src[i] * slow->div; - else - memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs); - } - - /* update bus state variables and rate */ - bus->u.cbus.slow_user = slow; - bus->u.cbus.top_user = top; - - rate = tegra14_clk_cap_shared_bus(bus, rate, ceiling); - mv = tegra_dvfs_predict_millivolts(bus, rate); - if (IS_ERR_VALUE(mv)) - return -EINVAL; - - if (bus->dvfs) { - mv -= bus->dvfs->cur_millivolts; - if (bus->refcnt && (mv > 0)) { - ret = tegra_dvfs_set_rate(bus, rate); - if (ret) - return ret; - } - } - - old_rate = clk_get_rate_locked(bus); - if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) { - ret = bus->ops->set_rate(bus, rate); - if (ret) - return ret; - } - - if (bus->dvfs) { - if (bus->refcnt && (mv <= 0)) { - ret = tegra_dvfs_set_rate(bus, rate); - if (ret) - return ret; - } - } - - clk_rate_change_notify(bus, rate); - return 0; -}; -#else -static int tegra14_clk_cbus_update(struct clk *bus) -{ - unsigned long rate, old_rate; - - if (detach_shared_bus) - return 0; - - rate = tegra14_clk_shared_bus_update(bus, NULL, NULL, NULL); - - old_rate = clk_get_rate_locked(bus); - if (rate == old_rate) - return 0; - - return clk_set_rate_locked(bus, rate); -} -#endif - -static int tegra14_clk_cbus_migrate_users(struct clk *user) -{ -#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS - struct clk *src_bus, *dst_bus, *top_user, *c; - struct list_head *pos, *n; - - if (!user->u.shared_bus_user.client || !user->inputs) - return 0; - - /* Dual cbus on Tegra14 */ - src_bus = user->inputs[0].input; - dst_bus = user->inputs[1].input; - - if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user) - return 0; - - /* Make sure top user on the source bus is requesting highest rate */ - if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user && - bus_user_request_is_lower(src_bus->u.cbus.top_user, - dst_bus->u.cbus.top_user))) - swap(src_bus, dst_bus); - - /* If top user is the slow one on its own (source) bus, do nothing */ - top_user = src_bus->u.cbus.top_user; - BUG_ON(!top_user->u.shared_bus_user.client); - if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user)) - return 0; - - /* If source bus top user is slower than all users on destination bus, - move top user; otherwise move all users slower than the top one */ - if (!dst_bus->u.cbus.slow_user || - !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) { - cbus_move_enabled_user(top_user, dst_bus, src_bus); - } else { - list_for_each_safe(pos, n, &src_bus->shared_bus_list) { - c = list_entry(pos, struct clk, u.shared_bus_user.node); - if (c->u.shared_bus_user.enabled && - c->u.shared_bus_user.client && - bus_user_is_slower(c, top_user)) - cbus_move_enabled_user(c, dst_bus, src_bus); - } - } - - /* Update destination bus 1st (move clients), then source */ - tegra_clk_shared_bus_update(dst_bus); - tegra_clk_shared_bus_update(src_bus); -#endif - return 0; -} - -static struct clk_ops tegra_clk_cbus_ops = { - .init = tegra14_clk_cbus_init, - .enable = tegra14_clk_cbus_enable, - .set_rate = tegra14_clk_cbus_set_rate, - .round_rate = tegra14_clk_cbus_round_rate, - .round_rate_updown = tegra14_clk_cbus_round_updown, - .shared_bus_update = tegra14_clk_cbus_update, -}; - -/* shared bus ops */ -/* - * Some clocks may have multiple downstream users that need to request a - * higher clock rate. Shared bus clocks provide a unique shared_bus_user - * clock to each user. The frequency of the bus is set to the highest - * enabled shared_bus_user clock, with a minimum value set by the - * shared bus. - * - * Optionally shared bus may support users migration. Since shared bus and - * its * children (users) have reversed rate relations: user rates determine - * bus rate, * switching user from one parent/bus to another may change rates - * of both parents. Therefore we need a cross-bus lock on top of individual - * user and bus locks. For now, limit bus switch support to cbus only if - * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set. - */ - -static unsigned long tegra14_clk_shared_bus_update(struct clk *bus, - struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap) -{ - struct clk *c; - struct clk *slow = NULL; - struct clk *top = NULL; - - unsigned long override_rate = 0; - unsigned long top_rate = 0; - unsigned long rate = bus->min_rate; - unsigned long bw = 0; - unsigned long iso_bw = 0; - unsigned long ceiling = bus->max_rate; - unsigned long ceiling_but_iso = bus->max_rate; - u32 usage_flags = 0; - - list_for_each_entry(c, &bus->shared_bus_list, - u.shared_bus_user.node) { - /* - * Ignore requests from disabled floor and bw users, and from - * auto-users riding the bus. Always honor ceiling users, even - * if they are disabled - we do not want to keep enabled parent - * bus just because ceiling is set. Ignore SCLK/AHB/APB dividers - * to propagate flat max request. - */ - if (c->u.shared_bus_user.enabled || - (c->u.shared_bus_user.mode == SHARED_CEILING) || - (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) { - unsigned long request_rate = c->u.shared_bus_user.rate; - if (!(c->flags & DIV_BUS)) - request_rate *= c->div ? : 1; - usage_flags |= c->u.shared_bus_user.usage_flag; - - switch (c->u.shared_bus_user.mode) { - case SHARED_ISO_BW: - iso_bw += request_rate; - if (iso_bw > bus->max_rate) - iso_bw = bus->max_rate; - /* fall thru */ - case SHARED_BW: - bw += request_rate; - if (bw > bus->max_rate) - bw = bus->max_rate; - break; - case SHARED_CEILING_BUT_ISO: - ceiling_but_iso = - min(request_rate, ceiling_but_iso); - break; - case SHARED_CEILING: - ceiling = min(request_rate, ceiling); - break; - case SHARED_OVERRIDE: - if (override_rate == 0) - override_rate = request_rate; - break; - case SHARED_AUTO: - break; - case SHARED_FLOOR: - default: - rate = max(request_rate, rate); - if (c->u.shared_bus_user.client - && request_rate) { - if (top_rate < request_rate) { - top_rate = request_rate; - top = c; - } else if ((top_rate == request_rate) && - bus_user_is_slower(c, top)) { - top = c; - } - } - } - if (c->u.shared_bus_user.client && - (!slow || bus_user_is_slower(c, slow))) - slow = c; - } - } - - if (bus->flags & PERIPH_EMC_ENB) { - unsigned long iso_bw_min; - bw = tegra_emc_apply_efficiency( - bw, iso_bw, bus->max_rate, usage_flags, &iso_bw_min); - if (bus->ops && bus->ops->round_rate) - iso_bw_min = bus->ops->round_rate(bus, iso_bw_min); - ceiling_but_iso = max(ceiling_but_iso, iso_bw_min); - } - - rate = override_rate ? : max(rate, bw); - ceiling = min(ceiling, ceiling_but_iso); - ceiling = override_rate ? bus->max_rate : ceiling; - bus->override_rate = override_rate; - - if (bus_top && bus_slow && rate_cap) { - /* If dynamic bus dvfs table, let the caller to complete - rounding and aggregation */ - *bus_top = top; - *bus_slow = slow; - *rate_cap = ceiling; - } else { - /* If satic bus dvfs table, complete rounding and aggregation */ - rate = tegra14_clk_cap_shared_bus(bus, rate, ceiling); - } - - return rate; -}; - -static unsigned long tegra14_clk_cap_shared_bus(struct clk *bus, - unsigned long rate, unsigned long ceiling) -{ - if (bus->ops && bus->ops->round_rate_updown) - ceiling = bus->ops->round_rate_updown(bus, ceiling, false); - - rate = min(rate, ceiling); - - if (bus->ops && bus->ops->round_rate) - rate = bus->ops->round_rate(bus, rate); - - return rate; -} - -static int tegra_clk_shared_bus_migrate_users(struct clk *user) -{ - if (detach_shared_bus) - return 0; - - /* Only cbus migration is supported */ - if (user->flags & PERIPH_ON_CBUS) - return tegra14_clk_cbus_migrate_users(user); - return -ENOSYS; -} - -static void tegra_clk_shared_bus_user_init(struct clk *c) -{ - c->max_rate = c->parent->max_rate; - c->u.shared_bus_user.rate = c->parent->max_rate; - c->state = OFF; - c->set = true; - - if ((c->u.shared_bus_user.mode == SHARED_CEILING) || - (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) { - c->state = ON; - c->refcnt++; - } - - if (c->u.shared_bus_user.client_id) { - c->u.shared_bus_user.client = - tegra_get_clock_by_name(c->u.shared_bus_user.client_id); - if (!c->u.shared_bus_user.client) { - pr_err("%s: could not find clk %s\n", __func__, - c->u.shared_bus_user.client_id); - return; - } - c->u.shared_bus_user.client->flags |= - c->parent->flags & PERIPH_ON_CBUS; - c->flags |= c->parent->flags & PERIPH_ON_CBUS; - c->div = c->u.shared_bus_user.client_div ? : 1; - c->mul = 1; - } - - list_add_tail(&c->u.shared_bus_user.node, - &c->parent->shared_bus_list); -} - -static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p) -{ - int ret; - const struct clk_mux_sel *sel; - - if (detach_shared_bus) - return 0; - - if (c->parent == p) - return 0; - - if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c))) - return -ENOSYS; - - for (sel = c->inputs; sel->input != NULL; sel++) { - if (sel->input == p) - break; - } - if (!sel->input) - return -EINVAL; - - if (c->refcnt) - clk_enable(p); - - list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list); - ret = tegra_clk_shared_bus_update(p); - if (ret) { - list_move_tail(&c->u.shared_bus_user.node, - &c->parent->shared_bus_list); - tegra_clk_shared_bus_update(c->parent); - clk_disable(p); - return ret; - } - - tegra_clk_shared_bus_update(c->parent); - - if (c->refcnt) - clk_disable(c->parent); - - clk_reparent(c, p); - - return 0; -} - -static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - - c->u.shared_bus_user.rate = rate; - ret = tegra_clk_shared_bus_update(c->parent); - - if (!ret && c->cross_clk_mutex && clk_cansleep(c)) - tegra_clk_shared_bus_migrate_users(c); - - return ret; -} - -static long tegra_clk_shared_bus_user_round_rate( - struct clk *c, unsigned long rate) -{ - /* - * Defer rounding requests until aggregated. BW users must not be - * rounded at all, others just clipped to bus range (some clients - * may use round api to find limits). Ignore SCLK/AHB and AHB/APB - * dividers to keep flat bus requests propagation. - */ - if ((c->u.shared_bus_user.mode != SHARED_BW) && - (c->u.shared_bus_user.mode != SHARED_ISO_BW)) { - if (!(c->flags & DIV_BUS) && (c->div > 1)) - rate *= c->div; - - if (rate > c->parent->max_rate) - rate = c->parent->max_rate; - else if (rate < c->parent->min_rate) - rate = c->parent->min_rate; - - if (!(c->flags & DIV_BUS) && (c->div > 1)) - rate /= c->div; - } - return rate; -} - -static int tegra_clk_shared_bus_user_enable(struct clk *c) -{ - int ret; - - c->u.shared_bus_user.enabled = true; - ret = tegra_clk_shared_bus_update(c->parent); - if (!ret && c->u.shared_bus_user.client) - ret = clk_enable(c->u.shared_bus_user.client); - - if (!ret && c->cross_clk_mutex && clk_cansleep(c)) - tegra_clk_shared_bus_migrate_users(c); - - return ret; -} - -static void tegra_clk_shared_bus_user_disable(struct clk *c) -{ - if (c->u.shared_bus_user.client) - clk_disable(c->u.shared_bus_user.client); - c->u.shared_bus_user.enabled = false; - tegra_clk_shared_bus_update(c->parent); - - if (c->cross_clk_mutex && clk_cansleep(c)) - tegra_clk_shared_bus_migrate_users(c); -} - -static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert) -{ - if (c->u.shared_bus_user.client) { - if (c->u.shared_bus_user.client->ops && - c->u.shared_bus_user.client->ops->reset) - c->u.shared_bus_user.client->ops->reset( - c->u.shared_bus_user.client, assert); - } -} - -static struct clk_ops tegra_clk_shared_bus_user_ops = { - .init = tegra_clk_shared_bus_user_init, - .enable = tegra_clk_shared_bus_user_enable, - .disable = tegra_clk_shared_bus_user_disable, - .set_parent = tegra_clk_shared_bus_user_set_parent, - .set_rate = tegra_clk_shared_bus_user_set_rate, - .round_rate = tegra_clk_shared_bus_user_round_rate, - .reset = tegra_clk_shared_bus_user_reset, -}; - -/* - * AHB and APB shared bus operations - * APB shared bus is a user of AHB shared bus - * AHB shared bus is a user of SCLK complex shared bus - * SCLK/AHB and AHB/APB dividers can be dynamically changed. When AHB and APB - * users requests are propagated to SBUS target rate, current values of the - * dividers are ignored, and flat maximum request is selected as SCLK bus final - * target. Then the dividers will be re-evaluated, based on AHB and APB targets. - * Both AHB and APB buses are always enabled. - */ -static void tegra14_clk_ahb_apb_init(struct clk *c, struct clk *bus_clk) -{ - tegra_clk_shared_bus_user_init(c); - c->max_rate = bus_clk->max_rate; - c->min_rate = bus_clk->min_rate; - c->mul = bus_clk->mul; - c->div = bus_clk->div; - - c->u.shared_bus_user.rate = clk_get_rate(bus_clk); - c->u.shared_bus_user.enabled = true; - c->parent->child_bus = c; -} - -static void tegra14_clk_ahb_init(struct clk *c) -{ - struct clk *bus_clk = c->parent->u.system.hclk; - tegra14_clk_ahb_apb_init(c, bus_clk); -} - -static void tegra14_clk_apb_init(struct clk *c) -{ - struct clk *bus_clk = c->parent->parent->u.system.pclk; - tegra14_clk_ahb_apb_init(c, bus_clk); -} - -static int tegra14_clk_ahb_apb_update(struct clk *bus) -{ - unsigned long rate; - - if (detach_shared_bus) - return 0; - - rate = tegra14_clk_shared_bus_update(bus, NULL, NULL, NULL); - return clk_set_rate_locked(bus, rate); -} - -static struct clk_ops tegra_clk_ahb_ops = { - .init = tegra14_clk_ahb_init, - .set_rate = tegra_clk_shared_bus_user_set_rate, - .round_rate = tegra_clk_shared_bus_user_round_rate, - .shared_bus_update = tegra14_clk_ahb_apb_update, -}; - -static struct clk_ops tegra_clk_apb_ops = { - .init = tegra14_clk_apb_init, - .set_rate = tegra_clk_shared_bus_user_set_rate, - .round_rate = tegra_clk_shared_bus_user_round_rate, - .shared_bus_update = tegra14_clk_ahb_apb_update, -}; - -/* Clock definitions */ -static struct clk tegra_clk_32k = { - .name = "clk_32k", - .rate = 32768, - .ops = NULL, - .max_rate = 32768, -}; - -static struct clk tegra_osc = { - .name = "osc", - .flags = ENABLE_ON_INIT, - .ops = &tegra_osc_ops, - .reg = 0x1fc, - .reg_shift = 28, - .max_rate = 48000000, -}; - -static struct clk tegra_osc_div2 = { - .name = "osc_div2", - .ops = &tegra_osc_div_ops, - .parent = &tegra_osc, - .mul = 1, - .div = 2, - .state = ON, - .max_rate = 24000000, -}; - -static struct clk tegra_osc_div4 = { - .name = "osc_div4", - .ops = &tegra_osc_div_ops, - .parent = &tegra_osc, - .mul = 1, - .div = 4, - .state = ON, - .max_rate = 12000000, -}; - -static struct clk tegra_clk_m = { - .name = "clk_m", - .ops = &tegra_clk_m_ops, - .parent = &tegra_osc, - .max_rate = 48000000, -}; - -static struct clk tegra_pll_ref = { - .name = "pll_ref", - .flags = ENABLE_ON_INIT, - .ops = &tegra_pll_ref_ops, - .parent = &tegra_osc, - .max_rate = 26000000, -}; - -static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { - { 12000000, 624000000, 104, 1, 2}, - { 12000000, 600000000, 100, 1, 2}, - { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_c = { - .name = "pll_c", - .ops = &tegra_pllxc_ops, - .reg = 0x80, - .parent = &tegra_pll_ref, - .max_rate = 1400000000, - .u.pll = { - .input_min = 12000000, - .input_max = 800000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ - .vco_min = 600000000, - .vco_max = 1400000000, - .freq_table = tegra_pll_c_freq_table, - .lock_delay = 300, - .misc1 = 0x88 - 0x80, - .round_p_to_pdiv = pllxc_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_c_out1 = { - .name = "pll_c_out1", - .ops = &tegra_pll_div_ops, -#ifdef CONFIG_TEGRA_DUAL_CBUS - .flags = DIV_U71 | DIV_U71_INT, -#else - .flags = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS, -#endif - .parent = &tegra_pll_c, - .reg = 0x84, - .reg_shift = 0, - .max_rate = 700000000, -}; - -static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = { - { 12000000, 600000000, 100, 1, 2}, - { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_c2 = { - .name = "pll_c2", - .ops = &tegra_pllcx_ops, - .flags = PLL_ALT_MISC_REG, - .reg = 0x4e8, - .parent = &tegra_pll_ref, - .max_rate = 1200000000, - .u.pll = { - .input_min = 12000000, - .input_max = 48000000, - .cf_min = 12000000, - .cf_max = 19200000, - .vco_min = 624000000, - .vco_max = 1248000000, - .freq_table = tegra_pll_cx_freq_table, - .lock_delay = 300, - .misc1 = 0x4f0 - 0x4e8, - .round_p_to_pdiv = pllcx_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_c3 = { - .name = "pll_c3", - .ops = &tegra_pllcx_ops, - .flags = PLL_ALT_MISC_REG, - .reg = 0x4fc, - .parent = &tegra_pll_ref, - .max_rate = 1200000000, - .u.pll = { - .input_min = 12000000, - .input_max = 48000000, - .cf_min = 12000000, - .cf_max = 19200000, - .vco_min = 624000000, - .vco_max = 1248000000, - .freq_table = tegra_pll_cx_freq_table, - .lock_delay = 300, - .misc1 = 0x504 - 0x4fc, - .round_p_to_pdiv = pllcx_round_p_to_pdiv, - }, -}; - -static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { - { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */ - { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ - { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */ - { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */ - { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */ - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_m = { - .name = "pll_m", - .flags = PLLM, - .ops = &tegra_pllm_ops, - .reg = 0x90, - .parent = &tegra_pll_ref, - .max_rate = 1066000000, - .u.pll = { - .input_min = 12000000, - .input_max = 500000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ - .vco_min = 500000000, - .vco_max = 1066000000, - .freq_table = tegra_pll_m_freq_table, - .lock_delay = 300, - .misc1 = 0x98 - 0x90, - .round_p_to_pdiv = pllm_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_m_out1 = { - .name = "pll_m_out1", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_INT, - .parent = &tegra_pll_m, - .reg = 0x94, - .reg_shift = 0, - .max_rate = 1066000000, -}; - -static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { - /* Parameters below are made up just to satisfy software */ - { 12000000, 408000000, 816, 12, 2, 8}, - { 13000000, 408000000, 816, 13, 2, 8}, - { 16800000, 408000000, 680, 14, 2, 8}, - { 19200000, 408000000, 680, 16, 2, 8}, - { 26000000, 408000000, 816, 26, 2, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_p = { - .name = "pll_p", - .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, - .ops = &tegra_pllp_ops, - .reg = 0xa0, - .parent = &tegra_pll_ref, - .max_rate = 432000000, - .u.pll = { - .input_min = 2000000, - .input_max = 31000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 200000000, - .vco_max = 700000000, - .freq_table = tegra_pll_p_freq_table, - .lock_delay = 300, - }, -}; - -static struct clk tegra_pll_p_out1 = { - .name = "pll_p_out1", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED, - .parent = &tegra_pll_p, - .reg = 0xa4, - .reg_shift = 0, - .max_rate = 432000000, -}; - -static struct clk tegra_pll_p_out2 = { - .name = "pll_p_out2", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT, - .parent = &tegra_pll_p, - .reg = 0xa4, - .reg_shift = 16, - .max_rate = 432000000, -}; - -static struct clk tegra_pll_p_out3 = { - .name = "pll_p_out3", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED, - .parent = &tegra_pll_p, - .reg = 0xa8, - .reg_shift = 0, - .max_rate = 432000000, -}; - -static struct clk tegra_pll_p_out4 = { - .name = "pll_p_out4", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71 | DIV_U71_FIXED, - .parent = &tegra_pll_p, - .reg = 0xa8, - .reg_shift = 16, - .max_rate = 432000000, -}; - -static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { - { 9600000, 282240000, 147, 5, 1, 4}, - { 9600000, 368640000, 192, 5, 1, 4}, - { 9600000, 240000000, 200, 8, 1, 8}, - - { 28800000, 282240000, 245, 25, 1, 8}, - { 28800000, 368640000, 320, 25, 1, 8}, - { 28800000, 240000000, 200, 24, 1, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_a = { - .name = "pll_a", - .flags = PLL_HAS_CPCON, - .ops = &tegra_pll_ops, - .reg = 0xb0, - .parent = &tegra_pll_p_out1, - .max_rate = 700000000, - .u.pll = { - .input_min = 2000000, - .input_max = 31000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 200000000, - .vco_max = 700000000, - .freq_table = tegra_pll_a_freq_table, - .lock_delay = 300, - }, -}; - -static struct clk tegra_pll_a_out0 = { - .name = "pll_a_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_U71, - .parent = &tegra_pll_a, - .reg = 0xb4, - .reg_shift = 0, - .max_rate = 100000000, -}; - -static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { - { 12000000, 216000000, 864, 12, 4, 12}, - { 13000000, 216000000, 864, 13, 4, 12}, - { 16800000, 216000000, 720, 14, 4, 12}, - { 19200000, 216000000, 720, 16, 4, 12}, - { 26000000, 216000000, 864, 26, 4, 12}, - - { 12000000, 594000000, 594, 12, 1, 12}, - { 13000000, 594000000, 594, 13, 1, 12}, - { 16800000, 594000000, 495, 14, 1, 12}, - { 19200000, 594000000, 495, 16, 1, 12}, - { 26000000, 594000000, 594, 26, 1, 12}, - - { 12000000, 1000000000, 1000, 12, 1, 12}, - { 13000000, 1000000000, 1000, 13, 1, 12}, - { 19200000, 1000000000, 625, 12, 1, 12}, - { 26000000, 1000000000, 1000, 26, 1, 12}, - - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_d = { - .name = "pll_d", - .flags = PLL_HAS_CPCON | PLLD, - .ops = &tegra_plld_ops, - .reg = 0xd0, - .parent = &tegra_pll_ref, - .max_rate = 1000000000, - .u.pll = { - .input_min = 2000000, - .input_max = 40000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 500000000, - .vco_max = 1000000000, - .freq_table = tegra_pll_d_freq_table, - .lock_delay = 1000, - }, -}; - -static struct clk tegra_pll_d_out0 = { - .name = "pll_d_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_2 | PLLD, - .parent = &tegra_pll_d, - .max_rate = 500000000, -}; - -static struct clk tegra_pll_d2 = { - .name = "pll_d2", - .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, - .ops = &tegra_plld_ops, - .reg = 0x4b8, - .parent = &tegra_pll_ref, - .max_rate = 1000000000, - .u.pll = { - .input_min = 2000000, - .input_max = 40000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 500000000, - .vco_max = 1000000000, - .freq_table = tegra_pll_d_freq_table, - .lock_delay = 1000, - }, -}; - -static struct clk tegra_pll_d2_out0 = { - .name = "pll_d2_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_2 | PLLD, - .parent = &tegra_pll_d2, - .max_rate = 500000000, -}; - -static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 2, 12}, - { 13000000, 480000000, 960, 13, 2, 12}, - { 16800000, 480000000, 400, 7, 2, 5}, - { 19200000, 480000000, 200, 4, 2, 3}, - { 26000000, 480000000, 960, 26, 2, 12}, - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_u = { - .name = "pll_u", - .flags = PLL_HAS_CPCON | PLLU, - .ops = &tegra_pll_ops, - .reg = 0xc0, - .parent = &tegra_pll_ref, - .max_rate = 480000000, - .u.pll = { - .input_min = 2000000, - .input_max = 40000000, - .cf_min = 1000000, - .cf_max = 6000000, - .vco_min = 480000000, - .vco_max = 960000000, - .freq_table = tegra_pll_u_freq_table, - .lock_delay = 1000, - .cpcon_default = 12, - }, -}; - -static struct clk tegra_pll_u_480M = { - .name = "pll_u_480M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 22, - .parent = &tegra_pll_u, - .mul = 1, - .div = 1, - .max_rate = 480000000, -}; - -static struct clk tegra_pll_u_60M = { - .name = "pll_u_60M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 23, - .parent = &tegra_pll_u, - .mul = 1, - .div = 8, - .max_rate = 60000000, -}; - -static struct clk tegra_pll_u_48M = { - .name = "pll_u_48M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 25, - .parent = &tegra_pll_u, - .mul = 1, - .div = 10, - .max_rate = 48000000, -}; - -static struct clk tegra_pll_u_12M = { - .name = "pll_u_12M", - .flags = PLLU, - .ops = &tegra_pll_div_ops, - .reg = 0xc0, - .reg_shift = 21, - .parent = &tegra_pll_u, - .mul = 1, - .div = 40, - .max_rate = 12000000, -}; - -static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { - /* 1 GHz */ - { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */ - { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ - { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */ - { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */ - { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */ - - { 0, 0, 0, 0, 0, 0 }, -}; - -static struct clk tegra_pll_x = { - .name = "pll_x", - .flags = PLL_ALT_MISC_REG | PLLX, - .ops = &tegra_pllxc_ops, - .reg = 0xe0, - .parent = &tegra_pll_ref, - .max_rate = 1800000000, - .u.pll = { - .input_min = 12000000, - .input_max = 800000000, - .cf_min = 12000000, - .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ - .vco_min = 700000000, - .vco_max = 2600000000U, - .freq_table = tegra_pll_x_freq_table, - .lock_delay = 300, - .misc1 = 0x510 - 0xe0, - .round_p_to_pdiv = pllxc_round_p_to_pdiv, - }, -}; - -static struct clk tegra_pll_x_out0 = { - .name = "pll_x_out0", - .ops = &tegra_pll_div_ops, - .flags = DIV_2 | PLLX, - .parent = &tegra_pll_x, - .max_rate = 700000000, -}; - -/* FIXME: remove; for now, should be always checked-in as "0" */ -#define USE_LP_CPU_TO_TEST_DFLL 0 - -static struct clk tegra_dfll_cpu = { - .name = "dfll_cpu", - .flags = DFLL, - .ops = &tegra_dfll_ops, - .reg = 0x2f4, - .max_rate = 2116500000UL, -}; - -/* Audio sync clocks */ -#define SYNC_SOURCE(_id, _dev) \ - { \ - .name = #_id "_sync", \ - .lookup = { \ - .dev_id = #_dev , \ - .con_id = "ext_audio_sync", \ - }, \ - .rate = 24000000, \ - .max_rate = 24000000, \ - .ops = &tegra_sync_source_ops \ - } -static struct clk tegra_sync_source_list[] = { - SYNC_SOURCE(i2s0, tegra30-i2s.0), - SYNC_SOURCE(i2s1, tegra30-i2s.1), - SYNC_SOURCE(i2s2, tegra30-i2s.2), - SYNC_SOURCE(i2s3, tegra30-i2s.3), - SYNC_SOURCE(i2s4, tegra30-i2s.4), - SYNC_SOURCE(vimclk, vimclk), -}; - -static struct clk_mux_sel mux_d_audio_clk[] = { - { .input = &tegra_pll_a_out0, .value = 0x0001}, - { .input = &tegra_pll_p, .value = 0x8001}, - { .input = &tegra_clk_m, .value = 0xc001}, - { .input = &tegra_sync_source_list[0], .value = 0xE001}, - { .input = &tegra_sync_source_list[1], .value = 0xE002}, - { .input = &tegra_sync_source_list[2], .value = 0xE003}, - { .input = &tegra_sync_source_list[3], .value = 0xE004}, - { .input = &tegra_sync_source_list[4], .value = 0xE005}, - { .input = &tegra_pll_a_out0, .value = 0xE006}, - { .input = &tegra_sync_source_list[5], .value = 0xE007}, - { 0, 0 } -}; - -static struct clk_mux_sel mux_audio_sync_clk[] = { - { .input = &tegra_sync_source_list[0], .value = 1}, - { .input = &tegra_sync_source_list[1], .value = 2}, - { .input = &tegra_sync_source_list[2], .value = 3}, - { .input = &tegra_sync_source_list[3], .value = 4}, - { .input = &tegra_sync_source_list[4], .value = 5}, - { .input = &tegra_pll_a_out0, .value = 6}, - { .input = &tegra_sync_source_list[5], .value = 7}, - { 0, 0 } -}; - -#define AUDIO_SYNC_CLK(_id, _dev, _index) \ - { \ - .name = #_id, \ - .lookup = { \ - .dev_id = #_dev, \ - .con_id = "audio_sync", \ - }, \ - .inputs = mux_audio_sync_clk, \ - .reg = 0x4A0 + (_index) * 4, \ - .max_rate = 24000000, \ - .ops = &tegra_audio_sync_clk_ops \ - } -static struct clk tegra_clk_audio_list[] = { - AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0), - AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1), - AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2), - AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3), - AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4), -}; - -#define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \ - { \ - .name = #_id "_2x", \ - .lookup = { \ - .dev_id = #_dev, \ - .con_id = "audio_sync_2x" \ - }, \ - .flags = PERIPH_NO_RESET, \ - .max_rate = 48000000, \ - .ops = &tegra_clk_double_ops, \ - .reg = 0x49C, \ - .reg_shift = 24 + (_index), \ - .parent = &tegra_clk_audio_list[(_index)], \ - .u.periph = { \ - .clk_num = 113 + (_index), \ - }, \ - } -static struct clk tegra_clk_audio_2x_list[] = { - AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0), - AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1), - AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2), - AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3), - AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4), -}; - -#define MUX_I2S_SPDIF(_id, _index) \ -static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ - {.input = &tegra_pll_a_out0, .value = 0}, \ - {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ - {.input = &tegra_pll_p, .value = 2}, \ - {.input = &tegra_clk_m, .value = 3}, \ - { 0, 0}, \ -} -MUX_I2S_SPDIF(audio0, 0); -MUX_I2S_SPDIF(audio1, 1); -MUX_I2S_SPDIF(audio2, 2); -MUX_I2S_SPDIF(audio3, 3); -MUX_I2S_SPDIF(audio4, 4); - -/* Audio sync dmic clocks */ -#define AUDIO_SYNC_DMIC_CLK(_id, _dev, _index) \ - { \ - .name = #_id "dmic", \ - .lookup = { \ - .dev_id = #_dev, \ - .con_id = "audio_sync_dmic", \ - }, \ - .inputs = mux_audio_sync_clk, \ - .reg = 0x560 + (_index) * 4, \ - .max_rate = 24000000, \ - .ops = &tegra_audio_sync_clk_ops \ - } - -static struct clk tegra_clk_audio_dmic_list[] = { - AUDIO_SYNC_DMIC_CLK(audio0, tegra30-i2s.0, 0), - AUDIO_SYNC_DMIC_CLK(audio1, tegra30-i2s.1, 1), -}; - -#define MUX_AUDIO_DMIC(_id, _index) \ -static struct clk_mux_sel mux_pllaout0_##_id##_dmic_pllp_clkm[] = { \ - {.input = &tegra_pll_a_out0, .value = 0}, \ - {.input = &tegra_clk_audio_dmic_list[(_index)], .value = 1}, \ - {.input = &tegra_pll_p, .value = 2}, \ - {.input = &tegra_clk_m, .value = 3}, \ - { 0, 0}, \ -} -MUX_AUDIO_DMIC(audio0, 0); -MUX_AUDIO_DMIC(audio1, 1); - - -/* External clock outputs (through PMC) */ -#define MUX_EXTERN_OUT(_id) \ -static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \ - {.input = &tegra_osc, .value = 0}, \ - {.input = &tegra_osc_div2, .value = 1}, \ - {.input = &tegra_osc_div4, .value = 2}, \ - {.input = NULL, .value = 3}, /* placeholder */ \ - { 0, 0}, \ -} -MUX_EXTERN_OUT(1); -MUX_EXTERN_OUT(2); -MUX_EXTERN_OUT(3); - -static struct clk_mux_sel *mux_extern_out_list[] = { - mux_clkm_clkm2_clkm4_extern1, - mux_clkm_clkm2_clkm4_extern2, - mux_clkm_clkm2_clkm4_extern3, -}; - -#define CLK_OUT_CLK(_id, _max_rate) \ - { \ - .name = "clk_out_" #_id, \ - .lookup = { \ - .dev_id = "clk_out_" #_id, \ - .con_id = "extern" #_id, \ - }, \ - .ops = &tegra_clk_out_ops, \ - .reg = 0x1a8, \ - .inputs = mux_clkm_clkm2_clkm4_extern##_id, \ - .flags = MUX_CLK_OUT, \ - .max_rate = _max_rate, \ - .u.periph = { \ - .clk_num = (_id - 1) * 8 + 2, \ - }, \ - } -static struct clk tegra_clk_out_list[] = { - CLK_OUT_CLK(1, 38400000), - CLK_OUT_CLK(2, 40800000), - CLK_OUT_CLK(3, 38400000), -}; - -/* called after peripheral external clocks are initialized */ -static void init_clk_out_mux(void) -{ - int i; - struct clk *c; - - /* output clock con_id is the name of peripheral - external clock connected to input 3 of the output mux */ - for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) { - c = tegra_get_clock_by_name( - tegra_clk_out_list[i].lookup.con_id); - if (!c) - pr_err("%s: could not find clk %s\n", __func__, - tegra_clk_out_list[i].lookup.con_id); - mux_extern_out_list[i][3].input = c; - } -} - -/* Peripheral muxes */ -static struct clk_mux_sel mux_cclk_g[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_clk_32k, .value = 2}, - { .input = &tegra_pll_m, .value = 3}, - { .input = &tegra_pll_p, .value = 4}, - { .input = &tegra_pll_p_out4, .value = 5}, - /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra14x */ - /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra14x */ - { .input = &tegra_pll_x, .value = 8}, - { .input = &tegra_dfll_cpu, .value = 15}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_cclk_lp[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_clk_32k, .value = 2}, - { .input = &tegra_pll_m, .value = 3}, - { .input = &tegra_pll_p, .value = 4}, - { .input = &tegra_pll_p_out4, .value = 5}, - /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra14x */ - /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra14x */ - { .input = &tegra_pll_x_out0, .value = 8}, -#if USE_LP_CPU_TO_TEST_DFLL - { .input = &tegra_dfll_cpu, .value = 15}, -#endif - { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_sclk[] = { - { .input = &tegra_clk_m, .value = 0}, - { .input = &tegra_pll_c_out1, .value = 1}, - { .input = &tegra_pll_p_out4, .value = 2}, - { .input = &tegra_pll_p, .value = 3}, - { .input = &tegra_pll_p_out2, .value = 4}, - { .input = &tegra_pll_c, .value = 5}, - { .input = &tegra_clk_32k, .value = 6}, - { .input = &tegra_pll_m_out1, .value = 7}, - { 0, 0}, -}; - -static struct clk tegra_clk_cclk_g = { - .name = "cclk_g", - .flags = DIV_U71 | DIV_U71_INT | MUX, - .inputs = mux_cclk_g, - .reg = 0x368, - .ops = &tegra_super_ops, - .max_rate = 2116500000UL, -}; - -static struct clk tegra_clk_cclk_lp = { - .name = "cclk_lp", - .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX, - .inputs = mux_cclk_lp, - .reg = 0x370, - .ops = &tegra_super_ops, - .max_rate = 900000000, -}; - -static struct clk tegra_clk_sclk = { - .name = "sclk", - .inputs = mux_sclk, - .reg = 0x28, - .ops = &tegra_super_ops, - .max_rate = 384000000, - .min_rate = 12000000, -}; - -static struct clk tegra_clk_virtual_cpu_g = { - .name = "cpu_g", - .parent = &tegra_clk_cclk_g, - .ops = &tegra_cpu_ops, - .max_rate = 2116500000UL, - .u.cpu = { - .main = &tegra_pll_x, - .backup = &tegra_pll_p_out4, - .dynamic = &tegra_dfll_cpu, - .mode = MODE_G, - }, -}; - -static struct clk tegra_clk_virtual_cpu_lp = { - .name = "cpu_lp", - .parent = &tegra_clk_cclk_lp, - .ops = &tegra_cpu_ops, - .max_rate = 900000000, - .u.cpu = { - .main = &tegra_pll_x, - .backup = &tegra_pll_p_out4, -#if USE_LP_CPU_TO_TEST_DFLL - .dynamic = &tegra_dfll_cpu, -#endif - .mode = MODE_LP, - }, -}; - -static struct clk_mux_sel mux_cpu_cmplx[] = { - { .input = &tegra_clk_virtual_cpu_g, .value = 0}, - { .input = &tegra_clk_virtual_cpu_lp, .value = 1}, - { 0, 0}, -}; - -static struct clk tegra_clk_cpu_cmplx = { - .name = "cpu", - .inputs = mux_cpu_cmplx, - .ops = &tegra_cpu_cmplx_ops, - .max_rate = 2116500000UL, -}; - -static struct clk tegra_clk_cop = { - .name = "cop", - .parent = &tegra_clk_sclk, - .ops = &tegra_cop_ops, - .max_rate = 384000000, -}; - -static struct clk tegra_clk_hclk = { - .name = "hclk", - .flags = DIV_BUS, - .parent = &tegra_clk_sclk, - .reg = 0x30, - .reg_shift = 4, - .ops = &tegra_bus_ops, - .max_rate = 384000000, - .min_rate = 12000000, -}; - -static struct clk tegra_clk_pclk = { - .name = "pclk", - .flags = DIV_BUS, - .parent = &tegra_clk_hclk, - .reg = 0x30, - .reg_shift = 0, - .ops = &tegra_bus_ops, - .max_rate = 192000000, - .min_rate = 12000000, -}; - -static struct raw_notifier_head sbus_rate_change_nh; - -static struct clk tegra_clk_sbus_cmplx = { - .name = "sbus", - .parent = &tegra_clk_sclk, - .ops = &tegra_sbus_cmplx_ops, - .u.system = { - .pclk = &tegra_clk_pclk, - .hclk = &tegra_clk_hclk, - .sclk_low = &tegra_pll_p_out2, -#ifdef CONFIG_TEGRA_PLLM_SCALED - .sclk_high = &tegra_pll_c_out1, -#else - .sclk_high = &tegra_pll_m_out1, -#endif - }, - .rate_change_nh = &sbus_rate_change_nh, -}; - -static struct clk tegra_clk_ahb = { - .name = "ahb.sclk", - .flags = DIV_BUS, - .parent = &tegra_clk_sbus_cmplx, - .ops = &tegra_clk_ahb_ops, -}; - -static struct clk tegra_clk_apb = { - .name = "apb.sclk", - .flags = DIV_BUS, - .parent = &tegra_clk_ahb, - .ops = &tegra_clk_apb_ops, -}; - -static struct clk tegra_clk_blink = { - .name = "blink", - .parent = &tegra_clk_32k, - .reg = 0x40, - .ops = &tegra_blink_clk_ops, - .max_rate = 32768, -}; - - -/* Multimedia modules muxes */ -static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = { - { .input = &tegra_pll_m, .value = 0}, - { .input = &tegra_pll_c2, .value = 1}, - { .input = &tegra_pll_c, .value = 2}, - { .input = &tegra_pll_c3, .value = 3}, - { .input = &tegra_pll_p, .value = 4}, - { .input = &tegra_pll_a_out0, .value = 6}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { - { .input = &tegra_pll_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_pll_a_out0, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = { - { .input = &tegra_pll_a_out0, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -/* EMC muxes */ -/* FIXME: add EMC latency mux */ -static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { - { .input = &tegra_pll_m, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */ - /* { .input = &tegra_pll_c2, .value = 5}, - no use on tegra14x */ - /* { .input = &tegra_pll_c3, .value = 6}, - no use on tegra14x */ - { .input = &tegra_pll_c, .value = 7}, /* low jitter PLLM input */ - { 0, 0}, -}; - - -/* Display subsystem muxes */ -static struct clk_mux_sel mux_plld2[] = { - {.input = &tegra_pll_d2_out0, .value = 5}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plld_plld2_clkm[] = { - {.input = &tegra_pll_d_out0, .value = 2}, - {.input = &tegra_pll_d2_out0, .value = 5}, - {.input = &tegra_clk_m, .value = 6}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plld_out0_plld2_out0[] = { - { .input = &tegra_pll_d_out0, .value = 0}, - { .input = &tegra_pll_d2_out0, .value = 1}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_clkm[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -/* Peripheral muxes */ -static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_pll_c2, .value = 1}, - { .input = &tegra_pll_c, .value = 2}, - { .input = &tegra_pll_c3, .value = 3}, - { .input = &tegra_pll_m, .value = 4}, - { .input = &tegra_clk_m, .value = 6}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_pll_m, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_clkm[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_clkm1[] = { - { .input = &tegra_pll_p, .value = 0}, - { .input = &tegra_clk_m, .value = 1}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_clk_32k, .value = 2}, - {.input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = { - {.input = &tegra_pll_p, .value = 0}, - {.input = &tegra_pll_c, .value = 1}, - {.input = &tegra_clk_m, .value = 2}, - {.input = &tegra_clk_32k, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_plla_clk32_pllp_clkm[] = { - { .input = &tegra_pll_a_out0, .value = 0}, - { .input = &tegra_clk_32k, .value = 1}, - { .input = &tegra_pll_p, .value = 2}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp3_pllc_clkm[] = { - { .input = &tegra_pll_p_out3, .value = 0}, - { .input = &tegra_pll_c, .value = 1}, - { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, -}; - -/* Single clock source ("fake") muxes */ -static struct clk_mux_sel mux_clk_m[] = { - { .input = &tegra_clk_m, .value = 0}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pllp_out3[] = { - { .input = &tegra_pll_p_out3, .value = 0}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_clk_32k[] = { - { .input = &tegra_clk_32k, .value = 0}, - { 0, 0}, -}; - -static struct clk tegra_clk_emc; -static struct clk_mux_sel mux_clk_emc[] = { - { .input = &tegra_clk_emc, .value = 0}, - { 0, 0}, -}; - -static struct clk_mux_sel mux_pll_p[] = { - { .input = &tegra_pll_p, .value = 0}, - { 0, 0}, -}; - -static struct raw_notifier_head emc_rate_change_nh; - -static struct clk tegra_clk_emc = { - .name = "emc", - .ops = &tegra_emc_clk_ops, - .reg = 0x19c, - .max_rate = 1066000000, - .min_rate = 12750000, - .inputs = mux_pllm_pllc_pllp_clkm, - .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB, - .u.periph = { - .clk_num = 57, - }, - .rate_change_nh = &emc_rate_change_nh, -}; - -static struct raw_notifier_head host1x_rate_change_nh; - -static struct clk tegra_clk_host1x = { - .name = "host1x", - .lookup = { - .dev_id = "host1x", - }, - .ops = &tegra_1xbus_clk_ops, - .reg = 0x180, - .inputs = mux_pllm_pllc_pllp_plla, - .flags = MUX | DIV_U71 | DIV_U71_INT, - .max_rate = 408000000, - .min_rate = 12000000, - .u.periph = { - .clk_num = 28, - .pll_low = &tegra_pll_p, -#ifdef CONFIG_TEGRA_PLLM_SCALED - .pll_high = &tegra_pll_c, -#else - .pll_high = &tegra_pll_m, -#endif - }, - .rate_change_nh = &host1x_rate_change_nh, -}; - -static struct raw_notifier_head msenc_rate_change_nh; - -static struct clk tegra_clk_msenc = { - .name = "msenc", - .lookup = { - .dev_id = "msenc", - }, - .ops = &tegra_1xbus_clk_ops, - .reg = 0x1f0, - .inputs = mux_pllm_pllc_pllp_plla, - .flags = MUX | DIV_U71 | DIV_U71_INT, - .max_rate = 600000000, - .min_rate = 34000000, - .u.periph = { - .clk_num = 91, - .pll_low = &tegra_pll_p, -#ifdef CONFIG_TEGRA_PLLM_SCALED - .pll_high = &tegra_pll_c, -#else - .pll_high = &tegra_pll_m, -#endif - }, - .rate_change_nh = &msenc_rate_change_nh, -}; - -#ifdef CONFIG_TEGRA_DUAL_CBUS - -static struct raw_notifier_head c2bus_rate_change_nh; -static struct raw_notifier_head c3bus_rate_change_nh; - -static struct clk tegra_clk_c2bus = { - .name = "c2bus", - .parent = &tegra_pll_c2, - .ops = &tegra_clk_cbus_ops, - .max_rate = 800000000, - .mul = 1, - .div = 1, - .flags = PERIPH_ON_CBUS, - .shared_bus_backup = { - .input = &tegra_pll_p, - }, - .rate_change_nh = &c2bus_rate_change_nh, -}; -static struct clk tegra_clk_c3bus = { - .name = "c3bus", - .parent = &tegra_pll_c3, - .ops = &tegra_clk_cbus_ops, - .max_rate = 700000000, - .mul = 1, - .div = 1, - .flags = PERIPH_ON_CBUS, - .shared_bus_backup = { - .input = &tegra_pll_p, - }, - .rate_change_nh = &c3bus_rate_change_nh, -}; - -#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS -static DEFINE_MUTEX(cbus_mutex); -#define CROSS_CBUS_MUTEX (&cbus_mutex) -#else -#define CROSS_CBUS_MUTEX NULL -#endif - - -static struct clk_mux_sel mux_clk_cbus[] = { - { .input = &tegra_clk_c2bus, .value = 0}, - { .input = &tegra_clk_c3bus, .value = 1}, - { 0, 0}, -}; - -#define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .inputs = mux_clk_cbus, \ - .flags = MUX, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - }, \ - .cross_clk_mutex = CROSS_CBUS_MUTEX, \ - } - -#else - -static struct raw_notifier_head cbus_rate_change_nh; - -static struct clk tegra_clk_cbus = { - .name = "cbus", - .parent = &tegra_pll_c, - .ops = &tegra_clk_cbus_ops, - .max_rate = 700000000, - .mul = 1, - .div = 2, - .flags = PERIPH_ON_CBUS, - .shared_bus_backup = { - .input = &tegra_pll_p, - }, - .rate_change_nh = &cbus_rate_change_nh, -}; -#endif - -static void tegra14_camera_mclk_init(struct clk *c) -{ - c->state = OFF; - c->set = true; - - if (!strcmp(c->name, "mclk")) { - c->parent = tegra_get_clock_by_name("vi_sensor"); - c->max_rate = c->parent->max_rate; - } - - if (!strcmp(c->name, "mclk2")) { - c->parent = tegra_get_clock_by_name("vi_sensor2"); - c->max_rate = c->parent->max_rate; - } -} - -static int tegra14_camera_mclk_set_rate(struct clk *c, unsigned long rate) -{ - return clk_set_rate(c->parent, rate); -} - -static struct clk_ops tegra_camera_mclk_ops = { - .init = tegra14_camera_mclk_init, - .enable = tegra14_periph_clk_enable, - .disable = tegra14_periph_clk_disable, - .set_rate = tegra14_camera_mclk_set_rate, -}; - -static struct clk tegra_camera_mclk = { - .name = "mclk", - .ops = &tegra_camera_mclk_ops, - .u.periph = { - .clk_num = 92, - }, - .flags = PERIPH_NO_RESET, -}; - -static struct clk tegra_camera_mclk2 = { - .name = "mclk2", - .ops = &tegra_camera_mclk_ops, - .u.periph = { - .clk_num = 171, - }, - .flags = PERIPH_NO_RESET, -}; - -#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_periph_clk_ops, \ - .reg = _reg, \ - .inputs = _inputs, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - }, \ - } - -#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \ - _flags, _ops) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = _ops, \ - .reg = _reg, \ - .inputs = _inputs, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - }, \ - } - -#define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_periph_clk_ops, \ - .reg = _reg, \ - .inputs = _inputs, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - .src_mask = 0xE01F << 16, \ - .src_shift = 16, \ - }, \ - } - -#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - }, \ - } - -#define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - .usage_flag = _flag, \ - }, \ - } - -static DEFINE_MUTEX(sbus_cross_mutex); -#define SHARED_SCLK(_name, _dev, _con, _parent, _id, _div, _mode)\ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .ops = &tegra_clk_shared_bus_user_ops, \ - .parent = _parent, \ - .u.shared_bus_user = { \ - .client_id = _id, \ - .client_div = _div, \ - .mode = _mode, \ - }, \ - .cross_clk_mutex = &sbus_cross_mutex, \ -} - -struct clk tegra_list_clks[] = { - PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0), - PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), - PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), - PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), - PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("dmic0", "tegra30-i2s.0", NULL, 161, 0x64c, 24576000, mux_pllaout0_audio0_dmic_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("dmic1", "tegra30-i2s.0", NULL, 162, 0x650, 24576000, mux_pllaout0_audio1_dmic_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("sbc1", "tegra11-spi.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc2", "tegra11-spi.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc3", "tegra11-spi.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), - PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT), - PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 19200000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("mipibif", "tegra-mipi-bif", NULL, 173, 0x660, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("i2c1", "tegra14-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c2", "tegra14-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c3", "tegra14-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c4", "tegra14-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c5", "tegra14-i2c.4", "div-clk", 47, 0x128, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("i2c6", "tegra14-i2c.5", "div-clk", 166, 0x65c, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), - PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 800000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), - PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 800000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE), - PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 800000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), - PERIPH_CLK("vi_sensor", NULL, "vi_sensor", 164, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("vi_sensor2",NULL, "vi_sensor2", 165, 0x658, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 800000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT), - PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT), - PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops), - PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_plld2, MUX | MUX8 | DIV_U71), - PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_plld_plld2_clkm, MUX | MUX8), - PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_plld_plld2_clkm, MUX | MUX8), - PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0), - PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), - PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), - PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops), - PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops), - PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), - PERIPH_CLK("csi", "vi", "csi", 52, 0, 500000000, mux_pllp_out3, 0), - PERIPH_CLK("isp", "vi", "isp", 23, 0x648, 800000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), - PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), - PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71), - PERIPH_CLK("entropy", "entropy", NULL, 149, 0x628, 102000000, mux_pllp_clkm1, MUX | DIV_U71), - - PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 19200000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71), - PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), - PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT), - PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), - PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), - PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB), - - PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB), - - PERIPH_CLK("mc_bbc", "mc_bbc", NULL, 170, 0, 1066000000,mux_clk_emc, PERIPH_NO_RESET), - PERIPH_CLK("mc_capa", "mc_capa", NULL, 167, 0, 1066000000,mux_clk_emc, PERIPH_NO_RESET), - PERIPH_CLK("mc_cbpa", "mc_cbpa", NULL, 168, 0, 1066000000,mux_clk_emc, PERIPH_NO_RESET), - PERIPH_CLK("pll_p_bbc", "pll_p_bbc", NULL, 175, 0, 432000000,mux_pll_p, PERIPH_NO_RESET), - - PERIPH_CLK("isp_sapor", "isp_sapor", NULL, 163, 0x654, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("hdmi_audio","hdmi_audio", NULL, 176, 0x668, 26000000, mux_pllp_pllc_clkm, MUX | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("clk72mhz", "clk72mhz", NULL, 177, 0x66c, 102000000, mux_pllp3_pllc_clkm, MUX | DIV_U71 | PERIPH_NO_RESET), - PERIPH_CLK("vim2_clk", "vi", "vim2_clk", 171, 0, 26000000, mux_clk_m, PERIPH_NO_RESET), - PERIPH_CLK("vgpio", "vgpio", NULL, 172, 0, 26000000, mux_clk_m, PERIPH_NO_RESET), - - SHARED_SCLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_SCLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_SCLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_ahb, NULL, 0, 0), - SHARED_SCLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_ahb, NULL, 0, 0), - SHARED_SCLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_ahb, NULL, 0, 0), - SHARED_SCLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_ahb, NULL, 0, 0), - SHARED_SCLK("sdmmc3.sclk", "sdhci-tegra.2", "sclk", &tegra_clk_ahb, NULL, 0, 0), - SHARED_SCLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_ahb, NULL, 0, 0), - SHARED_SCLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_SCLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_SCLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), - SHARED_SCLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), - SHARED_SCLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_SCLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE), - - SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc", - &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)), - SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)), - SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING_BUT_ISO, 0), - SHARED_EMC_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)), - SHARED_EMC_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_2D)), - SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)), - SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("sdmmc3.emc", "sdhci-tegra.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)), - SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0), - SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0), - SHARED_EMC_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0), - SHARED_EMC_CLK("bbc_bw.emc", "tegra_bb.0", "emc_bw", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_BB)), - SHARED_EMC_CLK("bbc_fl.emc", "tegra_bb.0", "emc_fl", &tegra_clk_emc, NULL, 0, 0, 0), - -#ifdef CONFIG_TEGRA_DUAL_CBUS - DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0), - DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0), - DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0), - SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0), - SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE), - SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("battery.c2bus", "battery_edp", "gpu", &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING), - - DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0), - DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0), - SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0), - SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE), -#else - SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0), - SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0), - SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0), - SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0), - SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0), - SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), - SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE), - SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("battery.cbus", "battery_edp", "gpu", &tegra_clk_cbus, NULL, 0, SHARED_CEILING), - SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), -#endif - SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0), - SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0), - SHARED_CLK("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING), - SHARED_CLK("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0), - SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE), - - SHARED_CLK("nv.msenc", "tegra_msenc", "msenc", &tegra_clk_msenc, NULL, 0, 0), - SHARED_CLK("cap.msenc", "cap.msenc", NULL, &tegra_clk_msenc, NULL, 0, SHARED_CEILING), - SHARED_CLK("override.msenc", "override.msenc", NULL, &tegra_clk_msenc, NULL, 0, SHARED_OVERRIDE), -}; - -#define CLK_DUPLICATE(_name, _dev, _con) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - } - -/* Some clocks may be used by different drivers depending on the board - * configuration. List those here to register them twice in the clock lookup - * table under two names. - */ -struct clk_duplicate tegra_clk_duplicates[] = { - CLK_DUPLICATE("usbd", "utmip-pad", NULL), - CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), - CLK_DUPLICATE("usbd", "tegra-otg", NULL), - CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL), - CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"), - CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL), - CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"), - CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), - CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), - CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), - CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), - CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"), - CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"), - CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"), - CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"), - CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"), - CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"), - CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"), - CLK_DUPLICATE("cop", "tegra-avp", "cop"), - CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), - CLK_DUPLICATE("cop", "nvavp", "cop"), - CLK_DUPLICATE("bsev", "nvavp", "bsev"), - CLK_DUPLICATE("vde", "tegra-aes", "vde"), - CLK_DUPLICATE("bsea", "tegra-aes", "bsea"), - CLK_DUPLICATE("bsea", "nvavp", "bsea"), - CLK_DUPLICATE("clk_m", NULL, "apb_pclk"), - CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL), - CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL), - CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL), - CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL), - CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL), - CLK_DUPLICATE("cl_dvfs_ref", "tegra14-i2c.4", NULL), - CLK_DUPLICATE("cl_dvfs_soc", "tegra14-i2c.4", NULL), - CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL), - CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL), - CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL), - CLK_DUPLICATE("vcp", "nvavp", "vcp"), - CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"), - CLK_DUPLICATE("avp.emc", "nvavp", "emc"), - CLK_DUPLICATE("vde.cbus", "nvavp", "vde"), - CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"), - CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"), - CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"), - CLK_DUPLICATE("twd", "smp_twd", NULL), - CLK_DUPLICATE("tsec", "tegra_tsec", "tsec"), - CLK_DUPLICATE("csus", "touch_clk", "e1680_ts_clk_con"), - CLK_DUPLICATE("dmic0", "tegra-dmic.0", NULL), - CLK_DUPLICATE("dmic1", "tegra-dmic.1", NULL), - CLK_DUPLICATE("mclk2", NULL, "default_mclk"), -}; - -struct clk *tegra_ptr_clks[] = { - &tegra_clk_32k, - &tegra_osc, - &tegra_osc_div2, - &tegra_osc_div4, - &tegra_clk_m, - &tegra_pll_ref, - &tegra_pll_m, - &tegra_pll_m_out1, - &tegra_pll_c, - &tegra_pll_c_out1, - &tegra_pll_c2, - &tegra_pll_c3, - &tegra_pll_p, - &tegra_pll_p_out1, - &tegra_pll_p_out2, - &tegra_pll_p_out3, - &tegra_pll_p_out4, - &tegra_pll_a, - &tegra_pll_a_out0, - &tegra_pll_d, - &tegra_pll_d_out0, - &tegra_pll_d2, - &tegra_pll_d2_out0, - &tegra_pll_u, - &tegra_pll_u_480M, - &tegra_pll_u_60M, - &tegra_pll_u_48M, - &tegra_pll_u_12M, - &tegra_pll_x, - &tegra_pll_x_out0, - &tegra_dfll_cpu, - &tegra_clk_cclk_g, - &tegra_clk_cclk_lp, - &tegra_clk_sclk, - &tegra_clk_hclk, - &tegra_clk_pclk, - &tegra_clk_virtual_cpu_g, - &tegra_clk_virtual_cpu_lp, - &tegra_clk_cpu_cmplx, - &tegra_clk_blink, - &tegra_clk_cop, - &tegra_clk_sbus_cmplx, - &tegra_clk_ahb, - &tegra_clk_apb, - &tegra_clk_emc, - &tegra_clk_host1x, - &tegra_clk_msenc, - &tegra14_clk_twd, -#ifdef CONFIG_TEGRA_DUAL_CBUS - &tegra_clk_c2bus, - &tegra_clk_c3bus, -#else - &tegra_clk_cbus, -#endif -}; - -struct clk *tegra_ptr_camera_mclks[] = { - &tegra_camera_mclk, - &tegra_camera_mclk2, -}; - -/* Return true from this function if the target rate can be locked without - switching pll clients to back-up source */ -static bool tegra14_is_dyn_ramp( - struct clk *c, unsigned long rate, bool from_vco_min) -{ -#if PLLCX_USE_DYN_RAMP - /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */ - if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) { - struct clk_pll_freq_table cfg, old_cfg; - unsigned long input_rate = clk_get_rate(c->parent); - - u32 val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLCX, old_cfg, val); - old_cfg.p = pllcx_p[old_cfg.p]; - - if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) { - if ((cfg.n == old_cfg.n) || - PLLCX_IS_DYN(cfg.p, old_cfg.p)) - return true; - } - } -#endif - -#if PLLXC_USE_DYN_RAMP - /* PPLX, PLLC support dynamic ramp when changing NDIV only */ - if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) { - struct clk_pll_freq_table cfg, old_cfg; - unsigned long input_rate = clk_get_rate(c->parent); - - if (from_vco_min) { - old_cfg.m = PLL_FIXED_MDIV(c, input_rate); - old_cfg.p = 1; - } else { - u32 val = clk_readl(c->reg + PLL_BASE); - PLL_BASE_PARSE(PLLXC, old_cfg, val); - old_cfg.p = pllxc_p[old_cfg.p]; - } - - if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) { - if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p)) - return true; - } - } -#endif - return false; -} - -/* - * Backup pll is used as transitional CPU clock source while main pll is - * relocking; in addition all CPU rates below backup level are sourced from - * backup pll only. Target backup levels for each CPU mode are selected high - * enough to avoid voltage droop when CPU clock is switched between backup and - * main plls. Actual backup rates will be rounded to match backup source fixed - * frequency. Backup rates are also used as stay-on-backup thresholds, and must - * be kept the same in G and LP mode (will need to add a separate stay-on-backup - * parameter to allow different backup rates if necessary). - * - * Sbus threshold must be exact factor of pll_p rate. - */ -#define CPU_G_BACKUP_RATE_TARGET 200000000 -#define CPU_LP_BACKUP_RATE_TARGET 200000000 - -static void tegra14_pllp_init_dependencies(unsigned long pllp_rate) -{ - u32 div; - unsigned long backup_rate; - - switch (pllp_rate) { - case 216000000: - tegra_pll_p_out1.u.pll_div.default_rate = 28800000; - tegra_pll_p_out3.u.pll_div.default_rate = 72000000; - tegra_clk_sbus_cmplx.u.system.threshold = 108000000; - tegra_clk_host1x.u.periph.threshold = 108000000; - tegra_clk_msenc.u.periph.threshold = 108000000; - break; - case 408000000: - tegra_pll_p_out1.u.pll_div.default_rate = 9600000; - tegra_pll_p_out3.u.pll_div.default_rate = 68000000; - tegra_clk_sbus_cmplx.u.system.threshold = 204000000; - tegra_clk_host1x.u.periph.threshold = 204000000; - tegra_clk_msenc.u.periph.threshold = 204000000; - break; - case 204000000: - tegra_pll_p_out1.u.pll_div.default_rate = 4800000; - tegra_pll_p_out3.u.pll_div.default_rate = 68000000; - tegra_clk_sbus_cmplx.u.system.threshold = 204000000; - tegra_clk_host1x.u.periph.threshold = 204000000; - tegra_clk_msenc.u.periph.threshold = 204000000; - break; - default: - pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate); - BUG(); - } - pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate); - - div = pllp_rate / CPU_G_BACKUP_RATE_TARGET; - backup_rate = pllp_rate / div; - tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate; - - div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET; - backup_rate = pllp_rate / div; - tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate; -} - -static void tegra14_init_one_clock(struct clk *c) -{ - clk_init(c); - INIT_LIST_HEAD(&c->shared_bus_list); - if (!c->lookup.dev_id && !c->lookup.con_id) - c->lookup.con_id = c->name; - c->lookup.clk = c; - clkdev_add(&c->lookup); -} - -/* - * Direct access to DFLL for G CPU idle driver; called just before/after CPU is - * clock gated, provided no DFLL mode change is in progress. - */ -int tegra14_cpu_g_idle_rate_exchange(unsigned long *rate) -{ - int ret = 0; - struct clk *dfll = &tegra_dfll_cpu; - unsigned long old_rate, new_rate, flags; - - if (!tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) - return -EPERM; - - /* Clip min to oscillator rate */ - new_rate = max(*rate, tegra_osc.rate); - - clk_lock_save(dfll, &flags); - - old_rate = clk_get_rate_locked(dfll); - *rate = old_rate; - if (new_rate != old_rate) - ret = clk_set_rate_locked(dfll, new_rate); - - clk_unlock_restore(dfll, &flags); - return ret; -} - -/* - * Direct access to LP CPU backup PLL. - * - * - Called before/after EMC bus update to boost/restore LP CPU backup rate. - * Sequence counter mechanism is used to make sure that cpufreq governor setting - * that maybe changed concurrently with EMC rate update is not overwritten by - * restoration procedure. - * - * - Called before/after LP CPU is clock- or power-gated. In this case there is - * no way for cpufreq governor setting to change concurrently, and sequence - * counter can be ignored. - */ -static int cpu_lp_backup_boost_begin(unsigned long *rate, unsigned int *start) -{ - int ret; - unsigned long flags; - struct clk *backup = tegra_clk_virtual_cpu_lp.u.cpu.backup; - const seqcount_t *s = &tegra_clk_virtual_cpu_lp.u.cpu.backup_seqcnt; - unsigned long new_rate = min( - *rate, tegra_clk_virtual_cpu_lp.u.cpu.backup_rate); - - clk_lock_save(backup, &flags); - - *start = raw_seqcount_begin(s); - ret = read_seqcount_retry(s, *start) ? -EBUSY : 0; - if (!ret) { - *rate = clk_get_rate_locked(backup); - if (new_rate != (*rate)) - ret = clk_set_rate_locked(backup, new_rate); - } - clk_unlock_restore(backup, &flags); - return ret; -} - -static void cpu_lp_backup_boost_end(unsigned long rate, unsigned int start) -{ - unsigned long flags; - struct clk *backup = tegra_clk_virtual_cpu_lp.u.cpu.backup; - const seqcount_t *s = &tegra_clk_virtual_cpu_lp.u.cpu.backup_seqcnt; - - clk_lock_save(backup, &flags); - - if (!read_seqcount_retry(s, start)) { - if (rate != clk_get_rate_locked(backup)) - clk_set_rate_locked(backup, rate); - } - clk_unlock_restore(backup, &flags); -} - -int tegra14_cpu_lp_idle_rate_exchange(unsigned long *rate) -{ - unsigned int seqcnt; /* ignored */ - return cpu_lp_backup_boost_begin(rate, &seqcnt); -} - -void tegra_edp_throttle_cpu_now(u8 factor) -{ - /* empty definition for tegra14 */ - return; -} - -bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p) -{ - /* - * Most of the Tegra14 multimedia and peripheral muxes include pll_c2 - * and pll_c3 as possible inputs. However, per clock policy these plls - * are allowed to be used only by handful devices aggregated on cbus. - * For all others, instead of enforcing policy at run-time in this - * function, we simply stripped out pll_c2 and pll_c3 options from the - * respective muxes statically. - */ - - /* - * In configuration with dual cbus pll_c can be used as a scaled clock - * source for EMC only when pll_m is fixed, or as a general fixed rate - * clock source for EMC and other peripherals if pll_m is scaled. In - * configuration with single cbus pll_c can be used as a scaled cbus - * clock source only. - */ - if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) { -#ifdef CONFIG_TEGRA_DUAL_CBUS -#ifndef CONFIG_TEGRA_PLLM_SCALED - return c->flags & PERIPH_EMC_ENB; -#endif -#else - return c->flags & PERIPH_ON_CBUS; -#endif - } - - /* - * In any configuration pll_m must not be used as a clock source for - * cbus modules. If pll_m is scaled it can be used as EMC source only. - * Otherwise fixed rate pll_m can be used as clock source for EMC and - * other peripherals. - */ - if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) { - if (c->flags & PERIPH_ON_CBUS) - return false; -#ifdef CONFIG_TEGRA_PLLM_SCALED - return c->flags & PERIPH_EMC_ENB; -#endif - } - return true; -} - -/* Internal LA may request some clocks to be enabled on init via TRANSACTION - SCRATCH register settings */ -void __init tegra14x_clk_init_la(void) -{ - struct clk *c; - u32 reg = readl(misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0); - - if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE)) - return; - - c = tegra_get_clock_by_name("la"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - - if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) { - c = tegra_get_clock_by_name("dds"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - } - if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) { - c = tegra_get_clock_by_name("dp2"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - - c = tegra_get_clock_by_name("hdmi"); - if (WARN(!c, "%s: could not find la clk\n", __func__)) - return; - clk_enable(c); - } -} - -#ifdef CONFIG_CPU_FREQ - -/* - * Frequency table index must be sequential starting at 0 and frequencies - * must be ascending. - */ -#define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */ -#define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1) - -static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE]; -static struct tegra_cpufreq_table_data freq_table_data; - -struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) -{ - int i, j; - bool g_vmin_done = false; - unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq; - struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g"); - struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp"); - - /* Initialize once */ - if (freq_table_data.freq_table) - return &freq_table_data; - - /* Clean table */ - for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) { - freq_table[i].index = i; - freq_table[i].frequency = CPUFREQ_TABLE_END; - } - - lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000; - if (!lp_backup_freq) { - WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n", - __func__); - return NULL; - } - if (!cpu_clk_lp->dvfs) { - WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n", - __func__); - return NULL; - } - if (!cpu_clk_g->dvfs) { - WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n", - __func__); - return NULL; - } - g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000; - if (g_vmin_freq < lp_backup_freq) { - WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate" - " exceeds G CPU rate at Vmin\n", __func__); - return NULL; - } else if (g_vmin_freq == lp_backup_freq) { - g_vmin_done = true; - } - - /* Start with backup frequencies */ - i = 0; - freq = lp_backup_freq; - freq_table[i++].frequency = freq/4; - freq_table[i++].frequency = freq/2; - freq_table[i++].frequency = freq; - - /* Throttle low index at backup level*/ - freq_table_data.throttle_lowest_index = i - 1; - - /* - * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU - * dvfs rate at minimum voltage is not missed (if it happens to be below - * LP maximum rate) - */ - max_freq = cpu_clk_lp->max_rate / 1000; - for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) { - freq = cpu_clk_lp->dvfs->freqs[j] / 1000; - if (freq <= lp_backup_freq) - continue; - - if (!g_vmin_done && (freq >= g_vmin_freq)) { - g_vmin_done = true; - if (freq > g_vmin_freq) - freq_table[i++].frequency = g_vmin_freq; - } - freq_table[i++].frequency = freq; - - if (freq == max_freq) - break; - } - - /* Set G CPU min rate at least one table step below LP maximum */ - cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000; - - /* Suspend index at max LP CPU */ - freq_table_data.suspend_index = i - 1; - - /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs - ladder rate at minimum voltage */ - if (freq < g_vmin_freq) { - int n = (g_vmin_freq - freq) / CPU_FREQ_STEP; - for (j = 0; j <= n; j++) { - freq = g_vmin_freq - CPU_FREQ_STEP * (n - j); - freq_table[i++].frequency = freq; - } - } - - /* Now, step along the rest of G CPU dvfs ladder */ - g_start_freq = freq; - max_freq = cpu_clk_g->max_rate / 1000; - for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) { - freq = cpu_clk_g->dvfs->freqs[j] / 1000; - if (freq > g_start_freq) - freq_table[i++].frequency = freq; - if (freq == max_freq) - break; - } - - /* Throttle high index one step below maximum */ - BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE); - freq_table_data.throttle_highest_index = i - 2; - freq_table_data.freq_table = freq_table; - return &freq_table_data; -} - -unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate) -{ - static unsigned long emc_max_rate; - - if (emc_max_rate == 0) - emc_max_rate = clk_round_rate( - tegra_get_clock_by_name("emc"), ULONG_MAX); - - /* Vote on memory bus frequency based on cpu frequency; - cpu rate is in kHz, emc rate is in Hz */ - if (cpu_rate >= 1300000) - return emc_max_rate; /* cpu >= 1.3 GHz, emc max */ - else if (cpu_rate >= 1000000) - return 650000000; /* cpu >= 1.0 GHz, emc 650 MHz */ - else if (cpu_rate >= 725000) - return 400000000; /* cpu >= 725 MHz, emc 400 MHz */ - else if (cpu_rate >= 550000) - return 200000000; /* cpu >= 550 MHz, emc 200 MHz */ - else if (cpu_rate >= 400000) - return 100000000; /* cpu >= 400 MHz, emc 100 MHz */ - else if (cpu_rate >= 275000) - return 50000000; /* cpu >= 275 MHz, emc 50 MHz */ - else - return 0; /* emc min */ -} - -int tegra_update_mselect_rate(unsigned long cpu_rate) -{ - static struct clk *mselect; - - unsigned long mselect_rate; - - if (!mselect) { - mselect = tegra_get_clock_by_name("mselect"); - if (!mselect) - return -ENODEV; - } - - /* Vote on mselect frequency based on cpu frequency: - keep mselect at half of cpu rate up to 102 MHz; - cpu rate is in kHz, mselect rate is in Hz */ - mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000; - mselect_rate = min(mselect_rate, 102000000UL); - - if (mselect_rate != clk_get_rate(mselect)) - return clk_set_rate(mselect, mselect_rate); - - return 0; -} -#endif - -#ifdef CONFIG_PM_SLEEP -static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + - PERIPH_CLK_SOURCE_NUM + 26]; - -static int tegra14_clk_suspend(void) -{ - unsigned long off; - u32 *ctx = clk_rst_suspend; - - *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; - *ctx++ = clk_readl(CPU_SOFTRST_CTRL); - *ctx++ = clk_readl(CPU_SOFTRST_CTRL1); - *ctx++ = clk_readl(CPU_SOFTRST_CTRL2); - - *ctx++ = clk_readl(tegra_pll_p_out1.reg); - *ctx++ = clk_readl(tegra_pll_p_out3.reg); - - *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); - *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); - *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); - *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); - *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE); - *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); - - *ctx++ = clk_readl(tegra_pll_m_out1.reg); - *ctx++ = clk_readl(tegra_pll_a_out0.reg); - *ctx++ = clk_readl(tegra_pll_c_out1.reg); - - *ctx++ = clk_readl(tegra_clk_cclk_lp.reg); - *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); - - *ctx++ = clk_readl(tegra_clk_sclk.reg); - *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); - *ctx++ = clk_readl(tegra_clk_pclk.reg); - - for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; - off += 4) { - if (off == PERIPH_CLK_SOURCE_EMC) - continue; - *ctx++ = clk_readl(off); - } - for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; - off += 4) { - *ctx++ = clk_readl(off); - } - for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_I2S4; off += 4) - *ctx++ = clk_readl(off); - for (off = PERIPH_CLK_SOURCE_CILAB; - off <= PERIPH_CLK_SOURCE_CLK72MHZ; off += 4) - *ctx++ = clk_readl(off); - - *ctx++ = clk_readl(RST_DEVICES_L); - *ctx++ = clk_readl(RST_DEVICES_H); - *ctx++ = clk_readl(RST_DEVICES_U); - *ctx++ = clk_readl(RST_DEVICES_V); - *ctx++ = clk_readl(RST_DEVICES_W); - *ctx++ = clk_readl(RST_DEVICES_X); - - *ctx++ = clk_readl(CLK_OUT_ENB_L); - *ctx++ = clk_readl(CLK_OUT_ENB_H); - *ctx++ = clk_readl(CLK_OUT_ENB_U); - *ctx++ = clk_readl(CLK_OUT_ENB_V); - *ctx++ = clk_readl(CLK_OUT_ENB_W); - *ctx++ = clk_readl(CLK_OUT_ENB_X); - - *ctx++ = clk_readl(tegra_clk_cclk_g.reg); - *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); - - *ctx++ = clk_readl(SPARE_REG); - *ctx++ = clk_readl(MISC_CLK_ENB); - *ctx++ = clk_readl(CLK_MASK_ARM); - - tegra14_clk_emc_suspend(&tegra_clk_emc, ctx++); - - return 0; -} - -static void tegra14_clk_resume(void) -{ - unsigned long off; - const u32 *ctx = clk_rst_suspend; - u32 val; - u32 plla_base; - u32 plld_base; - u32 plld2_base; - u32 pll_p_out12, pll_p_out34; - u32 pll_a_out0, pll_m_out1, pll_c_out1; - struct clk *p; - - /* FIXME: OSC_CTRL already restored by warm boot code? */ - val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; - val |= *ctx++; - clk_writel(val, OSC_CTRL); - clk_writel(*ctx++, CPU_SOFTRST_CTRL); - clk_writel(*ctx++, CPU_SOFTRST_CTRL1); - clk_writel(*ctx++, CPU_SOFTRST_CTRL2); - - /* FIXME: DFLL? */ - /* Since we are going to reset devices and switch clock sources in this - * function, plls and secondary dividers is required to be enabled. The - * actual value will be restored back later. Note that boot plls: pllm, - * pllp, and pllu are already configured and enabled - */ - val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - val |= val << 16; - pll_p_out12 = *ctx++; - clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg); - pll_p_out34 = *ctx++; - clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg); - - tegra14_pllcx_clk_resume_enable(&tegra_pll_c2); - tegra14_pllcx_clk_resume_enable(&tegra_pll_c3); - tegra14_pllxc_clk_resume_enable(&tegra_pll_c); - tegra14_pllxc_clk_resume_enable(&tegra_pll_x); - - plla_base = *ctx++; - clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); - clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE); - - plld_base = *ctx++; - clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); - clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE); - - plld2_base = *ctx++; - clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); - clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE); - - udelay(1000); - - val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - pll_m_out1 = *ctx++; - clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg); - pll_a_out0 = *ctx++; - clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg); - pll_c_out1 = *ctx++; - clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg); - - val = *ctx++; - tegra14_super_clk_resume(&tegra_clk_cclk_lp, - tegra_clk_virtual_cpu_lp.u.cpu.backup, val); - clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); - - clk_writel(*ctx++, tegra_clk_sclk.reg); - clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); - clk_writel(*ctx++, tegra_clk_pclk.reg); - - /* enable all clocks before configuring clock sources */ - clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L); - clk_writel(0xffddfff7ul, CLK_OUT_ENB_H); - clk_writel(0xfbfffbfeul, CLK_OUT_ENB_U); - clk_writel(0xfffffffful, CLK_OUT_ENB_V); - clk_writel(0xff7ffffful, CLK_OUT_ENB_W); - wmb(); - - for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; - off += 4) { - if (off == PERIPH_CLK_SOURCE_EMC) - continue; - clk_writel(*ctx++, off); - } - for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; - off += 4) { - clk_writel(*ctx++, off); - } - for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_I2S4; off += 4) - clk_writel(*ctx++, off); - for (off = PERIPH_CLK_SOURCE_CILAB; - off <= PERIPH_CLK_SOURCE_CLK72MHZ; off += 4) - clk_writel(*ctx++, off); - - udelay(RESET_PROPAGATION_DELAY); - - clk_writel(*ctx++, RST_DEVICES_L); - clk_writel(*ctx++, RST_DEVICES_H); - clk_writel(*ctx++, RST_DEVICES_U); - clk_writel(*ctx++, RST_DEVICES_V); - clk_writel(*ctx++, RST_DEVICES_W); - clk_writel(*ctx++, RST_DEVICES_X); - wmb(); - - clk_writel(*ctx++, CLK_OUT_ENB_L); - clk_writel(*ctx++, CLK_OUT_ENB_H); - clk_writel(*ctx++, CLK_OUT_ENB_U); - - /* For LP0 resume, clk to lpcpu is required to be on */ - /* FIXME: should be saved as on? */ - val = *ctx++; - val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN; - clk_writel(val, CLK_OUT_ENB_V); - - clk_writel(*ctx++, CLK_OUT_ENB_W); - clk_writel(*ctx++, CLK_OUT_ENB_X); - wmb(); - - /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */ - tegra14_dfll_clk_resume(&tegra_dfll_cpu); - - /* CPU G clock restored after DFLL and PLLs */ - clk_writel(*ctx++, tegra_clk_cclk_g.reg); - clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); - - clk_writel(*ctx++, SPARE_REG); - clk_writel(*ctx++, MISC_CLK_ENB); - clk_writel(*ctx++, CLK_MASK_ARM); - - /* Restore back the actual pll and secondary divider values */ - clk_writel(pll_p_out12, tegra_pll_p_out1.reg); - clk_writel(pll_p_out34, tegra_pll_p_out3.reg); - - p = &tegra_pll_c2; - if (p->state == OFF) - tegra14_pllcx_clk_disable(p); - p = &tegra_pll_c3; - if (p->state == OFF) - tegra14_pllcx_clk_disable(p); - p = &tegra_pll_c; - if (p->state == OFF) - tegra14_pllxc_clk_disable(p); - p = &tegra_pll_x; - if (p->state == OFF) - tegra14_pllxc_clk_disable(p); - - clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE); - clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE); - clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE); - - clk_writel(pll_m_out1, tegra_pll_m_out1.reg); - clk_writel(pll_a_out0, tegra_pll_a_out0.reg); - clk_writel(pll_c_out1, tegra_pll_c_out1.reg); - - /* Since EMC clock is not restored, and may not preserve parent across - suspend, update current state, and mark EMC DFS as out of sync */ - p = tegra_clk_emc.parent; - tegra14_periph_clk_init(&tegra_clk_emc); - - /* Turn Off pll_m if it was OFF before suspend, and emc was not switched - to pll_m across suspend; re-init pll_m to sync s/w and h/w states */ - if ((tegra_pll_m.state == OFF) && - (&tegra_pll_m != tegra_clk_emc.parent)) - tegra14_pllm_clk_disable(&tegra_pll_m); - tegra14_pllm_clk_init(&tegra_pll_m); - - if (p != tegra_clk_emc.parent) { - pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)", - p->name, p->refcnt, tegra_clk_emc.parent->name, - tegra_clk_emc.parent->refcnt); - - /* emc switched to the new parent by low level code, but ref - count and s/w state need to be updated */ - clk_disable(p); - clk_enable(tegra_clk_emc.parent); - } - tegra_emc_timing_invalidate(); - - tegra14_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */ - tegra14_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */ - - tegra14_clk_emc_resume(&tegra_clk_emc, ctx++); -} - -static struct syscore_ops tegra_clk_syscore_ops = { - .suspend = tegra14_clk_suspend, - .resume = tegra14_clk_resume, -}; -#endif - -void __init tegra14x_init_clocks(void) -{ - int i; - struct clk *c; - - for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) - tegra14_init_one_clock(tegra_ptr_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) - tegra14_init_one_clock(&tegra_list_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_ptr_camera_mclks); i++) - tegra14_init_one_clock(tegra_ptr_camera_mclks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { - c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); - if (!c) { - pr_err("%s: Unknown duplicate clock %s\n", __func__, - tegra_clk_duplicates[i].name); - continue; - } - - tegra_clk_duplicates[i].lookup.clk = c; - clkdev_add(&tegra_clk_duplicates[i].lookup); - } - - for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) - tegra14_init_one_clock(&tegra_sync_source_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) - tegra14_init_one_clock(&tegra_clk_audio_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) - tegra14_init_one_clock(&tegra_clk_audio_2x_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_dmic_list); i++) - tegra14_init_one_clock(&tegra_clk_audio_dmic_list[i]); - - init_clk_out_mux(); - for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) - tegra14_init_one_clock(&tegra_clk_out_list[i]); - - /* Initialize to default */ - tegra_init_cpu_edp_limits(0); - -#ifdef CONFIG_PM_SLEEP - register_syscore_ops(&tegra_clk_syscore_ops); -#endif -} diff --git a/arch/arm/mach-tegra/tegra14_dvfs.c b/arch/arm/mach-tegra/tegra14_dvfs.c deleted file mode 100644 index dfe3ed448945..000000000000 --- a/arch/arm/mach-tegra/tegra14_dvfs.c +++ /dev/null @@ -1,978 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14_dvfs.c - * - * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/string.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/kobject.h> -#include <linux/err.h> - -#include "clock.h" -#include "dvfs.h" -#include "board.h" -#include "tegra_cl_dvfs.h" -#include "tegra_core_sysfs_limits.h" - -static bool tegra_dvfs_cpu_disabled; -static bool tegra_dvfs_core_disabled; - -#define KHZ 1000 -#define MHZ 1000000 - -/* FIXME: need tegra14 step */ -#define VDD_SAFE_STEP 100 - -static int vdd_core_vmin_trips_table[MAX_THERMAL_LIMITS] = { 20, }; -static int vdd_core_therm_floors_table[MAX_THERMAL_LIMITS] = { 900, }; - -static int vdd_cpu_vmax_trips_table[MAX_THERMAL_LIMITS] = { 62, 72, }; -static int vdd_cpu_therm_caps_table[MAX_THERMAL_LIMITS] = { 1180, 1150, }; - -static struct tegra_cooling_device cpu_vmax_cdev = { - .cdev_type = "cpu_hot", -}; - -static struct tegra_cooling_device cpu_vmin_cdev = { - .cdev_type = "cpu_cold", -}; - -static struct tegra_cooling_device core_vmin_cdev = { - .cdev_type = "core_cold", -}; - -static struct dvfs_rail tegra14_dvfs_rail_vdd_cpu = { - .reg_id = "vdd_cpu", - .max_millivolts = 1400, - .min_millivolts = 800, - .step = VDD_SAFE_STEP, - .jmp_to_zero = true, - .vmin_cdev = &cpu_vmin_cdev, - .vmax_cdev = &cpu_vmax_cdev, -}; - -static struct dvfs_rail tegra14_dvfs_rail_vdd_core = { - .reg_id = "vdd_core", - .max_millivolts = 1400, - .min_millivolts = 800, - .step = VDD_SAFE_STEP, - .vmin_cdev = &core_vmin_cdev, -}; - -static struct dvfs_rail *tegra14_dvfs_rails[] = { - &tegra14_dvfs_rail_vdd_cpu, - &tegra14_dvfs_rail_vdd_core, -}; - -/* default cvb alignment on Tegra14 - 10mV */ -int __attribute__((weak)) tegra_get_cvb_alignment_uV(void) -{ - return 10000; -} - -int __attribute__((weak)) tegra_get_core_cvb_alignment_uV(void) -{ - return 6250; -} - -/* CPU DVFS tables */ -static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { - { - .speedo_id = 0, - .process_id = -1, - .dfll_tune_data = { - .tune0 = 0x0041061F, - .tune0_high_mv = 0x0041001F, - .tune1 = 0x00000007, - .droop_rate_min = 1000000, - .tune_high_min_millivolts = 900, - .tune_high_margin_mv = 40, - .min_millivolts = 800, - }, - .max_mv = 1230, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 408000, { 2167974, -118652, 2434}, { 812396, 0, 0} }, - { 510000, { 2210727, -119982, 2434}, { 824163, 0, 0} }, - { 612000, { 2255116, -121322, 2434}, { 837498, 0, 0} }, - { 714000, { 2301137, -122662, 2434}, { 852671, 0, 0} }, - { 816000, { 2348792, -124002, 2434}, { 869680, 0, 0} }, - { 918000, { 2398075, -125332, 2434}, { 888794, 0, 0} }, - {1020000, { 2448994, -126672, 2434}, { 909476, 0, 0} }, - {1122000, { 2501546, -128012, 2434}, { 931995, 0, 0} }, - {1224000, { 2555727, -129342, 2434}, { 956619, 0, 0} }, - {1326000, { 2611544, -130682, 2434}, { 982812, 0, 0} }, - {1428000, { 2668994, -132022, 2434}, { 1010841, 0, 0} }, - {1530000, { 2728076, -133362, 2434}, { 1040706, 0, 0} }, - {1632000, { 2788787, -134692, 2434}, { 1072677, 0, 0} }, - {1734000, { 2851134, -136032, 2434}, { 1106216, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20 }, - .therm_floors_table = { 900 }, - }, - { - .speedo_id = 1, - .process_id = 1, - .dfll_tune_data = { - .tune0 = 0x0041061F, - .tune0_high_mv = 0x0041001F, - .tune1 = 0x00000007, - .droop_rate_min = 1000000, - .tune_high_min_millivolts = 900, - .tune_high_margin_mv = 40, - .min_millivolts = 800, - }, - .max_mv = 1230, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ - { 408000, { 2167974, -118652, 2434}, { 812396, 0, 0} }, - { 510000, { 2210727, -119982, 2434}, { 824163, 0, 0} }, - { 612000, { 2255116, -121322, 2434}, { 837498, 0, 0} }, - { 714000, { 2301137, -122662, 2434}, { 852671, 0, 0} }, - { 816000, { 2348792, -124002, 2434}, { 869680, 0, 0} }, - { 918000, { 2398075, -125332, 2434}, { 888794, 0, 0} }, - {1020000, { 2448994, -126672, 2434}, { 909476, 0, 0} }, - {1122000, { 2501546, -128012, 2434}, { 931995, 0, 0} }, - {1224000, { 2555727, -129342, 2434}, { 956619, 0, 0} }, - {1326000, { 2611544, -130682, 2434}, { 982812, 0, 0} }, - {1428000, { 2668994, -132022, 2434}, { 1010841, 0, 0} }, - {1530000, { 2728076, -133362, 2434}, { 1040706, 0, 0} }, - {1632000, { 2788787, -134692, 2434}, { 1072677, 0, 0} }, - {1734000, { 2851134, -136032, 2434}, { 1106216, 0, 0} }, - {1836000, { 2915114, -137372, 2434}, { 1141591, 0, 0} }, - {1938000, { 2980727, -138712, 2434}, { 1178803, 0, 0} }, - {2014500, { 3030673, -139702, 2434}, { 1207951, 0, 0} }, - {2116500, { 3099135, -141042, 2434}, { 1248368, 0, 0} }, - { 0, { 0, 0, 0}, { 0, 0, 0} }, - }, - .vmin_trips_table = { 20 }, - .therm_floors_table = { 900 }, - }, -}; - -static int cpu_millivolts[MAX_DVFS_FREQS]; -static int cpu_dfll_millivolts[MAX_DVFS_FREQS]; - -static struct dvfs cpu_dvfs = { - .clk_name = "cpu_g", - .millivolts = cpu_millivolts, - .dfll_millivolts = cpu_dfll_millivolts, - .auto_dvfs = true, - .dvfs_rail = &tegra14_dvfs_rail_vdd_cpu, -}; - -/* Core DVFS tables */ -static const int core_millivolts[MAX_DVFS_FREQS] = { - 800, 850, 900, 950, 1000, 1050, 1100, 1150, 1200, 1230}; - -#define CORE_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \ - { \ - .clk_name = _clk_name, \ - .speedo_id = _speedo_id, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .millivolts = core_millivolts, \ - .auto_dvfs = _auto, \ - .dvfs_rail = &tegra14_dvfs_rail_vdd_core, \ - } - -#define OVRRD_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \ - { \ - .clk_name = _clk_name, \ - .speedo_id = _speedo_id, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .millivolts = core_millivolts, \ - .auto_dvfs = _auto, \ - .can_override = true, \ - .dvfs_rail = &tegra14_dvfs_rail_vdd_core, \ - } - - -static struct dvfs core_dvfs_table[] = { - /* Core voltages (mV): 800, 850, 900, 950, 1000, 1050, 1100, 1150, 1200, 1230 */ - CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 249600, 364800, 460800, 556800, 633600, 691200, 729600, 768000, 768000, 768000), - CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 307200, 393600, 489600, 556800, 652800, 729600, 768000, 768000, 768000, 768000), - CORE_DVFS("cpu_lp", 1, 1, 1, KHZ, 307200, 393600, 489600, 556800, 652800, 729600, 768000, 806400, 806400, 806400), - -#ifndef CONFIG_TEGRA_DUAL_CBUS - CORE_DVFS("3d", 0, 0, 1, KHZ, 153600, 230400, 307200, 384000, 499200, 556800, 600000, 600000, 600000, 600000), - CORE_DVFS("2d", 0, 0, 1, KHZ, 153600, 230400, 307200, 384000, 499200, 556800, 600000, 600000, 600000, 600000), - CORE_DVFS("epp", 0, 0, 1, KHZ, 153600, 230400, 307200, 384000, 499200, 556800, 600000, 600000, 600000, 600000), - CORE_DVFS("3d", 0, 1, 1, KHZ, 192000, 268800, 345600, 384000, 499200, 556800, 600000, 600000, 600000, 600000), - CORE_DVFS("2d", 0, 1, 1, KHZ, 192000, 268800, 345600, 384000, 499200, 556800, 600000, 600000, 600000, 600000), - CORE_DVFS("epp", 0, 1, 1, KHZ, 192000, 268800, 345600, 384000, 499200, 556800, 600000, 600000, 600000, 600000), - CORE_DVFS("3d", 1, 1, 1, KHZ, 192000, 268800, 345600, 384000, 499200, 556800, 595200, 672000, 710400, 748800), - CORE_DVFS("2d", 1, 1, 1, KHZ, 192000, 268800, 345600, 384000, 499200, 556800, 595200, 672000, 710400, 748800), - CORE_DVFS("epp", 1, 1, 1, KHZ, 192000, 268800, 345600, 384000, 499200, 556800, 595200, 672000, 710400, 748800), -#endif - CORE_DVFS("se", 0, 0, 1, KHZ, 115200, 192000, 249600, 326400, 364800, 441600, 480000, 518400, 518400, 518400), - CORE_DVFS("vde", 0, 0, 1, KHZ, 115200, 192000, 249600, 326400, 364800, 441600, 480000, 518400, 518400, 518400), - CORE_DVFS("se", 0, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 518400, 518400, 518400), - CORE_DVFS("vde", 0, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 518400, 518400, 518400), - CORE_DVFS("se", 1, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 537600, 537600, 537600), - CORE_DVFS("vde", 1, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 537600, 537600, 537600), - - CORE_DVFS("msenc", 0, 0, 1, KHZ, 68000, 102000, 136000, 204000, 204000, 204000, 384000, 408000, 408000, 408000), - CORE_DVFS("msenc", 0, 1, 1, KHZ, 81600, 136000, 204000, 204000, 204000, 204000, 408000, 408000, 408000, 408000), - CORE_DVFS("msenc", 1, 1, 1, KHZ, 81600, 136000, 204000, 204000, 204000, 204000, 408000, 408000, 408000, 408000), - - CORE_DVFS("tsec", 0, 0, 1, KHZ, 136000, 204000, 204000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - CORE_DVFS("tsec", 0, 1, 1, KHZ, 136000, 204000, 384000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - CORE_DVFS("tsec", 1, 1, 1, KHZ, 136000, 204000, 384000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - - CORE_DVFS("host1x", 0, 0, 1, KHZ, 102000, 102000, 204000, 204000, 204000, 204000, 384000, 408000, 408000, 408000), - CORE_DVFS("host1x", 0, 1, 1, KHZ, 136000, 136000, 204000, 204000, 204000, 384000, 384000, 408000, 408000, 408000), - CORE_DVFS("host1x", 1, 1, 1, KHZ, 136000, 136000, 204000, 204000, 204000, 384000, 384000, 408000, 408000, 408000), - - CORE_DVFS("vi", -1, -1, 1, KHZ, 136000, 204000, 204000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - CORE_DVFS("isp", -1, -1, 1, KHZ, 136000, 204000, 204000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), - - CORE_DVFS("sbus", 0, 0, 1, KHZ, 102000, 102000, 102000, 102000, 204000, 384000, 384000, 408000, 408000, 408000), - CORE_DVFS("sbus", 0, 1, 1, KHZ, 136000, 136000, 204000, 204000, 204000, 384000, 384000, 408000, 408000, 408000), - CORE_DVFS("sbus", 1, 1, 1, KHZ, 136000, 136000, 204000, 204000, 204000, 384000, 384000, 408000, 408000, 408000), - - CORE_DVFS("emc", -1, -1, 1, KHZ, 1, 1, 1, 1, 1, 1,1066000,1066000,1066000,1066000), - -#ifdef CONFIG_TEGRA_DUAL_CBUS - CORE_DVFS("c3bus", 0, 0, 1, KHZ, 115200, 192000, 249600, 326400, 364800, 441600, 480000, 518400, 518400, 518400), - CORE_DVFS("c3bus", 0, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 518400, 518400, 518400), - CORE_DVFS("c3bus", 1, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 537600, 537600, 537600), -#else - CORE_DVFS("cbus", 0, 0, 1, KHZ, 115200, 192000, 249600, 326400, 364800, 441600, 480000, 518400, 518400, 518400), - CORE_DVFS("cbus", 0, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 518400, 518400, 518400), - CORE_DVFS("cbus", 1, 1, 1, KHZ, 153600, 211200, 288000, 345600, 403200, 460800, 499200, 537600, 537600, 537600), -#endif - /* Core voltages (mV): 800, 850, 900, 950, 1000, 1050, 1100, 1150, 1200, 1230 */ - /* Clock limits for I/O peripherals */ - CORE_DVFS("cilab", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 102000, 114700, 136000, 136000, 136000, 136000), - CORE_DVFS("cilcd", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 102000, 114700, 136000, 136000, 136000, 136000), - CORE_DVFS("cile", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 102000, 114700, 136000, 136000, 136000, 136000), - CORE_DVFS("dsia", -1, -1, 1, KHZ, 252000, 431000, 431000, 431000, 431000, 431000, 431000, 431000, 431000, 431000), - CORE_DVFS("dsib", -1, -1, 1, KHZ, 252000, 431000, 431000, 431000, 431000, 431000, 431000, 431000, 431000, 431000), - CORE_DVFS("hdmi", -1, -1, 1, KHZ, 111300, 111300, 111300, 135600, 173200, 212300, 270000, 270000, 270000, 270000), - - CORE_DVFS("pll_m", 0, 0, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c", 0, 0, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c2", 0, 0, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c3", 0, 0, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_m", 0, 1, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c", 0, 1, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c2", 0, 1, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c3", 0, 1, 1, KHZ, 408000, 667000, 800000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_m", 1, 1, 1, KHZ, 533000, 667000, 933000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c", 1, 1, 1, KHZ, 533000, 667000, 933000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c2", 1, 1, 1, KHZ, 533000, 667000, 933000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - CORE_DVFS("pll_c3", 1, 1, 1, KHZ, 533000, 667000, 933000,1066000,1066000,1066000,1066000,1066000,1066000,1066000), - - /* Core voltages (mV):» » 800, 850, 900, 950, 1000, 1050, 1100, 1150, 1200, 1230 */ - /* Clock limits for IO Peripherals */ - CORE_DVFS("sbc1", -1, -1, 1, KHZ, 33000, 33000, 33000, 30000, 30000, 50000, 50000, 50000, 50000, 50000), - CORE_DVFS("sbc2", -1, -1, 1, KHZ, 33000, 33000, 33000, 30000, 30000, 50000, 50000, 50000, 50000, 50000), - CORE_DVFS("sbc3", -1, -1, 1, KHZ, 33000, 33000, 33000, 30000, 30000, 50000, 50000, 50000, 50000, 50000), - - OVRRD_DVFS("sdmmc1", -1, -1, 1, KHZ, 51000, 51000, 51000, 51000, 51000, 51000, 136000, 136000, 136000, 204000), - OVRRD_DVFS("sdmmc3", -1, -1, 1, KHZ, 51000, 51000, 51000, 51000, 51000, 51000, 136000, 136000, 136000, 204000), - OVRRD_DVFS("sdmmc4", -1, -1, 1, KHZ, 51000, 51000, 51000, 51000, 51000, 51000, 136000, 136000, 136000, 192000), - - /* - * The clock rate for the display controllers that determines the - * necessary core voltage depends on a divider that is internal - * to the display block. Disable auto-dvfs on the display clocks, - * and let the display driver call tegra_dvfs_set_rate manually - */ - CORE_DVFS("disp1", -1, -1, 0, KHZ, 74250, 165000, 165000, 165000, 165000, 165000, 165000, 165000, 165000, 165000), - CORE_DVFS("disp2", -1, -1, 0, KHZ, 74250, 165000, 165000, 165000, 165000, 165000, 165000, 165000, 165000, 165000), -}; - -/* C2BUS dvfs tables */ -static struct core_cvb_dvfs c2bus_cvb_dvfs_table[] = { - { - .speedo_id = 0, - .process_id = 0, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll pll: c0, c1, c2 */ - { 153600, { }, { 800000, 0, 0}, }, - { 230400, { }, { 850000, 0, 0}, }, - { 307200, { }, { 900000, 0, 0}, }, - { 384000, { }, { 950000, 0, 0}, }, - { 499200, { }, { 1000000, 0, 0}, }, - { 556800, { }, { 1050000, 0, 0}, }, - { 600000, { }, { 1100000, 0, 0}, }, - { 600000, { }, { 1150000, 0, 0}, }, - { 600000, { }, { 1200000, 0, 0}, }, - { 600000, { }, { 1230000, 0, 0}, }, - { 0, { }, { 0, 0, 0}, }, - }, - }, - { - .speedo_id = 0, - .process_id = 1, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll pll: c0, c1, c2 */ - { 192000, { }, { 800000, 0, 0}, }, - { 268800, { }, { 850000, 0, 0}, }, - { 345600, { }, { 900000, 0, 0}, }, - { 384000, { }, { 950000, 0, 0}, }, - { 499200, { }, { 1000000, 0, 0}, }, - { 556800, { }, { 1050000, 0, 0}, }, - { 600000, { }, { 1100000, 0, 0}, }, - { 600000, { }, { 1150000, 0, 0}, }, - { 600000, { }, { 1200000, 0, 0}, }, - { 600000, { }, { 1230000, 0, 0}, }, - { 0, { }, { 0, 0, 0}, }, - }, - }, - { - .speedo_id = 1, - .process_id = 1, - .freqs_mult = KHZ, - .speedo_scale = 100, - .voltage_scale = 1000, - .cvb_table = { - /*f dfll pll: c0, c1, c2 */ - { 192000, { }, { 800000, 0, 0}, }, - { 268800, { }, { 850000, 0, 0}, }, - { 345600, { }, { 900000, 0, 0}, }, - { 384000, { }, { 950000, 0, 0}, }, - { 499200, { }, { 1000000, 0, 0}, }, - { 556800, { }, { 1050000, 0, 0}, }, - { 595200, { }, { 1100000, 0, 0}, }, - { 672000, { }, { 1150000, 0, 0}, }, - { 710400, { }, { 1200000, 0, 0}, }, - { 748800, { }, { 1230000, 0, 0}, }, - { 0, { }, { 0, 0, 0}, }, - }, - }, -}; - -static int c2bus_millivolts[MAX_DVFS_FREQS]; -static struct dvfs c2bus_dvfs_table[] = { - { .clk_name = "3d", }, - { .clk_name = "2d", }, - { .clk_name = "epp", }, - { .clk_name = "c2bus", }, /* must be the last */ -}; - -int tegra_dvfs_disable_core_set(const char *arg, const struct kernel_param *kp) -{ - int ret; - - ret = param_set_bool(arg, kp); - if (ret) - return ret; - - if (tegra_dvfs_core_disabled) - tegra_dvfs_rail_disable(&tegra14_dvfs_rail_vdd_core); - else - tegra_dvfs_rail_enable(&tegra14_dvfs_rail_vdd_core); - - return 0; -} - -int tegra_dvfs_disable_cpu_set(const char *arg, const struct kernel_param *kp) -{ - int ret; - - ret = param_set_bool(arg, kp); - if (ret) - return ret; - - if (tegra_dvfs_cpu_disabled) - tegra_dvfs_rail_disable(&tegra14_dvfs_rail_vdd_cpu); - else - tegra_dvfs_rail_enable(&tegra14_dvfs_rail_vdd_cpu); - - return 0; -} - -int tegra_dvfs_disable_get(char *buffer, const struct kernel_param *kp) -{ - return param_get_bool(buffer, kp); -} - -static struct kernel_param_ops tegra_dvfs_disable_core_ops = { - .set = tegra_dvfs_disable_core_set, - .get = tegra_dvfs_disable_get, -}; - -static struct kernel_param_ops tegra_dvfs_disable_cpu_ops = { - .set = tegra_dvfs_disable_cpu_set, - .get = tegra_dvfs_disable_get, -}; - -module_param_cb(disable_core, &tegra_dvfs_disable_core_ops, - &tegra_dvfs_core_disabled, 0644); -module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops, - &tegra_dvfs_cpu_disabled, 0644); - -static bool __init can_update_max_rate(struct clk *c, struct dvfs *d) -{ - /* Don't update manual dvfs clocks */ - if (!d->auto_dvfs) - return false; - - /* - * Don't update EMC shared bus, since EMC dvfs is board dependent: max - * rate and EMC scaling frequencies are determined by tegra BCT (flashed - * together with the image) and board specific EMC DFS table; we will - * check the scaling ladder against nominal core voltage when the table - * is loaded (and if on particular board the table is not loaded, EMC - * scaling is disabled). - */ - if (c->ops->shared_bus_update && (c->flags & PERIPH_EMC_ENB)) - return false; - - /* - * Don't update shared cbus, and don't propagate common cbus dvfs - * limit down to shared users, but set maximum rate for each user - * equal to the respective client limit. - */ - if (c->ops->shared_bus_update && (c->flags & PERIPH_ON_CBUS)) { - struct clk *user; - unsigned long rate; - - list_for_each_entry( - user, &c->shared_bus_list, u.shared_bus_user.node) { - if (user->u.shared_bus_user.client) { - rate = user->u.shared_bus_user.client->max_rate; - user->max_rate = rate; - user->u.shared_bus_user.rate = rate; - } - } - return false; - } - - /* Other, than EMC and cbus, auto-dvfs clocks can be updated */ - return true; -} - -static void __init init_dvfs_one(struct dvfs *d, int max_freq_index) -{ - int ret; - struct clk *c = tegra_get_clock_by_name(d->clk_name); - - if (!c) { - pr_debug("tegra14_dvfs: no clock found for %s\n", - d->clk_name); - return; - } - - /* Update max rate for auto-dvfs clocks, with shared bus exceptions */ - if (can_update_max_rate(c, d)) { - BUG_ON(!d->freqs[max_freq_index]); - tegra_init_max_rate( - c, d->freqs[max_freq_index] * d->freqs_mult); - } - d->max_millivolts = d->dvfs_rail->nominal_millivolts; - - ret = tegra_enable_dvfs_on_clk(c, d); - if (ret) - pr_err("tegra14_dvfs: failed to enable dvfs on %s\n", c->name); -} - -static bool __init match_dvfs_one(const char *name, - int dvfs_speedo_id, int dvfs_process_id, - int speedo_id, int process_id) -{ - if ((dvfs_process_id != -1 && dvfs_process_id != process_id) || - (dvfs_speedo_id != -1 && dvfs_speedo_id != speedo_id)) { - pr_debug("tegra14_dvfs: rejected %s speedo %d, process %d\n", - name, dvfs_speedo_id, dvfs_process_id); - return false; - } - return true; -} - -/* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) / v_scale */ -static inline int get_cvb_voltage(int speedo, int s_scale, - struct cvb_dvfs_parameters *cvb) -{ - /* apply only speedo scale: output mv = cvb_mv * v_scale */ - int mv; - mv = DIV_ROUND_CLOSEST(cvb->c2 * speedo, s_scale); - mv = DIV_ROUND_CLOSEST((mv + cvb->c1) * speedo, s_scale) + cvb->c0; - return mv; -} - -static inline int round_cvb_voltage(int mv, int v_scale) -{ - /* combined: apply voltage scale and round to cvb alignment step */ - int cvb_align_step_uv = tegra_get_cvb_alignment_uV(); - - return DIV_ROUND_UP(mv * 1000, v_scale * cvb_align_step_uv) * - cvb_align_step_uv / 1000; -} - -static inline int round_core_cvb_voltage(int mv, int v_scale) -{ - /* combined: apply voltage scale and round to cvb alignment step */ - int cvb_align_step_uv = tegra_get_core_cvb_alignment_uV(); - - return DIV_ROUND_UP(mv * 1000, v_scale * cvb_align_step_uv) * - cvb_align_step_uv / 1000; -} - -static int __init set_cpu_dvfs_data( - struct cpu_cvb_dvfs *d, struct dvfs *cpu_dvfs, int *max_freq_index) -{ - int i, j, mv, dfll_mv, min_dfll_mv; - unsigned long fmax_at_vmin = 0; - unsigned long fmax_pll_mode = 0; - unsigned long fmin_use_dfll = 0; - struct cvb_dvfs_table *table = NULL; - int speedo = tegra_cpu_speedo_value(); - - min_dfll_mv = d->dfll_tune_data.min_millivolts; - min_dfll_mv = round_cvb_voltage(min_dfll_mv * 1000, 1000); - d->max_mv = round_cvb_voltage(d->max_mv * 1000, 1000); - BUG_ON(min_dfll_mv < tegra14_dvfs_rail_vdd_cpu.min_millivolts); - - /* - * Use CVB table to fill in CPU dvfs frequencies and voltages. Each - * CVB entry specifies CPU frequency and CVB coefficients to calculate - * the respective voltage when either DFLL or PLL is used as CPU clock - * source. - * - * Minimum voltage limit is applied only to DFLL source. For PLL source - * voltage can go as low as table specifies. Maximum voltage limit is - * applied to both sources, but differently: directly clip voltage for - * DFLL, and limit maximum frequency for PLL. - */ - for (i = 0, j = 0; i < MAX_DVFS_FREQS; i++) { - table = &d->cvb_table[i]; - if (!table->freq) - break; - - dfll_mv = get_cvb_voltage( - speedo, d->speedo_scale, &table->cvb_dfll_param); - dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale); - - mv = get_cvb_voltage( - speedo, d->speedo_scale, &table->cvb_pll_param); - mv = round_cvb_voltage(mv, d->voltage_scale); - - /* - * Check maximum frequency at minimum voltage for dfll source; - * round down unless all table entries are above Vmin, then use - * the 1st entry as is. - */ - dfll_mv = max(dfll_mv, min_dfll_mv); - if (dfll_mv > min_dfll_mv) { - if (!j) - fmax_at_vmin = table->freq; - if (!fmax_at_vmin) - fmax_at_vmin = cpu_dvfs->freqs[j - 1]; - } - - /* Clip maximum frequency at maximum voltage for pll source */ - if (mv > d->max_mv) { - if (!j) - break; /* 1st entry already above Vmax */ - if (!fmax_pll_mode) - fmax_pll_mode = cpu_dvfs->freqs[j - 1]; - } - - /* Minimum rate with pll source voltage above dfll Vmin */ - if ((mv >= min_dfll_mv) && (!fmin_use_dfll)) - fmin_use_dfll = table->freq; - - /* fill in dvfs tables */ - cpu_dvfs->freqs[j] = table->freq; - cpu_dfll_millivolts[j] = min(dfll_mv, d->max_mv); - cpu_millivolts[j] = mv; - j++; - - /* - * "Round-up" frequency list cut-off (keep first entry that - * exceeds max voltage - the voltage limit will be enforced - * anyway, so when requested this frequency dfll will settle - * at whatever high frequency it can on the particular chip) - */ - if (dfll_mv > d->max_mv) - break; - } - /* Table must not be empty, must have at least one entry above Vmin */ - if (!i || !j || !fmax_at_vmin) { - pr_err("tegra14_dvfs: invalid cpu dvfs table\n"); - return -ENOENT; - } - - /* In the dfll operating range dfll voltage at any rate should be - better (below) than pll voltage */ - if (!fmin_use_dfll || (fmin_use_dfll > fmax_at_vmin)) { - WARN(1, "tegra14_dvfs: pll voltage is below dfll in the dfll" - " operating range\n"); - fmin_use_dfll = fmax_at_vmin; - } - - /* dvfs tables are successfully populated - fill in the rest */ - cpu_dvfs->speedo_id = d->speedo_id; - cpu_dvfs->process_id = d->process_id; - cpu_dvfs->freqs_mult = d->freqs_mult; - cpu_dvfs->dvfs_rail->nominal_millivolts = min(d->max_mv, - max(cpu_millivolts[j - 1], cpu_dfll_millivolts[j - 1])); - *max_freq_index = j - 1; - - cpu_dvfs->dfll_data = d->dfll_tune_data; - cpu_dvfs->dfll_data.max_rate_boost = fmax_pll_mode ? - (cpu_dvfs->freqs[j - 1] - fmax_pll_mode) * d->freqs_mult : 0; - cpu_dvfs->dfll_data.out_rate_min = fmax_at_vmin * d->freqs_mult; - cpu_dvfs->dfll_data.use_dfll_rate_min = fmin_use_dfll * d->freqs_mult; - cpu_dvfs->dfll_data.min_millivolts = min_dfll_mv; - return 0; -} - -static int __init set_c2bus_dvfs_data( - struct core_cvb_dvfs *d, struct dvfs *c2bus_dvfs, int *max_freq_index) -{ - int i, j, mv, min_mv, max_mv; - struct cvb_dvfs_table *table = NULL; - int speedo = 0; /* FIXME: tegra_core_speedo_value(); */ - - min_mv = round_core_cvb_voltage(core_millivolts[0] * 1000, 1000); - max_mv = tegra14_dvfs_rail_vdd_core.nominal_millivolts; - - /* - * Use CVB table to fill in c2bus dvfs frequencies and voltages. Each - * CVB entry specifies c2bus frequency and CVB coefficients to calculate - * the respective voltage. - */ - for (i = 0, j = 0; i < MAX_DVFS_FREQS; i++) { - table = &d->cvb_table[i]; - if (!table->freq) - break; - - mv = get_cvb_voltage( - speedo, d->speedo_scale, &table->cvb_pll_param); - mv = round_core_cvb_voltage(mv, d->voltage_scale); - - if (mv > max_mv) - break; - - /* fill in c2bus dvfs tables */ - mv = max(mv, min_mv); - if (!j || (mv > c2bus_millivolts[j - 1])) { - c2bus_millivolts[j] = mv; - c2bus_dvfs->freqs[j] = table->freq; - j++; - } else { - c2bus_dvfs->freqs[j - 1] = table->freq; - } - } - /* Table must not be empty, must have at least one entry above Vmin */ - if (!i || !j) { - pr_err("tegra14_dvfs: invalid c2bus dvfs table\n"); - return -ENOENT; - } - - /* dvfs tables are successfully populated - fill in the c2bus dvfs */ - c2bus_dvfs->speedo_id = d->speedo_id; - c2bus_dvfs->process_id = d->process_id; - c2bus_dvfs->freqs_mult = d->freqs_mult; - c2bus_dvfs->millivolts = c2bus_millivolts; - c2bus_dvfs->dvfs_rail = &tegra14_dvfs_rail_vdd_core; - c2bus_dvfs->auto_dvfs = 1; - - *max_freq_index = j - 1; - return 0; -} - -static int __init init_c2bus_cvb_dvfs(int soc_speedo_id, int core_process_id) -{ - int i, ret; - int max_freq_index = 0; - int n = ARRAY_SIZE(c2bus_cvb_dvfs_table); - int m = ARRAY_SIZE(c2bus_dvfs_table); - struct dvfs *bus_dvfs = &c2bus_dvfs_table[m - 1]; - - /* - * Setup bus (last) entry in c2bus legacy dvfs table from cvb data; - * determine maximum frequency index (cvb may devine for c2bus modules - * number of frequencies, and voltage levels different from other core - * dvfs modules). Error when c2bus legacy dvfs table can not be - * constructed must never happen. - */ - for (ret = 0, i = 0; i < n; i++) { - struct core_cvb_dvfs *d = &c2bus_cvb_dvfs_table[i]; - if (match_dvfs_one("c2bus cvb", d->speedo_id, d->process_id, - soc_speedo_id, core_process_id)) { - ret = set_c2bus_dvfs_data(d, bus_dvfs, &max_freq_index); - break; - } - } - BUG_ON((i == n) || ret); - - /* - * Copy bus dvfs entry across all entries in c2bus legacy devfs table, - * and bind each entry to clock - */ - for (i = 0; i < m; i++) { - struct dvfs *d = &c2bus_dvfs_table[i]; - if (d != bus_dvfs) { - const char *name = d->clk_name; - *d = *bus_dvfs; - d->clk_name = name; - } -#ifdef CONFIG_TEGRA_DUAL_CBUS - init_dvfs_one(d, max_freq_index); -#endif - } - return 0; -} - -static int __init get_core_nominal_mv_index(int speedo_id) -{ - int i; - int mv = tegra_core_speedo_mv(); - int core_edp_limit = get_core_edp(); - - /* - * Start with nominal level for the chips with this speedo_id. Then, - * make sure core nominal voltage is below edp limit for the board - * (if edp limit is set). - */ - if (core_edp_limit) - mv = min(mv, core_edp_limit); - mv = round_core_cvb_voltage(mv * 1000, 1000); - - /* Round nominal level down to the nearest core scaling step */ - for (i = 0; i < MAX_DVFS_FREQS; i++) { - if ((core_millivolts[i] == 0) || (mv < core_millivolts[i])) - break; - } - - if (i == 0) { - pr_err("tegra14_dvfs: unable to adjust core dvfs table to" - " nominal voltage %d\n", mv); - return -ENOSYS; - } - return i - 1; -} - -int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, - bool before_clk_update, int cpu_event) -{ - /* empty definition for tegra14 */ - return 0; -} - -void __init tegra14x_init_dvfs(void) -{ - int cpu_speedo_id = tegra_cpu_speedo_id(); - int cpu_process_id = tegra_cpu_process_id(); - int soc_speedo_id = tegra_soc_speedo_id(); - int core_process_id = tegra_core_process_id(); - - int i, ret; - int core_nominal_mv_index; - int cpu_max_freq_index = 0; - -#ifndef CONFIG_TEGRA_CORE_DVFS - tegra_dvfs_core_disabled = true; -#endif -#ifndef CONFIG_TEGRA_CPU_DVFS - tegra_dvfs_cpu_disabled = true; -#endif - /* Setup rail bins */ - tegra14_dvfs_rail_vdd_cpu.stats.bin_uV = tegra_get_cvb_alignment_uV(); - tegra14_dvfs_rail_vdd_core.stats.bin_uV = - tegra_get_core_cvb_alignment_uV(); - - /* Align dvfs voltages */ - for (i = 0; (i < MAX_DVFS_FREQS) && (core_millivolts[i] != 0); i++) { - ((int *)core_millivolts)[i] = - round_core_cvb_voltage(core_millivolts[i] * 1000, 1000); - } - - /* - * Find nominal voltages for core (1st) and cpu rails before rail - * init. Nominal voltage index in core scaling ladder can also be - * used to determine max dvfs frequencies for all core clocks. In - * case of error disable core scaling and set index to 0, so that - * core clocks would not exceed rates allowed at minimum voltage. - */ - core_nominal_mv_index = get_core_nominal_mv_index(soc_speedo_id); - if (core_nominal_mv_index < 0) { - tegra14_dvfs_rail_vdd_core.disabled = true; - tegra_dvfs_core_disabled = true; - core_nominal_mv_index = 0; - } - tegra14_dvfs_rail_vdd_core.nominal_millivolts = - core_millivolts[core_nominal_mv_index]; - - /* - * Setup cpu dvfs and dfll tables from cvb data, determine nominal - * voltage for cpu rail, and cpu maximum frequency. Note that entire - * frequency range is guaranteed only when dfll is used as cpu clock - * source. Reaching maximum frequency with pll as cpu clock source - * may not be possible within nominal voltage range (dvfs mechanism - * would automatically fail frequency request in this case, so that - * voltage limit is not violated). Error when cpu dvfs table can not - * be constructed must never happen. - */ - for (ret = 0, i = 0; i < ARRAY_SIZE(cpu_cvb_dvfs_table); i++) { - struct cpu_cvb_dvfs *d = &cpu_cvb_dvfs_table[i]; - if (match_dvfs_one("cpu cvb", d->speedo_id, d->process_id, - cpu_speedo_id, cpu_process_id)) { - ret = set_cpu_dvfs_data( - d, &cpu_dvfs, &cpu_max_freq_index); - break; - } - } - BUG_ON((i == ARRAY_SIZE(cpu_cvb_dvfs_table)) || ret); - - /* Init thermal limits */ - tegra_dvfs_rail_init_vmax_thermal_profile( - vdd_cpu_vmax_trips_table, vdd_cpu_therm_caps_table, - &tegra14_dvfs_rail_vdd_cpu, &cpu_dvfs.dfll_data); - tegra_dvfs_rail_init_vmin_thermal_profile( - cpu_cvb_dvfs_table[i].vmin_trips_table, - cpu_cvb_dvfs_table[i].therm_floors_table, - &tegra14_dvfs_rail_vdd_cpu, &cpu_dvfs.dfll_data); - tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table, - vdd_core_therm_floors_table, &tegra14_dvfs_rail_vdd_core, NULL); - - /* Init rail structures and dependencies */ - tegra_dvfs_init_rails(tegra14_dvfs_rails, - ARRAY_SIZE(tegra14_dvfs_rails)); - - /* Init c2bus modules (a subset of core dvfs) that have cvb data */ - init_c2bus_cvb_dvfs(soc_speedo_id, core_process_id); - - /* Search core dvfs table for speedo/process matching entries and - initialize dvfs-ed clocks */ - for (i = 0; i < ARRAY_SIZE(core_dvfs_table); i++) { - struct dvfs *d = &core_dvfs_table[i]; - if (!match_dvfs_one(d->clk_name, d->speedo_id, d->process_id, - soc_speedo_id, core_process_id)) - continue; - init_dvfs_one(d, core_nominal_mv_index); - } - - /* Initialize matching cpu dvfs entry already found when nominal - voltage was determined */ - init_dvfs_one(&cpu_dvfs, cpu_max_freq_index); - - /* Finally disable dvfs on rails if necessary */ - if (tegra_dvfs_core_disabled) - tegra_dvfs_rail_disable(&tegra14_dvfs_rail_vdd_core); - if (tegra_dvfs_cpu_disabled) - tegra_dvfs_rail_disable(&tegra14_dvfs_rail_vdd_cpu); - - pr_info("tegra dvfs: VDD_CPU nominal %dmV, scaling %s\n", - tegra14_dvfs_rail_vdd_cpu.nominal_millivolts, - tegra_dvfs_cpu_disabled ? "disabled" : "enabled"); - pr_info("tegra dvfs: VDD_CORE nominal %dmV, scaling %s\n", - tegra14_dvfs_rail_vdd_core.nominal_millivolts, - tegra_dvfs_core_disabled ? "disabled" : "enabled"); -} - -int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail) -{ - return 0; -} - -int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail) -{ - return 0; -} - -/* Core voltage and bus cap object and tables */ -static struct kobject *cap_kobj; - -static struct core_dvfs_cap_table tegra14_core_cap_table[] = { -#ifdef CONFIG_TEGRA_DUAL_CBUS - { .cap_name = "cap.c2bus" }, - { .cap_name = "cap.c3bus" }, -#else - { .cap_name = "cap.cbus" }, -#endif - { .cap_name = "cap.sclk" }, - { .cap_name = "cap.emc" }, - { .cap_name = "cap.host1x" }, - { .cap_name = "cap.msenc" }, -}; - -/* - * Keep sys file names the same for dual and single cbus configurations to - * avoid changes in user space GPU capping interface. - */ -static struct core_bus_limit_table tegra14_bus_cap_table[] = { -#ifdef CONFIG_TEGRA_DUAL_CBUS - { .limit_clk_name = "cap.profile.c2bus", - .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "cbus_cap_level", .mode = 0644} }, - }, -#else - { .limit_clk_name = "cap.profile.cbus", - .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} }, - .level_attr = {.attr = {.name = "cbus_cap_level", .mode = 0644} }, - }, -#endif -}; - -static int __init tegra14_dvfs_init_core_cap(void) -{ - int ret; - - cap_kobj = kobject_create_and_add("tegra_cap", kernel_kobj); - if (!cap_kobj) { - pr_err("tegra14_dvfs: failed to create sysfs cap object\n"); - return 0; - } - - ret = tegra_init_shared_bus_cap( - tegra14_bus_cap_table, ARRAY_SIZE(tegra14_bus_cap_table), - cap_kobj); - if (ret) { - pr_err("tegra14_dvfs: failed to init bus cap interface (%d)\n", - ret); - kobject_del(cap_kobj); - return 0; - } - - ret = tegra_init_core_cap( - tegra14_core_cap_table, ARRAY_SIZE(tegra14_core_cap_table), - core_millivolts, ARRAY_SIZE(core_millivolts), cap_kobj); - - if (ret) { - pr_err("tegra14_dvfs: failed to init core cap interface (%d)\n", - ret); - kobject_del(cap_kobj); - return 0; - } - pr_info("tegra dvfs: tegra sysfs cap interface is initialized\n"); - - return 0; -} -late_initcall(tegra14_dvfs_init_core_cap); diff --git a/arch/arm/mach-tegra/tegra14_edp.c b/arch/arm/mach-tegra/tegra14_edp.c deleted file mode 100644 index 1c64785b5771..000000000000 --- a/arch/arm/mach-tegra/tegra14_edp.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14_edp.c - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/string.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/kobject.h> -#include <linux/err.h> - -#include <mach/edp.h> - -#include "clock.h" -#include "common.h" - -#define CORE_MODULES_STATES 1 -#define TEMPERATURE_RANGES 5 -#define CAP_CLKS_NUM 2 -#define TOTAL_CAPS (CORE_EDP_PROFILES_NUM * CORE_MODULES_STATES *\ - TEMPERATURE_RANGES * CAP_CLKS_NUM) - -struct core_edp_entry { - int sku; - unsigned int cap_mA; - int mult; - unsigned long cap_cpu[CORE_EDP_PROFILES_NUM][ - CORE_MODULES_STATES][TEMPERATURE_RANGES][CAP_CLKS_NUM]; -}; - -static int temperatures[] = { 50, 70, 80, 90, 100 }; - -#ifdef CONFIG_TEGRA_DUAL_CBUS -static char *cap_clks_names[] = { "edp.emc", "edp.c2bus" }; -#else -static char *cap_clks_names[] = { "edp.emc", "edp.cbus" }; -#endif -static struct clk *cap_clks[CAP_CLKS_NUM]; - -/* FIXME: Populate with correct values as per final EDP tables. - * Currently contains *safe* values - */ -static struct core_edp_entry core_edp_table[] = { - { - .sku = 0x7, - .cap_mA = 3000, /* 3A cap */ - .mult = 1000000, /* MHZ */ - .cap_cpu = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 921, 655 }, - { 921, 596 }, - { 921, 596 }, - { 921, 596 }, - { 921, 557 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 921, 655 }, - { 921, 596 }, - { 921, 596 }, - { 921, 596 }, - { 788, 596 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 921, 655 }, - { 788, 655 }, - { 921, 596 }, - { 921, 596 }, - { 788, 596 }, - } - }, - }, - }, - { - .sku = 0x3, - .cap_mA = 3000, /* 3A cap */ - .mult = 1000000, /* MHZ */ - .cap_cpu = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 921, 672 }, - { 921, 596 }, - { 921, 596 }, - { 921, 596 }, - { 921, 557 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 921, 672 }, - { 788, 672 }, - { 921, 596 }, - { 921, 596 }, - { 788, 596 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 921, 672 }, - { 788, 672 }, - { 921, 596 }, - { 921, 596 }, - { 788, 596 }, - } - }, - }, - }, - { - .sku = 0x3, /* SL460 */ - .cap_mA = 3500, /* 3.5A cap */ - .mult = 1000000, /* MHZ */ - .cap_cpu = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 921, 711 }, - { 921, 711 }, - { 921, 711 }, - { 921, 672 }, - { 921, 672 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 788, 749 }, - { 921, 711 }, - { 921, 711 }, - { 921, 672 }, - { 921, 672 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 788, 749 }, - { 921, 711 }, - { 921, 711 }, - { 921, 672 }, - { 921, 672 }, - } - }, - }, - }, - { - .sku = 0x3, /* SL460 */ - .cap_mA = 4000, /* 4A cap */ - .mult = 1000000, /* MHZ */ - .cap_cpu = { - /* favor emc */ - { /* core modules power state 0 (all ON) */ - {{ 921, 749 }, - { 921, 749 }, - { 921, 711 }, - { 921, 672 }, - { 921, 672 }, - }, - }, - /* balanced profile */ - { /* core modules power state 0 (all ON) */ - {{ 921, 749 }, - { 921, 749 }, - { 921, 711 }, - { 921, 672 }, - { 921, 672 }, - }, - }, - /* favor gpu */ - { /* core modules power state 0 (all ON) */ - {{ 921, 749 }, - { 921, 749 }, - { 921, 711 }, - { 921, 672 }, - { 921, 672 }, - } - }, - }, - } -}; - -#ifdef CONFIG_TEGRA_EDP_LIMITS -#define LEAKAGE_CONSTS_IJK_COMMON \ - { \ - /* i = 0 */ \ - { { 564982, -1353469, 309283, -20862, }, \ - { -1866916, 4500931, -1026666, 68669, }, \ - { 1965934, -4869757, 1107682, -73554, }, \ - { -637854, 1715497, -388916, 25621, }, \ - }, \ - /* i = 1 */ \ - { { -7341396, 7706464, -1729662, 114105, }, \ - { 24249928, -25178676, 5651247, -370322, }, \ - { -26109261, 26794485, -6018513, 392722, }, \ - { 9127986, -9288224, 2091707, -135487, }, \ - }, \ - /* i = 2 */ \ - { { 9830061, -9444047, 2035950, -132842, }, \ - { -31837469, 30412491, -6571344, 428173, }, \ - { 33645736, -31974811, 6933186, -452148, }, \ - { -11561204, 11000249, -2395570, 156270, }, \ - }, \ - /* i = 3 */ \ - { { -2848862, 2437747, -500201, 31386, }, \ - { 9160903, -7785587, 1605160, -100724, }, \ - { -9619266, 8124245, -1686232, 106069, }, \ - { 3291191, -2777151, 581139, -36610, }, \ - }, \ - } - -#define LEAKAGE_PARAMS_COMMON_PART \ - .temp_scaled = 10, \ - .dyn_scaled = 1000000, \ - .dyn_consts_n = { 376000, 638000, 916000, 1203000 }, \ - .consts_scaled = 1000000, \ - .leakage_consts_n = { 489500, 730600, 867600, 1000000 }, \ - .ijk_scaled = 1000, \ - .leakage_min = 30, \ - .volt_temp_cap = { 80, 1200 }, \ - .leakage_consts_ijk = LEAKAGE_CONSTS_IJK_COMMON - -static struct tegra_edp_cpu_leakage_params t14x_leakage_params[] = { - { - .cpu_speedo_id = 0, /* A01 CPU */ - LEAKAGE_PARAMS_COMMON_PART, - }, - { - .cpu_speedo_id = 1, /* SKU 0x3 CPU */ - LEAKAGE_PARAMS_COMMON_PART, - }, -}; - -struct tegra_edp_cpu_leakage_params *tegra14x_get_leakage_params(int index, - unsigned int *sz) -{ - BUG_ON(index >= ARRAY_SIZE(t14x_leakage_params)); - if (sz) - *sz = ARRAY_SIZE(t14x_leakage_params); - return &t14x_leakage_params[index]; -} -#endif - -static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(core_edp_table); i++) { - struct core_edp_entry *entry = &core_edp_table[i]; - if ((entry->sku == sku) && (entry->cap_mA == regulator_mA)) - return entry; - } - return NULL; -} - -static unsigned long clip_cap_rate(struct clk *cap_clk, unsigned long rate) -{ - unsigned long floor, ceiling; - struct clk *p = clk_get_parent(cap_clk); - - if (!p || !p->ops || !p->ops->shared_bus_update) { - WARN(1, "%s: edp cap clk %s is not a shared bus user\n", - __func__, cap_clk->name); - return rate; - } - - /* - * Clip cap rate to shared bus possible rates (going up via shared - * bus * ladder since bus clocks always rounds up with resolution of - * at least 2kHz) - */ - ceiling = clk_round_rate(p, clk_get_min_rate(p)); - do { - floor = ceiling; - ceiling = clk_round_rate(p, floor + 2000); - if (IS_ERR_VALUE(ceiling)) { - pr_err("%s: failed to clip %lu to %s possible rates\n", - __func__, rate, p->name); - return rate; - } - } while ((floor < ceiling) && (ceiling <= rate)); - - if (floor > rate) - WARN(1, "%s: %s cap rate %lu is below %s floor %lu\n", - __func__, cap_clk->name, rate, p->name, floor); - return floor; -} - -int __init tegra14x_select_core_edp_table(unsigned int regulator_mA, - struct tegra_core_edp_limits *limits) -{ - int i; - int sku; - unsigned long *cap_rates; - struct core_edp_entry *edp_entry; - - BUG_ON(ARRAY_SIZE(temperatures) != TEMPERATURE_RANGES); - BUG_ON(ARRAY_SIZE(cap_clks_names) != CAP_CLKS_NUM); - - for (i = 0; i < CAP_CLKS_NUM; i++) { - struct clk *c = tegra_get_clock_by_name(cap_clks_names[i]); - if (!c) { - pr_err("%s: failed to find edp cap clock %s\n", - __func__, cap_clks_names[i]); - return -ENODEV; - } - cap_clks[i] = c; - } - - sku = tegra_get_sku_id(); - if (sku == 0x0) - sku = 0x7; - - if ((sku == 0x7) && (regulator_mA >= 3500)) { - pr_info("%s: no core edp capping for sku %d, %d mA\n", - __func__, sku, regulator_mA); - return -ENODATA; - } - - edp_entry = find_edp_entry(sku, regulator_mA); - if (!edp_entry) { - pr_info("%s: no core edp table for sku %d, %d mA\n", - __func__, sku, regulator_mA); - return -ENODATA; - } - - limits->sku = sku; - limits->cap_clocks = cap_clks; - limits->cap_clocks_num = CAP_CLKS_NUM; - limits->temperatures = temperatures; - limits->temperature_ranges = TEMPERATURE_RANGES; - limits->core_modules_states = CORE_MODULES_STATES; - - cap_rates = &edp_entry->cap_cpu[0][0][0][0]; - limits->cap_rates_scpu_on = cap_rates; - limits->cap_rates_scpu_off = cap_rates; - for (i = 0; i < TOTAL_CAPS; i++, cap_rates++) { - unsigned long rate = *cap_rates * edp_entry->mult; - *cap_rates = clip_cap_rate(cap_clks[i % CAP_CLKS_NUM], rate); - } - - return 0; -} diff --git a/arch/arm/mach-tegra/tegra14_emc.c b/arch/arm/mach-tegra/tegra14_emc.c deleted file mode 100644 index 2b50d949d4f4..000000000000 --- a/arch/arm/mach-tegra/tegra14_emc.c +++ /dev/null @@ -1,1885 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14_emc.c - * - * Copyright (c) 2013-2014, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/delay.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/hrtimer.h> -#include <linux/pasr.h> -#include <linux/platform_device.h> -#include <linux/platform_data/tegra_emc_pdata.h> - -#include <asm/cputime.h> - -#include "clock.h" -#include "dvfs.h" -#include "board.h" -#include "iomap.h" -#include "tegra14_emc.h" - -#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE -static bool emc_enable = true; -#else -static bool emc_enable; -#endif -module_param(emc_enable, bool, 0644); - -u8 tegra_emc_bw_efficiency = 100; -static struct emc_iso_usage tegra14_emc_iso_usage[] = { - { BIT(EMC_USER_DC1), 80 }, - { BIT(EMC_USER_DC2), 80 }, - { BIT(EMC_USER_DC1) | BIT(EMC_USER_DC2), 50 }, - { BIT(EMC_USER_DC1) | BIT(EMC_USER_VI), 50 }, - { BIT(EMC_USER_DC2) | BIT(EMC_USER_VI), 50 }, - { BIT(EMC_USER_BB), 50 }, -}; - -#define PLL_C_DIRECT_FLOOR 333500000 -#define EMC_STATUS_UPDATE_TIMEOUT 100 -#define TEGRA_EMC_TABLE_MAX_SIZE 16 - -#define TEGRA_EMC_MODE_REG_17 0x00110000 -#define TEGRA_EMC_MRW_DEV_SHIFT 30 -#define TEGRA_EMC_MRW_DEV1 2 -#define TEGRA_EMC_MRW_DEV2 1 - -#define TEGRA_MC_EMEM_ADR_CFG_DEV 0x58 -#define TEGRA_EMEM_DEV_DEVSIZE_SHIFT 16 -#define TEGRA_EMEM_DEV_DEVSIZE_MASK 0xF - -enum { - DLL_CHANGE_NONE = 0, - DLL_CHANGE_ON, - DLL_CHANGE_OFF, -}; - -#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19c -#define EMC_CLK_DIV_SHIFT 0 -#define EMC_CLK_DIV_MASK (0xFF << EMC_CLK_DIV_SHIFT) -#define EMC_CLK_SOURCE_SHIFT 29 -#define EMC_CLK_SOURCE_MASK (0x7 << EMC_CLK_SOURCE_SHIFT) -#define EMC_CLK_LOW_JITTER_ENABLE (0x1 << 31) -#define EMC_CLK_FORCE_CC_TRIGGER (0x1 << 27) -#define EMC_CLK_MC_SAME_FREQ (0x1 << 16) - -#define PMC_IO_DPD2_REQ 0x1C0 -#define PMC_IO_DPD2_REQ_CODE_SHIFT 30 -#define PMC_IO_DPD2_REQ_CODE_DPD_OFF 0x1 -#define PMC_IO_DPD2_REQ_CODE_DPD_ON 0x2 -#define PMC_IO_DPD2_REQ_DISC_BIAS (0x1 << 27) - -/* FIXME: actual Tegar14 list */ -#define BURST_REG_LIST \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RC), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC_SLR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RAS), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RP), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_R2W), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_W2R), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_R2P), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_W2P), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RD_RCD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WR_RCD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RRD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_REXT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WEXT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV_MASK), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE_WIDTH), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_IBDLY), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM_WIDTH), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CDB_CNTL_2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QRST), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_MASK), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_REFRESH), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_BURST_REFRESH_NUM), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PRE_REFRESH_REQ_CNT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2WR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2RD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PCHG2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ACT2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AR2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RW2PDEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSRDLL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKESR), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TPD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TFAW), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TRPAB), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTABLE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTOP), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TREFBW), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_WRITE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_READ), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL_PERIOD), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS0), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS1), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS7), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE0), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE1), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE7), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_ADDR0), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_ADDR1), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_ADDR2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS0), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS1), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS5), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS7), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQ0), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQ1), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQ2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQ3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQSPADCTRL2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQPADCTRL2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CLKPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CLKPADCTRL2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2COMPPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQSPADCTRL3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQSPADCTRL4), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DSR_VTTGEN_DRV), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_TXDSRVTTGEN), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_SPARE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_TERM_CTRL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_INTERVAL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_WAIT_CNT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG2), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG3), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_DURATION), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_DYN_SELF_REF_CONTROL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_EINPUT), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_EINPUT_DURATION), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QSAFE), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG6), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_PIPE_MACRO_CTL), \ - DEFINE_REG(TEGRA_EMC_BASE, EMC_QPOP), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_CFG), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_OUTSTANDING_REQ), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_OUTSTANDING_REQ_RING3), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RCD), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RP), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RC), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAS), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_FAW), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RRD), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAP2PRE), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_WAP2PRE), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2R), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2W), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2W), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2R), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE), \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING3_THROTTLE), \ - -#define BURST_UP_DOWN_REG_LIST \ - DEFINE_REG(TEGRA_MC_BASE, MC_PTSA_GRANT_DECREMENT), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_1), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_1), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_1), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_0), \ - DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_1), - -#define DEFINE_REG(base, reg) ((base) ? (IO_ADDRESS((base)) + (reg)) : 0) -static void __iomem *burst_reg_addr[TEGRA14_EMC_MAX_NUM_REGS] = { - BURST_REG_LIST -}; -#ifndef EMULATE_CLOCK_SWITCH -static void __iomem *burst_up_down_reg_addr[TEGRA14_EMC_MAX_NUM_REGS] = { - BURST_UP_DOWN_REG_LIST -}; -#endif -#undef DEFINE_REG - -#define DEFINE_REG(base, reg) reg##_INDEX -enum { - BURST_REG_LIST -}; -#undef DEFINE_REG - -#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284 -#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288 -#define CLK_ENB_EMC_DLL (1 << 14) -#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664 -#define EMC_DLL_DYN_MUX_CTRL (1 << 16) - -#define FBIO_SPARE_CFG_SW_DLL_RST_CTRL_N (1 << 27) - -struct emc_sel { - struct clk *input; - u32 value; - unsigned long input_rate; -}; -static struct emc_sel tegra_emc_clk_sel[TEGRA_EMC_TABLE_MAX_SIZE]; -static struct tegra14_emc_table start_timing; -static const struct tegra14_emc_table *emc_timing; -static unsigned long dram_over_temp_state = DRAM_OVER_TEMP_NONE; - -static ktime_t clkchange_time; -static int clkchange_delay = 100; - -static const struct tegra14_emc_table *tegra_emc_table; -static const struct tegra14_emc_table *tegra_emc_table_derated; -static int tegra_emc_table_size; - -static u32 dram_dev_num; -static u32 dram_type = -1; - -static u32 dsr_override; - -static int pasr_enable; - -static struct clk *emc; - -static struct { - cputime64_t time_at_clock[TEGRA_EMC_TABLE_MAX_SIZE]; - int last_sel; - u64 last_update; - u64 clkchange_count; - spinlock_t spinlock; -} emc_stats; - -static DEFINE_SPINLOCK(emc_access_lock); - -static void __iomem *emc_base = IO_ADDRESS(TEGRA_EMC_BASE); -/* !!!FIXME!!! Need clean up for T148 */ -#ifdef CONFIG_ARCH_TEGRA_11x_SOC -static void __iomem *emc0_base = IO_ADDRESS(TEGRA_EMC0_BASE); -static void __iomem *emc1_base = IO_ADDRESS(TEGRA_EMC1_BASE); -#endif -static void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE); -static void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); -static void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); - -static inline void emc_writel(u32 val, unsigned long addr) -{ - writel(val, emc_base + addr); -} -/* !!!FIXME!!! Need clean up for T148 */ -#ifdef CONFIG_ARCH_TEGRA_11x_SOC -static inline void emc0_writel(u32 val, unsigned long addr) -{ - writel(val, emc0_base + addr); -} -static inline void emc1_writel(u32 val, unsigned long addr) -{ - writel(val, emc1_base + addr); -} -#endif -static inline u32 emc_readl(unsigned long addr) -{ - return readl(emc_base + addr); -} -static inline void mc_writel(u32 val, unsigned long addr) -{ - writel(val, mc_base + addr); -} -static inline u32 mc_readl(unsigned long addr) -{ - return readl(mc_base + addr); -} - -static inline void ccfifo_writel(u32 val, unsigned long addr) -{ - writel(val, emc_base + EMC_CCFIFO_DATA); - writel(addr, emc_base + EMC_CCFIFO_ADDR); -} - -static int last_round_idx; -static inline int get_start_idx(unsigned long rate) -{ - if (tegra_emc_table[last_round_idx].rate == rate) - return last_round_idx; - return 0; -} - -static void emc_last_stats_update(int last_sel) -{ - unsigned long flags; - u64 cur_jiffies = get_jiffies_64(); - - spin_lock_irqsave(&emc_stats.spinlock, flags); - - if (emc_stats.last_sel < TEGRA_EMC_TABLE_MAX_SIZE) - emc_stats.time_at_clock[emc_stats.last_sel] = - emc_stats.time_at_clock[emc_stats.last_sel] + - (cur_jiffies - emc_stats.last_update); - - emc_stats.last_update = cur_jiffies; - - if (last_sel < TEGRA_EMC_TABLE_MAX_SIZE) { - emc_stats.clkchange_count++; - emc_stats.last_sel = last_sel; - } - spin_unlock_irqrestore(&emc_stats.spinlock, flags); -} - -static int wait_for_update(u32 status_reg, u32 bit_mask, bool updated_state) -{ - int i; - for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++) { - if (!!(emc_readl(status_reg) & bit_mask) == updated_state) - return 0; - udelay(1); - } - return -ETIMEDOUT; -} - -static inline void emc_timing_update(void) -{ - int err; - - emc_writel(0x1, EMC_TIMING_CONTROL); - err = wait_for_update(EMC_STATUS, - EMC_STATUS_TIMING_UPDATE_STALLED, false); - if (err) { - pr_err("%s: timing update error: %d", __func__, err); - BUG(); - } -} - -static inline void auto_cal_disable(void) -{ - int err; - - emc_writel(0, EMC_AUTO_CAL_INTERVAL); - err = wait_for_update(EMC_AUTO_CAL_STATUS, - EMC_AUTO_CAL_STATUS_ACTIVE, false); - if (err) { - pr_err("%s: disable auto-cal error: %d", __func__, err); - BUG(); - } -} - -static inline void set_over_temp_timing( - const struct tegra14_emc_table *next_timing, unsigned long state) -{ -#define REFRESH_X2 1 -#define REFRESH_X4 2 -#define REFRESH_SPEEDUP(val, speedup) \ - do { \ - val = ((val) & 0xFFFF0000) | \ - (((val) & 0xFFFF) >> (speedup)); \ - } while (0) - - u32 ref = next_timing->burst_regs[EMC_REFRESH_INDEX]; - u32 pre_ref = next_timing->burst_regs[EMC_PRE_REFRESH_REQ_CNT_INDEX]; - u32 dsr_cntrl = next_timing->burst_regs[EMC_DYN_SELF_REF_CONTROL_INDEX]; - - switch (state) { - case DRAM_OVER_TEMP_NONE: - break; - case DRAM_OVER_TEMP_REFRESH_X2: - REFRESH_SPEEDUP(ref, REFRESH_X2); - REFRESH_SPEEDUP(pre_ref, REFRESH_X2); - REFRESH_SPEEDUP(dsr_cntrl, REFRESH_X2); - break; - case DRAM_OVER_TEMP_REFRESH_X4: - case DRAM_OVER_TEMP_THROTTLE: - REFRESH_SPEEDUP(ref, REFRESH_X4); - REFRESH_SPEEDUP(pre_ref, REFRESH_X4); - REFRESH_SPEEDUP(dsr_cntrl, REFRESH_X4); - break; - default: - WARN(1, "%s: Failed to set dram over temp state %lu\n", - __func__, state); - return; - } - - __raw_writel(ref, burst_reg_addr[EMC_REFRESH_INDEX]); - __raw_writel(pre_ref, burst_reg_addr[EMC_PRE_REFRESH_REQ_CNT_INDEX]); - __raw_writel(dsr_cntrl, burst_reg_addr[EMC_DYN_SELF_REF_CONTROL_INDEX]); -} - -static inline bool dqs_preset(const struct tegra14_emc_table *next_timing, - const struct tegra14_emc_table *last_timing) -{ - bool ret = false; - -#define DQS_SET(reg, bit) \ - do { \ - if ((next_timing->burst_regs[EMC_##reg##_INDEX] & \ - EMC_##reg##_##bit##_ENABLE) && \ - (!(last_timing->burst_regs[EMC_##reg##_INDEX] & \ - EMC_##reg##_##bit##_ENABLE))) { \ - emc_writel(last_timing->burst_regs[EMC_##reg##_INDEX] \ - | EMC_##reg##_##bit##_ENABLE, EMC_##reg); \ - ret = true; \ - } \ - } while (0) - - DQS_SET(XM2DQSPADCTRL2, RX_FT_REC); - DQS_SET(XM2DQSPADCTRL2, VREF_DQ); - - return ret; -} - -static inline int get_dll_change(const struct tegra14_emc_table *next_timing, - const struct tegra14_emc_table *last_timing) -{ - bool next_dll_enabled = !(next_timing->emc_mode_1 & 0x1); - bool last_dll_enabled = !(last_timing->emc_mode_1 & 0x1); - - if (next_dll_enabled == last_dll_enabled) - return DLL_CHANGE_NONE; - else if (next_dll_enabled) - return DLL_CHANGE_ON; - else - return DLL_CHANGE_OFF; -} - -static inline void set_dram_mode(const struct tegra14_emc_table *next_timing, - const struct tegra14_emc_table *last_timing, - int dll_change) -{ - /* first mode_2, then mode_1; mode_reset is not applicable */ - if (next_timing->emc_mode_2 != last_timing->emc_mode_2) - ccfifo_writel(next_timing->emc_mode_2, EMC_MRW2); - if (next_timing->emc_mode_1 != last_timing->emc_mode_1) - ccfifo_writel(next_timing->emc_mode_1, EMC_MRW); - if (next_timing->emc_mode_4 != last_timing->emc_mode_4) - ccfifo_writel(next_timing->emc_mode_4, EMC_MRW4); -} - -static inline void do_clock_change(u32 clk_setting) -{ - int err; - - mc_readl(MC_EMEM_ADR_CFG); /* completes prev writes */ - writel(clk_setting, clk_base + emc->reg); - readl(clk_base + emc->reg);/* completes prev write */ - - err = wait_for_update(EMC_INTSTATUS, - EMC_INTSTATUS_CLKCHANGE_COMPLETE, true); - if (err) { - pr_err("%s: clock change completion error: %d", __func__, err); - BUG(); - } -} - -static u32 emc_prelock_dll(const struct tegra14_emc_table *last_timing, - const struct tegra14_emc_table *next_timing) -{ - u32 dll_locked, dll_out; - u32 emc_cfg_dig_dll; - u32 emc_dll_clk_src; - u32 fbio_spare_old, fbio_spare_new; - u32 div_value = (next_timing->src_sel_reg & EMC_CLK_DIV_MASK); - u32 src_value = (next_timing->src_sel_reg & EMC_CLK_SOURCE_MASK); - - /* WAR for missing PLLC_UD DLL clock source selector. */ - if (src_value == (0x7 << EMC_CLK_SOURCE_SHIFT)) - src_value = (0x1 << EMC_CLK_SOURCE_SHIFT); - - /* - * Step 1: - * If the DLL is disabled don't bother disabling it again. - */ - emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL); - - if (last_timing->rate <= 408000) - goto skip_dll_disable; - - emc_cfg_dig_dll &= ~EMC_CFG_DIG_DLL_EN; - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - -skip_dll_disable: - /* - * Step 1.25: - * Force the DLL into override mode. - */ - dll_out = emc_readl(EMC_DIG_DLL_STATUS) & EMC_DIG_DLL_STATUS_OUT; - emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL); - emc_cfg_dig_dll &= ~(EMC_CFG_DIG_DLL_OVERRIDE_VAL_MASK << - EMC_CFG_DIG_DLL_OVERRIDE_VAL_SHIFT); - emc_cfg_dig_dll |= ((dll_out & EMC_CFG_DIG_DLL_OVERRIDE_VAL_MASK) << - EMC_CFG_DIG_DLL_OVERRIDE_VAL_SHIFT); - emc_cfg_dig_dll |= EMC_CFG_DIG_DLL_OVERRIDE_EN; - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - - /* - * Step 1.5: - * Force the DLL into one shot mode. - */ - emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL); - emc_cfg_dig_dll &= ~(EMC_CFG_DIG_DLL_MODE_MASK << - EMC_CFG_DIG_DLL_MODE_SHIFT); - emc_cfg_dig_dll |= (EMC_CFG_DIG_DLL_MODE_RUN_TIL_LOCK << - EMC_CFG_DIG_DLL_MODE_SHIFT); - emc_cfg_dig_dll &= ~(EMC_CFG_DIG_DLL_UDSET_MASK << - EMC_CFG_DIG_DLL_UDSET_SHIFT); - emc_cfg_dig_dll |= (0x2 << EMC_CFG_DIG_DLL_UDSET_SHIFT); - emc_cfg_dig_dll &= ~(EMC_CFG_DIG_DLL_LOCK_LIMIT_MASK << - EMC_CFG_DIG_DLL_LOCK_LIMIT_SHIFT); - emc_cfg_dig_dll |= (next_timing->emc_cfg_dig_dll & - (3 << EMC_CFG_DIG_DLL_LOCK_LIMIT_SHIFT)); - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - - /* - * Step 2: - * Set the DLL's prelocking input. We do this so that we can get an - * override value for when we do the actual swap to this PLL later on. - * Once we swap, we will want this override value. - */ - emc_dll_clk_src = (div_value | src_value); - writel(emc_dll_clk_src, - clk_base + CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL); - writel(emc_dll_clk_src | EMC_DLL_DYN_MUX_CTRL, - clk_base + CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL); - - /* - * Step 2.5: - * Enable CLK to DLL from CAR. - */ - writel(CLK_ENB_EMC_DLL, - clk_base + CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET); - udelay(1); - - /* - * Step 3: - * Reset the DLL and wait for it to lock against the target freq. - */ - fbio_spare_old = emc_readl(EMC_FBIO_SPARE); - fbio_spare_new = fbio_spare_old | FBIO_SPARE_CFG_SW_DLL_RST_CTRL_N; - - emc_writel(fbio_spare_new, EMC_FBIO_SPARE); - emc_timing_update(); - emc_writel(fbio_spare_old, EMC_FBIO_SPARE); - emc_timing_update(); - - emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL); - emc_cfg_dig_dll |= (EMC_CFG_DIG_DLL_EN); - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - udelay(1); - - do { - dll_locked = emc_readl(EMC_DIG_DLL_STATUS) & - EMC_DIG_DLL_STATUS_LOCKED; - } while (!dll_locked); - - if (WARN_ON((emc_readl(EMC_INTSTATUS) & - EMC_INTSTATUS_DLL_LOCK_TIMEOUT_INT))) - emc_writel(EMC_INTSTATUS_DLL_LOCK_TIMEOUT_INT, - EMC_INTSTATUS); - - /* - * Step 4: - * Disable CLK to DLL from CAR. - */ - writel(CLK_ENB_EMC_DLL, - clk_base + CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR); - udelay(1); - - /* - * Step 5: - * Now, reinvoke the state machine logic without the clock. - */ - emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL); - emc_cfg_dig_dll &= ~EMC_CFG_DIG_DLL_EN; - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - - emc_cfg_dig_dll |= EMC_CFG_DIG_DLL_EN; - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - udelay(1); - - dll_out = emc_readl(EMC_DIG_DLL_STATUS) & EMC_DIG_DLL_STATUS_OUT; - - emc_cfg_dig_dll = emc_readl(EMC_CFG_DIG_DLL); - emc_cfg_dig_dll &= ~EMC_CFG_DIG_DLL_EN; - emc_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - emc_timing_update(); - - return dll_out; -} - -static noinline void emc_set_clock(const struct tegra14_emc_table *next_timing, - const struct tegra14_emc_table *last_timing, - u32 clk_setting) -{ - int i, dll_change, pre_wait; - bool dyn_sref_enabled, zcal_long; - - u32 dll_override, emc_cfg_dig_dll, pmc_dpd; - u32 t_start, t_diff; - - u32 use_prelock = 0; - u32 emc_cfg_reg = emc_readl(EMC_CFG); - - if (!(clk_setting & EMC_CLK_FORCE_CC_TRIGGER)) - use_prelock = next_timing->emc_cfg_dig_dll & EMC_CFG_DIG_DLL_EN; - - dyn_sref_enabled = emc_cfg_reg & EMC_CFG_DYN_SREF_ENABLE; - dll_change = get_dll_change(next_timing, last_timing); - zcal_long = (next_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0) && - (last_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0); - - /* 1. clear clkchange_complete interrupts */ - emc_writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE | - EMC_INTSTATUS_DLL_LOCK_TIMEOUT_INT, EMC_INTSTATUS); - - /* 1.5 On t148, prelock the DLL - assuming the DLL is enabled. */ - if (use_prelock) - dll_override = emc_prelock_dll(last_timing, next_timing); - else - dll_override = 0; - - /* 2. disable dynamic self-refresh and preset dqs vref, then wait for - possible self-refresh entry/exit and/or dqs vref settled - waiting - before the clock change decreases worst case change stall time */ - pre_wait = 0; - if (dyn_sref_enabled) { - emc_cfg_reg &= ~EMC_CFG_DYN_SREF_ENABLE; - emc_writel(emc_cfg_reg, EMC_CFG); - pre_wait = 5; /* 5us+ for self-refresh entry/exit */ - } - - /* 2.5 check dq/dqs vref delay */ - if (dqs_preset(next_timing, last_timing)) { - if (pre_wait < 30) - pre_wait = 30; /* (T148) 30us+ for dqs vref settled */ - /* Take the DISC pads out of DPD. */ - pmc_dpd = (PMC_IO_DPD2_REQ_CODE_DPD_OFF << - PMC_IO_DPD2_REQ_CODE_SHIFT); - writel(pmc_dpd | PMC_IO_DPD2_REQ_DISC_BIAS, - pmc_base + PMC_IO_DPD2_REQ); - } - emc_timing_update(); - t_start = tegra_read_usec_raw(); - - /* 3. For t148, leave auto cal alone. */ - - /* 4. program burst shadow registers */ - for (i = 0; i < next_timing->burst_regs_num; i++) { - if (!burst_reg_addr[i]) - continue; - __raw_writel(next_timing->burst_regs[i], burst_reg_addr[i]); - } - if (!use_prelock && !(clk_setting & EMC_CLK_FORCE_CC_TRIGGER)) - writel(next_timing->emc_cfg_dig_dll | EMC_CFG_DIG_DLL_RESET | - EMC_CFG_DIG_DLL_OVERRIDE_EN, emc_base + EMC_CFG_DIG_DLL); - - if ((dram_type == DRAM_TYPE_LPDDR2) && - (dram_over_temp_state != DRAM_OVER_TEMP_NONE)) - set_over_temp_timing(next_timing, dram_over_temp_state); - - emc_cfg_reg &= ~EMC_CFG_UPDATE_MASK; - emc_cfg_reg |= next_timing->emc_cfg & EMC_CFG_UPDATE_MASK; - emc_writel(emc_cfg_reg, EMC_CFG); - wmb(); - barrier(); - - /* 4.1 On ddr3 when DLL is re-started predict MRS long wait count and - overwrite DFS table setting - No DDR3 on t148. */ - - /* 5.2 Moved to ccfifo - see 6.1. */ - - /* 6. turn Off dll and enter self-refresh on DDR3 - No DDR3. */ - - /* 6.1 Disable auto-refresh right before clock change. */ - ccfifo_writel(EMC_REFCTRL_DISABLE_ALL(dram_dev_num), EMC_REFCTRL); - - /* 6.2 Set EMC_SEL_DPD_CTRL based on next freq: disable DATA_DPD for - frequencies above 408 MHz. */ - if (next_timing->rate > 408000) - ccfifo_writel(emc_readl(EMC_SEL_DPD_CTRL) & - ~EMC_SEL_DPD_CTRL_DATA_DPD_ENABLE, - EMC_SEL_DPD_CTRL); - else - ccfifo_writel(emc_readl(EMC_SEL_DPD_CTRL) | - EMC_SEL_DPD_CTRL_DATA_DPD_ENABLE, - EMC_SEL_DPD_CTRL); - - /* 7. flow control marker 2 */ - ccfifo_writel(1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); - - /* 7.05 Re-enable autorefresh with the CCFIFO. */ - ccfifo_writel(EMC_REFCTRL_ENABLE_ALL(dram_dev_num), EMC_REFCTRL); - - /* 7.1 Use the new override value. */ - if (use_prelock) { - emc_cfg_dig_dll = next_timing->emc_cfg_dig_dll & - ~(EMC_CFG_DIG_DLL_OVERRIDE_VAL_MASK << - EMC_CFG_DIG_DLL_OVERRIDE_VAL_SHIFT); - emc_cfg_dig_dll |= (dll_override << - EMC_CFG_DIG_DLL_OVERRIDE_VAL_SHIFT); - emc_cfg_dig_dll |= EMC_CFG_DIG_DLL_OVERRIDE_EN; - emc_cfg_dig_dll &= ~EMC_CFG_DIG_DLL_EN; - emc_cfg_dig_dll &= ~EMC_CFG_DIG_DLL_STALL_RW_UNTIL_LOCK; - ccfifo_writel(emc_cfg_dig_dll, EMC_CFG_DIG_DLL); - } - - /* 7.2 Force an emc timing update here. */ - ccfifo_writel(1, EMC_TIMING_CONTROL); - - /* 8. exit self-refresh on DDR3 - No DDR3 on t148. */ - - /* 9. set dram mode registers */ - set_dram_mode(next_timing, last_timing, dll_change); - - /* 9.5 Update two fields in EMC_CFG that are not shadowed. */ - emc_cfg_reg &= ~(EMC_CFG_MAN_PRE_WR | EMC_CFG_MAN_PRE_RD); - emc_cfg_reg |= next_timing->emc_cfg & - (EMC_CFG_MAN_PRE_WR | EMC_CFG_MAN_PRE_RD); - ccfifo_writel(emc_cfg_reg, EMC_CFG); - - /* 10. issue zcal command if turning zcal On */ - if (zcal_long) { - ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); - if (dram_dev_num > 1) - ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV1, EMC_ZQ_CAL); - } - - /* 10.1 dummy write to RO register to remove stall after change */ - ccfifo_writel(0, EMC_CCFIFO_STATUS); - - /* 11.5 program burst_up_down registers if emc rate is going down */ - if (next_timing->rate < last_timing->rate) { - for (i = 0; i < next_timing->burst_up_down_regs_num; i++) - __raw_writel(next_timing->burst_up_down_regs[i], - burst_up_down_reg_addr[i]); - wmb(); - } - - /* 11.75 Wait what ever time is necessary to make sure pre_wait us - have elapsed since programming vref mode. */ - if (pre_wait) { - t_diff = tegra_read_usec_raw() - t_start; - if (t_diff <= pre_wait) - udelay(1 + pre_wait - t_diff); - } - - /* 12-14. read any MC register to ensure the programming is done - change EMC clock source register wait for clk change completion */ - do_clock_change(clk_setting); - - /* 14.1 re-enable auto-refresh */ - - /* 14.2 program burst_up_down registers if emc rate is going up */ - if (next_timing->rate > last_timing->rate) { - for (i = 0; i < next_timing->burst_up_down_regs_num; i++) - __raw_writel(next_timing->burst_up_down_regs[i], - burst_up_down_reg_addr[i]); - wmb(); - } - - /* 14.3 Check if we are entering schmit mode. If we are, then DPD can - be requested for the BG BIAS cells of the DISC pads. */ - if (~next_timing->burst_regs[EMC_XM2DQSPADCTRL2_INDEX] & - EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE) { - pmc_dpd = (PMC_IO_DPD2_REQ_CODE_DPD_ON << - PMC_IO_DPD2_REQ_CODE_SHIFT); - writel(pmc_dpd | PMC_IO_DPD2_REQ_DISC_BIAS, - pmc_base + PMC_IO_DPD2_REQ); - } - - /* 15. restore auto-cal. On t148, this is just a reprogramming - its - already enabled during the clock change itself. */ - emc_writel(next_timing->emc_acal_interval, EMC_AUTO_CAL_INTERVAL); - - /* 16. restore dynamic self-refresh - for t148 if requested, we will - leave DSR disabled. Otherwise just follow the table entry. */ - if (!dsr_override && next_timing->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { - emc_cfg_reg |= EMC_CFG_DYN_SREF_ENABLE; - emc_writel(emc_cfg_reg, EMC_CFG); - } - - /* 17. set zcal wait count */ - if (zcal_long) - emc_writel(next_timing->emc_zcal_cnt_long, EMC_ZCAL_WAIT_CNT); - - /* 18. update restored timing */ - emc_timing_update(); -} - -static inline void emc_get_timing(struct tegra14_emc_table *timing) -{ - int i; - - /* Burst updates depends on previous state; burst_up_down are - * stateless. */ - for (i = 0; i < timing->burst_regs_num; i++) { - if (burst_reg_addr[i]) - timing->burst_regs[i] = __raw_readl(burst_reg_addr[i]); - else - timing->burst_regs[i] = 0; - } - timing->emc_acal_interval = 0; - timing->emc_zcal_cnt_long = 0; - timing->emc_mode_reset = 0; - timing->emc_mode_1 = 0; - timing->emc_mode_2 = 0; - timing->emc_mode_4 = 0; - timing->emc_cfg = emc_readl(EMC_CFG); - timing->rate = clk_get_rate_locked(emc) / 1000; -} - -/* The EMC registers have shadow registers. When the EMC clock is updated - * in the clock controller, the shadow registers are copied to the active - * registers, allowing glitchless memory bus frequency changes. - * This function updates the shadow registers for a new clock frequency, - * and relies on the clock lock on the emc clock to avoid races between - * multiple frequency changes. In addition access lock prevents concurrent - * access to EMC registers from reading MRR registers */ -int tegra_emc_set_rate(unsigned long rate) -{ - int i; - u32 clk_setting; - const struct tegra14_emc_table *last_timing; - unsigned long flags; - s64 last_change_delay; - - if (!tegra_emc_table) - return -EINVAL; - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; /* invalid entry */ - - if (tegra_emc_table[i].rate == rate) - break; - } - - if (i >= tegra_emc_table_size) - return -EINVAL; - - if (!emc_timing) { - /* can not assume that boot timing matches dfs table even - if boot frequency matches one of the table nodes */ - emc_get_timing(&start_timing); - last_timing = &start_timing; - } - else - last_timing = emc_timing; - - clk_setting = tegra_emc_clk_sel[i].value; - - if (!timekeeping_suspended) { - last_change_delay = ktime_us_delta(ktime_get(), clkchange_time); - if ((last_change_delay >= 0) && - (last_change_delay < clkchange_delay)) - udelay(clkchange_delay - (int)last_change_delay); - } - - spin_lock_irqsave(&emc_access_lock, flags); - /* Pick from the EMC tables based on the status of the over temp state - flag. */ - emc_set_clock(dram_over_temp_state != DRAM_OVER_TEMP_THROTTLE ? - &tegra_emc_table[i] : &tegra_emc_table_derated[i], - last_timing, clk_setting); - clkchange_time = timekeeping_suspended ? clkchange_time : ktime_get(); - emc_timing = dram_over_temp_state != DRAM_OVER_TEMP_THROTTLE ? - &tegra_emc_table[i] : &tegra_emc_table_derated[i]; - if (dram_over_temp_state == DRAM_OVER_TEMP_THROTTLE) - pr_debug("[emc] Picked derated freq.\n"); - spin_unlock_irqrestore(&emc_access_lock, flags); - - emc_last_stats_update(i); - - pr_debug("%s: rate %lu setting 0x%x\n", __func__, rate, clk_setting); - - return 0; -} - -long tegra_emc_round_rate_updown(unsigned long rate, bool up) -{ - int i; - unsigned long table_rate; - - if (!tegra_emc_table) - return clk_get_rate_locked(emc); /* no table - no rate change */ - - if (!emc_enable) - return -EINVAL; - - pr_debug("%s: %lu\n", __func__, rate); - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; /* invalid entry */ - - table_rate = tegra_emc_table[i].rate; - if (table_rate >= rate) { - if (!up && i && (table_rate > rate)) { - i--; - table_rate = tegra_emc_table[i].rate; - } - pr_debug("%s: using %lu\n", __func__, table_rate); - last_round_idx = i; - return table_rate * 1000; - } - } - - return -EINVAL; -} - -struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value) -{ - int i; - - if (!tegra_emc_table) { - if (rate == clk_get_rate_locked(emc)) { - *div_value = emc->div - 2; - return emc->parent; - } - return NULL; - } - - pr_debug("%s: %lu\n", __func__, rate); - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_table[i].rate == rate) { - struct clk *p = tegra_emc_clk_sel[i].input; - - if (p && (tegra_emc_clk_sel[i].input_rate == - clk_get_rate(p))) { - *div_value = (tegra_emc_clk_sel[i].value & - EMC_CLK_DIV_MASK) >> EMC_CLK_DIV_SHIFT; - return p; - } - } - } - return NULL; -} - -bool tegra_emc_is_parent_ready(unsigned long rate, struct clk **parent, - unsigned long *parent_rate, unsigned long *backup_rate) -{ - - int i; - struct clk *p = NULL; - unsigned long p_rate = 0; - - if (!tegra_emc_table) - return true; - - pr_debug("%s: %lu\n", __func__, rate); - - /* Table entries specify rate in kHz */ - rate = rate / 1000; - - i = get_start_idx(rate); - for (; i < tegra_emc_table_size; i++) { - if (tegra_emc_table[i].rate == rate) { - p = tegra_emc_clk_sel[i].input; - if (!p) - continue; /* invalid entry */ - - p_rate = tegra_emc_clk_sel[i].input_rate; - if (p_rate == clk_get_rate(p)) - return true; - break; - } - } - - /* Table match not found - "non existing parent" is ready */ - if (!p) - return true; - -#ifdef CONFIG_TEGRA_PLLM_SCALED - /* - * Table match found, but parent is not ready - check if backup entry - * was found during initialization, and return the respective backup - * rate - */ - if (emc->shared_bus_backup.input && - (emc->shared_bus_backup.input != p)) { - *parent = p; - *parent_rate = p_rate; - *backup_rate = emc->shared_bus_backup.bus_rate; - return false; - } -#else - /* - * Table match found, but parent is not ready - continue search - * for backup rate: min rate above requested that has different - * parent source (since only pll_c is scaled and may not be ready, - * any other parent can provide backup) - */ - *parent = p; - *parent_rate = p_rate; - - for (i++; i < tegra_emc_table_size; i++) { - p = tegra_emc_clk_sel[i].input; - if (!p) - continue; /* invalid entry */ - - if (p != (*parent)) { - *backup_rate = tegra_emc_table[i].rate * 1000; - return false; - } - } -#endif - /* Parent is not ready, and no backup found */ - *backup_rate = -EINVAL; - return false; -} - -static inline const struct clk_mux_sel *get_emc_input(u32 val) -{ - const struct clk_mux_sel *sel; - - for (sel = emc->inputs; sel->input != NULL; sel++) { - if (sel->value == val) - break; - } - return sel; -} - -static int find_matching_input(const struct tegra14_emc_table *table, - struct clk *pll_c, struct clk *pll_m, struct emc_sel *emc_clk_sel) -{ - u32 div_value = (table->src_sel_reg & EMC_CLK_DIV_MASK) >> - EMC_CLK_DIV_SHIFT; - u32 src_value = (table->src_sel_reg & EMC_CLK_SOURCE_MASK) >> - EMC_CLK_SOURCE_SHIFT; - unsigned long input_rate = 0; - unsigned long table_rate = table->rate * 1000; /* table rate in kHz */ - const struct clk_mux_sel *sel = get_emc_input(src_value); - -#ifdef CONFIG_TEGRA_PLLM_SCALED - struct clk *scalable_pll = pll_m; -#else - struct clk *scalable_pll = pll_c; -#endif - pr_info_once("tegra: %s is selected as scalable EMC clock source\n", - scalable_pll->name); - - if (div_value & 0x1) { - pr_warn("tegra: invalid odd divider for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - if (!sel->input) { - pr_warn("tegra: no matching input found for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - if (div_value && (table->src_sel_reg & EMC_CLK_LOW_JITTER_ENABLE)) { - pr_warn("tegra: invalid LJ path for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - if (!(table->src_sel_reg & EMC_CLK_MC_SAME_FREQ) != - !(MC_EMEM_ARB_MISC0_EMC_SAME_FREQ & - table->burst_regs[MC_EMEM_ARB_MISC0_INDEX])) { - pr_warn("tegra: ambiguous EMC to MC ratio for EMC rate %lu\n", - table_rate); - return -EINVAL; - } - -#ifndef CONFIG_TEGRA_DUAL_CBUS - if (sel->input == pll_c) { - pr_warn("tegra: %s is cbus source: no EMC rate %lu support\n", - sel->input->name, table_rate); - return -EINVAL; - } -#endif - - if (sel->input == scalable_pll) { - input_rate = table_rate * (1 + div_value / 2); - } else { - /* all other sources are fixed, must exactly match the rate */ - input_rate = clk_get_rate(sel->input); - if (input_rate != (table_rate * (1 + div_value / 2))) { - pr_warn("tegra: EMC rate %lu does not match %s rate %lu\n", - table_rate, sel->input->name, input_rate); - return -EINVAL; - } - } - -#ifdef CONFIG_TEGRA_PLLM_SCALED - if (sel->input == pll_c) { - /* maybe overwritten in a loop - end up at max rate - from pll_c */ - emc->shared_bus_backup.input = pll_c; - emc->shared_bus_backup.bus_rate = table_rate; - } -#endif - /* Get ready emc clock selection settings for this table rate */ - emc_clk_sel->input = sel->input; - emc_clk_sel->input_rate = input_rate; - emc_clk_sel->value = table->src_sel_reg; - - return 0; -} - -static void adjust_emc_dvfs_table(const struct tegra14_emc_table *table, - int table_size) -{ - int i, j; - unsigned long rate; - - for (i = 0; i < MAX_DVFS_FREQS; i++) { - int mv = emc->dvfs->millivolts[i]; - if (!mv) - break; - - /* For each dvfs voltage find maximum supported rate; - use 1MHz placeholder if not found */ - for (rate = 1000, j = 0; j < table_size; j++) { - if (tegra_emc_clk_sel[j].input == NULL) - continue; /* invalid entry */ - - if ((mv >= table[j].emc_min_mv) && - (rate < table[j].rate)) - rate = table[j].rate; - } - /* Table entries specify rate in kHz */ - emc->dvfs->freqs[i] = rate * 1000; - } -} - -#ifdef CONFIG_TEGRA_PLLM_SCALED -/* When pll_m is scaled, pll_c must provide backup rate; - if not - remove rates that require pll_m scaling */ -static int purge_emc_table(unsigned long max_rate) -{ - int i; - int ret = 0; - - if (emc->shared_bus_backup.input) - return ret; - - pr_warn("tegra: selected pll_m scaling option but no backup source:\n"); - pr_warn(" removed not supported entries from the table:\n"); - - /* made all entries with non matching rate invalid */ - for (i = 0; i < tegra_emc_table_size; i++) { - struct emc_sel *sel = &tegra_emc_clk_sel[i]; - if (sel->input) { - if (clk_get_rate(sel->input) != sel->input_rate) { - pr_warn(" EMC rate %lu\n", - tegra_emc_table[i].rate * 1000); - sel->input = NULL; - sel->input_rate = 0; - sel->value = 0; - if (max_rate == tegra_emc_table[i].rate) - ret = -EINVAL; - } - } - } - return ret; -} -#else -/* When pll_m is fixed @ max EMC rate, it always provides backup for pll_c */ -#define purge_emc_table(max_rate) (0) -#endif - -static int init_emc_table(const struct tegra14_emc_table *table, - const struct tegra14_emc_table *table_der, - int table_size) -{ - int i, mv; - u32 reg; - bool max_entry = false; - bool emc_max_dvfs_sel = get_emc_max_dvfs(); - unsigned long boot_rate, max_rate; - struct clk *pll_c = tegra_get_clock_by_name("pll_c"); - struct clk *pll_m = tegra_get_clock_by_name("pll_m"); - - emc_stats.clkchange_count = 0; - spin_lock_init(&emc_stats.spinlock); - emc_stats.last_update = get_jiffies_64(); - emc_stats.last_sel = TEGRA_EMC_TABLE_MAX_SIZE; - - if (dram_type != DRAM_TYPE_LPDDR2) { - pr_err("tegra: not supported DRAM type %u\n", dram_type); - return -ENODATA; - } - - if (!table || !table_size) { - pr_err("tegra: EMC DFS table is empty\n"); - return -ENODATA; - } - - boot_rate = clk_get_rate(emc) / 1000; - max_rate = boot_rate; - - tegra_emc_table_size = min(table_size, TEGRA_EMC_TABLE_MAX_SIZE); - switch (table[0].rev) { - case 0x50: - case 0x51: - pr_err("tegra: invalid EMC DFS table (0x%02x): too old.\n", - table[0].rev); - break; - case 0x52: - start_timing.burst_regs_num = table[0].burst_regs_num; - break; - default: - pr_err("tegra: invalid EMC DFS table: unknown rev 0x%x\n", - table[0].rev); - return -ENODATA; - } - - /* Check that the derated table and non-derated table match. */ - if (WARN(!table_der, "tegra: emc: Missing derated tables!\n")) - return -EINVAL; - for (i = 0; i < tegra_emc_table_size; i++) { - if (table[i].rate != table_der[i].rate || - table[i].rev != table_der[i].rev || - table[i].emc_min_mv != table_der[i].emc_min_mv || - table[i].src_sel_reg != table_der[i].src_sel_reg) { - pr_err("tegra: emc: Derated table mismatch.\n"); - return -EINVAL; - } - } - pr_info("tegra: emc: Derated table is valid.\n"); - - /* Match EMC source/divider settings with table entries */ - for (i = 0; i < tegra_emc_table_size; i++) { - unsigned long table_rate = table[i].rate; - - /* Skip "no-rate" entry, or entry violating ascending order */ - if (!table_rate || - (i && (table_rate <= table[i-1].rate))) - continue; - - BUG_ON(table[i].rev != table[0].rev); - - if (find_matching_input(&table[i], pll_c, pll_m, - &tegra_emc_clk_sel[i])) - continue; - - if (table_rate == boot_rate) - emc_stats.last_sel = i; - - if (emc_max_dvfs_sel) { - /* EMC max rate = max table entry above boot rate */ - if (table_rate >= max_rate) { - max_rate = table_rate; - max_entry = true; - } - } else if (table_rate == max_rate) { - /* EMC max rate = boot rate */ - max_entry = true; - break; - } - } - - /* Validate EMC rate and voltage limits */ - if (!max_entry) { - pr_err("tegra: invalid EMC DFS table: entry for max rate" - " %lu kHz is not found\n", max_rate); - return -ENODATA; - } - - tegra_emc_table = table; - tegra_emc_table_derated = table_der; - - /* - * Purge rates that cannot be reached because table does not specify - * proper backup source. If maximum rate was purged, fall back on boot - * rate as maximum limit. In any case propagate new maximum limit - * down stream to shared users, and check it against nominal voltage. - */ - if (purge_emc_table(max_rate)) - max_rate = boot_rate; - tegra_init_max_rate(emc, max_rate * 1000); - - if (emc->dvfs) { - adjust_emc_dvfs_table(tegra_emc_table, tegra_emc_table_size); - mv = tegra_dvfs_predict_peak_millivolts(emc, max_rate * 1000); - if ((mv <= 0) || (mv > emc->dvfs->max_millivolts)) { - tegra_emc_table = NULL; - pr_err("tegra: invalid EMC DFS table: maximum rate %lu" - " kHz does not match nominal voltage %d\n", - max_rate, emc->dvfs->max_millivolts); - return -ENODATA; - } - } - - pr_info("tegra: validated EMC DFS table\n"); - - /* Configure clock change mode according to dram type */ - reg = emc_readl(EMC_CFG_2) & (~EMC_CFG_2_MODE_MASK); - reg |= ((dram_type == DRAM_TYPE_LPDDR2) ? EMC_CFG_2_PD_MODE : - EMC_CFG_2_SREF_MODE) << EMC_CFG_2_MODE_SHIFT; - emc_writel(reg, EMC_CFG_2); - -#if defined(CONFIG_TEGRA_ERRATA_1252872) - emc_writel(tegra_emc_table->emc_acal_interval, EMC_AUTO_CAL_INTERVAL); - emc_timing_update(); -#endif - return 0; -} - -#ifdef CONFIG_PASR -/* Check if the attached memory device uses LPDDR3 protocol. - * Bit 8 (enable LPDDR3 write preamble toggle) of EMC_FBIO_SPARE is enabled - * for LPDDR3. - */ -static bool tegra14_is_lpddr3(void) -{ - return emc_readl(EMC_FBIO_SPARE) & BIT(8); -} - -static void tegra14_pasr_apply_mask(u16 *mem_reg, void *cookie) -{ - u32 val = 0; - int device = (int)cookie; - - val = TEGRA_EMC_MODE_REG_17 | *mem_reg; - val |= device << TEGRA_EMC_MRW_DEV_SHIFT; - - emc_writel(val, EMC_MRW); - - pr_debug("%s: cookie = %d mem_reg = 0x%04x val = 0x%08x\n", __func__, - (int)cookie, *mem_reg, val); -} - -static int tegra14_pasr_enable(const char *arg, const struct kernel_param *kp) -{ - unsigned int old_pasr_enable; - void *cookie; - u16 mem_reg; - unsigned long device_size; - - if (!tegra14_is_lpddr3()) - return -ENOSYS; - - old_pasr_enable = pasr_enable; - param_set_int(arg, kp); - - if (old_pasr_enable == pasr_enable) - return 0; - - device_size = (mc_readl(TEGRA_MC_EMEM_ADR_CFG_DEV) >> - TEGRA_EMEM_DEV_DEVSIZE_SHIFT) & - TEGRA_EMEM_DEV_DEVSIZE_MASK; - device_size = (4 << device_size) << 20; - - /* Cookie represents the device number to write to MRW register. - * 0x2 to for only dev0, 0x1 for dev1. - */ - if (pasr_enable == 0) { - mem_reg = 0; - - cookie = (void *)(int)TEGRA_EMC_MRW_DEV1; - if (!pasr_register_mask_function(TEGRA_DRAM_BASE, - NULL, cookie)) - tegra14_pasr_apply_mask(&mem_reg, cookie); - cookie = (void *)(int)TEGRA_EMC_MRW_DEV2; - if (!pasr_register_mask_function(TEGRA_DRAM_BASE + device_size, - NULL, cookie)) - tegra14_pasr_apply_mask(&mem_reg, cookie); - } else { - cookie = (void *)(int)2; - pasr_register_mask_function(TEGRA_DRAM_BASE, - &tegra14_pasr_apply_mask, cookie); - - cookie = (void *)(int)1; - pasr_register_mask_function(TEGRA_DRAM_BASE + device_size, - &tegra14_pasr_apply_mask, cookie); - } - - return 0; -} - -static struct kernel_param_ops tegra14_pasr_enable_ops = { - .set = tegra14_pasr_enable, - .get = param_get_int, -}; -module_param_cb(pasr_enable, &tegra14_pasr_enable_ops, &pasr_enable, 0644); -#endif - -static int tegra14_emc_probe(struct platform_device *pdev) -{ - struct tegra14_emc_pdata *pdata; - struct resource *res; - u32 padctrl; - - pasr_enable = 0; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "missing register base\n"); - return -ENOMEM; - } - - pdata = pdev->dev.platform_data; - if (!pdata) { - dev_err(&pdev->dev, "missing platform data\n"); - return -ENODATA; - } - -#if defined(CONFIG_TEGRA_ERRATA_1252872) - padctrl = emc_readl(EMC_XM2CMDPADCTRL); - padctrl &= ~(0x7 << 12); - padctrl &= ~(0x7 << 20); - emc_writel(padctrl, EMC_XM2CMDPADCTRL); -#endif - - return init_emc_table(pdata->tables, pdata->tables_derated, - pdata->num_tables); -} - -static struct platform_driver tegra14_emc_driver = { - .driver = { - .name = "tegra-emc", - .owner = THIS_MODULE, - }, - .probe = tegra14_emc_probe, -}; - -int __init tegra14_emc_init(void) -{ - int ret = platform_driver_register(&tegra14_emc_driver); - if (!ret) { - tegra_emc_iso_usage_table_init(tegra14_emc_iso_usage, - ARRAY_SIZE(tegra14_emc_iso_usage)); - if (emc_enable) { - unsigned long rate = tegra_emc_round_rate_updown( - emc->boot_rate, false); - if (!IS_ERR_VALUE(rate)) - tegra_clk_preset_emc_monitor(rate); - } - } - return ret; -} - -void tegra_emc_timing_invalidate(void) -{ - emc_timing = NULL; -} - -void tegra_emc_dram_type_init(struct clk *c) -{ - emc = c; - - dram_type = (emc_readl(EMC_FBIO_CFG5) & - EMC_CFG5_TYPE_MASK) >> EMC_CFG5_TYPE_SHIFT; - - dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */ -} - -int tegra_emc_get_dram_type(void) -{ - return dram_type; -} - -static int emc_read_mrr(int dev, int addr) -{ - int ret; - u32 val, emc_cfg; - - if (dram_type != DRAM_TYPE_LPDDR2) - return -ENODEV; - - ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, false); - if (ret) - return ret; - - emc_cfg = emc_readl(EMC_CFG); - if (emc_cfg & EMC_CFG_DRAM_ACPD) { - emc_writel(emc_cfg & ~EMC_CFG_DRAM_ACPD, EMC_CFG); - emc_timing_update(); - } - - val = dev ? DRAM_DEV_SEL_1 : DRAM_DEV_SEL_0; - val |= (addr << EMC_MRR_MA_SHIFT) & EMC_MRR_MA_MASK; - emc_writel(val, EMC_MRR); - - ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, true); - if (emc_cfg & EMC_CFG_DRAM_ACPD) { - emc_writel(emc_cfg, EMC_CFG); - emc_timing_update(); - } - if (ret) - return ret; - - val = emc_readl(EMC_MRR) & EMC_MRR_DATA_MASK; - return val; -} - -int tegra_emc_get_dram_temperature(void) -{ - int mr4; - unsigned long flags; - - spin_lock_irqsave(&emc_access_lock, flags); - - mr4 = emc_read_mrr(0, 4); - if (IS_ERR_VALUE(mr4)) { - spin_unlock_irqrestore(&emc_access_lock, flags); - return mr4; - } - spin_unlock_irqrestore(&emc_access_lock, flags); - - mr4 = (mr4 & LPDDR2_MR4_TEMP_MASK) >> LPDDR2_MR4_TEMP_SHIFT; - return mr4; -} - -int tegra_emc_dsr_override(int override) -{ - int i, emc_cfg; - unsigned long flags, rate; - const struct tegra14_emc_table *tbl_timing; - - if (override != TEGRA_EMC_DSR_NORMAL && - override != TEGRA_EMC_DSR_OVERRIDE) - return -EINVAL; - - /* No-op. */ - if (override == dsr_override) - return 0; - - spin_lock_irqsave(&emc_access_lock, flags); - - dsr_override = override; - emc_cfg = emc_readl(EMC_CFG); - - /* - * If override is specified, just turn off DSR. Otherwise follow the - * state specified in the current rate's table entry. However, it is - * possible that we will be booting (warm or cold) with a rate that - * is not in the table. If this is the case, we cannot determine what - * needs to happen so we will simply leave dsr_override set to 0 and - * let the next clock change handle returning DSR state to the table's - * state. - */ - emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; - if (override == TEGRA_EMC_DSR_NORMAL) { - /* Get table entry for current rate if we don't have a valid - rate already. */ - tbl_timing = emc_timing; - if (!tbl_timing) { - /* Without the table, we can't do anything here. */ - if (!tegra_emc_table) { - spin_unlock_irqrestore(&emc_access_lock, flags); - return -EINVAL; - } - rate = clk_get_rate_all_locked(emc) / 1000; - for (i = 0; i < tegra_emc_table_size; i++) { - if (tegra_emc_table[i].rate == rate) { - tbl_timing = &tegra_emc_table[i]; - break; - } - } - } - - if (tbl_timing && tbl_timing->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) - emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; - } - - emc_writel(emc_cfg, EMC_CFG); - emc_timing_update(); - spin_unlock_irqrestore(&emc_access_lock, flags); - return 0; -} - -int tegra_emc_dsr_override_status(void) -{ - return dsr_override; -} - -int tegra_emc_dsr_status(void) -{ - int emc_cfg = emc_readl(EMC_CFG); - - if (emc_cfg & EMC_CFG_DYN_SREF_ENABLE) - return 1; - else - return 0; -} - -int tegra_emc_set_over_temp_state(unsigned long state) -{ - int offset; - unsigned long flags; - - if (dram_type != DRAM_TYPE_LPDDR2 || !emc_timing) - return -ENODEV; - - if (state > DRAM_OVER_TEMP_THROTTLE) - return -EINVAL; - - /* Silently do nothing if there is no state change. */ - if (state == dram_over_temp_state) - return 0; - - /* - * If derating needs to be turned on/off force a clock change. That - * will take care of the refresh as well. In derating is not going to - * be changed then all that is needed is an update to the refresh - * settings. - */ - spin_lock_irqsave(&emc_access_lock, flags); - if (state == DRAM_OVER_TEMP_THROTTLE) { - dram_over_temp_state = state; - offset = emc_timing - tegra_emc_table; - emc_set_clock(emc_timing, &tegra_emc_table_derated[offset], - tegra_emc_clk_sel[offset].value | - EMC_CLK_FORCE_CC_TRIGGER); - emc_timing = &tegra_emc_table_derated[offset]; - } else if (dram_over_temp_state == DRAM_OVER_TEMP_THROTTLE) { - dram_over_temp_state = state; - offset = emc_timing - tegra_emc_table_derated; - emc_set_clock(emc_timing, &tegra_emc_table[offset], - tegra_emc_clk_sel[offset].value | - EMC_CLK_FORCE_CC_TRIGGER); - emc_timing = &tegra_emc_table[offset]; - } else { - set_over_temp_timing(emc_timing, state); - emc_timing_update(); - if (state != DRAM_OVER_TEMP_NONE) - emc_writel(EMC_REF_FORCE_CMD, EMC_REF); - dram_over_temp_state = state; - } - spin_unlock_irqrestore(&emc_access_lock, flags); - - return 0; -} - -#ifdef CONFIG_DEBUG_FS - -static struct dentry *emc_debugfs_root; - -static int emc_stats_show(struct seq_file *s, void *data) -{ - int i; - - emc_last_stats_update(TEGRA_EMC_TABLE_MAX_SIZE); - - seq_printf(s, "%-10s %-10s \n", "rate kHz", "time"); - for (i = 0; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; /* invalid entry */ - - seq_printf(s, "%-10lu %-10llu \n", tegra_emc_table[i].rate, - cputime64_to_clock_t(emc_stats.time_at_clock[i])); - } - seq_printf(s, "%-15s %llu\n", "transitions:", - emc_stats.clkchange_count); - seq_printf(s, "%-15s %llu\n", "time-stamp:", - cputime64_to_clock_t(emc_stats.last_update)); - - return 0; -} - -static int emc_stats_open(struct inode *inode, struct file *file) -{ - return single_open(file, emc_stats_show, inode->i_private); -} - -static const struct file_operations emc_stats_fops = { - .open = emc_stats_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int emc_table_info_show(struct seq_file *s, void *data) -{ - int i; - - seq_printf(s, "Table info:\n"); - seq_printf(s, " Rev: 0x%02x\n", tegra_emc_table->rev); - seq_printf(s, " Table ID: %s\n", tegra_emc_table->table_id); - seq_printf(s, " Possible rates (kHz):\n"); - - for (i = 0; i < tegra_emc_table_size; i++) { - if (tegra_emc_clk_sel[i].input == NULL) - continue; - seq_printf(s, " %lu\n", tegra_emc_table[i].rate); - } - - return 0; -} - -static int emc_table_info_open(struct inode *inode, struct file *file) -{ - return single_open(file, emc_table_info_show, inode->i_private); -} - -static const struct file_operations emc_table_info_fops = { - .open = emc_table_info_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int dram_temperature_get(void *data, u64 *val) -{ - *val = tegra_emc_get_dram_temperature(); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(dram_temperature_fops, dram_temperature_get, - NULL, "%lld\n"); - -static int over_temp_state_get(void *data, u64 *val) -{ - *val = dram_over_temp_state; - return 0; -} -static int over_temp_state_set(void *data, u64 val) -{ - return tegra_emc_set_over_temp_state(val); -} -DEFINE_SIMPLE_ATTRIBUTE(over_temp_state_fops, over_temp_state_get, - over_temp_state_set, "%llu\n"); - -static int efficiency_get(void *data, u64 *val) -{ - *val = tegra_emc_bw_efficiency; - return 0; -} -static int efficiency_set(void *data, u64 val) -{ - tegra_emc_bw_efficiency = (val > 100) ? 100 : val; - if (emc) - tegra_clk_shared_bus_update(emc); - - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(efficiency_fops, efficiency_get, - efficiency_set, "%llu\n"); - -static int dsr_get(void *data, u64 *val) -{ - *val = tegra_emc_dsr_status(); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(dsr_fops, dsr_get, NULL, "%llu\n"); - -static int dsr_override_set(void *data, u64 val) -{ - if (val) - tegra_emc_dsr_override(TEGRA_EMC_DSR_OVERRIDE); - else - tegra_emc_dsr_override(TEGRA_EMC_DSR_NORMAL); - - return 0; -} - -static int dsr_override_get(void *data, u64 *val) -{ - *val = tegra_emc_dsr_override_status(); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(dsr_override_fops, dsr_override_get, - dsr_override_set, "%llu\n"); - -static int __init tegra_emc_debug_init(void) -{ - if (!tegra_emc_table) - return 0; - - emc_debugfs_root = debugfs_create_dir("tegra_emc", NULL); - if (!emc_debugfs_root) - return -ENOMEM; - - if (!debugfs_create_file( - "stats", S_IRUGO, emc_debugfs_root, NULL, &emc_stats_fops)) - goto err_out; - - if (!debugfs_create_u32("clkchange_delay", S_IRUGO | S_IWUSR, - emc_debugfs_root, (u32 *)&clkchange_delay)) - goto err_out; - - if (!debugfs_create_file("dram_temperature", S_IRUGO, emc_debugfs_root, - NULL, &dram_temperature_fops)) - goto err_out; - - if (!debugfs_create_file("over_temp_state", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &over_temp_state_fops)) - goto err_out; - - if (!debugfs_create_file("efficiency", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &efficiency_fops)) - goto err_out; - - if (!debugfs_create_file("dsr", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &dsr_fops)) - goto err_out; - - if (!debugfs_create_file("dsr_override", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &dsr_override_fops)) - goto err_out; - - if (!debugfs_create_file("table_info", S_IRUGO | S_IWUSR, - emc_debugfs_root, NULL, &emc_table_info_fops)) - goto err_out; - - if (tegra_emc_iso_usage_debugfs_init(emc_debugfs_root)) - goto err_out; - - return 0; - -err_out: - debugfs_remove_recursive(emc_debugfs_root); - return -ENOMEM; -} - -late_initcall(tegra_emc_debug_init); -#endif diff --git a/arch/arm/mach-tegra/tegra14_emc.h b/arch/arm/mach-tegra/tegra14_emc.h deleted file mode 100644 index f23ad94017cd..000000000000 --- a/arch/arm/mach-tegra/tegra14_emc.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14_emc.h - * - * Copyright (c) 2013-2014, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_TEGRA14_EMC_H -#define _MACH_TEGRA_TEGRA14_EMC_H - -#include <mach/tegra_emc.h> - -int tegra14_emc_init(void); -extern u32 notrace tegra_read_usec_raw(void); - -enum { - DRAM_DEV_SEL_ALL = 0, - DRAM_DEV_SEL_0 = (2 << 30), - DRAM_DEV_SEL_1 = (1 << 30), -}; -#define DRAM_BROADCAST(num) \ - (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) - -#define EMC_INTSTATUS 0x0 -#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4) -#define EMC_INTSTATUS_DLL_LOCK_TIMEOUT_INT (0x1 << 9) - -#define EMC_DBG 0x8 -#define EMC_DBG_WRITE_MUX_ACTIVE (0x1 << 1) - -#define EMC_CFG 0xc -#define EMC_CFG_DRAM_ACPD (0x1 << 29) -#define EMC_CFG_DYN_SREF_ENABLE (0x1 << 28) -#define EMC_CFG_PWR_MASK (0xF << 28) -#define EMC_CFG_MAN_PRE_WR (0x1 << 23) -#define EMC_CFG_MAN_PRE_RD (0x1 << 22) -#define EMC_CFG_PERIODIC_QRST (0x1 << 21) -#define EMC_CFG_EN_DYNAMIC_PUTERM (0x1 << 20) -#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (0x1 << 19) -#define EMC_CFG_DSR_VTTGEN_DRV_EN (0x1 << 18) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE3 (0x1 << 7) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (0x1 << 1) -#define EMC_CFG_UPDATE_MASK \ - (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE | \ - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 | \ - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 | \ - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE3 | \ - EMC_CFG_DSR_VTTGEN_DRV_EN | \ - EMC_CFG_DLY_WR_DQ_HALF_CLOCK | \ - EMC_CFG_EN_DYNAMIC_PUTERM | \ - EMC_CFG_PERIODIC_QRST | \ - EMC_CFG_DRAM_ACPD) - -#define EMC_ADR_CFG 0x10 -#define EMC_REFCTRL 0x20 -#define EMC_REFCTRL_DEV_SEL_SHIFT 0 -#define EMC_REFCTRL_DEV_SEL_MASK \ - (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT) -#define EMC_REFCTRL_ENABLE (0x1 << 31) -#define EMC_REFCTRL_ENABLE_ALL(num) \ - (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \ - | EMC_REFCTRL_ENABLE) -#define EMC_REFCTRL_DISABLE_ALL(num) \ - ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) - -#define EMC_TIMING_CONTROL 0x28 -#define EMC_RC 0x2c -#define EMC_RFC 0x30 -#define EMC_RAS 0x34 -#define EMC_RP 0x38 -#define EMC_R2W 0x3c -#define EMC_W2R 0x40 -#define EMC_R2P 0x44 -#define EMC_W2P 0x48 -#define EMC_RD_RCD 0x4c -#define EMC_WR_RCD 0x50 -#define EMC_RRD 0x54 -#define EMC_REXT 0x58 -#define EMC_WDV 0x5c -#define EMC_QUSE 0x60 -#define EMC_QRST 0x64 -#define EMC_QSAFE 0x68 -#define EMC_RDV 0x6c -#define EMC_REFRESH 0x70 -#define EMC_BURST_REFRESH_NUM 0x74 -#define EMC_PDEX2WR 0x78 -#define EMC_PDEX2RD 0x7c -#define EMC_PCHG2PDEN 0x80 -#define EMC_ACT2PDEN 0x84 -#define EMC_AR2PDEN 0x88 -#define EMC_RW2PDEN 0x8c -#define EMC_TXSR 0x90 -#define EMC_TCKE 0x94 -#define EMC_TFAW 0x98 -#define EMC_TRPAB 0x9c -#define EMC_TCLKSTABLE 0xa0 -#define EMC_TCLKSTOP 0xa4 -#define EMC_TREFBW 0xa8 -#define EMC_ODT_WRITE 0xb0 -#define EMC_ODT_READ 0xb4 -#define EMC_WEXT 0xb8 -#define EMC_CTT 0xbc -#define EMC_RFC_SLR 0xc0 -#define EMC_MRS_WAIT_CNT2 0xc4 - -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) -#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 -#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) - -#define EMC_MRS 0xcc -#define EMC_MODE_SET_DLL_RESET (0x1 << 8) -#define EMC_MODE_SET_LONG_CNT (0x1 << 26) -#define EMC_EMRS 0xd0 -#define EMC_REF 0xd4 -#define EMC_REF_FORCE_CMD 1 -#define EMC_PRE 0xd8 -#define EMC_NOP 0xdc - -#define EMC_SELF_REF 0xe0 -#define EMC_SELF_REF_CMD_ENABLED (0x1 << 0) -#define EMC_SELF_REF_DEV_SEL_SHIFT 30 -#define EMC_SELF_REF_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) - -#define EMC_DPD 0xe4 -#define EMC_MRW 0xe8 - -#define EMC_MRR 0xec -#define EMC_MRR_DEV_SEL_SHIFT 30 -#define EMC_MRR_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_MRR_MA_SHIFT 16 -#define EMC_MRR_MA_MASK (0xFF << EMC_MRR_MA_SHIFT) -#define EMC_MRR_DATA_MASK ((0x1 << EMC_MRR_MA_SHIFT) - 1) -#define LPDDR2_MR4_TEMP_SHIFT 0 -#define LPDDR2_MR4_TEMP_MASK (0x7 << LPDDR2_MR4_TEMP_SHIFT) - -#define EMC_CMDQ 0xf0 -#define EMC_MC2EMCQ 0xf4 -#define EMC_XM2DQSPADCTRL3 0xf8 -#define EMC_XM2DQSPADCTRL3_VREF_ENABLE (0x1 << 5) -#define EMC_FBIO_SPARE 0x100 - -#define EMC_FBIO_CFG5 0x104 -#define EMC_CFG5_TYPE_SHIFT 0x0 -#define EMC_CFG5_TYPE_MASK (0x3 << EMC_CFG5_TYPE_SHIFT) -enum { - DRAM_TYPE_DDR3 = 0, - DRAM_TYPE_LPDDR2 = 2, -}; -#define EMC_CFG5_QUSE_MODE_SHIFT 13 -#define EMC_CFG5_QUSE_MODE_MASK \ - (0x7 << EMC_CFG5_QUSE_MODE_SHIFT) -enum { - EMC_CFG5_QUSE_MODE_NORMAL = 0, - EMC_CFG5_QUSE_MODE_ALWAYS_ON, - EMC_CFG5_QUSE_MODE_INTERNAL_LPBK, - EMC_CFG5_QUSE_MODE_PULSE_INTERN, - EMC_CFG5_QUSE_MODE_PULSE_EXTERN, - EMC_CFG5_QUSE_MODE_DIRECT_QUSE, -}; - -#define EMC_FBIO_WRPTR_EQ_2 0x108 -#define EMC_FBIO_CFG6 0x114 -#define EMC_FBIO_CFG7 0x11c -#define EMC_CFG_RSV 0x120 -#define EMC_ACPD_CONTROL 0x124 -#define EMC_EMRS2 0x12c -#define EMC_EMRS3 0x130 -#define EMC_MRW2 0x134 -#define EMC_MRW3 0x138 -#define EMC_MRW4 0x13c -#define EMC_CLKEN_OVERRIDE 0x140 -#define EMC_R2R 0x144 -#define EMC_W2W 0x148 -#define EMC_EINPUT 0x14c -#define EMC_EINPUT_DURATION 0x150 -#define EMC_PUTERM 0x154 -#define EMC_TCKESR 0x158 -#define EMC_TPD 0x15c - -#define EMC_AUTO_CAL_CONFIG 0x2a4 -#define EMC_AUTO_CAL_INTERVAL 0x2a8 -#define EMC_AUTO_CAL_STATUS 0x2ac -#define EMC_AUTO_CAL_STATUS_ACTIVE (0x1 << 31) -#define EMC_REQ_CTRL 0x2b0 -#define EMC_STATUS 0x2b4 -#define EMC_STATUS_TIMING_UPDATE_STALLED (0x1 << 23) -#define EMC_STATUS_MRR_DIVLD (0x1 << 20) - -#define EMC_CFG_2 0x2b8 -#define EMC_CFG_2_MODE_SHIFT 0 -#define EMC_CFG_2_MODE_MASK (0x3 << EMC_CFG_2_MODE_SHIFT) -#define EMC_CFG_2_SREF_MODE 0x1 -#define EMC_CFG_2_PD_MODE 0x3 - -#define EMC_CFG_DIG_DLL 0x2bc -#define EMC_CFG_DIG_DLL_EN (0x1 << 0) -#define EMC_CFG_DIG_DLL_OVERRIDE_EN (0x1 << 2) -#define EMC_CFG_DIG_DLL_STALL_ALL_TRAFFIC (0x1 << 3) -#define EMC_CFG_DIG_DLL_STALL_RW_UNTIL_LOCK (0x1 << 4) -#define EMC_CFG_DIG_DLL_RESET (0x1 << 30) -#define EMC_CFG_DIG_DLL_MODE_SHIFT 0x6 -#define EMC_CFG_DIG_DLL_MODE_MASK 0x3 -#define EMC_CFG_DIG_DLL_UDSET_SHIFT 0x8 -#define EMC_CFG_DIG_DLL_UDSET_MASK 0xf -#define EMC_CFG_DIG_DLL_OVERRIDE_VAL_SHIFT 0x10 -#define EMC_CFG_DIG_DLL_OVERRIDE_VAL_MASK 0x3ff -#define EMC_CFG_DIG_DLL_LOCK_LIMIT_SHIFT 0x1c /* 28 */ -#define EMC_CFG_DIG_DLL_LOCK_LIMIT_MASK 0x3 -#define EMC_CFG_DIG_DLL_USE_OVERRIDE_UNTIL_LOCK (0x1 << 31) - -#define EMC_CFG_DIG_DLL_MODE_RUN_TIL_LOCK 0x1 - -#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 -#define EMC_DIG_DLL_STATUS 0x2c8 -#define EMC_DIG_DLL_STATUS_ALARM (0x1 << 14) -#define EMC_DIG_DLL_STATUS_LOCKED (0x1 << 15) -#define EMC_DIG_DLL_STATUS_OUT 0x3ff -#define EMC_RDV_MASK 0x2cc -#define EMC_WDV_MASK 0x2d0 -#define EMC_CTT_DURATION 0x2d8 -#define EMC_CTT_TERM_CTRL 0x2dc -#define EMC_ZCAL_INTERVAL 0x2e0 -#define EMC_ZCAL_WAIT_CNT 0x2e4 -#define EMC_ZCAL_MRW_CMD 0x2e8 - -#define EMC_ZQ_CAL 0x2ec -#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30 -#define EMC_ZQ_CAL_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_ZQ_CAL_CMD (0x1 << 0) -#define EMC_ZQ_CAL_LONG (0x1 << 4) -#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ - (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) -#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ - (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) - -#define EMC_XM2CMDPADCTRL 0x2f0 -#define EMC_XM2CMDPADCTRL2 0x2f4 -#define EMC_XM2DQSPADCTRL 0x2f8 -#define EMC_XM2DQSPADCTRL2 0x2fc -#define EMC_XM2DQSPADCTRL2_VREF_DQ_ENABLE (0x1 << 5) -#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE (0x1 << 0) -#define EMC_XM2DQPADCTRL 0x300 -#define EMC_XM2DQPADCTRL2 0x304 -#define EMC_XM2CLKPADCTRL 0x308 -#define EMC_XM2COMPPADCTRL 0x30c -#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (0x1 << 10) -#define EMC_XM2VTTGENPADCTRL 0x310 -#define EMC_XM2VTTGENPADCTRL2 0x314 -#define EMC_XM2COMPPADCTRL2 0x318 -#define EMC_EMCPADEN 0x31c -#define EMC_XM2DQSPADCTRL4 0x320 -#define EMC_SCRATCH0 0x324 -#define EMC_DLL_XFORM_DQS0 0x328 -#define EMC_DLL_XFORM_DQS1 0x32c -#define EMC_DLL_XFORM_DQS2 0x330 -#define EMC_DLL_XFORM_DQS3 0x334 -#define EMC_DLL_XFORM_DQS4 0x338 -#define EMC_DLL_XFORM_DQS5 0x33c -#define EMC_DLL_XFORM_DQS6 0x340 -#define EMC_DLL_XFORM_DQS7 0x344 -#define EMC_DLL_XFORM_QUSE0 0x348 -#define EMC_DLL_XFORM_QUSE1 0x34c -#define EMC_DLL_XFORM_QUSE2 0x350 -#define EMC_DLL_XFORM_QUSE3 0x354 -#define EMC_DLL_XFORM_QUSE4 0x358 -#define EMC_DLL_XFORM_QUSE5 0x35c -#define EMC_DLL_XFORM_QUSE6 0x360 -#define EMC_DLL_XFORM_QUSE7 0x364 -#define EMC_DLL_XFORM_DQ0 0x368 -#define EMC_DLL_XFORM_DQ1 0x36c -#define EMC_DLL_XFORM_DQ2 0x370 -#define EMC_DLL_XFORM_DQ3 0x374 -#define EMC_DLI_RX_TRIM0 0x378 -#define EMC_DLI_RX_TRIM1 0x37c -#define EMC_DLI_RX_TRIM2 0x380 -#define EMC_DLI_RX_TRIM3 0x384 -#define EMC_DLI_RX_TRIM4 0x388 -#define EMC_DLI_RX_TRIM5 0x38c -#define EMC_DLI_RX_TRIM6 0x390 -#define EMC_DLI_RX_TRIM7 0x394 -#define EMC_DLI_TX_TRIM0 0x398 -#define EMC_DLI_TX_TRIM1 0x39c -#define EMC_DLI_TX_TRIM2 0x3a0 -#define EMC_DLI_TX_TRIM3 0x3a4 -#define EMC_DLI_TRIM_TXDQS0 0x3a8 -#define EMC_DLI_TRIM_TXDQS1 0x3ac -#define EMC_DLI_TRIM_TXDQS2 0x3b0 -#define EMC_DLI_TRIM_TXDQS3 0x3b4 -#define EMC_DLI_TRIM_TXDQS4 0x3b8 -#define EMC_DLI_TRIM_TXDQS5 0x3bc -#define EMC_DLI_TRIM_TXDQS6 0x3c0 -#define EMC_DLI_TRIM_TXDQS7 0x3c4 -#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc -#define EMC_AUTO_CAL_CLK_STATUS 0x3d4 -#define EMC_SEL_DPD_CTRL 0x3d8 -#define EMC_SEL_DPD_CTRL_DATA_DPD_ENABLE (0x1 << 8) -#define EMC_PRE_REFRESH_REQ_CNT 0x3dc -#define EMC_DYN_SELF_REF_CONTROL 0x3e0 -#define EMC_TXSRDLL 0x3e4 -#define EMC_CCFIFO_ADDR 0x3e8 -#define EMC_CCFIFO_DATA 0x3ec -#define EMC_CCFIFO_STATUS 0x3f0 -#define EMC_CDB_CNTL_2 0x3f8 -#define EMC_XM2CLKPADCTRL2 0x3fc -#define EMC_SWIZZLE_RANK0_BYTE_CFG 0x400 -#define EMC_SWIZZLE_RANK0_BYTE0 0x404 -#define EMC_SWIZZLE_RANK0_BYTE1 0x408 -#define EMC_SWIZZLE_RANK0_BYTE2 0x40c -#define EMC_SWIZZLE_RANK0_BYTE3 0x410 -#define EMC_SWIZZLE_RANK1_BYTE_CFG 0x414 -#define EMC_SWIZZLE_RANK1_BYTE0 0x418 -#define EMC_SWIZZLE_RANK1_BYTE1 0x41c -#define EMC_SWIZZLE_RANK1_BYTE2 0x420 -#define EMC_SWIZZLE_RANK1_BYTE3 0x424 -#define EMC_CA_TRAINING_START 0x428 -#define EMC_CA_TRAINING_BUSY 0x42c -#define EMC_CA_TRAINING_CFG 0x430 -#define EMC_CA_TRAINING_TIMING_CNTL1 0x434 -#define EMC_CA_TRAINING_TIMING_CNTL2 0x438 -#define EMC_CA_TRAINING_CA_LEAD_IN 0x43c -#define EMC_CA_TRAINING_CA 0x440 -#define EMC_CA_TRAINING_CA_LEAD_OUT 0x444 -#define EMC_CA_TRAINING_RESULT1 0x448 -#define EMC_CA_TRAINING_RESULT2 0x44c -#define EMC_CA_TRAINING_RESULT3 0x450 -#define EMC_CA_TRAINING_RESULT4 0x454 -#define EMC_AUTO_CAL_CONFIG2 0x458 -#define EMC_AUTO_CAL_CONFIG3 0x45c -#define EMC_AUTO_CAL_STATUS2 0x460 -#define EMC_XM2CMDPADCTRL3 0x464 -#define EMC_IBDLY 0x468 -#define EMC_DLL_XFORM_ADDR0 0x46c -#define EMC_DLL_XFORM_ADDR1 0x470 -#define EMC_DLL_XFORM_ADDR2 0x474 -#define EMC_DLI_ADDR_TRIM 0x478 -#define EMC_DSR_VTTGEN_DRV 0x47c -#define EMC_TXDSRVTTGEN 0x480 -#define EMC_XM2CMDPADCTRL4 0x484 -#define EMC_PIPE_MACRO_CTL 0x488 -#define EMC_AUTO_CAL_STATUS3 0x48c -#define EMC_QPOP 0x490 -#define EMC_QUSE_WIDTH 0x494 -#define EMC_PUTERM_WIDTH 0x498 -#define EMC_BGBIAS_CTL0 0x49c - -#define MC_EMEM_CFG 0x50 -#define MC_EMEM_ADR_CFG 0x54 -#define MC_EMEM_ADR_CFG_DEV0 0x58 -#define MC_EMEM_ADR_CFG_DEV1 0x5c -#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64 -#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68 -#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c - -#define MC_BBCLL_EARB_CFG 0x80 -#define MC_EMEM_ARB_BBCLL_OVERRIDE 0x8c - -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 -#define MC_EMEM_ARB_TIMING_RCD 0x98 -#define MC_EMEM_ARB_TIMING_RP 0x9c -#define MC_EMEM_ARB_TIMING_RC 0xa0 -#define MC_EMEM_ARB_TIMING_RAS 0xa4 -#define MC_EMEM_ARB_TIMING_FAW 0xa8 -#define MC_EMEM_ARB_TIMING_RRD 0xac -#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 -#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 -#define MC_EMEM_ARB_TIMING_R2R 0xb8 -#define MC_EMEM_ARB_TIMING_W2W 0xbc -#define MC_EMEM_ARB_TIMING_R2W 0xc0 -#define MC_EMEM_ARB_TIMING_W2R 0xc4 -#define MC_EMEM_ARB_DA_TURNS 0xd0 -#define MC_EMEM_ARB_DA_COVERS 0xd4 -#define MC_EMEM_ARB_MISC0 0xd8 -#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ (0x1 << 27) -#define MC_EMEM_ARB_MISC1 0xdc -#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 -#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 -#define MC_EMEM_ARB_OVERRIDE 0xe8 -#define MC_EMEM_ARB_RSV 0xec - -#define MC_BBC_MEM_REGIONS 0xf0 -#define MC_CLKEN_OVERRIDE 0xf4 -#define MC_TIMING_CONTROL_DBG 0xf8 -#define MC_TIMING_CONTROL 0xfc - -#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210 -#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac - -#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 -#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 -#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec -#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 -#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 -#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 -#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc -#define MC_LATENCY_ALLOWANCE_EPP_0 0x300 -#define MC_LATENCY_ALLOWANCE_EPP_1 0x304 -#define MC_LATENCY_ALLOWANCE_G2_0 0x308 -#define MC_LATENCY_ALLOWANCE_G2_1 0x30c -#define MC_LATENCY_ALLOWANCE_HC_0 0x310 -#define MC_LATENCY_ALLOWANCE_HC_1 0x314 -#define MC_LATENCY_ALLOWANCE_HDA_0 0x318 -#define MC_LATENCY_ALLOWANCE_ISP_0 0x31c -#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 -#define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324 -#define MC_LATENCY_ALLOWANCE_MSENC_0 0x328 -#define MC_LATENCY_ALLOWANCE_NV_0 0x334 -#define MC_LATENCY_ALLOWANCE_NV_1 0x338 -#define MC_LATENCY_ALLOWANCE_NV2_0 0x33c -#define MC_LATENCY_ALLOWANCE_NV2_1 0x340 -#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 -#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 -#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c -#define MC_LATENCY_ALLOWANCE_VDE_0 0x354 -#define MC_LATENCY_ALLOWANCE_VDE_1 0x358 -#define MC_LATENCY_ALLOWANCE_VDE_2 0x35c -#define MC_LATENCY_ALLOWANCE_VDE_3 0x360 -#define MC_LATENCY_ALLOWANCE_VI_0 0x364 -#define MC_LATENCY_ALLOWANCE_VI_1 0x368 -#define MC_LATENCY_ALLOWANCE_VI_2 0x36c -#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c -#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 -#define MC_LATENCY_ALLOWANCE_NV_2 0x384 -#define MC_LATENCY_ALLOWANCE_NV_3 0x388 -#define MC_LATENCY_ALLOWANCE_EMUCIF_0 0x38c -#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 -#define MC_LATENCY_ALLOWANCE_BBMCI_0 0x394 - -#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418 -#define MC_VIDEO_PROTECT_BOM 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c -#define MC_VIDEO_PROTECT_REG_CTRL 0x650 - -#define MC_SEC_CARVEOUT_BOM 0x670 -#define MC_SEC_CARVEOUT_SIZE_MB 0x674 -#define MC_SEC_CARVEOUT_REG_CTRL 0x678 - -#define MC_PTSA_GRANT_DECREMENT 0x960 - -#define MC_RESERVED_RSV 0x3fc -#define MC_RESERVED_RSV_1 0x958 - -#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c -#define MC_EMEM_ARB_OVERRIDE_1 0x968 - -#endif diff --git a/arch/arm/mach-tegra/tegra14_speedo.c b/arch/arm/mach-tegra/tegra14_speedo.c deleted file mode 100644 index f40e19ea9008..000000000000 --- a/arch/arm/mach-tegra/tegra14_speedo.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14_speedo.c - * - * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/bug.h> - -#include <linux/tegra-soc.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/tegra-fuse.h> - -#include "iomap.h" -#include "common.h" - -#define CPU_PROCESS_CORNERS_NUM 2 -#define CORE_PROCESS_CORNERS_NUM 2 -#define CPU_IDDQ_BITS 13 - -#define TEGRA148_CPU_SPEEDO 2109 -#define FUSE_CPU_IDDQ 0x118 /*FIXME: update T148 register*/ -#define FUSE_CPU_SPEEDO_0 0x114 -#define FUSE_CORE_SPEEDO_0 0x134 -#define FUSE_SPARE_BIT_62_0 0x398 -static int threshold_index; -static int cpu_process_id; -static int core_process_id; -static int cpu_speedo_id; -static int cpu_speedo_value; -static int soc_speedo_id; -static int package_id; -static int cpu_iddq_value; -static int core_speedo_value; - -static int enable_app_profiles; - -static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { -/* proc_id 0, 1 */ - {2070, UINT_MAX}, /* [0]: threshold_index 0 */ - {0, UINT_MAX}, /* [1]: threshold_index 1 */ -}; - -static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { -/* proc_id 0, 1 */ - {1295, UINT_MAX}, /* [0]: threshold_index 0 */ - {0, UINT_MAX}, /* [1]: threshold_index 0 */ -}; - -static void rev_sku_to_speedo_ids(int rev, int sku) -{ - - switch (sku) { - case 0x00: /* Eng */ - case 0x07: - cpu_speedo_id = 0; - soc_speedo_id = 0; - threshold_index = 0; - break; - - case 0x03: - case 0x83: - cpu_speedo_id = 1; - soc_speedo_id = 1; - threshold_index = 1; - break; - - default: - pr_err("Tegra14 Unknown SKU %d\n", sku); - cpu_speedo_id = 0; - soc_speedo_id = 0; - threshold_index = 0; - break; - } -} - -void tegra_init_speedo_data(void) -{ - int i; - - cpu_speedo_value = 1024 + tegra_fuse_readl(FUSE_CPU_SPEEDO_0); - core_speedo_value = tegra_fuse_readl(FUSE_CORE_SPEEDO_0); - - rev_sku_to_speedo_ids(tegra_revision, tegra_get_sku_id()); - - for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) { - if (cpu_speedo_value < - cpu_process_speedos[threshold_index][i]) { - break; - } - } - cpu_process_id = i; - - cpu_iddq_value = 0; - for (i = 0; i < CPU_IDDQ_BITS; i++) { - cpu_iddq_value = (cpu_iddq_value << 1) + - tegra_fuse_readl(FUSE_SPARE_BIT_62_0 - 4*i); - } - - if (!cpu_iddq_value) - cpu_iddq_value = tegra_fuse_readl(FUSE_CPU_IDDQ); - - - for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) { - if (core_speedo_value < - core_process_speedos[threshold_index][i]) { - break; - } - } - - core_process_id = i; - - pr_info("Tegra14: CPU Speedo %d, Soc Speedo %d", - cpu_speedo_value, core_speedo_value); - pr_info("Tegra14: CPU Speedo ID %d, Soc Speedo ID %d", - cpu_speedo_id, soc_speedo_id); -} - -int tegra_cpu_process_id(void) -{ - return cpu_process_id; -} - -int tegra_core_process_id(void) -{ - return core_process_id; -} - -int tegra_cpu_speedo_id(void) -{ - return cpu_speedo_id; -} - -int tegra_soc_speedo_id(void) -{ - return soc_speedo_id; -} - -int tegra_package_id(void) -{ - return package_id; -} - -int tegra_cpu_speedo_value(void) -{ - return cpu_speedo_value; -} - -int tegra_core_speedo_value(void) -{ - return core_speedo_value; -} - -/* - * CPU and core nominal voltage levels as determined by chip SKU and speedo - * (not final - can be lowered by dvfs tables and rail dependencies; the - * latter is resolved by the dvfs code) - */ -int tegra_cpu_speedo_mv(void) -{ - /* Not applicable on Tegra148 */ - return -ENOSYS; -} - -int tegra_core_speedo_mv(void) -{ - switch (soc_speedo_id) { - case 0: - case 1: - return 1230; - default: - BUG(); - } -} - -int tegra_get_cpu_iddq_value() -{ - return cpu_iddq_value; -} - -static int get_enable_app_profiles(char *val, const struct kernel_param *kp) -{ - return param_get_uint(val, kp); -} - -static struct kernel_param_ops tegra_profiles_ops = { - .get = get_enable_app_profiles, -}; - -module_param_cb(tegra_enable_app_profiles, - &tegra_profiles_ops, &enable_app_profiles, 0444); diff --git a/arch/arm/mach-tegra/tegra14x_la.c b/arch/arm/mach-tegra/tegra14x_la.c deleted file mode 100644 index f84c9eb7f329..000000000000 --- a/arch/arm/mach-tegra/tegra14x_la.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra14x_la.c - * - * Copyright (C) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/stringify.h> -#include <linux/clk.h> -#include <linux/clk/tegra.h> -#include <linux/tegra-soc.h> -#include <asm/io.h> -#include <mach/latency_allowance.h> - -#include "iomap.h" -#include "la_priv.h" - -#define T14X_MC_LA_AVPC_ARM7_0 0x2e4 -#define T14X_MC_LA_DC_0 0x2e8 -#define T14X_MC_LA_DC_1 0x2ec -#define T14X_MC_LA_DC_2 0x2f0 -#define T14X_MC_LA_DCB_0 0x2f4 -#define T14X_MC_LA_DCB_1 0x2f8 -#define T14X_MC_LA_DCB_2 0x2fc -#define T14X_MC_LA_EPP_0 0x300 -#define T14X_MC_LA_EPP_1 0x304 -#define T14X_MC_LA_G2_0 0x308 -#define T14X_MC_LA_G2_1 0x30c -#define T14X_MC_LA_HC_0 0x310 -#define T14X_MC_LA_HC_1 0x314 -#define T14X_MC_LA_HDA_0 0x318 -#define T14X_MC_LA_ISP_0 0x31C -#define T14X_MC_LA_MPCORE_0 0x320 -#define T14X_MC_LA_MPCORELP_0 0x324 -#define T14X_MC_LA_MSENC_0 0x328 -#define T14X_MC_LA_NV_0 0x334 -#define T14X_MC_LA_NV_1 0x338 -#define T14X_MC_LA_NV2_0 0x33c -#define T14X_MC_LA_NV2_1 0x340 -#define T14X_MC_LA_PPCS_0 0x344 -#define T14X_MC_LA_PPCS_1 0x348 -#define T14X_MC_LA_PTC_0 0x34c - -#define T14X_MC_LA_VDE_0 0x354 -#define T14X_MC_LA_VDE_1 0x358 -#define T14X_MC_LA_VDE_2 0x35c -#define T14X_MC_LA_VDE_3 0x360 -#define T14X_MC_LA_VI_0 0x364 -#define T14X_MC_LA_VI_1 0x368 -#define T14X_MC_LA_VI_2 0x36c -#define T14X_MC_LA_ISP2_0 0x370 /* T14x specific*/ -#define T14X_MC_LA_ISP2_1 0x374 /* T14x specific*/ - -#define T14X_MC_LA_EMUCIF_0 0x38c -#define T14X_MC_LA_TSEC_0 0x390 - -#define T14X_MC_LA_BBMCI_0 0x394 /* T14x specific*/ -#define T14X_MC_LA_BBMCILL_0 0x398 /* T14x specific*/ -#define T14X_MC_LA_DC_3 0x39c /* T14x specific*/ - -#define T14X_MC_DIS_PTSA_RATE_0 0x41c -#define T14X_MC_DIS_PTSA_MIN_0 0x420 -#define T14X_MC_DIS_PTSA_MAX_0 0x424 -#define T14X_MC_DISB_PTSA_RATE_0 0x428 -#define T14X_MC_DISB_PTSA_MIN_0 0x42c -#define T14X_MC_DISB_PTSA_MAX_0 0x430 -#define T14X_MC_VE_PTSA_RATE_0 0x434 -#define T14X_MC_VE_PTSA_MIN_0 0x438 -#define T14X_MC_VE_PTSA_MAX_0 0x43c -#define T14X_MC_RING2_PTSA_RATE_0 0x440 -#define T14X_MC_RING2_PTSA_MIN_0 0x444 -#define T14X_MC_RING2_PTSA_MAX_0 0x448 -#define T14X_MC_MLL_MPCORER_PTSA_RATE_0 0x44c -#define T14X_MC_MLL_MPCORER_PTSA_MIN_0 0x450 -#define T14X_MC_MLL_MPCORER_PTSA_MAX_0 0x454 -#define T14X_MC_SMMU_SMMU_PTSA_RATE_0 0x458 -#define T14X_MC_SMMU_SMMU_PTSA_MIN_0 0x45c -#define T14X_MC_SMMU_SMMU_PTSA_MAX_0 0x460 -#define T14X_MC_R0_DIS_PTSA_RATE_0 0x464 -#define T14X_MC_R0_DIS_PTSA_MIN_0 0x468 -#define T14X_MC_R0_DIS_PTSA_MAX_0 0x46c -#define T14X_MC_R0_DISB_PTSA_RATE_0 0x470 -#define T14X_MC_R0_DISB_PTSA_MIN_0 0x474 -#define T14X_MC_R0_DISB_PTSA_MAX_0 0x478 -#define T14X_MC_RING1_PTSA_RATE_0 0x47c -#define T14X_MC_RING1_PTSA_MIN_0 0x480 -#define T14X_MC_RING1_PTSA_MAX_0 0x484 - -#define T14X_MC_BBC_PTSA_RATE_0 0x4d0 -#define T14X_MC_BBC_PTSA_MIN_0 0x4d4 -#define T14X_MC_BBC_PTSA_MAX_0 0x4d8 - -#define T14X_MC_SCALED_LA_DISPLAY0A_0 0x690 -#define T14X_MC_SCALED_LA_DISPLAY0B_0 0x698 -#define T14X_MC_SCALED_LA_DISPLAY0BB_0 0x69c -#define T14X_MC_SCALED_LA_DISPLAY0C_0 0x6a0 - - -#define T14X_MC_DIS_EXTRA_SNAP_LEVELS_0 0x2ac -#define T14X_MC_HEG_EXTRA_SNAP_LEVELS_0 0x2b0 -#define T14X_MC_EMEM_ARB_MISC0_0 0x0d8 -#define T14X_MC_TIMING_CONTROL_0 0xfc -#define T14X_MC_PTSA_GRANT_DECREMENT_0 0x960 - -#define T14X_MC_BBCLL_EARB_CFG_0 0x080 - -#define T14X_BASE_EMC_FREQ_MHZ 800 -#define T14X_MAX_CAMERA_BW_MHZ 528 -#define T14X_MAX_BBCDMA_BW_MHZ 1200 -#define T14X_MAX_BBCLL_BW_MHZ 640 - -/* maximum valid value for latency allowance */ -#define T14X_MC_LA_MAX_VALUE 255 - -#define T14X_MC_RA(r) \ - (IO_ADDRESS(TEGRA_MC_BASE) + (T14X_MC_##r)) -#define T14X_RA(r) \ - (IO_ADDRESS(TEGRA_MC_BASE) + (T14X_MC_LA_##r)) - -#define T14X_LA(f, e, a, r, i, ss, la) \ -{ \ - .fifo_size_in_atoms = f, \ - .expiration_in_ns = e, \ - .reg_addr = T14X_RA(a), \ - .mask = MASK(r), \ - .shift = SHIFT(r), \ - .id = ID(i), \ - .name = __stringify(i), \ - .scaling_supported = ss, \ - .init_la = la, \ -} - -/* - * The consensus for getting the fifo_size_in_atoms is: - * 1.If REORDER_DEPTH exists, use it(default is overridden). - * 2.Else if (write_client) use RFIFO_DEPTH. - * 3.Else (read client) use RDFIFO_DEPTH. - * Multiply the value by 2 for dual channel. - * Multiply the value by 2 for wide clients. - * A client is wide, if CMW is larger than MW. - * Refer to project.h file. - */ -struct la_client_info t14x_la_info_array[] = { - T14X_LA(4, 150, AVPC_ARM7_0, 7 : 0, AVPC_ARM7R, false, 0), - T14X_LA(8, 150, AVPC_ARM7_0, 23 : 16, AVPC_ARM7W, false, 0), - T14X_LA(128, 1050, DC_0, 7 : 0, DISPLAY_0A, true, 0), - T14X_LA(128, 1050, DC_0, 23 : 16, DISPLAY_0B, true, 0), - T14X_LA(128, 1050, DC_1, 7 : 0, DISPLAY_0C, true, 0), - T14X_LA(192, 1050, DC_2, 7 : 0, DISPLAY_HC, false, 0), - T14X_LA(128, 1920, DCB_0, 7 : 0, DISPLAY_0AB, true, 0), - T14X_LA(128, 1050, DCB_0, 23 : 16, DISPLAY_0BB, true, 0), - T14X_LA(128, 1920, DCB_1, 7 : 0, DISPLAY_0CB, true, 0), - T14X_LA(192, 1050, DCB_2, 7 : 0, DISPLAY_HCB, false, 0), - T14X_LA(192, 1920, DC_2, 23 : 16, DISPLAY_T, false, 0), - T14X_LA(192, 1920, DC_3, 7 : 0, DISPLAYD, false, 0), - T14X_LA(32, 150, EPP_0, 7 : 0, EPPUP, false, 0), - T14X_LA(32, 150, EPP_0, 23 : 16, EPPU, false, 0), - T14X_LA(32, 150, EPP_1, 7 : 0, EPPV, false, 0), - T14X_LA(32, 150, EPP_1, 23 : 16, EPPY, false, 0), - T14X_LA(128, 150, G2_0, 7 : 0, G2PR, false, 35), - T14X_LA(128, 150, G2_0, 23 : 16, G2SR, false, 21), - T14X_LA(72, 150, G2_1, 7 : 0, G2DR, false, 24), - T14X_LA(128, 150, G2_1, 23 : 16, G2DW, false, 9), - T14X_LA(16, 150, HC_0, 7 : 0, HOST1X_DMAR, false, 0), - T14X_LA(8, 150, HC_0, 23 : 16, HOST1XR, false, 0), - T14X_LA(32, 150, HC_1, 7 : 0, HOST1XW, false, 0), - T14X_LA(64, 150, HDA_0, 7 : 0, HDAR, false, 0), - T14X_LA(64, 150, HDA_0, 23 : 16, HDAW, false, 0), - T14X_LA(64, 150, ISP_0, 7 : 0, ISPW, false, 0), - T14X_LA(40, 150, MPCORE_0, 7 : 0, MPCORER, false, 0), - T14X_LA(42, 150, MPCORE_0, 23 : 16, MPCOREW, false, 0), - T14X_LA(24, 150, MPCORELP_0, 7 : 0, MPCORE_LPR, false, 0), - T14X_LA(24, 150, MPCORELP_0, 23 : 16, MPCORE_LPW, false, 0), - T14X_LA(160, 150, NV_0, 7 : 0, FDCDRD, false, 30), - T14X_LA(256, 150, NV_0, 23 : 16, IDXSRD, false, 23), - T14X_LA(256, 150, NV_1, 7 : 0, TEXL2SRD, false, 23), - T14X_LA(128, 150, NV_1, 23 : 16, FDCDWR, false, 23), - T14X_LA(160, 150, NV2_0, 7 : 0, FDCDRD2, false, 30), - T14X_LA(128, 150, NV2_1, 7 : 0, FDCDWR2, false, 23), - T14X_LA(4, 150, PPCS_0, 7 : 0, PPCS_AHBDMAR, false, 0), - T14X_LA(29, 150, PPCS_0, 23 : 16, PPCS_AHBSLVR, false, 0), - T14X_LA(8, 150, PPCS_1, 7 : 0, PPCS_AHBDMAW, false, 0), - T14X_LA(8, 150, PPCS_1, 23 : 16, PPCS_AHBSLVW, false, 0), - T14X_LA(20, 150, PTC_0, 7 : 0, PTCR, false, 0), - T14X_LA(8, 150, VDE_0, 7 : 0, VDE_BSEVR, false, 28), - T14X_LA(9, 150, VDE_0, 23 : 16, VDE_MBER, false, 59), - T14X_LA(64, 150, VDE_1, 7 : 0, VDE_MCER, false, 27), - T14X_LA(32, 150, VDE_1, 23 : 16, VDE_TPER, false, 110), - T14X_LA(4, 150, VDE_2, 7 : 0, VDE_BSEVW, false, 255), - T14X_LA(4, 150, VDE_2, 23 : 16, VDE_DBGW, false, 255), - T14X_LA(8, 150, VDE_3, 7 : 0, VDE_MBEW, false, 132), - T14X_LA(32, 150, VDE_3, 23 : 16, VDE_TPMW, false, 38), - T14X_LA(200, 1050, VI_0, 7 : 0, VI_WSB, true, 0), - T14X_LA(200, 1050, VI_1, 7 : 0, VI_WU, true, 0), - T14X_LA(200, 1050, VI_1, 23 : 16, VI_WV, true, 0), - T14X_LA(200, 1050, VI_2, 7 : 0, VI_WY, true, 0), - - T14X_LA(64, 150, MSENC_0,7 : 0, MSENCSRD, false, 50), - T14X_LA(16, 150, MSENC_0,23 : 16, MSENCSWR, false, 37), - T14X_LA(14, 150, EMUCIF_0,7 : 0, EMUCIFR, false, 0), - T14X_LA(24, 150, EMUCIF_0,23 : 16, EMUCIFW, false, 0), - T14X_LA(32, 150, TSEC_0, 7 : 0, TSECSRD, false, 0), - T14X_LA(32, 150, TSEC_0, 23 : 16, TSECSWR, false, 0), - - T14X_LA(125, 150, VI_0, 23 : 16, VI_W, false, 0), - T14X_LA(75, 150, ISP2_0, 7 : 0, ISP_RA, false, 0), - T14X_LA(150, 150, ISP2_1, 7 : 0, ISP_WA, false, 0), - T14X_LA(64, 150, ISP2_1, 23 : 16, ISP_WB, false, 0), - T14X_LA(32, 150, BBMCI_0,7 : 0, BBCR, false, 8), - T14X_LA(32, 150, BBMCI_0,23 : 16, BBCW, false, 8), - T14X_LA(16, 150, BBMCILL_0,7 : 0, BBCLLR, false, 1), - -/* end of list. */ - T14X_LA(0, 0, DC_3, 0 : 0, MAX_ID, false, 0) -}; - -static struct la_chip_specific *cs; - -static unsigned int t14x_get_ptsa_rate(unsigned int bw) -{ - // 8 = (1 channels) * (2 ddr) * (4 bytes) - // T148DIFF - T114 code was wrong - hopefully this is right for T148 - unsigned base_memory_bw = 8 * T14X_BASE_EMC_FREQ_MHZ; - // 281 = 256 * 1.1 (1.1 is the extra margin for ISO clients) - unsigned rate = 281 * bw / base_memory_bw; - if (rate > 255) - rate = 255; - return rate; -} - -static void program_ptsa(void) -{ - struct ptsa_info *p = &cs->ptsa_info; - - writel(p->ptsa_grant_dec, T14X_MC_RA(PTSA_GRANT_DECREMENT_0)); - writel(1, T14X_MC_RA(TIMING_CONTROL_0)); - - writel(p->dis_ptsa_rate, T14X_MC_RA(DIS_PTSA_RATE_0)); - writel(p->dis_ptsa_min, T14X_MC_RA(DIS_PTSA_MIN_0)); - writel(p->dis_ptsa_max, T14X_MC_RA(DIS_PTSA_MAX_0)); - - writel(p->disb_ptsa_rate, T14X_MC_RA(DISB_PTSA_RATE_0)); - writel(p->disb_ptsa_min, T14X_MC_RA(DISB_PTSA_MIN_0)); - writel(p->disb_ptsa_max, T14X_MC_RA(DISB_PTSA_MAX_0)); - - writel(p->ve_ptsa_rate, T14X_MC_RA(VE_PTSA_RATE_0)); - writel(p->ve_ptsa_min, T14X_MC_RA(VE_PTSA_MIN_0)); - writel(p->ve_ptsa_max, T14X_MC_RA(VE_PTSA_MAX_0)); - - writel(p->ring2_ptsa_rate, T14X_MC_RA(RING2_PTSA_RATE_0)); - writel(p->ring2_ptsa_min, T14X_MC_RA(RING2_PTSA_MIN_0)); - writel(p->ring2_ptsa_max, T14X_MC_RA(RING2_PTSA_MAX_0)); - - writel(p->bbc_ptsa_rate, T14X_MC_RA(BBC_PTSA_RATE_0)); - writel(p->bbc_ptsa_min, T14X_MC_RA(BBC_PTSA_MIN_0)); - writel(p->bbc_ptsa_max, T14X_MC_RA(BBC_PTSA_MAX_0)); - - writel(p->bbcll_earb_cfg, T14X_MC_RA(BBCLL_EARB_CFG_0)); - - writel(p->mpcorer_ptsa_rate, T14X_MC_RA(MLL_MPCORER_PTSA_RATE_0)); - writel(p->mpcorer_ptsa_min, T14X_MC_RA(MLL_MPCORER_PTSA_MIN_0)); - writel(p->mpcorer_ptsa_max, T14X_MC_RA(MLL_MPCORER_PTSA_MAX_0)); - - writel(p->smmu_ptsa_rate, T14X_MC_RA(SMMU_SMMU_PTSA_RATE_0)); - writel(p->smmu_ptsa_min, T14X_MC_RA(SMMU_SMMU_PTSA_MIN_0)); - writel(p->smmu_ptsa_max, T14X_MC_RA(SMMU_SMMU_PTSA_MAX_0)); - - writel(p->ring1_ptsa_rate, T14X_MC_RA(RING1_PTSA_RATE_0)); - writel(p->ring1_ptsa_min, T14X_MC_RA(RING1_PTSA_MIN_0)); - writel(p->ring1_ptsa_max, T14X_MC_RA(RING1_PTSA_MAX_0)); - - writel(p->dis_extra_snap_level, T14X_MC_RA(DIS_EXTRA_SNAP_LEVELS_0)); - writel(p->heg_extra_snap_level, T14X_MC_RA(HEG_EXTRA_SNAP_LEVELS_0)); -} - -static void save_ptsa(void) -{ - struct ptsa_info *p = &cs->ptsa_info; - - p->ptsa_grant_dec = readl(T14X_MC_RA(PTSA_GRANT_DECREMENT_0)); - - p->dis_ptsa_rate = readl(T14X_MC_RA(DIS_PTSA_RATE_0)); - p->dis_ptsa_min = readl(T14X_MC_RA(DIS_PTSA_MIN_0)); - p->dis_ptsa_max = readl(T14X_MC_RA(DIS_PTSA_MAX_0)); - - p->disb_ptsa_rate = readl(T14X_MC_RA(DISB_PTSA_RATE_0)); - p->disb_ptsa_min = readl(T14X_MC_RA(DISB_PTSA_MIN_0)); - p->disb_ptsa_max = readl(T14X_MC_RA(DISB_PTSA_MAX_0)); - - p->ve_ptsa_rate = readl(T14X_MC_RA(VE_PTSA_RATE_0)); - p->ve_ptsa_min = readl(T14X_MC_RA(VE_PTSA_MIN_0)); - p->ve_ptsa_max = readl(T14X_MC_RA(VE_PTSA_MAX_0)); - - p->ring2_ptsa_rate = readl(T14X_MC_RA(RING2_PTSA_RATE_0)); - p->ring2_ptsa_min = readl(T14X_MC_RA(RING2_PTSA_MIN_0)); - p->ring2_ptsa_max = readl(T14X_MC_RA(RING2_PTSA_MAX_0)); - - p->bbc_ptsa_rate = readl(T14X_MC_RA(BBC_PTSA_RATE_0)); - p->bbc_ptsa_min = readl(T14X_MC_RA(BBC_PTSA_MIN_0)); - p->bbc_ptsa_max = readl(T14X_MC_RA(BBC_PTSA_MAX_0)); - - p->bbcll_earb_cfg = readl(T14X_MC_RA(BBCLL_EARB_CFG_0)); - - p->mpcorer_ptsa_rate = readl(T14X_MC_RA(MLL_MPCORER_PTSA_RATE_0)); - p->mpcorer_ptsa_min = readl(T14X_MC_RA(MLL_MPCORER_PTSA_MIN_0)); - p->mpcorer_ptsa_max = readl(T14X_MC_RA(MLL_MPCORER_PTSA_MAX_0)); - - p->smmu_ptsa_rate = readl(T14X_MC_RA(SMMU_SMMU_PTSA_RATE_0)); - p->smmu_ptsa_min = readl(T14X_MC_RA(SMMU_SMMU_PTSA_MIN_0)); - p->smmu_ptsa_max = readl(T14X_MC_RA(SMMU_SMMU_PTSA_MAX_0)); - - p->ring1_ptsa_rate = readl(T14X_MC_RA(RING1_PTSA_RATE_0)); - p->ring1_ptsa_min = readl(T14X_MC_RA(RING1_PTSA_MIN_0)); - p->ring1_ptsa_max = readl(T14X_MC_RA(RING1_PTSA_MAX_0)); - - p->dis_extra_snap_level = readl(T14X_MC_RA(DIS_EXTRA_SNAP_LEVELS_0)); - p->heg_extra_snap_level = readl(T14X_MC_RA(HEG_EXTRA_SNAP_LEVELS_0)); -} - -static void program_ring1_ptsa(struct ptsa_info *p) -{ - p->ring1_ptsa_rate = p->dis_ptsa_rate + - p->bbc_ptsa_rate; -#if defined(CONFIG_TEGRA_ERRATA_977223) - p->ring1_ptsa_rate /= 2; -#endif - p->ring1_ptsa_rate += p->disb_ptsa_rate + - p->ve_ptsa_rate + - p->ring2_ptsa_rate; - writel(p->ring1_ptsa_rate, T14X_MC_RA(RING1_PTSA_RATE_0)); -} - -static void t14x_init_ptsa(void) -{ - struct ptsa_info *p = &cs->ptsa_info; - struct clk *emc_clk __attribute__((unused)); - unsigned long emc_freq __attribute__((unused)); - unsigned long same_freq __attribute__((unused)); - unsigned long grant_dec __attribute__((unused)); - - emc_clk = clk_get(NULL, "emc"); - la_debug("**** emc clk_rate=%luMHz", clk_get_rate(emc_clk) / 1000000); - - emc_freq = clk_get_rate(emc_clk); - emc_freq /= 1000000; - /* Compute initial value for grant dec */ - same_freq = readl(T14X_MC_RA(EMEM_ARB_MISC0_0)); - same_freq = same_freq >> 27 & 1; - grant_dec = 256 * (same_freq ? 2 : 1) * emc_freq / - T14X_BASE_EMC_FREQ_MHZ; - if (grant_dec > 511) - grant_dec = 511; - - p->dis_ptsa_min = 0x36; - p->dis_ptsa_max = 0x1e; - p->dis_ptsa_rate = readl(T14X_MC_RA(DIS_PTSA_RATE_0)); - - p->disb_ptsa_min = 0x36; - p->disb_ptsa_max = 0x1e; - p->disb_ptsa_rate = readl(T14X_MC_RA(DISB_PTSA_RATE_0)); - - p->ve_ptsa_rate = t14x_get_ptsa_rate(T14X_MAX_CAMERA_BW_MHZ); - p->ve_ptsa_min = 0x3d; - p->ve_ptsa_max = 0x14; - - p->ring2_ptsa_rate = 0x01; - p->ring2_ptsa_min = 0x3f; - p->ring2_ptsa_max = 0x01; - - p->bbc_ptsa_min = 0x3e; - p->bbc_ptsa_max = 0x18; - - p->mpcorer_ptsa_rate = 23 * emc_freq / T14X_BASE_EMC_FREQ_MHZ; - p->mpcorer_ptsa_min = 0x3f; - p->mpcorer_ptsa_max = 0x0b; - - p->smmu_ptsa_rate = 0x1; - p->smmu_ptsa_min = 0x1; - p->smmu_ptsa_max = 0x1; - - p->ring1_ptsa_min = 0x36; - p->ring1_ptsa_max = 0x1f; - - p->dis_extra_snap_level = 0x0; - p->heg_extra_snap_level = 0x2; - p->ptsa_grant_dec = grant_dec; - - p->bbc_ptsa_rate = t14x_get_ptsa_rate(T14X_MAX_BBCDMA_BW_MHZ); - - /* BBC ring0 ptsa max/min/rate/limit */ - p->bbcll_earb_cfg = 0xd << 24 | 0x3f << 16 | - t14x_get_ptsa_rate(T14X_MAX_BBCLL_BW_MHZ) << 8 | 8 << 0; - - program_ring1_ptsa(p); - program_ptsa(); -} - -#define ID_IDX(x) (ID(x) - ID(DISPLAY_0A)) -static void t14x_update_display_ptsa_rate(unsigned int *disp_bw_array) -{ - unsigned int total_dis_bw; - unsigned int total_disb_bw; - struct ptsa_info *p = &cs->ptsa_info; - - if (cs->disable_ptsa || cs->disable_disp_ptsa) - return; - total_dis_bw = disp_bw_array[ID_IDX(DISPLAY_0A)] + - disp_bw_array[ID_IDX(DISPLAY_0B)] + - disp_bw_array[ID_IDX(DISPLAY_0C)] + - disp_bw_array[ID_IDX(DISPLAY_T)] + - disp_bw_array[ID_IDX(DISPLAYD)]; - total_disb_bw = disp_bw_array[ID_IDX(DISPLAY_0AB)] + - disp_bw_array[ID_IDX(DISPLAY_0BB)] + - disp_bw_array[ID_IDX(DISPLAY_0CB)]; - - p->dis_ptsa_rate = t14x_get_ptsa_rate(total_dis_bw); - p->disb_ptsa_rate = t14x_get_ptsa_rate(total_disb_bw); - - writel(p->dis_ptsa_rate, T14X_MC_RA(DIS_PTSA_RATE_0)); - writel(p->disb_ptsa_rate, T14X_MC_RA(DISB_PTSA_RATE_0)); - - program_ring1_ptsa(p); -} - -#define BBC_ID_IDX(x) (ID(x) - ID(BBCR)) -static void t14x_update_bbc_ptsa_rate(uint *bbc_bw_array) -{ - uint total_bbc_bw; - struct ptsa_info *p = &cs->ptsa_info; - - if (cs->disable_ptsa || cs->disable_bbc_ptsa) - return; - - total_bbc_bw = bbc_bw_array[BBC_ID_IDX(BBCR)] + - bbc_bw_array[BBC_ID_IDX(BBCW)]; - p->bbc_ptsa_rate = t14x_get_ptsa_rate(total_bbc_bw); - writel(p->bbc_ptsa_rate, T14X_MC_RA(BBC_PTSA_RATE_0)); - program_ring1_ptsa(p); -} - -static void program_la(struct la_client_info *ci, int la) -{ - unsigned long reg_read; - unsigned long reg_write; - - spin_lock(&cs->lock); - reg_read = readl(ci->reg_addr); - reg_write = (reg_read & ~ci->mask) | - (la << ci->shift); - writel(reg_write, ci->reg_addr); - ci->la_set = la; - la_debug("reg_addr=0x%x, read=0x%x, write=0x%x", - (u32)ci->reg_addr, (u32)reg_read, (u32)reg_write); - - BUG_ON(la > 255); - /* la scaling for display is on in MC always. - * set lo and hi la values to same as normal la. - */ - switch (ci->id) { - case ID(DISPLAY_0A): - writel(la << 16 | la, T14X_MC_RA(SCALED_LA_DISPLAY0A_0)); - break; - case ID(DISPLAY_0B): - writel(la << 16 | la, T14X_MC_RA(SCALED_LA_DISPLAY0B_0)); - break; - case ID(DISPLAY_0C): - writel(la << 16 | la, T14X_MC_RA(SCALED_LA_DISPLAY0C_0)); - break; - case ID(DISPLAY_0BB): - writel(la << 16 | la, T14X_MC_RA(SCALED_LA_DISPLAY0BB_0)); - break; - default: - break; - } - spin_unlock(&cs->lock); -} - -#define DISPLAY_MARGIN 100 /* 100 -> 1.0, 110 -> 1.1 */ -static int t14x_set_la(enum tegra_la_id id, unsigned int bw_mbps) -{ - int ideal_la; - int la_to_set; - unsigned int fifo_size_in_atoms; - int bytes_per_atom = cs->atom_size; - struct la_client_info *ci; - int idx = cs->id_to_index[id]; - - VALIDATE_ID(id, cs); - VALIDATE_BW(bw_mbps); - - ci = &cs->la_info_array[idx]; - fifo_size_in_atoms = ci->fifo_size_in_atoms; - - if (id == TEGRA_LA_BBCR || id == TEGRA_LA_BBCW) { - cs->bbc_bw_array[id - TEGRA_LA_BBCR] = bw_mbps; - t14x_update_bbc_ptsa_rate(cs->bbc_bw_array); -#ifdef CONFIG_TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE - return 0; -#endif - } - - if (id >= TEGRA_LA_DISPLAY_0A && id <= TEGRA_LA_DISPLAYD) { - cs->disp_bw_array[id - TEGRA_LA_DISPLAY_0A] = bw_mbps; - t14x_update_display_ptsa_rate(cs->disp_bw_array); - } - - if (bw_mbps == 0) { - la_to_set = cs->la_max_value; - } else { - if (id >= TEGRA_LA_DISPLAY_0A && id <= TEGRA_LA_DISPLAYD) { - /* display la margin shold be 1.1 */ - ideal_la = (100 * fifo_size_in_atoms * bytes_per_atom * 1000) / - (DISPLAY_MARGIN * bw_mbps * cs->ns_per_tick); - } else { - ideal_la = (fifo_size_in_atoms * bytes_per_atom * 1000) / - (bw_mbps * cs->ns_per_tick); - } - la_to_set = ideal_la - - (ci->expiration_in_ns / cs->ns_per_tick) - 1; - } - - la_debug("\n%s:id=%d,idx=%d, bw=%dmbps, la_to_set=%d", - __func__, id, idx, bw_mbps, la_to_set); - la_to_set = (la_to_set < 0) ? 0 : la_to_set; - la_to_set = (la_to_set > cs->la_max_value) ? cs->la_max_value : la_to_set; - - if (cs->disable_la) - return 0; - program_la(ci, la_to_set); - return 0; -} - -static int t14x_la_suspend(void) -{ - int i = 0; - struct la_client_info *ci; - - /* stashing LA and PTSA from registers is necessary - * in order to get latest values programmed by DVFS. - */ - for (i = 0; i < cs->la_info_array_size; i++) { - ci = &cs->la_info_array[i]; - ci->la_set = (readl(ci->reg_addr) & ci->mask) >> - ci->shift; - } - save_ptsa(); - return 0; -} - -static void t14x_la_resume(void) -{ - int i; - - for (i = 0; i < cs->la_info_array_size; i++) { - if (cs->la_info_array[i].la_set) - program_la(&cs->la_info_array[i], - cs->la_info_array[i].la_set); - } - program_ptsa(); -} - -void tegra_la_get_t14x_specific(struct la_chip_specific *cs_la) -{ - cs_la->ns_per_tick = 30; - cs_la->atom_size = 16; - cs_la->la_max_value = T14X_MC_LA_MAX_VALUE; - cs_la->la_info_array = t14x_la_info_array; - cs_la->la_info_array_size = ARRAY_SIZE(t14x_la_info_array); - cs_la->init_ptsa = t14x_init_ptsa; - cs_la->update_display_ptsa_rate = t14x_update_display_ptsa_rate; - cs_la->set_la = t14x_set_la; - cs_la->suspend = t14x_la_suspend; - cs_la->resume = t14x_la_resume; - cs = cs_la; -} diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/arch/arm/mach-tegra/tegra20_speedo.c index 12e163e2ec2f..9f8890651101 100644 --- a/arch/arm/mach-tegra/tegra20_speedo.c +++ b/arch/arm/mach-tegra/tegra20_speedo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -63,13 +63,11 @@ void tegra20_init_speedo_data(void) u32 reg; u32 val; int i; - u32 tegra_sku_id; BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT); BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT); tegra_package_id = -1; - tegra_sku_id = tegra_get_sku_id(); if (SPEEDO_ID_SELECT_0(tegra_revision)) tegra_soc_speedo_id = SPEEDO_ID_0; diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/arch/arm/mach-tegra/tegra30_speedo.c index fa6f601a7071..125cb16424a6 100644 --- a/arch/arm/mach-tegra/tegra30_speedo.c +++ b/arch/arm/mach-tegra/tegra30_speedo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,16 +16,13 @@ #include <linux/kernel.h> #include <linux/bug.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/tegra-fuse.h> +#include "fuse.h" #define CORE_PROCESS_CORNERS_NUM 1 -#define CPU_PROCESS_CORNERS_NUM 7 +#define CPU_PROCESS_CORNERS_NUM 6 #define FUSE_SPEEDO_CALIB_0 0x114 -#define FUSE_IDDQ_CALIB_0 0x118 #define FUSE_PACKAGE_INFO 0X1FC #define FUSE_TEST_PROG_VER 0X128 @@ -51,9 +48,6 @@ enum { THRESHOLD_INDEX_9, THRESHOLD_INDEX_10, THRESHOLD_INDEX_11, - THRESHOLD_INDEX_12, - THRESHOLD_INDEX_13, - THRESHOLD_INDEX_14, THRESHOLD_INDEX_COUNT, }; @@ -70,9 +64,6 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { {180}, {180}, {180}, - {185}, - {185}, - {210}, }; static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { @@ -88,19 +79,10 @@ static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { {364, 364, 364, 364, 397, UINT_MAX}, {295, 336, 358, 375, 391, UINT_MAX}, {295, 336, 358, 375, 391, UINT_MAX}, - {300, 311, 360, 371, 381, 415, 431}, - {300, 311, 410, 431, UINT_MAX}, - {358, 358, 358, 358, 397, UINT_MAX}, }; static int threshold_index; -static int cpu_iddq_value; - -/* - * Only AP37 supports App Profile - * This informs user space of support without exposing cpu id's - */ -static int enable_app_profiles; +static int package_id; static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp) { @@ -153,7 +135,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) threshold_index = THRESHOLD_INDEX_1; break; case 0x81: - switch (tegra_package_id) { + switch (package_id) { case 1: tegra_cpu_speedo_id = 2; tegra_soc_speedo_id = 2; @@ -165,13 +147,13 @@ static void rev_sku_to_speedo_ids(int rev, int sku) threshold_index = THRESHOLD_INDEX_7; break; default: - pr_err("Tegra30: Unknown pkg %d\n", tegra_package_id); + pr_err("Tegra30: Unknown pkg %d\n", package_id); BUG(); break; } break; case 0x80: - switch (tegra_package_id) { + switch (package_id) { case 1: tegra_cpu_speedo_id = 5; tegra_soc_speedo_id = 2; @@ -183,13 +165,13 @@ static void rev_sku_to_speedo_ids(int rev, int sku) threshold_index = THRESHOLD_INDEX_9; break; default: - pr_err("Tegra30: Unknown pkg %d\n", tegra_package_id); + pr_err("Tegra30: Unknown pkg %d\n", package_id); BUG(); break; } break; case 0x83: - switch (tegra_package_id) { + switch (package_id) { case 1: tegra_cpu_speedo_id = 7; tegra_soc_speedo_id = 1; @@ -201,7 +183,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) threshold_index = THRESHOLD_INDEX_3; break; default: - pr_err("Tegra30: Unknown pkg %d\n", tegra_package_id); + pr_err("Tegra30: Unknown pkg %d\n", package_id); BUG(); break; } @@ -211,26 +193,6 @@ static void rev_sku_to_speedo_ids(int rev, int sku) tegra_soc_speedo_id = 1; threshold_index = THRESHOLD_INDEX_11; break; - case 0xA0: /* T37 or A37 */ - switch (tegra_package_id) { - case 1: /* MID => T37 */ - tegra_cpu_speedo_id = 13; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_14; - break; - case 2: /* DSC => AP37 */ - tegra_cpu_speedo_id = 12; - tegra_soc_speedo_id = 2; - threshold_index = THRESHOLD_INDEX_9; - enable_app_profiles = 1; - break; - default: - pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n", - tegra_package_id); - BUG(); - break; - } - break; case 0x08: tegra_cpu_speedo_id = 1; tegra_soc_speedo_id = 1; @@ -246,20 +208,8 @@ static void rev_sku_to_speedo_ids(int rev, int sku) tegra_soc_speedo_id = 2; threshold_index = THRESHOLD_INDEX_6; break; - case 0x91: /* T30AGS-Ax */ - case 0xb0: /* T30IQS-Ax */ - case 0xb1: /* T30MQS-Ax */ - case 0x90: /* T30AQS-Ax */ - tegra_soc_speedo_id = 3; - threshold_index = THRESHOLD_INDEX_12; - break; - case 0x93: /* T30AG-Ax */ - tegra_cpu_speedo_id = 11; - tegra_soc_speedo_id = 3; - threshold_index = THRESHOLD_INDEX_13; - break; case 0: - switch (tegra_package_id) { + switch (package_id) { case 1: tegra_cpu_speedo_id = 2; tegra_soc_speedo_id = 2; @@ -271,7 +221,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) threshold_index = THRESHOLD_INDEX_3; break; default: - pr_err("Tegra30: Unknown pkg %d\n", tegra_package_id); + pr_err("Tegra30: Unknown pkg %d\n", package_id); BUG(); break; } @@ -293,95 +243,20 @@ static void rev_sku_to_speedo_ids(int rev, int sku) } } -/* - * CPU and core nominal voltage levels as determined by chip SKU and speedo - * (not final - can be lowered by dvfs tables and rail dependencies; the - * latter is resolved by the dvfs code) - */ -static const int cpu_speedo_nominal_millivolts[] = -/* speedo_id 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */ - { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150, 1007, 916, 850, 1237, 1237, 950, 900}; - void tegra30_init_speedo_data(void) { u32 cpu_speedo_val; u32 core_speedo_val; int i; - int fuse_sku, new_sku; - - fuse_sku = tegra_get_sku_id(); - new_sku = fuse_sku; BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != THRESHOLD_INDEX_COUNT); BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != THRESHOLD_INDEX_COUNT); - tegra_package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F; - - cpu_iddq_value = tegra_fuse_readl(FUSE_IDDQ_CALIB_0); - cpu_iddq_value = ((cpu_iddq_value >> 5) & 0x3ff) * 8; - - /* SKU Overrides - * T33 => T30, T30L - * T33S => T30S, T30SL - * T30 => T30L - * T30S => T30SL - * AP33 => AP30 - */ - switch (tegra_sku_override) { - case 1: - /* Base sku override */ - if (fuse_sku == 0x80) { - if (tegra_package_id == 1) { - /* T33 to T30 */ - pr_info("%s: SKU OR: T33->T30\n", __func__); - new_sku = 0x81; - } else if (tegra_package_id == 2) { - /* T33S->T30S */ - pr_info("%s: SKU OR: T33S->T30S\n", __func__); - new_sku = 0x83; - } - } else if (fuse_sku == 0x81) { - if (tegra_package_id == 2) { - /* AP33->AP30 */ - pr_info("%s: SKU OR: AP33->AP30\n", __func__); - new_sku = 0x87; - } - } - break; - case 2: - /* L sku override */ - if (fuse_sku == 0x80) { - if (tegra_package_id == 1) { - /* T33->T30L */ - pr_info("%s: SKU OR: T33->T30L\n", __func__); - new_sku = 0x83; - } else if (tegra_package_id == 2) { - /* T33S->T33SL */ - pr_info("%s: SKU OR: T33S->T30SL\n", __func__); - new_sku = 0x8f; - } - } else if (fuse_sku == 0x81) { - if (tegra_package_id == 1) { - pr_info("%s: SKU OR: T30->T30L\n", __func__); - /* T30->T30L */ - new_sku = 0x83; - } - } else if (fuse_sku == 0x83) { - if (tegra_package_id == 2) { - pr_info("%s: SKU OR: T30S->T30SL\n", __func__); - /* T30S to T30SL */ - new_sku = 0x8f; - } - } - break; - default: - /* no override */ - break; - } + package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F; - rev_sku_to_speedo_ids(tegra_revision, new_sku); + rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id); fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val); pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val); pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val); @@ -397,34 +272,6 @@ void tegra30_init_speedo_data(void) cpu_speedo_val); tegra_cpu_process_id = 0; tegra_cpu_speedo_id = 1; - } else { - if (threshold_index == 12) { - if (tegra_cpu_process_id <= 2) { - switch(fuse_sku) { - case 0xb0: - case 0xb1: - tegra_cpu_speedo_id = 9; - break; - case 0x90: - case 0x91: - tegra_cpu_speedo_id = 14; - default: - break; - } - } else if (tegra_cpu_process_id >= 3 && tegra_cpu_process_id < 6) { - switch(fuse_sku) { - case 0xb0: - case 0xb1: - tegra_cpu_speedo_id = 10; - break; - case 0x90: - case 0x91: - tegra_cpu_speedo_id = 15; - default: - break; - } - } - } } for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) { @@ -442,48 +289,4 @@ void tegra30_init_speedo_data(void) pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d", tegra_cpu_speedo_id, tegra_soc_speedo_id); - - tegra_cpu_speedo_mv = - cpu_speedo_nominal_millivolts[tegra_cpu_speedo_id]; - - switch (tegra_soc_speedo_id) { - case 0: - tegra_core_speedo_mv = 1200; - break; - case 1: - if ((tegra_cpu_speedo_id != 7) && - (tegra_cpu_speedo_id != 8)) { - tegra_core_speedo_mv = 1200; - break; - } - /* fall thru for T30L or T30SL */ - case 2: - if (tegra_cpu_speedo_id != 13) - tegra_core_speedo_mv = 1300; - else /* T37 */ - tegra_core_speedo_mv = 1350; - break; - case 3: - tegra_core_speedo_mv = 1250; - break; - default: - BUG(); - } -} - -int tegra_get_cpu_iddq_value() -{ - return cpu_iddq_value; } - -static int get_enable_app_profiles(char *val, const struct kernel_param *kp) -{ - return param_get_uint(val, kp); -} - -static struct kernel_param_ops tegra_profiles_ops = { - .get = get_enable_app_profiles, -}; - -module_param_cb(tegra_enable_app_profiles, - &tegra_profiles_ops, &enable_app_profiles, 0444); diff --git a/arch/arm/mach-tegra/tegra3_la.c b/arch/arm/mach-tegra/tegra3_la.c deleted file mode 100644 index 43d5699e746e..000000000000 --- a/arch/arm/mach-tegra/tegra3_la.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra3_la.c - * - * Copyright (C) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/stringify.h> -#include <linux/clk.h> -#include <linux/clk/tegra.h> -#include <linux/tegra-soc.h> -#include <asm/io.h> -#include <mach/latency_allowance.h> - -#include "iomap.h" -#include "la_priv.h" - -#define T3_MC_LA_AFI_0 0x2e0 -#define T3_MC_LA_AVPC_ARM7_0 0x2e4 -#define T3_MC_LA_DC_0 0x2e8 -#define T3_MC_LA_DC_1 0x2ec -#define T3_MC_LA_DC_2 0x2f0 -#define T3_MC_LA_DCB_0 0x2f4 -#define T3_MC_LA_DCB_1 0x2f8 -#define T3_MC_LA_DCB_2 0x2fc -#define T3_MC_LA_EPP_0 0x300 -#define T3_MC_LA_EPP_1 0x304 -#define T3_MC_LA_G2_0 0x308 -#define T3_MC_LA_G2_1 0x30c -#define T3_MC_LA_HC_0 0x310 -#define T3_MC_LA_HC_1 0x314 -#define T3_MC_LA_HDA_0 0x318 -#define T3_MC_LA_ISP_0 0x31C -#define T3_MC_LA_MPCORE_0 0x320 -#define T3_MC_LA_MPCORELP_0 0x324 -#define T3_MC_LA_MPE_0 0x328 -#define T3_MC_LA_MPE_1 0x32c -#define T3_MC_LA_MPE_2 0x330 -#define T3_MC_LA_NV_0 0x334 -#define T3_MC_LA_NV_1 0x338 -#define T3_MC_LA_NV2_0 0x33c -#define T3_MC_LA_NV2_1 0x340 -#define T3_MC_LA_PPCS_0 0x344 -#define T3_MC_LA_PPCS_1 0x348 -#define T3_MC_LA_PTC_0 0x34c -#define T3_MC_LA_SATA_0 0x350 -#define T3_MC_LA_VDE_0 0x354 -#define T3_MC_LA_VDE_1 0x358 -#define T3_MC_LA_VDE_2 0x35c -#define T3_MC_LA_VDE_3 0x360 -#define T3_MC_LA_VI_0 0x364 -#define T3_MC_LA_VI_1 0x368 -#define T3_MC_LA_VI_2 0x36c - -#define T3_MC_ARB_OVERRIDE 0xe8 -#define GLOBAL_LATENCY_SCALING_ENABLE_BIT 7 - -#define DS_DISP_MCCIF_DISPLAY0A_HYST (0x481 * 4) -#define DS_DISP_MCCIF_DISPLAY0B_HYST (0x482 * 4) -#define DS_DISP_MCCIF_DISPLAY0C_HYST (0x483 * 4) -#define DS_DISP_MCCIF_DISPLAY1B_HYST (0x484 * 4) - -#define DS_DISP_MCCIF_DISPLAY0AB_HYST (0x481 * 4) -#define DS_DISP_MCCIF_DISPLAY0BB_HYST (0x482 * 4) -#define DS_DISP_MCCIF_DISPLAY0CB_HYST (0x483 * 4) -#define DS_DISP_MCCIF_DISPLAY1BB_HYST (0x484 * 4) - -#define VI_MCCIF_VIWSB_HYST (0x9a * 4) -#define VI_MCCIF_VIWU_HYST (0x9b * 4) -#define VI_MCCIF_VIWV_HYST (0x9c * 4) -#define VI_MCCIF_VIWY_HYST (0x9d * 4) - -#define VI_TIMEOUT_WOCAL_VI (0x70 * 4) -#define VI_RESERVE_3 (0x97 * 4) -#define VI_RESERVE_4 (0x98 * 4) - -/* maximum valid value for latency allowance */ -#define T3_MC_LA_MAX_VALUE 255 - -#define T3_MC_RA(r) \ - (IO_ADDRESS(TEGRA_MC_BASE) + (T3_MC_##r)) -#define T3_RA(r) \ - (IO_ADDRESS(TEGRA_MC_BASE) + (T3_MC_LA_##r)) - -#define T3_LA(f, e, a, r, i, ss, la) \ -{ \ - .fifo_size_in_atoms = f, \ - .expiration_in_ns = e, \ - .reg_addr = T3_RA(a), \ - .mask = MASK(r), \ - .shift = SHIFT(r), \ - .id = ID(i), \ - .name = __stringify(i), \ - .scaling_supported = ss, \ - .init_la = la, \ -} - -/* - * The consensus for getting the fifo_size_in_atoms is: - * 1.If REORDER_DEPTH exists, use it(default is overridden). - * 2.Else if (write_client) use RFIFO_DEPTH. - * 3.Else (read client) use RDFIFO_DEPTH. - * Multiply the value by 2 for wide clients. - * A client is wide, if CMW is larger than MW. - * Refer to project.h file. - */ -struct la_client_info t3_la_info_array[] = { - T3_LA(32, 150, AFI_0, 7 : 0, AFIR, false, 0), - T3_LA(32, 150, AFI_0, 23 : 16, AFIW, false, 0), - T3_LA(2, 150, AVPC_ARM7_0, 7 : 0, AVPC_ARM7R, false, 0), - T3_LA(2, 150, AVPC_ARM7_0, 23 : 16, AVPC_ARM7W, false, 0), - T3_LA(128, 1050, DC_0, 7 : 0, DISPLAY_0A, true, 0), - T3_LA(64, 1050, DC_0, 23 : 16, DISPLAY_0B, true, 0), - T3_LA(128, 1050, DC_1, 7 : 0, DISPLAY_0C, true, 0), - T3_LA(64, 1050, DC_1, 23 : 16, DISPLAY_1B, true, 0), - T3_LA(2, 1050, DC_2, 7 : 0, DISPLAY_HC, false, 0), - T3_LA(128, 1050, DCB_0, 7 : 0, DISPLAY_0AB, true, 0), - T3_LA(64, 1050, DCB_0, 23 : 16, DISPLAY_0BB, true, 0), - T3_LA(128, 1050, DCB_1, 7 : 0, DISPLAY_0CB, true, 0), - T3_LA(64, 1050, DCB_1, 23 : 16, DISPLAY_1BB, true, 0), - T3_LA(2, 1050, DCB_2, 7 : 0, DISPLAY_HCB, false, 0), - T3_LA(8, 150, EPP_0, 7 : 0, EPPUP, false, 0), - T3_LA(64, 150, EPP_0, 23 : 16, EPPU, false, 0), - T3_LA(64, 150, EPP_1, 7 : 0, EPPV, false, 0), - T3_LA(64, 150, EPP_1, 23 : 16, EPPY, false, 0), - T3_LA(64, 150, G2_0, 7 : 0, G2PR, false, 0), - T3_LA(64, 150, G2_0, 23 : 16, G2SR, false, 0), - T3_LA(48, 150, G2_1, 7 : 0, G2DR, false, 0), - T3_LA(128, 150, G2_1, 23 : 16, G2DW, false, 0), - T3_LA(16, 150, HC_0, 7 : 0, HOST1X_DMAR, false, 0), - T3_LA(8, 150, HC_0, 23 : 16, HOST1XR, false, 0), - T3_LA(32, 150, HC_1, 7 : 0, HOST1XW, false, 0), - T3_LA(16, 150, HDA_0, 7 : 0, HDAR, false, 0), - T3_LA(16, 150, HDA_0, 23 : 16, HDAW, false, 0), - T3_LA(64, 150, ISP_0, 7 : 0, ISPW, false, 0), - T3_LA(14, 150, MPCORE_0, 7 : 0, MPCORER, false, 0), - T3_LA(24, 150, MPCORE_0, 23 : 16, MPCOREW, false, 0), - T3_LA(14, 150, MPCORELP_0, 7 : 0, MPCORE_LPR, false, 0), - T3_LA(24, 150, MPCORELP_0, 23 : 16, MPCORE_LPW, false, 0), - T3_LA(8, 150, MPE_0, 7 : 0, MPE_UNIFBR, false, 0), - T3_LA(2, 150, MPE_0, 23 : 16, MPE_IPRED, false, 0), - T3_LA(64, 150, MPE_1, 7 : 0, MPE_AMEMRD, false, 0), - T3_LA(8, 150, MPE_1, 23 : 16, MPE_CSRD, false, 0), - T3_LA(8, 150, MPE_2, 7 : 0, MPE_UNIFBW, false, 0), - T3_LA(8, 150, MPE_2, 23 : 16, MPE_CSWR, false, 0), - T3_LA(96, 150, NV_0, 7 : 0, FDCDRD, false, 0), - T3_LA(64, 150, NV_0, 23 : 16, IDXSRD, false, 0), - T3_LA(64, 150, NV_1, 7 : 0, TEXSRD, false, 0), - T3_LA(96, 150, NV_1, 23 : 16, FDCDWR, false, 0), - T3_LA(96, 150, NV2_0, 7 : 0, FDCDRD2, false, 0), - T3_LA(64, 150, NV2_0, 23 : 16, IDXSRD2, false, 0), - T3_LA(64, 150, NV2_1, 7 : 0, TEXSRD2, false, 0), - T3_LA(96, 150, NV2_1, 23 : 16, FDCDWR2, false, 0), - T3_LA(2, 150, PPCS_0, 7 : 0, PPCS_AHBDMAR, false, 0), - T3_LA(8, 150, PPCS_0, 23 : 16, PPCS_AHBSLVR, false, 0), - T3_LA(2, 150, PPCS_1, 7 : 0, PPCS_AHBDMAW, false, 0), - T3_LA(4, 150, PPCS_1, 23 : 16, PPCS_AHBSLVW, false, 0), - T3_LA(2, 150, PTC_0, 7 : 0, PTCR, false, 0), - T3_LA(32, 150, SATA_0, 7 : 0, SATAR, false, 0), - T3_LA(32, 150, SATA_0, 23 : 16, SATAW, false, 0), - T3_LA(8, 150, VDE_0, 7 : 0, VDE_BSEVR, false, 0), - T3_LA(4, 150, VDE_0, 23 : 16, VDE_MBER, false, 0), - T3_LA(16, 150, VDE_1, 7 : 0, VDE_MCER, false, 0), - T3_LA(16, 150, VDE_1, 23 : 16, VDE_TPER, false, 0), - T3_LA(4, 150, VDE_2, 7 : 0, VDE_BSEVW, false, 0), - T3_LA(16, 150, VDE_2, 23 : 16, VDE_DBGW, false, 0), - T3_LA(2, 150, VDE_3, 7 : 0, VDE_MBEW, false, 0), - T3_LA(16, 150, VDE_3, 23 : 16, VDE_TPMW, false, 0), - T3_LA(8, 1050, VI_0, 7 : 0, VI_RUV, false, 0), - T3_LA(64, 1050, VI_0, 23 : 16, VI_WSB, true, 0), - T3_LA(64, 1050, VI_1, 7 : 0, VI_WU, true, 0), - T3_LA(64, 1050, VI_1, 23 : 16, VI_WV, true, 0), - T3_LA(64, 1050, VI_2, 7 : 0, VI_WY, true, 0), - -/* end of list. */ - T3_LA(0, 0, AFI_0, 0 : 0, MAX_ID, false, 0) -}; - -#define DISP1_RA(r) \ - (IO_ADDRESS(TEGRA_DISPLAY_BASE) + DS_DISP_MCCIF_##r##_HYST) -#define DISP2_RA(r) \ - (IO_ADDRESS(TEGRA_DISPLAY2_BASE) + DS_DISP_MCCIF_##r##_HYST) - -#define DISP_SCALING_REG_INFO(id, r, ra) \ - { \ - ID(id), \ - ra(r), MASK(15 : 8), SHIFT(15 : 8), \ - ra(r), MASK(23 : 16), SHIFT(15 : 8), \ - ra(r), MASK(7 : 0), SHIFT(15 : 8) \ - } - -struct la_scaling_reg_info disp_info[] = { - DISP_SCALING_REG_INFO(DISPLAY_0A, DISPLAY0A, DISP1_RA), - DISP_SCALING_REG_INFO(DISPLAY_0B, DISPLAY0B, DISP1_RA), - DISP_SCALING_REG_INFO(DISPLAY_0C, DISPLAY0C, DISP1_RA), - DISP_SCALING_REG_INFO(DISPLAY_1B, DISPLAY1B, DISP1_RA), - DISP_SCALING_REG_INFO(MAX_ID, DISPLAY1B, DISP1_RA), /*dummy entry*/ - DISP_SCALING_REG_INFO(DISPLAY_0AB, DISPLAY0AB, DISP2_RA), - DISP_SCALING_REG_INFO(DISPLAY_0BB, DISPLAY0BB, DISP2_RA), - DISP_SCALING_REG_INFO(DISPLAY_0CB, DISPLAY0CB, DISP2_RA), - DISP_SCALING_REG_INFO(DISPLAY_1BB, DISPLAY1BB, DISP2_RA), -}; - -#define VI_TH_RA(r) \ - (IO_ADDRESS(TEGRA_VI_BASE) + VI_MCCIF_##r##_HYST) -#define VI_TM_RA(r) \ - (IO_ADDRESS(TEGRA_VI_BASE) + VI_TIMEOUT_WOCAL_VI) -#define VI_TL_RA(r) \ - (IO_ADDRESS(TEGRA_VI_BASE) + VI_RESERVE_##r) - -struct la_scaling_reg_info vi_info[] = { - { - ID(VI_WSB), - VI_TL_RA(4), MASK(7 : 0), SHIFT(7 : 0), - VI_TM_RA(0), MASK(7 : 0), SHIFT(7 : 0), - VI_TH_RA(VIWSB), MASK(7 : 0), SHIFT(7 : 0) - }, - { - ID(VI_WU), - VI_TL_RA(3), MASK(15 : 8), SHIFT(15 : 8), - VI_TM_RA(0), MASK(15 : 8), SHIFT(15 : 8), - VI_TH_RA(VIWU), MASK(7 : 0), SHIFT(7 : 0) - }, - { - ID(VI_WV), - VI_TL_RA(3), MASK(7 : 0), SHIFT(7 : 0), - VI_TM_RA(0), MASK(23 : 16), SHIFT(23 : 16), - VI_TH_RA(VIWV), MASK(7 : 0), SHIFT(7 : 0) - }, - { - ID(VI_WY), - VI_TL_RA(4), MASK(15 : 8), SHIFT(15 : 8), - VI_TM_RA(0), MASK(31 : 24), SHIFT(31 : 24), - VI_TH_RA(VIWY), MASK(7 : 0), SHIFT(7 : 0) - } -}; - -static struct la_chip_specific *cs; - -static void set_thresholds(struct la_scaling_reg_info *info, - enum tegra_la_id id) -{ - unsigned long reg_read; - unsigned long reg_write; - unsigned int thresh_low; - unsigned int thresh_mid; - unsigned int thresh_high; - int la_set; - int idx = cs->id_to_index[id]; - - reg_read = readl(cs->la_info_array[idx].reg_addr); - la_set = (reg_read & cs->la_info_array[idx].mask) >> - cs->la_info_array[idx].shift; - /* la should be set before enabling scaling. */ - BUG_ON(la_set != cs->scaling_info[idx].la_set); - - thresh_low = (cs->scaling_info[idx].threshold_low * la_set) / 100; - thresh_mid = (cs->scaling_info[idx].threshold_mid * la_set) / 100; - thresh_high = (cs->scaling_info[idx].threshold_high * la_set) / 100; - la_debug("%s: la_set=%d, thresh_low=%d(%d%%), thresh_mid=%d(%d%%)," - " thresh_high=%d(%d%%) ", __func__, la_set, - thresh_low, cs->scaling_info[idx].threshold_low, - thresh_mid, cs->scaling_info[idx].threshold_mid, - thresh_high, cs->scaling_info[idx].threshold_high); - - reg_read = readl(info->tl_reg_addr); - reg_write = (reg_read & ~info->tl_mask) | - (thresh_low << info->tl_shift); - writel(reg_write, info->tl_reg_addr); - la_debug("reg_addr=0x%x, read=0x%x, write=0x%x", - (u32)info->tl_reg_addr, (u32)reg_read, (u32)reg_write); - - reg_read = readl(info->tm_reg_addr); - reg_write = (reg_read & ~info->tm_mask) | - (thresh_mid << info->tm_shift); - writel(reg_write, info->tm_reg_addr); - la_debug("reg_addr=0x%x, read=0x%x, write=0x%x", - (u32)info->tm_reg_addr, (u32)reg_read, (u32)reg_write); - - reg_read = readl(info->th_reg_addr); - reg_write = (reg_read & ~info->th_mask) | - (thresh_high << info->th_shift); - writel(reg_write, info->th_reg_addr); - la_debug("reg_addr=0x%x, read=0x%x, write=0x%x", - (u32)info->th_reg_addr, (u32)reg_read, (u32)reg_write); -} - -static void set_disp_latency_thresholds(enum tegra_la_id id) -{ - set_thresholds(&disp_info[id - ID(DISPLAY_0A)], id); -} - -static void set_vi_latency_thresholds(enum tegra_la_id id) -{ - set_thresholds(&vi_info[id - ID(VI_WSB)], id); -} - -/* Thresholds for scaling are specified in % of fifo freeness. - * If threshold_low is specified as 20%, it means when the fifo free - * between 0 to 20%, use la as programmed_la. - * If threshold_mid is specified as 50%, it means when the fifo free - * between 20 to 50%, use la as programmed_la/2 . - * If threshold_high is specified as 80%, it means when the fifo free - * between 50 to 80%, use la as programmed_la/4. - * When the fifo is free between 80 to 100%, use la as 0(highest priority). - */ -int t3_enable_la_scaling(enum tegra_la_id id, - unsigned int threshold_low, - unsigned int threshold_mid, - unsigned int threshold_high) -{ - unsigned long reg; - void __iomem *scaling_enable_reg = - (void __iomem *)(T3_MC_RA(ARB_OVERRIDE)); - int idx = cs->id_to_index[id]; - - VALIDATE_ID(id, cs); - VALIDATE_THRESHOLDS(threshold_low, threshold_mid, threshold_high); - - if (cs->la_info_array[idx].scaling_supported == false) - goto exit; - - spin_lock(&cs->lock); - - la_debug("\n%s: id=%d, tl=%d, tm=%d, th=%d", __func__, - id, threshold_low, threshold_mid, threshold_high); - cs->scaling_info[idx].threshold_low = threshold_low; - cs->scaling_info[idx].threshold_mid = threshold_mid; - cs->scaling_info[idx].threshold_high = threshold_high; - cs->scaling_info[idx].scaling_ref_count++; - - if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_1BB)) - set_disp_latency_thresholds(id); - else if (id >= ID(VI_WSB) && id <= ID(VI_WY)) - set_vi_latency_thresholds(id); - if (!cs->la_scaling_enable_count++) { - reg = readl(scaling_enable_reg); - reg |= (1 << GLOBAL_LATENCY_SCALING_ENABLE_BIT); - writel(reg, scaling_enable_reg); - la_debug("enabled scaling."); - } - spin_unlock(&cs->lock); -exit: - return 0; -} - -void t3_disable_la_scaling(enum tegra_la_id id) -{ - unsigned long reg; - void __iomem *scaling_enable_reg = - (void __iomem *)(T3_MC_RA(ARB_OVERRIDE)); - int idx; - - BUG_ON(id >= TEGRA_LA_MAX_ID); - idx = cs->id_to_index[id]; - BUG_ON(cs->la_info_array[idx].id != id); - - if (cs->la_info_array[idx].scaling_supported == false) - return; - spin_lock(&cs->lock); - la_debug("\n%s: id=%d", __func__, id); - cs->scaling_info[idx].scaling_ref_count--; - BUG_ON(cs->scaling_info[idx].scaling_ref_count < 0); - - if (!--cs->la_scaling_enable_count) { - reg = readl(scaling_enable_reg); - reg = reg & ~(1 << GLOBAL_LATENCY_SCALING_ENABLE_BIT); - writel(reg, scaling_enable_reg); - la_debug("disabled scaling."); - } - spin_unlock(&cs->lock); -} - -void tegra_la_get_t3_specific(struct la_chip_specific *cs_la) -{ - cs_la->ns_per_tick = 30; - cs_la->atom_size = 16; - cs_la->la_max_value = T3_MC_LA_MAX_VALUE; - cs_la->la_info_array = t3_la_info_array; - cs_la->la_info_array_size = ARRAY_SIZE(t3_la_info_array); - cs_la->enable_la_scaling = t3_enable_la_scaling; - cs_la->disable_la_scaling = t3_disable_la_scaling; - cs = cs_la; -} diff --git a/arch/arm/mach-tegra/timer-t2.c b/arch/arm/mach-tegra/timer-t2.c deleted file mode 100644 index 45f12ecaf407..000000000000 --- a/arch/arm/mach-tegra/timer-t2.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * arch/arch/mach-tegra/timer.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2011 NVIDIA Corporation. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/init.h> -#include <linux/err.h> -#include <linux/time.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/syscore_ops.h> -#include <linux/export.h> - -#include <asm/mach/time.h> -#include <asm/localtimer.h> -#include <asm/sched_clock.h> - -#include <mach/irqs.h> - -#include "board.h" -#include "clock.h" -#include "iomap.h" -#include "timer.h" - -/* - * Timers usage: - * TMR1 - Free. - * TMR2 - used by AVP. - * TMR3 - used as general CPU timer. - * TMR4 - used for LP2 wakeup. -*/ - -#define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE) -#define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE) -#define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE) -#define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE) - -#define timer_writel(value, reg) \ - __raw_writel(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - __raw_readl(timer_reg_base + (reg)) - - -static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); - -#ifdef CONFIG_PM_SLEEP -static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id) -{ - timer_writel(1<<30, TIMER4_OFFSET + TIMER_PCR); - return IRQ_HANDLED; -} - -static struct irqaction tegra_lp2wake_irq = { - .name = "timer_lp2wake", - .flags = IRQF_DISABLED, - .handler = tegra_lp2wake_interrupt, - .dev_id = NULL, - .irq = INT_TMR4, -}; - -void tegra2_lp2_set_trigger(unsigned long cycles) -{ - timer_writel(0, TIMER4_OFFSET + TIMER_PTV); - if (cycles) { - u32 reg = 0x80000000ul | min(0x1ffffffful, cycles); - timer_writel(reg, TIMER4_OFFSET + TIMER_PTV); - } -} -EXPORT_SYMBOL(tegra2_lp2_set_trigger); - -unsigned long tegra2_lp2_timer_remain(void) -{ - return timer_readl(TIMER4_OFFSET + TIMER_PCR) & 0x1ffffffful; -} -#endif - -void __init tegra20_init_timer(void) -{ - int ret; - -#ifdef CONFIG_PM_SLEEP - ret = setup_irq(tegra_lp2wake_irq.irq, &tegra_lp2wake_irq); - if (ret) { - pr_err("Failed to register LP2 timer IRQ: %d\n", ret); - BUG(); - } -#endif -} diff --git a/arch/arm/mach-tegra/wakeups-t11x.c b/arch/arm/mach-tegra/wakeups-t11x.c deleted file mode 100644 index de81a32ee234..000000000000 --- a/arch/arm/mach-tegra/wakeups-t11x.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/tegra.h> - -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> -#include "board.h" -#include "tegra-board-id.h" -#include "gpio-names.h" -#include "iomap.h" - -/* Tegra USB1 wake source index */ -#define USB1_VBUS_WAKE 19 -#define USB1_ID_WAKE 21 -#define USB1_REM_WAKE 39 - -/* constants for USB1 wake sources - VBUS and ID */ -#define USB1_IF_USB_PHY_VBUS_SENSORS_0 0x408 -#define VBUS_WAKEUP_STS_BIT 10 -#define ID_STS_BIT 2 - -static int tegra_gpio_wakes[] = { - TEGRA_GPIO_PO5, /* wake0 */ - TEGRA_GPIO_PV1, /* wake1 */ - -EINVAL, /* wake2 */ - -EINVAL, /* wake3 */ - -EINVAL, /* wake4 */ - -EINVAL, /* wake5 */ - TEGRA_GPIO_PU5, /* wake6 */ - TEGRA_GPIO_PU6, /* wake7 */ - TEGRA_GPIO_PC7, /* wake8 */ - TEGRA_GPIO_PS2, /* wake9 */ - -EINVAL, /* wake10 */ - TEGRA_GPIO_PW3, /* wake11 */ - TEGRA_GPIO_PW2, /* wake12 */ - -EINVAL, /* wake13 */ - TEGRA_GPIO_PDD3, /* wake14 */ - TEGRA_GPIO_PJ2, /* wake15 */ - -EINVAL, /* wake16 */ - -EINVAL, /* wake17 */ - -EINVAL, /* wake18 */ - -EINVAL, /* wake19 */ - -EINVAL, /* wake20 */ - -EINVAL, /* wake21 */ - -EINVAL, /* wake22 */ - TEGRA_GPIO_PI5, /* wake23 */ - TEGRA_GPIO_PV0, /* wake24 */ - -EINVAL, /* wake25 */ - -EINVAL, /* wake26 */ - TEGRA_GPIO_PS0, /* wake27 */ - -EINVAL, /* wake28 */ - -EINVAL, /* wake29 */ - -EINVAL, /* wake30 */ - -EINVAL, /* wake31 */ - -EINVAL, /* wake32 */ - TEGRA_GPIO_PJ0, /* wake33 */ - TEGRA_GPIO_PK2, /* wake34 */ - TEGRA_GPIO_PI6, /* wake35 */ - -EINVAL, /* wake36 */ - -EINVAL, /* wake37 */ - -EINVAL, /* wake38 */ - -EINVAL, /* wake39 */ - -EINVAL, /* wake40 */ - -EINVAL, /* wake41 */ - -EINVAL, /* wake42 */ - -EINVAL, /* wake43 */ - -EINVAL, /* wake44 */ - TEGRA_GPIO_PBB6, /* wake45 */ - -EINVAL, /* wake46 */ - TEGRA_GPIO_PT6, /* wake47 */ - -EINVAL, /* wake48 */ - TEGRA_GPIO_PR7, /* wake49 */ - TEGRA_GPIO_PR4, /* wake50 */ - TEGRA_GPIO_PQ0, /* wake51 */ - TEGRA_GPIO_PEE3, /* wake52 */ - -EINVAL, /* wake53 */ - TEGRA_GPIO_PQ5, /* wake54 */ - -EINVAL, /* wake55 */ - TEGRA_GPIO_PV2, /* wake56 */ - -EINVAL, /* wake57 */ - -EINVAL, /* wake58 */ -}; - -static int tegra_wake_event_irq[] = { - -EAGAIN, /* ULPI DATA4 */ /* wake0 */ - -EAGAIN, /* wake1 */ - -EAGAIN, /* wake2 */ - -EINVAL, /* SDMMC3 DAT1 */ /* wake3 */ - -EINVAL, /* HDMI INT */ /* wake4 */ - -EAGAIN, /* wake5 */ - -EAGAIN, /* wake6 */ - -EAGAIN, /* wake7 */ - -EAGAIN, /* wake8 */ - -EAGAIN, /* UART3 RXD */ /* wake9 */ - -EINVAL, /* SDMMC4 DAT1 */ /* wake10 */ - -EAGAIN, /* wake11 */ - -EAGAIN, /* wake12 */ - -EINVAL, /* SDMMC1 DAT1 */ /* wake13 */ - -EAGAIN, /* wake14 */ - INT_EDP, /* wake15 */ - INT_RTC, /* Tegra RTC */ /* wake16 */ - INT_KBC, /* Tegra KBC */ /* wake17 */ - INT_EXTERNAL_PMU, /* wake18 */ - INT_USB, /* wake19 */ - -EINVAL, /* wake20 */ - INT_USB, /* wake21 */ - -EINVAL, /* wake22 */ - -EAGAIN, /* wake23 */ - -EAGAIN, /* wake24 */ - -EAGAIN, /* wake25 */ - -EAGAIN, /* wake26 */ - -EAGAIN, /* wake27 */ - -EAGAIN, /* wake28 */ - -EAGAIN, /* wake29 */ - -EINVAL, /* I2S0 SDATA OUT */ /* wake30 */ - -EINVAL, /* wake31 */ - -EINVAL, /* ULPI DATA3 */ /* wake32 */ - -EAGAIN, /* wake33 */ - -EAGAIN, /* wake34 */ - -EAGAIN, /* wake35 */ - -EAGAIN, /* wake36 */ - -EINVAL, /* usb_vbus_wakeup[2] not on t35 */ /* wake37 */ - -EINVAL, /* usb_iddig[2] not on t35 */ /* wake38 */ - INT_USB, /* utmip0 line wakeup event - USB1 */ /* wake39 */ - -EINVAL, /* utmip1 line wakeup - USB2 , not on t35 */ /* wake40 */ - -EINVAL, /* utmip2 line wakeup event - USB3 */ /* wake41 */ - INT_USB2, /* uhsic line wakeup event - USB2 */ /* wake42 */ - INT_USB3, /* uhsic2 line wakeup event - USB3 */ /* wake43 */ - -EINVAL, /* I2C1 DAT */ /* wake44 */ - -EAGAIN, /* wake45 */ - -EINVAL, /* PWR I2C DAT */ /* wake46 */ - -EAGAIN, /* I2C2 DAT */ /* wake47 */ - -EINVAL, /* I2C3 DAT */ /* wake48 */ - -EAGAIN, /* wake49 */ - -EAGAIN, /* wake50 */ - -EAGAIN, /* KBC11 */ /* wake51 */ - -EAGAIN, /* HDMI CEC */ /* wake52 */ - -EINVAL, /* I2C3 CLK */ /* wake53 */ - -EAGAIN, /* wake54 */ - -EINVAL, /* UART3 CTS */ /* wake55 */ - -EAGAIN, /* SDMMC3 CD */ /* wake56 */ - -EINVAL, /* spdif_in */ /* wake57 */ - INT_XUSB_PADCTL, /* XUSB superspeed wake */ /* wake58 */ -}; - -#ifdef CONFIG_TEGRA_INTERNAL_USB_CABLE_WAKE_SUPPORT -/* USB1 VBUS and ID wake sources are handled as special case - * Note: SD card detect is an ANY wake source but is - * mostly a GPIO which can handle any edge wakeup. - */ -static u8 any_wake_t11x[] = { - /* DO NOT EDIT this list */ - [ANY_WAKE_INDEX_VBUS] = USB1_VBUS_WAKE, - [ANY_WAKE_INDEX_ID] = USB1_ID_WAKE, -}; - -void tegra_get_internal_any_wake_list(u8 *wake_count, u8 **any_wake, - u8 *remote_usb) -{ - *wake_count = ARRAY_SIZE(any_wake_t11x); - *any_wake = any_wake_t11x; - *remote_usb = USB1_REM_WAKE; -} - -/* Needed on dalmore today hence exposed this API */ -int get_vbus_id_cable_connect_state(bool *is_vbus_connected, - bool *is_id_connected) -{ - static void __iomem *usb1_base = IO_ADDRESS(TEGRA_USB_BASE); - u32 reg; - - reg = readl(usb1_base + USB1_IF_USB_PHY_VBUS_SENSORS_0); - - /* ID bit when 0 - ID cable connected */ - *is_id_connected = (reg & (1 << ID_STS_BIT)) ? false : true; - - /* - * VBUS_WAKEUP_STS_BIT is also set when ID is connected - * and we are supplying VBUS, hence below conditional assignment - */ - if (*is_id_connected) - *is_vbus_connected = false; - else - /* VBUS bit when 1 - VBUS cable connected */ - *is_vbus_connected = (reg & (1 << VBUS_WAKEUP_STS_BIT)) ? - true : false; - return 0; -} -#endif - -void tegra_set_usb_wake_source(void) -{ - struct board_info board_info; - - tegra_get_board_info(&board_info); - /* For Dalmore */ - if (board_info.board_id == BOARD_E1611) { - tegra_wake_event_irq[41] = INT_USB3; - tegra_wake_event_irq[43] = -EINVAL; - } -} - -static int __init tegra11x_wakeup_table_init(void) -{ - tegra_gpio_wake_table = tegra_gpio_wakes; - tegra_irq_wake_table = tegra_wake_event_irq; - tegra_wake_table_len = ARRAY_SIZE(tegra_gpio_wakes); - return 0; -} - -int __init tegra_wakeup_table_init(void) -{ - return tegra11x_wakeup_table_init(); -} diff --git a/arch/arm/mach-tegra/wakeups-t11x.h b/arch/arm/mach-tegra/wakeups-t11x.h deleted file mode 100644 index e61fa362d61d..000000000000 --- a/arch/arm/mach-tegra/wakeups-t11x.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/mach-tegra/wakeups-t11x.h - * - * Declarations of Tegra 11x LP0 wakeup sources - * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MACH_TEGRA_WAKEUPS_T11X_H -#define __MACH_TEGRA_WAKEUPS_T11X_H - -#ifndef CONFIG_ARCH_TEGRA_11x_SOC -#error "Tegra 11x wakeup sources valid only for CONFIG_ARCH_TEGRA_11x_SOC" -#endif - -#define TEGRA_WAKE_GPIO_PO5 0 -#define TEGRA_WAKE_GPIO_PV1 1 -#define TEGRA_WAKE_GPIO_PU5 6 -#define TEGRA_WAKE_GPIO_PU6 7 -#define TEGRA_WAKE_GPIO_PC7 8 -#define TEGRA_WAKE_GPIO_PS2 9 -#define TEGRA_WAKE_GPIO_PW3 11 -#define TEGRA_WAKE_GPIO_PW2 12 -#define TEGRA_WAKE_GPIO_PDD3 14 -#define TEGRA_WAKE_GPIO_PI5 23 -#define TEGRA_WAKE_GPIO_PV0 24 -#define TEGRA_WAKE_GPIO_PS0 27 -#define TEGRA_WAKE_GPIO_PJ0 33 -#define TEGRA_WAKE_GPIO_PK2 34 -#define TEGRA_WAKE_GPIO_PI6 35 -#define TEGRA_WAKE_GPIO_PBB6 45 -#define TEGRA_WAKE_GPIO_PT6 47 -#define TEGRA_WAKE_GPIO_PR7 49 -#define TEGRA_WAKE_GPIO_PR4 50 -#define TEGRA_WAKE_GPIO_PQ0 51 -#define TEGRA_WAKE_GPIO_PQ5 54 -#define TEGRA_WAKE_GPIO_PV2 56 - -#endif diff --git a/arch/arm/mach-tegra/wakeups-t14x.c b/arch/arm/mach-tegra/wakeups-t14x.c deleted file mode 100644 index d8124ba736ab..000000000000 --- a/arch/arm/mach-tegra/wakeups-t14x.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/tegra.h> - -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> -#include "board.h" -#include "tegra-board-id.h" -#include "gpio-names.h" -#include "iomap.h" - -static int tegra_gpio_wakes[] = { - TEGRA_GPIO_PL0, /* wake0 */ - TEGRA_GPIO_PL2, /* wake1 */ - TEGRA_GPIO_PM2, /* wake2 */ - TEGRA_GPIO_PB4, /* wake3 */ - TEGRA_GPIO_PM4, /* wake4 */ - TEGRA_GPIO_PM7, /* wake5 */ - TEGRA_GPIO_PN1, /* wake6 */ - TEGRA_GPIO_PO0, /* wake7 */ - TEGRA_GPIO_PO1, /* wake8 */ - TEGRA_GPIO_PO2, /* wake9 */ - TEGRA_GPIO_PC3, /* wake10 */ - TEGRA_GPIO_PO3, /* wake11 */ - TEGRA_GPIO_PO4, /* wake12 */ - TEGRA_GPIO_PA4, /* wake13 */ - TEGRA_GPIO_PO5, /* wake14 */ - TEGRA_GPIO_PO6, /* wake15 */ - -EINVAL, /* wake16 */ - -EINVAL, /* wake17 */ - -EINVAL, /* wake18 */ - -EINVAL, /* wake19 */ - -EINVAL, /* wake20 */ - -EINVAL, /* wake21 */ - -EINVAL, /* wake22 */ - TEGRA_GPIO_PJ5, /* wake23 */ - TEGRA_GPIO_PJ6, /* wake24 */ - TEGRA_GPIO_PJ1, /* wake25 */ - TEGRA_GPIO_PJ2, /* wake26 */ - TEGRA_GPIO_PJ3, /* wake27 */ - TEGRA_GPIO_PJ4, /* wake28 */ - TEGRA_GPIO_PJ0, /* wake29 */ - -EINVAL, /* wake30 */ - -EINVAL, /* wake31 */ - -EINVAL, /* wake32 */ - TEGRA_GPIO_PJ0, /* wake33 */ - TEGRA_GPIO_PK2, /* wake34 */ - TEGRA_GPIO_PI6, /* wake35 */ - -EINVAL, /* wake36 */ - -EINVAL, /* wake37 */ - -EINVAL, /* wake38 */ - -EINVAL, /* wake39 */ - -EINVAL, /* wake40 */ - -EINVAL, /* wake41 */ - -EINVAL, /* wake42 */ - -EINVAL, /* wake43 */ - -EINVAL, /* wake44 */ - TEGRA_GPIO_PBB6, /* wake45 */ - -EINVAL, /* wake46 */ - TEGRA_GPIO_PL6, /* wake47 */ - -EINVAL, /* wake48 */ - TEGRA_GPIO_PR7, /* wake49 */ - TEGRA_GPIO_PR4, /* wake50 */ - -EINVAL, /* wake51 */ - TEGRA_GPIO_PN5, /* wake52 */ - -EINVAL, /* wake53 */ - TEGRA_GPIO_PQ5, /* wake54 */ - TEGRA_GPIO_PK3, /* wake55 */ - -EINVAL, /* wake56 */ - -EINVAL, /* wake57 */ - -EINVAL, /* wake58 */ - -EINVAL, /* wake59 */ - -EINVAL, /* wake60 */ - -EINVAL, /* wake61 */ - -EINVAL, /* wake62 */ - -EINVAL, /* wake63 */ -}; - -static int tegra_wake_event_irq[] = { - -EAGAIN, /* SPI3_MOSI */ /* wake0 */ - -EAGAIN, /* SPI3_SCK */ /* wake1 */ - -EAGAIN, /* BT_WAKE_AP */ /* wake2 */ - -EAGAIN, /* SDMMC3 DAT1 */ /* wake3 */ - -EAGAIN, /* NFC_INT_L */ /* wake4 */ - -EAGAIN, /* MOTION_INT_L */ /* wake5 */ - -EAGAIN, /* TOUCH_INT_L */ /* wake6 */ - -EAGAIN, /* wake7 */ - -EAGAIN, /* wake8 */ - -EAGAIN, /* UART3 RXD */ /* wake9 */ - -EAGAIN, /* SDMMC4 DAT1 */ /* wake10 */ - -EAGAIN, /* wake11 */ - -EAGAIN, /* wake12 */ - -EAGAIN, /* SDMMC1 DAT1 */ /* wake13 */ - -EAGAIN, /* wake14 */ - -EAGAIN, /* INT_EDP */ /* wake15 */ - -EINVAL, /* Tegra RTC */ /* wake16 */ - -EINVAL, /* Tegra KBC */ /* wake17 */ - INT_EXTERNAL_PMU, /* wake18 */ - -EINVAL, /* removed USB1 VBUS wake */ /* wake19 */ - -EINVAL, /* removed USB2 VBUS wake */ /* wake20 */ - -EINVAL, /* removed USB1 ID wake */ /* wake21 */ - -EINVAL, /* removed USB2 ID wake */ /* wake22 */ - -EAGAIN, /* wake23 */ - -EAGAIN, /* wake24 */ - -EAGAIN, /* KB_ROW0 */ /* wake25 */ - -EAGAIN, /* KB_ROW1 */ /* wake26 */ - -EAGAIN, /* KB_ROW2 */ /* wake27 */ - -EAGAIN, /* KB_COL0 */ /* wake28 */ - -EINVAL, /* INT_MIPI_BIF - BCL */ /* wake29 */ - -EINVAL, /* I2S0 SDATA OUT */ /* wake30 */ - -EINVAL, /* wake31 */ - -EINVAL, /* ULPI DATA3 */ /* wake32 */ - -EAGAIN, /* wake33 */ - -EAGAIN, /* wake34 */ - -EAGAIN, /* wake35 */ - -EINVAL, /* wake36 */ - -EINVAL, /* removed USB3 VBUS wake */ /* wake37 */ - -EINVAL, /* removed USB3 ID wake */ /* wake38 */ - INT_USB, /* USB1 UTMIP */ /* wake39 */ - -EINVAL, /* removed USB2 UTMIP wake */ /* wake40 */ - -EINVAL, /* removed USB3 UTMIP wake */ /* wake41 */ - INT_USB2, /* USB2 UHSIC PHY */ /* wake42 */ - -EINVAL, /* removed USB3 UHSIC PHY wake */ /* wake43 */ - -EINVAL, /* I2C1 DAT */ /* wake44 */ - -EAGAIN, /* wake45 */ - -EINVAL, /* PWR I2C DAT */ /* wake46 */ - -EAGAIN, /* I2C2 DAT */ /* wake47 */ - -EINVAL, /* I2C3 DAT */ /* wake48 */ - -EAGAIN, /* wake49 */ - -EAGAIN, /* wake50 */ - -EINVAL, /* KBC11 */ /* wake51 */ - -EAGAIN, /* HDMI CEC */ /* wake52 */ - -EINVAL, /* I2C3 CLK */ /* wake53 */ - -EAGAIN, /* wake54 */ - -EAGAIN, /* UART3 CTS */ /* wake55 */ - -EINVAL, /* wake56 */ - -EINVAL, /* wake57 */ - -EINVAL, /* wake58 */ - INT_BB2AP_INT0, /* wake59 */ - -EINVAL, /* wake60 */ - -EINVAL, /* wake61 */ - -EINVAL, /* wake62 */ - -EINVAL, /* wake63 */ -}; - -static int __init tegra14x_wakeup_table_init(void) -{ - tegra_gpio_wake_table = tegra_gpio_wakes; - tegra_irq_wake_table = tegra_wake_event_irq; - tegra_wake_table_len = ARRAY_SIZE(tegra_gpio_wakes); - return 0; -} - -int __init tegra_wakeup_table_init(void) -{ - return tegra14x_wakeup_table_init(); -} diff --git a/arch/arm/mach-tegra/wakeups-t14x.h b/arch/arm/mach-tegra/wakeups-t14x.h deleted file mode 100644 index 5acc7bed0f76..000000000000 --- a/arch/arm/mach-tegra/wakeups-t14x.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-tegra/wakeups-t14x.h - * - * Declarations of Tegra 14x LP0 wakeup sources - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MACH_TEGRA_WAKEUPS_T14X_H -#define __MACH_TEGRA_WAKEUPS_T14X_H - -#ifndef CONFIG_ARCH_TEGRA_14x_SOC -#error "Tegra 14x wakeup sources valid only for CONFIG_ARCH_TEGRA_14x_SOC" -#endif - - -/* Must align with tegra_gpio_wakes table in wakeups-t14x.c */ -#define TEGRA_WAKE_GPIO_PL0 0 /* wake0 */ -#define TEGRA_WAKE_GPIO_PL2 1 /* wake1 */ -#define TEGRA_WAKE_GPIO_PM2 2 /* wake2 */ -#define TEGRA_WAKE_GPIO_PM4 4 /* wake4 */ -#define TEGRA_WAKE_GPIO_PM7 5 /* wake5 */ -#define TEGRA_WAKE_GPIO_PN1 6 /* wake6 */ -#define TEGRA_WAKE_GPIO_PO0 7 /* wake7 */ -#define TEGRA_WAKE_GPIO_PO1 8 /* wake8 */ -#define TEGRA_WAKE_GPIO_PO2 9 /* wake9 */ -#define TEGRA_WAKE_GPIO_PO3 11 /* wake11 */ -#define TEGRA_WAKE_GPIO_PO4 12 /* wake12 */ -#define TEGRA_WAKE_GPIO_PO5 14 /* wake14 */ -#define TEGRA_WAKE_GPIO_PO6 15 /* wake15 */ -#define TEGRA_WAKE_GPIO_PJ5 23 /* wake23 */ -#define TEGRA_WAKE_GPIO_PJ6 24 /* wake24 */ -#define TEGRA_WAKE_GPIO_PJ1 25 /* wake25 */ -#define TEGRA_WAKE_GPIO_PJ2 26 /* wake26 */ -#define TEGRA_WAKE_GPIO_PJ3 27 /* wake27 */ -#define TEGRA_WAKE_GPIO_PJ4 28 /* wake28 */ -#define TEGRA_WAKE_GPIO_PJ0 33 /* wake33 */ -#define TEGRA_WAKE_GPIO_PK2 34 /* wake34 */ -#define TEGRA_WAKE_GPIO_PI6 35 /* wake35 */ -#define TEGRA_WAKE_GPIO_PBB6 45 /* wake45 */ -#define TEGRA_WAKE_GPIO_PR7 49 /* wake49 */ -#define TEGRA_WAKE_GPIO_PR4 50 /* wake50 */ -#define TEGRA_WAKE_GPIO_PQ5 54 /* wake54 */ - -#endif diff --git a/arch/arm/mach-tegra/wakeups-t3.c b/arch/arm/mach-tegra/wakeups-t3.c deleted file mode 100644 index 1aea292b2d64..000000000000 --- a/arch/arm/mach-tegra/wakeups-t3.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/tegra.h> - -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> - -#include "gpio-names.h" -#include "iomap.h" - -static int tegra_gpio_wakes[] = { - TEGRA_GPIO_PO5, /* wake0 */ - TEGRA_GPIO_PV1, /* wake1 */ - TEGRA_GPIO_PL1, /* wake2 */ - TEGRA_GPIO_PB6, /* wake3 */ - TEGRA_GPIO_PN7, /* wake4 */ - TEGRA_GPIO_PBB6, /* wake5 */ - TEGRA_GPIO_PU5, /* wake6 */ - TEGRA_GPIO_PU6, /* wake7 */ - TEGRA_GPIO_PC7, /* wake8 */ - TEGRA_GPIO_PS2, /* wake9 */ - TEGRA_GPIO_PAA1, /* wake10 */ - TEGRA_GPIO_PW3, /* wake11 */ - TEGRA_GPIO_PW2, /* wake12 */ - TEGRA_GPIO_PY6, /* wake13 */ - TEGRA_GPIO_PDD3, /* wake14 */ - TEGRA_GPIO_PJ2, /* wake15 */ - -EINVAL, /* wake16 */ - -EINVAL, /* wake17 */ - -EINVAL, /* wake18 */ - -EINVAL, /* TEGRA_USB1_VBUS, */ /* wake19 */ - -EINVAL, /* TEGRA_USB2_VBUS, */ /* wake20 */ - -EINVAL, /* TEGRA_USB1_ID, */ /* wake21 */ - -EINVAL, /* TEGRA_USB2_ID, */ /* wake22 */ - TEGRA_GPIO_PI5, /* wake23 */ - TEGRA_GPIO_PV0, /* wake24 */ - TEGRA_GPIO_PS4, /* wake25 */ - TEGRA_GPIO_PS5, /* wake26 */ - TEGRA_GPIO_PS0, /* wake27 */ - TEGRA_GPIO_PS6, /* wake28 */ - TEGRA_GPIO_PS7, /* wake29 */ - TEGRA_GPIO_PN2, /* wake30 */ - -EINVAL, /* not used */ /* wake31 */ - TEGRA_GPIO_PO4, /* wake32 */ - TEGRA_GPIO_PJ0, /* wake33 */ - TEGRA_GPIO_PK2, /* wake34 */ - TEGRA_GPIO_PI6, /* wake35 */ - TEGRA_GPIO_PBB1, /* wake36 */ - -EINVAL, /* TEGRA_USB3_VBUS, */ /* wake37 */ - -EINVAL, /* TEGRA_USB3_ID, */ /* wake38 */ - -EINVAL, /* TEGRA_USB1_UTMIP, */ /* wake39 */ - -EINVAL, /* TEGRA_USB2_UTMIP, */ /* wake40 */ - -EINVAL, /* TEGRA_USB3_UTMIP, */ /* wake41 */ -}; - -static int tegra_wake_event_irq[] = { - -EAGAIN, /* wake0 */ - -EAGAIN, /* wake1 */ - -EAGAIN, /* wake2 */ - -EAGAIN, /* wake3 */ - -EAGAIN, /* wake4 */ - -EAGAIN, /* wake5 */ - -EAGAIN, /* wake6 */ - -EAGAIN, /* wake7 */ - -EAGAIN, /* wake8 */ - -EAGAIN, /* wake9 */ - -EAGAIN, /* wake10 */ - -EAGAIN, /* wake11 */ - -EAGAIN, /* wake12 */ - -EAGAIN, /* wake13 */ - -EAGAIN, /* wake14 */ - -EAGAIN, /* wake15 */ - INT_RTC, /* wake16 */ - INT_KBC, /* wake17 */ - INT_EXTERNAL_PMU, /* wake18 */ - -EINVAL, /* TEGRA_USB1_VBUS, */ /* wake19 */ - -EINVAL, /* TEGRA_USB2_VBUS, */ /* wake20 */ - -EINVAL, /* TEGRA_USB1_ID, */ /* wake21 */ - -EINVAL, /* TEGRA_USB2_ID, */ /* wake22 */ - -EAGAIN, /* wake23 */ - -EAGAIN, /* wake24 */ - -EAGAIN, /* wake25 */ - -EAGAIN, /* wake26 */ - -EAGAIN, /* wake27 */ - -EAGAIN, /* wake28 */ - -EAGAIN, /* wake29 */ - -EAGAIN, /* wake30 */ - -EINVAL, /* not used */ /* wake31 */ - -EAGAIN, /* wake32 */ - -EAGAIN, /* wake33 */ - -EAGAIN, /* wake34 */ - -EAGAIN, /* wake35 */ - -EAGAIN, /* wake36 */ - -EINVAL, /* TEGRA_USB3_VBUS, */ /* wake37 */ - -EINVAL, /* TEGRA_USB3_ID, */ /* wake38 */ - INT_USB, /* TEGRA_USB1_UTMIP, */ /* wake39 */ - INT_USB2, /* TEGRA_USB2_UTMIP, */ /* wake40 */ - INT_USB3, /* TEGRA_USB3_UTMIP, */ /* wake41 */ - INT_USB2, /* TEGRA_USB2_UHSIC, */ /* wake42 */ -}; - -static int __init tegra3_wakeup_table_init(void) -{ - tegra_gpio_wake_table = tegra_gpio_wakes; - tegra_irq_wake_table = tegra_wake_event_irq; - tegra_wake_table_len = ARRAY_SIZE(tegra_gpio_wakes); - return 0; -} - -int __init tegra_wakeup_table_init(void) -{ - return tegra3_wakeup_table_init(); -} diff --git a/arch/arm/mach-tegra/wakeups-t3.h b/arch/arm/mach-tegra/wakeups-t3.h deleted file mode 100644 index 6c56698a4399..000000000000 --- a/arch/arm/mach-tegra/wakeups-t3.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * arch/arm/mach-tegra/wakeups-t3.h - * - * Declarations of Tegra 3 LP0 wakeup sources - * - * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MACH_TEGRA_WAKEUPS_T3_H -#define __MACH_TEGRA_WAKEUPS_T3_H - -#ifndef CONFIG_ARCH_TEGRA_3x_SOC -#error "Tegra 3 wakeup sources valid only for CONFIG_ARCH_TEGRA_3x_SOC" -#endif - -#define TEGRA_WAKE_GPIO_PO5 0 -#define TEGRA_WAKE_GPIO_PV1 1 -#define TEGRA_WAKE_GPIO_PL1 2 -#define TEGRA_WAKE_GPIO_PB6 3 -#define TEGRA_WAKE_GPIO_PN7 4 -#define TEGRA_WAKE_GPIO_PBB6 5 -#define TEGRA_WAKE_GPIO_PU5 6 -#define TEGRA_WAKE_GPIO_PU6 7 -#define TEGRA_WAKE_GPIO_PC7 8 -#define TEGRA_WAKE_GPIO_PS2 9 -#define TEGRA_WAKE_GPIO_PAA1 10 -#define TEGRA_WAKE_GPIO_PW3 11 -#define TEGRA_WAKE_GPIO_PW2 12 -#define TEGRA_WAKE_GPIO_PY6 13 -#define TEGRA_WAKE_GPIO_PDD3 14 -#define TEGRA_WAKE_GPIO_PJ2 15 -#define TEGRA_WAKE_RTC_ALARM 16 -#define TEGRA_WAKE_KBC_EVENT 17 -#define TEGRA_WAKE_PWR_INT 18 -#define TEGRA_WAKE_USB1_VBUS 19 -#define TEGRA_WAKE_USB2_VBUS 20 -#define TEGRA_WAKE_USB1_ID 21 -#define TEGRA_WAKE_USB2_ID 22 -#define TEGRA_WAKE_GPIO_PI5 23 -#define TEGRA_WAKE_GPIO_PV0 24 -#define TEGRA_WAKE_GPIO_PS4 25 -#define TEGRA_WAKE_GPIO_PS5 26 -#define TEGRA_WAKE_GPIO_PS0 27 -#define TEGRA_WAKE_GPIO_PS6 28 -#define TEGRA_WAKE_GPIO_PS7 29 -#define TEGRA_WAKE_GPIO_PN2 30 -/* bit 31 is unused */ - -#define TEGRA_WAKE_GPIO_PO4 32 -#define TEGRA_WAKE_GPIO_PJ0 33 -#define TEGRA_WAKE_GPIO_PK2 34 -#define TEGRA_WAKE_GPIO_PI6 35 -#define TEGRA_WAKE_GPIO_PBB1 36 -#define TEGRA_WAKE_USB3_ID 37 -#define TEGRA_WAKE_USB3_VBUS 38 - -#endif diff --git a/arch/arm64/mach-tegra/Kconfig b/arch/arm64/mach-tegra/Kconfig index 45d1d3220c2b..6c5a2a14363f 100644 --- a/arch/arm64/mach-tegra/Kconfig +++ b/arch/arm64/mach-tegra/Kconfig @@ -4,7 +4,6 @@ source arch/arm/mach-tegra/Kconfig config ARCH_TEGRA_13x_SOC bool "Tegra 13x family SOC" - depends on !ARCH_TEGRA_14x_SOC select ARCH_TEGRA_HAS_PCIE select CPU_V8 select DENVER_CPU diff --git a/drivers/platform/tegra/Makefile b/drivers/platform/tegra/Makefile index ef369ad3a0ca..fe619dc3f6f9 100644 --- a/drivers/platform/tegra/Makefile +++ b/drivers/platform/tegra/Makefile @@ -64,9 +64,6 @@ obj-$(CONFIG_ARCH_TEGRA_13x_SOC) += tegra3_throttle.o endif obj-y += latency_allowance.o -obj-y += tegra3_la.o -obj-y += tegra11x_la.o -obj-y += tegra14x_la.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12x_la.o obj-$(CONFIG_ARCH_TEGRA_13x_SOC) += tegra13_speedo.o diff --git a/drivers/platform/tegra/mc/Makefile b/drivers/platform/tegra/mc/Makefile index 31d86edca45d..070569e0a80c 100644 --- a/drivers/platform/tegra/mc/Makefile +++ b/drivers/platform/tegra/mc/Makefile @@ -6,10 +6,7 @@ obj-y += mc.o # MC error reporting. obj-y += mcerr.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += mcerr-t3.o -obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += mcerr-t11.o obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += mcerr-t12.o -obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += mcerr-t14.o ifeq ($(CONFIG_PM_SLEEP),y) obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += mc-timing-t12x.o diff --git a/drivers/platform/tegra/mc/mcerr-t11.c b/drivers/platform/tegra/mc/mcerr-t11.c deleted file mode 100644 index 5cfc1b9b8e22..000000000000 --- a/drivers/platform/tegra/mc/mcerr-t11.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Tegra 11x SoC-specific mcerr code. - * - * Copyright (c) 2010-2014, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <mach/mcerr.h> - -/*** Auto generated by `mcp.pl'. Do not modify! ***/ - -#define dummy_client client("dummy", "dummy") - -struct mc_client mc_clients[] = { - client("ptc", "csr_ptcr"), - client("dc", "csr_display0a"), - client("dcb", "csr_display0ab"), - client("dc", "csr_display0b"), - client("dcb", "csr_display0bb"), - client("dc", "csr_display0c"), - client("dcb", "csr_display0cb"), - dummy_client, - dummy_client, - client("epp", "cbr_eppup"), - client("g2", "cbr_g2pr"), - client("g2", "cbr_g2sr"), - dummy_client, - dummy_client, - dummy_client, - client("avpc", "csr_avpcarm7r"), - client("dc", "csr_displayhc"), - client("dcb", "csr_displayhcb"), - client("nv", "csr_fdcdrd"), - client("nv", "csr_fdcdrd2"), - client("g2", "csr_g2dr"), - client("hda", "csr_hdar"), - client("hc", "csr_host1xdmar"), - client("hc", "csr_host1xr"), - client("nv", "csr_idxsrd"), - dummy_client, - dummy_client, - dummy_client, - client("msenc", "csr_msencsrd"), - client("ppcs", "csr_ppcsahbdmar"), - client("ppcs", "csr_ppcsahbslvr"), - dummy_client, - client("nv", "csr_texl2srd"), - dummy_client, - client("vde", "csr_vdebsevr"), - client("vde", "csr_vdember"), - client("vde", "csr_vdemcer"), - client("vde", "csr_vdetper"), - client("mpcorelp", "csr_mpcorelpr"), - client("mpcore", "csr_mpcorer"), - client("epp", "cbw_eppu"), - client("epp", "cbw_eppv"), - client("epp", "cbw_eppy"), - client("msenc", "csw_msencswr"), - client("vi", "cbw_viwsb"), - client("vi", "cbw_viwu"), - client("vi", "cbw_viwv"), - client("vi", "cbw_viwy"), - client("g2", "ccw_g2dw"), - dummy_client, - client("avpc", "csw_avpcarm7w"), - client("nv", "csw_fdcdwr"), - client("nv", "csw_fdcdwr2"), - client("hda", "csw_hdaw"), - client("hc", "csw_host1xw"), - client("isp", "csw_ispw"), - client("mpcorelp", "csw_mpcorelpw"), - client("mpcore", "csw_mpcorew"), - dummy_client, - client("ppcs", "csw_ppcsahbdmaw"), - client("ppcs", "csw_ppcsahbslvw"), - dummy_client, - client("vde", "csw_vdebsevw"), - client("vde", "csw_vdedbgw"), - client("vde", "csw_vdembew"), - client("vde", "csw_vdetpmw"), - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - client("xusb_host", "csr_xusb_hostr"), - client("xusb_host", "csw_xusb_hostw"), - client("xusb_dev", "csr_xusb_devr"), - client("xusb_dev", "csw_xusb_devw"), - client("nv", "csw_fdcdwr3"), - client("nv", "csr_fdcdrd3"), - client("nv", "csw_fdcdwr4"), - client("nv", "csr_fdcdrd4"), - client("emucif", "csr_emucifr"), - client("emucif", "csw_emucifw"), - client("tsec", "csr_tsecsrd"), - client("tsec", "csw_tsecswr"), -}; -int mc_client_last = ARRAY_SIZE(mc_clients) - 1; -/*** Done. ***/ - -static void mcerr_t11x_info_update(struct mc_client *c, u32 stat) -{ - if (stat & MC_INT_DECERR_EMEM) - c->intr_counts[0]++; - if (stat & MC_INT_SECURITY_VIOLATION) - c->intr_counts[1]++; - if (stat & MC_INT_INVALID_SMMU_PAGE) - c->intr_counts[2]++; - if (stat & MC_INT_DECERR_VPR) - c->intr_counts[3]++; - if (stat & MC_INT_SECERR_SEC) - c->intr_counts[4]++; - - if (stat & ~MC_INT_EN_MASK) - c->intr_counts[5]++; -} - -/* - * T11x reports addresses in a 32 byte range thus we can only give an - * approximate location for the invalid memory request, not the exact address. - */ -static void mcerr_t11x_print(const struct mc_error *err, - const struct mc_client *client, - u32 status, phys_addr_t addr, - int secure, int rw, const char *smmu_info) -{ - pr_err("[mcerr] (%s) %s: %s\n", client->swgid, client->name, err->msg); - pr_err("[mcerr] status = 0x%08x; addr = [0x%08lx -> 0x%08lx]", - status, (ulong)(addr & ~0x1f), (ulong)(addr | 0x1f)); - pr_err("[mcerr] secure: %s, access-type: %s, SMMU fault: %s\n", - secure ? "yes" : "no", rw ? "write" : "read", - smmu_info ? smmu_info : "none"); -} - -#define fmt_hdr "%-18s %-18s %-9s %-9s %-9s %-10s %-10s %-9s\n" -#define fmt_cli "%-18s %-18s %-9u %-9u %-9u %-10u %-10u %-9u\n" -static int mcerr_t11x_debugfs_show(struct seq_file *s, void *v) -{ - int i, j; - int do_print; - - seq_printf(s, fmt_hdr, - "swgid", "client", "decerr", "secerr", "smmuerr", - "decerr-VPR", "secerr-SEC", "unknown"); - for (i = 0; i < ARRAY_SIZE(mc_clients); i++) { - do_print = 0; - if (strcmp(mc_clients[i].name, "dummy") == 0) - continue; - /* Only print clients who actually have errors. */ - for (j = 0; j < INTR_COUNT; j++) { - if (mc_clients[i].intr_counts[j]) { - do_print = 1; - break; - } - } - if (do_print) - seq_printf(s, fmt_cli, - mc_clients[i].swgid, - mc_clients[i].name, - mc_clients[i].intr_counts[0], - mc_clients[i].intr_counts[1], - mc_clients[i].intr_counts[2], - mc_clients[i].intr_counts[3], - mc_clients[i].intr_counts[4], - mc_clients[i].intr_counts[5]); - } - return 0; -} - -/* - * Set up chip specific functions and data for handling this particular chip's - * error decoding and logging. - */ -void mcerr_chip_specific_setup(struct mcerr_chip_specific *spec) -{ - spec->mcerr_print = mcerr_t11x_print; - spec->mcerr_info_update = mcerr_t11x_info_update; - spec->mcerr_debugfs_show = mcerr_t11x_debugfs_show; - spec->nr_clients = ARRAY_SIZE(mc_clients); - return; -} diff --git a/drivers/platform/tegra/mc/mcerr-t14.c b/drivers/platform/tegra/mc/mcerr-t14.c deleted file mode 100644 index 4400f8a4e7af..000000000000 --- a/drivers/platform/tegra/mc/mcerr-t14.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Tegra 14x SoC-specific mcerr code. - * - * Copyright (c) 2012-2014, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <mach/mcerr.h> - -/*** Auto generated by `mcp.pl'. Do not modify! ***/ - -#define dummy_client client("dummy", "dummy") - -struct mc_client mc_clients[] = { - client("ptc", "csr_ptcr"), - client("dc", "csr_display0a"), - client("dcb", "cbr_display0ab"), - client("dc", "csr_display0b"), - client("dcb", "csr_display0bb"), - client("dc", "csr_display0c"), - client("dcb", "cbr_display0cb"), - dummy_client, - dummy_client, - client("epp", "cbr_eppup"), - client("g2", "cbr_g2pr"), - client("g2", "cbr_g2sr"), - dummy_client, - dummy_client, - dummy_client, - client("avpc", "csr_avpcarm7r"), - client("dc", "csr_displayhc"), - client("dcb", "csr_displayhcb"), - client("nv", "csr_fdcdrd"), - client("nv", "csr_fdcdrd2"), - client("g2", "csr_g2dr"), - client("hda", "csr_hdar"), - client("hc", "csr_host1xdmar"), - client("hc", "csr_host1xr"), - client("nv", "csr_idxsrd"), - dummy_client, - dummy_client, - dummy_client, - client("msenc", "csr_msencsrd"), - client("ppcs", "csr_ppcsahbdmar"), - client("ppcs", "csr_ppcsahbslvr"), - dummy_client, - client("nv", "csr_texl2srd"), - dummy_client, - client("vde", "csr_vdebsevr"), - client("vde", "csr_vdember"), - client("vde", "csr_vdemcer"), - client("vde", "csr_vdetper"), - client("mpcorelp", "csr_mpcorelpr"), - client("mpcore", "csr_mpcorer"), - client("epp", "cbw_eppu"), - client("epp", "cbw_eppv"), - client("epp", "cbw_eppy"), - client("msenc", "csw_msencswr"), - client("vi", "cbw_viwsb"), - client("vi", "cbw_viwu"), - client("vi", "cbw_viwv"), - client("vi", "cbw_viwy"), - client("g2", "ccw_g2dw"), - dummy_client, - client("avpc", "csw_avpcarm7w"), - client("nv", "csw_fdcdwr"), - client("nv", "csw_fdcdwr2"), - client("hda", "csw_hdaw"), - client("hc", "csw_host1xw"), - client("isp", "csw_ispw"), - client("mpcorelp", "csw_mpcorelpw"), - client("mpcore", "csw_mpcorew"), - dummy_client, - client("ppcs", "csw_ppcsahbdmaw"), - client("ppcs", "csw_ppcsahbslvw"), - dummy_client, - client("vde", "csw_vdebsevw"), - client("vde", "csw_vdedbgw"), - client("vde", "csw_vdembew"), - client("vde", "csw_vdetpmw"), - dummy_client, - dummy_client, - client("isp", "csr_ispra"), - dummy_client, - client("isp", "csw_ispwa"), - client("isp", "csw_ispwb"), - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - dummy_client, - client("emucif", "csr_emucifr"), - client("emucif", "csw_emucifw"), - client("tsec", "csr_tsecsrd"), - client("tsec", "csw_tsecswr"), - client("vi", "csw_viw"), - client("bbmci", "csr_bbcr"), - client("bbmci", "csw_bbcw"), - client("bbmcill", "csr_bbcllr"), - client("dc", "csr_displayt"), - dummy_client, - client("dc", "csr_displayd"), -}; -int mc_client_last = ARRAY_SIZE(mc_clients) - 1; -/*** Done. ***/ - -static void mcerr_t14x_info_update(struct mc_client *c, u32 stat) -{ - if (stat & MC_INT_DECERR_EMEM) - c->intr_counts[0]++; - if (stat & MC_INT_SECURITY_VIOLATION) - c->intr_counts[1]++; - if (stat & MC_INT_INVALID_SMMU_PAGE) - c->intr_counts[2]++; - if (stat & MC_INT_DECERR_VPR) - c->intr_counts[3]++; - if (stat & MC_INT_SECERR_SEC) - c->intr_counts[4]++; - if (stat & MC_INT_BBC_PRIVATE_MEM_VIOLATION) - c->intr_counts[5]++; - if (stat & MC_INT_DECERR_BBC) - c->intr_counts[6]++; - - if (stat & ~MC_INT_EN_MASK) - c->intr_counts[7]++; -} - -#define fmt_hdr "%-18s %-18s %-9s %-9s %-9s %-10s %-10s %-9s %-9s %-9s\n" -#define fmt_cli "%-18s %-18s %-9u %-9u %-9u %-10u %-10u %-9u %-9u %-9u\n"; -static int mcerr_t14x_debugfs_show(struct seq_file *s, void *v) -{ - int i, j; - int do_print; - - seq_printf(s, fmt_hdr, - "swgid", "client", "decerr", "secerr", "smmuerr", - "decerr-VPR", "secerr-SEC", "priv-bbc", "decerr-bbc", - "unknown"); - for (i = 0; i < ARRAY_SIZE(mc_clients); i++) { - do_print = 0; - if (strcmp(mc_clients[i].name, "dummy") == 0) - continue; - /* Only print clients who actually have errors. */ - for (j = 0; j < INTR_COUNT; j++) { - if (mc_clients[i].intr_counts[j]) { - do_print = 1; - break; - } - } - if (do_print) - seq_printf(s, fmt_cli, - mc_clients[i].swgid, - mc_clients[i].name, - mc_clients[i].intr_counts[0], - mc_clients[i].intr_counts[1], - mc_clients[i].intr_counts[2], - mc_clients[i].intr_counts[3], - mc_clients[i].intr_counts[4], - mc_clients[i].intr_counts[5], - mc_clients[i].intr_counts[6], - mc_clients[i].intr_counts[7]); - } - return 0; -} - -/* - * Set up chip specific functions and data for handling this particular chip's - * error decoding and logging. - */ -void mcerr_chip_specific_setup(struct mcerr_chip_specific *spec) -{ - spec->mcerr_info_update = mcerr_t14x_info_update; - spec->mcerr_debugfs_show = mcerr_t14x_debugfs_show; - spec->nr_clients = ARRAY_SIZE(mc_clients); - return; -} diff --git a/drivers/platform/tegra/mc/mcerr-t3.c b/drivers/platform/tegra/mc/mcerr-t3.c deleted file mode 100644 index 50118f726879..000000000000 --- a/drivers/platform/tegra/mc/mcerr-t3.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Tegra 3 SoC-specific mcerr code. - * - * Copyright (c) 2010-2014, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <mach/mcerr.h> - -/*** Auto generated by `mcp.pl'. Do not modify! ***/ - -#define dummy_client client("dummy", "dummy") - -struct mc_client mc_clients[] = { - client("ptc", "csr_ptcr"), - client("dc", "cbr_display0a"), - client("dcb", "cbr_display0ab"), - client("dc", "cbr_display0b"), - client("dcb", "cbr_display0bb"), - client("dc", "cbr_display0c"), - client("dcb", "cbr_display0cb"), - client("dc", "cbr_display1b"), - client("dcb", "cbr_display1bb"), - client("epp", "cbr_eppup"), - client("g2", "cbr_g2pr"), - client("g2", "cbr_g2sr"), - client("mpe", "cbr_mpeunifbr"), - client("vi", "cbr_viruv"), - client("afi", "csr_afir"), - client("avpc", "csr_avpcarm7r"), - client("dc", "csr_displayhc"), - client("dcb", "csr_displayhcb"), - client("nv", "csr_fdcdrd"), - client("nv2", "csr_fdcdrd2"), - client("g2", "csr_g2dr"), - client("hda", "csr_hdar"), - client("hc", "csr_host1xdmar"), - client("hc", "csr_host1xr"), - client("nv", "csr_idxsrd"), - client("nv2", "csr_idxsrd2"), - client("mpe", "csr_mpe_ipred"), - client("mpe", "csr_mpeamemrd"), - client("mpe", "csr_mpecsrd"), - client("ppcs", "csr_ppcsahbdmar"), - client("ppcs", "csr_ppcsahbslvr"), - client("sata", "csr_satar"), - client("nv", "csr_texsrd"), - client("nv2", "csr_texsrd2"), - client("vde", "csr_vdebsevr"), - client("vde", "csr_vdember"), - client("vde", "csr_vdemcer"), - client("vde", "csr_vdetper"), - client("mpcorelp", "csr_mpcorelpr"), - client("mpcore", "csr_mpcorer"), - client("epp", "cbw_eppu"), - client("epp", "cbw_eppv"), - client("epp", "cbw_eppy"), - client("mpe", "cbw_mpeunifbw"), - client("vi", "cbw_viwsb"), - client("vi", "cbw_viwu"), - client("vi", "cbw_viwv"), - client("vi", "cbw_viwy"), - client("g2", "ccw_g2dw"), - client("afi", "csw_afiw"), - client("avpc", "csw_avpcarm7w"), - client("nv", "csw_fdcdwr"), - client("nv2", "csw_fdcdwr2"), - client("hda", "csw_hdaw"), - client("hc", "csw_host1xw"), - client("isp", "csw_ispw"), - client("mpcorelp", "csw_mpcorelpw"), - client("mpcore", "csw_mpcorew"), - client("mpe", "csw_mpecswr"), - client("ppcs", "csw_ppcsahbdmaw"), - client("ppcs", "csw_ppcsahbslvw"), - client("sata", "csw_sataw"), - client("vde", "csw_vdebsevw"), - client("vde", "csw_vdedbgw"), - client("vde", "csw_vdembew"), - client("vde", "csw_vdetpmw"), -}; -int mc_client_last = ARRAY_SIZE(mc_clients) - 1; -/*** Done. ***/ - -/* - * Defaults work for T30. - */ -void mcerr_chip_specific_setup(struct mcerr_chip_specific *spec) -{ - return; -} diff --git a/drivers/platform/tegra/tegra11x_la.c b/drivers/platform/tegra/tegra11x_la.c deleted file mode 100644 index 36b136a47651..000000000000 --- a/drivers/platform/tegra/tegra11x_la.c +++ /dev/null @@ -1,2 +0,0 @@ -/* Automatically generated file; DO NOT EDIT. */ -#include "../../../arch/arm/mach-tegra/tegra11x_la.c" diff --git a/drivers/platform/tegra/tegra14x_la.c b/drivers/platform/tegra/tegra14x_la.c deleted file mode 100644 index dad4e31b5498..000000000000 --- a/drivers/platform/tegra/tegra14x_la.c +++ /dev/null @@ -1,2 +0,0 @@ -/* Automatically generated file; DO NOT EDIT. */ -#include "../../../arch/arm/mach-tegra/tegra14x_la.c" diff --git a/drivers/platform/tegra/tegra3_la.c b/drivers/platform/tegra/tegra3_la.c deleted file mode 100644 index e7f2bd2c4a78..000000000000 --- a/drivers/platform/tegra/tegra3_la.c +++ /dev/null @@ -1,2 +0,0 @@ -/* Automatically generated file; DO NOT EDIT. */ -#include "../../../arch/arm/mach-tegra/tegra3_la.c" diff --git a/drivers/platform/tegra/timer-t3.c b/drivers/platform/tegra/timer-t3.c deleted file mode 100644 index ddfb1511aa7f..000000000000 --- a/drivers/platform/tegra/timer-t3.c +++ /dev/null @@ -1,2 +0,0 @@ -/* Automatically generated file; DO NOT EDIT. */ -#include "../../../arch/arm/mach-tegra/timer-t3.c" diff --git a/firmware/Makefile b/firmware/Makefile index ecac840a1613..cbb09ce9730a 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -136,9 +136,6 @@ fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin -fw-shipped-$(CONFIG_MACH_ROTH) += p2454-uc.fw -fw-shipped-$(CONFIG_MACH_ROTH) += p2560-uc.fw - fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) # Directories which we _might_ need to create, so we have a rule for them. diff --git a/firmware/p2454-uc.HEX b/firmware/p2454-uc.HEX deleted file mode 100644 index 99c9f1da3cb9..000000000000 --- a/firmware/p2454-uc.HEX +++ /dev/null @@ -1,261 +0,0 @@ -:40000000407d0068303030307e3030307e3030307d3a3c7e7e3030307e3030307e3030307d34f07e7d268a7e7e3030307d3aba7e7d3acd7e7d08247e7d3a3f7e7d3a517e3a -:400040007d3a607e7d3a6f7e7d3a7e7e7d3a8d7e7d3a9c7e7d3aab7e7d3ace7e7d0e647e303030303030303040711062e30070ef62e33850804e711062010f62000f620962 -:400080006162082070ef6200ff62083e4100fe5d0021603960a0416200fd5d0021403940a0366200fb5d0821203920a02b6200f75d0821203920a020620c007110620dfe4f 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0; #endif - /* Overwrite above code using board id */ - if (board_info.board_id == BOARD_E1690) { - test_value = 0; - } else { /* ERS */ - test_value = 4; - } if ((reg & M97236_JACKSW_MASK) == test_value) { schedule_delayed_work(&max97236->jack_work, diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig index 31652893fcd6..47ed21d7e7ec 100644 --- a/sound/soc/tegra/Kconfig +++ b/sound/soc/tegra/Kconfig @@ -298,7 +298,7 @@ config SND_SOC_TEGRA_RT5640 help Say Y or M here if you want to add support for SoC audio on Tegra boards using the ALC5640 codec. Currently, the supported boards - are Kai,Cardhu,Dalmore and Macallan. + are Kai,Cardhu and Dalmore. config MACH_HAS_SND_SOC_TEGRA_RT5645 bool |