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-rw-r--r--drivers/net/wireless/Kconfig1
-rw-r--r--drivers/net/wireless/Makefile2
-rw-r--r--drivers/net/wireless/ath6kl/Kconfig149
-rw-r--r--drivers/net/wireless/ath6kl/Makefile138
-rw-r--r--drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h51
-rw-r--r--drivers/net/wireless/ath6kl/bmi/src/bmi.c984
-rw-r--r--drivers/net/wireless/ath6kl/bmi/src/makefile22
-rw-r--r--drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h88
-rw-r--r--drivers/net/wireless/ath6kl/hif/sdio/Makefile86
-rw-r--r--drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h128
-rw-r--r--drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt35
-rw-r--r--drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c1010
-rw-r--r--drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c390
-rw-r--r--drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c1399
-rw-r--r--drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h383
-rw-r--r--drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c762
-rw-r--r--drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c752
-rw-r--r--drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c1255
-rw-r--r--drivers/net/wireless/ath6kl/htc2/AR6000/makefile22
-rw-r--r--drivers/net/wireless/ath6kl/htc2/htc.c558
-rw-r--r--drivers/net/wireless/ath6kl/htc2/htc_debug.h34
-rw-r--r--drivers/net/wireless/ath6kl/htc2/htc_internal.h213
-rw-r--r--drivers/net/wireless/ath6kl/htc2/htc_recv.c1545
-rw-r--r--drivers/net/wireless/ath6kl/htc2/htc_send.c1019
-rw-r--r--drivers/net/wireless/ath6kl/htc2/htc_services.c444
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h57
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h47
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/addrs.h86
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h83
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h1951
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h32
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h996
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h405
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h500
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h1182
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h205
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h346
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h95
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h83
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h1951
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h32
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h996
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h405
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h500
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h1182
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h205
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h346
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h95
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h3287
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h3670
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h33
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h36
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h44
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h7072
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h104
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h1249
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h1090
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h587
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h3061
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h33
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h556
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h518
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h634
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h560
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h971
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h2061
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h205
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h256
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h33
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h318
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h163
-rw-r--r--drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h191
-rw-r--r--drivers/net/wireless/ath6kl/include/a_config.h45
-rw-r--r--drivers/net/wireless/ath6kl/include/a_debug.h215
-rw-r--r--drivers/net/wireless/ath6kl/include/a_drv.h46
-rw-r--r--drivers/net/wireless/ath6kl/include/a_drv_api.h228
-rw-r--r--drivers/net/wireless/ath6kl/include/a_hci.h668
-rw-r--r--drivers/net/wireless/ath6kl/include/a_osapi.h53
-rw-r--r--drivers/net/wireless/ath6kl/include/a_types.h50
-rw-r--r--drivers/net/wireless/ath6kl/include/aggr_recv_api.h136
-rw-r--r--drivers/net/wireless/ath6kl/include/ar3kconfig.h58
-rw-r--r--drivers/net/wireless/ath6kl/include/ar6000_api.h50
-rw-r--r--drivers/net/wireless/ath6kl/include/ar6000_diag.h44
-rw-r--r--drivers/net/wireless/ath6kl/include/ar6kap_common.h40
-rw-r--r--drivers/net/wireless/ath6kl/include/athbtfilter.h129
-rw-r--r--drivers/net/wireless/ath6kl/include/athdefs.h80
-rw-r--r--drivers/net/wireless/ath6kl/include/athendpack.h48
-rw-r--r--drivers/net/wireless/ath6kl/include/athstartpack.h47
-rw-r--r--drivers/net/wireless/ath6kl/include/bmi.h128
-rw-r--r--drivers/net/wireless/ath6kl/include/bmi_msg.h231
-rw-r--r--drivers/net/wireless/ath6kl/include/btcoexGpio.h68
-rw-r--r--drivers/net/wireless/ath6kl/include/cnxmgmt.h32
-rw-r--r--drivers/net/wireless/ath6kl/include/common_drv.h90
-rw-r--r--drivers/net/wireless/ath6kl/include/dbglog.h122
-rw-r--r--drivers/net/wireless/ath6kl/include/dbglog_api.h48
-rw-r--r--drivers/net/wireless/ath6kl/include/dbglog_id.h530
-rw-r--r--drivers/net/wireless/ath6kl/include/discovery.h71
-rw-r--r--drivers/net/wireless/ath6kl/include/dl_list.h149
-rw-r--r--drivers/net/wireless/ath6kl/include/dset_api.h61
-rw-r--r--drivers/net/wireless/ath6kl/include/dset_internal.h51
-rw-r--r--drivers/net/wireless/ath6kl/include/dsetid.h122
-rw-r--r--drivers/net/wireless/ath6kl/include/epping_test.h115
-rw-r--r--drivers/net/wireless/ath6kl/include/gmboxif.h73
-rw-r--r--drivers/net/wireless/ath6kl/include/gpio.h43
-rw-r--r--drivers/net/wireless/ath6kl/include/gpio_api.h55
-rw-r--r--drivers/net/wireless/ath6kl/include/hci_transport_api.h243
-rw-r--r--drivers/net/wireless/ath6kl/include/hif.h421
-rw-r--r--drivers/net/wireless/ath6kl/include/host_version.h48
-rw-r--r--drivers/net/wireless/ath6kl/include/htc.h232
-rw-r--r--drivers/net/wireless/ath6kl/include/htc_api.h568
-rw-r--r--drivers/net/wireless/ath6kl/include/htc_packet.h223
-rw-r--r--drivers/net/wireless/ath6kl/include/htc_services.h48
-rw-r--r--drivers/net/wireless/ath6kl/include/ini_dset.h80
-rw-r--r--drivers/net/wireless/ath6kl/include/pkt_log.h41
-rw-r--r--drivers/net/wireless/ath6kl/include/regdump.h45
-rw-r--r--drivers/net/wireless/ath6kl/include/roaming.h37
-rw-r--r--drivers/net/wireless/ath6kl/include/targaddrs.h232
-rw-r--r--drivers/net/wireless/ath6kl/include/target_reg_table.h236
-rw-r--r--drivers/net/wireless/ath6kl/include/testcmd.h179
-rw-r--r--drivers/net/wireless/ath6kl/include/wlan_api.h122
-rw-r--r--drivers/net/wireless/ath6kl/include/wlan_defs.h75
-rw-r--r--drivers/net/wireless/ath6kl/include/wlan_dset.h30
-rw-r--r--drivers/net/wireless/ath6kl/include/wmi.h3053
-rw-r--r--drivers/net/wireless/ath6kl/include/wmi_api.h435
-rw-r--r--drivers/net/wireless/ath6kl/include/wmi_thin.h343
-rw-r--r--drivers/net/wireless/ath6kl/include/wmix.h275
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c432
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c506
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h74
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c972
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h156
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/common_drv.c973
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/credit_dist.c375
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/makefile22
-rw-r--r--drivers/net/wireless/ath6kl/miscdrv/miscdrv.h40
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/ar6000_android.c621
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c6311
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c455
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/cfg80211.c1467
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/eeprom.c581
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c119
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/hci_bridge.c1126
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h694
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h175
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h1202
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/athendpack_linux.h0
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/athstartpack_linux.h0
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h47
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h46
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/config_linux.h54
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h45
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h70
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h174
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h361
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h50
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h281
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/ioctl.c4559
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/netbuf.c233
-rw-r--r--drivers/net/wireless/ath6kl/os/linux/wireless_ext.c2703
-rw-r--r--drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h112
-rw-r--r--drivers/net/wireless/ath6kl/reorder/makefile22
-rw-r--r--drivers/net/wireless/ath6kl/reorder/rcv_aggr.c662
-rw-r--r--drivers/net/wireless/ath6kl/wlan/include/ieee80211.h397
-rw-r--r--drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h81
-rw-r--r--drivers/net/wireless/ath6kl/wlan/src/makefile22
-rw-r--r--drivers/net/wireless/ath6kl/wlan/src/wlan_node.c569
-rw-r--r--drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c196
-rw-r--r--drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c57
-rw-r--r--drivers/net/wireless/ath6kl/wmi/makefile22
-rw-r--r--drivers/net/wireless/ath6kl/wmi/wmi.c6536
-rw-r--r--drivers/net/wireless/ath6kl/wmi/wmi_host.h78
171 files changed, 94552 insertions, 0 deletions
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 5bc00db21b24..32ec9aafa39d 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -503,5 +503,6 @@ source "drivers/net/wireless/rt2x00/Kconfig"
source "drivers/net/wireless/orinoco/Kconfig"
source "drivers/net/wireless/wl12xx/Kconfig"
source "drivers/net/wireless/iwmc3200wifi/Kconfig"
+source "drivers/net/wireless/ath6kl/Kconfig"
endmenu
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 7a4647e78fd3..a1a2df3973a5 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -62,3 +62,5 @@ obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o
obj-$(CONFIG_WL12XX) += wl12xx/
obj-$(CONFIG_IWM) += iwmc3200wifi/
+
+obj-$(CONFIG_ATH6K_LEGACY) += ath6kl/
diff --git a/drivers/net/wireless/ath6kl/Kconfig b/drivers/net/wireless/ath6kl/Kconfig
new file mode 100644
index 000000000000..cc0e5e3a5cad
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/Kconfig
@@ -0,0 +1,149 @@
+config ATH6K_LEGACY
+ tristate "Atheros AR600x support (non mac80211)"
+ depends on MMC
+ depends on WLAN_80211
+ help
+ This module adds support for wireless adapters based on Atheros AR600x chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl.
+
+choice
+ prompt "AR600x Board Data Configuration"
+ depends on ATH6K_LEGACY
+ default AR600x_SD31_XXX
+ help
+ Select the appropriate board data template from the list below that matches your AR600x based reference design.
+
+config AR600x_SD31_XXX
+ bool "SD31-xxx"
+ help
+ Board Data file for a standard SD31 reference design (File: bdata.SD31.bin)
+
+config AR600x_WB31_XXX
+ bool "WB31-xxx"
+ help
+ Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin)
+
+config AR600x_SD32_XXX
+ bool "SD32-xxx"
+ help
+ Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin)
+
+config AR600x_CUSTOM_XXX
+ bool "CUSTOM-xxx"
+ help
+ Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin)
+endchoice
+
+config ATH6KL_ENABLE_COEXISTENCE
+ bool "BT Coexistence support"
+ depends on ATH6K_LEGACY
+ help
+ Enables WLAN/BT coexistence support. Select the apprpriate configuration from below.
+
+choice
+ prompt "Front-End Antenna Configuration"
+ depends on ATH6KL_ENABLE_COEXISTENCE
+ default AR600x_DUAL_ANTENNA
+ help
+ Select the appropriate configuration from the list below that matches your AR600x based reference design.
+
+config AR600x_DUAL_ANTENNA
+ bool "Dual Antenna"
+ help
+ Dual Antenna Design
+
+config AR600x_SINGLE_ANTENNA
+ bool "Single Antenna"
+ help
+ Single Antenna Design
+endchoice
+
+choice
+ prompt "Collocated Bluetooth Type"
+ depends on ATH6KL_ENABLE_COEXISTENCE
+ default AR600x_BT_AR3001
+ help
+ Select the appropriate configuration from the list below that matches your AR600x based reference design.
+
+config AR600x_BT_QCOM
+ bool "Qualcomm BTS4020X"
+ help
+ Qualcomm BT (3 Wire PTA)
+
+config AR600x_BT_CSR
+ bool "CSR BC06"
+ help
+ CSR BT (3 Wire PTA)
+
+config AR600x_BT_AR3001
+ bool "Atheros AR3001"
+ help
+ Atheros BT (3 Wire PTA)
+endchoice
+
+config ATH6KL_HCI_BRIDGE
+ bool "HCI over SDIO support"
+ depends on ATH6K_LEGACY
+ help
+ Enables BT over SDIO. Applicable only for combo designs (eg: WB31)
+
+config ATH6KL_CONFIG_GPIO_BT_RESET
+ bool "Configure BT Reset GPIO"
+ depends on ATH6KL_HCI_BRIDGE
+ help
+ Configure a WLAN GPIO for use with BT.
+
+config AR600x_BT_RESET_PIN
+ int "GPIO"
+ depends on ATH6KL_CONFIG_GPIO_BT_RESET
+ default 22
+ help
+ WLAN GPIO to be used for resetting BT
+
+config ATH6KL_CFG80211
+ bool "CFG80211 support"
+ depends on ATH6K_LEGACY
+ help
+ Enables support for CFG80211 APIs
+
+config ATH6KL_HTC_RAW_INTERFACE
+ bool "RAW HTC support"
+ depends on ATH6K_LEGACY
+ help
+ Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface
+
+config ATH6KL_VIRTUAL_SCATTER_GATHER
+ bool "Virtual Scatter-Gather support"
+ depends on ATH6K_LEGACY
+ help
+ Enables virtual scatter gather support for the hardware that does not support it natively.
+
+config ATH6KL_DEBUG
+ bool "Debug support"
+ depends on ATH6K_LEGACY
+ help
+ Enables debug support
+
+config ATH6KL_ENABLE_HOST_DEBUG
+ bool "Host Debug support"
+ depends on ATH6KL_DEBUG
+ help
+ Enables debug support in the driver
+
+config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
+ bool "Target Debug support - Enable UART prints"
+ depends on ATH6KL_DEBUG
+ help
+ Enables uart prints
+
+config AR600x_DEBUG_UART_TX_PIN
+ int "GPIO"
+ depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
+ default 8
+ help
+ WLAN GPIO to be used for Debug UART (Tx)
+
+config ATH6KL_DISABLE_TARGET_DBGLOGS
+ bool "Target Debug support - Disable Debug logs"
+ depends on ATH6KL_DEBUG
+ help
+ Enables debug logs
diff --git a/drivers/net/wireless/ath6kl/Makefile b/drivers/net/wireless/ath6kl/Makefile
new file mode 100644
index 000000000000..b839dc5c54c5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/Makefile
@@ -0,0 +1,138 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
+#
+# $ATH_LICENSE_HOSTSDK0_C$
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+
+ccflags-y += -I$(obj)/include
+ccflags-y += -I$(obj)/wlan/include
+ccflags-y += -I$(obj)/os/linux/include
+ccflags-y += -I$(obj)/os
+ccflags-y += -I$(obj)/bmi/include
+ccflags-y += -I$(obj)/include/AR6002/hw4.0
+
+ifeq ($(CONFIG_AR600x_SD31_XXX),y)
+ccflags-y += -DAR600x_SD31_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_WB31_XXX),y)
+ccflags-y += -DAR600x_WB31_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_SD32_XXX),y)
+ccflags-y += -DAR600x_SD32_XXX
+endif
+
+ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y)
+ccflags-y += -DAR600x_CUSTOM_XXX
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y)
+ccflags-y += -DENABLE_COEXISTENCE
+endif
+
+ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
+ccflags-y += -DAR600x_DUAL_ANTENNA
+endif
+
+ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y)
+ccflags-y += -DAR600x_SINGLE_ANTENNA
+endif
+
+ifeq ($(CONFIG_AR600x_BT_QCOM),y)
+ccflags-y += -DAR600x_BT_QCOM
+endif
+
+ifeq ($(CONFIG_AR600x_BT_CSR),y)
+ccflags-y += -DAR600x_BT_CSR
+endif
+
+ifeq ($(CONFIG_AR600x_BT_AR3001),y)
+ccflags-y += -DAR600x_BT_AR3001
+endif
+
+ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y)
+ccflags-y += -DATH_AR6K_ENABLE_GMBOX
+ccflags-y += -DHCI_TRANSPORT_SDIO
+ccflags-y += -DSETUPHCI_ENABLED
+ccflags-y += -DSETUPBTDEV_ENABLED
+ath6kl-y += htc2/AR6000/ar6k_gmbox.o
+ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o
+ath6kl-y += miscdrv/ar3kconfig.o
+ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o
+ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o
+endif
+
+ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
+ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
+endif
+
+ifeq ($(CONFIG_ATH6KL_CFG80211),y)
+ccflags-y += -DATH6K_CONFIG_CFG80211
+ath6kl-y += os/linux/cfg80211.o
+endif
+
+ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
+ccflags-y += -DHTC_RAW_INTERFACE
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y)
+ccflags-y += -DDEBUG
+endif
+
+ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y)
+ccflags-y += -DENABLEUARTPRINT_SET
+endif
+
+ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y)
+ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS
+endif
+
+ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y)
+ccflags-y += -DATH6K_CONFIG_HIF_VIRTUAL_SCATTER
+endif
+
+ccflags-y += -DLINUX -DKERNEL_2_6
+ccflags-y += -DTCMD
+ccflags-y += -DSEND_EVENT_TO_APP
+ccflags-y += -DUSER_KEYS
+ccflags-y += -DNO_SYNC_FLUSH
+ccflags-y += -DHTC_EP_STAT_PROFILING
+ccflags-y += -DATH_AR6K_11N_SUPPORT
+ccflags-y += -DWAPI_ENABLE
+ccflags-y += -DCHECKSUM_OFFLOAD
+ccflags-y += -DWLAN_HEADERS
+ccflags-y += -DINIT_MODE_DRV_ENABLED
+ccflags-y += -DBMIENABLE_SET
+
+obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
+ath6kl-y += htc2/AR6000/ar6k.o
+ath6kl-y += htc2/AR6000/ar6k_events.o
+ath6kl-y += htc2/htc_send.o
+ath6kl-y += htc2/htc_recv.o
+ath6kl-y += htc2/htc_services.o
+ath6kl-y += htc2/htc.o
+ath6kl-y += bmi/src/bmi.o
+ath6kl-y += os/linux/ar6000_drv.o
+ath6kl-y += os/linux/ar6000_raw_if.o
+ath6kl-y += os/linux/netbuf.o
+ath6kl-y += os/linux/wireless_ext.o
+ath6kl-y += os/linux/ioctl.o
+ath6kl-y += os/linux/hci_bridge.o
+ath6kl-y += miscdrv/common_drv.o
+ath6kl-y += miscdrv/credit_dist.o
+ath6kl-y += wmi/wmi.o
+ath6kl-y += reorder/rcv_aggr.o
+ath6kl-y += wlan/src/wlan_node.o
+ath6kl-y += wlan/src/wlan_recv_beacon.o
+ath6kl-y += wlan/src/wlan_utils.o
+
+# ATH_HIF_TYPE := sdio
+ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include
+ccflags-y += -DSDIO
+ath6kl-y += hif/sdio/linux_sdio/src/hif.o
+ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o
diff --git a/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h b/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h
new file mode 100644
index 000000000000..729e3a6ac54d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h
@@ -0,0 +1,51 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi_internal.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef BMI_INTERNAL_H
+#define BMI_INTERNAL_H
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME bmi
+#include "a_debug.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "bmi_msg.h"
+
+#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+
+#define BMI_COMMUNICATION_TIMEOUT 100000
+
+/* ------ Global Variable Declarations ------- */
+A_BOOL bmiDone;
+
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_BOOL want_timeout);
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/bmi/src/bmi.c b/drivers/net/wireless/ath6kl/bmi/src/bmi.c
new file mode 100644
index 000000000000..4fe280a06478
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/bmi/src/bmi.c
@@ -0,0 +1,984 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#include "hif.h"
+#include "bmi.h"
+#include "htc_api.h"
+#include "bmi_internal.h"
+
+#ifdef DEBUG
+static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
+ { ATH_DEBUG_BMI , "BMI Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
+ "bmi",
+ "Boot Manager Interface",
+ ATH_DEBUG_MASK_DEFAULTS,
+ ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
+ bmi_debug_desc);
+
+#endif
+
+/*
+Although we had envisioned BMI to run on top of HTC, this is not how the
+final implementation ended up. On the Target side, BMI is a part of the BSP
+and does not use the HTC protocol nor even DMA -- it is intentionally kept
+very simple.
+*/
+
+static A_BOOL pendingEventsFuncCheck = FALSE;
+static A_UINT32 *pBMICmdCredits;
+static A_UCHAR *pBMICmdBuf;
+#define MAX_BMI_CMDBUF_SZ (BMI_DATASZ_MAX + \
+ sizeof(A_UINT32) /* cmd */ + \
+ sizeof(A_UINT32) /* addr */ + \
+ sizeof(A_UINT32))/* length */
+#define BMI_COMMAND_FITS(sz) ((sz) <= MAX_BMI_CMDBUF_SZ)
+
+/* APIs visible to the driver */
+void
+BMIInit(void)
+{
+ bmiDone = FALSE;
+ pendingEventsFuncCheck = FALSE;
+
+ /*
+ * On some platforms, it's not possible to DMA to a static variable
+ * in a device driver (e.g. Linux loadable driver module).
+ * So we need to A_MALLOC space for "command credits" and for commands.
+ *
+ * Note: implicitly relies on A_MALLOC to provide a buffer that is
+ * suitable for DMA (or PIO). This buffer will be passed down the
+ * bus stack.
+ */
+ if (!pBMICmdCredits) {
+ pBMICmdCredits = (A_UINT32 *)A_MALLOC_NOWAIT(4);
+ A_ASSERT(pBMICmdCredits);
+ }
+
+ if (!pBMICmdBuf) {
+ pBMICmdBuf = (A_UCHAR *)A_MALLOC_NOWAIT(MAX_BMI_CMDBUF_SZ);
+ A_ASSERT(pBMICmdBuf);
+ }
+
+ A_REGISTER_MODULE_DEBUG_INFO(bmi);
+}
+
+A_STATUS
+BMIDone(HIF_DEVICE *device)
+{
+ A_STATUS status;
+ A_UINT32 cid;
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
+ return A_OK;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
+ bmiDone = TRUE;
+ cid = BMI_DONE;
+
+ status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ if (pBMICmdCredits) {
+ A_FREE(pBMICmdCredits);
+ pBMICmdCredits = NULL;
+ }
+
+ if (pBMICmdBuf) {
+ A_FREE(pBMICmdBuf);
+ pBMICmdBuf = NULL;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info)
+{
+ A_STATUS status;
+ A_UINT32 cid;
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device));
+ cid = BMI_GET_TARGET_INFO;
+
+ status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver,
+ sizeof(targ_info->target_ver), TRUE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n"));
+ return A_ERROR;
+ }
+
+ if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
+ /* Determine how many bytes are in the Target's targ_info */
+ status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count,
+ sizeof(targ_info->target_info_byte_count), TRUE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n"));
+ return A_ERROR;
+ }
+
+ /*
+ * The Target's targ_info doesn't match the Host's targ_info.
+ * We need to do some backwards compatibility work to make this OK.
+ */
+ A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info));
+
+ /* Read the remainder of the targ_info */
+ status = bmiBufferReceive(device,
+ ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count),
+ sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n",
+ targ_info->target_info_byte_count));
+ return A_ERROR;
+ }
+ } else {
+ /*
+ * Target must be an AR6001 whose firmware does not
+ * support BMI_GET_TARGET_INFO. Construct the data
+ * that it would have sent.
+ */
+ targ_info->target_info_byte_count=sizeof(*targ_info);
+ targ_info->target_type=TARGET_TYPE_AR6001;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
+ targ_info->target_ver, targ_info->target_type));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ A_UINT32 remaining, rxlen;
+
+ A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)));
+ memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+ device, address, length));
+
+ cid = BMI_READ_MEMORY;
+
+ remaining = length;
+
+ while (remaining)
+ {
+ rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &rxlen, sizeof(rxlen));
+ offset += sizeof(length);
+
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+ status = bmiBufferReceive(device, pBMICmdBuf, rxlen, TRUE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+ A_MEMCPY(&buffer[length - remaining], pBMICmdBuf, rxlen);
+ remaining -= rxlen; address += rxlen;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n"));
+ return A_OK;
+}
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ A_UINT32 remaining, txlen;
+ const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
+
+ A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + header));
+ memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + header);
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+ device, address, length));
+
+ cid = BMI_WRITE_MEMORY;
+
+ remaining = length;
+ while (remaining)
+ {
+ txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
+ remaining : (BMI_DATASZ_MAX - header);
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen));
+ offset += sizeof(txlen);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen);
+ offset += txlen;
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+ remaining -= txlen; address += txlen;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param)));
+ memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+ device, address, *param));
+
+ cid = BMI_EXECUTE;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&(pBMICmdBuf[offset]), param, sizeof(*param));
+ offset += sizeof(*param);
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), FALSE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+
+ A_MEMCPY(param, pBMICmdBuf, sizeof(*param));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param));
+ return A_OK;
+}
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+ A_UINT32 address)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+ memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
+ device, address));
+
+ cid = BMI_SET_APP_START;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n"));
+ return A_OK;
+}
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+ memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
+ device, address));
+
+ cid = BMI_READ_SOC_REGISTER;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), TRUE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+ A_MEMCPY(param, pBMICmdBuf, sizeof(*param));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param));
+ return A_OK;
+}
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 param)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param)));
+ memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+ device, address, param));
+
+ cid = BMI_WRITE_SOC_REGISTER;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &param, sizeof(param));
+ offset += sizeof(param);
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n"));
+ return A_OK;
+}
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+ A_UINT32 ROM_addr,
+ A_UINT32 RAM_addr,
+ A_UINT32 nbytes,
+ A_UINT32 do_activate,
+ A_UINT32 *rompatch_id)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+ sizeof(nbytes) + sizeof(do_activate)));
+ memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+ sizeof(nbytes) + sizeof(do_activate));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n",
+ device, ROM_addr, RAM_addr, nbytes, do_activate));
+
+ cid = BMI_ROMPATCH_INSTALL;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &ROM_addr, sizeof(ROM_addr));
+ offset += sizeof(ROM_addr);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &RAM_addr, sizeof(RAM_addr));
+ offset += sizeof(RAM_addr);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &nbytes, sizeof(nbytes));
+ offset += sizeof(nbytes);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &do_activate, sizeof(do_activate));
+ offset += sizeof(do_activate);
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*rompatch_id), TRUE);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+ A_MEMCPY(rompatch_id, pBMICmdBuf, sizeof(*rompatch_id));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id));
+ return A_OK;
+}
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+ A_UINT32 rompatch_id)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(rompatch_id)));
+ memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(rompatch_id));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n",
+ device, rompatch_id));
+
+ cid = BMI_ROMPATCH_UNINSTALL;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_id, sizeof(rompatch_id));
+ offset += sizeof(rompatch_id);
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id));
+ return A_OK;
+}
+
+static A_STATUS
+_BMIrompatchChangeActivation(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list,
+ A_UINT32 do_activate)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ A_UINT32 length;
+
+ A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)));
+ memset(pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n",
+ device, rompatch_count));
+
+ cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE;
+
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_count, sizeof(rompatch_count));
+ offset += sizeof(rompatch_count);
+ length = rompatch_count * sizeof(*rompatch_list);
+ A_MEMCPY(&(pBMICmdBuf[offset]), rompatch_list, length);
+ offset += length;
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list)
+{
+ return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1);
+}
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list)
+{
+ return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0);
+}
+
+A_STATUS
+BMILZData(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ A_UINT32 remaining, txlen;
+ const A_UINT32 header = sizeof(cid) + sizeof(length);
+
+ A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX+header));
+ memset (pBMICmdBuf, 0, BMI_DATASZ_MAX+header);
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n",
+ device, length));
+
+ cid = BMI_LZ_DATA;
+
+ remaining = length;
+ while (remaining)
+ {
+ txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
+ remaining : (BMI_DATASZ_MAX - header);
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen));
+ offset += sizeof(txlen);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen);
+ offset += txlen;
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+ remaining -= txlen;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMILZStreamStart(HIF_DEVICE *device,
+ A_UINT32 address)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+
+ A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address)));
+ memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n",
+ device, address));
+
+ cid = BMI_LZ_STREAM_START;
+ offset = 0;
+ A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address));
+ offset += sizeof(address);
+ status = bmiBufferSend(device, pBMICmdBuf, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n"));
+
+ return A_OK;
+}
+
+/* BMI Access routines */
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_STATUS status;
+ A_UINT32 timeout;
+ A_UINT32 address;
+ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+
+ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+ &mboxAddress[0], sizeof(mboxAddress));
+
+ *pBMICmdCredits = 0;
+ timeout = BMI_COMMUNICATION_TIMEOUT;
+
+ while(timeout-- && !(*pBMICmdCredits)) {
+ /* Read the counter register to get the command credits */
+ address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
+ /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
+ * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to
+ * make all HIF accesses 4-byte aligned */
+ status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, 4,
+ HIF_RD_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
+ return A_ERROR;
+ }
+ /* the counter is only 8=bits, ignore anything in the upper 3 bytes */
+ (*pBMICmdCredits) &= 0xFF;
+ }
+
+ if (*pBMICmdCredits) {
+ address = mboxAddress[ENDPOINT1];
+ status = HIFReadWrite(device, address, buffer, length,
+ HIF_WR_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
+ return A_ERROR;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n"));
+ return A_ERROR;
+ }
+
+ return status;
+}
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_BOOL want_timeout)
+{
+ A_STATUS status;
+ A_UINT32 address;
+ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+ HIF_PENDING_EVENTS_INFO hifPendingEvents;
+ static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL;
+
+ if (!pendingEventsFuncCheck) {
+ /* see if the HIF layer implements an alternative function to get pending events
+ * do this only once! */
+ HIFConfigureDevice(device,
+ HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+ &getPendingEventsFunc,
+ sizeof(getPendingEventsFunc));
+ pendingEventsFuncCheck = TRUE;
+ }
+
+ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+ &mboxAddress[0], sizeof(mboxAddress));
+
+ /*
+ * During normal bootup, small reads may be required.
+ * Rather than issue an HIF Read and then wait as the Target
+ * adds successive bytes to the FIFO, we wait here until
+ * we know that response data is available.
+ *
+ * This allows us to cleanly timeout on an unexpected
+ * Target failure rather than risk problems at the HIF level. In
+ * particular, this avoids SDIO timeouts and possibly garbage
+ * data on some host controllers. And on an interconnect
+ * such as Compact Flash (as well as some SDIO masters) which
+ * does not provide any indication on data timeout, it avoids
+ * a potential hang or garbage response.
+ *
+ * Synchronization is more difficult for reads larger than the
+ * size of the MBOX FIFO (128B), because the Target is unable
+ * to push the 129th byte of data until AFTER the Host posts an
+ * HIF Read and removes some FIFO data. So for large reads the
+ * Host proceeds to post an HIF Read BEFORE all the data is
+ * actually available to read. Fortunately, large BMI reads do
+ * not occur in practice -- they're supported for debug/development.
+ *
+ * So Host/Target BMI synchronization is divided into these cases:
+ * CASE 1: length < 4
+ * Should not happen
+ *
+ * CASE 2: 4 <= length <= 128
+ * Wait for first 4 bytes to be in FIFO
+ * If CONSERVATIVE_BMI_READ is enabled, also wait for
+ * a BMI command credit, which indicates that the ENTIRE
+ * response is available in the the FIFO
+ *
+ * CASE 3: length > 128
+ * Wait for the first 4 bytes to be in FIFO
+ *
+ * For most uses, a small timeout should be sufficient and we will
+ * usually see a response quickly; but there may be some unusual
+ * (debug) cases of BMI_EXECUTE where we want an larger timeout.
+ * For now, we use an unbounded busy loop while waiting for
+ * BMI_EXECUTE.
+ *
+ * If BMI_EXECUTE ever needs to support longer-latency execution,
+ * especially in production, this code needs to be enhanced to sleep
+ * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
+ * a function of Host processor speed.
+ */
+ if (length >= 4) { /* NB: Currently, always true */
+ /*
+ * NB: word_available is declared static for esoteric reasons
+ * having to do with protection on some OSes.
+ */
+ static A_UINT32 word_available;
+ A_UINT32 timeout;
+
+ word_available = 0;
+ timeout = BMI_COMMUNICATION_TIMEOUT;
+ while((!want_timeout || timeout--) && !word_available) {
+
+ if (getPendingEventsFunc != NULL) {
+ status = getPendingEventsFunc(device,
+ &hifPendingEvents,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n"));
+ break;
+ }
+
+ if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) {
+ word_available = 1;
+ }
+ continue;
+ }
+
+ status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available,
+ sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n"));
+ return A_ERROR;
+ }
+ /* We did a 4-byte read to the same register; all we really want is one bit */
+ word_available &= (1 << ENDPOINT1);
+ }
+
+ if (!word_available) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n"));
+ return A_ERROR;
+ }
+ }
+
+#define CONSERVATIVE_BMI_READ 0
+#if CONSERVATIVE_BMI_READ
+ /*
+ * This is an extra-conservative CREDIT check. It guarantees
+ * that ALL data is available in the FIFO before we start to
+ * read from the interconnect.
+ *
+ * This credit check is useless when firmware chooses to
+ * allow multiple outstanding BMI Command Credits, since the next
+ * credit will already be present. To restrict the Target to one
+ * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT.
+ *
+ * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set)
+ * we cannot wait for the next credit because the Target's FIFO
+ * will not hold the entire response. So we need the Host to
+ * start to empty the FIFO sooner. (And again, large reads are
+ * not used in practice; they are for debug/development only.)
+ *
+ * For a more conservative Host implementation (which would be
+ * safer for a Compact Flash interconnect):
+ * Set CONSERVATIVE_BMI_READ (above) to 1
+ * Set HI_OPTION_BMI_CRED_LIMIT and
+ * reduce BMI_DATASZ_MAX to 32 or 64
+ */
+ if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */
+ A_UINT32 timeout;
+
+ *pBMICmdCredits = 0;
+ timeout = BMI_COMMUNICATION_TIMEOUT;
+ while((!want_timeout || timeout--) && !(*pBMICmdCredits) {
+ /* Read the counter register to get the command credits */
+ address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
+ /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing,
+ * we can read this counter multiple times using a non-incrementing address mode.
+ * The rationale here is to make all HIF accesses a multiple of 4 bytes */
+ status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, sizeof(*pBMICmdCredits),
+ HIF_RD_SYNC_BYTE_FIX, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
+ return A_ERROR;
+ }
+ /* we did a 4-byte read to the same count register so mask off upper bytes */
+ (*pBMICmdCredits) &= 0xFF;
+ }
+
+ if (!(*pBMICmdCredits)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout- bmiBufferReceive no credit\n"));
+ return A_ERROR;
+ }
+ }
+#endif
+
+ address = mboxAddress[ENDPOINT1];
+ status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+
+A_STATUS
+BMIFastDownload(HIF_DEVICE *device, A_UINT32 address, A_UCHAR *buffer, A_UINT32 length)
+{
+ A_STATUS status = A_ERROR;
+ A_UINT32 lastWord = 0;
+ A_UINT32 lastWordOffset = length & ~0x3;
+ A_UINT32 unalignedBytes = length & 0x3;
+
+ status = BMILZStreamStart (device, address);
+ if (A_FAILED(status)) {
+ return A_ERROR;
+ }
+
+ if (unalignedBytes) {
+ /* copy the last word into a zero padded buffer */
+ A_MEMCPY(&lastWord, &buffer[lastWordOffset], unalignedBytes);
+ }
+
+ status = BMILZData(device, buffer, lastWordOffset);
+
+ if (A_FAILED(status)) {
+ return A_ERROR;
+ }
+
+ if (unalignedBytes) {
+ status = BMILZData(device, (A_UINT8 *)&lastWord, 4);
+ }
+
+ if (A_SUCCESS(status)) {
+ //
+ // Close compressed stream and open a new (fake) one. This serves mainly to flush Target caches.
+ //
+ status = BMILZStreamStart (device, 0x00);
+ if (A_FAILED(status)) {
+ return A_ERROR;
+ }
+ }
+ return status;
+}
+
+A_STATUS
+BMIRawWrite(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length)
+{
+ return bmiBufferSend(device, buffer, length);
+}
+
+A_STATUS
+BMIRawRead(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length, A_BOOL want_timeout)
+{
+ return bmiBufferReceive(device, buffer, length, want_timeout);
+}
diff --git a/drivers/net/wireless/ath6kl/bmi/src/makefile b/drivers/net/wireless/ath6kl/bmi/src/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/bmi/src/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h b/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h
new file mode 100644
index 000000000000..78d29ca14dc2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h
@@ -0,0 +1,88 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_sdio_common.h" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// common header file for HIF modules designed for SDIO
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef HIF_SDIO_COMMON_H_
+#define HIF_SDIO_COMMON_H_
+
+ /* SDIO manufacturer ID and Codes */
+#define MANUFACTURER_ID_AR6001_BASE 0x100
+#define MANUFACTURER_ID_AR6002_BASE 0x200
+#define MANUFACTURER_ID_AR6003_BASE 0x300
+#define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00
+#define FUNCTION_CLASS 0x0
+#define MANUFACTURER_CODE 0x271 /* Atheros */
+
+ /* Mailbox address in SDIO address space */
+#define HIF_MBOX_BASE_ADDR 0x800
+#define HIF_MBOX_WIDTH 0x800
+#define HIF_MBOX_START_ADDR(mbox) \
+ ( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH)
+
+#define HIF_MBOX_END_ADDR(mbox) \
+ (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
+
+ /* extended MBOX address for larger MBOX writes to MBOX 0*/
+#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024)
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024)
+
+ /* version 1 of the chip has only a 12K extended mbox range */
+#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000
+#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024)
+
+ /* GMBOX addresses */
+#define HIF_GMBOX_BASE_ADDR 0x7000
+#define HIF_GMBOX_WIDTH 0x4000
+
+ /* for SDIO we recommend a 128-byte block size */
+#define HIF_DEFAULT_IO_BLOCK_SIZE 128
+
+ /* set extended MBOX window information for SDIO interconnects */
+static INLINE void SetExtendedMboxWindowInfo(A_UINT16 Manfid, HIF_DEVICE_MBOX_INFO *pInfo)
+{
+ switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) {
+ case MANUFACTURER_ID_AR6001_BASE :
+ /* no extended MBOX */
+ break;
+ case MANUFACTURER_ID_AR6002_BASE :
+ /* MBOX 0 has an extended range */
+ pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR;
+ pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002;
+ break;
+ case MANUFACTURER_ID_AR6003_BASE :
+ /* MBOX 0 has an extended range */
+ pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1;
+ pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1;
+ pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR;
+ pInfo->GMboxSize = HIF_GMBOX_WIDTH;
+ break;
+ default:
+ A_ASSERT(FALSE);
+ break;
+ }
+}
+
+/* special CCCR (func 0) registers */
+
+#define CCCR_SDIO_IRQ_MODE_REG 0xF0 /* interrupt mode register */
+#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) /* mode to enable special 4-bit interrupt assertion without clock*/
+
+#endif /*HIF_SDIO_COMMON_H_*/
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/Makefile b/drivers/net/wireless/ath6kl/hif/sdio/Makefile
new file mode 100644
index 000000000000..6f282bb8ad5f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/Makefile
@@ -0,0 +1,86 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2008 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+
+#
+#SDIO HIF makefile for atheros SDIO stack
+#
+
+# Check for SDIO stack
+ifdef ATH_SDIO_STACK_BASE
+# Someone already set it on entry, the stack resides outside this tree, we will try to build it
+_SDIO_STACK = YES
+else
+# Check for SDIO stack within this tree
+_SDIO_STACK = $(shell if [ -f $(ATH_SRC_BASE)/sdiostack/src/Makefile ]; then echo "YES"; else echo "NO"; fi)
+
+ifeq ($(_SDIO_STACK), YES)
+ # SDIO stack is part of the kit and will need to be compiled
+ATH_SDIO_STACK_BASE := $(ATH_SRC_BASE)/sdiostack
+endif
+endif
+
+
+ifeq ($(ATH_BUS_SUBTYPE),linux_sdio)
+_HIF_SUB_TYPE = linux_sdio
+_SDIO_STACK = NO
+else
+_HIF_SUB_TYPE = linux_athsdio
+endif
+
+
+ifeq ($(_SDIO_STACK), YES)
+ # Pass and translate build variables to the SDIO stack makefile
+_SDIO_STACK_MAKE_PARAMS := CT_BUILD_TYPE=$(ATH_BUILD_TYPE) \
+ CT_OS_TYPE=linux \
+ CT_OS_SUB_TYPE=$(ATH_OS_SUB_TYPE) \
+ CT_LINUXPATH=$(ATH_LINUXPATH) \
+ CT_BUILD_TYPE=$(ATH_BUILD_TYPE) \
+ CT_CROSS_COMPILE_TYPE=$(ATH_CROSS_COMPILE_TYPE) \
+ CT_ARCH_CPU_TYPE=$(ATH_ARCH_CPU_TYPE) \
+ CT_HC_DRIVERS=$(ATH_HC_DRIVERS) \
+ CT_MAKE_INCLUDE_OVERRIDE=$(_LOCALMAKE_INCLUDE) \
+ CT_BUILD_OUTPUT_OVERRIDE=$(COMPILED_IMAGE_OBJECTS_PATH) \
+ BUS_BUILD=1
+endif
+EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/hif/sdio/$(_HIF_SUB_TYPE)/include
+EXTRA_CFLAGS += -DSDIO
+EXTRA_CFLAGS += -I$(ATH_SDIO_STACK_BASE)/src/include
+
+ifeq ($(ATH_OS_SUB_TYPE),linux_2_4)
+obj-y += ../../hif/sdio/linux_athsdio/src/hif.o
+obj-y += ../../hif/sdio/linux_athsdio/src/hif_scatter.o
+endif
+
+ifneq ($(ATH_OS_SUB_TYPE),linux_2_4)
+ar6000-objs := ../../hif/sdio/$(_HIF_SUB_TYPE)/src/hif.o \
+ ../../hif/sdio/$(_HIF_SUB_TYPE)/src/hif_scatter.o
+
+
+endif
+
+all:
+ifeq ($(_SDIO_STACK),YES)
+ $(MAKE) $(_SDIO_STACK_MAKE_PARAMS) -C $(ATH_SDIO_STACK_BASE)/src default
+ -cp -f $(ATH_SDIO_STACK_BASE)/src/Module.symvers $(COMPILED_IMAGE_OBJECTS_PATH)
+endif
+
+clean:
+ifeq ($(_SDIO_STACK),YES)
+ $(MAKE) $(_SDIO_STACK_MAKE_PARAMS) -C $(ATH_SDIO_STACK_BASE)/src clean
+endif
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
new file mode 100644
index 000000000000..e0155a58ec9a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
@@ -0,0 +1,128 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_internal.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// internal header file for hif layer
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HIF_INTERNAL_H_
+#define _HIF_INTERNAL_H_
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "hif.h"
+#include "../../../common/hif_sdio_common.h"
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
+#include <linux/scatterlist.h>
+#define HIF_LINUX_MMC_SCATTER_SUPPORT
+#endif
+
+#define BUS_REQUEST_MAX_NUM 64
+
+#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000
+#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
+#define FLAGS_CARD_ENAB 0x02
+#define FLAGS_CARD_IRQ_UNMSK 0x04
+
+#define HIF_MBOX_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE
+#define HIF_MBOX0_BLOCK_SIZE 1
+#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
+
+struct _HIF_SCATTER_REQ_PRIV;
+
+typedef struct bus_request {
+ struct bus_request *next; /* link list of available requests */
+ struct bus_request *inusenext; /* link list of in use requests */
+ struct semaphore sem_req;
+ A_UINT32 address; /* request data */
+ A_UCHAR *buffer;
+ A_UINT32 length;
+ A_UINT32 request;
+ void *context;
+ A_STATUS status;
+ struct _HIF_SCATTER_REQ_PRIV *pScatterReq; /* this request is a scatter request */
+} BUS_REQUEST;
+
+struct hif_device {
+ struct sdio_func *func;
+ spinlock_t asynclock;
+ struct task_struct* async_task; /* task to handle async commands */
+ struct semaphore sem_async; /* wake up for async task */
+ int async_shutdown; /* stop the async task */
+ struct completion async_completion; /* thread completion */
+ BUS_REQUEST *asyncreq; /* request for async tasklet */
+ BUS_REQUEST *taskreq; /* async tasklet data */
+ spinlock_t lock;
+ BUS_REQUEST *s_busRequestFreeQueue; /* free list */
+ BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */
+ void *claimedContext;
+ HTC_CALLBACKS htcCallbacks;
+ A_UINT8 *dma_buffer;
+ DL_LIST ScatterReqHead; /* scatter request list head */
+ A_BOOL scatter_enabled; /* scatter enabled flag */
+ A_BOOL is_suspend;
+};
+
+#define HIF_DMA_BUFFER_SIZE (32 * 1024)
+#define CMD53_FIXED_ADDRESS 1
+#define CMD53_INCR_ADDRESS 2
+
+BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device);
+void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+
+#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define MAX_SCATTER_REQUESTS 4
+#define MAX_SCATTER_ENTRIES_PER_REQ 16
+#define MAX_SCATTER_REQ_TRANSFER_SIZE 32*1024
+
+typedef struct _HIF_SCATTER_REQ_PRIV {
+ HIF_SCATTER_REQ *pHifScatterReq; /* HIF scatter request with allocated entries */
+ HIF_DEVICE *device; /* this device */
+ BUS_REQUEST *busrequest; /* request associated with request */
+ /* scatter list for linux */
+ struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
+} HIF_SCATTER_REQ_PRIV;
+
+#define ATH_DEBUG_SCATTER ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo);
+void CleanupHIFScatterResources(HIF_DEVICE *device);
+A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest);
+
+#else // HIF_LINUX_MMC_SCATTER_SUPPORT
+
+static inline A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo)
+{
+ return A_ENOTSUP;
+}
+
+static inline A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+ return A_ENOTSUP;
+}
+
+#define CleanupHIFScatterResources(d) { }
+
+#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#endif // _HIF_INTERNAL_H_
+
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt
new file mode 100644
index 000000000000..0c98fd89a343
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt
@@ -0,0 +1,35 @@
+HIF support for native Linux MMC Stack.
+paull@atheros.com
+
+11/6/09
+Added patches for the MMC stacks Standard Host Controller for 2.6.30 and 2.6.32
+Patches enable ENE board support and speed up transfers for any Standard Host Controller
+linux2.6.30_mmc_std_host.patch
+linuxMMC_std_host_2.6.32-rc5sdio.patch
+
+
+2/18/2009
+Added patch for Freescale MX35 SD host driver. tested with SD25 AR6102 Olca 2.1.2
+
+12/18/2008
+Tested on Freescale MX27 and OMAP3530 Beageleboard Linux ver 2.6.28
+adds DMA bounce buffer support
+hif.c ver 5 and hif.h ver 4 are for the old HTC/HIF interface and shouold be useable with 2.1 drivers
+ver 6 and 5 are for the new HTC/HIF interface
+For older Linux MMC stack versions, comment out in hif.c hifDeviceInserted() the lines:
+ /* give us some time to enable, in ms */
+ func->enable_timeout = 100;
+it is only required on some platforms, eg Beagleboard.
+
+7/18/2008
+
+a. tested on Fedora Core 9 kernel 2.6.25.6, x86 with ENE standrad host controller,using the Olca 2.1.1RC.15
+b. requires applying the linux2.6.25.6mmc.patch to the kernel drivers/mmc directory
+c. through put is 20-22mbs up/down link
+d. new platform type is:
+ ATH_PLATFORM=LOCAL_i686_NATIVEMMC-SDIO
+ TARGET_TYPE=AR6002
+e. known issues: unloading the driver on Fedora Core 9 after conecting to an AP seems to not be complete.
+
+
+
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c
new file mode 100644
index 000000000000..75becd04cc49
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c
@@ -0,0 +1,1010 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF layer reference implementation for Linux Native MMC stack
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <linux/mmc/card.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio.h>
+#include <linux/kthread.h>
+
+/* by default setup a bounce buffer for the data packets, if the underlying host controller driver
+ does not use DMA you may be able to skip this step and save the memory allocation and transfer time */
+#define HIF_USE_DMA_BOUNCE_BUFFER 1
+#include "hif_internal.h"
+#define ATH_MODULE_NAME hif
+#include "a_debug.h"
+
+
+#if HIF_USE_DMA_BOUNCE_BUFFER
+/* macro to check if DMA buffer is WORD-aligned and DMA-able. Most host controllers assume the
+ * buffer is DMA'able and will bug-check otherwise (i.e. buffers on the stack).
+ * virt_addr_valid check fails on stack memory.
+ */
+#define BUFFER_NEEDS_BOUNCE(buffer) (((A_UINT32)(buffer) & 0x3) || !virt_addr_valid((buffer)))
+#else
+#define BUFFER_NEEDS_BOUNCE(buffer) (FALSE)
+#endif
+
+/* ATHENV */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev)
+#define to_sdio_driver(d) container_of(d, struct sdio_driver, drv)
+static int hifDeviceSuspend(struct device *dev);
+static int hifDeviceResume(struct device *dev);
+#endif /* CONFIG_PM */
+static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id);
+static void hifDeviceRemoved(struct sdio_func *func);
+static HIF_DEVICE *addHifDevice(struct sdio_func *func);
+static HIF_DEVICE *getHifDevice(struct sdio_func *func);
+static void delHifDevice(HIF_DEVICE * device);
+static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte);
+
+int reset_sdio_on_unload = 0;
+module_param(reset_sdio_on_unload, int, 0644);
+
+extern A_UINT32 nohifscattersupport;
+
+
+/* ------ Static Variables ------ */
+static const struct sdio_device_id ar6k_id_table[] = {
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) },
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) },
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) },
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1)) },
+ { /* null */ },
+};
+MODULE_DEVICE_TABLE(sdio, ar6k_id_table);
+
+static struct sdio_driver ar6k_driver = {
+ .name = "ar6k_wlan",
+ .id_table = ar6k_id_table,
+ .probe = hifDeviceInserted,
+ .remove = hifDeviceRemoved,
+};
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+/* New suspend/resume based on linux-2.6.32
+ * Need to patch linux-2.6.32 with mmc2.6.32_suspend.patch
+ * Need to patch with msmsdcc2.6.29_suspend.patch for msm_sdcc host
+ */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+static struct dev_pm_ops ar6k_device_pm_ops = {
+#else
+static struct pm_ops ar6k_device_pm_ops = {
+#endif
+ .suspend = hifDeviceSuspend,
+ .resume = hifDeviceResume,
+};
+#endif /* CONFIG_PM */
+
+/* make sure we only unregister when registered. */
+static int registered = 0;
+
+OSDRV_CALLBACKS osdrvCallbacks;
+extern A_UINT32 onebitmode;
+extern A_UINT32 busspeedlow;
+extern A_UINT32 debughif;
+
+static void ResetAllCards(void);
+
+#ifdef DEBUG
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif,
+ "hif",
+ "(Linux MMC) Host Interconnect Framework",
+ ATH_DEBUG_MASK_DEFAULTS,
+ 0,
+ NULL);
+
+#endif
+
+
+/* ------ Functions ------ */
+A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks)
+{
+ int status;
+ AR_DEBUG_ASSERT(callbacks != NULL);
+
+ A_REGISTER_MODULE_DEBUG_INFO(hif);
+
+ /* store the callback handlers */
+ osdrvCallbacks = *callbacks;
+
+ /* Register with bus driver core */
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n"));
+ registered = 1;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+ if (callbacks->deviceSuspendHandler && callbacks->deviceResumeHandler) {
+ ar6k_driver.drv.pm = &ar6k_device_pm_ops;
+ }
+#endif /* CONFIG_PM */
+ status = sdio_register_driver(&ar6k_driver);
+ AR_DEBUG_ASSERT(status==0);
+
+ if (status != 0) {
+ return A_ERROR;
+ }
+
+ return A_OK;
+
+}
+
+static A_STATUS
+__HIFReadWrite(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_UINT32 request,
+ void *context)
+{
+ A_UINT8 opcode;
+ A_STATUS status = A_OK;
+ int ret;
+ A_UINT8 *tbuffer;
+ A_BOOL bounced = FALSE;
+
+ AR_DEBUG_ASSERT(device != NULL);
+ AR_DEBUG_ASSERT(device->func != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p (addr:0x%X)\n",
+ device, buffer, address));
+
+ do {
+ if (request & HIF_EXTENDED_IO) {
+ //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: Invalid command type: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ if (request & HIF_BLOCK_BASIS) {
+ /* round to whole block length size */
+ length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("AR6000: Block mode (BlockLen: %d)\n",
+ length));
+ } else if (request & HIF_BYTE_BASIS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("AR6000: Byte mode (BlockLen: %d)\n",
+ length));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: Invalid data mode: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+#if 0
+ /* useful for checking register accesses */
+ if (length & 0x3) {
+ A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n",
+ request & HIF_WRITE ? "write":"read", address, length);
+ }
+#endif
+
+ if (request & HIF_WRITE) {
+ if ((address >= HIF_MBOX_START_ADDR(0)) &&
+ (address <= HIF_MBOX_END_ADDR(3)))
+ {
+
+ AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH);
+
+ /*
+ * Mailbox write. Adjust the address so that the last byte
+ * falls on the EOM address.
+ */
+ address += (HIF_MBOX_WIDTH - length);
+ }
+ }
+
+ if (request & HIF_FIXED_ADDRESS) {
+ opcode = CMD53_FIXED_ADDRESS;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address));
+ } else if (request & HIF_INCREMENTAL_ADDRESS) {
+ opcode = CMD53_INCR_ADDRESS;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: Invalid address mode: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ if (request & HIF_WRITE) {
+#if HIF_USE_DMA_BOUNCE_BUFFER
+ if (BUFFER_NEEDS_BOUNCE(buffer)) {
+ AR_DEBUG_ASSERT(device->dma_buffer != NULL);
+ tbuffer = device->dma_buffer;
+ /* copy the write data to the dma buffer */
+ AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE);
+ memcpy(tbuffer, buffer, length);
+ bounced = TRUE;
+ } else {
+ tbuffer = buffer;
+ }
+#else
+ tbuffer = buffer;
+#endif
+ if (opcode == CMD53_FIXED_ADDRESS) {
+ ret = sdio_writesb(device->func, address, tbuffer, length);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n",
+ ret, address, length, *(int *)tbuffer));
+ } else {
+ ret = sdio_memcpy_toio(device->func, address, tbuffer, length);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n",
+ ret, address, length, *(int *)tbuffer));
+ }
+ } else if (request & HIF_READ) {
+#if HIF_USE_DMA_BOUNCE_BUFFER
+ if (BUFFER_NEEDS_BOUNCE(buffer)) {
+ AR_DEBUG_ASSERT(device->dma_buffer != NULL);
+ AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE);
+ tbuffer = device->dma_buffer;
+ bounced = TRUE;
+ } else {
+ tbuffer = buffer;
+ }
+#else
+ tbuffer = buffer;
+#endif
+ if (opcode == CMD53_FIXED_ADDRESS) {
+ ret = sdio_readsb(device->func, tbuffer, address, length);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n",
+ ret, address, length, *(int *)tbuffer));
+ } else {
+ ret = sdio_memcpy_fromio(device->func, tbuffer, address, length);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n",
+ ret, address, length, *(int *)tbuffer));
+ }
+#if HIF_USE_DMA_BOUNCE_BUFFER
+ if (bounced) {
+ /* copy the read data from the dma buffer */
+ memcpy(buffer, tbuffer, length);
+ }
+#endif
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: Invalid direction: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: SDIO bus operation failed! MMC stack returned : %d \n", ret));
+ status = A_ERROR;
+ }
+ } while (FALSE);
+
+ return status;
+}
+
+void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+ unsigned long flags;
+ BUS_REQUEST *async;
+ BUS_REQUEST *active;
+
+ spin_lock_irqsave(&device->asynclock, flags);
+ active = device->asyncreq;
+ if (active == NULL) {
+ device->asyncreq = busrequest;
+ device->asyncreq->inusenext = NULL;
+ } else {
+ for (async = device->asyncreq;
+ async != NULL;
+ async = async->inusenext) {
+ active = async;
+ }
+ active->inusenext = busrequest;
+ busrequest->inusenext = NULL;
+ }
+ spin_unlock_irqrestore(&device->asynclock, flags);
+}
+
+
+/* queue a read/write request */
+A_STATUS
+HIFReadWrite(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_UINT32 request,
+ void *context)
+{
+ A_STATUS status = A_OK;
+ BUS_REQUEST *busrequest;
+
+
+ AR_DEBUG_ASSERT(device != NULL);
+ AR_DEBUG_ASSERT(device->func != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p addr:0x%X\n", device,address));
+
+ do {
+ if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){
+ /* serialize all requests through the async thread */
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n",
+ (request & HIF_ASYNCHRONOUS)?"Async":"Synch"));
+ busrequest = hifAllocateBusRequest(device);
+ if (busrequest == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: no async bus requests available (%s, addr:0x%X, len:%d) \n",
+ request & HIF_READ ? "READ":"WRITE", address, length));
+ return A_ERROR;
+ }
+ busrequest->address = address;
+ busrequest->buffer = buffer;
+ busrequest->length = length;
+ busrequest->request = request;
+ busrequest->context = context;
+
+ AddToAsyncList(device, busrequest);
+
+ if (request & HIF_SYNCHRONOUS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest));
+
+ /* wait for completion */
+ up(&device->sem_async);
+ if (down_interruptible(&busrequest->sem_req) != 0) {
+ /* interrupted, exit */
+ return A_ERROR;
+ } else {
+ A_STATUS status = busrequest->status;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n",
+ (unsigned int)busrequest, busrequest->status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request));
+ hifFreeBusRequest(device, busrequest);
+ return status;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest));
+ up(&device->sem_async);
+ return A_PENDING;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request));
+ status = A_EINVAL;
+ break;
+ }
+ } while(0);
+
+ return status;
+}
+/* thread to serialize all requests, both sync and async */
+static int async_task(void *param)
+ {
+ HIF_DEVICE *device;
+ BUS_REQUEST *request;
+ A_STATUS status;
+ unsigned long flags;
+
+ device = (HIF_DEVICE *)param;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n"));
+ set_current_state(TASK_INTERRUPTIBLE);
+ while(!device->async_shutdown) {
+ /* wait for work */
+ if (down_interruptible(&device->sem_async) != 0) {
+ /* interrupted, exit */
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n"));
+ break;
+ }
+ if (device->async_shutdown) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n"));
+ break;
+ }
+ /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */
+ sdio_claim_host(device->func);
+ spin_lock_irqsave(&device->asynclock, flags);
+ /* pull the request to work on */
+ while (device->asyncreq != NULL) {
+ request = device->asyncreq;
+ if (request->inusenext != NULL) {
+ device->asyncreq = request->inusenext;
+ } else {
+ device->asyncreq = NULL;
+ }
+ spin_unlock_irqrestore(&device->asynclock, flags);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request));
+
+ if (request->pScatterReq != NULL) {
+ A_ASSERT(device->scatter_enabled);
+ /* this is a queued scatter request, pass the request to scatter routine which
+ * executes it synchronously, note, no need to free the request since scatter requests
+ * are maintained on a separate list */
+ status = DoHifReadWriteScatter(device,request);
+ } else {
+ /* call HIFReadWrite in sync mode to do the work */
+ status = __HIFReadWrite(device, request->address, request->buffer,
+ request->length, request->request & ~HIF_SYNCHRONOUS, NULL);
+ if (request->request & HIF_ASYNCHRONOUS) {
+ void *context = request->context;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request));
+ hifFreeBusRequest(device, request);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request));
+ device->htcCallbacks.rwCompletionHandler(context, status);
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request));
+ request->status = status;
+ up(&request->sem_req);
+ }
+ }
+ spin_lock_irqsave(&device->asynclock, flags);
+ }
+ spin_unlock_irqrestore(&device->asynclock, flags);
+ sdio_release_host(device->func);
+ }
+
+ complete_and_exit(&device->async_completion, 0);
+ return 0;
+ }
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+ void *config, A_UINT32 configLen)
+{
+ A_UINT32 count;
+ A_STATUS status;
+
+ switch(opcode) {
+ case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
+ ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
+ ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
+ ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
+ ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
+ break;
+
+ case HIF_DEVICE_GET_MBOX_ADDR:
+ for (count = 0; count < 4; count ++) {
+ ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
+ }
+
+ if (configLen >= sizeof(HIF_DEVICE_MBOX_INFO)) {
+ SetExtendedMboxWindowInfo((A_UINT16)device->func->device,
+ (HIF_DEVICE_MBOX_INFO *)config);
+ }
+
+ break;
+ case HIF_DEVICE_GET_IRQ_PROC_MODE:
+ *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY;
+ break;
+ case HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT:
+ if (!device->scatter_enabled) {
+ return A_ENOTSUP;
+ }
+ status = SetupHIFScatterSupport(device, (HIF_DEVICE_SCATTER_SUPPORT_INFO *)config);
+ if (A_FAILED(status)) {
+ device->scatter_enabled = FALSE;
+ }
+ return status;
+ case HIF_DEVICE_GET_OS_DEVICE:
+ /* pass back a pointer to the SDIO function's "dev" struct */
+ ((HIF_DEVICE_OS_DEVICE_INFO *)config)->pOSDevice = &device->func->dev;
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ ("AR6000: Unsupported configuration opcode: %d\n", opcode));
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+
+void
+HIFShutDownDevice(HIF_DEVICE *device)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n"));
+ if (device != NULL) {
+ AR_DEBUG_ASSERT(device->func != NULL);
+ } else {
+ /* since we are unloading the driver anyways, reset all cards in case the SDIO card
+ * is externally powered and we are unloading the SDIO stack. This avoids the problem when
+ * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already
+ * enumerated */
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n"));
+ ResetAllCards();
+
+ /* Unregister with bus driver core */
+ if (registered) {
+ registered = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("AR6000: Unregistering with the bus driver\n"));
+ sdio_unregister_driver(&ar6k_driver);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("AR6000: Unregistered\n"));
+ }
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n"));
+}
+
+static void
+hifIRQHandler(struct sdio_func *func)
+{
+ A_STATUS status;
+ HIF_DEVICE *device;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n"));
+
+ device = getHifDevice(func);
+ /* release the host during ints so we can pick it back up when we process cmds */
+ sdio_release_host(device->func);
+ status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context);
+ sdio_claim_host(device->func);
+ AR_DEBUG_ASSERT(status == A_OK || status == A_ECANCELED);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n"));
+}
+
+/* handle HTC startup via thread*/
+static int startup_task(void *param)
+{
+ HIF_DEVICE *device;
+
+ device = (HIF_DEVICE *)param;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n"));
+ /* start up inform DRV layer */
+ if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n"));
+ }
+ return 0;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+/* handle HTC startup via thread*/
+static int resume_task(void *param)
+{
+ HIF_DEVICE *device;
+ device = (HIF_DEVICE *)param;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from resume_task\n"));
+ /* start up inform DRV layer */
+ if (device && device->claimedContext && osdrvCallbacks.deviceResumeHandler &&
+ osdrvCallbacks.deviceResumeHandler(device->claimedContext) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n"));
+ }
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id)
+{
+ int ret;
+ HIF_DEVICE * device;
+ int count;
+ struct task_struct* startup_task_struct;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n",
+ func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize));
+
+ addHifDevice(func);
+ device = getHifDevice(func);
+
+ spin_lock_init(&device->lock);
+
+ spin_lock_init(&device->asynclock);
+
+ DL_LIST_INIT(&device->ScatterReqHead);
+
+ if (!nohifscattersupport) {
+ /* try to allow scatter operation on all instances,
+ * unless globally overridden */
+ device->scatter_enabled = TRUE;
+ }
+
+ /* enable the SDIO function */
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n"));
+ sdio_claim_host(func);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n"));
+
+ if ((id->device & MANUFACTURER_ID_AR6K_BASE_MASK) >= MANUFACTURER_ID_AR6003_BASE) {
+ /* enable 4-bit ASYNC interrupt on AR6003 or later devices */
+ ret = Func0_CMD52WriteByte(func->card, CCCR_SDIO_IRQ_MODE_REG, SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: failed to enable 4-bit ASYNC IRQ mode %d \n",ret));
+ sdio_release_host(func);
+ return ret;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: 4-bit ASYNC IRQ mode enabled\n"));
+ }
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ /* give us some time to enable, in ms */
+ func->enable_timeout = 100;
+#endif
+ ret = sdio_enable_func(func);
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
+ __FUNCTION__, ret));
+ sdio_release_host(func);
+ return ret;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE));
+ ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
+ sdio_release_host(func);
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n",
+ __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
+ return ret;
+ }
+ /* Initialize the bus requests to be used later */
+ A_MEMZERO(device->busRequest, sizeof(device->busRequest));
+ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
+ sema_init(&device->busRequest[count].sem_req, 0);
+ hifFreeBusRequest(device, &device->busRequest[count]);
+ }
+
+ /* create async I/O thread */
+ device->async_shutdown = 0;
+ device->async_task = kthread_create(async_task,
+ (void *)device,
+ "AR6K Async");
+ if (IS_ERR(device->async_task)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
+ sema_init(&device->sem_async, 0);
+ wake_up_process(device->async_task );
+
+ /* create startup thread */
+ startup_task_struct = kthread_create(startup_task,
+ (void *)device,
+ "AR6K startup");
+ if (IS_ERR(startup_task_struct)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n"));
+ wake_up_process(startup_task_struct);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret));
+ return ret;
+}
+
+
+void
+HIFAckInterrupt(HIF_DEVICE *device)
+{
+ AR_DEBUG_ASSERT(device != NULL);
+
+ /* Acknowledge our function IRQ */
+}
+
+void
+HIFUnMaskInterrupt(HIF_DEVICE *device)
+{
+ int ret;;
+
+ AR_DEBUG_ASSERT(device != NULL);
+ AR_DEBUG_ASSERT(device->func != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n"));
+
+ /* Register the IRQ Handler */
+ sdio_claim_host(device->func);
+ ret = sdio_claim_irq(device->func, hifIRQHandler);
+ sdio_release_host(device->func);
+ AR_DEBUG_ASSERT(ret == 0);
+}
+
+void HIFMaskInterrupt(HIF_DEVICE *device)
+{
+ int ret;;
+
+ AR_DEBUG_ASSERT(device != NULL);
+ AR_DEBUG_ASSERT(device->func != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n"));
+
+ /* Mask our function IRQ */
+ sdio_claim_host(device->func);
+ ret = sdio_release_irq(device->func);
+ sdio_release_host(device->func);
+ AR_DEBUG_ASSERT(ret == 0);
+}
+
+BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device)
+{
+ BUS_REQUEST *busrequest;
+ unsigned long flag;
+
+ /* Acquire lock */
+ spin_lock_irqsave(&device->lock, flag);
+
+ /* Remove first in list */
+ if((busrequest = device->s_busRequestFreeQueue) != NULL)
+ {
+ device->s_busRequestFreeQueue = busrequest->next;
+ }
+
+ /* Release lock */
+ spin_unlock_irqrestore(&device->lock, flag);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest));
+ return busrequest;
+}
+
+void
+hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+ unsigned long flag;
+
+ AR_DEBUG_ASSERT(busrequest != NULL);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest));
+ /* Acquire lock */
+ spin_lock_irqsave(&device->lock, flag);
+
+
+ /* Insert first in list */
+ busrequest->next = device->s_busRequestFreeQueue;
+ busrequest->inusenext = NULL;
+ device->s_busRequestFreeQueue = busrequest;
+
+ /* Release lock */
+ spin_unlock_irqrestore(&device->lock, flag);
+}
+
+static int hifDisableFunc(HIF_DEVICE *device, struct sdio_func *func)
+{
+ int ret = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
+ device = getHifDevice(func);
+ if (!IS_ERR(device->async_task)) {
+ init_completion(&device->async_completion);
+ device->async_shutdown = 1;
+ up(&device->sem_async);
+ wait_for_completion(&device->async_completion);
+ device->async_task = NULL;
+ }
+ /* Disable the card */
+ sdio_claim_host(device->func);
+ ret = sdio_disable_func(device->func);
+
+ if (reset_sdio_on_unload) {
+ /* reset the SDIO interface. This is useful in automated testing where the card
+ * does not need to be removed at the end of the test. It is expected that the user will
+ * also unload/reload the host controller driver to force the bus driver to re-enumerate the slot */
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6000: reseting SDIO card back to uninitialized state \n"));
+
+ /* NOTE : sdio_f0_writeb() cannot be used here, that API only allows access
+ * to undefined registers in the range of: 0xF0-0xFF */
+
+ ret = Func0_CMD52WriteByte(device->func->card, SDIO_CCCR_ABORT, (1 << 3));
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: reset failed : %d \n",ret));
+ }
+ }
+
+ sdio_release_host(device->func);
+ return ret;
+}
+
+static void hifDeviceRemoved(struct sdio_func *func)
+{
+ A_STATUS status = A_OK;
+ HIF_DEVICE *device;
+ AR_DEBUG_ASSERT(func != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
+ device = getHifDevice(func);
+ if (device->claimedContext != NULL) {
+ status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device);
+ }
+
+ if (device->is_suspend) {
+ device->is_suspend = FALSE;
+ } else {
+ if (hifDisableFunc(device, func)!=0) {
+ status = A_ERROR;
+ }
+ }
+ CleanupHIFScatterResources(device);
+
+ delHifDevice(device);
+ AR_DEBUG_ASSERT(status == A_OK);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n"));
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM)
+static int hifDeviceSuspend(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ A_STATUS status = A_OK;
+ HIF_DEVICE *device;
+ device = getHifDevice(func);
+ if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
+ status = osdrvCallbacks.deviceSuspendHandler(device->claimedContext);
+ }
+ if (status == A_OK) {
+ hifDisableFunc(device, func);
+ device->is_suspend = TRUE;
+ } else if (status == A_EBUSY) {
+ status = A_OK; /* assume that sdio host controller will take care the power of wifi chip */
+ }
+ return A_SUCCESS(status) ? 0 : status;
+}
+
+static int hifDeviceResume(struct device *dev)
+{
+ struct task_struct* pTask;
+ const char *taskName;
+ int (*taskFunc)(void *);
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ A_STATUS ret = A_OK;
+ HIF_DEVICE *device;
+ device = getHifDevice(func);
+
+ if (device->is_suspend) {
+ /* enable the SDIO function */
+ sdio_claim_host(func);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ /* give us some time to enable, in ms */
+ func->enable_timeout = 100;
+#endif
+ ret = sdio_enable_func(func);
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
+ __FUNCTION__, ret));
+ sdio_release_host(func);
+ return ret;
+ }
+ ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
+ sdio_release_host(func);
+ if (ret) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n",
+ __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
+ return ret;
+ }
+ device->is_suspend = FALSE;
+ /* create async I/O thread */
+ if (!device->async_task) {
+ device->async_shutdown = 0;
+ device->async_task = kthread_create(async_task,
+ (void *)device,
+ "AR6K Async");
+ if (IS_ERR(device->async_task)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
+ wake_up_process(device->async_task );
+ }
+ }
+
+ if (!device->claimedContext) {
+ printk("WARNING!!! No claimedContext during resume wlan\n");
+ taskFunc = startup_task;
+ taskName = "AR6K startup";
+ } else {
+ taskFunc = resume_task;
+ taskName = "AR6K resume";
+ }
+ /* create resume thread */
+ pTask = kthread_create(taskFunc, (void *)device, taskName);
+ if (IS_ERR(pTask)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create resume task\n", __FUNCTION__));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start resume task\n"));
+ wake_up_process(pTask);
+ return A_SUCCESS(ret) ? 0 : ret;
+}
+#endif /* CONFIG_PM */
+
+static HIF_DEVICE *
+addHifDevice(struct sdio_func *func)
+{
+ HIF_DEVICE *hifdevice;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n"));
+ AR_DEBUG_ASSERT(func != NULL);
+ hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL);
+ AR_DEBUG_ASSERT(hifdevice != NULL);
+#if HIF_USE_DMA_BOUNCE_BUFFER
+ hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
+ AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL);
+#endif
+ hifdevice->func = func;
+ sdio_set_drvdata(func, hifdevice);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice));
+ return hifdevice;
+}
+
+static HIF_DEVICE *
+getHifDevice(struct sdio_func *func)
+{
+ AR_DEBUG_ASSERT(func != NULL);
+ return (HIF_DEVICE *)sdio_get_drvdata(func);
+}
+
+static void
+delHifDevice(HIF_DEVICE * device)
+{
+ AR_DEBUG_ASSERT(device!= NULL);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device));
+ if (device->dma_buffer != NULL) {
+ kfree(device->dma_buffer);
+ }
+ kfree(device);
+}
+
+static void ResetAllCards(void)
+{
+}
+
+void HIFClaimDevice(HIF_DEVICE *device, void *context)
+{
+ device->claimedContext = context;
+}
+
+void HIFReleaseDevice(HIF_DEVICE *device)
+{
+ device->claimedContext = NULL;
+}
+
+A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks)
+{
+ if (device->htcCallbacks.context != NULL) {
+ /* already in use! */
+ return A_ERROR;
+ }
+ device->htcCallbacks = *callbacks;
+ return A_OK;
+}
+
+void HIFDetachHTC(HIF_DEVICE *device)
+{
+ A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks));
+}
+
+#define SDIO_SET_CMD52_ARG(arg,rw,func,raw,address,writedata) \
+ (arg) = (((rw) & 1) << 31) | \
+ (((func) & 0x7) << 28) | \
+ (((raw) & 1) << 27) | \
+ (1 << 26) | \
+ (((address) & 0x1FFFF) << 9) | \
+ (1 << 8) | \
+ ((writedata) & 0xFF)
+
+#define SDIO_SET_CMD52_READ_ARG(arg,func,address) \
+ SDIO_SET_CMD52_ARG(arg,0,(func),0,address,0x00)
+#define SDIO_SET_CMD52_WRITE_ARG(arg,func,address,value) \
+ SDIO_SET_CMD52_ARG(arg,1,(func),0,address,value)
+
+static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte)
+{
+ struct mmc_command ioCmd;
+ unsigned long arg;
+
+ memset(&ioCmd,0,sizeof(ioCmd));
+ SDIO_SET_CMD52_WRITE_ARG(arg,0,address,byte);
+ ioCmd.opcode = SD_IO_RW_DIRECT;
+ ioCmd.arg = arg;
+ ioCmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
+
+ return mmc_wait_for_cmd(card->host, &ioCmd, 0);
+}
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
new file mode 100644
index 000000000000..de236d269f0d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
@@ -0,0 +1,390 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif_scatter.c" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF scatter implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio.h>
+#include <linux/kthread.h>
+#include "hif_internal.h"
+#define ATH_MODULE_NAME hif
+#include "a_debug.h"
+
+#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
+
+#define _CMD53_ARG_READ 0
+#define _CMD53_ARG_WRITE 1
+#define _CMD53_ARG_BLOCK_BASIS 1
+#define _CMD53_ARG_FIXED_ADDRESS 0
+#define _CMD53_ARG_INCR_ADDRESS 1
+
+#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
+ (arg) = (((rw) & 1) << 31) | \
+ (((func) & 0x7) << 28) | \
+ (((mode) & 1) << 27) | \
+ (((opcode) & 1) << 26) | \
+ (((address) & 0x1FFFF) << 9) | \
+ ((bytes_blocks) & 0x1FF)
+
+static void FreeScatterReq(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
+{
+ unsigned long flag;
+
+ spin_lock_irqsave(&device->lock, flag);
+
+ DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink);
+
+ spin_unlock_irqrestore(&device->lock, flag);
+
+}
+
+static HIF_SCATTER_REQ *AllocScatterReq(HIF_DEVICE *device)
+{
+ DL_LIST *pItem;
+ unsigned long flag;
+
+ spin_lock_irqsave(&device->lock, flag);
+
+ pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead);
+
+ spin_unlock_irqrestore(&device->lock, flag);
+
+ if (pItem != NULL) {
+ return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
+ }
+
+ return NULL;
+}
+
+ /* called by async task to perform the operation synchronously using direct MMC APIs */
+A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
+{
+ int i;
+ A_UINT8 rw;
+ A_UINT8 opcode;
+ struct mmc_request mmcreq;
+ struct mmc_command cmd;
+ struct mmc_data data;
+ HIF_SCATTER_REQ_PRIV *pReqPriv;
+ HIF_SCATTER_REQ *pReq;
+ A_STATUS status = A_OK;
+ struct scatterlist *pSg;
+
+ pReqPriv = busrequest->pScatterReq;
+
+ A_ASSERT(pReqPriv != NULL);
+
+ pReq = pReqPriv->pHifScatterReq;
+
+ memset(&mmcreq, 0, sizeof(struct mmc_request));
+ memset(&cmd, 0, sizeof(struct mmc_command));
+ memset(&data, 0, sizeof(struct mmc_data));
+
+ data.blksz = HIF_MBOX_BLOCK_SIZE;
+ data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n",
+ (pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks,
+ pReq->TotalLength,pReq->ValidScatterEntries));
+
+ if (pReq->Request & HIF_WRITE) {
+ rw = _CMD53_ARG_WRITE;
+ data.flags = MMC_DATA_WRITE;
+ } else {
+ rw = _CMD53_ARG_READ;
+ data.flags = MMC_DATA_READ;
+ }
+
+ if (pReq->Request & HIF_FIXED_ADDRESS) {
+ opcode = _CMD53_ARG_FIXED_ADDRESS;
+ } else {
+ opcode = _CMD53_ARG_INCR_ADDRESS;
+ }
+
+ /* fill SG entries */
+ pSg = pReqPriv->sgentries;
+ sg_init_table(pSg, pReq->ValidScatterEntries);
+
+ /* assemble SG list */
+ for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) {
+ /* setup each sg entry */
+ if ((A_UINT32)pReq->ScatterList[i].pBuffer & 0x3) {
+ /* note some scatter engines can handle unaligned buffers, print this
+ * as informational only */
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
+ ("HIF: (%s) Scatter Buffer is unaligned 0x%08x\n",
+ pReq->Request & HIF_WRITE ? "WRITE":"READ",
+ (A_UINT32)pReq->ScatterList[i].pBuffer));
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, (" %d: Addr:0x%X, Len:%d \n",
+ i,(A_UINT32)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length));
+
+ sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length);
+ }
+ /* set scatter-gather table for request */
+ data.sg = pReqPriv->sgentries;
+ data.sg_len = pReq->ValidScatterEntries;
+ /* set command argument */
+ SDIO_SET_CMD53_ARG(cmd.arg,
+ rw,
+ device->func->num,
+ _CMD53_ARG_BLOCK_BASIS,
+ opcode,
+ pReq->Address,
+ data.blocks);
+
+ cmd.opcode = SD_IO_RW_EXTENDED;
+ cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+
+ mmcreq.cmd = &cmd;
+ mmcreq.data = &data;
+
+ mmc_set_data_timeout(&data, device->func->card);
+ /* synchronous call to process request */
+ mmc_wait_for_req(device->func->card->host, &mmcreq);
+
+ if (cmd.error) {
+ status = A_ERROR;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error));
+ }
+
+ if (data.error) {
+ status = A_ERROR;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error));
+ }
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
+ (pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks));
+ }
+
+ /* set completion status, fail or success */
+ pReq->CompletionStatus = status;
+
+ if (pReq->Request & HIF_ASYNCHRONOUS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%X (%d)\n",(unsigned int)busrequest, status));
+ /* complete the request */
+ A_ASSERT(pReq->CompletionRoutine != NULL);
+ pReq->CompletionRoutine(pReq);
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%X (%d)\n", (unsigned int)busrequest,status));
+ /* signal wait */
+ up(&busrequest->sem_req);
+ }
+
+ return status;
+}
+
+ /* callback to issue a read-write scatter request */
+static A_STATUS HifReadWriteScatter(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
+{
+ A_STATUS status = A_EINVAL;
+ A_UINT32 request = pReq->Request;
+ HIF_SCATTER_REQ_PRIV *pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
+
+ do {
+
+ A_ASSERT(pReqPriv != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n",
+ pReq->TotalLength, pReq->ValidScatterEntries));
+
+ if (!(request & HIF_EXTENDED_IO)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("HIF-SCATTER: Invalid command type: 0x%08x\n", request));
+ break;
+ }
+
+ if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request));
+ break;
+ }
+
+ if (!(request & HIF_BLOCK_BASIS)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("HIF-SCATTER: Invalid data mode: 0x%08x\n", request));
+ break;
+ }
+
+ if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength));
+ break;
+ }
+
+ if (pReq->TotalLength == 0) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* add bus request to the async list for the async I/O thread to process */
+ AddToAsyncList(device, pReqPriv->busrequest);
+
+ if (request & HIF_SYNCHRONOUS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%X\n", (unsigned int)pReqPriv->busrequest));
+ /* signal thread and wait */
+ up(&device->sem_async);
+ if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n"));
+ /* interrupted, exit */
+ status = A_ERROR;
+ break;
+ } else {
+ status = pReq->CompletionStatus;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%X\n", (unsigned int)pReqPriv->busrequest));
+ /* wake thread, it will process and then take care of the async callback */
+ up(&device->sem_async);
+ status = A_OK;
+ }
+
+ } while (FALSE);
+
+ if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+ pReq->CompletionStatus = status;
+ pReq->CompletionRoutine(pReq);
+ status = A_OK;
+ }
+
+ return status;
+}
+
+ /* setup of HIF scatter resources */
+A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo)
+{
+ A_STATUS status = A_ERROR;
+ int i;
+ HIF_SCATTER_REQ_PRIV *pReqPriv;
+ BUS_REQUEST *busrequest;
+
+ do {
+
+ /* check if host supports scatter requests and it meets our requirements */
+ if (device->func->card->host->max_hw_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n",
+ device->func->card->host->max_hw_segs, MAX_SCATTER_ENTRIES_PER_REQ));
+ status = A_ENOTSUP;
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n",
+ MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ));
+
+ for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {
+ /* allocate the private request blob */
+ pReqPriv = (HIF_SCATTER_REQ_PRIV *)A_MALLOC(sizeof(HIF_SCATTER_REQ_PRIV));
+ if (NULL == pReqPriv) {
+ break;
+ }
+ A_MEMZERO(pReqPriv, sizeof(HIF_SCATTER_REQ_PRIV));
+ /* save the device instance*/
+ pReqPriv->device = device;
+ /* allocate the scatter request */
+ pReqPriv->pHifScatterReq = (HIF_SCATTER_REQ *)A_MALLOC(sizeof(HIF_SCATTER_REQ) +
+ (MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM)));
+
+ if (NULL == pReqPriv->pHifScatterReq) {
+ A_FREE(pReqPriv);
+ break;
+ }
+ /* just zero the main part of the scatter request */
+ A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(HIF_SCATTER_REQ));
+ /* back pointer to the private struct */
+ pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv;
+ /* allocate a bus request for this scatter request */
+ busrequest = hifAllocateBusRequest(device);
+ if (NULL == busrequest) {
+ A_FREE(pReqPriv->pHifScatterReq);
+ A_FREE(pReqPriv);
+ break;
+ }
+ /* assign the scatter request to this bus request */
+ busrequest->pScatterReq = pReqPriv;
+ /* point back to the request */
+ pReqPriv->busrequest = busrequest;
+ /* add it to the scatter pool */
+ FreeScatterReq(device,pReqPriv->pHifScatterReq);
+ }
+
+ if (i != MAX_SCATTER_REQUESTS) {
+ status = A_NO_MEMORY;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n"));
+ break;
+ }
+
+ /* set scatter function pointers */
+ pInfo->pAllocateReqFunc = AllocScatterReq;
+ pInfo->pFreeReqFunc = FreeScatterReq;
+ pInfo->pReadWriteScatterFunc = HifReadWriteScatter;
+ pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ;
+ pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE;
+
+ status = A_OK;
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ CleanupHIFScatterResources(device);
+ }
+
+ return status;
+}
+
+ /* clean up scatter support */
+void CleanupHIFScatterResources(HIF_DEVICE *device)
+{
+ HIF_SCATTER_REQ_PRIV *pReqPriv;
+ HIF_SCATTER_REQ *pReq;
+
+ /* empty the free list */
+
+ while (1) {
+
+ pReq = AllocScatterReq(device);
+
+ if (NULL == pReq) {
+ break;
+ }
+
+ pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
+ A_ASSERT(pReqPriv != NULL);
+
+ if (pReqPriv->busrequest != NULL) {
+ pReqPriv->busrequest->pScatterReq = NULL;
+ /* free bus request */
+ hifFreeBusRequest(device, pReqPriv->busrequest);
+ pReqPriv->busrequest = NULL;
+ }
+
+ if (pReqPriv->pHifScatterReq != NULL) {
+ A_FREE(pReqPriv->pHifScatterReq);
+ pReqPriv->pHifScatterReq = NULL;
+ }
+
+ A_FREE(pReqPriv);
+ }
+}
+
+#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c
new file mode 100644
index 000000000000..dfcc60b548e4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c
@@ -0,0 +1,1399 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K device layer that handles register level I/O
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+#define MAILBOX_FOR_BLOCK_SIZE 1
+
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+
+static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev);
+
+void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
+{
+ LOCK_AR6K(pDev);
+ HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
+ UNLOCK_AR6K(pDev);
+}
+
+HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
+{
+ HTC_PACKET *pPacket;
+
+ LOCK_AR6K(pDev);
+ pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
+ UNLOCK_AR6K(pDev);
+
+ return pPacket;
+}
+
+void DevCleanup(AR6K_DEVICE *pDev)
+{
+ DevCleanupGMbox(pDev);
+
+ if (pDev->HifAttached) {
+ HIFDetachHTC(pDev->HIFDevice);
+ pDev->HifAttached = FALSE;
+ }
+
+ DevCleanupVirtualScatterSupport(pDev);
+
+ if (A_IS_MUTEX_VALID(&pDev->Lock)) {
+ A_MUTEX_DELETE(&pDev->Lock);
+ }
+}
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev)
+{
+ A_UINT32 blocksizes[AR6K_MAILBOXES];
+ A_STATUS status = A_OK;
+ int i;
+ HTC_CALLBACKS htcCallbacks;
+
+ do {
+
+ DL_LIST_INIT(&pDev->ScatterReqHead);
+ /* initialize our free list of IO packets */
+ INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
+ A_MUTEX_INIT(&pDev->Lock);
+
+ A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
+ /* the device layer handles these */
+ htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
+ htcCallbacks.dsrHandler = DevDsrHandler;
+ htcCallbacks.context = pDev;
+
+ status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ pDev->HifAttached = TRUE;
+
+ /* get the addresses for all 4 mailboxes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+ &pDev->MailBoxInfo, sizeof(pDev->MailBoxInfo));
+
+ if (status != A_OK) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* carve up register I/O packets (these are for ASYNC register I/O ) */
+ for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
+ HTC_PACKET *pIOPacket;
+ pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
+ SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
+ pDev,
+ pDev->RegIOBuffers[i].Buffer,
+ AR6K_REG_IO_BUFFER_SIZE,
+ 0); /* don't care */
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ /* get the block sizes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ blocksizes, sizeof(blocksizes));
+
+ if (status != A_OK) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* note: we actually get the block size of a mailbox other than 0, for SDIO the block
+ * size on mailbox 0 is artificially set to 1. So we use the block size that is set
+ * for the other 3 mailboxes */
+ pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
+ /* must be a power of 2 */
+ A_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
+
+ /* assemble mask, used for padding to a block */
+ pDev->BlockMask = pDev->BlockSize - 1;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
+ pDev->BlockSize, pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]));
+
+ pDev->GetPendingEventsFunc = NULL;
+ /* see if the HIF layer implements the get pending events function */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+ &pDev->GetPendingEventsFunc,
+ sizeof(pDev->GetPendingEventsFunc));
+
+ /* assume we can process HIF interrupt events asynchronously */
+ pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
+
+ /* see if the HIF layer overrides this assumption */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_IRQ_PROC_MODE,
+ &pDev->HifIRQProcessingMode,
+ sizeof(pDev->HifIRQProcessingMode));
+
+ switch (pDev->HifIRQProcessingMode) {
+ case HIF_DEVICE_IRQ_SYNC_ONLY:
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("HIF Interrupt processing is SYNC ONLY\n"));
+ /* see if HIF layer wants HTC to yield */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
+ &pDev->HifIRQYieldParams,
+ sizeof(pDev->HifIRQYieldParams));
+
+ if (pDev->HifIRQYieldParams.RecvPacketYieldCount > 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ ("HIF requests that DSR yield per %d RECV packets \n",
+ pDev->HifIRQYieldParams.RecvPacketYieldCount));
+ pDev->DSRCanYield = TRUE;
+ }
+ break;
+ case HIF_DEVICE_IRQ_ASYNC_SYNC:
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
+ break;
+ default:
+ A_ASSERT(FALSE);
+ }
+
+ pDev->HifMaskUmaskRecvEvent = NULL;
+
+ /* see if the HIF layer implements the mask/unmask recv events function */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+ &pDev->HifMaskUmaskRecvEvent,
+ sizeof(pDev->HifMaskUmaskRecvEvent));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n",
+ (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent));
+
+ status = DevDisableInterrupts(pDev);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ status = DevSetupGMbox(pDev);
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ if (pDev->HifAttached) {
+ HIFDetachHTC(pDev->HIFDevice);
+ pDev->HifAttached = FALSE;
+ }
+ }
+
+ return status;
+
+}
+
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+
+ LOCK_AR6K(pDev);
+
+ /* Enable all the interrupts except for the internal AR6000 CPU interrupt */
+ pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
+ INT_STATUS_ENABLE_CPU_SET(0x01) |
+ INT_STATUS_ENABLE_COUNTER_SET(0x01);
+
+ if (NULL == pDev->GetPendingEventsFunc) {
+ pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ } else {
+ /* The HIF layer provided us with a pending events function which means that
+ * the detection of pending mbox messages is handled in the HIF layer.
+ * This is the case for the SPI2 interface.
+ * In the normal case we enable MBOX interrupts, for the case
+ * with HIFs that offer this mechanism, we keep these interrupts
+ * masked */
+ pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ }
+
+
+ /* Set up the CPU Interrupt Status Register */
+ pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
+
+ /* Set up the Error Interrupt Status Register */
+ pDev->IrqEnableRegisters.error_status_enable =
+ ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
+ ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
+
+ /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
+ pDev->IrqEnableRegisters.counter_int_status_enable =
+ COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
+
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ UNLOCK_AR6K(pDev);
+
+ /* always synchronous */
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ /* Can't write it for some reason */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Failed to update interrupt control registers err: %d\n", status));
+
+ }
+
+ return status;
+}
+
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
+{
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+
+ LOCK_AR6K(pDev);
+ /* Disable all interrupts */
+ pDev->IrqEnableRegisters.int_status_enable = 0;
+ pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
+ pDev->IrqEnableRegisters.error_status_enable = 0;
+ pDev->IrqEnableRegisters.counter_int_status_enable = 0;
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ UNLOCK_AR6K(pDev);
+
+ /* always synchronous */
+ return HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+}
+
+/* enable device interrupts */
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
+{
+ /* for good measure, make sure interrupt are disabled before unmasking at the HIF
+ * layer.
+ * The rationale here is that between device insertion (where we clear the interrupts the first time)
+ * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets.
+ * The AR6K interrupt enables reset back to an "enabled" state when this happens.
+ * */
+ DevDisableInterrupts(pDev);
+
+ /* Unmask the host controller interrupts */
+ HIFUnMaskInterrupt(pDev->HIFDevice);
+
+ return DevEnableInterrupts(pDev);
+}
+
+/* disable all device interrupts */
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
+{
+ /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while
+ * we zero out our shadow registers in DevDisableInterrupts()*/
+ HIFMaskInterrupt(pDev->HIFDevice);
+
+ return DevDisableInterrupts(pDev);
+}
+
+/* callback when our fetch to enable/disable completes */
+static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Failed to disable receiver, status:%d \n", pPacket->Status));
+ }
+ /* free this IO packet */
+ AR6KFreeIOPacket(pDev,pPacket);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "override" method when the HIF reports another methods to
+ * disable recv events */
+static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
+ EnableRecv,AsyncMode));
+
+ do {
+
+ if (AsyncMode) {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+ pIOPacket->pContext = pDev;
+
+ /* call the HIF layer override and do this asynchronously */
+ status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+ EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+ pIOPacket);
+ break;
+ }
+
+ /* if we get here we are doing it synchronously */
+ status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+ EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+ NULL);
+
+ } while (FALSE);
+
+ if (A_FAILED(status) && (pIOPacket != NULL)) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ return status;
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "normal" method using the interrupt enable registers through
+ * the host I/F */
+static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+
+ /* take the lock to protect interrupt enable shadows */
+ LOCK_AR6K(pDev);
+
+ if (EnableRecv) {
+ pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ } else {
+ pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ }
+
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+ UNLOCK_AR6K(pDev);
+
+ do {
+
+ if (AsyncMode) {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* copy values to write to our async I/O buffer */
+ A_MEMCPY(pIOPacket->pBuffer,&regs,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+ pIOPacket->pContext = pDev;
+
+ /* write it out asynchronously */
+ HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_ASYNC_BYTE_INC,
+ pIOPacket);
+ break;
+ }
+
+ /* if we get here we are doing it synchronously */
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ } while (FALSE);
+
+ if (A_FAILED(status) && (pIOPacket != NULL)) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ return status;
+}
+
+
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+ if (NULL == pDev->HifMaskUmaskRecvEvent) {
+ return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
+ } else {
+ return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
+ }
+}
+
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+ if (NULL == pDev->HifMaskUmaskRecvEvent) {
+ return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
+ } else {
+ return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
+ }
+}
+
+void DevDumpRegisters(AR6K_DEVICE *pDev,
+ AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
+ AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("\n<------- Register Table -------->\n"));
+
+ if (pIrqProcRegs != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Host Int Status: 0x%x\n",pIrqProcRegs->host_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0]));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1]));
+
+ if (pDev->MailBoxInfo.GMboxAddress != 0) {
+ /* if the target supports GMBOX hardware, dump some additional state */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("GMBOX Host Int Status 2: 0x%x\n",pIrqProcRegs->host_int_status2));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("GMBOX RX Avail: 0x%x\n",pIrqProcRegs->gmbox_rx_avail));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("GMBOX lookahead alias 0: 0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[0]));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("GMBOX lookahead alias 1: 0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[1]));
+ }
+
+ }
+
+ if (pIrqEnableRegs != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------->\n"));
+}
+
+
+#define DEV_GET_VIRT_DMA_INFO(p) ((DEV_SCATTER_DMA_VIRTUAL_INFO *)((p)->HIFPrivate[0]))
+
+static HIF_SCATTER_REQ *DevAllocScatterReq(HIF_DEVICE *Context)
+{
+ DL_LIST *pItem;
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+ LOCK_AR6K(pDev);
+ pItem = DL_ListRemoveItemFromHead(&pDev->ScatterReqHead);
+ UNLOCK_AR6K(pDev);
+ if (pItem != NULL) {
+ return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
+ }
+ return NULL;
+}
+
+static void DevFreeScatterReq(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+ LOCK_AR6K(pDev);
+ DL_ListInsertTail(&pDev->ScatterReqHead, &pReq->ListLink);
+ UNLOCK_AR6K(pDev);
+}
+
+A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA)
+{
+ A_UINT8 *pDMABuffer = NULL;
+ int i, remaining;
+ A_UINT32 length;
+
+ pDMABuffer = pReq->pScatterBounceBuffer;
+
+ if (pDMABuffer == NULL) {
+ A_ASSERT(FALSE);
+ return A_EINVAL;
+ }
+
+ remaining = (int)pReq->TotalLength;
+
+ for (i = 0; i < pReq->ValidScatterEntries; i++) {
+
+ length = min((int)pReq->ScatterList[i].Length, remaining);
+
+ if (length != (int)pReq->ScatterList[i].Length) {
+ A_ASSERT(FALSE);
+ /* there is a problem with the scatter list */
+ return A_EINVAL;
+ }
+
+ if (FromDMA) {
+ /* from DMA buffer */
+ A_MEMCPY(pReq->ScatterList[i].pBuffer, pDMABuffer , length);
+ } else {
+ /* to DMA buffer */
+ A_MEMCPY(pDMABuffer, pReq->ScatterList[i].pBuffer, length);
+ }
+
+ pDMABuffer += length;
+ remaining -= length;
+ }
+
+ return A_OK;
+}
+
+static void DevReadWriteScatterAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+ HIF_SCATTER_REQ *pReq = (HIF_SCATTER_REQ *)pPacket->pPktContext;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevReadWriteScatterAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ pReq->CompletionStatus = pPacket->Status;
+
+ AR6KFreeIOPacket(pDev,pPacket);
+
+ pReq->CompletionRoutine(pReq);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevReadWriteScatterAsyncHandler \n"));
+}
+
+static A_STATUS DevReadWriteScatter(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+ A_UINT32 request = pReq->Request;
+
+ do {
+
+ if (pReq->TotalLength > AR6K_MAX_TRANSFER_SIZE_PER_SCATTER) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Invalid length: %d \n", pReq->TotalLength));
+ break;
+ }
+
+ if (pReq->TotalLength == 0) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ if (request & HIF_ASYNCHRONOUS) {
+ /* use an I/O packet to carry this request */
+ pIOPacket = AR6KAllocIOPacket(pDev);
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ /* save the request */
+ pIOPacket->pPktContext = pReq;
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevReadWriteScatterAsyncHandler;
+ pIOPacket->pContext = pDev;
+ }
+
+ if (request & HIF_WRITE) {
+ /* in virtual DMA, we are issuing the requests through the legacy HIFReadWrite API
+ * this API will adjust the address automatically for the last byte to fall on the mailbox
+ * EOM. */
+
+ /* if the address is an extended address, we can adjust the address here since the extended
+ * address will bypass the normal checks in legacy HIF layers */
+ if (pReq->Address == pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress) {
+ pReq->Address += pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize - pReq->TotalLength;
+ }
+ }
+
+ /* use legacy readwrite */
+ status = HIFReadWrite(pDev->HIFDevice,
+ pReq->Address,
+ DEV_GET_VIRT_DMA_INFO(pReq)->pVirtDmaBuffer,
+ pReq->TotalLength,
+ request,
+ (request & HIF_ASYNCHRONOUS) ? pIOPacket : NULL);
+
+ } while (FALSE);
+
+ if ((status != A_PENDING) && A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+ if (pIOPacket != NULL) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+ pReq->CompletionStatus = status;
+ pReq->CompletionRoutine(pReq);
+ status = A_OK;
+ }
+
+ return status;
+}
+
+
+static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev)
+{
+ HIF_SCATTER_REQ *pReq;
+
+ while (1) {
+ pReq = DevAllocScatterReq((HIF_DEVICE *)pDev);
+ if (NULL == pReq) {
+ break;
+ }
+ A_FREE(pReq);
+ }
+
+}
+
+ /* function to set up virtual scatter support if HIF layer has not implemented the interface */
+static A_STATUS DevSetupVirtualScatterSupport(AR6K_DEVICE *pDev)
+{
+ A_STATUS status = A_OK;
+ int bufferSize, sgreqSize;
+ int i;
+ DEV_SCATTER_DMA_VIRTUAL_INFO *pVirtualInfo;
+ HIF_SCATTER_REQ *pReq;
+
+ bufferSize = sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO) +
+ 2 * (A_GET_CACHE_LINE_BYTES()) + AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
+
+ sgreqSize = sizeof(HIF_SCATTER_REQ) +
+ (AR6K_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM));
+
+ for (i = 0; i < AR6K_SCATTER_REQS; i++) {
+ /* allocate the scatter request, buffer info and the actual virtual buffer itself */
+ pReq = (HIF_SCATTER_REQ *)A_MALLOC(sgreqSize + bufferSize);
+
+ if (NULL == pReq) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ A_MEMZERO(pReq, sgreqSize);
+
+ /* the virtual DMA starts after the scatter request struct */
+ pVirtualInfo = (DEV_SCATTER_DMA_VIRTUAL_INFO *)((A_UINT8 *)pReq + sgreqSize);
+ A_MEMZERO(pVirtualInfo, sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO));
+
+ pVirtualInfo->pVirtDmaBuffer = &pVirtualInfo->DataArea[0];
+ /* align buffer to cache line in case host controller can actually DMA this */
+ pVirtualInfo->pVirtDmaBuffer = A_ALIGN_TO_CACHE_LINE(pVirtualInfo->pVirtDmaBuffer);
+ /* store the structure in the private area */
+ pReq->HIFPrivate[0] = pVirtualInfo;
+ /* we emulate a DMA bounce interface */
+ pReq->ScatterMethod = HIF_SCATTER_DMA_BOUNCE;
+ pReq->pScatterBounceBuffer = pVirtualInfo->pVirtDmaBuffer;
+ /* free request to the list */
+ DevFreeScatterReq((HIF_DEVICE *)pDev,pReq);
+ }
+
+ if (A_FAILED(status)) {
+ DevCleanupVirtualScatterSupport(pDev);
+ } else {
+ pDev->HifScatterInfo.pAllocateReqFunc = DevAllocScatterReq;
+ pDev->HifScatterInfo.pFreeReqFunc = DevFreeScatterReq;
+ pDev->HifScatterInfo.pReadWriteScatterFunc = DevReadWriteScatter;
+ pDev->HifScatterInfo.MaxScatterEntries = AR6K_SCATTER_ENTRIES_PER_REQ;
+ pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
+ pDev->ScatterIsVirtual = TRUE;
+ }
+
+ return status;
+}
+
+
+A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer)
+{
+ A_STATUS status;
+
+ if (pDev->MailBoxInfo.Flags & HIF_MBOX_FLAG_NO_BUNDLING) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HIF requires bundling disabled\n"));
+ return A_ENOTSUP;
+ }
+
+ status = HIFConfigureDevice(pDev->HIFDevice,
+ HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
+ &pDev->HifScatterInfo,
+ sizeof(pDev->HifScatterInfo));
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ ("AR6K: ** HIF layer does not support scatter requests (%d) \n",status));
+
+ /* we can try to use a virtual DMA scatter mechanism using legacy HIFReadWrite() */
+ status = DevSetupVirtualScatterSupport(pDev);
+
+ if (A_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("AR6K: virtual scatter transfers enabled (max scatter items:%d: maxlen:%d) \n",
+ DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
+ }
+
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("AR6K: HIF layer supports scatter requests (max scatter items:%d: maxlen:%d) \n",
+ DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
+ }
+
+ if (A_SUCCESS(status)) {
+ /* for the recv path, the maximum number of bytes per recv bundle is just limited
+ * by the maximum transfer size at the HIF layer */
+ pDev->MaxRecvBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
+
+ /* for the send path, the max transfer size is limited by the existence and size of
+ * the extended mailbox address range */
+ if (pDev->MailBoxInfo.MboxProp[0].ExtendedAddress != 0) {
+ pDev->MaxSendBundleSize = pDev->MailBoxInfo.MboxProp[0].ExtendedSize;
+ } else {
+ /* legacy */
+ pDev->MaxSendBundleSize = AR6K_LEGACY_MAX_WRITE_LENGTH;
+ }
+
+ if (pDev->MaxSendBundleSize > pDev->HifScatterInfo.MaxTransferSizePerScatterReq) {
+ /* limit send bundle size to what the HIF can support for scatter requests */
+ pDev->MaxSendBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("AR6K: max recv: %d max send: %d \n",
+ DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev), DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)));
+
+ }
+ return status;
+}
+
+A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async)
+{
+ A_STATUS status;
+
+ if (Read) {
+ /* read operation */
+ pScatterReq->Request = (Async) ? HIF_RD_ASYNC_BLOCK_FIX : HIF_RD_SYNC_BLOCK_FIX;
+ pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
+ A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev));
+ } else {
+ A_UINT32 mailboxWidth;
+
+ /* write operation */
+ pScatterReq->Request = (Async) ? HIF_WR_ASYNC_BLOCK_INC : HIF_WR_SYNC_BLOCK_INC;
+ A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev));
+ if (pScatterReq->TotalLength > AR6K_LEGACY_MAX_WRITE_LENGTH) {
+ /* for large writes use the extended address */
+ pScatterReq->Address = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress;
+ mailboxWidth = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize;
+ } else {
+ pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
+ mailboxWidth = AR6K_LEGACY_MAX_WRITE_LENGTH;
+ }
+
+ if (!pDev->ScatterIsVirtual) {
+ /* we are passing this scatter list down to the HIF layer' scatter request handler, fixup the address
+ * so that the last byte falls on the EOM, we do this for those HIFs that support the
+ * scatter API */
+ pScatterReq->Address += (mailboxWidth - pScatterReq->TotalLength);
+ }
+
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV | ATH_DEBUG_SEND,
+ ("DevSubmitScatterRequest, Entries: %d, Total Length: %d Mbox:0x%X (mode: %s : %s)\n",
+ pScatterReq->ValidScatterEntries,
+ pScatterReq->TotalLength,
+ pScatterReq->Address,
+ Async ? "ASYNC" : "SYNC",
+ (Read) ? "RD" : "WR"));
+
+ status = DEV_PREPARE_SCATTER_OPERATION(pScatterReq);
+
+ if (A_FAILED(status)) {
+ if (Async) {
+ pScatterReq->CompletionStatus = status;
+ pScatterReq->CompletionRoutine(pScatterReq);
+ return A_OK;
+ }
+ return status;
+ }
+
+ status = pDev->HifScatterInfo.pReadWriteScatterFunc(pDev->ScatterIsVirtual ? pDev : pDev->HIFDevice,
+ pScatterReq);
+ if (!Async) {
+ /* in sync mode, we can touch the scatter request */
+ pScatterReq->CompletionStatus = status;
+ DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+ } else {
+ if (status == A_PENDING) {
+ status = A_OK;
+ }
+ }
+
+ return status;
+}
+
+
+#ifdef MBOXHW_UNIT_TEST
+
+
+/* This is a mailbox hardware unit test that must be called in a schedulable context
+ * This test is very simple, it will send a list of buffers with a counting pattern
+ * and the target will invert the data and send the message back
+ *
+ * the unit test has the following constraints:
+ *
+ * The target has at least 8 buffers of 256 bytes each. The host will send
+ * the following pattern of buffers in rapid succession :
+ *
+ * 1 buffer - 128 bytes
+ * 1 buffer - 256 bytes
+ * 1 buffer - 512 bytes
+ * 1 buffer - 1024 bytes
+ *
+ * The host will send the buffers to one mailbox and wait for buffers to be reflected
+ * back from the same mailbox. The target sends the buffers FIFO order.
+ * Once the final buffer has been received for a mailbox, the next mailbox is tested.
+ *
+ *
+ * Note: To simplifythe test , we assume that the chosen buffer sizes
+ * will fall on a nice block pad
+ *
+ * It is expected that higher-order tests will be written to stress the mailboxes using
+ * a message-based protocol (with some performance timming) that can create more
+ * randomness in the packets sent over mailboxes.
+ *
+ * */
+
+#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1))
+
+#define BUFFER_BLOCK_PAD 128
+
+#if 0
+#define BUFFER1 128
+#define BUFFER2 256
+#define BUFFER3 512
+#define BUFFER4 1024
+#endif
+
+#if 1
+#define BUFFER1 80
+#define BUFFER2 200
+#define BUFFER3 444
+#define BUFFER4 800
+#endif
+
+#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
+ A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
+ A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
+ A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
+
+#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4)
+
+#define TEST_CREDITS_RECV_TIMEOUT 100
+
+static A_UINT8 g_Buffer[TOTAL_BYTES];
+static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
+static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
+
+#define BUFFER_PROC_LIST_DEPTH 4
+
+typedef struct _BUFFER_PROC_LIST{
+ A_UINT8 *pBuffer;
+ A_UINT32 length;
+}BUFFER_PROC_LIST;
+
+
+#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
+{ \
+ (pList)->pBuffer = (pCurrpos); \
+ (pList)->length = (len); \
+ (pCurrpos) += (len); \
+ (pList)++; \
+}
+
+/* a simple and crude way to send different "message" sizes */
+static void AssembleBufferList(BUFFER_PROC_LIST *pList)
+{
+ A_UINT8 *pBuffer = g_Buffer;
+
+#if BUFFER_PROC_LIST_DEPTH < 4
+#error "Buffer processing list depth is not deep enough!!"
+#endif
+
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
+
+}
+
+#define FILL_ZERO TRUE
+#define FILL_COUNTING FALSE
+static void InitBuffers(A_BOOL Zero)
+{
+ A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
+ int i;
+
+ /* fill buffer with 16 bit counting pattern or zeros */
+ for (i = 0; i < (TOTAL_BYTES / 2) ; i++) {
+ if (!Zero) {
+ pBuffer16[i] = (A_UINT16)i;
+ } else {
+ pBuffer16[i] = 0;
+ }
+ }
+}
+
+
+static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
+{
+ int i;
+ A_UINT16 startCount;
+ A_BOOL success = TRUE;
+
+ /* get the starting count */
+ startCount = pBuffer16[0];
+ /* invert it, this is the expected value */
+ startCount = ~startCount;
+ /* scan the buffer and verify */
+ for (i = 0; i < (Length / 2) ; i++,startCount++) {
+ /* target will invert all the data */
+ if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
+ success = FALSE;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
+ pBuffer16[i], ((A_UINT16)~startCount), i, Length));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
+ pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
+ break;
+ }
+ }
+
+ return success;
+}
+
+static A_BOOL CheckBuffers(void)
+{
+ int i;
+ A_BOOL success = TRUE;
+ BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+ /* assemble the list */
+ AssembleBufferList(checkList);
+
+ /* scan the buffers and verify */
+ for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
+ success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
+ if (!success) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
+ (A_UINT32)checkList[i].pBuffer, checkList[i].length));
+ break;
+ }
+ }
+
+ return success;
+}
+
+ /* find the end marker for the last buffer we will be sending */
+static A_UINT16 GetEndMarker(void)
+{
+ A_UINT8 *pBuffer;
+ BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+ /* fill up buffers with the normal counting pattern */
+ InitBuffers(FILL_COUNTING);
+
+ /* assemble the list we will be sending down */
+ AssembleBufferList(checkList);
+ /* point to the last 2 bytes of the last buffer */
+ pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
+
+ /* the last count in the last buffer is the marker */
+ return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
+}
+
+#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
+
+/* send the ordered buffers to the target */
+static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+ A_STATUS status = A_OK;
+ A_UINT32 request = HIF_WR_SYNC_BLOCK_INC;
+ BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
+ int i;
+ int totalBytes = 0;
+ int paddedLength;
+ int totalwPadding = 0;
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
+
+ /* fill buffer with counting pattern */
+ InitBuffers(FILL_COUNTING);
+
+ /* assemble the order in which we send */
+ AssembleBufferList(sendList);
+
+ for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
+
+ /* we are doing block transfers, so we need to pad everything to a block size */
+ paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
+ (~(g_BlockSizes[mbox] - 1));
+
+ /* send each buffer synchronously */
+ status = HIFReadWrite(pDev->HIFDevice,
+ g_MailboxAddrs[mbox],
+ sendList[i].pBuffer,
+ paddedLength,
+ request,
+ NULL);
+ if (status != A_OK) {
+ break;
+ }
+ totalBytes += sendList[i].length;
+ totalwPadding += paddedLength;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
+
+ return status;
+}
+
+/* poll the mailbox credit counter until we get a credit or timeout */
+static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
+{
+ A_STATUS status = A_OK;
+ int timeout = TEST_CREDITS_RECV_TIMEOUT;
+ A_UINT8 credits = 0;
+ A_UINT32 address;
+
+ while (TRUE) {
+
+ /* Read the counter register to get credits, this auto-decrements */
+ address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
+ status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
+ HIF_RD_SYNC_BYTE_FIX, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
+ status = A_ERROR;
+ break;
+ }
+
+ if (credits) {
+ break;
+ }
+
+ timeout--;
+
+ if (timeout <= 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
+ status = A_ERROR;
+ break;
+ }
+
+ /* delay a little, target may not be ready */
+ A_MDELAY(1000);
+
+ }
+
+ if (status == A_OK) {
+ *pCredits = credits;
+ }
+
+ return status;
+}
+
+
+/* wait for the buffers to come back */
+static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+ A_STATUS status = A_OK;
+ A_UINT32 request = HIF_RD_SYNC_BLOCK_INC;
+ BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
+ int curBuffer;
+ int credits;
+ int i;
+ int totalBytes = 0;
+ int paddedLength;
+ int totalwPadding = 0;
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
+
+ /* zero the buffers */
+ InitBuffers(FILL_ZERO);
+
+ /* assemble the order in which we should receive */
+ AssembleBufferList(recvList);
+
+ curBuffer = 0;
+
+ while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
+
+ /* get number of buffers that have been completed, this blocks
+ * until we get at least 1 credit or it times out */
+ status = GetCredits(pDev, mbox, &credits);
+
+ if (status != A_OK) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
+
+ /* get all the buffers that are sitting on the queue */
+ for (i = 0; i < credits; i++) {
+ A_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
+ /* recv the current buffer synchronously, the buffers should come back in
+ * order... with padding applied by the target */
+ paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
+ (~(g_BlockSizes[mbox] - 1));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ g_MailboxAddrs[mbox],
+ recvList[curBuffer].pBuffer,
+ paddedLength,
+ request,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
+ recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
+ break;
+ }
+
+ totalwPadding += paddedLength;
+ totalBytes += recvList[curBuffer].length;
+ curBuffer++;
+ }
+
+ if (status != A_OK) {
+ break;
+ }
+ /* go back and get some more */
+ credits = 0;
+ }
+
+ if (totalBytes != TEST_BYTES) {
+ A_ASSERT(FALSE);
+ } else {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
+ mbox, totalBytes, totalwPadding));
+ }
+
+ return status;
+
+
+}
+
+static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
+{
+ A_STATUS status;
+
+ do {
+ /* send out buffers */
+ status = SendBuffers(pDev,mbox);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
+ break;
+ }
+
+ /* go get them, this will block */
+ status = RecvBuffers(pDev, mbox);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
+ break;
+ }
+
+ /* check the returned data patterns */
+ if (!CheckBuffers()) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
+ status = A_ERROR;
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
+
+ } while (FALSE);
+
+ return status;
+}
+
+/* here is where the test starts */
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
+{
+ int i;
+ A_STATUS status;
+ int credits = 0;
+ A_UINT8 params[4];
+ int numBufs;
+ int bufferSize;
+ A_UINT16 temp;
+
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n"));
+
+ do {
+ /* get the addresses for all 4 mailboxes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+ g_MailboxAddrs, sizeof(g_MailboxAddrs));
+
+ if (status != A_OK) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* get the block sizes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ g_BlockSizes, sizeof(g_BlockSizes));
+
+ if (status != A_OK) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* note, the HIF layer usually reports mbox 0 to have a block size of
+ * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
+ * the same. */
+ g_BlockSizes[0] = g_BlockSizes[1];
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
+
+ if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
+ g_BlockSizes[1], BUFFER_BLOCK_PAD));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
+
+ /* the target lets us know it is ready by giving us 1 credit on
+ * mailbox 0 */
+ status = GetCredits(pDev, 0, &credits);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
+
+ /* read the first 4 scratch registers */
+ status = HIFReadWrite(pDev->HIFDevice,
+ SCRATCH_ADDRESS,
+ params,
+ 4,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
+ break;
+ }
+
+ numBufs = params[0];
+ bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
+ ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
+ numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
+
+ if ((numBufs * bufferSize) < TOTAL_BYTES) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
+ TOTAL_BYTES, (numBufs*bufferSize)));
+ status = A_ERROR;
+ break;
+ }
+
+ temp = GetEndMarker();
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ SCRATCH_ADDRESS + 4,
+ (A_UINT8 *)&temp,
+ 2,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
+
+ temp = (A_UINT16)g_BlockSizes[1];
+ /* convert to a mask */
+ temp = temp - 1;
+ status = HIFReadWrite(pDev->HIFDevice,
+ SCRATCH_ADDRESS + 6,
+ (A_UINT8 *)&temp,
+ 2,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
+
+ /* execute the test on each mailbox */
+ for (i = 0; i < AR6K_MAILBOXES; i++) {
+ status = DoOneMboxHWTest(pDev, i);
+ if (status != A_OK) {
+ break;
+ }
+ }
+
+ } while (FALSE);
+
+ if (status == A_OK) {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n"));
+ }
+ /* don't let HTC_Start continue, the target is actually not running any HTC code */
+ return A_ERROR;
+}
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h
new file mode 100644
index 000000000000..b71ddb96cbde
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h
@@ -0,0 +1,383 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k.h" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K device layer that handles register level I/O
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef AR6K_H_
+#define AR6K_H_
+
+#include "hci_transport_api.h"
+#include "../htc_debug.h"
+
+#define AR6K_MAILBOXES 4
+
+/* HTC runs over mailbox 0 */
+#define HTC_MAILBOX 0
+
+#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
+
+#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
+ INT_STATUS_ENABLE_CPU_MASK | \
+ INT_STATUS_ENABLE_COUNTER_MASK)
+
+
+//#define MBOXHW_UNIT_TEST 1
+
+#include "athstartpack.h"
+typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
+ A_UINT8 host_int_status;
+ A_UINT8 cpu_int_status;
+ A_UINT8 error_int_status;
+ A_UINT8 counter_int_status;
+ A_UINT8 mbox_frame;
+ A_UINT8 rx_lookahead_valid;
+ A_UINT8 host_int_status2;
+ A_UINT8 gmbox_rx_avail;
+ A_UINT32 rx_lookahead[2];
+ A_UINT32 rx_gmbox_lookahead_alias[2];
+} POSTPACK AR6K_IRQ_PROC_REGISTERS;
+
+#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
+
+typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
+ A_UINT8 int_status_enable;
+ A_UINT8 cpu_int_status_enable;
+ A_UINT8 error_status_enable;
+ A_UINT8 counter_int_status_enable;
+} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
+
+typedef PREPACK struct _AR6K_GMBOX_CTRL_REGISTERS {
+ A_UINT8 int_status_enable;
+} POSTPACK AR6K_GMBOX_CTRL_REGISTERS;
+
+#include "athendpack.h"
+
+#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
+
+#define AR6K_REG_IO_BUFFER_SIZE 32
+#define AR6K_MAX_REG_IO_BUFFERS 8
+#define FROM_DMA_BUFFER TRUE
+#define TO_DMA_BUFFER FALSE
+#define AR6K_SCATTER_ENTRIES_PER_REQ 16
+#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
+#define AR6K_SCATTER_REQS 4
+#define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
+
+/* buffers for ASYNC I/O */
+typedef struct AR6K_ASYNC_REG_IO_BUFFER {
+ HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */
+ A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE];
+} AR6K_ASYNC_REG_IO_BUFFER;
+
+typedef struct _AR6K_GMBOX_INFO {
+ void *pProtocolContext;
+ A_STATUS (*pMessagePendingCallBack)(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes);
+ A_STATUS (*pCreditsPendingCallback)(void *pContext, int NumCredits, A_BOOL CreditIRQEnabled);
+ void (*pTargetFailureCallback)(void *pContext, A_STATUS Status);
+ void (*pStateDumpCallback)(void *pContext);
+ A_BOOL CreditCountIRQEnabled;
+} AR6K_GMBOX_INFO;
+
+typedef struct _AR6K_DEVICE {
+ A_MUTEX_T Lock;
+ AR6K_IRQ_PROC_REGISTERS IrqProcRegisters;
+ AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters;
+ void *HIFDevice;
+ A_UINT32 BlockSize;
+ A_UINT32 BlockMask;
+ HIF_DEVICE_MBOX_INFO MailBoxInfo;
+ HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
+ void *HTCContext;
+ HTC_PACKET_QUEUE RegisterIOList;
+ AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
+ void (*TargetFailureCallback)(void *Context);
+ A_STATUS (*MessagePendingCallback)(void *Context,
+ A_UINT32 LookAheads[],
+ int NumLookAheads,
+ A_BOOL *pAsyncProc,
+ int *pNumPktsFetched);
+ HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode;
+ HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
+ A_BOOL HifAttached;
+ HIF_DEVICE_IRQ_YIELD_PARAMS HifIRQYieldParams;
+ A_BOOL DSRCanYield;
+ int CurrentDSRRecvCount;
+ HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo;
+ DL_LIST ScatterReqHead;
+ A_BOOL ScatterIsVirtual;
+ int MaxRecvBundleSize;
+ int MaxSendBundleSize;
+ AR6K_GMBOX_INFO GMboxInfo;
+ A_BOOL GMboxEnabled;
+ AR6K_GMBOX_CTRL_REGISTERS GMboxControlRegisters;
+ int RecheckIRQStatusCnt;
+} AR6K_DEVICE;
+
+#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
+#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
+#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev);
+void DevCleanup(AR6K_DEVICE *pDev);
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+ A_UINT32 *pLookAhead,
+ int TimeoutMS);
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
+A_STATUS DevDsrHandler(void *context);
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
+void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev);
+void DevDumpRegisters(AR6K_DEVICE *pDev,
+ AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
+ AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
+
+#define DEV_STOP_RECV_ASYNC TRUE
+#define DEV_STOP_RECV_SYNC FALSE
+#define DEV_ENABLE_RECV_ASYNC TRUE
+#define DEV_ENABLE_RECV_SYNC FALSE
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+
+
+#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
+#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
+#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
+
+static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
+ A_UINT32 paddedLength;
+ A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+ A_STATUS status;
+
+ /* adjust the length to be a multiple of block size if appropriate */
+ paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
+
+#if 0
+ if (paddedLength > pPacket->BufferLength) {
+ A_ASSERT(FALSE);
+ if (pPacket->Completion != NULL) {
+ COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+ return A_OK;
+ }
+ return A_EINVAL;
+ }
+#endif
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+ paddedLength,
+ pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+ sync ? "SYNC" : "ASYNC"));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+ pPacket->pBuffer,
+ paddedLength, /* the padded length */
+ sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+ sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
+
+ if (sync) {
+ pPacket->Status = status;
+ } else {
+ if (status == A_PENDING) {
+ status = A_OK;
+ }
+ }
+
+ return status;
+}
+
+static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
+ A_UINT32 paddedLength;
+ A_STATUS status;
+ A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+ /* adjust the length to be a multiple of block size if appropriate */
+ paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
+
+ if (paddedLength > pPacket->BufferLength) {
+ A_ASSERT(FALSE);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+ paddedLength,RecvLength,pPacket->BufferLength));
+ if (pPacket->Completion != NULL) {
+ COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+ return A_OK;
+ }
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("DevRecvPacket (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
+ (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
+ paddedLength,
+ pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+ sync ? "SYNC" : "ASYNC"));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
+ pPacket->pBuffer,
+ paddedLength,
+ sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
+ sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
+
+ if (sync) {
+ pPacket->Status = status;
+ }
+
+ return status;
+}
+
+#define DEV_CHECK_RECV_YIELD(pDev) \
+ ((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
+
+#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
+#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
+
+/**************************************************/
+/****** Scatter Function and Definitions
+ *
+ *
+ */
+
+A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA);
+
+ /* copy any READ data back into scatter list */
+#define DEV_FINISH_SCATTER_OPERATION(pR) \
+ if (A_SUCCESS((pR)->CompletionStatus) && \
+ !((pR)->Request & HIF_WRITE) && \
+ ((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \
+ (pR)->CompletionStatus = DevCopyScatterListToFromDMABuffer((pR),FROM_DMA_BUFFER); \
+ }
+
+ /* copy any WRITE data to bounce buffer */
+static INLINE A_STATUS DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ *pReq) {
+ if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
+ return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);
+ } else {
+ return A_OK;
+ }
+}
+
+
+A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer);
+
+#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries
+#define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
+#define DEV_ALLOC_SCATTER_REQ(pDev) \
+ (pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
+
+#define DEV_FREE_SCATTER_REQ(pDev,pR) \
+ (pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
+
+#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize
+#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize
+
+#define DEV_SCATTER_READ TRUE
+#define DEV_SCATTER_WRITE FALSE
+#define DEV_SCATTER_ASYNC TRUE
+#define DEV_SCATTER_SYNC FALSE
+A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async);
+
+#ifdef MBOXHW_UNIT_TEST
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
+#endif
+
+ /* completely virtual */
+typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO {
+ A_UINT8 *pVirtDmaBuffer; /* dma-able buffer - CPU accessible address */
+ A_UINT8 DataArea[1]; /* start of data area */
+} DEV_SCATTER_DMA_VIRTUAL_INFO;
+
+
+
+void DumpAR6KDevState(AR6K_DEVICE *pDev);
+
+/**************************************************/
+/****** GMBOX functions and definitions
+ *
+ *
+ */
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+
+void DevCleanupGMbox(AR6K_DEVICE *pDev);
+A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev);
+A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev);
+void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev);
+
+#else
+
+ /* compiled out */
+#define DevCleanupGMbox(p)
+#define DevCheckGMboxInterrupts(p) A_OK
+#define DevNotifyGMboxTargetFailure(p)
+
+static INLINE A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) {
+ pDev->GMboxEnabled = FALSE;
+ return A_OK;
+}
+
+#endif
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+
+ /* GMBOX protocol modules must expose each of these internal APIs */
+HCI_TRANSPORT_HANDLE GMboxAttachProtocol(AR6K_DEVICE *pDev, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev);
+void GMboxProtocolUninstall(AR6K_DEVICE *pDev);
+
+ /* API used by GMBOX protocol modules */
+AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle);
+#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
+{ \
+ (pDev)->GMboxInfo.pProtocolContext = (context); \
+ (pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \
+ (pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
+ (pDev)->GMboxInfo.pTargetFailureCallback = (failure); \
+ (pDev)->GMboxInfo.pStateDumpCallback = (statedump); \
+}
+
+#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
+
+A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength);
+A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength);
+
+#define PROC_IO_ASYNC TRUE
+#define PROC_IO_SYNC FALSE
+typedef enum GMBOX_IRQ_ACTION_TYPE {
+ GMBOX_ACTION_NONE = 0,
+ GMBOX_DISABLE_ALL,
+ GMBOX_ERRORS_IRQ_ENABLE,
+ GMBOX_RECV_IRQ_ENABLE,
+ GMBOX_RECV_IRQ_DISABLE,
+ GMBOX_CREDIT_IRQ_ENABLE,
+ GMBOX_CREDIT_IRQ_DISABLE,
+} GMBOX_IRQ_ACTION_TYPE;
+
+A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL AsyncMode);
+A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits);
+A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize);
+A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes);
+A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int AckTimeoutMS);
+
+#endif
+
+#endif /*AR6K_H_*/
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c
new file mode 100644
index 000000000000..178cbb3e2962
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c
@@ -0,0 +1,762 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_events.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR6K Driver layer event handling (i.e. interrupts, message polling)
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
+
+#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
+
+/* completion routine for ALL HIF layer async I/O */
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
+{
+ HTC_PACKET *pPacket = (HTC_PACKET *)context;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("+DevRWCompletionHandler (Pkt:0x%X) , Status: %d \n",
+ (A_UINT32)pPacket,
+ status));
+
+ COMPLETE_HTC_PACKET(pPacket,status);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("-DevRWCompletionHandler\n"));
+
+ return A_OK;
+}
+
+/* mailbox recv message polling */
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+ A_UINT32 *pLookAhead,
+ int TimeoutMS)
+{
+ A_STATUS status = A_OK;
+ int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
+
+ A_ASSERT(timeout > 0);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
+
+ while (TRUE) {
+
+ if (pDev->GetPendingEventsFunc != NULL) {
+
+ HIF_PENDING_EVENTS_INFO events;
+
+ /* the HIF layer uses a special mechanism to get events, do this
+ * synchronously */
+ status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+ &events,
+ NULL);
+ if (A_FAILED(status))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
+ break;
+ }
+
+ if (events.Events & HIF_RECV_MSG_AVAIL)
+ {
+ /* there is a message available, the lookahead should be valid now */
+ *pLookAhead = events.LookAhead;
+
+ break;
+ }
+ } else {
+
+ /* this is the standard HIF way.... */
+ /* load the register table */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ (A_UINT8 *)&pDev->IrqProcRegisters,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (A_FAILED(status)){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
+ break;
+ }
+
+ /* check for MBOX data and valid lookahead */
+ if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) {
+ if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
+ {
+ /* mailbox has a message and the look ahead is valid */
+ *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+ break;
+ }
+ }
+
+ }
+
+ timeout--;
+
+ if (timeout <= 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
+ status = A_ERROR;
+
+ /* check if the target asserted */
+ if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+ /* target signaled an assert, process this pending interrupt
+ * this will call the target failure handler */
+ DevServiceDebugInterrupt(pDev);
+ }
+
+ break;
+ }
+
+ /* delay a little */
+ A_MDELAY(DELAY_PER_INTERVAL_MS);
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout));
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
+
+ return status;
+}
+
+static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ A_UINT8 cpu_int_status;
+ A_UINT8 regBuffer[4];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
+ cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
+ pDev->IrqEnableRegisters.cpu_int_status_enable;
+ A_ASSERT(cpu_int_status);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
+ cpu_int_status));
+
+ /* Clear the interrupt */
+ pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
+
+ /* set up the register transfer buffer to hit the register 4 times , this is done
+ * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+ * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+ /* set W1C value to clear the interrupt, this hits the register first */
+ regBuffer[0] = cpu_int_status;
+ /* the remaining 4 values are set to zero which have no-effect */
+ regBuffer[1] = 0;
+ regBuffer[2] = 0;
+ regBuffer[3] = 0;
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ CPU_INT_STATUS_ADDRESS,
+ regBuffer,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+
+ A_ASSERT(status == A_OK);
+ return status;
+}
+
+
+static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ A_UINT8 error_int_status;
+ A_UINT8 regBuffer[4];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
+ error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
+ A_ASSERT(error_int_status);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
+ error_int_status));
+
+ if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
+ /* Wakeup */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
+ }
+
+ if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
+ /* Rx Underflow */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
+ }
+
+ if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
+ /* Tx Overflow */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
+ }
+
+ /* Clear the interrupt */
+ pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
+
+ /* set up the register transfer buffer to hit the register 4 times , this is done
+ * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+ * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+ /* set W1C value to clear the interrupt, this hits the register first */
+ regBuffer[0] = error_int_status;
+ /* the remaining 4 values are set to zero which have no-effect */
+ regBuffer[1] = 0;
+ regBuffer[2] = 0;
+ regBuffer[3] = 0;
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ ERROR_INT_STATUS_ADDRESS,
+ regBuffer,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+
+ A_ASSERT(status == A_OK);
+ return status;
+}
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
+{
+ A_UINT32 dummy;
+ A_STATUS status;
+
+ /* Send a target failure event to the application */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
+
+ if (pDev->TargetFailureCallback != NULL) {
+ pDev->TargetFailureCallback(pDev->HTCContext);
+ }
+
+ if (pDev->GMboxEnabled) {
+ DevNotifyGMboxTargetFailure(pDev);
+ }
+
+ /* clear the interrupt , the debug error interrupt is
+ * counter 0 */
+ /* read counter to clear interrupt */
+ status = HIFReadWrite(pDev->HIFDevice,
+ COUNT_DEC_ADDRESS,
+ (A_UINT8 *)&dummy,
+ 4,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ A_ASSERT(status == A_OK);
+ return status;
+}
+
+static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
+{
+ A_UINT8 counter_int_status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
+
+ counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+ pDev->IrqEnableRegisters.counter_int_status_enable;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
+ counter_int_status));
+
+ /* Check if the debug interrupt is pending
+ * NOTE: other modules like GMBOX may use the counter interrupt for
+ * credit flow control on other counters, we only need to check for the debug assertion
+ * counter interrupt */
+ if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+ return DevServiceDebugInterrupt(pDev);
+ }
+
+ return A_OK;
+}
+
+/* callback when our fetch to get interrupt status registers completes */
+static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+ A_UINT32 lookAhead = 0;
+ A_BOOL otherInts = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ do {
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
+ /* bail out, don't unmask HIF interrupt */
+ break;
+ }
+
+ if (pDev->GetPendingEventsFunc != NULL) {
+ /* the HIF layer collected the information for us */
+ HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
+ if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
+ lookAhead = pEvents->LookAhead;
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
+ }
+ }
+ if (pEvents->Events & HIF_OTHER_EVENTS) {
+ otherInts = TRUE;
+ }
+ } else {
+ /* standard interrupt table handling.... */
+ AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
+ A_UINT8 host_int_status;
+
+ host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
+
+ if (host_int_status & (1 << HTC_MAILBOX)) {
+ host_int_status &= ~(1 << HTC_MAILBOX);
+ if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+ /* mailbox has a message and the look ahead is valid */
+ lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
+ }
+ }
+ }
+
+ if (host_int_status) {
+ /* there are other interrupts to handle */
+ otherInts = TRUE;
+ }
+ }
+
+ if (otherInts || (lookAhead == 0)) {
+ /* if there are other interrupts to process, we cannot do this in the async handler so
+ * ack the interrupt which will cause our sync handler to run again
+ * if however there are no more messages, we can now ack the interrupt */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
+ otherInts, lookAhead));
+ HIFAckInterrupt(pDev->HIFDevice);
+ } else {
+ int fetched = 0;
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
+ lookAhead));
+ /* lookahead is non-zero and there are no other interrupts to service,
+ * go get the next message */
+ status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched);
+
+ if (A_SUCCESS(status) && !fetched) {
+ /* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n"));
+ DevAsyncIrqProcessComplete(pDev);
+ }
+ }
+
+ } while (FALSE);
+
+ /* free this IO packet */
+ AR6KFreeIOPacket(pDev,pPacket);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
+}
+
+/* called by the HTC layer when it wants us to check if the device has any more pending
+ * recv messages, this starts off a series of async requests to read interrupt registers */
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket;
+
+ /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
+ * cause us to switch contexts */
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ do {
+
+ if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+ /* break the async processing chain right here, no need to continue.
+ * The DevDsrHandler() will handle things in a loop when things are driven
+ * synchronously */
+ break;
+ }
+
+ /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
+ * the target, if upper layers determine that we are in a low-throughput mode, we can
+ * rely on taking another interrupt rather than re-checking the status registers which can
+ * re-wake the target */
+ if (pDev->RecheckIRQStatusCnt == 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
+ /* ack interrupt */
+ HIFAckInterrupt(pDev->HIFDevice);
+ break;
+ }
+
+ /* first allocate one of our HTC packets we created for async I/O
+ * we reuse HTC packet definitions so that we can use the completion mechanism
+ * in DevRWCompletionHandler() */
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ /* there should be only 1 asynchronous request out at a time to read these registers
+ * so this should actually never happen */
+ status = A_NO_MEMORY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevGetEventAsyncHandler;
+ pIOPacket->pContext = pDev;
+
+ if (pDev->GetPendingEventsFunc) {
+ /* HIF layer has it's own mechanism, pass the IO to it.. */
+ status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+ (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
+ pIOPacket);
+
+ } else {
+ /* standard way, read the interrupt register table asynchronously again */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_ASYNC_BYTE_INC,
+ pIOPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
+
+ return status;
+}
+
+void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
+ HIFAckInterrupt(pDev->HIFDevice);
+}
+
+/* process pending interrupts synchronously */
+static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 host_int_status = 0;
+ A_UINT32 lookAhead = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ /*** NOTE: the HIF implementation guarantees that the context of this call allows
+ * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
+ * can block or switch thread/task ontexts.
+ * This is a fully schedulable context.
+ * */
+ do {
+
+ if (pDev->IrqEnableRegisters.int_status_enable == 0) {
+ /* interrupt enables have been cleared, do not try to process any pending interrupts that
+ * may result in more bus transactions. The target may be unresponsive at this
+ * point. */
+ break;
+ }
+
+ if (pDev->GetPendingEventsFunc != NULL) {
+ HIF_PENDING_EVENTS_INFO events;
+
+ /* the HIF layer uses a special mechanism to get events
+ * get this synchronously */
+ status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+ &events,
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (events.Events & HIF_RECV_MSG_AVAIL) {
+ lookAhead = events.LookAhead;
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
+ }
+ }
+
+ if (!(events.Events & HIF_OTHER_EVENTS) ||
+ !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
+ /* no need to read the register table, no other interesting interrupts.
+ * Some interfaces (like SPI) can shadow interrupt sources without
+ * requiring the host to do a full table read */
+ break;
+ }
+
+ /* otherwise fall through and read the register table */
+ }
+
+ /*
+ * Read the first 28 bytes of the HTC register table. This will yield us
+ * the value of different int status registers and the lookahead
+ * registers.
+ * length = sizeof(int_status) + sizeof(cpu_int_status) +
+ * sizeof(error_int_status) + sizeof(counter_int_status) +
+ * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
+ * sizeof(hole) + sizeof(rx_lookahead) +
+ * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
+ * sizeof(error_status_enable) +
+ * sizeof(counter_int_status_enable);
+ *
+ */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ (A_UINT8 *)&pDev->IrqProcRegisters,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
+ DevDumpRegisters(pDev,
+ &pDev->IrqProcRegisters,
+ &pDev->IrqEnableRegisters);
+ }
+
+ /* Update only those registers that are enabled */
+ host_int_status = pDev->IrqProcRegisters.host_int_status &
+ pDev->IrqEnableRegisters.int_status_enable;
+
+ if (NULL == pDev->GetPendingEventsFunc) {
+ /* only look at mailbox status if the HIF layer did not provide this function,
+ * on some HIF interfaces reading the RX lookahead is not valid to do */
+ if (host_int_status & (1 << HTC_MAILBOX)) {
+ /* mask out pending mailbox value, we use "lookAhead" as the real flag for
+ * mailbox processing below */
+ host_int_status &= ~(1 << HTC_MAILBOX);
+ if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+ /* mailbox has a message and the look ahead is valid */
+ lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
+ }
+ }
+ }
+ } else {
+ /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
+ host_int_status &= ~(1 << HTC_MAILBOX);
+ }
+
+ if (pDev->GMboxEnabled) {
+ /*call GMBOX layer to process any interrupts of interest */
+ status = DevCheckGMboxInterrupts(pDev);
+ }
+
+ } while (FALSE);
+
+
+ do {
+
+ /* did the interrupt status fetches succeed? */
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if ((0 == host_int_status) && (0 == lookAhead)) {
+ /* nothing to process, the caller can use this to break out of a loop */
+ *pDone = TRUE;
+ break;
+ }
+
+ if (lookAhead != 0) {
+ int fetched = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
+ /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
+ * mailbox...
+ * When emptying the recv mailbox we use the async handler above called from the
+ * completion routine of the callers read request. This can improve performance
+ * by reducing context switching when we rapidly pull packets */
+ status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (!fetched) {
+ /* HTC could not pull any messages out due to lack of resources */
+ /* force DSR handler to ack the interrupt */
+ *pASyncProcessing = FALSE;
+ pDev->RecheckIRQStatusCnt = 0;
+ }
+ }
+
+ /* now handle the rest of them */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
+ host_int_status));
+
+ if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
+ /* CPU Interrupt */
+ status = DevServiceCPUInterrupt(pDev);
+ if (A_FAILED(status)){
+ break;
+ }
+ }
+
+ if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
+ /* Error Interrupt */
+ status = DevServiceErrorInterrupt(pDev);
+ if (A_FAILED(status)){
+ break;
+ }
+ }
+
+ if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
+ /* Counter Interrupt */
+ status = DevServiceCounterInterrupt(pDev);
+ if (A_FAILED(status)){
+ break;
+ }
+ }
+
+ } while (FALSE);
+
+ /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
+ * the target, if upper layers determine that we are in a low-throughput mode, we can
+ * rely on taking another interrupt rather than re-checking the status registers which can
+ * re-wake the target.
+ *
+ * NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
+ * be used due to possible side-effects. For example, SPI requires the host to drain all
+ * messages from the mailbox before exiting the ISR routine. */
+ if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n"));
+ *pDone = TRUE;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
+ *pDone, *pASyncProcessing, status));
+
+ return status;
+}
+
+
+/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
+A_STATUS DevDsrHandler(void *context)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
+ A_STATUS status = A_OK;
+ A_BOOL done = FALSE;
+ A_BOOL asyncProc = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ /* reset the recv counter that tracks when we need to yield from the DSR */
+ pDev->CurrentDSRRecvCount = 0;
+ /* reset counter used to flag a re-scan of IRQ status registers on the target */
+ pDev->RecheckIRQStatusCnt = 0;
+
+ while (!done) {
+ status = ProcessPendingIRQs(pDev, &done, &asyncProc);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+ /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
+ asyncProc = FALSE;
+ /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
+ * this has a nice side effect of blocking us until all async read requests are completed.
+ * This behavior is required on some HIF implementations that do not allow ASYNC
+ * processing in interrupt handlers (like Windows CE) */
+
+ if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) {
+ /* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
+ * checking for more messages and return */
+ break;
+ }
+ }
+
+ if (asyncProc) {
+ /* the function performed some async I/O for performance, we
+ need to exit the ISR immediately, the check below will prevent the interrupt from being
+ Ack'd while we handle it asynchronously */
+ break;
+ }
+
+ }
+
+ if (A_SUCCESS(status) && !asyncProc) {
+ /* Ack the interrupt only if :
+ * 1. we did not get any errors in processing interrupts
+ * 2. there are no outstanding async processing requests */
+ if (pDev->DSRCanYield) {
+ /* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
+ * The HIF layer must ACK the interrupt on behalf of HTC */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
+ HIFAckInterrupt(pDev->HIFDevice);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
+ return status;
+}
+
+void DumpAR6KDevState(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+ AR6K_IRQ_PROC_REGISTERS procRegs;
+
+ LOCK_AR6K(pDev);
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+ UNLOCK_AR6K(pDev);
+
+ /* load the register table from the device */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ (A_UINT8 *)&procRegs,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("DumpAR6KDevState : Failed to read register table (%d) \n",status));
+ return;
+ }
+
+ DevDumpRegisters(pDev,&procRegs,&regs);
+
+ if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
+ pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);
+ }
+
+ /* dump any bus state at the HIF layer */
+ HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
+
+}
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c
new file mode 100644
index 000000000000..f1408082a809
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c
@@ -0,0 +1,752 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_gmbox.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Generic MBOX API implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+#include "hw/mbox_host_reg.h"
+#include "gmboxif.h"
+
+/*
+ * This file provides management functions and a toolbox for GMBOX protocol modules.
+ * Only one protocol module can be installed at a time. The determination of which protocol
+ * module is installed is determined at compile time.
+ *
+ */
+#ifdef ATH_AR6K_ENABLE_GMBOX
+ /* GMBOX definitions */
+#define GMBOX_INT_STATUS_ENABLE_REG 0x488
+#define GMBOX_INT_STATUS_RX_DATA (1 << 0)
+#define GMBOX_INT_STATUS_TX_OVERFLOW (1 << 1)
+#define GMBOX_INT_STATUS_RX_OVERFLOW (1 << 2)
+
+#define GMBOX_LOOKAHEAD_MUX_REG 0x498
+#define GMBOX_LA_MUX_OVERRIDE_2_3 (1 << 0)
+
+#define AR6K_GMBOX_CREDIT_DEC_ADDRESS (COUNT_DEC_ADDRESS + 4 * AR6K_GMBOX_CREDIT_COUNTER)
+#define AR6K_GMBOX_CREDIT_SIZE_ADDRESS (COUNT_ADDRESS + AR6K_GMBOX_CREDIT_SIZE_COUNTER)
+
+
+ /* external APIs for allocating and freeing internal I/O packets to handle ASYNC I/O */
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+
+/* callback when our fetch to enable/disable completes */
+static void DevGMboxIRQActionAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxIRQActionAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("IRQAction Operation (%d) failed! status:%d \n", pPacket->PktInfo.AsRx.HTCRxFlags,pPacket->Status));
+ }
+ /* free this IO packet */
+ AR6KFreeIOPacket(pDev,pPacket);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxIRQActionAsyncHandler \n"));
+}
+
+static A_STATUS DevGMboxCounterEnableDisable(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
+{
+ A_STATUS status = A_OK;
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+ HTC_PACKET *pIOPacket = NULL;
+
+ LOCK_AR6K(pDev);
+
+ if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
+ pDev->GMboxInfo.CreditCountIRQEnabled = TRUE;
+ pDev->IrqEnableRegisters.counter_int_status_enable |=
+ COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER);
+ pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_COUNTER_SET(0x01);
+ } else {
+ pDev->GMboxInfo.CreditCountIRQEnabled = FALSE;
+ pDev->IrqEnableRegisters.counter_int_status_enable &=
+ ~(COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER));
+ }
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ UNLOCK_AR6K(pDev);
+
+ do {
+
+ if (AsyncMode) {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* copy values to write to our async I/O buffer */
+ A_MEMCPY(pIOPacket->pBuffer,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
+ pIOPacket->pContext = pDev;
+ pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
+ /* write it out asynchronously */
+ HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_ASYNC_BYTE_INC,
+ pIOPacket);
+
+ pIOPacket = NULL;
+ break;
+ }
+
+ /* if we get here we are doing it synchronously */
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));
+ } else {
+ if (!AsyncMode) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" IRQAction Operation (%d) success \n", IrqAction));
+ }
+ }
+
+ if (pIOPacket != NULL) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ return status;
+}
+
+
+A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+ A_UINT8 GMboxIntControl[4];
+
+ if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
+ return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_ENABLE, AsyncMode);
+ } else if(GMBOX_CREDIT_IRQ_DISABLE == IrqAction) {
+ return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
+ }
+
+ if (GMBOX_DISABLE_ALL == IrqAction) {
+ /* disable credit IRQ, those are on a different set of registers */
+ DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
+ }
+
+ /* take the lock to protect interrupt enable shadows */
+ LOCK_AR6K(pDev);
+
+ switch (IrqAction) {
+
+ case GMBOX_DISABLE_ALL:
+ pDev->GMboxControlRegisters.int_status_enable = 0;
+ break;
+ case GMBOX_ERRORS_IRQ_ENABLE:
+ pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_TX_OVERFLOW |
+ GMBOX_INT_STATUS_RX_OVERFLOW;
+ break;
+ case GMBOX_RECV_IRQ_ENABLE:
+ pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_RX_DATA;
+ break;
+ case GMBOX_RECV_IRQ_DISABLE:
+ pDev->GMboxControlRegisters.int_status_enable &= ~GMBOX_INT_STATUS_RX_DATA;
+ break;
+ case GMBOX_ACTION_NONE:
+ default:
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ GMboxIntControl[0] = pDev->GMboxControlRegisters.int_status_enable;
+ GMboxIntControl[1] = GMboxIntControl[0];
+ GMboxIntControl[2] = GMboxIntControl[0];
+ GMboxIntControl[3] = GMboxIntControl[0];
+
+ UNLOCK_AR6K(pDev);
+
+ do {
+
+ if (AsyncMode) {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* copy values to write to our async I/O buffer */
+ A_MEMCPY(pIOPacket->pBuffer,GMboxIntControl,sizeof(GMboxIntControl));
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
+ pIOPacket->pContext = pDev;
+ pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
+ /* write it out asynchronously */
+ HIFReadWrite(pDev->HIFDevice,
+ GMBOX_INT_STATUS_ENABLE_REG,
+ pIOPacket->pBuffer,
+ sizeof(GMboxIntControl),
+ HIF_WR_ASYNC_BYTE_FIX,
+ pIOPacket);
+ pIOPacket = NULL;
+ break;
+ }
+
+ /* if we get here we are doing it synchronously */
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ GMBOX_INT_STATUS_ENABLE_REG,
+ GMboxIntControl,
+ sizeof(GMboxIntControl),
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));
+ } else {
+ if (!AsyncMode) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" IRQAction Operation (%d) success \n", IrqAction));
+ }
+ }
+
+ if (pIOPacket != NULL) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ return status;
+}
+
+void DevCleanupGMbox(AR6K_DEVICE *pDev)
+{
+ if (pDev->GMboxEnabled) {
+ pDev->GMboxEnabled = FALSE;
+ GMboxProtocolUninstall(pDev);
+ }
+}
+
+A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 muxControl[4];
+
+ do {
+
+ if (0 == pDev->MailBoxInfo.GMboxAddress) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" GMBOX Advertised: Address:0x%X , size:%d \n",
+ pDev->MailBoxInfo.GMboxAddress, pDev->MailBoxInfo.GMboxSize));
+
+ status = DevGMboxIRQAction(pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* write to mailbox look ahead mux control register, we want the
+ * GMBOX lookaheads to appear on lookaheads 2 and 3
+ * the register is 1-byte wide so we need to hit it 4 times to align the operation
+ * to 4-bytes */
+ muxControl[0] = GMBOX_LA_MUX_OVERRIDE_2_3;
+ muxControl[1] = GMBOX_LA_MUX_OVERRIDE_2_3;
+ muxControl[2] = GMBOX_LA_MUX_OVERRIDE_2_3;
+ muxControl[3] = GMBOX_LA_MUX_OVERRIDE_2_3;
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ GMBOX_LOOKAHEAD_MUX_REG,
+ muxControl,
+ sizeof(muxControl),
+ HIF_WR_SYNC_BYTE_FIX, /* hit this register 4 times */
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ status = GMboxProtocolInstall(pDev);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ pDev->GMboxEnabled = TRUE;
+
+ } while (FALSE);
+
+ return status;
+}
+
+A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 counter_int_status;
+ int credits;
+ A_UINT8 host_int_status2;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("+DevCheckGMboxInterrupts \n"));
+
+ /* the caller guarantees that this is a context that allows for blocking I/O */
+
+ do {
+
+ host_int_status2 = pDev->IrqProcRegisters.host_int_status2 &
+ pDev->GMboxControlRegisters.int_status_enable;
+
+ if (host_int_status2 & GMBOX_INT_STATUS_TX_OVERFLOW) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : TX Overflow \n"));
+ status = A_ECOMM;
+ }
+
+ if (host_int_status2 & GMBOX_INT_STATUS_RX_OVERFLOW) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : RX Overflow \n"));
+ status = A_ECOMM;
+ }
+
+ if (A_FAILED(status)) {
+ if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
+ pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, status);
+ }
+ break;
+ }
+
+ if (host_int_status2 & GMBOX_INT_STATUS_RX_DATA) {
+ if (pDev->IrqProcRegisters.gmbox_rx_avail > 0) {
+ A_ASSERT(pDev->GMboxInfo.pMessagePendingCallBack != NULL);
+ status = pDev->GMboxInfo.pMessagePendingCallBack(
+ pDev->GMboxInfo.pProtocolContext,
+ (A_UINT8 *)&pDev->IrqProcRegisters.rx_gmbox_lookahead_alias[0],
+ pDev->IrqProcRegisters.gmbox_rx_avail);
+ }
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+ pDev->IrqEnableRegisters.counter_int_status_enable;
+
+ /* check if credit interrupt is pending */
+ if (counter_int_status & (COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER))) {
+
+ /* do synchronous read */
+ status = DevGMboxReadCreditCounter(pDev, PROC_IO_SYNC, &credits);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ A_ASSERT(pDev->GMboxInfo.pCreditsPendingCallback != NULL);
+ status = pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
+ credits,
+ pDev->GMboxInfo.CreditCountIRQEnabled);
+ }
+
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("-DevCheckGMboxInterrupts (%d) \n",status));
+
+ return status;
+}
+
+
+A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength)
+{
+ A_UINT32 paddedLength;
+ A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+ A_STATUS status;
+ A_UINT32 address;
+
+ /* adjust the length to be a multiple of block size if appropriate */
+ paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("DevGMboxWrite, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+ WriteLength,
+ pDev->MailBoxInfo.GMboxAddress,
+ sync ? "SYNC" : "ASYNC"));
+
+ /* last byte of packet has to hit the EOM marker */
+ address = pDev->MailBoxInfo.GMboxAddress + pDev->MailBoxInfo.GMboxSize - paddedLength;
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ address,
+ pPacket->pBuffer,
+ paddedLength, /* the padded length */
+ sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+ sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
+
+ if (sync) {
+ pPacket->Status = status;
+ } else {
+ if (status == A_PENDING) {
+ status = A_OK;
+ }
+ }
+
+ return status;
+}
+
+A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength)
+{
+
+ A_UINT32 paddedLength;
+ A_STATUS status;
+ A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+ /* adjust the length to be a multiple of block size if appropriate */
+ paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, ReadLength);
+
+ if (paddedLength > pPacket->BufferLength) {
+ A_ASSERT(FALSE);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("DevGMboxRead, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+ paddedLength,ReadLength,pPacket->BufferLength));
+ if (pPacket->Completion != NULL) {
+ COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+ return A_OK;
+ }
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("DevGMboxRead (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
+ (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
+ paddedLength,
+ pDev->MailBoxInfo.GMboxAddress,
+ sync ? "SYNC" : "ASYNC"));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ pDev->MailBoxInfo.GMboxAddress,
+ pPacket->pBuffer,
+ paddedLength,
+ sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
+ sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
+
+ if (sync) {
+ pPacket->Status = status;
+ }
+
+ return status;
+}
+
+
+static int ProcessCreditCounterReadBuffer(A_UINT8 *pBuffer, int Length)
+{
+ int credits = 0;
+
+ /* theory of how this works:
+ * We read the credit decrement register multiple times on a byte-wide basis.
+ * The number of times (32) aligns the I/O operation to be a multiple of 4 bytes and provides a
+ * reasonable chance to acquire "all" pending credits in a single I/O operation.
+ *
+ * Once we obtain the filled buffer, we can walk through it looking for credit decrement transitions.
+ * Each non-zero byte represents a single credit decrement (which is a credit given back to the host)
+ * For example if the target provides 3 credits and added 4 more during the 32-byte read operation the following
+ * pattern "could" appear:
+ *
+ * 0x3 0x2 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 ......rest zeros
+ * <---------> <----------------------------->
+ * \_ credits aleady there \_ target adding 4 more credits
+ *
+ * The total available credits would be 7, since there are 7 non-zero bytes in the buffer.
+ *
+ * */
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ DebugDumpBytes(pBuffer, Length, "GMBOX Credit read buffer");
+ }
+
+ while (Length) {
+ if (*pBuffer != 0) {
+ credits++;
+ }
+ Length--;
+ pBuffer++;
+ }
+
+ return credits;
+}
+
+
+/* callback when our fetch to enable/disable completes */
+static void DevGMboxReadCreditsAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxReadCreditsAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Read Credit Operation failed! status:%d \n", pPacket->Status));
+ } else {
+ int credits = 0;
+ credits = ProcessCreditCounterReadBuffer(pPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
+ pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
+ credits,
+ pDev->GMboxInfo.CreditCountIRQEnabled);
+
+
+ }
+ /* free this IO packet */
+ AR6KFreeIOPacket(pDev,pPacket);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxReadCreditsAsyncHandler \n"));
+}
+
+A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+DevGMboxReadCreditCounter (%s) \n", AsyncMode ? "ASYNC" : "SYNC"));
+
+ do {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ A_MEMZERO(pIOPacket->pBuffer,AR6K_REG_IO_BUFFER_SIZE);
+
+ if (AsyncMode) {
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevGMboxReadCreditsAsyncHandler;
+ pIOPacket->pContext = pDev;
+ /* read registers asynchronously */
+ HIFReadWrite(pDev->HIFDevice,
+ AR6K_GMBOX_CREDIT_DEC_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_REG_IO_BUFFER_SIZE, /* hit the register multiple times */
+ HIF_RD_ASYNC_BYTE_FIX,
+ pIOPacket);
+ pIOPacket = NULL;
+ break;
+ }
+
+ pIOPacket->Completion = NULL;
+ /* if we get here we are doing it synchronously */
+ status = HIFReadWrite(pDev->HIFDevice,
+ AR6K_GMBOX_CREDIT_DEC_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_REG_IO_BUFFER_SIZE,
+ HIF_RD_SYNC_BYTE_FIX,
+ NULL);
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" DevGMboxReadCreditCounter failed! status:%d \n", status));
+ }
+
+ if (pIOPacket != NULL) {
+ if (A_SUCCESS(status)) {
+ /* sync mode processing */
+ *pCredits = ProcessCreditCounterReadBuffer(pIOPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
+ }
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-DevGMboxReadCreditCounter (%s) (%d) \n",
+ AsyncMode ? "ASYNC" : "SYNC", status));
+
+ return status;
+}
+
+A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize)
+{
+ A_STATUS status;
+ A_UINT8 buffer[4];
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ AR6K_GMBOX_CREDIT_SIZE_ADDRESS,
+ buffer,
+ sizeof(buffer),
+ HIF_RD_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
+ NULL);
+
+ if (A_SUCCESS(status)) {
+ if (buffer[0] == 0) {
+ *pCreditSize = 256;
+ } else {
+ *pCreditSize = buffer[0];
+ }
+
+ }
+
+ return status;
+}
+
+void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev)
+{
+ /* Target ASSERTED!!! */
+ if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
+ pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, A_HARDWARE);
+ }
+}
+
+A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes)
+{
+
+ A_STATUS status = A_OK;
+ AR6K_IRQ_PROC_REGISTERS procRegs;
+ int maxCopy;
+
+ do {
+ /* on entry the caller provides the length of the lookahead buffer */
+ if (*pLookAheadBytes > sizeof(procRegs.rx_gmbox_lookahead_alias)) {
+ A_ASSERT(FALSE);
+ status = A_EINVAL;
+ break;
+ }
+
+ maxCopy = *pLookAheadBytes;
+ *pLookAheadBytes = 0;
+ /* load the register table from the device */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ (A_UINT8 *)&procRegs,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("DevGMboxRecvLookAheadPeek : Failed to read register table (%d) \n",status));
+ break;
+ }
+
+ if (procRegs.gmbox_rx_avail > 0) {
+ int bytes = procRegs.gmbox_rx_avail > maxCopy ? maxCopy : procRegs.gmbox_rx_avail;
+ A_MEMCPY(pLookAheadBuffer,&procRegs.rx_gmbox_lookahead_alias[0],bytes);
+ *pLookAheadBytes = bytes;
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int Signal, int AckTimeoutMS)
+{
+ A_STATUS status = A_OK;
+ int i;
+ A_UINT8 buffer[4];
+
+ A_MEMZERO(buffer, sizeof(buffer));
+
+ do {
+
+ if (Signal >= MBOX_SIG_HCI_BRIDGE_MAX) {
+ status = A_EINVAL;
+ break;
+ }
+
+ /* set the last buffer to do the actual signal trigger */
+ buffer[3] = (1 << Signal);
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_WLAN_ADDRESS,
+ buffer,
+ sizeof(buffer),
+ HIF_WR_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ } while (FALSE);
+
+
+ if (A_SUCCESS(status)) {
+ /* now read back the register to see if the bit cleared */
+ while (AckTimeoutMS) {
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_WLAN_ADDRESS,
+ buffer,
+ sizeof(buffer),
+ HIF_RD_SYNC_BYTE_FIX,
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ for (i = 0; i < sizeof(buffer); i++) {
+ if (buffer[i] & (1 << Signal)) {
+ /* bit is still set */
+ break;
+ }
+ }
+
+ if (i >= sizeof(buffer)) {
+ /* done */
+ break;
+ }
+
+ AckTimeoutMS--;
+ A_MDELAY(1);
+ }
+
+ if (0 == AckTimeoutMS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("DevGMboxSetTargetInterrupt : Ack Timed-out (sig:%d) \n",Signal));
+ status = A_ERROR;
+ }
+ }
+
+ return status;
+
+}
+
+#endif //ATH_AR6K_ENABLE_GMBOX
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
new file mode 100644
index 000000000000..ec5c1dc18ed2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
@@ -0,0 +1,1255 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6k_prot_hciUart.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Protocol module for use in bridging HCI-UART packets over the GMBOX interface
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "../htc_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+#include "hci_transport_api.h"
+#include "gmboxif.h"
+#include "ar6000_diag.h"
+#include "hw/apb_map.h"
+#include "hw/mbox_reg.h"
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+#define HCI_UART_COMMAND_PKT 0x01
+#define HCI_UART_ACL_PKT 0x02
+#define HCI_UART_SCO_PKT 0x03
+#define HCI_UART_EVENT_PKT 0x04
+
+#define HCI_RECV_WAIT_BUFFERS (1 << 0)
+
+#define HCI_SEND_WAIT_CREDITS (1 << 0)
+
+#define HCI_UART_BRIDGE_CREDIT_SIZE 128
+
+#define CREDIT_POLL_COUNT 256
+
+#define HCI_DELAY_PER_INTERVAL_MS 10
+#define BTON_TIMEOUT_MS 500
+#define BTOFF_TIMEOUT_MS 500
+#define BAUD_TIMEOUT_MS 1
+
+typedef struct {
+ HCI_TRANSPORT_CONFIG_INFO HCIConfig;
+ A_BOOL HCIAttached;
+ A_BOOL HCIStopped;
+ A_UINT32 RecvStateFlags;
+ A_UINT32 SendStateFlags;
+ HCI_TRANSPORT_PACKET_TYPE WaitBufferType;
+ HTC_PACKET_QUEUE SendQueue; /* write queue holding HCI Command and ACL packets */
+ HTC_PACKET_QUEUE HCIACLRecvBuffers; /* recv queue holding buffers for incomming ACL packets */
+ HTC_PACKET_QUEUE HCIEventBuffers; /* recv queue holding buffers for incomming event packets */
+ AR6K_DEVICE *pDev;
+ A_MUTEX_T HCIRxLock;
+ A_MUTEX_T HCITxLock;
+ int CreditsMax;
+ int CreditsConsumed;
+ int CreditsAvailable;
+ int CreditSize;
+ int CreditsCurrentSeek;
+ int SendProcessCount;
+} GMBOX_PROTO_HCI_UART;
+
+#define LOCK_HCI_RX(t) A_MUTEX_LOCK(&(t)->HCIRxLock);
+#define UNLOCK_HCI_RX(t) A_MUTEX_UNLOCK(&(t)->HCIRxLock);
+#define LOCK_HCI_TX(t) A_MUTEX_LOCK(&(t)->HCITxLock);
+#define UNLOCK_HCI_TX(t) A_MUTEX_UNLOCK(&(t)->HCITxLock);
+
+#define DO_HCI_RECV_INDICATION(p,pt) \
+{ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI: Indicate Recv on packet:0x%X status:%d len:%d type:%d \n", \
+ (A_UINT32)(pt),(pt)->Status, A_SUCCESS((pt)->Status) ? (pt)->ActualLength : 0, HCI_GET_PACKET_TYPE(pt))); \
+ (p)->HCIConfig.pHCIPktRecv((p)->HCIConfig.pContext, (pt)); \
+}
+
+#define DO_HCI_SEND_INDICATION(p,pt) \
+{ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Indicate Send on packet:0x%X status:%d type:%d \n", \
+ (A_UINT32)(pt),(pt)->Status,HCI_GET_PACKET_TYPE(pt))); \
+ (p)->HCIConfig.pHCISendComplete((p)->HCIConfig.pContext, (pt)); \
+}
+
+static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous);
+
+static void HCIUartCleanup(GMBOX_PROTO_HCI_UART *pProtocol)
+{
+ A_ASSERT(pProtocol != NULL);
+
+ A_MUTEX_DELETE(&pProtocol->HCIRxLock);
+ A_MUTEX_DELETE(&pProtocol->HCITxLock);
+
+ A_FREE(pProtocol);
+}
+
+static A_STATUS InitTxCreditState(GMBOX_PROTO_HCI_UART *pProt)
+{
+ A_STATUS status;
+ int credits;
+ int creditPollCount = CREDIT_POLL_COUNT;
+ A_BOOL gotCredits = FALSE;
+
+ pProt->CreditsConsumed = 0;
+
+ do {
+
+ if (pProt->CreditsMax != 0) {
+ /* we can only call this only once per target reset */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI: InitTxCreditState - already called! \n"));
+ A_ASSERT(FALSE);
+ status = A_EINVAL;
+ break;
+ }
+
+ /* read the credit counter. At startup the target will set the credit counter
+ * to the max available, we read this in a loop because it may take
+ * multiple credit counter reads to get all credits */
+
+ while (creditPollCount) {
+
+ credits = 0;
+
+ status = DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (!gotCredits && (0 == credits)) {
+ creditPollCount--;
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: credit is 0, retrying (%d) \n",creditPollCount));
+ A_MDELAY(HCI_DELAY_PER_INTERVAL_MS);
+ continue;
+ } else {
+ gotCredits = TRUE;
+ }
+
+ if (0 == credits) {
+ break;
+ }
+
+ pProt->CreditsMax += credits;
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (0 == creditPollCount) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("** HCI : Failed to get credits! GMBOX Target was not available \n"));
+ status = A_ERROR;
+ break;
+ }
+
+ /* now get the size */
+ status = DevGMboxReadCreditSize(pProt->pDev, &pProt->CreditSize);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ } while (FALSE);
+
+ if (A_SUCCESS(status)) {
+ pProt->CreditsAvailable = pProt->CreditsMax;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI : InitTxCreditState - credits avail: %d, size: %d \n",
+ pProt->CreditsAvailable, pProt->CreditSize));
+ }
+
+ return status;
+}
+
+static A_STATUS CreditsAvailableCallback(void *pContext, int Credits, A_BOOL CreditIRQEnabled)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+ A_BOOL enableCreditIrq = FALSE;
+ A_BOOL disableCreditIrq = FALSE;
+ A_BOOL doPendingSends = FALSE;
+ A_STATUS status = A_OK;
+
+ /** this callback is called under 2 conditions:
+ * 1. The credit IRQ interrupt was enabled and signaled.
+ * 2. A credit counter read completed.
+ *
+ * The function must not assume that the calling context can block !
+ */
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback (Credits:%d, IRQ:%s) \n",
+ Credits, CreditIRQEnabled ? "ON" : "OFF"));
+
+ LOCK_HCI_RX(pProt);
+
+ do {
+
+ if (0 == Credits) {
+ if (!CreditIRQEnabled) {
+ /* enable credit IRQ */
+ enableCreditIrq = TRUE;
+ }
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: current credit state, consumed:%d available:%d max:%d seek:%d\n",
+ pProt->CreditsConsumed,
+ pProt->CreditsAvailable,
+ pProt->CreditsMax,
+ pProt->CreditsCurrentSeek));
+
+ pProt->CreditsAvailable += Credits;
+ A_ASSERT(pProt->CreditsAvailable <= pProt->CreditsMax);
+ pProt->CreditsConsumed -= Credits;
+ A_ASSERT(pProt->CreditsConsumed >= 0);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state, consumed:%d available:%d max:%d seek:%d\n",
+ pProt->CreditsConsumed,
+ pProt->CreditsAvailable,
+ pProt->CreditsMax,
+ pProt->CreditsCurrentSeek));
+
+ if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) {
+ /* we have enough credits to fullfill at least 1 packet waiting in the queue */
+ pProt->CreditsCurrentSeek = 0;
+ pProt->SendStateFlags &= ~HCI_SEND_WAIT_CREDITS;
+ doPendingSends = TRUE;
+ if (CreditIRQEnabled) {
+ /* credit IRQ was enabled, we shouldn't need it anymore */
+ disableCreditIrq = TRUE;
+ }
+ } else {
+ /* not enough credits yet, enable credit IRQ if we haven't already */
+ if (!CreditIRQEnabled) {
+ enableCreditIrq = TRUE;
+ }
+ }
+
+ } while (FALSE);
+
+ UNLOCK_HCI_RX(pProt);
+
+ if (enableCreditIrq) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Enabling credit count IRQ...\n"));
+ /* must use async only */
+ status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_ENABLE, PROC_IO_ASYNC);
+ } else if (disableCreditIrq) {
+ /* must use async only */
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Disabling credit count IRQ...\n"));
+ status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_DISABLE, PROC_IO_ASYNC);
+ }
+
+ if (doPendingSends) {
+ HCITrySend(pProt, NULL, FALSE);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback \n"));
+ return status;
+}
+
+static INLINE void NotifyTransportFailure(GMBOX_PROTO_HCI_UART *pProt, A_STATUS status)
+{
+ if (pProt->HCIConfig.TransportFailure != NULL) {
+ pProt->HCIConfig.TransportFailure(pProt->HCIConfig.pContext, status);
+ }
+}
+
+static void FailureCallback(void *pContext, A_STATUS Status)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+
+ /* target assertion occured */
+ NotifyTransportFailure(pProt, Status);
+}
+
+static void StateDumpCallback(void *pContext)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("============ HCIUart State ======================\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("RecvStateFlags : 0x%X \n",pProt->RecvStateFlags));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendStateFlags : 0x%X \n",pProt->SendStateFlags));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("WaitBufferType : %d \n",pProt->WaitBufferType));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendQueue Depth : %d \n",HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue)));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsMax : %d \n",pProt->CreditsMax));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsConsumed : %d \n",pProt->CreditsConsumed));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsAvailable : %d \n",pProt->CreditsAvailable));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("==================================================\n"));
+}
+
+static A_STATUS HCIUartMessagePending(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext;
+ A_STATUS status = A_OK;
+ int totalRecvLength = 0;
+ HCI_TRANSPORT_PACKET_TYPE pktType = HCI_PACKET_INVALID;
+ A_BOOL recvRefillCalled = FALSE;
+ A_BOOL blockRecv = FALSE;
+ HTC_PACKET *pPacket = NULL;
+
+ /** caller guarantees that this is a fully block-able context (synch I/O is allowed) */
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCIUartMessagePending Lookahead Bytes:%d \n",ValidBytes));
+
+ LOCK_HCI_RX(pProt);
+
+ do {
+
+ if (ValidBytes < 3) {
+ /* not enough for ACL or event header */
+ break;
+ }
+
+ if ((LookAheadBytes[0] == HCI_UART_ACL_PKT) && (ValidBytes < 5)) {
+ /* not enough for ACL data header */
+ break;
+ }
+
+ switch (LookAheadBytes[0]) {
+ case HCI_UART_EVENT_PKT:
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n",
+ LookAheadBytes[1], LookAheadBytes[2]));
+ totalRecvLength = LookAheadBytes[2];
+ totalRecvLength += 3; /* add type + event code + length field */
+ pktType = HCI_EVENT_TYPE;
+ break;
+ case HCI_UART_ACL_PKT:
+ totalRecvLength = (LookAheadBytes[4] << 8) | LookAheadBytes[3];
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI ACL: conn:0x%X length: %d \n",
+ ((LookAheadBytes[2] & 0xF0) << 8) | LookAheadBytes[1], totalRecvLength));
+ totalRecvLength += 5; /* add type + connection handle + length field */
+ pktType = HCI_ACL_TYPE;
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",LookAheadBytes[0]));
+ status = A_EPROTO;
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (pProt->HCIConfig.pHCIPktRecvAlloc != NULL) {
+ UNLOCK_HCI_RX(pProt);
+ /* user is using a per-packet allocation callback */
+ pPacket = pProt->HCIConfig.pHCIPktRecvAlloc(pProt->HCIConfig.pContext,
+ pktType,
+ totalRecvLength);
+ LOCK_HCI_RX(pProt);
+
+ } else {
+ HTC_PACKET_QUEUE *pQueue;
+ /* user is using a refill handler that can refill multiple HTC buffers */
+
+ /* select buffer queue */
+ if (pktType == HCI_ACL_TYPE) {
+ pQueue = &pProt->HCIACLRecvBuffers;
+ } else {
+ pQueue = &pProt->HCIEventBuffers;
+ }
+
+ if (HTC_QUEUE_EMPTY(pQueue)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("** HCI pkt type: %d has no buffers available calling allocation handler \n",
+ pktType));
+ /* check for refill handler */
+ if (pProt->HCIConfig.pHCIPktRecvRefill != NULL) {
+ recvRefillCalled = TRUE;
+ UNLOCK_HCI_RX(pProt);
+ /* call the re-fill handler */
+ pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext,
+ pktType,
+ 0);
+ LOCK_HCI_RX(pProt);
+ /* check if we have more buffers */
+ pPacket = HTC_PACKET_DEQUEUE(pQueue);
+ /* fall through */
+ }
+ } else {
+ pPacket = HTC_PACKET_DEQUEUE(pQueue);
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HCI pkt type: %d now has %d recv buffers left \n",
+ pktType, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+ }
+ }
+
+ if (NULL == pPacket) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("** HCI pkt type: %d has no buffers available stopping recv...\n", pktType));
+ /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+ pProt->RecvStateFlags |= HCI_RECV_WAIT_BUFFERS;
+ pProt->WaitBufferType = pktType;
+ blockRecv = TRUE;
+ break;
+ }
+
+ if (totalRecvLength > (int)pPacket->BufferLength) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI-UART pkt: %d requires %d bytes (%d buffer bytes avail) ! \n",
+ LookAheadBytes[0], totalRecvLength, pPacket->BufferLength));
+ status = A_EINVAL;
+ break;
+ }
+
+ } while (FALSE);
+
+ UNLOCK_HCI_RX(pProt);
+
+ /* locks are released, we can go fetch the packet */
+
+ do {
+
+ if (A_FAILED(status) || (NULL == pPacket)) {
+ break;
+ }
+
+ /* do this synchronously, we don't need to be fast here */
+ pPacket->Completion = NULL;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI : getting recv packet len:%d hci-uart-type: %s \n",
+ totalRecvLength, (LookAheadBytes[0] == HCI_UART_EVENT_PKT) ? "EVENT" : "ACL"));
+
+ status = DevGMboxRead(pProt->pDev, pPacket, totalRecvLength);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (pPacket->pBuffer[0] != LookAheadBytes[0]) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not contain expected packet type: %d ! \n",
+ pPacket->pBuffer[0]));
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pPacket->pBuffer[0] == HCI_UART_EVENT_PKT) {
+ /* validate event header fields */
+ if ((pPacket->pBuffer[1] != LookAheadBytes[1]) ||
+ (pPacket->pBuffer[2] != LookAheadBytes[2])) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n"));
+ DebugDumpBytes(LookAheadBytes, 3, "Expected HCI-UART Header");
+ DebugDumpBytes(pPacket->pBuffer, 3, "** Bad HCI-UART Header");
+ status = A_EPROTO;
+ break;
+ }
+ } else if (pPacket->pBuffer[0] == HCI_UART_ACL_PKT) {
+ /* validate acl header fields */
+ if ((pPacket->pBuffer[1] != LookAheadBytes[1]) ||
+ (pPacket->pBuffer[2] != LookAheadBytes[2]) ||
+ (pPacket->pBuffer[3] != LookAheadBytes[3]) ||
+ (pPacket->pBuffer[4] != LookAheadBytes[4])) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n"));
+ DebugDumpBytes(LookAheadBytes, 5, "Expected HCI-UART Header");
+ DebugDumpBytes(pPacket->pBuffer, 5, "** Bad HCI-UART Header");
+ status = A_EPROTO;
+ break;
+ }
+ }
+
+ /* adjust buffer to move past packet ID */
+ pPacket->pBuffer++;
+ pPacket->ActualLength = totalRecvLength - 1;
+ pPacket->Status = A_OK;
+ /* indicate packet */
+ DO_HCI_RECV_INDICATION(pProt,pPacket);
+ pPacket = NULL;
+
+ /* check if we need to refill recv buffers */
+ if ((pProt->HCIConfig.pHCIPktRecvRefill != NULL) && !recvRefillCalled) {
+ HTC_PACKET_QUEUE *pQueue;
+ int watermark;
+
+ if (pktType == HCI_ACL_TYPE) {
+ watermark = pProt->HCIConfig.ACLRecvBufferWaterMark;
+ pQueue = &pProt->HCIACLRecvBuffers;
+ } else {
+ watermark = pProt->HCIConfig.EventRecvBufferWaterMark;
+ pQueue = &pProt->HCIEventBuffers;
+ }
+
+ if (HTC_PACKET_QUEUE_DEPTH(pQueue) < watermark) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("** HCI pkt type: %d watermark hit (%d) current:%d \n",
+ pktType, watermark, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+ /* call the re-fill handler */
+ pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext,
+ pktType,
+ HTC_PACKET_QUEUE_DEPTH(pQueue));
+ }
+ }
+
+ } while (FALSE);
+
+ /* check if we need to disable the reciever */
+ if (A_FAILED(status) || blockRecv) {
+ DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_DISABLE, PROC_IO_SYNC);
+ }
+
+ /* see if we need to recycle the recv buffer */
+ if (A_FAILED(status) && (pPacket != NULL)) {
+ HTC_PACKET_QUEUE queue;
+
+ if (A_EPROTO == status) {
+ DebugDumpBytes(pPacket->pBuffer, totalRecvLength, "Bad HCI-UART Recv packet");
+ }
+ /* recycle packet */
+ HTC_PACKET_RESET_RX(pPacket);
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket);
+ HCI_TransportAddReceivePkts(pProt,&queue);
+ NotifyTransportFailure(pProt,status);
+ }
+
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCIUartMessagePending \n"));
+
+ return status;
+}
+
+static void HCISendPacketCompletion(void *Context, HTC_PACKET *pPacket)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)Context;
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion (pPacket:0x%X) \n",(A_UINT32)pPacket));
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Send Packet (0x%X) failed: %d , len:%d \n",
+ (A_UINT32)pPacket, pPacket->Status, pPacket->ActualLength));
+ }
+
+ DO_HCI_SEND_INDICATION(pProt,pPacket);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion \n"));
+}
+
+static A_STATUS SeekCreditsSynch(GMBOX_PROTO_HCI_UART *pProt)
+{
+ A_STATUS status = A_OK;
+ int credits;
+ int retry = 100;
+
+ while (TRUE) {
+ credits = 0;
+ status = DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits);
+ if (A_FAILED(status)) {
+ break;
+ }
+ LOCK_HCI_TX(pProt);
+ pProt->CreditsAvailable += credits;
+ pProt->CreditsConsumed -= credits;
+ if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) {
+ pProt->CreditsCurrentSeek = 0;
+ UNLOCK_HCI_TX(pProt);
+ break;
+ }
+ UNLOCK_HCI_TX(pProt);
+ retry--;
+ if (0 == retry) {
+ status = A_EBUSY;
+ break;
+ }
+ A_MDELAY(20);
+ }
+
+ return status;
+}
+
+static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous)
+{
+ A_STATUS status = A_OK;
+ int transferLength;
+ int creditsRequired, remainder;
+ A_UINT8 hciUartType;
+ A_BOOL synchSendComplete = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCITrySend (pPacket:0x%X) %s \n",(A_UINT32)pPacket,
+ Synchronous ? "SYNC" :"ASYNC"));
+
+ LOCK_HCI_TX(pProt);
+
+ /* increment write processing count on entry */
+ pProt->SendProcessCount++;
+
+ do {
+
+ if (pProt->HCIStopped) {
+ status = A_ECANCELED;
+ break;
+ }
+
+ if (pPacket != NULL) {
+ /* packet was supplied */
+ if (Synchronous) {
+ /* in synchronous mode, the send queue can only hold 1 packet */
+ if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+ status = A_EBUSY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ if (pProt->SendProcessCount > 1) {
+ /* another thread or task is draining the TX queues */
+ status = A_EBUSY;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket);
+
+ } else {
+ /* see if adding this packet hits the max depth (asynchronous mode only) */
+ if ((pProt->HCIConfig.MaxSendQueueDepth > 0) &&
+ ((HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue) + 1) >= pProt->HCIConfig.MaxSendQueueDepth)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("HCI Send queue is full, Depth:%d, Max:%d \n",
+ HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue),
+ pProt->HCIConfig.MaxSendQueueDepth));
+ /* queue will be full, invoke any callbacks to determine what action to take */
+ if (pProt->HCIConfig.pHCISendFull != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("HCI : Calling driver's send full callback.... \n"));
+ if (pProt->HCIConfig.pHCISendFull(pProt->HCIConfig.pContext,
+ pPacket) == HCI_SEND_FULL_DROP) {
+ /* drop it */
+ status = A_NO_RESOURCE;
+ break;
+ }
+ }
+ }
+
+ HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket);
+ }
+
+ }
+
+ if (pProt->SendStateFlags & HCI_SEND_WAIT_CREDITS) {
+ break;
+ }
+
+ if (pProt->SendProcessCount > 1) {
+ /* another thread or task is draining the TX queues */
+ break;
+ }
+
+ /***** beyond this point only 1 thread may enter ******/
+
+ /* now drain the send queue for transmission as long as we have enough
+ * credits */
+ while (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+
+ pPacket = HTC_PACKET_DEQUEUE(&pProt->SendQueue);
+
+ switch (HCI_GET_PACKET_TYPE(pPacket)) {
+ case HCI_COMMAND_TYPE:
+ hciUartType = HCI_UART_COMMAND_PKT;
+ break;
+ case HCI_ACL_TYPE:
+ hciUartType = HCI_UART_ACL_PKT;
+ break;
+ default:
+ status = A_EINVAL;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Got head packet:0x%X , Type:%d Length: %d Remaining Queue Depth: %d\n",
+ (A_UINT32)pPacket, HCI_GET_PACKET_TYPE(pPacket), pPacket->ActualLength,
+ HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue)));
+
+ transferLength = 1; /* UART type header is 1 byte */
+ transferLength += pPacket->ActualLength;
+ transferLength = DEV_CALC_SEND_PADDED_LEN(pProt->pDev, transferLength);
+
+ /* figure out how many credits this message requires */
+ creditsRequired = transferLength / pProt->CreditSize;
+ remainder = transferLength % pProt->CreditSize;
+
+ if (remainder) {
+ creditsRequired++;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Creds Required:%d Got:%d\n",
+ creditsRequired, pProt->CreditsAvailable));
+
+ if (creditsRequired > pProt->CreditsAvailable) {
+ if (Synchronous) {
+ /* in synchronous mode we need to seek credits in synchronously */
+ pProt->CreditsCurrentSeek = creditsRequired;
+ UNLOCK_HCI_TX(pProt);
+ status = SeekCreditsSynch(pProt);
+ LOCK_HCI_TX(pProt);
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* fall through and continue processing this send op */
+ } else {
+ /* not enough credits, queue back to the head */
+ HTC_PACKET_ENQUEUE_TO_HEAD(&pProt->SendQueue,pPacket);
+ /* waiting for credits */
+ pProt->SendStateFlags |= HCI_SEND_WAIT_CREDITS;
+ /* provide a hint to reduce attempts to re-send if credits are dribbling back
+ * this hint is the short fall of credits */
+ pProt->CreditsCurrentSeek = creditsRequired;
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: packet:0x%X placed back in queue. head packet needs: %d credits \n",
+ (A_UINT32)pPacket, pProt->CreditsCurrentSeek));
+ pPacket = NULL;
+ UNLOCK_HCI_TX(pProt);
+
+ /* schedule a credit counter read, our CreditsAvailableCallback callback will be called
+ * with the result */
+ DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_ASYNC, NULL);
+
+ LOCK_HCI_TX(pProt);
+ break;
+ }
+ }
+
+ /* caller guarantees some head room */
+ pPacket->pBuffer--;
+ pPacket->pBuffer[0] = hciUartType;
+
+ pProt->CreditsAvailable -= creditsRequired;
+ pProt->CreditsConsumed += creditsRequired;
+ A_ASSERT(pProt->CreditsConsumed <= pProt->CreditsMax);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state: consumed:%d available:%d max:%d\n",
+ pProt->CreditsConsumed, pProt->CreditsAvailable, pProt->CreditsMax));
+
+ UNLOCK_HCI_TX(pProt);
+
+ /* write it out */
+ if (Synchronous) {
+ pPacket->Completion = NULL;
+ pPacket->pContext = NULL;
+ } else {
+ pPacket->Completion = HCISendPacketCompletion;
+ pPacket->pContext = pProt;
+ }
+
+ status = DevGMboxWrite(pProt->pDev,pPacket,transferLength);
+ if (Synchronous) {
+ synchSendComplete = TRUE;
+ } else {
+ pPacket = NULL;
+ }
+
+ LOCK_HCI_TX(pProt);
+
+ }
+
+ } while (FALSE);
+
+ pProt->SendProcessCount--;
+ A_ASSERT(pProt->SendProcessCount >= 0);
+ UNLOCK_HCI_TX(pProt);
+
+ if (Synchronous) {
+ A_ASSERT(pPacket != NULL);
+ if (A_SUCCESS(status) && (!synchSendComplete)) {
+ status = A_EBUSY;
+ A_ASSERT(FALSE);
+ LOCK_HCI_TX(pProt);
+ if (pPacket->ListLink.pNext != NULL) {
+ /* remove from the queue */
+ HTC_PACKET_REMOVE(&pProt->SendQueue,pPacket);
+ }
+ UNLOCK_HCI_TX(pProt);
+ }
+ } else {
+ if (A_FAILED(status) && (pPacket != NULL)) {
+ pPacket->Status = status;
+ DO_HCI_SEND_INDICATION(pProt,pPacket);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HCITrySend: \n"));
+ return status;
+}
+
+static void FlushSendQueue(GMBOX_PROTO_HCI_UART *pProt)
+{
+ HTC_PACKET *pPacket;
+ HTC_PACKET_QUEUE discardQueue;
+
+ INIT_HTC_PACKET_QUEUE(&discardQueue);
+
+ LOCK_HCI_TX(pProt);
+
+ if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) {
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->SendQueue);
+ }
+
+ UNLOCK_HCI_TX(pProt);
+
+ /* discard packets */
+ while (!HTC_QUEUE_EMPTY(&discardQueue)) {
+ pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
+ pPacket->Status = A_ECANCELED;
+ DO_HCI_SEND_INDICATION(pProt,pPacket);
+ }
+
+}
+
+static void FlushRecvBuffers(GMBOX_PROTO_HCI_UART *pProt)
+{
+ HTC_PACKET_QUEUE discardQueue;
+ HTC_PACKET *pPacket;
+
+ INIT_HTC_PACKET_QUEUE(&discardQueue);
+
+ LOCK_HCI_RX(pProt);
+ /*transfer list items from ACL and event buffer queues to the discard queue */
+ if (!HTC_QUEUE_EMPTY(&pProt->HCIACLRecvBuffers)) {
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIACLRecvBuffers);
+ }
+ if (!HTC_QUEUE_EMPTY(&pProt->HCIEventBuffers)) {
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIEventBuffers);
+ }
+ UNLOCK_HCI_RX(pProt);
+
+ /* now empty the discard queue */
+ while (!HTC_QUEUE_EMPTY(&discardQueue)) {
+ pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
+ pPacket->Status = A_ECANCELED;
+ DO_HCI_RECV_INDICATION(pProt,pPacket);
+ }
+
+}
+
+/*** protocol module install entry point ***/
+
+A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev)
+{
+ A_STATUS status = A_OK;
+ GMBOX_PROTO_HCI_UART *pProtocol = NULL;
+
+ do {
+
+ pProtocol = A_MALLOC(sizeof(GMBOX_PROTO_HCI_UART));
+
+ if (NULL == pProtocol) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ A_MEMZERO(pProtocol, sizeof(*pProtocol));
+ pProtocol->pDev = pDev;
+ INIT_HTC_PACKET_QUEUE(&pProtocol->SendQueue);
+ INIT_HTC_PACKET_QUEUE(&pProtocol->HCIACLRecvBuffers);
+ INIT_HTC_PACKET_QUEUE(&pProtocol->HCIEventBuffers);
+ A_MUTEX_INIT(&pProtocol->HCIRxLock);
+ A_MUTEX_INIT(&pProtocol->HCITxLock);
+
+ } while (FALSE);
+
+ if (A_SUCCESS(status)) {
+ LOCK_AR6K(pDev);
+ DEV_GMBOX_SET_PROTOCOL(pDev,
+ HCIUartMessagePending,
+ CreditsAvailableCallback,
+ FailureCallback,
+ StateDumpCallback,
+ pProtocol);
+ UNLOCK_AR6K(pDev);
+ } else {
+ if (pProtocol != NULL) {
+ HCIUartCleanup(pProtocol);
+ }
+ }
+
+ return status;
+}
+
+/*** protocol module uninstall entry point ***/
+void GMboxProtocolUninstall(AR6K_DEVICE *pDev)
+{
+ GMBOX_PROTO_HCI_UART *pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev);
+
+ if (pProtocol != NULL) {
+
+ /* notify anyone attached */
+ if (pProtocol->HCIAttached) {
+ A_ASSERT(pProtocol->HCIConfig.TransportRemoved != NULL);
+ pProtocol->HCIConfig.TransportRemoved(pProtocol->HCIConfig.pContext);
+ pProtocol->HCIAttached = FALSE;
+ }
+
+ HCIUartCleanup(pProtocol);
+ DEV_GMBOX_SET_PROTOCOL(pDev,NULL,NULL,NULL,NULL,NULL);
+ }
+
+}
+
+static A_STATUS NotifyTransportReady(GMBOX_PROTO_HCI_UART *pProt)
+{
+ HCI_TRANSPORT_PROPERTIES props;
+ A_STATUS status = A_OK;
+
+ do {
+
+ A_MEMZERO(&props,sizeof(props));
+
+ /* HCI UART only needs one extra byte at the head to indicate the packet TYPE */
+ props.HeadRoom = 1;
+ props.TailRoom = 0;
+ props.IOBlockPad = pProt->pDev->BlockSize;
+ if (pProt->HCIAttached) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI: notifying attached client to transport... \n"));
+ A_ASSERT(pProt->HCIConfig.TransportReady != NULL);
+ status = pProt->HCIConfig.TransportReady(pProt,
+ &props,
+ pProt->HCIConfig.pContext);
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+/*********** HCI UART protocol implementation ************************************************/
+
+HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo)
+{
+ GMBOX_PROTO_HCI_UART *pProtocol = NULL;
+ AR6K_DEVICE *pDev;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportAttach \n"));
+
+ pDev = HTCGetAR6KDevice(HTCHandle);
+
+ LOCK_AR6K(pDev);
+
+ do {
+
+ pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev);
+
+ if (NULL == pProtocol) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not installed! \n"));
+ break;
+ }
+
+ if (pProtocol->HCIAttached) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol already attached! \n"));
+ break;
+ }
+
+ A_MEMCPY(&pProtocol->HCIConfig, pInfo, sizeof(HCI_TRANSPORT_CONFIG_INFO));
+
+ A_ASSERT(pProtocol->HCIConfig.pHCIPktRecv != NULL);
+ A_ASSERT(pProtocol->HCIConfig.pHCISendComplete != NULL);
+
+ pProtocol->HCIAttached = TRUE;
+
+ } while (FALSE);
+
+ UNLOCK_AR6K(pDev);
+
+ if (pProtocol != NULL) {
+ /* TODO ... should we use a worker? */
+ NotifyTransportReady(pProtocol);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach (0x%X) \n",(A_UINT32)pProtocol));
+ return (HCI_TRANSPORT_HANDLE)pProtocol;
+}
+
+void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans)
+{
+ GMBOX_PROTO_HCI_UART *pProtocol = (GMBOX_PROTO_HCI_UART *)HciTrans;
+ AR6K_DEVICE *pDev = pProtocol->pDev;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportDetach \n"));
+
+ LOCK_AR6K(pDev);
+ if (!pProtocol->HCIAttached) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not attached! \n"));
+ UNLOCK_AR6K(pDev);
+ return;
+ }
+ pProtocol->HCIAttached = FALSE;
+ UNLOCK_AR6K(pDev);
+
+ HCI_TransportStop(HciTrans);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach \n"));
+}
+
+A_STATUS HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+ A_STATUS status = A_OK;
+ A_BOOL unblockRecv = FALSE;
+ HTC_PACKET *pPacket;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCI_TransportAddReceivePkt \n"));
+
+ LOCK_HCI_RX(pProt);
+
+ do {
+
+ if (pProt->HCIStopped) {
+ status = A_ECANCELED;
+ break;
+ }
+
+ pPacket = HTC_GET_PKT_AT_HEAD(pQueue);
+
+ if (NULL == pPacket) {
+ status = A_EINVAL;
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv packet added, type :%d, len:%d num:%d \n",
+ HCI_GET_PACKET_TYPE(pPacket), pPacket->BufferLength, HTC_PACKET_QUEUE_DEPTH(pQueue)));
+
+ if (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) {
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIEventBuffers, pQueue);
+ } else if (HCI_GET_PACKET_TYPE(pPacket) == HCI_ACL_TYPE) {
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIACLRecvBuffers, pQueue);
+ } else {
+ status = A_EINVAL;
+ break;
+ }
+
+ if (pProt->RecvStateFlags & HCI_RECV_WAIT_BUFFERS) {
+ if (pProt->WaitBufferType == HCI_GET_PACKET_TYPE(pPacket)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv was blocked on packet type :%d, unblocking.. \n",
+ pProt->WaitBufferType));
+ pProt->RecvStateFlags &= ~HCI_RECV_WAIT_BUFFERS;
+ pProt->WaitBufferType = HCI_PACKET_INVALID;
+ unblockRecv = TRUE;
+ }
+ }
+
+ } while (FALSE);
+
+ UNLOCK_HCI_RX(pProt);
+
+ if (A_FAILED(status)) {
+ while (!HTC_QUEUE_EMPTY(pQueue)) {
+ pPacket = HTC_PACKET_DEQUEUE(pQueue);
+ pPacket->Status = A_ECANCELED;
+ DO_HCI_RECV_INDICATION(pProt,pPacket);
+ }
+ }
+
+ if (unblockRecv) {
+ DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_ASYNC);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCI_TransportAddReceivePkt \n"));
+
+ return A_OK;
+}
+
+A_STATUS HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+
+ return HCITrySend(pProt,pPacket,Synchronous);
+}
+
+void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStop \n"));
+
+ LOCK_AR6K(pProt->pDev);
+ if (pProt->HCIStopped) {
+ UNLOCK_AR6K(pProt->pDev);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n"));
+ return;
+ }
+ pProt->HCIStopped = TRUE;
+ UNLOCK_AR6K(pProt->pDev);
+
+ /* disable interrupts */
+ DevGMboxIRQAction(pProt->pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
+ FlushSendQueue(pProt);
+ FlushRecvBuffers(pProt);
+
+ /* signal bridge side to power down BT */
+ DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_OFF, BTOFF_TIMEOUT_MS);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n"));
+}
+
+A_STATUS HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans)
+{
+ A_STATUS status;
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStart \n"));
+
+ /* set stopped in case we have a problem in starting */
+ pProt->HCIStopped = TRUE;
+
+ do {
+
+ status = InitTxCreditState(pProt);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ status = DevGMboxIRQAction(pProt->pDev, GMBOX_ERRORS_IRQ_ENABLE, PROC_IO_SYNC);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* enable recv */
+ status = DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_SYNC);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* signal bridge side to power up BT */
+ status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_ON, BTON_TIMEOUT_MS);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI_TransportStart : Failed to trigger BT ON \n"));
+ break;
+ }
+
+ /* we made it */
+ pProt->HCIStopped = FALSE;
+
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStart \n"));
+
+ return status;
+}
+
+A_STATUS HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+ return DevGMboxIRQAction(pProt->pDev,
+ Enable ? GMBOX_RECV_IRQ_ENABLE : GMBOX_RECV_IRQ_DISABLE,
+ PROC_IO_SYNC);
+
+}
+
+A_STATUS HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
+ HTC_PACKET *pPacket,
+ int MaxPollMS)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+ A_STATUS status = A_OK;
+ A_UINT8 lookAhead[8];
+ int bytes;
+ int totalRecvLength;
+
+ MaxPollMS = MaxPollMS / 16;
+
+ if (MaxPollMS < 2) {
+ MaxPollMS = 2;
+ }
+
+ while (MaxPollMS) {
+
+ bytes = sizeof(lookAhead);
+ status = DevGMboxRecvLookAheadPeek(pProt->pDev,lookAhead,&bytes);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (bytes < 3) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI recv poll got bytes: %d, retry : %d \n",
+ bytes, MaxPollMS));
+ A_MDELAY(16);
+ MaxPollMS--;
+ continue;
+ }
+
+ totalRecvLength = 0;
+ switch (lookAhead[0]) {
+ case HCI_UART_EVENT_PKT:
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n",
+ lookAhead[1], lookAhead[2]));
+ totalRecvLength = lookAhead[2];
+ totalRecvLength += 3; /* add type + event code + length field */
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",lookAhead[0]));
+ status = A_EPROTO;
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ pPacket->Completion = NULL;
+ status = DevGMboxRead(pProt->pDev,pPacket,totalRecvLength);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ pPacket->pBuffer++;
+ pPacket->ActualLength = totalRecvLength - 1;
+ pPacket->Status = A_OK;
+ break;
+ }
+
+ if (MaxPollMS == 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI recv poll timeout! \n"));
+ status = A_ERROR;
+ }
+
+ return status;
+}
+
+#define LSB_SCRATCH_IDX 4
+#define MSB_SCRATCH_IDX 5
+A_STATUS HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud)
+{
+ GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans;
+ HIF_DEVICE *pHIFDevice = (HIF_DEVICE *)(pProt->pDev->HIFDevice);
+ A_UINT32 scaledBaud, scratchAddr;
+ A_STATUS status = A_OK;
+
+ /* Divide the desired baud rate by 100
+ * Store the LSB in the local scratch register 4 and the MSB in the local
+ * scratch register 5 for the target to read
+ */
+ scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * LSB_SCRATCH_IDX);
+ scaledBaud = (Baud / 100) & LOCAL_SCRATCH_VALUE_MASK;
+ status = ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud);
+ scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * MSB_SCRATCH_IDX);
+ scaledBaud = ((Baud / 100) >> (LOCAL_SCRATCH_VALUE_MSB+1)) & LOCAL_SCRATCH_VALUE_MASK;
+ status |= ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud);
+ if (A_OK != status) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to set up baud rate in scratch register!"));
+ return status;
+ }
+
+ /* Now interrupt the target to tell it about the baud rate */
+ status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BAUD_SET, BAUD_TIMEOUT_MS);
+ if (A_OK != status) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to tell target to change baud rate!"));
+ }
+
+ return status;
+}
+
+#endif //ATH_AR6K_ENABLE_GMBOX
+
diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/makefile b/drivers/net/wireless/ath6kl/htc2/AR6000/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/AR6000/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/htc2/htc.c b/drivers/net/wireless/ath6kl/htc2/htc.c
new file mode 100644
index 000000000000..0068685972a9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc.c
@@ -0,0 +1,558 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+#ifdef DEBUG
+static ATH_DEBUG_MASK_DESCRIPTION g_HTCDebugDescription[] = {
+ { ATH_DEBUG_SEND , "Send"},
+ { ATH_DEBUG_RECV , "Recv"},
+ { ATH_DEBUG_SYNC , "Sync"},
+ { ATH_DEBUG_DUMP , "Dump Data (RX or TX)"},
+ { ATH_DEBUG_IRQ , "Interrupt Processing"}
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc,
+ "htc",
+ "Host Target Communications",
+ ATH_DEBUG_MASK_DEFAULTS,
+ ATH_DEBUG_DESCRIPTION_COUNT(g_HTCDebugDescription),
+ g_HTCDebugDescription);
+
+#endif
+
+static void HTCReportFailure(void *Context);
+static void ResetEndpointStates(HTC_TARGET *target);
+
+void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
+{
+ LOCK_HTC(target);
+ HTC_PACKET_ENQUEUE(pList,pPacket);
+ UNLOCK_HTC(target);
+}
+
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList)
+{
+ HTC_PACKET *pPacket;
+
+ LOCK_HTC(target);
+ pPacket = HTC_PACKET_DEQUEUE(pList);
+ UNLOCK_HTC(target);
+
+ return pPacket;
+}
+
+/* cleanup the HTC instance */
+static void HTCCleanup(HTC_TARGET *target)
+{
+ A_INT32 i;
+
+ DevCleanup(&target->Device);
+
+ for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
+ if (target->HTCControlBuffers[i].Buffer) {
+ A_FREE(target->HTCControlBuffers[i].Buffer);
+ }
+ }
+
+ if (A_IS_MUTEX_VALID(&target->HTCLock)) {
+ A_MUTEX_DELETE(&target->HTCLock);
+ }
+
+ if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
+ A_MUTEX_DELETE(&target->HTCRxLock);
+ }
+
+ if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
+ A_MUTEX_DELETE(&target->HTCTxLock);
+ }
+ /* free our instance */
+ A_FREE(target);
+}
+
+/* registered target arrival callback from the HIF layer */
+HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo)
+{
+ HTC_TARGET *target = NULL;
+ A_STATUS status = A_OK;
+ int i;
+ A_UINT32 ctrl_bufsz;
+ A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
+
+ A_REGISTER_MODULE_DEBUG_INFO(htc);
+
+ do {
+
+ /* allocate target memory */
+ if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+ status = A_ERROR;
+ break;
+ }
+
+ A_MEMZERO(target, sizeof(HTC_TARGET));
+ A_MUTEX_INIT(&target->HTCLock);
+ A_MUTEX_INIT(&target->HTCRxLock);
+ A_MUTEX_INIT(&target->HTCTxLock);
+ INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
+ INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
+
+ /* give device layer the hif device handle */
+ target->Device.HIFDevice = hif_handle;
+ /* give the device layer our context (for event processing)
+ * the device layer will register it's own context with HIF
+ * so we need to set this so we can fetch it in the target remove handler */
+ target->Device.HTCContext = target;
+ /* set device layer target failure callback */
+ target->Device.TargetFailureCallback = HTCReportFailure;
+ /* set device layer recv message pending callback */
+ target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
+ target->EpWaitingForBuffers = ENDPOINT_MAX;
+
+ A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO));
+
+ ResetEndpointStates(target);
+
+ /* setup device layer */
+ status = DevSetup(&target->Device);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+
+ /* get the block sizes */
+ status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ blocksizes, sizeof(blocksizes));
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n"));
+ break;
+ }
+
+ /* Set the control buffer size based on the block size */
+ if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) {
+ ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH;
+ } else {
+ ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH;
+ }
+ for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
+ target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz);
+ if (target->HTCControlBuffers[i].Buffer == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+ status = A_ERROR;
+ break;
+ }
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* carve up buffers/packets for control messages */
+ for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
+ HTC_PACKET *pControlPacket;
+ pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+ SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
+ target,
+ target->HTCControlBuffers[i].Buffer,
+ ctrl_bufsz,
+ ENDPOINT_0);
+ HTC_FREE_CONTROL_RX(target,pControlPacket);
+ }
+
+ for (;i < NUM_CONTROL_BUFFERS;i++) {
+ HTC_PACKET *pControlPacket;
+ pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+ INIT_HTC_PACKET_INFO(pControlPacket,
+ target->HTCControlBuffers[i].Buffer,
+ ctrl_bufsz);
+ HTC_FREE_CONTROL_TX(target,pControlPacket);
+ }
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ if (target != NULL) {
+ HTCCleanup(target);
+ target = NULL;
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n"));
+
+ return target;
+}
+
+void HTCDestroy(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%X \n",(A_UINT32)target));
+ HTCCleanup(target);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n"));
+}
+
+/* get the low level HIF device for the caller , the caller may wish to do low level
+ * HIF requests */
+void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ return target->Device.HIFDevice;
+}
+
+/* wait for the target to arrive (sends HTC Ready message)
+ * this operation is fully synchronous and the message is polled for */
+A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_STATUS status;
+ HTC_PACKET *pPacket = NULL;
+ HTC_READY_EX_MSG *pRdyMsg;
+ HTC_SERVICE_CONNECT_REQ connect;
+ HTC_SERVICE_CONNECT_RESP resp;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target));
+
+ do {
+
+#ifdef MBOXHW_UNIT_TEST
+
+ status = DoMboxHWTest(&target->Device);
+
+ if (status != A_OK) {
+ break;
+ }
+
+#endif
+
+ /* we should be getting 1 control message that the target is ready */
+ status = HTCWaitforControlMessage(target, &pPacket);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
+ break;
+ }
+
+ /* we controlled the buffer creation so it has to be properly aligned */
+ pRdyMsg = (HTC_READY_EX_MSG *)pPacket->pBuffer;
+
+ if ((pRdyMsg->Version2_0_Info.MessageID != HTC_MSG_READY_ID) ||
+ (pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
+ /* this message is not valid */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+
+ if (pRdyMsg->Version2_0_Info.CreditCount == 0 || pRdyMsg->Version2_0_Info.CreditSize == 0) {
+ /* this message is not valid */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ target->TargetCredits = pRdyMsg->Version2_0_Info.CreditCount;
+ target->TargetCreditSize = pRdyMsg->Version2_0_Info.CreditSize;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, (" Target Ready: credits: %d credit size: %d\n",
+ target->TargetCredits, target->TargetCreditSize));
+
+ /* check if this is an extended ready message */
+ if (pPacket->ActualLength >= sizeof(HTC_READY_EX_MSG)) {
+ /* this is an extended message */
+ target->HTCTargetVersion = pRdyMsg->HTCVersion;
+ target->MaxMsgPerBundle = pRdyMsg->MaxMsgsPerHTCBundle;
+ } else {
+ /* legacy */
+ target->HTCTargetVersion = HTC_VERSION_2P0;
+ target->MaxMsgPerBundle = 0;
+ }
+
+#ifdef HTC_FORCE_LEGACY_2P0
+ /* for testing and comparison...*/
+ target->HTCTargetVersion = HTC_VERSION_2P0;
+ target->MaxMsgPerBundle = 0;
+#endif
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
+ ("Using HTC Protocol Version : %s (%d)\n ",
+ (target->HTCTargetVersion == HTC_VERSION_2P0) ? "2.0" : ">= 2.1",
+ target->HTCTargetVersion));
+
+ if (target->MaxMsgPerBundle > 0) {
+ /* limit what HTC can handle */
+ target->MaxMsgPerBundle = min(HTC_HOST_MAX_MSG_PER_BUNDLE, target->MaxMsgPerBundle);
+ /* target supports message bundling, setup device layer */
+ if (A_FAILED(DevSetupMsgBundling(&target->Device,target->MaxMsgPerBundle))) {
+ /* device layer can't handle bundling */
+ target->MaxMsgPerBundle = 0;
+ } else {
+ /* limit bundle what the device layer can handle */
+ target->MaxMsgPerBundle = min(DEV_GET_MAX_MSG_PER_BUNDLE(&target->Device),
+ target->MaxMsgPerBundle);
+ }
+ }
+
+ if (target->MaxMsgPerBundle > 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
+ (" HTC bundling allowed. Max Msg Per HTC Bundle: %d\n", target->MaxMsgPerBundle));
+ target->SendBundlingEnabled = TRUE;
+ target->RecvBundlingEnabled = TRUE;
+ if (!DEV_IS_LEN_BLOCK_ALIGNED(&target->Device,target->TargetCreditSize)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("*** Credit size: %d is not block aligned! Disabling send bundling \n",
+ target->TargetCreditSize));
+ /* disallow send bundling since the credit size is not aligned to a block size
+ * the I/O block padding will spill into the next credit buffer which is fatal */
+ target->SendBundlingEnabled = FALSE;
+ }
+ }
+
+ /* setup our pseudo HTC control endpoint connection */
+ A_MEMZERO(&connect,sizeof(connect));
+ A_MEMZERO(&resp,sizeof(resp));
+ connect.EpCallbacks.pContext = target;
+ connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
+ connect.EpCallbacks.EpRecv = HTCControlRecv;
+ connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */
+ connect.EpCallbacks.EpSendFull = NULL; /* not nedded */
+ connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
+ connect.ServiceID = HTC_CTRL_RSVD_SVC;
+
+ /* connect fake service */
+ status = HTCConnectService((HTC_HANDLE)target,
+ &connect,
+ &resp);
+
+ if (!A_FAILED(status)) {
+ break;
+ }
+
+ } while (FALSE);
+
+ if (pPacket != NULL) {
+ HTC_FREE_CONTROL_RX(target,pPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
+
+ return status;
+}
+
+
+
+/* Start HTC, enable interrupts and let the target know host has finished setup */
+A_STATUS HTCStart(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_PACKET *pPacket;
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
+
+ /* make sure interrupts are disabled at the chip level,
+ * this function can be called again from a reboot of the target without shutting down HTC */
+ DevDisableInterrupts(&target->Device);
+ /* make sure state is cleared again */
+ target->OpStateFlags = 0;
+ target->RecvStateFlags = 0;
+
+ /* now that we are starting, push control receive buffers into the
+ * HTC control endpoint */
+
+ while (1) {
+ pPacket = HTC_ALLOC_CONTROL_RX(target);
+ if (NULL == pPacket) {
+ break;
+ }
+ HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
+ }
+
+ do {
+
+ AR_DEBUG_ASSERT(target->InitCredits != NULL);
+ AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
+ AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
+
+ /* call init credits callback to do the distribution ,
+ * NOTE: the first entry in the distribution list is ENDPOINT_0, so
+ * we pass the start of the list after this one. */
+ target->InitCredits(target->pCredDistContext,
+ target->EpCreditDistributionListHead->pNext,
+ target->TargetCredits);
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+ DumpCreditDistStates(target);
+ }
+
+ /* the caller is done connecting to services, so we can indicate to the
+ * target that the setup phase is complete */
+ status = HTCSendSetupComplete(target);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* unmask interrupts */
+ status = DevUnmaskInterrupts(&target->Device);
+
+ if (A_FAILED(status)) {
+ HTCStop(target);
+ }
+
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
+ return status;
+}
+
+static void ResetEndpointStates(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ int i;
+
+ for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+ pEndpoint = &target->EndPoint[i];
+
+ A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist));
+ pEndpoint->ServiceID = 0;
+ pEndpoint->MaxMsgLength = 0;
+ pEndpoint->MaxTxQueueDepth = 0;
+#ifdef HTC_EP_STAT_PROFILING
+ A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
+#endif
+ INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
+ INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
+ INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
+ pEndpoint->target = target;
+ }
+ /* reset distribution list */
+ target->EpCreditDistributionListHead = NULL;
+}
+
+/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
+void HTCStop(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
+
+ LOCK_HTC(target);
+ /* mark that we are shutting down .. */
+ target->OpStateFlags |= HTC_OP_STATE_STOPPING;
+ UNLOCK_HTC(target);
+
+ /* Masking interrupts is a synchronous operation, when this function returns
+ * all pending HIF I/O has completed, we can safely flush the queues */
+ DevMaskInterrupts(&target->Device);
+
+ /* flush all send packets */
+ HTCFlushSendPkts(target);
+ /* flush all recv buffers */
+ HTCFlushRecvBuffers(target);
+
+ ResetEndpointStates(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
+}
+
+void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+ LOCK_HTC_TX(target);
+
+ DumpCreditDistStates(target);
+
+ UNLOCK_HTC_TX(target);
+
+ DumpAR6KDevState(&target->Device);
+}
+
+/* report a target failure from the device, this is a callback from the device layer
+ * which uses a mechanism to report errors from the target (i.e. special interrupts) */
+static void HTCReportFailure(void *Context)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+
+ target->TargetFailure = TRUE;
+
+ if (target->HTCInitInfo.TargetFailure != NULL) {
+ /* let upper layer know, it needs to call HTCStop() */
+ target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR);
+ }
+}
+
+A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ HTC_ENDPOINT_STAT_ACTION Action,
+ HTC_ENDPOINT_STATS *pStats)
+{
+
+#ifdef HTC_EP_STAT_PROFILING
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_BOOL clearStats = FALSE;
+ A_BOOL sample = FALSE;
+
+ switch (Action) {
+ case HTC_EP_STAT_SAMPLE :
+ sample = TRUE;
+ break;
+ case HTC_EP_STAT_SAMPLE_AND_CLEAR :
+ sample = TRUE;
+ clearStats = TRUE;
+ break;
+ case HTC_EP_STAT_CLEAR :
+ clearStats = TRUE;
+ break;
+ default:
+ break;
+ }
+
+ A_ASSERT(Endpoint < ENDPOINT_MAX);
+
+ /* lock out TX and RX while we sample and/or clear */
+ LOCK_HTC_TX(target);
+ LOCK_HTC_RX(target);
+
+ if (sample) {
+ A_ASSERT(pStats != NULL);
+ /* return the stats to the caller */
+ A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+ }
+
+ if (clearStats) {
+ /* reset stats */
+ A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+ }
+
+ UNLOCK_HTC_RX(target);
+ UNLOCK_HTC_TX(target);
+
+ return TRUE;
+#else
+ return FALSE;
+#endif
+}
+
+AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ return &target->Device;
+}
+
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_debug.h b/drivers/net/wireless/ath6kl/htc2/htc_debug.h
new file mode 100644
index 000000000000..0ceecf0dd36c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_debug.h
@@ -0,0 +1,34 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_debug.h" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef HTC_DEBUG_H_
+#define HTC_DEBUG_H_
+
+#define ATH_MODULE_NAME htc
+#include "a_debug.h"
+
+/* ------- Debug related stuff ------- */
+
+#define ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4)
+
+
+#endif /*HTC_DEBUG_H_*/
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_internal.h b/drivers/net/wireless/ath6kl/htc2/htc_internal.h
new file mode 100644
index 000000000000..fbff23f598f1
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_internal.h
@@ -0,0 +1,213 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_internal.h" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HTC_INTERNAL_H_
+#define _HTC_INTERNAL_H_
+
+/* for debugging, uncomment this to capture the last frame header, on frame header
+ * processing errors, the last frame header is dump for comparison */
+//#define HTC_CAPTURE_LAST_FRAME
+
+//#define HTC_EP_STAT_PROFILING
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_debug.h"
+#include "htc.h"
+#include "htc_api.h"
+#include "bmi_msg.h"
+#include "hif.h"
+#include "AR6000/ar6k.h"
+
+/* HTC operational parameters */
+#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */
+#define HTC_TARGET_DEBUG_INTR_MASK 0x01
+#define HTC_TARGET_CREDIT_INTR_MASK 0xF0
+
+#define HTC_HOST_MAX_MSG_PER_BUNDLE 8
+#define HTC_MIN_HTC_MSGS_TO_BUNDLE 2
+
+/* packet flags */
+
+#define HTC_RX_PKT_IGNORE_LOOKAHEAD (1 << 0)
+#define HTC_RX_PKT_REFRESH_HDR (1 << 1)
+#define HTC_RX_PKT_PART_OF_BUNDLE (1 << 2)
+#define HTC_RX_PKT_NO_RECYCLE (1 << 3)
+
+/* scatter request flags */
+
+#define HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE (1 << 0)
+
+typedef struct _HTC_ENDPOINT {
+ HTC_ENDPOINT_ID Id;
+ HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to
+ non-zero value means this endpoint is in use */
+ HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */
+ HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */
+ HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */
+ HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */
+ int MaxTxQueueDepth; /* max depth of the TX queue before we need to
+ call driver's full handler */
+ int MaxMsgLength; /* max length of endpoint message */
+ int TxProcessCount; /* reference count to continue tx processing */
+ HTC_PACKET_QUEUE RecvIndicationQueue; /* recv packets ready to be indicated */
+ int RxProcessCount; /* reference count to allow single processing context */
+ struct _HTC_TARGET *target; /* back pointer to target */
+ A_UINT8 SeqNo; /* TX seq no (helpful) for debugging */
+ A_UINT32 LocalConnectionFlags; /* local connection flags */
+#ifdef HTC_EP_STAT_PROFILING
+ HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */
+#endif
+} HTC_ENDPOINT;
+
+#ifdef HTC_EP_STAT_PROFILING
+#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
+#else
+#define INC_HTC_EP_STAT(p,stat,count)
+#endif
+
+#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL
+
+#define NUM_CONTROL_BUFFERS 8
+#define NUM_CONTROL_TX_BUFFERS 2
+#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
+
+typedef struct HTC_CONTROL_BUFFER {
+ HTC_PACKET HtcPacket;
+ A_UINT8 *Buffer;
+} HTC_CONTROL_BUFFER;
+
+#define HTC_RECV_WAIT_BUFFERS (1 << 0)
+#define HTC_OP_STATE_STOPPING (1 << 0)
+
+/* our HTC target state */
+typedef struct _HTC_TARGET {
+ HTC_ENDPOINT EndPoint[ENDPOINT_MAX];
+ HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS];
+ HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead;
+ HTC_PACKET_QUEUE ControlBufferTXFreeList;
+ HTC_PACKET_QUEUE ControlBufferRXFreeList;
+ HTC_CREDIT_DIST_CALLBACK DistributeCredits;
+ HTC_CREDIT_INIT_CALLBACK InitCredits;
+ void *pCredDistContext;
+ int TargetCredits;
+ unsigned int TargetCreditSize;
+ A_MUTEX_T HTCLock;
+ A_MUTEX_T HTCRxLock;
+ A_MUTEX_T HTCTxLock;
+ AR6K_DEVICE Device; /* AR6K - specific state */
+ A_UINT32 OpStateFlags;
+ A_UINT32 RecvStateFlags;
+ HTC_ENDPOINT_ID EpWaitingForBuffers;
+ A_BOOL TargetFailure;
+#ifdef HTC_CAPTURE_LAST_FRAME
+ HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */
+ A_UINT8 LastTrailer[256];
+ A_UINT8 LastTrailerLength;
+#endif
+ HTC_INIT_INFO HTCInitInfo;
+ A_UINT8 HTCTargetVersion;
+ int MaxMsgPerBundle; /* max messages per bundle for HTC */
+ A_BOOL SendBundlingEnabled; /* run time enable for send bundling (dynamic) */
+ int RecvBundlingEnabled; /* run time enable for recv bundling (dynamic) */
+} HTC_TARGET;
+
+#define HTC_STOPPING(t) ((t)->OpStateFlags & HTC_OP_STATE_STOPPING)
+#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock);
+#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock);
+#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock);
+#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
+#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock);
+#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
+
+#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
+#define HTC_RECYCLE_RX_PKT(target,p,e) \
+{ \
+ if ((p)->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_NO_RECYCLE) { \
+ HTC_PACKET_RESET_RX(pPacket); \
+ pPacket->Status = A_ECANCELED; \
+ (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \
+ (p)); \
+ } else { \
+ HTC_PACKET_RESET_RX(pPacket); \
+ HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \
+ } \
+}
+
+/* internal HTC functions */
+void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
+void HTCControlRecv(void *Context, HTC_PACKET *pPacket);
+A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
+void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
+A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket);
+void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
+A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched);
+void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
+A_STATUS HTCSendSetupComplete(HTC_TARGET *target);
+void HTCFlushRecvBuffers(HTC_TARGET *target);
+void HTCFlushSendPkts(HTC_TARGET *target);
+void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
+void DumpCreditDistStates(HTC_TARGET *target);
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
+ HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
+ if (pPacket != NULL) {
+ /* set payload pointer area with some headroom */
+ pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
+ }
+ return pPacket;
+}
+
+#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
+#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
+#define HTC_FREE_CONTROL_RX(t,p) \
+{ \
+ HTC_PACKET_RESET_RX(p); \
+ HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
+}
+
+#define HTC_PREPARE_SEND_PKT(pP,sendflags,ctrl0,ctrl1) \
+{ \
+ A_UINT8 *pHdrBuf; \
+ (pP)->pBuffer -= HTC_HDR_LENGTH; \
+ pHdrBuf = (pP)->pBuffer; \
+ A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)(pP)->ActualLength); \
+ A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,(sendflags)); \
+ A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)(pP)->Endpoint); \
+ A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[0], (A_UINT8)(ctrl0)); \
+ A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[1], (A_UINT8)(ctrl1)); \
+}
+
+#define HTC_UNPREPARE_SEND_PKT(pP) \
+ (pP)->pBuffer += HTC_HDR_LENGTH; \
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_INTERNAL_H_ */
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_recv.c b/drivers/net/wireless/ath6kl/htc2/htc_recv.c
new file mode 100644
index 000000000000..2b4c130b9467
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_recv.c
@@ -0,0 +1,1545 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_recv.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+#define HTCIssueRecv(t, p) \
+ DevRecvPacket(&(t)->Device, \
+ (p), \
+ (p)->ActualLength)
+
+#define DO_RCV_COMPLETION(e,q) DoRecvCompletion(e,q)
+
+#define DUMP_RECV_PKT_INFO(pP) \
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC RECV packet 0x%X (%d bytes) (hdr:0x%X) on ep : %d \n", \
+ (A_UINT32)(pP), \
+ (pP)->ActualLength, \
+ (pP)->PktInfo.AsRx.ExpectedHdr, \
+ (pP)->Endpoint))
+
+#ifdef HTC_EP_STAT_PROFILING
+#define HTC_RX_STAT_PROFILE(t,ep,numLookAheads) \
+{ \
+ INC_HTC_EP_STAT((ep), RxReceived, 1); \
+ if ((numLookAheads) == 1) { \
+ INC_HTC_EP_STAT((ep), RxLookAheads, 1); \
+ } else if ((numLookAheads) > 1) { \
+ INC_HTC_EP_STAT((ep), RxBundleLookAheads, 1); \
+ } \
+}
+#else
+#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
+#endif
+
+static void DoRecvCompletion(HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET_QUEUE *pQueueToIndicate)
+{
+
+ do {
+
+ if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
+ /* nothing to indicate */
+ break;
+ }
+
+ if (pEndpoint->EpCallBacks.EpRecvPktMultiple != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d, recv multiple callback (%d pkts) \n",
+ pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate)));
+ /* a recv multiple handler is being used, pass the queue to the handler */
+ pEndpoint->EpCallBacks.EpRecvPktMultiple(pEndpoint->EpCallBacks.pContext,
+ pQueueToIndicate);
+ INIT_HTC_PACKET_QUEUE(pQueueToIndicate);
+ } else {
+ HTC_PACKET *pPacket;
+ /* using legacy EpRecv */
+ do {
+ pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate);
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d recv callback on packet 0x%X \n", \
+ pEndpoint->Id, (A_UINT32)(pPacket)));
+ pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket);
+ } while (!HTC_QUEUE_EMPTY(pQueueToIndicate));
+ }
+
+ } while (FALSE);
+
+}
+
+static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target,
+ A_UINT8 *pBuffer,
+ int Length,
+ A_UINT32 *pNextLookAheads,
+ int *pNumLookAheads,
+ HTC_ENDPOINT_ID FromEndpoint)
+{
+ HTC_RECORD_HDR *pRecord;
+ A_UINT8 *pRecordBuf;
+ HTC_LOOKAHEAD_REPORT *pLookAhead;
+ A_UINT8 *pOrigBuffer;
+ int origLength;
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length));
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer");
+ }
+
+ pOrigBuffer = pBuffer;
+ origLength = Length;
+ status = A_OK;
+
+ while (Length > 0) {
+
+ if (Length < sizeof(HTC_RECORD_HDR)) {
+ status = A_EPROTO;
+ break;
+ }
+ /* these are byte aligned structs */
+ pRecord = (HTC_RECORD_HDR *)pBuffer;
+ Length -= sizeof(HTC_RECORD_HDR);
+ pBuffer += sizeof(HTC_RECORD_HDR);
+
+ if (pRecord->Length > Length) {
+ /* no room left in buffer for record */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
+ pRecord->Length, pRecord->RecordID, Length));
+ status = A_EPROTO;
+ break;
+ }
+ /* start of record follows the header */
+ pRecordBuf = pBuffer;
+
+ switch (pRecord->RecordID) {
+ case HTC_RECORD_CREDITS:
+ AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT));
+ HTCProcessCreditRpt(target,
+ (HTC_CREDIT_REPORT *)pRecordBuf,
+ pRecord->Length / (sizeof(HTC_CREDIT_REPORT)),
+ FromEndpoint);
+ break;
+ case HTC_RECORD_LOOKAHEAD:
+ AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT));
+ pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf;
+ if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) &&
+ (pNextLookAheads != NULL)) {
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n",
+ pLookAhead->PreValid,
+ pLookAhead->PostValid));
+
+ /* look ahead bytes are valid, copy them over */
+ ((A_UINT8 *)(&pNextLookAheads[0]))[0] = pLookAhead->LookAhead[0];
+ ((A_UINT8 *)(&pNextLookAheads[0]))[1] = pLookAhead->LookAhead[1];
+ ((A_UINT8 *)(&pNextLookAheads[0]))[2] = pLookAhead->LookAhead[2];
+ ((A_UINT8 *)(&pNextLookAheads[0]))[3] = pLookAhead->LookAhead[3];
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ DebugDumpBytes((A_UINT8 *)pNextLookAheads,4,"Next Look Ahead");
+ }
+ /* just one normal lookahead */
+ *pNumLookAheads = 1;
+ }
+ break;
+ case HTC_RECORD_LOOKAHEAD_BUNDLE:
+ AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT));
+ if (pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT) &&
+ (pNextLookAheads != NULL)) {
+ HTC_BUNDLED_LOOKAHEAD_REPORT *pBundledLookAheadRpt;
+ int i;
+
+ pBundledLookAheadRpt = (HTC_BUNDLED_LOOKAHEAD_REPORT *)pRecordBuf;
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ DebugDumpBytes(pRecordBuf,pRecord->Length,"Bundle LookAhead");
+ }
+
+ if ((pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))) >
+ HTC_HOST_MAX_MSG_PER_BUNDLE) {
+ /* this should never happen, the target restricts the number
+ * of messages per bundle configured by the host */
+ A_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ for (i = 0; i < (int)(pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))); i++) {
+ ((A_UINT8 *)(&pNextLookAheads[i]))[0] = pBundledLookAheadRpt->LookAhead[0];
+ ((A_UINT8 *)(&pNextLookAheads[i]))[1] = pBundledLookAheadRpt->LookAhead[1];
+ ((A_UINT8 *)(&pNextLookAheads[i]))[2] = pBundledLookAheadRpt->LookAhead[2];
+ ((A_UINT8 *)(&pNextLookAheads[i]))[3] = pBundledLookAheadRpt->LookAhead[3];
+ pBundledLookAheadRpt++;
+ }
+
+ *pNumLookAheads = i;
+ }
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n",
+ pRecord->RecordID, pRecord->Length));
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* advance buffer past this record for next time around */
+ pBuffer += pRecord->Length;
+ Length -= pRecord->Length;
+ }
+
+ if (A_FAILED(status)) {
+ DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer");
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n"));
+ return status;
+
+}
+
+/* process a received message (i.e. strip off header, process any trailer data)
+ * note : locks must be released when this function is called */
+static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target,
+ HTC_PACKET *pPacket,
+ A_UINT32 *pNextLookAheads,
+ int *pNumLookAheads)
+{
+ A_UINT8 temp;
+ A_UINT8 *pBuf;
+ A_STATUS status = A_OK;
+ A_UINT16 payloadLen;
+ A_UINT32 lookAhead;
+
+ pBuf = pPacket->pBuffer;
+
+ if (pNumLookAheads != NULL) {
+ *pNumLookAheads = 0;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n"));
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT");
+ }
+
+ do {
+ /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to
+ * retrieve 16 bit fields */
+ payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen);
+
+ ((A_UINT8 *)&lookAhead)[0] = pBuf[0];
+ ((A_UINT8 *)&lookAhead)[1] = pBuf[1];
+ ((A_UINT8 *)&lookAhead)[2] = pBuf[2];
+ ((A_UINT8 *)&lookAhead)[3] = pBuf[3];
+
+ if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_REFRESH_HDR) {
+ /* refresh expected hdr, since this was unknown at the time we grabbed the packets
+ * as part of a bundle */
+ pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead;
+ /* refresh actual length since we now have the real header */
+ pPacket->ActualLength = payloadLen + HTC_HDR_LENGTH;
+
+ /* validate the actual header that was refreshed */
+ if (pPacket->ActualLength > pPacket->BufferLength) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Refreshed HDR payload length (%d) in bundled RECV is invalid (hdr: 0x%X) \n",
+ payloadLen, lookAhead));
+ /* limit this to max buffer just to print out some of the buffer */
+ pPacket->ActualLength = min(pPacket->ActualLength, pPacket->BufferLength);
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pPacket->Endpoint != A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Refreshed HDR endpoint (%d) does not match expected endpoint (%d) \n",
+ A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID), pPacket->Endpoint));
+ status = A_EPROTO;
+ break;
+ }
+ }
+
+ if (lookAhead != pPacket->PktInfo.AsRx.ExpectedHdr) {
+ /* somehow the lookahead that gave us the full read length did not
+ * reflect the actual header in the pending message */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCProcessRecvHeader, lookahead mismatch! (pPkt:0x%X flags:0x%X) \n",
+ (A_UINT32)pPacket, pPacket->PktInfo.AsRx.HTCRxFlags));
+ DebugDumpBytes((A_UINT8 *)&pPacket->PktInfo.AsRx.ExpectedHdr,4,"Expected Message LookAhead");
+ DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header");
+#ifdef HTC_CAPTURE_LAST_FRAME
+ DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header");
+ if (target->LastTrailerLength != 0) {
+ DebugDumpBytes(target->LastTrailer,
+ target->LastTrailerLength,
+ "Last trailer");
+ }
+#endif
+ status = A_EPROTO;
+ break;
+ }
+
+ /* get flags */
+ temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags);
+
+ if (temp & HTC_FLAGS_RECV_TRAILER) {
+ /* this packet has a trailer */
+
+ /* extract the trailer length in control byte 0 */
+ temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]);
+
+ if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n",
+ payloadLen, temp));
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) {
+ /* this packet was fetched as part of an HTC bundle, the embedded lookahead is
+ * not valid since the next packet may have already been fetched as part of the
+ * bundle */
+ pNextLookAheads = NULL;
+ pNumLookAheads = NULL;
+ }
+
+ /* process trailer data that follows HDR + application payload */
+ status = HTCProcessTrailer(target,
+ (pBuf + HTC_HDR_LENGTH + payloadLen - temp),
+ temp,
+ pNextLookAheads,
+ pNumLookAheads,
+ pPacket->Endpoint);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+#ifdef HTC_CAPTURE_LAST_FRAME
+ A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp);
+ target->LastTrailerLength = temp;
+#endif
+ /* trim length by trailer bytes */
+ pPacket->ActualLength -= temp;
+ }
+#ifdef HTC_CAPTURE_LAST_FRAME
+ else {
+ target->LastTrailerLength = 0;
+ }
+#endif
+
+ /* if we get to this point, the packet is good */
+ /* remove header and adjust length */
+ pPacket->pBuffer += HTC_HDR_LENGTH;
+ pPacket->ActualLength -= HTC_HDR_LENGTH;
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ /* dump the whole packet */
+ DebugDumpBytes(pBuf,pPacket->ActualLength < 256 ? pPacket->ActualLength : 256 ,"BAD HTC Recv PKT");
+ } else {
+#ifdef HTC_CAPTURE_LAST_FRAME
+ A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR));
+#endif
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ if (pPacket->ActualLength > 0) {
+ AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg");
+ }
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n"));
+ return status;
+}
+
+static INLINE void HTCAsyncRecvCheckMorePackets(HTC_TARGET *target,
+ A_UINT32 NextLookAheads[],
+ int NumLookAheads,
+ A_BOOL CheckMoreMsgs)
+{
+ /* was there a lookahead for the next packet? */
+ if (NumLookAheads > 0) {
+ A_STATUS nextStatus;
+ int fetched = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTCAsyncRecvCheckMorePackets - num lookaheads were non-zero : %d \n",
+ NumLookAheads));
+ /* force status re-check */
+ REF_IRQ_STATUS_RECHECK(&target->Device);
+ /* we have more packets, get the next packet fetch started */
+ nextStatus = HTCRecvMessagePendingHandler(target, NextLookAheads, NumLookAheads, NULL, &fetched);
+ if (A_EPROTO == nextStatus) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Next look ahead from recv header was INVALID\n"));
+ DebugDumpBytes((A_UINT8 *)NextLookAheads,
+ NumLookAheads * (sizeof(A_UINT32)),
+ "BAD lookaheads from lookahead report");
+ }
+ if (A_SUCCESS(nextStatus) && !fetched) {
+ /* we could not fetch any more packets due to resources */
+ DevAsyncIrqProcessComplete(&target->Device);
+ }
+ } else {
+ if (CheckMoreMsgs) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTCAsyncRecvCheckMorePackets - rechecking for more messages...\n"));
+ /* if we did not get anything on the look-ahead,
+ * call device layer to asynchronously re-check for messages. If we can keep the async
+ * processing going we get better performance. If there is a pending message we will keep processing
+ * messages asynchronously which should pipeline things nicely */
+ DevCheckPendingRecvMsgsAsync(&target->Device);
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("HTCAsyncRecvCheckMorePackets - no check \n"));
+ }
+ }
+
+
+}
+
+ /* unload the recv completion queue */
+static INLINE void DrainRecvIndicationQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+ HTC_PACKET_QUEUE recvCompletions;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+DrainRecvIndicationQueue \n"));
+
+ INIT_HTC_PACKET_QUEUE(&recvCompletions);
+
+ LOCK_HTC_RX(target);
+
+ /* increment rx processing count on entry */
+ pEndpoint->RxProcessCount++;
+ if (pEndpoint->RxProcessCount > 1) {
+ pEndpoint->RxProcessCount--;
+ /* another thread or task is draining the RX completion queue on this endpoint
+ * that thread will reset the rx processing count when the queue is drained */
+ UNLOCK_HTC_RX(target);
+ return;
+ }
+
+ /******* at this point only 1 thread may enter ******/
+
+ while (TRUE) {
+
+ /* transfer items from main recv queue to the local one so we can release the lock */
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&recvCompletions, &pEndpoint->RecvIndicationQueue);
+
+ if (HTC_QUEUE_EMPTY(&recvCompletions)) {
+ /* all drained */
+ break;
+ }
+
+ /* release lock while we do the recv completions
+ * other threads can now queue more recv completions */
+ UNLOCK_HTC_RX(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("DrainRecvIndicationQueue : completing %d RECV packets \n",
+ HTC_PACKET_QUEUE_DEPTH(&recvCompletions)));
+ /* do completion */
+ DO_RCV_COMPLETION(pEndpoint,&recvCompletions);
+
+ /* re-acquire lock to grab some more completions */
+ LOCK_HTC_RX(target);
+ }
+
+ /* reset count */
+ pEndpoint->RxProcessCount = 0;
+ UNLOCK_HTC_RX(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-DrainRecvIndicationQueue \n"));
+
+}
+
+ /* optimization for recv packets, we can indicate a "hint" that there are more
+ * single-packets to fetch on this endpoint */
+#define SET_MORE_RX_PACKET_INDICATION_FLAG(L,N,E,P) \
+ if ((N) > 0) { SetRxPacketIndicationFlags((L)[0],(E),(P)); }
+
+ /* for bundled frames, we can force the flag to indicate there are more packets */
+#define FORCE_MORE_RX_PACKET_INDICATION_FLAG(P) \
+ (P)->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS;
+
+ /* note: this function can be called with the RX lock held */
+static INLINE void SetRxPacketIndicationFlags(A_UINT32 LookAhead,
+ HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET *pPacket)
+{
+ HTC_FRAME_HDR *pHdr = (HTC_FRAME_HDR *)&LookAhead;
+ /* check to see if the "next" packet is from the same endpoint of the
+ completing packet */
+ if (pHdr->EndpointID == pPacket->Endpoint) {
+ /* check that there is a buffer available to actually fetch it */
+ if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) {
+ /* provide a hint that there are more RX packets to fetch */
+ FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+ }
+ }
+}
+
+
+/* asynchronous completion handler for recv packet fetching, when the device layer
+ * completes a read request, it will call this completion handler */
+void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+ HTC_ENDPOINT *pEndpoint;
+ A_UINT32 nextLookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+ int numLookAheads = 0;
+ A_STATUS status;
+ A_BOOL checkMorePkts = TRUE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (pkt:0x%X, status:%d, ep:%d) \n",
+ (A_UINT32)pPacket, pPacket->Status, pPacket->Endpoint));
+
+ A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device));
+ AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+ pEndpoint = &target->EndPoint[pPacket->Endpoint];
+ pPacket->Completion = NULL;
+
+ /* get completion status */
+ status = pPacket->Status;
+
+ do {
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n",
+ pPacket->Status, pPacket->Endpoint));
+ break;
+ }
+ /* process the header for any trailer data */
+ status = HTCProcessRecvHeader(target,pPacket,nextLookAheads,&numLookAheads);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) {
+ /* this packet was part of a bundle that had to be broken up.
+ * It was fetched one message at a time. There may be other asynchronous reads queued behind this one.
+ * Do no issue another check for more packets since the last one in the series of requests
+ * will handle it */
+ checkMorePkts = FALSE;
+ }
+
+ DUMP_RECV_PKT_INFO(pPacket);
+ LOCK_HTC_RX(target);
+ SET_MORE_RX_PACKET_INDICATION_FLAG(nextLookAheads,numLookAheads,pEndpoint,pPacket);
+ /* we have a good packet, queue it to the completion queue */
+ HTC_PACKET_ENQUEUE(&pEndpoint->RecvIndicationQueue,pPacket);
+ HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
+ UNLOCK_HTC_RX(target);
+
+ /* check for more recv packets before indicating */
+ HTCAsyncRecvCheckMorePackets(target,nextLookAheads,numLookAheads,checkMorePkts);
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n",
+ status));
+ /* recycle this packet */
+ HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint);
+ } else {
+ /* a good packet was queued, drain the queue */
+ DrainRecvIndicationQueue(target,pEndpoint);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n"));
+}
+
+/* synchronously wait for a control message from the target,
+ * This function is used at initialization time ONLY. At init messages
+ * on ENDPOINT 0 are expected. */
+A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
+{
+ A_STATUS status;
+ A_UINT32 lookAhead;
+ HTC_PACKET *pPacket = NULL;
+ HTC_FRAME_HDR *pHdr;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n"));
+
+ do {
+
+ *ppControlPacket = NULL;
+
+ /* call the polling function to see if we have a message */
+ status = DevPollMboxMsgRecv(&target->Device,
+ &lookAhead,
+ HTC_TARGET_RESPONSE_TIMEOUT);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead));
+
+ /* check the lookahead */
+ pHdr = (HTC_FRAME_HDR *)&lookAhead;
+
+ if (pHdr->EndpointID != ENDPOINT_0) {
+ /* unexpected endpoint number, should be zero */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ /* bad message */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ pPacket = HTC_ALLOC_CONTROL_RX(target);
+
+ if (pPacket == NULL) {
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ pPacket->PktInfo.AsRx.HTCRxFlags = 0;
+ pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead;
+ pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+
+ if (pPacket->ActualLength > pPacket->BufferLength) {
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ /* we want synchronous operation */
+ pPacket->Completion = NULL;
+
+ /* get the message from the device, this will block */
+ status = HTCIssueRecv(target, pPacket);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* process receive header */
+ status = HTCProcessRecvHeader(target,pPacket,NULL,NULL);
+
+ pPacket->Status = status;
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n",
+ status));
+ break;
+ }
+
+ /* give the caller this control message packet, they are responsible to free */
+ *ppControlPacket = pPacket;
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ if (pPacket != NULL) {
+ /* cleanup buffer on error */
+ HTC_FREE_CONTROL_RX(target,pPacket);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n"));
+
+ return status;
+}
+
+static A_STATUS AllocAndPrepareRxPackets(HTC_TARGET *target,
+ A_UINT32 LookAheads[],
+ int Messages,
+ HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET_QUEUE *pQueue)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pPacket;
+ HTC_FRAME_HDR *pHdr;
+ int i,j;
+ int numMessages;
+ int fullLength;
+ A_BOOL noRecycle;
+
+ /* lock RX while we assemble the packet buffers */
+ LOCK_HTC_RX(target);
+
+ for (i = 0; i < Messages; i++) {
+
+ pHdr = (HTC_FRAME_HDR *)&LookAheads[i];
+
+ if (pHdr->EndpointID >= ENDPOINT_MAX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID));
+ /* invalid endpoint */
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pHdr->EndpointID != pEndpoint->Id) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d should be : %d (index:%d)\n",
+ pHdr->EndpointID, pEndpoint->Id, i));
+ /* invalid endpoint */
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
+ pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH));
+ status = A_EPROTO;
+ break;
+ }
+
+ if (0 == pEndpoint->ServiceID) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID));
+ /* endpoint isn't even connected */
+ status = A_EPROTO;
+ break;
+ }
+
+ if ((pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) == 0) {
+ /* HTC header only indicates 1 message to fetch */
+ numMessages = 1;
+ } else {
+ /* HTC header indicates that every packet to follow has the same padded length so that it can
+ * be optimally fetched as a full bundle */
+ numMessages = (pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT;
+ /* the count doesn't include the starter frame, just a count of frames to follow */
+ numMessages++;
+ A_ASSERT(numMessages <= target->MaxMsgPerBundle);
+ INC_HTC_EP_STAT(pEndpoint, RxBundleIndFromHdr, 1);
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTC header indicates :%d messages can be fetched as a bundle \n",numMessages));
+ }
+
+ fullLength = DEV_CALC_RECV_PADDED_LEN(&target->Device,pHdr->PayloadLen + sizeof(HTC_FRAME_HDR));
+
+ /* get packet buffers for each message, if there was a bundle detected in the header,
+ * use pHdr as a template to fetch all packets in the bundle */
+ for (j = 0; j < numMessages; j++) {
+
+ /* reset flag, any packets allocated using the RecvAlloc() API cannot be recycled on cleanup,
+ * they must be explicitly returned */
+ noRecycle = FALSE;
+
+ if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) {
+ UNLOCK_HTC_RX(target);
+ noRecycle = TRUE;
+ /* user is using a per-packet allocation callback */
+ pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext,
+ pEndpoint->Id,
+ fullLength);
+ LOCK_HTC_RX(target);
+
+ } else if ((pEndpoint->EpCallBacks.EpRecvAllocThresh != NULL) &&
+ (fullLength > pEndpoint->EpCallBacks.RecvAllocThreshold)) {
+ INC_HTC_EP_STAT(pEndpoint,RxAllocThreshHit,1);
+ INC_HTC_EP_STAT(pEndpoint,RxAllocThreshBytes,pHdr->PayloadLen);
+ /* threshold was hit, call the special recv allocation callback */
+ UNLOCK_HTC_RX(target);
+ noRecycle = TRUE;
+ /* user wants to allocate packets above a certain threshold */
+ pPacket = pEndpoint->EpCallBacks.EpRecvAllocThresh(pEndpoint->EpCallBacks.pContext,
+ pEndpoint->Id,
+ fullLength);
+ LOCK_HTC_RX(target);
+
+ } else {
+ /* user is using a refill handler that can refill multiple HTC buffers */
+
+ /* get a packet from the endpoint recv queue */
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+
+ if (NULL == pPacket) {
+ /* check for refill handler */
+ if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) {
+ UNLOCK_HTC_RX(target);
+ /* call the re-fill handler */
+ pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+ pEndpoint->Id);
+ LOCK_HTC_RX(target);
+ /* check if we have more buffers */
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+ /* fall through */
+ }
+ }
+ }
+
+ if (NULL == pPacket) {
+ /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+ target->RecvStateFlags |= HTC_RECV_WAIT_BUFFERS;
+ target->EpWaitingForBuffers = pEndpoint->Id;
+ status = A_NO_RESOURCE;
+ break;
+ }
+
+ AR_DEBUG_ASSERT(pPacket->Endpoint == pEndpoint->Id);
+ /* clear flags */
+ pPacket->PktInfo.AsRx.HTCRxFlags = 0;
+ pPacket->PktInfo.AsRx.IndicationFlags = 0;
+ pPacket->Status = A_OK;
+
+ if (noRecycle) {
+ /* flag that these packets cannot be recycled, they have to be returned to the
+ * user */
+ pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_NO_RECYCLE;
+ }
+ /* add packet to queue (also incase we need to cleanup down below) */
+ HTC_PACKET_ENQUEUE(pQueue,pPacket);
+
+ if (HTC_STOPPING(target)) {
+ status = A_ECANCELED;
+ break;
+ }
+
+ /* make sure this message can fit in the endpoint buffer */
+ if ((A_UINT32)fullLength > pPacket->BufferLength) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Payload Length Error : header reports payload of: %d (%d) endpoint buffer size: %d \n",
+ pHdr->PayloadLen, fullLength, pPacket->BufferLength));
+ status = A_EPROTO;
+ break;
+ }
+
+ if (j > 0) {
+ /* for messages fetched in a bundle the expected lookahead is unknown since we
+ * are only using the lookahead of the first packet as a template of what to
+ * expect for lengths */
+ /* flag that once we get the real HTC header we need to refesh the information */
+ pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_REFRESH_HDR;
+ /* set it to something invalid */
+ pPacket->PktInfo.AsRx.ExpectedHdr = 0xFFFFFFFF;
+ } else {
+
+ pPacket->PktInfo.AsRx.ExpectedHdr = LookAheads[i]; /* set expected look ahead */
+ }
+ /* set the amount of data to fetch */
+ pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+ }
+
+ if (A_FAILED(status)) {
+ if (A_NO_RESOURCE == status) {
+ /* this is actually okay */
+ status = A_OK;
+ }
+ break;
+ }
+
+ }
+
+ UNLOCK_HTC_RX(target);
+
+ if (A_FAILED(status)) {
+ while (!HTC_QUEUE_EMPTY(pQueue)) {
+ pPacket = HTC_PACKET_DEQUEUE(pQueue);
+ /* recycle all allocated packets */
+ HTC_RECYCLE_RX_PKT(target,pPacket,&target->EndPoint[pPacket->Endpoint]);
+ }
+ }
+
+ return status;
+}
+
+static void HTCAsyncRecvScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
+{
+ int i;
+ HTC_PACKET *pPacket;
+ HTC_ENDPOINT *pEndpoint;
+ A_UINT32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+ int numLookAheads = 0;
+ HTC_TARGET *target = (HTC_TARGET *)pScatterReq->Context;
+ A_STATUS status;
+ A_BOOL partialBundle = FALSE;
+ HTC_PACKET_QUEUE localRecvQueue;
+ A_BOOL procError = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCAsyncRecvScatterCompletion TotLen: %d Entries: %d\n",
+ pScatterReq->TotalLength, pScatterReq->ValidScatterEntries));
+
+ A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device));
+
+ if (A_FAILED(pScatterReq->CompletionStatus)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Recv Scatter Request Failed: %d \n",pScatterReq->CompletionStatus));
+ }
+
+ if (pScatterReq->CallerFlags & HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE) {
+ partialBundle = TRUE;
+ }
+
+ DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+
+ INIT_HTC_PACKET_QUEUE(&localRecvQueue);
+
+ pPacket = (HTC_PACKET *)pScatterReq->ScatterList[0].pCallerContexts[0];
+ /* note: all packets in a scatter req are for the same endpoint ! */
+ pEndpoint = &target->EndPoint[pPacket->Endpoint];
+
+ /* walk through the scatter list and process */
+ /* **** NOTE: DO NOT HOLD ANY LOCKS here, HTCProcessRecvHeader can take the TX lock
+ * as it processes credit reports */
+ for (i = 0; i < pScatterReq->ValidScatterEntries; i++) {
+ pPacket = (HTC_PACKET *)pScatterReq->ScatterList[i].pCallerContexts[0];
+ A_ASSERT(pPacket != NULL);
+ /* reset count, we are only interested in the look ahead in the last packet when we
+ * break out of this loop */
+ numLookAheads = 0;
+
+ if (A_SUCCESS(pScatterReq->CompletionStatus)) {
+ /* process header for each of the recv packets */
+ status = HTCProcessRecvHeader(target,pPacket,lookAheads,&numLookAheads);
+ } else {
+ status = A_ERROR;
+ }
+
+ if (A_SUCCESS(status)) {
+#ifdef HTC_EP_STAT_PROFILING
+ LOCK_HTC_RX(target);
+ HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
+ INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
+ UNLOCK_HTC_RX(target);
+#endif
+ if (i == (pScatterReq->ValidScatterEntries - 1)) {
+ /* last packet's more packets flag is set based on the lookahead */
+ SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,numLookAheads,pEndpoint,pPacket);
+ } else {
+ /* packets in a bundle automatically have this flag set */
+ FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+ }
+
+ DUMP_RECV_PKT_INFO(pPacket);
+ /* since we can't hold a lock in this loop, we insert into our local recv queue for
+ * storage until we can transfer them to the recv completion queue */
+ HTC_PACKET_ENQUEUE(&localRecvQueue,pPacket);
+
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Recv packet scatter entry %d failed (out of %d) \n",
+ i, pScatterReq->ValidScatterEntries));
+ /* recycle failed recv */
+ HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint);
+ /* set flag and continue processing the remaining scatter entries */
+ procError = TRUE;
+ }
+
+ }
+
+ /* free scatter request */
+ DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+
+ LOCK_HTC_RX(target);
+ /* transfer the packets in the local recv queue to the recv completion queue */
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RecvIndicationQueue, &localRecvQueue);
+
+ UNLOCK_HTC_RX(target);
+
+ if (!procError) {
+ /* pipeline the next check (asynchronously) for more packets */
+ HTCAsyncRecvCheckMorePackets(target,
+ lookAheads,
+ numLookAheads,
+ partialBundle ? FALSE : TRUE);
+ }
+
+ /* now drain the indication queue */
+ DrainRecvIndicationQueue(target,pEndpoint);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCAsyncRecvScatterCompletion \n"));
+}
+
+static A_STATUS HTCIssueRecvPacketBundle(HTC_TARGET *target,
+ HTC_PACKET_QUEUE *pRecvPktQueue,
+ HTC_PACKET_QUEUE *pSyncCompletionQueue,
+ int *pNumPacketsFetched,
+ A_BOOL PartialBundle)
+{
+ A_STATUS status = A_OK;
+ HIF_SCATTER_REQ *pScatterReq;
+ int i, totalLength;
+ int pktsToScatter;
+ HTC_PACKET *pPacket;
+ A_BOOL asyncMode = (pSyncCompletionQueue == NULL) ? TRUE : FALSE;
+ int scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device);
+
+ pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue);
+ pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle);
+
+ if ((HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue) - pktsToScatter) > 0) {
+ /* we were forced to split this bundle receive operation
+ * all packets in this partial bundle must have their lookaheads ignored */
+ PartialBundle = TRUE;
+ /* this would only happen if the target ignored our max bundle limit */
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ ("HTCIssueRecvPacketBundle : partial bundle detected num:%d , %d \n",
+ HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter));
+ }
+
+ totalLength = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCIssueRecvPacketBundle (Numpackets: %d , actual : %d) \n",
+ HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter));
+
+ do {
+
+ pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device);
+
+ if (pScatterReq == NULL) {
+ /* no scatter resources left, just let caller handle it the legacy way */
+ break;
+ }
+
+ pScatterReq->CallerFlags = 0;
+
+ if (PartialBundle) {
+ /* mark that this is a partial bundle, this has special ramifications to the
+ * scatter completion routine */
+ pScatterReq->CallerFlags |= HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE;
+ }
+
+ /* convert HTC packets to scatter list */
+ for (i = 0; i < pktsToScatter; i++) {
+ int paddedLength;
+
+ pPacket = HTC_PACKET_DEQUEUE(pRecvPktQueue);
+ A_ASSERT(pPacket != NULL);
+
+ paddedLength = DEV_CALC_RECV_PADDED_LEN(&target->Device, pPacket->ActualLength);
+
+ if ((scatterSpaceRemaining - paddedLength) < 0) {
+ /* exceeds what we can transfer, put the packet back */
+ HTC_PACKET_ENQUEUE_TO_HEAD(pRecvPktQueue,pPacket);
+ break;
+ }
+
+ scatterSpaceRemaining -= paddedLength;
+
+ if (PartialBundle || (i < (pktsToScatter - 1))) {
+ /* packet 0..n-1 cannot be checked for look-aheads since we are fetching a bundle
+ * the last packet however can have it's lookahead used */
+ pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD;
+ }
+
+ /* note: 1 HTC packet per scatter entry */
+ /* setup packet into */
+ pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer;
+ pScatterReq->ScatterList[i].Length = paddedLength;
+
+ pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_PART_OF_BUNDLE;
+
+ if (asyncMode) {
+ /* save HTC packet for async completion routine */
+ pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket;
+ } else {
+ /* queue to caller's sync completion queue, caller will unload this when we return */
+ HTC_PACKET_ENQUEUE(pSyncCompletionQueue,pPacket);
+ }
+
+ A_ASSERT(pScatterReq->ScatterList[i].Length);
+ totalLength += pScatterReq->ScatterList[i].Length;
+ }
+
+ pScatterReq->TotalLength = totalLength;
+ pScatterReq->ValidScatterEntries = i;
+
+ if (asyncMode) {
+ pScatterReq->CompletionRoutine = HTCAsyncRecvScatterCompletion;
+ pScatterReq->Context = target;
+ }
+
+ status = DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_READ, asyncMode);
+
+ if (A_SUCCESS(status)) {
+ *pNumPacketsFetched = i;
+ }
+
+ if (!asyncMode) {
+ /* free scatter request */
+ DEV_FREE_SCATTER_REQ(&target->Device, pScatterReq);
+ }
+
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCIssueRecvPacketBundle (status:%d) (fetched:%d) \n",
+ status,*pNumPacketsFetched));
+
+ return status;
+}
+
+static INLINE void CheckRecvWaterMark(HTC_ENDPOINT *pEndpoint)
+{
+ /* see if endpoint is using a refill watermark
+ * ** no need to use a lock here, since we are only inspecting...
+ * caller may must not hold locks when calling this function */
+ if (pEndpoint->EpCallBacks.RecvRefillWaterMark > 0) {
+ if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->RxBuffers) < pEndpoint->EpCallBacks.RecvRefillWaterMark) {
+ /* call the re-fill handler before we continue */
+ pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+ pEndpoint->Id);
+ }
+ }
+}
+
+/* callback when device layer or lookahead report parsing detects a pending message */
+A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+ A_STATUS status = A_OK;
+ HTC_PACKET *pPacket;
+ HTC_ENDPOINT *pEndpoint;
+ A_BOOL asyncProc = FALSE;
+ A_UINT32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE];
+ int pktsFetched;
+ HTC_PACKET_QUEUE recvPktQueue, syncCompletedPktsQueue;
+ A_BOOL partialBundle;
+ HTC_ENDPOINT_ID id;
+ int totalFetched = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler NumLookAheads: %d \n",NumLookAheads));
+
+ if (pNumPktsFetched != NULL) {
+ *pNumPktsFetched = 0;
+ }
+
+ if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) {
+ /* We use async mode to get the packets if the device layer supports it.
+ * The device layer interfaces with HIF in which HIF may have restrictions on
+ * how interrupts are processed */
+ asyncProc = TRUE;
+ }
+
+ if (pAsyncProc != NULL) {
+ /* indicate to caller how we decided to process this */
+ *pAsyncProc = asyncProc;
+ }
+
+ if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) {
+ A_ASSERT(FALSE);
+ return A_EPROTO;
+ }
+
+ /* on first entry copy the lookaheads into our temp array for processing */
+ A_MEMCPY(lookAheads, MsgLookAheads, (sizeof(A_UINT32)) * NumLookAheads);
+
+ while (TRUE) {
+
+ /* reset packets queues */
+ INIT_HTC_PACKET_QUEUE(&recvPktQueue);
+ INIT_HTC_PACKET_QUEUE(&syncCompletedPktsQueue);
+
+ if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) {
+ status = A_EPROTO;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ /* first lookahead sets the expected endpoint IDs for all packets in a bundle */
+ id = ((HTC_FRAME_HDR *)&lookAheads[0])->EndpointID;
+ pEndpoint = &target->EndPoint[id];
+
+ if (id >= ENDPOINT_MAX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MsgPend, Invalid Endpoint in look-ahead: %d \n",id));
+ status = A_EPROTO;
+ break;
+ }
+
+ /* try to allocate as many HTC RX packets indicated by the lookaheads
+ * these packets are stored in the recvPkt queue */
+ status = AllocAndPrepareRxPackets(target,
+ lookAheads,
+ NumLookAheads,
+ pEndpoint,
+ &recvPktQueue);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) >= 2) {
+ /* a recv bundle was detected, force IRQ status re-check again */
+ REF_IRQ_STATUS_RECHECK(&target->Device);
+ }
+
+ totalFetched += HTC_PACKET_QUEUE_DEPTH(&recvPktQueue);
+
+ /* we've got packet buffers for all we can currently fetch,
+ * this count is not valid anymore */
+ NumLookAheads = 0;
+ partialBundle = FALSE;
+
+ /* now go fetch the list of HTC packets */
+ while (!HTC_QUEUE_EMPTY(&recvPktQueue)) {
+
+ pktsFetched = 0;
+
+ if (target->RecvBundlingEnabled && (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 1)) {
+ /* there are enough packets to attempt a bundle transfer and recv bundling is allowed */
+ status = HTCIssueRecvPacketBundle(target,
+ &recvPktQueue,
+ asyncProc ? NULL : &syncCompletedPktsQueue,
+ &pktsFetched,
+ partialBundle);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) != 0) {
+ /* we couldn't fetch all packets at one time, this creates a broken
+ * bundle */
+ partialBundle = TRUE;
+ }
+ }
+
+ /* see if the previous operation fetched any packets using bundling */
+ if (0 == pktsFetched) {
+ /* dequeue one packet */
+ pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue);
+ A_ASSERT(pPacket != NULL);
+
+ if (asyncProc) {
+ /* we use async mode to get the packet if the device layer supports it
+ * set our callback and context */
+ pPacket->Completion = HTCRecvCompleteHandler;
+ pPacket->pContext = target;
+ } else {
+ /* fully synchronous */
+ pPacket->Completion = NULL;
+ }
+
+ if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 0) {
+ /* lookaheads in all packets except the last one in the bundle must be ignored */
+ pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD;
+ }
+
+ /* go fetch the packet */
+ status = HTCIssueRecv(target, pPacket);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (!asyncProc) {
+ /* sent synchronously, queue this packet for synchronous completion */
+ HTC_PACKET_ENQUEUE(&syncCompletedPktsQueue,pPacket);
+ }
+
+ }
+
+ }
+
+ if (A_SUCCESS(status)) {
+ CheckRecvWaterMark(pEndpoint);
+ }
+
+ if (asyncProc) {
+ /* we did this asynchronously so we can get out of the loop, the asynch processing
+ * creates a chain of requests to continue processing pending messages in the
+ * context of callbacks */
+ break;
+ }
+
+ /* synchronous handling */
+ if (target->Device.DSRCanYield) {
+ /* for the SYNC case, increment count that tracks when the DSR should yield */
+ target->Device.CurrentDSRRecvCount++;
+ }
+
+ /* in the sync case, all packet buffers are now filled,
+ * we can process each packet, check lookaheads and then repeat */
+
+ /* unload sync completion queue */
+ while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+ HTC_PACKET_QUEUE container;
+
+ pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue);
+ A_ASSERT(pPacket != NULL);
+
+ pEndpoint = &target->EndPoint[pPacket->Endpoint];
+ /* reset count on each iteration, we are only interested in the last packet's lookahead
+ * information when we break out of this loop */
+ NumLookAheads = 0;
+ /* process header for each of the recv packets
+ * note: the lookahead of the last packet is useful for us to continue in this loop */
+ status = HTCProcessRecvHeader(target,pPacket,lookAheads,&NumLookAheads);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+ /* last packet's more packets flag is set based on the lookahead */
+ SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,NumLookAheads,pEndpoint,pPacket);
+ } else {
+ /* packets in a bundle automatically have this flag set */
+ FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket);
+ }
+ /* good packet, indicate it */
+ HTC_RX_STAT_PROFILE(target,pEndpoint,NumLookAheads);
+
+ if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_PART_OF_BUNDLE) {
+ INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
+ }
+
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+ DO_RCV_COMPLETION(pEndpoint,&container);
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (NumLookAheads == 0) {
+ /* no more look aheads */
+ break;
+ }
+
+ /* when we process recv synchronously we need to check if we should yield and stop
+ * fetching more packets indicated by the embedded lookaheads */
+ if (target->Device.DSRCanYield) {
+ if (DEV_CHECK_RECV_YIELD(&target->Device)) {
+ /* break out, don't fetch any more packets */
+ break;
+ }
+ }
+
+
+ /* check whether other OS contexts have queued any WMI command/data for WLAN.
+ * This check is needed only if WLAN Tx and Rx happens in same thread context */
+ A_CHECK_DRV_TX();
+
+ /* for SYNCH processing, if we get here, we are running through the loop again due to a detected lookahead.
+ * Set flag that we should re-check IRQ status registers again before leaving IRQ processing,
+ * this can net better performance in high throughput situations */
+ REF_IRQ_STATUS_RECHECK(&target->Device);
+ }
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Failed to get pending recv messages (%d) \n",status));
+ /* cleanup any packets we allocated but didn't use to actually fetch any packets */
+ while (!HTC_QUEUE_EMPTY(&recvPktQueue)) {
+ pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue);
+ /* clean up packets */
+ HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]);
+ }
+ /* cleanup any packets in sync completion queue */
+ while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) {
+ pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue);
+ /* clean up packets */
+ HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]);
+ }
+ }
+
+ /* before leaving, check to see if host ran out of buffers and needs to stop the
+ * receiver */
+ if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ (" Host has no RX buffers, blocking receiver to prevent overrun.. \n"));
+ /* try to stop receive at the device layer */
+ DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
+ }
+
+ if (pNumPktsFetched != NULL) {
+ *pNumPktsFetched = totalFetched;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n"));
+
+ return status;
+}
+
+A_STATUS HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint;
+ A_BOOL unblockRecv = FALSE;
+ A_STATUS status = A_OK;
+ HTC_PACKET *pFirstPacket;
+
+ pFirstPacket = HTC_GET_PKT_AT_HEAD(pPktQueue);
+
+ if (NULL == pFirstPacket) {
+ A_ASSERT(FALSE);
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_ASSERT(pFirstPacket->Endpoint < ENDPOINT_MAX);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("+- HTCAddReceivePktMultiple : endPointId: %d, cnt:%d, length: %d\n",
+ pFirstPacket->Endpoint,
+ HTC_PACKET_QUEUE_DEPTH(pPktQueue),
+ pFirstPacket->BufferLength));
+
+ do {
+
+ pEndpoint = &target->EndPoint[pFirstPacket->Endpoint];
+
+ LOCK_HTC_RX(target);
+
+ if (HTC_STOPPING(target)) {
+ HTC_PACKET *pPacket;
+
+ UNLOCK_HTC_RX(target);
+
+ /* walk through queue and mark each one canceled */
+ HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) {
+ pPacket->Status = A_ECANCELED;
+ } HTC_PACKET_QUEUE_ITERATE_END;
+
+ DO_RCV_COMPLETION(pEndpoint,pPktQueue);
+ break;
+ }
+
+ /* store receive packets */
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RxBuffers, pPktQueue);
+
+ /* check if we are blocked waiting for a new buffer */
+ if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+ if (target->EpWaitingForBuffers == pFirstPacket->Endpoint) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n",
+ target->EpWaitingForBuffers));
+ target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS;
+ target->EpWaitingForBuffers = ENDPOINT_MAX;
+ unblockRecv = TRUE;
+ }
+ }
+
+ UNLOCK_HTC_RX(target);
+
+ if (unblockRecv && !HTC_STOPPING(target)) {
+ /* TODO : implement a buffer threshold count? */
+ DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+/* Makes a buffer available to the HTC module */
+A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+ HTC_PACKET_QUEUE queue;
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket);
+ return HTCAddReceivePktMultiple(HTCHandle, &queue);
+}
+
+void HTCUnblockRecv(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_BOOL unblockRecv = FALSE;
+
+ LOCK_HTC_RX(target);
+
+ /* check if we are blocked waiting for a new buffer */
+ if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n",
+ target->EpWaitingForBuffers));
+ target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS;
+ target->EpWaitingForBuffers = ENDPOINT_MAX;
+ unblockRecv = TRUE;
+ }
+
+ UNLOCK_HTC_RX(target);
+
+ if (unblockRecv && !HTC_STOPPING(target)) {
+ /* re-enable */
+ DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC);
+ }
+}
+
+static void HTCFlushRxQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET_QUEUE *pQueue)
+{
+ HTC_PACKET *pPacket;
+ HTC_PACKET_QUEUE container;
+
+ LOCK_HTC_RX(target);
+
+ while (1) {
+ pPacket = HTC_PACKET_DEQUEUE(pQueue);
+ if (NULL == pPacket) {
+ break;
+ }
+ UNLOCK_HTC_RX(target);
+ pPacket->Status = A_ECANCELED;
+ pPacket->ActualLength = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n",
+ (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint));
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+ /* give the packet back */
+ DO_RCV_COMPLETION(pEndpoint,&container);
+ LOCK_HTC_RX(target);
+ }
+
+ UNLOCK_HTC_RX(target);
+}
+
+static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+ /* flush any recv indications not already made */
+ HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RecvIndicationQueue);
+ /* flush any rx buffers */
+ HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RxBuffers);
+}
+
+void HTCFlushRecvBuffers(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ int i;
+
+ for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+ pEndpoint = &target->EndPoint[i];
+ if (pEndpoint->ServiceID == 0) {
+ /* not in use.. */
+ continue;
+ }
+ HTCFlushEndpointRX(target,pEndpoint);
+ }
+}
+
+
+void HTCEnableRecv(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+ if (!HTC_STOPPING(target)) {
+ /* re-enable */
+ DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+ }
+}
+
+void HTCDisableRecv(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+ if (!HTC_STOPPING(target)) {
+ /* disable */
+ DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+ }
+}
+
+int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ return HTC_PACKET_QUEUE_DEPTH(&(target->EndPoint[Endpoint].RxBuffers));
+}
+
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_send.c b/drivers/net/wireless/ath6kl/htc2/htc_send.c
new file mode 100644
index 000000000000..13eef67aaeaf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_send.c
@@ -0,0 +1,1019 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_send.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+typedef enum _HTC_SEND_QUEUE_RESULT {
+ HTC_SEND_QUEUE_OK = 0, /* packet was queued */
+ HTC_SEND_QUEUE_DROP = 1, /* this packet should be dropped */
+} HTC_SEND_QUEUE_RESULT;
+
+#define DO_EP_TX_COMPLETION(ep,q) DoSendCompletion(ep,q)
+
+/* call the distribute credits callback with the distribution */
+#define DO_DISTRIBUTION(t,reason,description,pList) \
+{ \
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \
+ (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \
+ (description), \
+ (A_UINT32)(t)->DistributeCredits, \
+ (A_UINT32)(t)->pCredDistContext, \
+ (A_UINT32)pList)); \
+ (t)->DistributeCredits((t)->pCredDistContext, \
+ (pList), \
+ (reason)); \
+}
+
+static void DoSendCompletion(HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET_QUEUE *pQueueToIndicate)
+{
+ do {
+
+ if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
+ /* nothing to indicate */
+ break;
+ }
+
+ if (pEndpoint->EpCallBacks.EpTxCompleteMultiple != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d, send complete multiple callback (%d pkts) \n",
+ pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate)));
+ /* a multiple send complete handler is being used, pass the queue to the handler */
+ pEndpoint->EpCallBacks.EpTxCompleteMultiple(pEndpoint->EpCallBacks.pContext,
+ pQueueToIndicate);
+ /* all packets are now owned by the callback, reset queue to be safe */
+ INIT_HTC_PACKET_QUEUE(pQueueToIndicate);
+ } else {
+ HTC_PACKET *pPacket;
+ /* using legacy EpTxComplete */
+ do {
+ pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate);
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d send complete callback on packet 0x%X \n", \
+ pEndpoint->Id, (A_UINT32)(pPacket)));
+ pEndpoint->EpCallBacks.EpTxComplete(pEndpoint->EpCallBacks.pContext, pPacket);
+ } while (!HTC_QUEUE_EMPTY(pQueueToIndicate));
+ }
+
+ } while (FALSE);
+
+}
+
+/* do final completion on sent packet */
+static INLINE void CompleteSentPacket(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET *pPacket)
+{
+ pPacket->Completion = NULL;
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("CompleteSentPacket: request failed (status:%d, ep:%d, length:%d creds:%d) \n",
+ pPacket->Status, pPacket->Endpoint, pPacket->ActualLength, pPacket->PktInfo.AsTx.CreditsUsed));
+ /* on failure to submit, reclaim credits for this packet */
+ LOCK_HTC_TX(target);
+ pEndpoint->CreditDist.TxCreditsToDist += pPacket->PktInfo.AsTx.CreditsUsed;
+ pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_SEND_COMPLETE,
+ "Send Complete",
+ target->EpCreditDistributionListHead->pNext);
+ UNLOCK_HTC_TX(target);
+ }
+ /* first, fixup the head room we allocated */
+ pPacket->pBuffer += HTC_HDR_LENGTH;
+}
+
+/* our internal send packet completion handler when packets are submited to the AR6K device
+ * layer */
+static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint];
+ HTC_PACKET_QUEUE container;
+
+ CompleteSentPacket(target,pEndpoint,pPacket);
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+ /* do completion */
+ DO_EP_TX_COMPLETION(pEndpoint,&container);
+}
+
+A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket)
+{
+ A_STATUS status;
+ A_BOOL sync = FALSE;
+
+ if (pPacket->Completion == NULL) {
+ /* mark that this request was synchronously issued */
+ sync = TRUE;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("+-HTCIssueSend: transmit length : %d (%s) \n",
+ pPacket->ActualLength + HTC_HDR_LENGTH,
+ sync ? "SYNC" : "ASYNC" ));
+
+ /* send message to device */
+ status = DevSendPacket(&target->Device,
+ pPacket,
+ pPacket->ActualLength + HTC_HDR_LENGTH);
+
+ if (sync) {
+ /* use local sync variable. If this was issued asynchronously, pPacket is no longer
+ * safe to access. */
+ pPacket->pBuffer += HTC_HDR_LENGTH;
+ }
+
+ /* if this request was asynchronous, the packet completion routine will be invoked by
+ * the device layer when the HIF layer completes the request */
+
+ return status;
+}
+
+ /* get HTC send packets from the TX queue on an endpoint */
+static INLINE void GetHTCSendPackets(HTC_TARGET *target,
+ HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET_QUEUE *pQueue)
+{
+ int creditsRequired;
+ int remainder;
+ A_UINT8 sendFlags;
+ HTC_PACKET *pPacket;
+ unsigned int transferLength;
+
+ /****** NOTE : the TX lock is held when this function is called *****************/
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+GetHTCSendPackets \n"));
+
+ /* loop until we can grab as many packets out of the queue as we can */
+ while (TRUE) {
+
+ sendFlags = 0;
+ /* get packet at head, but don't remove it */
+ pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue);
+ if (pPacket == NULL) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n",
+ (A_UINT32)pPacket, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
+
+ transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, pPacket->ActualLength + HTC_HDR_LENGTH);
+
+ if (transferLength <= target->TargetCreditSize) {
+ creditsRequired = 1;
+ } else {
+ /* figure out how many credits this message requires */
+ creditsRequired = transferLength / target->TargetCreditSize;
+ remainder = transferLength % target->TargetCreditSize;
+
+ if (remainder) {
+ creditsRequired++;
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n",
+ creditsRequired, pEndpoint->CreditDist.TxCredits));
+
+ if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+
+ /* not enough credits */
+ if (pPacket->Endpoint == ENDPOINT_0) {
+ /* leave it in the queue */
+ break;
+ }
+ /* invoke the registered distribution function only if this is not
+ * endpoint 0, we let the driver layer provide more credits if it can.
+ * We pass the credit distribution list starting at the endpoint in question
+ * */
+
+ /* set how many credits we need */
+ pEndpoint->CreditDist.TxCreditsSeek =
+ creditsRequired - pEndpoint->CreditDist.TxCredits;
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_SEEK_CREDITS,
+ "Seek Credits",
+ &pEndpoint->CreditDist);
+ pEndpoint->CreditDist.TxCreditsSeek = 0;
+
+ if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+ /* still not enough credits to send, leave packet in the queue */
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ (" Not enough credits for ep %d leaving packet in queue..\n",
+ pPacket->Endpoint));
+ break;
+ }
+
+ }
+
+ pEndpoint->CreditDist.TxCredits -= creditsRequired;
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired);
+
+ /* check if we need credits back from the target */
+ if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+ /* we are getting low on credits, see if we can ask for more from the distribution function */
+ pEndpoint->CreditDist.TxCreditsSeek =
+ pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits;
+
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_SEEK_CREDITS,
+ "Seek Credits",
+ &pEndpoint->CreditDist);
+
+ pEndpoint->CreditDist.TxCreditsSeek = 0;
+ /* see if we were successful in getting more */
+ if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+ /* tell the target we need credits ASAP! */
+ sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
+ INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1);
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n"));
+ }
+ }
+
+ /* now we can fully dequeue */
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue);
+ /* save the number of credits this packet consumed */
+ pPacket->PktInfo.AsTx.CreditsUsed = creditsRequired;
+ /* all TX packets are handled asynchronously */
+ pPacket->Completion = HTCSendPktCompletionHandler;
+ pPacket->pContext = target;
+ INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
+ /* save send flags */
+ pPacket->PktInfo.AsTx.SendFlags = sendFlags;
+ pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo;
+ pEndpoint->SeqNo++;
+ /* queue this packet into the caller's queue */
+ HTC_PACKET_ENQUEUE(pQueue,pPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-GetHTCSendPackets \n"));
+
+}
+
+static void HTCAsyncSendScatterCompletion(HIF_SCATTER_REQ *pScatterReq)
+{
+ int i;
+ HTC_PACKET *pPacket;
+ HTC_ENDPOINT *pEndpoint = (HTC_ENDPOINT *)pScatterReq->Context;
+ HTC_TARGET *target = (HTC_TARGET *)pEndpoint->target;
+ A_STATUS status = A_OK;
+ HTC_PACKET_QUEUE sendCompletes;
+
+ INIT_HTC_PACKET_QUEUE(&sendCompletes);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCAsyncSendScatterCompletion TotLen: %d Entries: %d\n",
+ pScatterReq->TotalLength, pScatterReq->ValidScatterEntries));
+
+ DEV_FINISH_SCATTER_OPERATION(pScatterReq);
+
+ if (A_FAILED(pScatterReq->CompletionStatus)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Send Scatter Request Failed: %d \n",pScatterReq->CompletionStatus));
+ status = A_ERROR;
+ }
+
+ /* walk through the scatter list and process */
+ for (i = 0; i < pScatterReq->ValidScatterEntries; i++) {
+ pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]);
+ A_ASSERT(pPacket != NULL);
+ pPacket->Status = status;
+ CompleteSentPacket(target,pEndpoint,pPacket);
+ /* add it to the completion queue */
+ HTC_PACKET_ENQUEUE(&sendCompletes, pPacket);
+ }
+
+ /* free scatter request */
+ DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+ /* complete all packets */
+ DO_EP_TX_COMPLETION(pEndpoint,&sendCompletes);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCAsyncSendScatterCompletion \n"));
+}
+
+ /* drain a queue and send as bundles
+ * this function may return without fully draining the queue under the following conditions :
+ * - scatter resources are exhausted
+ * - a message that will consume a partial credit will stop the bundling process early
+ * - we drop below the minimum number of messages for a bundle
+ * */
+static void HTCIssueSendBundle(HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET_QUEUE *pQueue,
+ int *pBundlesSent,
+ int *pTotalBundlesPkts)
+{
+ int pktsToScatter;
+ unsigned int scatterSpaceRemaining;
+ HIF_SCATTER_REQ *pScatterReq = NULL;
+ int i, packetsInScatterReq;
+ unsigned int transferLength;
+ HTC_PACKET *pPacket;
+ A_BOOL done = FALSE;
+ int bundlesSent = 0;
+ int totalPktsInBundle = 0;
+ HTC_TARGET *target = pEndpoint->target;
+ int creditRemainder = 0;
+ int creditPad;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCIssueSendBundle \n"));
+
+ while (!done) {
+
+ pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pQueue);
+ pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle);
+
+ if (pktsToScatter < HTC_MIN_HTC_MSGS_TO_BUNDLE) {
+ /* not enough to bundle */
+ break;
+ }
+
+ pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device);
+
+ if (pScatterReq == NULL) {
+ /* no scatter resources */
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" No more scatter resources \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" pkts to scatter: %d \n", pktsToScatter));
+
+ pScatterReq->TotalLength = 0;
+ pScatterReq->ValidScatterEntries = 0;
+
+ packetsInScatterReq = 0;
+ scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device);
+
+ for (i = 0; i < pktsToScatter; i++) {
+
+ pScatterReq->ScatterList[i].pCallerContexts[0] = NULL;
+
+ pPacket = HTC_GET_PKT_AT_HEAD(pQueue);
+ if (pPacket == NULL) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ creditPad = 0;
+ transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device,
+ pPacket->ActualLength + HTC_HDR_LENGTH);
+ /* see if the padded transfer length falls on a credit boundary */
+ creditRemainder = transferLength % target->TargetCreditSize;
+
+ if (creditRemainder != 0) {
+ /* the transfer consumes a "partial" credit, this packet cannot be bundled unless
+ * we add additional "dummy" padding (max 255 bytes) to consume the entire credit
+ *** NOTE: only allow the send padding if the endpoint is allowed to */
+ if (pEndpoint->LocalConnectionFlags & HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING) {
+ if (transferLength < target->TargetCreditSize) {
+ /* special case where the transfer is less than a credit */
+ creditPad = target->TargetCreditSize - transferLength;
+ } else {
+ creditPad = creditRemainder;
+ }
+
+ /* now check to see if we can indicate padding in the HTC header */
+ if ((creditPad > 0) && (creditPad <= 255)) {
+ /* adjust the transferlength of this packet with the new credit padding */
+ transferLength += creditPad;
+ } else {
+ /* the amount to pad is too large, bail on this packet, we have to
+ * send it using the non-bundled method */
+ pPacket = NULL;
+ }
+ } else {
+ /* bail on this packet, user does not want padding applied */
+ pPacket = NULL;
+ }
+ }
+
+ if (NULL == pPacket) {
+ /* can't bundle */
+ done = TRUE;
+ break;
+ }
+
+ if (scatterSpaceRemaining < transferLength) {
+ /* exceeds what we can transfer */
+ break;
+ }
+
+ scatterSpaceRemaining -= transferLength;
+ /* now remove it from the queue */
+ pPacket = HTC_PACKET_DEQUEUE(pQueue);
+ /* save it in the scatter list */
+ pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket;
+ /* prepare packet and flag message as part of a send bundle */
+ HTC_PREPARE_SEND_PKT(pPacket,
+ pPacket->PktInfo.AsTx.SendFlags | HTC_FLAGS_SEND_BUNDLE,
+ creditPad,
+ pPacket->PktInfo.AsTx.SeqNo);
+ pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer;
+ pScatterReq->ScatterList[i].Length = transferLength;
+ A_ASSERT(transferLength);
+ pScatterReq->TotalLength += transferLength;
+ pScatterReq->ValidScatterEntries++;
+ packetsInScatterReq++;
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" %d, Adding packet : 0x%X, len:%d (remaining space:%d) \n",
+ i, (A_UINT32)pPacket,transferLength,scatterSpaceRemaining));
+ }
+
+ if (packetsInScatterReq >= HTC_MIN_HTC_MSGS_TO_BUNDLE) {
+ /* send path is always asynchronous */
+ pScatterReq->CompletionRoutine = HTCAsyncSendScatterCompletion;
+ pScatterReq->Context = pEndpoint;
+ bundlesSent++;
+ totalPktsInBundle += packetsInScatterReq;
+ packetsInScatterReq = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Send Scatter total bytes: %d , entries: %d\n",
+ pScatterReq->TotalLength,pScatterReq->ValidScatterEntries));
+ DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_WRITE, DEV_SCATTER_ASYNC);
+ /* we don't own this anymore */
+ pScatterReq = NULL;
+ /* try to send some more */
+ continue;
+ }
+
+ /* not enough packets to use the scatter request, cleanup */
+ if (pScatterReq != NULL) {
+ if (packetsInScatterReq > 0) {
+ /* work backwards to requeue requests */
+ for (i = (packetsInScatterReq - 1); i >= 0; i--) {
+ pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]);
+ if (pPacket != NULL) {
+ /* undo any prep */
+ HTC_UNPREPARE_SEND_PKT(pPacket);
+ /* queue back to the head */
+ HTC_PACKET_ENQUEUE_TO_HEAD(pQueue,pPacket);
+ }
+ }
+ }
+ DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq);
+ }
+
+ /* if we get here, we sent all that we could, get out */
+ break;
+
+ }
+
+ *pBundlesSent = bundlesSent;
+ *pTotalBundlesPkts = totalPktsInBundle;
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCIssueSendBundle (sent:%d) \n",bundlesSent));
+
+ return;
+}
+
+/*
+ * if there are no credits, the packet(s) remains in the queue.
+ * this function returns the result of the attempt to send a queue of HTC packets */
+static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET *target,
+ HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET_QUEUE *pCallersSendQueue)
+{
+ HTC_PACKET_QUEUE sendQueue; /* temp queue to hold packets at various stages */
+ HTC_PACKET *pPacket;
+ int bundlesSent;
+ int pktsInBundles;
+ int overflow;
+ HTC_SEND_QUEUE_RESULT result = HTC_SEND_QUEUE_OK;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (Queue:0x%X Depth:%d)\n",
+ (A_UINT32)pCallersSendQueue,
+ (pCallersSendQueue == NULL) ? 0 : HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue)));
+
+ /* init the local send queue */
+ INIT_HTC_PACKET_QUEUE(&sendQueue);
+
+ do {
+
+ if (NULL == pCallersSendQueue) {
+ /* caller didn't provide a queue, just wants us to check queues and send */
+ break;
+ }
+
+ if (HTC_QUEUE_EMPTY(pCallersSendQueue)) {
+ /* empty queue */
+ result = HTC_SEND_QUEUE_DROP;
+ break;
+ }
+
+ if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) >= pEndpoint->MaxTxQueueDepth) {
+ /* we've already overflowed */
+ overflow = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue);
+ } else {
+ /* figure out how much we will overflow by */
+ overflow = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+ overflow += HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue);
+ /* figure out how much we will overflow the TX queue by */
+ overflow -= pEndpoint->MaxTxQueueDepth;
+ }
+
+ /* if overflow is negative or zero, we are okay */
+ if (overflow > 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ (" Endpoint %d, TX queue will overflow :%d , Tx Depth:%d, Max:%d \n",
+ pEndpoint->Id, overflow, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue), pEndpoint->MaxTxQueueDepth));
+ }
+ if ((overflow <= 0) || (pEndpoint->EpCallBacks.EpSendFull == NULL)) {
+ /* all packets will fit or caller did not provide send full indication handler
+ * -- just move all of them to the local sendQueue object */
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&sendQueue, pCallersSendQueue);
+ } else {
+ int i;
+ int goodPkts = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue) - overflow;
+
+ A_ASSERT(goodPkts >= 0);
+ /* we have overflowed, and a callback is provided */
+ /* dequeue all non-overflow packets into the sendqueue */
+ for (i = 0; i < goodPkts; i++) {
+ /* pop off caller's queue*/
+ pPacket = HTC_PACKET_DEQUEUE(pCallersSendQueue);
+ A_ASSERT(pPacket != NULL);
+ /* insert into local queue */
+ HTC_PACKET_ENQUEUE(&sendQueue,pPacket);
+ }
+
+ /* the caller's queue has all the packets that won't fit*/
+ /* walk through the caller's queue and indicate each one to the send full handler */
+ ITERATE_OVER_LIST_ALLOW_REMOVE(&pCallersSendQueue->QueueHead, pPacket, HTC_PACKET, ListLink) {
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Indicating overflowed TX packet: 0x%X \n",
+ (A_UINT32)pPacket));
+ if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext,
+ pPacket) == HTC_SEND_FULL_DROP) {
+ /* callback wants the packet dropped */
+ INC_HTC_EP_STAT(pEndpoint, TxDropped, 1);
+ /* leave this one in the caller's queue for cleanup */
+ } else {
+ /* callback wants to keep this packet, remove from caller's queue */
+ HTC_PACKET_REMOVE(pCallersSendQueue, pPacket);
+ /* put it in the send queue */
+ HTC_PACKET_ENQUEUE(&sendQueue,pPacket);
+ }
+
+ } ITERATE_END;
+
+ if (HTC_QUEUE_EMPTY(&sendQueue)) {
+ /* no packets made it in, caller will cleanup */
+ result = HTC_SEND_QUEUE_DROP;
+ break;
+ }
+ }
+
+ } while (FALSE);
+
+ if (result != HTC_SEND_QUEUE_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n"));
+ return result;
+ }
+
+ LOCK_HTC_TX(target);
+
+ if (!HTC_QUEUE_EMPTY(&sendQueue)) {
+ /* transfer packets */
+ HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->TxQueue,&sendQueue);
+ A_ASSERT(HTC_QUEUE_EMPTY(&sendQueue));
+ INIT_HTC_PACKET_QUEUE(&sendQueue);
+ }
+
+ /* increment tx processing count on entry */
+ pEndpoint->TxProcessCount++;
+ if (pEndpoint->TxProcessCount > 1) {
+ /* another thread or task is draining the TX queues on this endpoint
+ * that thread will reset the tx processing count when the queue is drained */
+ pEndpoint->TxProcessCount--;
+ UNLOCK_HTC_TX(target);
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend (busy) \n"));
+ return HTC_SEND_QUEUE_OK;
+ }
+
+ /***** beyond this point only 1 thread may enter ******/
+
+ /* now drain the endpoint TX queue for transmission as long as we have enough
+ * credits */
+ while (TRUE) {
+
+ if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) == 0) {
+ break;
+ }
+
+ /* get all the packets for this endpoint that we can for this pass */
+ GetHTCSendPackets(target, pEndpoint, &sendQueue);
+
+ if (HTC_PACKET_QUEUE_DEPTH(&sendQueue) == 0) {
+ /* didn't get any packets due to a lack of credits */
+ break;
+ }
+
+ UNLOCK_HTC_TX(target);
+
+ /* any packets to send are now in our local send queue */
+
+ bundlesSent = 0;
+ pktsInBundles = 0;
+
+ while (TRUE) {
+
+ /* try to send a bundle on each pass */
+ if ((target->SendBundlingEnabled) &&
+ (HTC_PACKET_QUEUE_DEPTH(&sendQueue) >= HTC_MIN_HTC_MSGS_TO_BUNDLE)) {
+ int temp1,temp2;
+ /* bundling is enabled and there is at least a minimum number of packets in the send queue
+ * send what we can in this pass */
+ HTCIssueSendBundle(pEndpoint, &sendQueue, &temp1, &temp2);
+ bundlesSent += temp1;
+ pktsInBundles += temp2;
+ }
+
+ /* if not bundling or there was a packet that could not be placed in a bundle, pull it out
+ * and send it the normal way */
+ pPacket = HTC_PACKET_DEQUEUE(&sendQueue);
+ if (NULL == pPacket) {
+ /* local queue is fully drained */
+ break;
+ }
+ HTC_PREPARE_SEND_PKT(pPacket,
+ pPacket->PktInfo.AsTx.SendFlags,
+ 0,
+ pPacket->PktInfo.AsTx.SeqNo);
+ HTCIssueSend(target, pPacket);
+
+ /* go back and see if we can bundle some more */
+ }
+
+ LOCK_HTC_TX(target);
+
+ INC_HTC_EP_STAT(pEndpoint, TxBundles, bundlesSent);
+ INC_HTC_EP_STAT(pEndpoint, TxPacketsBundled, pktsInBundles);
+
+ }
+
+ /* done with this endpoint, we can clear the count */
+ pEndpoint->TxProcessCount = 0;
+ UNLOCK_HTC_TX(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n"));
+
+ return HTC_SEND_QUEUE_OK;
+}
+
+A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint;
+ HTC_PACKET *pPacket;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCSendPktsMultiple: Queue: 0x%X, Pkts %d \n",
+ (A_UINT32)pPktQueue, HTC_PACKET_QUEUE_DEPTH(pPktQueue)));
+
+ /* get packet at head to figure out which endpoint these packets will go into */
+ pPacket = HTC_GET_PKT_AT_HEAD(pPktQueue);
+ if (NULL == pPacket) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n"));
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+ pEndpoint = &target->EndPoint[pPacket->Endpoint];
+
+ HTCTrySend(target, pEndpoint, pPktQueue);
+
+ /* do completion on any packets that couldn't get in */
+ if (!HTC_QUEUE_EMPTY(pPktQueue)) {
+
+ HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) {
+ if (HTC_STOPPING(target)) {
+ pPacket->Status = A_ECANCELED;
+ } else {
+ pPacket->Status = A_NO_RESOURCE;
+ }
+ } HTC_PACKET_QUEUE_ITERATE_END;
+
+ DO_EP_TX_COMPLETION(pEndpoint,pPktQueue);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n"));
+
+ return A_OK;
+}
+
+/* HTC API - HTCSendPkt */
+A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+ HTC_PACKET_QUEUE queue;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("+-HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n",
+ pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength));
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket);
+ return HTCSendPktsMultiple(HTCHandle, &queue);
+}
+
+/* check TX queues to drain because of credit distribution update */
+static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ HTC_ENDPOINT_CREDIT_DIST *pDistItem;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n"));
+ pDistItem = target->EpCreditDistributionListHead;
+
+ /* run through the credit distribution list to see
+ * if there are packets queued
+ * NOTE: no locks need to be taken since the distribution list
+ * is not dynamic (cannot be re-ordered) and we are not modifying any state */
+ while (pDistItem != NULL) {
+ pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved;
+
+ if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) > 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n",
+ pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
+ /* try to start the stalled queue, this list is ordered by priority.
+ * Highest priority queue get's processed first, if there are credits available the
+ * highest priority queue will get a chance to reclaim credits from lower priority
+ * ones */
+ HTCTrySend(target, pEndpoint, NULL);
+ }
+
+ pDistItem = pDistItem->pNext;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n"));
+}
+
+/* process credit reports and call distribution function */
+void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
+{
+ int i;
+ HTC_ENDPOINT *pEndpoint;
+ int totalCredits = 0;
+ A_BOOL doDist = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries));
+
+ /* lock out TX while we update credits */
+ LOCK_HTC_TX(target);
+
+ for (i = 0; i < NumEntries; i++, pRpt++) {
+ if (pRpt->EndpointID >= ENDPOINT_MAX) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ pEndpoint = &target->EndPoint[pRpt->EndpointID];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n",
+ pRpt->EndpointID, pRpt->Credits));
+
+
+#ifdef HTC_EP_STAT_PROFILING
+
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
+
+ if (FromEndpoint == pRpt->EndpointID) {
+ /* this credit report arrived on the same endpoint indicating it arrived in an RX
+ * packet */
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
+ } else if (FromEndpoint == ENDPOINT_0) {
+ /* this credit arrived on endpoint 0 as a NULL message */
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
+ } else {
+ /* arrived on another endpoint */
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
+ }
+
+#endif
+
+ if (ENDPOINT_0 == pRpt->EndpointID) {
+ /* always give endpoint 0 credits back */
+ pEndpoint->CreditDist.TxCredits += pRpt->Credits;
+ } else {
+ /* for all other endpoints, update credits to distribute, the distribution function
+ * will handle giving out credits back to the endpoints */
+ pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits;
+ /* flag that we have to do the distribution */
+ doDist = TRUE;
+ }
+
+ /* refresh tx depth for distribution function that will recover these credits
+ * NOTE: this is only valid when there are credits to recover! */
+ pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+
+ totalCredits += pRpt->Credits;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits));
+
+ if (doDist) {
+ /* this was a credit return based on a completed send operations
+ * note, this is done with the lock held */
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_SEND_COMPLETE,
+ "Send Complete",
+ target->EpCreditDistributionListHead->pNext);
+ }
+
+ UNLOCK_HTC_TX(target);
+
+ if (totalCredits) {
+ HTCCheckEndpointTxQueues(target);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n"));
+}
+
+/* flush endpoint TX queue */
+static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag)
+{
+ HTC_PACKET *pPacket;
+ HTC_PACKET_QUEUE discardQueue;
+ HTC_PACKET_QUEUE container;
+
+ /* initialize the discard queue */
+ INIT_HTC_PACKET_QUEUE(&discardQueue);
+
+ LOCK_HTC_TX(target);
+
+ /* interate from the front of the TX queue and flush out packets */
+ ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue.QueueHead, pPacket, HTC_PACKET, ListLink) {
+
+ /* check for removal */
+ if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) {
+ /* remove from queue */
+ HTC_PACKET_REMOVE(&pEndpoint->TxQueue, pPacket);
+ /* add it to the discard pile */
+ HTC_PACKET_ENQUEUE(&discardQueue, pPacket);
+ }
+
+ } ITERATE_END;
+
+ UNLOCK_HTC_TX(target);
+
+ /* empty the discard queue */
+ while (1) {
+ pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
+ if (NULL == pPacket) {
+ break;
+ }
+ pPacket->Status = A_ECANCELED;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n",
+ (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag));
+ INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket);
+ DO_EP_TX_COMPLETION(pEndpoint,&container);
+ }
+
+}
+
+void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n",
+ pEPDist->Endpoint, pEPDist->ServiceID));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n",
+ (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n",
+ HTC_PACKET_QUEUE_DEPTH(&((HTC_ENDPOINT *)pEPDist->pHTCReserved)->TxQueue)));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n"));
+}
+
+void DumpCreditDistStates(HTC_TARGET *target)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead;
+
+ while (pEPList != NULL) {
+ DumpCreditDist(pEPList);
+ pEPList = pEPList->pNext;
+ }
+
+ if (target->DistributeCredits != NULL) {
+ DO_DISTRIBUTION(target,
+ HTC_DUMP_CREDIT_STATE,
+ "Dump State",
+ NULL);
+ }
+}
+
+/* flush all send packets from all endpoint queues */
+void HTCFlushSendPkts(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ int i;
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+ DumpCreditDistStates(target);
+ }
+
+ for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+ pEndpoint = &target->EndPoint[i];
+ if (pEndpoint->ServiceID == 0) {
+ /* not in use.. */
+ continue;
+ }
+ HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL);
+ }
+
+
+}
+
+/* HTC API to flush an endpoint's TX queue*/
+void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint];
+
+ if (pEndpoint->ServiceID == 0) {
+ AR_DEBUG_ASSERT(FALSE);
+ /* not in use.. */
+ return;
+ }
+
+ HTCFlushEndpointTX(target, pEndpoint, Tag);
+}
+
+/* HTC API to indicate activity to the credit distribution function */
+void HTCIndicateActivityChange(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ A_BOOL Active)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint];
+ A_BOOL doDist = FALSE;
+
+ if (pEndpoint->ServiceID == 0) {
+ AR_DEBUG_ASSERT(FALSE);
+ /* not in use.. */
+ return;
+ }
+
+ LOCK_HTC_TX(target);
+
+ if (Active) {
+ if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) {
+ /* mark active now */
+ pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE;
+ doDist = TRUE;
+ }
+ } else {
+ if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+ /* mark inactive now */
+ pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE;
+ doDist = TRUE;
+ }
+ }
+
+ if (doDist) {
+ /* indicate current Tx Queue depth to the credit distribution function */
+ pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
+ /* do distribution again based on activity change
+ * note, this is done with the lock held */
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_ACTIVITY_CHANGE,
+ "Activity Change",
+ target->EpCreditDistributionListHead->pNext);
+ }
+
+ UNLOCK_HTC_TX(target);
+
+ if (doDist && !Active) {
+ /* if a stream went inactive and this resulted in a credit distribution change,
+ * some credits may now be available for HTC packets that are stuck in
+ * HTC queues */
+ HTCCheckEndpointTxQueues(target);
+ }
+}
+
+A_BOOL HTCIsEndpointActive(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint];
+
+ if (pEndpoint->ServiceID == 0) {
+ return FALSE;
+ }
+
+ if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
diff --git a/drivers/net/wireless/ath6kl/htc2/htc_services.c b/drivers/net/wireless/ath6kl/htc2/htc_services.c
new file mode 100644
index 000000000000..acef96e238c3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/htc2/htc_services.c
@@ -0,0 +1,444 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_services.c" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#include "htc_internal.h"
+
+void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
+{
+ /* not implemented
+ * we do not send control TX frames during normal runtime, only during setup */
+ AR_DEBUG_ASSERT(FALSE);
+}
+
+ /* callback when a control message arrives on this endpoint */
+void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
+{
+ AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
+
+ if (pPacket->Status == A_ECANCELED) {
+ /* this is a flush operation, return the control packet back to the pool */
+ HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket);
+ return;
+ }
+
+ /* the only control messages we are expecting are NULL messages (credit resports) */
+ if (pPacket->ActualLength > 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCControlRecv, got message with length:%d \n",
+ pPacket->ActualLength + HTC_HDR_LENGTH));
+
+ /* dump header and message */
+ DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
+ pPacket->ActualLength + HTC_HDR_LENGTH,
+ "Unexpected ENDPOINT 0 Message");
+ }
+
+ HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]);
+}
+
+A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
+{
+ HTC_PACKET *pSendPacket = NULL;
+ A_STATUS status;
+
+ do {
+ /* allocate a packet to send to the target */
+ pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+ if (NULL == pSendPacket) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ if (target->HTCTargetVersion >= HTC_VERSION_2P1) {
+ HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx;
+ A_UINT32 setupFlags = 0;
+
+ pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer;
+ A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
+ pSetupCompleteEx->MessageID = HTC_MSG_SETUP_COMPLETE_EX_ID;
+ if (target->MaxMsgPerBundle > 0) {
+ /* host can do HTC bundling, indicate this to the target */
+ setupFlags |= HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV;
+ pSetupCompleteEx->MaxMsgsPerBundledRecv = target->MaxMsgPerBundle;
+ }
+ A_MEMCPY(&pSetupCompleteEx->SetupFlags, &setupFlags, sizeof(pSetupCompleteEx->SetupFlags));
+ SET_HTC_PACKET_INFO_TX(pSendPacket,
+ NULL,
+ (A_UINT8 *)pSetupCompleteEx,
+ sizeof(HTC_SETUP_COMPLETE_EX_MSG),
+ ENDPOINT_0,
+ HTC_SERVICE_TX_PACKET_TAG);
+
+ } else {
+ HTC_SETUP_COMPLETE_MSG *pSetupComplete;
+ /* assemble setup complete message */
+ pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
+ A_MEMZERO(pSetupComplete, sizeof(HTC_SETUP_COMPLETE_MSG));
+ pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;
+ SET_HTC_PACKET_INFO_TX(pSendPacket,
+ NULL,
+ (A_UINT8 *)pSetupComplete,
+ sizeof(HTC_SETUP_COMPLETE_MSG),
+ ENDPOINT_0,
+ HTC_SERVICE_TX_PACKET_TAG);
+ }
+
+ /* we want synchronous operation */
+ pSendPacket->Completion = NULL;
+ HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
+ /* send the message */
+ status = HTCIssueSend(target,pSendPacket);
+
+ } while (FALSE);
+
+ if (pSendPacket != NULL) {
+ HTC_FREE_CONTROL_TX(target,pSendPacket);
+ }
+
+ return status;
+}
+
+
+A_STATUS HTCConnectService(HTC_HANDLE HTCHandle,
+ HTC_SERVICE_CONNECT_REQ *pConnectReq,
+ HTC_SERVICE_CONNECT_RESP *pConnectResp)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_STATUS status = A_OK;
+ HTC_PACKET *pRecvPacket = NULL;
+ HTC_PACKET *pSendPacket = NULL;
+ HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg;
+ HTC_CONNECT_SERVICE_MSG *pConnectMsg;
+ HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX;
+ HTC_ENDPOINT *pEndpoint;
+ unsigned int maxMsgSize = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n",
+ (A_UINT32)target, pConnectReq->ServiceID));
+
+ do {
+
+ AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
+
+ if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
+ /* special case for pseudo control service */
+ assignedEndpoint = ENDPOINT_0;
+ maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
+ } else {
+ /* allocate a packet to send to the target */
+ pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+ if (NULL == pSendPacket) {
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_NO_MEMORY;
+ break;
+ }
+ /* assemble connect service message */
+ pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
+ AR_DEBUG_ASSERT(pConnectMsg != NULL);
+ A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
+ pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
+ pConnectMsg->ServiceID = pConnectReq->ServiceID;
+ pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
+ /* check caller if it wants to transfer meta data */
+ if ((pConnectReq->pMetaData != NULL) &&
+ (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+ /* copy meta data into message buffer (after header ) */
+ A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
+ pConnectReq->pMetaData,
+ pConnectReq->MetaDataLength);
+ pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
+ }
+
+ SET_HTC_PACKET_INFO_TX(pSendPacket,
+ NULL,
+ (A_UINT8 *)pConnectMsg,
+ sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
+ ENDPOINT_0,
+ HTC_SERVICE_TX_PACKET_TAG);
+
+ /* we want synchronous operation */
+ pSendPacket->Completion = NULL;
+ HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
+ status = HTCIssueSend(target,pSendPacket);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* wait for response */
+ status = HTCWaitforControlMessage(target, &pRecvPacket);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* we controlled the buffer creation so it has to be properly aligned */
+ pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
+
+ if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
+ (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
+ /* this message is not valid */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ pConnectResp->ConnectRespCode = pResponseMsg->Status;
+ /* check response status */
+ if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Target failed service 0x%X connect request (status:%d)\n",
+ pResponseMsg->ServiceID, pResponseMsg->Status));
+ status = A_EPROTO;
+ break;
+ }
+
+ assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID;
+ maxMsgSize = pResponseMsg->MaxMsgSize;
+
+ if ((pConnectResp->pMetaData != NULL) &&
+ (pResponseMsg->ServiceMetaLength > 0) &&
+ (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+ /* caller supplied a buffer and the target responded with data */
+ int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
+ /* copy the meta data */
+ A_MEMCPY(pConnectResp->pMetaData,
+ ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
+ copyLength);
+ pConnectResp->ActualLength = copyLength;
+ }
+
+ }
+
+ /* the rest of these are parameter checks so set the error status */
+ status = A_EPROTO;
+
+ if (assignedEndpoint >= ENDPOINT_MAX) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ if (0 == maxMsgSize) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ pEndpoint = &target->EndPoint[assignedEndpoint];
+ pEndpoint->Id = assignedEndpoint;
+ if (pEndpoint->ServiceID != 0) {
+ /* endpoint already in use! */
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* return assigned endpoint to caller */
+ pConnectResp->Endpoint = assignedEndpoint;
+ pConnectResp->MaxMsgLength = maxMsgSize;
+
+ /* setup the endpoint */
+ pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
+ pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
+ pEndpoint->MaxMsgLength = maxMsgSize;
+ /* copy all the callbacks */
+ pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
+ /* set the credit distribution info for this endpoint, this information is
+ * passed back to the credit distribution callback function */
+ pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
+ pEndpoint->CreditDist.pHTCReserved = pEndpoint;
+ pEndpoint->CreditDist.Endpoint = assignedEndpoint;
+ pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
+
+ if (pConnectReq->MaxSendMsgSize != 0) {
+ /* override TxCreditsPerMaxMsg calculation, this optimizes the credit-low indications
+ * since the host will actually issue smaller messages in the Send path */
+ if (pConnectReq->MaxSendMsgSize > maxMsgSize) {
+ /* can't be larger than the maximum the target can support */
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+ pEndpoint->CreditDist.TxCreditsPerMaxMsg = pConnectReq->MaxSendMsgSize / target->TargetCreditSize;
+ } else {
+ pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
+ }
+
+ if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+ pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
+ }
+
+ /* save local connection flags */
+ pEndpoint->LocalConnectionFlags = pConnectReq->LocalConnectionFlags;
+
+ status = A_OK;
+
+ } while (FALSE);
+
+ if (pSendPacket != NULL) {
+ HTC_FREE_CONTROL_TX(target,pSendPacket);
+ }
+
+ if (pRecvPacket != NULL) {
+ HTC_FREE_CONTROL_RX(target,pRecvPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
+
+ return status;
+}
+
+static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
+
+ if (NULL == target->EpCreditDistributionListHead) {
+ target->EpCreditDistributionListHead = pEpDist;
+ pEpDist->pNext = NULL;
+ pEpDist->pPrev = NULL;
+ return;
+ }
+
+ /* queue to the end of the list, this does not have to be very
+ * fast since this list is built at startup time */
+ pCurEntry = target->EpCreditDistributionListHead;
+
+ while (pCurEntry) {
+ pLastEntry = pCurEntry;
+ pCurEntry = pCurEntry->pNext;
+ }
+
+ pLastEntry->pNext = pEpDist;
+ pEpDist->pPrev = pLastEntry;
+ pEpDist->pNext = NULL;
+}
+
+
+
+/* default credit init callback */
+static void HTCDefaultCreditInit(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ int TotalCredits)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ int totalEps = 0;
+ int creditsPerEndpoint;
+
+ pCurEpDist = pEPList;
+ /* first run through the list and figure out how many endpoints we are dealing with */
+ while (pCurEpDist != NULL) {
+ pCurEpDist = pCurEpDist->pNext;
+ totalEps++;
+ }
+
+ /* even distribution */
+ creditsPerEndpoint = TotalCredits/totalEps;
+
+ pCurEpDist = pEPList;
+ /* run through the list and set minimum and normal credits and
+ * provide the endpoint with some credits to start */
+ while (pCurEpDist != NULL) {
+
+ if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
+ /* too many endpoints and not enough credits */
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+ /* our minimum is set for at least 1 max message */
+ pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+ /* this value is ignored by our credit alg, since we do
+ * not dynamically adjust credits, this is the policy of
+ * the "default" credit distribution, something simple and easy */
+ pCurEpDist->TxCreditsNorm = 0xFFFF;
+ /* give the endpoint minimum credits */
+ pCurEpDist->TxCredits = creditsPerEndpoint;
+ pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+}
+
+/* default credit distribution callback, NOTE, this callback holds the TX lock */
+void HTCDefaultCreditDist(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+ HTC_CREDIT_DIST_REASON Reason)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+
+ if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
+ pCurEpDist = pEPDistList;
+ /* simple distribution */
+ while (pCurEpDist != NULL) {
+ if (pCurEpDist->TxCreditsToDist > 0) {
+ /* just give the endpoint back the credits */
+ pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+ pCurEpDist->TxCreditsToDist = 0;
+ }
+ pCurEpDist = pCurEpDist->pNext;
+ }
+ }
+
+ /* note we do not need to handle the other reason codes as this is a very
+ * simple distribution scheme, no need to seek for more credits or handle inactivity */
+}
+
+void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
+ void *pCreditDistContext,
+ HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+ HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+ HTC_SERVICE_ID ServicePriorityOrder[],
+ int ListLength)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ int i;
+ int ep;
+
+ if (CreditInitFunc != NULL) {
+ /* caller has supplied their own distribution functions */
+ target->InitCredits = CreditInitFunc;
+ AR_DEBUG_ASSERT(CreditDistFunc != NULL);
+ target->DistributeCredits = CreditDistFunc;
+ target->pCredDistContext = pCreditDistContext;
+ } else {
+ /* caller wants HTC to do distribution */
+ /* if caller wants service to handle distributions then
+ * it must set both of these to NULL! */
+ AR_DEBUG_ASSERT(CreditDistFunc == NULL);
+ target->InitCredits = HTCDefaultCreditInit;
+ target->DistributeCredits = HTCDefaultCreditDist;
+ target->pCredDistContext = target;
+ }
+
+ /* always add HTC control endpoint first, we only expose the list after the
+ * first one, this is added for TX queue checking */
+ AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
+
+ /* build the list of credit distribution structures in priority order
+ * supplied by the caller, these will follow endpoint 0 */
+ for (i = 0; i < ListLength; i++) {
+ /* match services with endpoints and add the endpoints to the distribution list
+ * in FIFO order */
+ for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
+ if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
+ /* queue this one to the list */
+ AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
+ break;
+ }
+ }
+ AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
+ }
+
+}
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h b/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h
new file mode 100644
index 000000000000..9e071548ed92
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h
@@ -0,0 +1,57 @@
+//------------------------------------------------------------------------------
+// <copyright file="AR6002_regdump.h" company="Atheros">
+// Copyright (c) 2006 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __AR6002_REGDUMP_H__
+#define __AR6002_REGDUMP_H__
+
+#if !defined(__ASSEMBLER__)
+/*
+ * XTensa CPU state
+ * This must match the state saved by the target exception handler.
+ */
+struct XTensa_exception_frame_s {
+ A_UINT32 xt_pc;
+ A_UINT32 xt_ps;
+ A_UINT32 xt_sar;
+ A_UINT32 xt_vpri;
+ A_UINT32 xt_a2;
+ A_UINT32 xt_a3;
+ A_UINT32 xt_a4;
+ A_UINT32 xt_a5;
+ A_UINT32 xt_exccause;
+ A_UINT32 xt_lcount;
+ A_UINT32 xt_lbeg;
+ A_UINT32 xt_lend;
+
+ A_UINT32 epc1, epc2, epc3, epc4;
+
+ /* Extra info to simplify post-mortem stack walkback */
+#define AR6002_REGDUMP_FRAMES 10
+ struct {
+ A_UINT32 a0; /* pc */
+ A_UINT32 a1; /* sp */
+ A_UINT32 a2;
+ A_UINT32 a3;
+ } wb[AR6002_REGDUMP_FRAMES];
+};
+typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
+#define RD_SIZE sizeof(CPU_exception_frame_t)
+
+#endif
+#endif /* __AR6002_REGDUMP_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h b/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h
new file mode 100644
index 000000000000..ca45848c3caa
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h
@@ -0,0 +1,47 @@
+//------------------------------------------------------------------------------
+// <copyright file="AR6K_version.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#define __VER_MAJOR_ 3
+#define __VER_MINOR_ 0
+#define __VER_PATCH_ 0
+
+/* The makear6ksdk script (used for release builds) modifies the following line. */
+#define __BUILD_NUMBER_ 1057
+
+
+/* Format of the version number. */
+#define VER_MAJOR_BIT_OFFSET 28
+#define VER_MINOR_BIT_OFFSET 24
+#define VER_PATCH_BIT_OFFSET 16
+#define VER_BUILD_NUM_BIT_OFFSET 0
+
+
+/*
+ * The version has the following format:
+ * Bits 28-31: Major version
+ * Bits 24-27: Minor version
+ * Bits 16-23: Patch version
+ * Bits 0-15: Build number (automatically generated during build process )
+ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
+ *
+ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
+ */
+#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/addrs.h b/drivers/net/wireless/ath6kl/include/AR6002/addrs.h
new file mode 100644
index 000000000000..bbb647fb942a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/addrs.h
@@ -0,0 +1,86 @@
+//------------------------------------------------------------------------------
+// <copyright file="addrs.h" company="Atheros">
+// Copyright (c) 2004-2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __ADDRS_H__
+#define __ADDRS_H__
+
+/*
+ * Special AR6002 Addresses that may be needed by special
+ * applications (e.g. ART) on the Host as well as Target.
+ */
+
+#if defined(AR6002_REV2)
+#define AR6K_RAM_START 0x00500000
+#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
+#define TARG_RAM_SZ (184*1024)
+#define TARG_ROM_SZ (80*1024)
+#endif
+#if defined(AR6002_REV4) || defined(AR6003)
+#define AR6K_RAM_START 0x00540000
+#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000)
+#define TARG_RAM_SZ (256*1024)
+#define TARG_ROM_SZ (256*1024)
+#endif
+
+#define AR6002_BOARD_DATA_SZ 768
+#define AR6003_BOARD_DATA_SZ 1024
+
+#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset))
+#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
+
+#define AR6K_ROM_START 0x004e0000
+#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000)
+#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
+#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
+
+/*
+ * At this ROM address is a pointer to the start of the ROM DataSet Index.
+ * If there are no ROM DataSets, there's a 0 at this address.
+ */
+#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8)
+#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4)
+
+/*
+ * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to
+ * board data.
+ */
+
+/* Size of Board Data, in bytes */
+#if defined(AR6002_REV4) || defined(AR6003)
+#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ
+#else
+#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ
+#endif
+
+
+/*
+ * Constants used by ASM code to access fields of host_interest_s,
+ * which is at a fixed location in RAM.
+ */
+#if defined(AR6002_REV4) || defined(AR6003)
+#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c)
+#else
+#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c)
+#endif
+#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR
+
+#endif /* __ADDRS_H__ */
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h
new file mode 100644
index 000000000000..28b972afc8d7
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h
@@ -0,0 +1,83 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_INTF_REG_REG_H_
+#define _ANALOG_INTF_REG_REG_H_
+
+#define SW_OVERRIDE_ADDRESS 0x00000080
+#define SW_OVERRIDE_OFFSET 0x00000080
+#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1
+#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1
+#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002
+#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
+#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
+#define SW_OVERRIDE_ENABLE_MSB 0
+#define SW_OVERRIDE_ENABLE_LSB 0
+#define SW_OVERRIDE_ENABLE_MASK 0x00000001
+#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
+#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
+
+#define SIN_VAL_ADDRESS 0x00000084
+#define SIN_VAL_OFFSET 0x00000084
+#define SIN_VAL_SIN_MSB 0
+#define SIN_VAL_SIN_LSB 0
+#define SIN_VAL_SIN_MASK 0x00000001
+#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
+#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
+
+#define SW_SCLK_ADDRESS 0x00000088
+#define SW_SCLK_OFFSET 0x00000088
+#define SW_SCLK_SW_SCLK_MSB 0
+#define SW_SCLK_SW_SCLK_LSB 0
+#define SW_SCLK_SW_SCLK_MASK 0x00000001
+#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
+#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
+
+#define SW_CNTL_ADDRESS 0x0000008c
+#define SW_CNTL_OFFSET 0x0000008c
+#define SW_CNTL_SW_SCAPTURE_MSB 2
+#define SW_CNTL_SW_SCAPTURE_LSB 2
+#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004
+#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
+#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
+#define SW_CNTL_SW_SUPDATE_MSB 1
+#define SW_CNTL_SW_SUPDATE_LSB 1
+#define SW_CNTL_SW_SUPDATE_MASK 0x00000002
+#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
+#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
+#define SW_CNTL_SW_SOUT_MSB 0
+#define SW_CNTL_SW_SOUT_LSB 0
+#define SW_CNTL_SW_SOUT_MASK 0x00000001
+#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
+#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_reg_reg_s {
+ unsigned char pad0[128]; /* pad to 0x80 */
+ volatile unsigned int sw_override;
+ volatile unsigned int sin_val;
+ volatile unsigned int sw_sclk;
+ volatile unsigned int sw_cntl;
+} analog_intf_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h
new file mode 100644
index 000000000000..c485ac725c2f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h
@@ -0,0 +1,1951 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_REG_REG_H_
+#define _ANALOG_REG_REG_H_
+
+#define SYNTH_SYNTH1_ADDRESS 0x00000000
+#define SYNTH_SYNTH1_OFFSET 0x00000000
+#define SYNTH_SYNTH1_PWD_BIAS_MSB 31
+#define SYNTH_SYNTH1_PWD_BIAS_LSB 31
+#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000
+#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB)
+#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK)
+#define SYNTH_SYNTH1_PWD_CP_MSB 30
+#define SYNTH_SYNTH1_PWD_CP_LSB 30
+#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000
+#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB)
+#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK)
+#define SYNTH_SYNTH1_PWD_VCMON_MSB 29
+#define SYNTH_SYNTH1_PWD_VCMON_LSB 29
+#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000
+#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB)
+#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK)
+#define SYNTH_SYNTH1_PWD_VCO_MSB 28
+#define SYNTH_SYNTH1_PWD_VCO_LSB 28
+#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000
+#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB)
+#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK)
+#define SYNTH_SYNTH1_PWD_PRESC_MSB 27
+#define SYNTH_SYNTH1_PWD_PRESC_LSB 27
+#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000
+#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB)
+#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK)
+#define SYNTH_SYNTH1_PWD_LODIV_MSB 26
+#define SYNTH_SYNTH1_PWD_LODIV_LSB 26
+#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000
+#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB)
+#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK)
+#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25
+#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25
+#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000
+#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB)
+#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK)
+#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24
+#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24
+#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000
+#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB)
+#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000
+#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK)
+#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22
+#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22
+#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000
+#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB)
+#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK)
+#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21
+#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20
+#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000
+#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB)
+#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK)
+#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19
+#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18
+#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000
+#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB)
+#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK)
+#define SYNTH_SYNTH1_SLIDINGIF_MSB 17
+#define SYNTH_SYNTH1_SLIDINGIF_LSB 17
+#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000
+#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB)
+#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK)
+#define SYNTH_SYNTH1_SPARE_PWD_MSB 16
+#define SYNTH_SYNTH1_SPARE_PWD_LSB 16
+#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000
+#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB)
+#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000
+#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14
+#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14
+#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000
+#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13
+#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13
+#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000
+#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB)
+#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12
+#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00
+#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_MSB 5
+#define SYNTH_SYNTH1_MONITOR_FB_LSB 5
+#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020
+#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK)
+#define SYNTH_SYNTH1_MONITOR_REF_MSB 4
+#define SYNTH_SYNTH1_MONITOR_REF_LSB 4
+#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010
+#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB)
+#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK)
+
+#define SYNTH_SYNTH2_ADDRESS 0x00000004
+#define SYNTH_SYNTH2_OFFSET 0x00000004
+#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31
+#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29
+#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000
+#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB)
+#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK)
+#define SYNTH_SYNTH2_VC_HI_REF_MSB 28
+#define SYNTH_SYNTH2_VC_HI_REF_LSB 26
+#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000
+#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB)
+#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK)
+#define SYNTH_SYNTH2_VC_MID_REF_MSB 25
+#define SYNTH_SYNTH2_VC_MID_REF_LSB 23
+#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000
+#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB)
+#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK)
+#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22
+#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20
+#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000
+#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB)
+#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK)
+#define SYNTH_SYNTH2_LOOP_CP_MSB 14
+#define SYNTH_SYNTH2_LOOP_CP_LSB 10
+#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00
+#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB)
+#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK)
+#define SYNTH_SYNTH2_LOOP_RS_MSB 9
+#define SYNTH_SYNTH2_LOOP_RS_LSB 5
+#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0
+#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB)
+#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK)
+#define SYNTH_SYNTH2_LOOP_CS_MSB 4
+#define SYNTH_SYNTH2_LOOP_CS_LSB 3
+#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018
+#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB)
+#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK)
+#define SYNTH_SYNTH2_SPARE_BITS_MSB 2
+#define SYNTH_SYNTH2_SPARE_BITS_LSB 0
+#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007
+#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB)
+#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK)
+
+#define SYNTH_SYNTH3_ADDRESS 0x00000008
+#define SYNTH_SYNTH3_OFFSET 0x00000008
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB)
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23
+#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18
+#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
+#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK)
+
+#define SYNTH_SYNTH4_ADDRESS 0x0000000c
+#define SYNTH_SYNTH4_OFFSET 0x0000000c
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB)
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK)
+#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30
+#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30
+#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000
+#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB)
+#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK)
+#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27
+#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27
+#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000
+#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB)
+#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
+#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK)
+#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25
+#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18
+#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
+#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB)
+#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
+#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK)
+#define SYNTH_SYNTH4_REFDIVSEL_MSB 16
+#define SYNTH_SYNTH4_REFDIVSEL_LSB 15
+#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000
+#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB)
+#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK)
+#define SYNTH_SYNTH4_PFDDELAY_MSB 14
+#define SYNTH_SYNTH4_PFDDELAY_LSB 14
+#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000
+#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB)
+#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK)
+#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13
+#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13
+#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000
+#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB)
+#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK)
+#define SYNTH_SYNTH4_PRESCSEL_MSB 12
+#define SYNTH_SYNTH4_PRESCSEL_LSB 11
+#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800
+#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB)
+#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK)
+#define SYNTH_SYNTH4_RESET_PRESC_MSB 10
+#define SYNTH_SYNTH4_RESET_PRESC_LSB 10
+#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400
+#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB)
+#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK)
+#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9
+#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9
+#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200
+#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB)
+#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK)
+#define SYNTH_SYNTH4_SDM_MODE_MSB 8
+#define SYNTH_SYNTH4_SDM_MODE_LSB 8
+#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100
+#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB)
+#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK)
+#define SYNTH_SYNTH4_SDM_DITHER_MSB 7
+#define SYNTH_SYNTH4_SDM_DITHER_LSB 6
+#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0
+#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB)
+#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK)
+#define SYNTH_SYNTH4_SPARE_MISC_MSB 3
+#define SYNTH_SYNTH4_SPARE_MISC_LSB 2
+#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c
+#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB)
+#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
+#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK)
+
+#define SYNTH_SYNTH5_ADDRESS 0x00000010
+#define SYNTH_SYNTH5_OFFSET 0x00000010
+#define SYNTH_SYNTH5_LOOP_IP0_MSB 31
+#define SYNTH_SYNTH5_LOOP_IP0_LSB 28
+#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000
+#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB)
+#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK)
+#define SYNTH_SYNTH5_SLOPE_IP_MSB 27
+#define SYNTH_SYNTH5_SLOPE_IP_LSB 25
+#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000
+#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB)
+#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK)
+#define SYNTH_SYNTH5_CPBIAS_MSB 24
+#define SYNTH_SYNTH5_CPBIAS_LSB 23
+#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000
+#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB)
+#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK)
+#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22
+#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22
+#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000
+#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB)
+#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK)
+#define SYNTH_SYNTH5_CPLOWLK_MSB 21
+#define SYNTH_SYNTH5_CPLOWLK_LSB 21
+#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000
+#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB)
+#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20
+#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000
+#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK)
+#define SYNTH_SYNTH5_CAPRANGE1_MSB 16
+#define SYNTH_SYNTH5_CAPRANGE1_LSB 13
+#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000
+#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB)
+#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK)
+#define SYNTH_SYNTH5_CAPRANGE2_MSB 12
+#define SYNTH_SYNTH5_CAPRANGE2_LSB 9
+#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00
+#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB)
+#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK)
+#define SYNTH_SYNTH5_CAPRANGE3_MSB 8
+#define SYNTH_SYNTH5_CAPRANGE3_LSB 5
+#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0
+#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB)
+#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK)
+#define SYNTH_SYNTH5_SPARE_MSB 1
+#define SYNTH_SYNTH5_SPARE_LSB 0
+#define SYNTH_SYNTH5_SPARE_MASK 0x00000003
+#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB)
+#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK)
+
+#define SYNTH_SYNTH6_ADDRESS 0x00000014
+#define SYNTH_SYNTH6_OFFSET 0x00000014
+#define SYNTH_SYNTH6_IRCP_MSB 31
+#define SYNTH_SYNTH6_IRCP_LSB 29
+#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000
+#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB)
+#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK)
+#define SYNTH_SYNTH6_IRVCMON_MSB 28
+#define SYNTH_SYNTH6_IRVCMON_LSB 26
+#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000
+#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB)
+#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK)
+#define SYNTH_SYNTH6_IRSPARE_MSB 25
+#define SYNTH_SYNTH6_IRSPARE_LSB 23
+#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000
+#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB)
+#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK)
+#define SYNTH_SYNTH6_ICPRESC_MSB 22
+#define SYNTH_SYNTH6_ICPRESC_LSB 20
+#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000
+#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB)
+#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK)
+#define SYNTH_SYNTH6_ICLODIV_MSB 19
+#define SYNTH_SYNTH6_ICLODIV_LSB 17
+#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000
+#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB)
+#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK)
+#define SYNTH_SYNTH6_ICLOMIX_MSB 16
+#define SYNTH_SYNTH6_ICLOMIX_LSB 14
+#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000
+#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB)
+#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK)
+#define SYNTH_SYNTH6_ICSPAREA_MSB 13
+#define SYNTH_SYNTH6_ICSPAREA_LSB 11
+#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800
+#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB)
+#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK)
+#define SYNTH_SYNTH6_ICSPAREB_MSB 10
+#define SYNTH_SYNTH6_ICSPAREB_LSB 8
+#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700
+#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB)
+#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK)
+#define SYNTH_SYNTH6_ICVCO_MSB 7
+#define SYNTH_SYNTH6_ICVCO_LSB 5
+#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0
+#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB)
+#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK)
+#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4
+#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3
+#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018
+#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB)
+#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK)
+#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2
+#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0
+#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007
+#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB)
+#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK)
+
+#define SYNTH_SYNTH7_ADDRESS 0x00000018
+#define SYNTH_SYNTH7_OFFSET 0x00000018
+#define SYNTH_SYNTH7_SYNTH_ON_MSB 31
+#define SYNTH_SYNTH7_SYNTH_ON_LSB 31
+#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000
+#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB)
+#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK)
+#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26
+#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26
+#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000
+#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB)
+#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK)
+#define SYNTH_SYNTH7_PIN_VC_MSB 24
+#define SYNTH_SYNTH7_PIN_VC_LSB 24
+#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000
+#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB)
+#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK)
+#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23
+#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16
+#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000
+#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB)
+#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK)
+#define SYNTH_SYNTH7_SHORT_R_MSB 15
+#define SYNTH_SYNTH7_SHORT_R_LSB 15
+#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000
+#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB)
+#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK)
+#define SYNTH_SYNTH7_RESET_RFD_MSB 14
+#define SYNTH_SYNTH7_RESET_RFD_LSB 14
+#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000
+#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB)
+#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK)
+#define SYNTH_SYNTH7_RESET_PFD_MSB 13
+#define SYNTH_SYNTH7_RESET_PFD_LSB 13
+#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000
+#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB)
+#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK)
+#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11
+#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11
+#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800
+#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB)
+#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK)
+#define SYNTH_SYNTH7_VC2HIGH_MSB 10
+#define SYNTH_SYNTH7_VC2HIGH_LSB 10
+#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400
+#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB)
+#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK)
+#define SYNTH_SYNTH7_VC2LOW_MSB 9
+#define SYNTH_SYNTH7_VC2LOW_LSB 9
+#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200
+#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB)
+#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK)
+#define SYNTH_SYNTH7_LOOP_IP_MSB 8
+#define SYNTH_SYNTH7_LOOP_IP_LSB 5
+#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0
+#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB)
+#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4
+#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018
+#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH7_SPARE_READ_MSB 2
+#define SYNTH_SYNTH7_SPARE_READ_LSB 0
+#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007
+#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB)
+#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK)
+
+#define SYNTH_SYNTH8_ADDRESS 0x0000001c
+#define SYNTH_SYNTH8_OFFSET 0x0000001c
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB)
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK)
+#define SYNTH_SYNTH8_FRACMODE_MSB 30
+#define SYNTH_SYNTH8_FRACMODE_LSB 30
+#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000
+#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB)
+#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK)
+#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29
+#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28
+#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000
+#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB)
+#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK)
+#define SYNTH_SYNTH8_SPARE_MSB 27
+#define SYNTH_SYNTH8_SPARE_LSB 27
+#define SYNTH_SYNTH8_SPARE_MASK 0x08000000
+#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB)
+#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK)
+#define SYNTH_SYNTH8_CHANSEL_MSB 26
+#define SYNTH_SYNTH8_CHANSEL_LSB 18
+#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000
+#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB)
+#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK)
+#define SYNTH_SYNTH8_CHANFRAC_MSB 17
+#define SYNTH_SYNTH8_CHANFRAC_LSB 1
+#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe
+#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB)
+#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001
+#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK)
+
+#define RF5G_RF5G1_ADDRESS 0x00000020
+#define RF5G_RF5G1_OFFSET 0x00000020
+#define RF5G_RF5G1_PDTXLO5_MSB 31
+#define RF5G_RF5G1_PDTXLO5_LSB 31
+#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000
+#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB)
+#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK)
+#define RF5G_RF5G1_PDTXMIX5_MSB 30
+#define RF5G_RF5G1_PDTXMIX5_LSB 30
+#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000
+#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB)
+#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK)
+#define RF5G_RF5G1_PDTXBUF5_MSB 29
+#define RF5G_RF5G1_PDTXBUF5_LSB 29
+#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000
+#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB)
+#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK)
+#define RF5G_RF5G1_PDPADRV5_MSB 28
+#define RF5G_RF5G1_PDPADRV5_LSB 28
+#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000
+#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB)
+#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK)
+#define RF5G_RF5G1_PDPAOUT5_MSB 27
+#define RF5G_RF5G1_PDPAOUT5_LSB 27
+#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000
+#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB)
+#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK)
+#define RF5G_RF5G1_TUNE_PADRV5_MSB 26
+#define RF5G_RF5G1_TUNE_PADRV5_LSB 24
+#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000
+#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB)
+#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK)
+#define RF5G_RF5G1_PWDTXPKD_MSB 23
+#define RF5G_RF5G1_PWDTXPKD_LSB 21
+#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000
+#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB)
+#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK)
+#define RF5G_RF5G1_DB5_MSB 20
+#define RF5G_RF5G1_DB5_LSB 18
+#define RF5G_RF5G1_DB5_MASK 0x001c0000
+#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB)
+#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK)
+#define RF5G_RF5G1_OB5_MSB 17
+#define RF5G_RF5G1_OB5_LSB 15
+#define RF5G_RF5G1_OB5_MASK 0x00038000
+#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB)
+#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK)
+#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14
+#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12
+#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000
+#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB)
+#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK)
+#define RF5G_RF5G1_PDLO5DIV_MSB 11
+#define RF5G_RF5G1_PDLO5DIV_LSB 11
+#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800
+#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB)
+#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK)
+#define RF5G_RF5G1_PDLO5MIX_MSB 10
+#define RF5G_RF5G1_PDLO5MIX_LSB 10
+#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400
+#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB)
+#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK)
+#define RF5G_RF5G1_PDQBUF5_MSB 9
+#define RF5G_RF5G1_PDQBUF5_LSB 9
+#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200
+#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB)
+#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK)
+#define RF5G_RF5G1_PDLO5AGC_MSB 8
+#define RF5G_RF5G1_PDLO5AGC_LSB 8
+#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100
+#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB)
+#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK)
+#define RF5G_RF5G1_PDREGLO5_MSB 7
+#define RF5G_RF5G1_PDREGLO5_LSB 7
+#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080
+#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB)
+#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK)
+#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6
+#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4
+#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070
+#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB)
+#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK)
+#define RF5G_RF5G1_LO5CONTROL_MSB 3
+#define RF5G_RF5G1_LO5CONTROL_LSB 3
+#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008
+#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB)
+#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK)
+#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2
+#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2
+#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004
+#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB)
+#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK)
+#define RF5G_RF5G1_SPARE_MSB 1
+#define RF5G_RF5G1_SPARE_LSB 0
+#define RF5G_RF5G1_SPARE_MASK 0x00000003
+#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB)
+#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK)
+
+#define RF5G_RF5G2_ADDRESS 0x00000024
+#define RF5G_RF5G2_OFFSET 0x00000024
+#define RF5G_RF5G2_AGCLO_B_MSB 31
+#define RF5G_RF5G2_AGCLO_B_LSB 29
+#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000
+#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB)
+#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK)
+#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28
+#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26
+#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000
+#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB)
+#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK)
+#define RF5G_RF5G2_PDCMOSLO5_MSB 25
+#define RF5G_RF5G2_PDCMOSLO5_LSB 25
+#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000
+#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB)
+#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK)
+#define RF5G_RF5G2_PDVGM5_MSB 24
+#define RF5G_RF5G2_PDVGM5_LSB 24
+#define RF5G_RF5G2_PDVGM5_MASK 0x01000000
+#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB)
+#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK)
+#define RF5G_RF5G2_PDCSLNA5_MSB 23
+#define RF5G_RF5G2_PDCSLNA5_LSB 23
+#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000
+#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB)
+#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK)
+#define RF5G_RF5G2_PDRFVGA5_MSB 22
+#define RF5G_RF5G2_PDRFVGA5_LSB 22
+#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000
+#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB)
+#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK)
+#define RF5G_RF5G2_PDREGFE5_MSB 21
+#define RF5G_RF5G2_PDREGFE5_LSB 21
+#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000
+#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB)
+#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK)
+#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20
+#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18
+#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000
+#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB)
+#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK)
+#define RF5G_RF5G2_BRFVGA5_MSB 17
+#define RF5G_RF5G2_BRFVGA5_LSB 15
+#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000
+#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB)
+#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK)
+#define RF5G_RF5G2_BCSLNA5_MSB 14
+#define RF5G_RF5G2_BCSLNA5_LSB 12
+#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000
+#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB)
+#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK)
+#define RF5G_RF5G2_BVGM5_MSB 11
+#define RF5G_RF5G2_BVGM5_LSB 9
+#define RF5G_RF5G2_BVGM5_MASK 0x00000e00
+#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB)
+#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK)
+#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8
+#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8
+#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100
+#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB)
+#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK)
+#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7
+#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6
+#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0
+#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB)
+#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK)
+#define RF5G_RF5G2_ENABLE_PCA_MSB 5
+#define RF5G_RF5G2_ENABLE_PCA_LSB 5
+#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020
+#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB)
+#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK)
+#define RF5G_RF5G2_TUNE_LO_MSB 4
+#define RF5G_RF5G2_TUNE_LO_LSB 2
+#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c
+#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB)
+#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK)
+#define RF5G_RF5G2_SPARE_MSB 1
+#define RF5G_RF5G2_SPARE_LSB 0
+#define RF5G_RF5G2_SPARE_MASK 0x00000003
+#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB)
+#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK)
+
+#define RF2G_RF2G1_ADDRESS 0x00000028
+#define RF2G_RF2G1_OFFSET 0x00000028
+#define RF2G_RF2G1_BLNA1_MSB 31
+#define RF2G_RF2G1_BLNA1_LSB 29
+#define RF2G_RF2G1_BLNA1_MASK 0xe0000000
+#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB)
+#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK)
+#define RF2G_RF2G1_BLNA1F_MSB 28
+#define RF2G_RF2G1_BLNA1F_LSB 26
+#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000
+#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB)
+#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK)
+#define RF2G_RF2G1_BLNA1BUF_MSB 25
+#define RF2G_RF2G1_BLNA1BUF_LSB 23
+#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000
+#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB)
+#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK)
+#define RF2G_RF2G1_BLNA2_MSB 22
+#define RF2G_RF2G1_BLNA2_LSB 20
+#define RF2G_RF2G1_BLNA2_MASK 0x00700000
+#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB)
+#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK)
+#define RF2G_RF2G1_DB_MSB 19
+#define RF2G_RF2G1_DB_LSB 17
+#define RF2G_RF2G1_DB_MASK 0x000e0000
+#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB)
+#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK)
+#define RF2G_RF2G1_OB_MSB 16
+#define RF2G_RF2G1_OB_LSB 14
+#define RF2G_RF2G1_OB_MASK 0x0001c000
+#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB)
+#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK)
+#define RF2G_RF2G1_FE_ATB_SEL_MSB 13
+#define RF2G_RF2G1_FE_ATB_SEL_LSB 11
+#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800
+#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB)
+#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK)
+#define RF2G_RF2G1_RF_ATB_SEL_MSB 10
+#define RF2G_RF2G1_RF_ATB_SEL_LSB 8
+#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700
+#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB)
+#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK)
+#define RF2G_RF2G1_SELLNA_MSB 7
+#define RF2G_RF2G1_SELLNA_LSB 7
+#define RF2G_RF2G1_SELLNA_MASK 0x00000080
+#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB)
+#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK)
+#define RF2G_RF2G1_LOCONTROL_MSB 6
+#define RF2G_RF2G1_LOCONTROL_LSB 6
+#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040
+#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB)
+#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK)
+#define RF2G_RF2G1_SHORTLNA2_MSB 5
+#define RF2G_RF2G1_SHORTLNA2_LSB 5
+#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020
+#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB)
+#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK)
+#define RF2G_RF2G1_SPARE_MSB 4
+#define RF2G_RF2G1_SPARE_LSB 0
+#define RF2G_RF2G1_SPARE_MASK 0x0000001f
+#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB)
+#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK)
+
+#define RF2G_RF2G2_ADDRESS 0x0000002c
+#define RF2G_RF2G2_OFFSET 0x0000002c
+#define RF2G_RF2G2_PDCGLNA_MSB 31
+#define RF2G_RF2G2_PDCGLNA_LSB 31
+#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000
+#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB)
+#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK)
+#define RF2G_RF2G2_PDCGLNABUF_MSB 30
+#define RF2G_RF2G2_PDCGLNABUF_LSB 30
+#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000
+#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB)
+#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK)
+#define RF2G_RF2G2_PDCSLNA_MSB 29
+#define RF2G_RF2G2_PDCSLNA_LSB 29
+#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000
+#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB)
+#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK)
+#define RF2G_RF2G2_PDDIV_MSB 28
+#define RF2G_RF2G2_PDDIV_LSB 28
+#define RF2G_RF2G2_PDDIV_MASK 0x10000000
+#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB)
+#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK)
+#define RF2G_RF2G2_PDPADRV_MSB 27
+#define RF2G_RF2G2_PDPADRV_LSB 27
+#define RF2G_RF2G2_PDPADRV_MASK 0x08000000
+#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB)
+#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK)
+#define RF2G_RF2G2_PDPAOUT_MSB 26
+#define RF2G_RF2G2_PDPAOUT_LSB 26
+#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000
+#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB)
+#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK)
+#define RF2G_RF2G2_PDREGLNA_MSB 25
+#define RF2G_RF2G2_PDREGLNA_LSB 25
+#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000
+#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB)
+#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK)
+#define RF2G_RF2G2_PDREGLO_MSB 24
+#define RF2G_RF2G2_PDREGLO_LSB 24
+#define RF2G_RF2G2_PDREGLO_MASK 0x01000000
+#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB)
+#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK)
+#define RF2G_RF2G2_PDRFGM_MSB 23
+#define RF2G_RF2G2_PDRFGM_LSB 23
+#define RF2G_RF2G2_PDRFGM_MASK 0x00800000
+#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB)
+#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK)
+#define RF2G_RF2G2_PDRXLO_MSB 22
+#define RF2G_RF2G2_PDRXLO_LSB 22
+#define RF2G_RF2G2_PDRXLO_MASK 0x00400000
+#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB)
+#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK)
+#define RF2G_RF2G2_PDTXLO_MSB 21
+#define RF2G_RF2G2_PDTXLO_LSB 21
+#define RF2G_RF2G2_PDTXLO_MASK 0x00200000
+#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB)
+#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK)
+#define RF2G_RF2G2_PDTXMIX_MSB 20
+#define RF2G_RF2G2_PDTXMIX_LSB 20
+#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000
+#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB)
+#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK)
+#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19
+#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19
+#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000
+#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB)
+#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK)
+#define RF2G_RF2G2_REGLO_BYPASS_MSB 18
+#define RF2G_RF2G2_REGLO_BYPASS_LSB 18
+#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000
+#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB)
+#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK)
+#define RF2G_RF2G2_ENABLE_PCB_MSB 17
+#define RF2G_RF2G2_ENABLE_PCB_LSB 17
+#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000
+#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB)
+#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK)
+#define RF2G_RF2G2_SPARE_MSB 16
+#define RF2G_RF2G2_SPARE_LSB 0
+#define RF2G_RF2G2_SPARE_MASK 0x0001ffff
+#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB)
+#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK)
+
+#define TOP_GAIN_ADDRESS 0x00000030
+#define TOP_GAIN_OFFSET 0x00000030
+#define TOP_GAIN_TX6DBLOQGAIN_MSB 31
+#define TOP_GAIN_TX6DBLOQGAIN_LSB 30
+#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000
+#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB)
+#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK)
+#define TOP_GAIN_TX1DBLOQGAIN_MSB 29
+#define TOP_GAIN_TX1DBLOQGAIN_LSB 27
+#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000
+#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB)
+#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK)
+#define TOP_GAIN_TXV2IGAIN_MSB 26
+#define TOP_GAIN_TXV2IGAIN_LSB 25
+#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000
+#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB)
+#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK)
+#define TOP_GAIN_PABUF5GN_MSB 24
+#define TOP_GAIN_PABUF5GN_LSB 24
+#define TOP_GAIN_PABUF5GN_MASK 0x01000000
+#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB)
+#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK)
+#define TOP_GAIN_PADRVGN_MSB 23
+#define TOP_GAIN_PADRVGN_LSB 21
+#define TOP_GAIN_PADRVGN_MASK 0x00e00000
+#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB)
+#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK)
+#define TOP_GAIN_PAOUT2GN_MSB 20
+#define TOP_GAIN_PAOUT2GN_LSB 18
+#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000
+#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB)
+#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK)
+#define TOP_GAIN_LNAON_MSB 17
+#define TOP_GAIN_LNAON_LSB 17
+#define TOP_GAIN_LNAON_MASK 0x00020000
+#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB)
+#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK)
+#define TOP_GAIN_LNAGAIN_MSB 16
+#define TOP_GAIN_LNAGAIN_LSB 13
+#define TOP_GAIN_LNAGAIN_MASK 0x0001e000
+#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB)
+#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK)
+#define TOP_GAIN_RFVGA5GAIN_MSB 12
+#define TOP_GAIN_RFVGA5GAIN_LSB 11
+#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800
+#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB)
+#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK)
+#define TOP_GAIN_RFGMGN_MSB 10
+#define TOP_GAIN_RFGMGN_LSB 8
+#define TOP_GAIN_RFGMGN_MASK 0x00000700
+#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB)
+#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK)
+#define TOP_GAIN_RX6DBLOQGAIN_MSB 7
+#define TOP_GAIN_RX6DBLOQGAIN_LSB 6
+#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0
+#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB)
+#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK)
+#define TOP_GAIN_RX1DBLOQGAIN_MSB 5
+#define TOP_GAIN_RX1DBLOQGAIN_LSB 3
+#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038
+#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB)
+#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK)
+#define TOP_GAIN_RX6DBHIQGAIN_MSB 2
+#define TOP_GAIN_RX6DBHIQGAIN_LSB 1
+#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006
+#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB)
+#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK)
+#define TOP_GAIN_SPARE_MSB 0
+#define TOP_GAIN_SPARE_LSB 0
+#define TOP_GAIN_SPARE_MASK 0x00000001
+#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB)
+#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK)
+
+#define TOP_TOP_ADDRESS 0x00000034
+#define TOP_TOP_OFFSET 0x00000034
+#define TOP_TOP_LOCALTXGAIN_MSB 31
+#define TOP_TOP_LOCALTXGAIN_LSB 31
+#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000
+#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB)
+#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK)
+#define TOP_TOP_LOCALRXGAIN_MSB 30
+#define TOP_TOP_LOCALRXGAIN_LSB 30
+#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000
+#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB)
+#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK)
+#define TOP_TOP_LOCALMODE_MSB 29
+#define TOP_TOP_LOCALMODE_LSB 29
+#define TOP_TOP_LOCALMODE_MASK 0x20000000
+#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB)
+#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK)
+#define TOP_TOP_CALFC_MSB 28
+#define TOP_TOP_CALFC_LSB 28
+#define TOP_TOP_CALFC_MASK 0x10000000
+#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB)
+#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK)
+#define TOP_TOP_CALDC_MSB 27
+#define TOP_TOP_CALDC_LSB 27
+#define TOP_TOP_CALDC_MASK 0x08000000
+#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB)
+#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK)
+#define TOP_TOP_CAL_RESIDUE_MSB 26
+#define TOP_TOP_CAL_RESIDUE_LSB 26
+#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000
+#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB)
+#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK)
+#define TOP_TOP_BMODE_MSB 25
+#define TOP_TOP_BMODE_LSB 25
+#define TOP_TOP_BMODE_MASK 0x02000000
+#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB)
+#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK)
+#define TOP_TOP_SYNTHON_MSB 24
+#define TOP_TOP_SYNTHON_LSB 24
+#define TOP_TOP_SYNTHON_MASK 0x01000000
+#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB)
+#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK)
+#define TOP_TOP_RXON_MSB 23
+#define TOP_TOP_RXON_LSB 23
+#define TOP_TOP_RXON_MASK 0x00800000
+#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB)
+#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK)
+#define TOP_TOP_TXON_MSB 22
+#define TOP_TOP_TXON_LSB 22
+#define TOP_TOP_TXON_MASK 0x00400000
+#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB)
+#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK)
+#define TOP_TOP_PAON_MSB 21
+#define TOP_TOP_PAON_LSB 21
+#define TOP_TOP_PAON_MASK 0x00200000
+#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB)
+#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK)
+#define TOP_TOP_CALTX_MSB 20
+#define TOP_TOP_CALTX_LSB 20
+#define TOP_TOP_CALTX_MASK 0x00100000
+#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB)
+#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK)
+#define TOP_TOP_LOCALADDAC_MSB 19
+#define TOP_TOP_LOCALADDAC_LSB 19
+#define TOP_TOP_LOCALADDAC_MASK 0x00080000
+#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB)
+#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK)
+#define TOP_TOP_PWDPLL_MSB 18
+#define TOP_TOP_PWDPLL_LSB 18
+#define TOP_TOP_PWDPLL_MASK 0x00040000
+#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB)
+#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK)
+#define TOP_TOP_PWDADC_MSB 17
+#define TOP_TOP_PWDADC_LSB 17
+#define TOP_TOP_PWDADC_MASK 0x00020000
+#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB)
+#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK)
+#define TOP_TOP_PWDDAC_MSB 16
+#define TOP_TOP_PWDDAC_LSB 16
+#define TOP_TOP_PWDDAC_MASK 0x00010000
+#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB)
+#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK)
+#define TOP_TOP_LOCALXTAL_MSB 15
+#define TOP_TOP_LOCALXTAL_LSB 15
+#define TOP_TOP_LOCALXTAL_MASK 0x00008000
+#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB)
+#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK)
+#define TOP_TOP_PWDCLKIN_MSB 14
+#define TOP_TOP_PWDCLKIN_LSB 14
+#define TOP_TOP_PWDCLKIN_MASK 0x00004000
+#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB)
+#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK)
+#define TOP_TOP_OSCON_MSB 13
+#define TOP_TOP_OSCON_LSB 13
+#define TOP_TOP_OSCON_MASK 0x00002000
+#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB)
+#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK)
+#define TOP_TOP_SCLKEN_FORCE_MSB 12
+#define TOP_TOP_SCLKEN_FORCE_LSB 12
+#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000
+#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB)
+#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK)
+#define TOP_TOP_SYNTHON_FORCE_MSB 11
+#define TOP_TOP_SYNTHON_FORCE_LSB 11
+#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800
+#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB)
+#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK)
+#define TOP_TOP_PDBIAS_MSB 10
+#define TOP_TOP_PDBIAS_LSB 10
+#define TOP_TOP_PDBIAS_MASK 0x00000400
+#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB)
+#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK)
+#define TOP_TOP_DATAOUTSEL_MSB 9
+#define TOP_TOP_DATAOUTSEL_LSB 8
+#define TOP_TOP_DATAOUTSEL_MASK 0x00000300
+#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB)
+#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK)
+#define TOP_TOP_REVID_MSB 7
+#define TOP_TOP_REVID_LSB 5
+#define TOP_TOP_REVID_MASK 0x000000e0
+#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB)
+#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK)
+#define TOP_TOP_INT2PAD_MSB 4
+#define TOP_TOP_INT2PAD_LSB 4
+#define TOP_TOP_INT2PAD_MASK 0x00000010
+#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB)
+#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK)
+#define TOP_TOP_INTH2PAD_MSB 3
+#define TOP_TOP_INTH2PAD_LSB 3
+#define TOP_TOP_INTH2PAD_MASK 0x00000008
+#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB)
+#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK)
+#define TOP_TOP_PAD2GND_MSB 2
+#define TOP_TOP_PAD2GND_LSB 2
+#define TOP_TOP_PAD2GND_MASK 0x00000004
+#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB)
+#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK)
+#define TOP_TOP_INT2GND_MSB 1
+#define TOP_TOP_INT2GND_LSB 1
+#define TOP_TOP_INT2GND_MASK 0x00000002
+#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB)
+#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK)
+#define TOP_TOP_FORCE_XPAON_MSB 0
+#define TOP_TOP_FORCE_XPAON_LSB 0
+#define TOP_TOP_FORCE_XPAON_MASK 0x00000001
+#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB)
+#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK)
+
+#define BIAS_BIAS_SEL_ADDRESS 0x00000038
+#define BIAS_BIAS_SEL_OFFSET 0x00000038
+#define BIAS_BIAS_SEL_PADON_MSB 31
+#define BIAS_BIAS_SEL_PADON_LSB 31
+#define BIAS_BIAS_SEL_PADON_MASK 0x80000000
+#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB)
+#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK)
+#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30
+#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25
+#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000
+#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB)
+#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK)
+#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24
+#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21
+#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000
+#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_SPARE_MSB 20
+#define BIAS_BIAS_SEL_SPARE_LSB 20
+#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000
+#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001
+#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK)
+
+#define BIAS_BIAS1_ADDRESS 0x0000003c
+#define BIAS_BIAS1_OFFSET 0x0000003c
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31
+#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000
+#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB)
+#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK)
+#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28
+#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26
+#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000
+#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB)
+#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25
+#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000
+#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22
+#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000
+#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000
+#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000
+#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000
+#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13
+#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800
+#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7
+#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5
+#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0
+#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB)
+#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK)
+#define BIAS_BIAS1_SPARE_MSB 1
+#define BIAS_BIAS1_SPARE_LSB 0
+#define BIAS_BIAS1_SPARE_MASK 0x00000003
+#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB)
+#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK)
+
+#define BIAS_BIAS2_ADDRESS 0x00000040
+#define BIAS_BIAS2_OFFSET 0x00000040
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31
+#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000
+#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB)
+#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK)
+#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28
+#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26
+#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000
+#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB)
+#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25
+#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000
+#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IRPLL25_MSB 22
+#define BIAS_BIAS2_PWD_IRPLL25_LSB 22
+#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000
+#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB)
+#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK)
+#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21
+#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19
+#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000
+#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB)
+#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK)
+#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18
+#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16
+#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000
+#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB)
+#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK)
+#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15
+#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13
+#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000
+#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB)
+#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK)
+#define BIAS_BIAS2_PWD_IRLDO25_MSB 12
+#define BIAS_BIAS2_PWD_IRLDO25_LSB 12
+#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000
+#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB)
+#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8
+#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0
+#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK)
+
+#define BIAS_BIAS3_ADDRESS 0x00000044
+#define BIAS_BIAS3_OFFSET 0x00000044
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB)
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK)
+#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28
+#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26
+#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000
+#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB)
+#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK)
+#define BIAS_BIAS3_PWD_ICDAC50_MSB 25
+#define BIAS_BIAS3_PWD_ICDAC50_LSB 23
+#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000
+#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB)
+#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK)
+#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22
+#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22
+#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000
+#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_ICBB50_MSB 21
+#define BIAS_BIAS3_PWD_ICBB50_LSB 21
+#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000
+#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB)
+#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK)
+#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20
+#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18
+#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000
+#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB)
+#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK)
+#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17
+#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17
+#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000
+#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_IRBB50_MSB 16
+#define BIAS_BIAS3_PWD_IRBB50_LSB 16
+#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000
+#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB)
+#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15
+#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13
+#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000
+#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12
+#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10
+#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00
+#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9
+#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7
+#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380
+#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6
+#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4
+#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070
+#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3
+#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e
+#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK)
+#define BIAS_BIAS3_SPARE_MSB 0
+#define BIAS_BIAS3_SPARE_LSB 0
+#define BIAS_BIAS3_SPARE_MASK 0x00000001
+#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB)
+#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK)
+
+#define TXPC_TXPC_ADDRESS 0x00000048
+#define TXPC_TXPC_OFFSET 0x00000048
+#define TXPC_TXPC_SELINTPD_MSB 31
+#define TXPC_TXPC_SELINTPD_LSB 31
+#define TXPC_TXPC_SELINTPD_MASK 0x80000000
+#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB)
+#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK)
+#define TXPC_TXPC_TEST_MSB 30
+#define TXPC_TXPC_TEST_LSB 30
+#define TXPC_TXPC_TEST_MASK 0x40000000
+#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB)
+#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK)
+#define TXPC_TXPC_TESTGAIN_MSB 29
+#define TXPC_TXPC_TESTGAIN_LSB 28
+#define TXPC_TXPC_TESTGAIN_MASK 0x30000000
+#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB)
+#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK)
+#define TXPC_TXPC_TESTDAC_MSB 27
+#define TXPC_TXPC_TESTDAC_LSB 22
+#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000
+#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB)
+#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK)
+#define TXPC_TXPC_TESTPWDPC_MSB 21
+#define TXPC_TXPC_TESTPWDPC_LSB 21
+#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000
+#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB)
+#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK)
+#define TXPC_TXPC_CURHALF_MSB 20
+#define TXPC_TXPC_CURHALF_LSB 20
+#define TXPC_TXPC_CURHALF_MASK 0x00100000
+#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB)
+#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK)
+#define TXPC_TXPC_NEGOUT_MSB 19
+#define TXPC_TXPC_NEGOUT_LSB 19
+#define TXPC_TXPC_NEGOUT_MASK 0x00080000
+#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB)
+#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK)
+#define TXPC_TXPC_CLKDELAY_MSB 18
+#define TXPC_TXPC_CLKDELAY_LSB 18
+#define TXPC_TXPC_CLKDELAY_MASK 0x00040000
+#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB)
+#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK)
+#define TXPC_TXPC_SELMODREF_MSB 17
+#define TXPC_TXPC_SELMODREF_LSB 17
+#define TXPC_TXPC_SELMODREF_MASK 0x00020000
+#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB)
+#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK)
+#define TXPC_TXPC_SELCMOUT_MSB 16
+#define TXPC_TXPC_SELCMOUT_LSB 16
+#define TXPC_TXPC_SELCMOUT_MASK 0x00010000
+#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB)
+#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK)
+#define TXPC_TXPC_TSMODE_MSB 15
+#define TXPC_TXPC_TSMODE_LSB 14
+#define TXPC_TXPC_TSMODE_MASK 0x0000c000
+#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB)
+#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK)
+#define TXPC_TXPC_N_MSB 13
+#define TXPC_TXPC_N_LSB 6
+#define TXPC_TXPC_N_MASK 0x00003fc0
+#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB)
+#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK)
+#define TXPC_TXPC_ON1STSYNTHON_MSB 5
+#define TXPC_TXPC_ON1STSYNTHON_LSB 5
+#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020
+#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB)
+#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK)
+#define TXPC_TXPC_SELINIT_MSB 4
+#define TXPC_TXPC_SELINIT_LSB 3
+#define TXPC_TXPC_SELINIT_MASK 0x00000018
+#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB)
+#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK)
+#define TXPC_TXPC_SELCOUNT_MSB 2
+#define TXPC_TXPC_SELCOUNT_LSB 2
+#define TXPC_TXPC_SELCOUNT_MASK 0x00000004
+#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB)
+#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK)
+#define TXPC_TXPC_ATBSEL_MSB 1
+#define TXPC_TXPC_ATBSEL_LSB 0
+#define TXPC_TXPC_ATBSEL_MASK 0x00000003
+#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB)
+#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK)
+
+#define TXPC_MISC_ADDRESS 0x0000004c
+#define TXPC_MISC_OFFSET 0x0000004c
+#define TXPC_MISC_FLIPBMODE_MSB 31
+#define TXPC_MISC_FLIPBMODE_LSB 31
+#define TXPC_MISC_FLIPBMODE_MASK 0x80000000
+#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB)
+#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK)
+#define TXPC_MISC_LEVEL_MSB 30
+#define TXPC_MISC_LEVEL_LSB 29
+#define TXPC_MISC_LEVEL_MASK 0x60000000
+#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB)
+#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK)
+#define TXPC_MISC_LDO_TEST_MODE_MSB 28
+#define TXPC_MISC_LDO_TEST_MODE_LSB 28
+#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000
+#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB)
+#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK)
+#define TXPC_MISC_NOTCXODET_MSB 27
+#define TXPC_MISC_NOTCXODET_LSB 27
+#define TXPC_MISC_NOTCXODET_MASK 0x08000000
+#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB)
+#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK)
+#define TXPC_MISC_PWDCLKIND_MSB 26
+#define TXPC_MISC_PWDCLKIND_LSB 26
+#define TXPC_MISC_PWDCLKIND_MASK 0x04000000
+#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB)
+#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK)
+#define TXPC_MISC_PWDXINPAD_MSB 25
+#define TXPC_MISC_PWDXINPAD_LSB 25
+#define TXPC_MISC_PWDXINPAD_MASK 0x02000000
+#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB)
+#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK)
+#define TXPC_MISC_LOCALBIAS_MSB 24
+#define TXPC_MISC_LOCALBIAS_LSB 24
+#define TXPC_MISC_LOCALBIAS_MASK 0x01000000
+#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB)
+#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK)
+#define TXPC_MISC_LOCALBIAS2X_MSB 23
+#define TXPC_MISC_LOCALBIAS2X_LSB 23
+#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000
+#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB)
+#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK)
+#define TXPC_MISC_SELTSP_MSB 22
+#define TXPC_MISC_SELTSP_LSB 22
+#define TXPC_MISC_SELTSP_MASK 0x00400000
+#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB)
+#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK)
+#define TXPC_MISC_SELTSN_MSB 21
+#define TXPC_MISC_SELTSN_LSB 21
+#define TXPC_MISC_SELTSN_MASK 0x00200000
+#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB)
+#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK)
+#define TXPC_MISC_SPARE_A_MSB 20
+#define TXPC_MISC_SPARE_A_LSB 18
+#define TXPC_MISC_SPARE_A_MASK 0x001c0000
+#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB)
+#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK)
+#define TXPC_MISC_DECOUT_MSB 17
+#define TXPC_MISC_DECOUT_LSB 8
+#define TXPC_MISC_DECOUT_MASK 0x0003ff00
+#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB)
+#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK)
+#define TXPC_MISC_XTALDIV_MSB 7
+#define TXPC_MISC_XTALDIV_LSB 6
+#define TXPC_MISC_XTALDIV_MASK 0x000000c0
+#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB)
+#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK)
+#define TXPC_MISC_SPARE_MSB 5
+#define TXPC_MISC_SPARE_LSB 0
+#define TXPC_MISC_SPARE_MASK 0x0000003f
+#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB)
+#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK)
+
+#define RXTXBB_RXTXBB1_ADDRESS 0x00000050
+#define RXTXBB_RXTXBB1_OFFSET 0x00000050
+#define RXTXBB_RXTXBB1_SPARE_MSB 31
+#define RXTXBB_RXTXBB1_SPARE_LSB 19
+#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000
+#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB)
+#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK)
+#define RXTXBB_RXTXBB1_FNOTCH_MSB 18
+#define RXTXBB_RXTXBB1_FNOTCH_LSB 17
+#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000
+#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB)
+#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK)
+#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16
+#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9
+#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00
+#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB)
+#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK)
+#define RXTXBB_RXTXBB1_PDV2I_MSB 7
+#define RXTXBB_RXTXBB1_PDV2I_LSB 7
+#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080
+#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB)
+#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK)
+#define RXTXBB_RXTXBB1_PDI2V_MSB 6
+#define RXTXBB_RXTXBB1_PDI2V_LSB 6
+#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040
+#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB)
+#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK)
+#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5
+#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5
+#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020
+#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB)
+#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK)
+#define RXTXBB_RXTXBB1_PDLOQ_MSB 1
+#define RXTXBB_RXTXBB1_PDLOQ_LSB 1
+#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002
+#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDHIQ_MSB 0
+#define RXTXBB_RXTXBB1_PDHIQ_LSB 0
+#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001
+#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK)
+
+#define RXTXBB_RXTXBB2_ADDRESS 0x00000054
+#define RXTXBB_RXTXBB2_OFFSET 0x00000054
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK)
+#define RXTXBB_RXTXBB2_SPARE_MSB 22
+#define RXTXBB_RXTXBB2_SPARE_LSB 21
+#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000
+#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB)
+#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000
+#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19
+#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19
+#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000
+#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK)
+#define RXTXBB_RXTXBB2_CMSEL_MSB 14
+#define RXTXBB_RXTXBB2_CMSEL_LSB 13
+#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000
+#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB)
+#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK)
+#define RXTXBB_RXTXBB2_FILTERFC_MSB 12
+#define RXTXBB_RXTXBB2_FILTERFC_LSB 8
+#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00
+#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB)
+#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK)
+
+#define RXTXBB_RXTXBB3_ADDRESS 0x00000058
+#define RXTXBB_RXTXBB3_OFFSET 0x00000058
+#define RXTXBB_RXTXBB3_SPARE_MSB 31
+#define RXTXBB_RXTXBB3_SPARE_LSB 27
+#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000
+#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB)
+#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK)
+
+#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c
+#define RXTXBB_RXTXBB4_OFFSET 0x0000005c
+#define RXTXBB_RXTXBB4_SPARE_MSB 31
+#define RXTXBB_RXTXBB4_SPARE_LSB 31
+#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000
+#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB)
+#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000
+#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29
+#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000
+#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK)
+
+#define ADDAC_ADDAC1_ADDRESS 0x00000060
+#define ADDAC_ADDAC1_OFFSET 0x00000060
+#define ADDAC_ADDAC1_PLL_SVREG_MSB 31
+#define ADDAC_ADDAC1_PLL_SVREG_LSB 31
+#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000
+#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB)
+#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK)
+#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30
+#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28
+#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000
+#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB)
+#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK)
+#define ADDAC_ADDAC1_PLL_ATB_MSB 27
+#define ADDAC_ADDAC1_PLL_ATB_LSB 26
+#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000
+#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB)
+#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK)
+#define ADDAC_ADDAC1_PLL_ICP_MSB 25
+#define ADDAC_ADDAC1_PLL_ICP_LSB 23
+#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000
+#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB)
+#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK)
+#define ADDAC_ADDAC1_PLL_FILTER_MSB 22
+#define ADDAC_ADDAC1_PLL_FILTER_LSB 15
+#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000
+#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB)
+#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK)
+#define ADDAC_ADDAC1_PWDPLL_MSB 14
+#define ADDAC_ADDAC1_PWDPLL_LSB 14
+#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000
+#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB)
+#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK)
+#define ADDAC_ADDAC1_PWDADC_MSB 13
+#define ADDAC_ADDAC1_PWDADC_LSB 13
+#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000
+#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB)
+#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK)
+#define ADDAC_ADDAC1_PWDDAC_MSB 12
+#define ADDAC_ADDAC1_PWDDAC_LSB 12
+#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000
+#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB)
+#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK)
+#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11
+#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11
+#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800
+#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB)
+#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK)
+#define ADDAC_ADDAC1_SELMANPWDS_MSB 10
+#define ADDAC_ADDAC1_SELMANPWDS_LSB 10
+#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400
+#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB)
+#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200
+#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK)
+#define ADDAC_ADDAC1_CM_SEL_MSB 8
+#define ADDAC_ADDAC1_CM_SEL_LSB 7
+#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180
+#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB)
+#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK)
+#define ADDAC_ADDAC1_SPARE_MSB 5
+#define ADDAC_ADDAC1_SPARE_LSB 0
+#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f
+#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB)
+#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_reg_reg_s {
+ volatile unsigned int synth_synth1;
+ volatile unsigned int synth_synth2;
+ volatile unsigned int synth_synth3;
+ volatile unsigned int synth_synth4;
+ volatile unsigned int synth_synth5;
+ volatile unsigned int synth_synth6;
+ volatile unsigned int synth_synth7;
+ volatile unsigned int synth_synth8;
+ volatile unsigned int rf5g_rf5g1;
+ volatile unsigned int rf5g_rf5g2;
+ volatile unsigned int rf2g_rf2g1;
+ volatile unsigned int rf2g_rf2g2;
+ volatile unsigned int top_gain;
+ volatile unsigned int top_top;
+ volatile unsigned int bias_bias_sel;
+ volatile unsigned int bias_bias1;
+ volatile unsigned int bias_bias2;
+ volatile unsigned int bias_bias3;
+ volatile unsigned int txpc_txpc;
+ volatile unsigned int txpc_misc;
+ volatile unsigned int rxtxbb_rxtxbb1;
+ volatile unsigned int rxtxbb_rxtxbb2;
+ volatile unsigned int rxtxbb_rxtxbb3;
+ volatile unsigned int rxtxbb_rxtxbb4;
+ volatile unsigned int addac_addac1;
+} analog_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h
new file mode 100644
index 000000000000..bba885ed1f08
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h
@@ -0,0 +1,32 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_MAP_H_
+#define _APB_MAP_H_
+
+#define RTC_BASE_ADDRESS 0x00004000
+#define VMC_BASE_ADDRESS 0x00008000
+#define UART_BASE_ADDRESS 0x0000c000
+#define SI_BASE_ADDRESS 0x00010000
+#define GPIO_BASE_ADDRESS 0x00014000
+#define MBOX_BASE_ADDRESS 0x00018000
+#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
+#define MAC_BASE_ADDRESS 0x00020000
+
+#endif /* _APB_MAP_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h
new file mode 100644
index 000000000000..de88e8cc91bb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h
@@ -0,0 +1,996 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_REG_REG_H_
+#define _GPIO_REG_REG_H_
+
+#define GPIO_OUT_ADDRESS 0x00000000
+#define GPIO_OUT_OFFSET 0x00000000
+#define GPIO_OUT_DATA_MSB 17
+#define GPIO_OUT_DATA_LSB 0
+#define GPIO_OUT_DATA_MASK 0x0003ffff
+#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
+#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
+
+#define GPIO_OUT_W1TS_ADDRESS 0x00000004
+#define GPIO_OUT_W1TS_OFFSET 0x00000004
+#define GPIO_OUT_W1TS_DATA_MSB 17
+#define GPIO_OUT_W1TS_DATA_LSB 0
+#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff
+#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
+#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
+
+#define GPIO_OUT_W1TC_ADDRESS 0x00000008
+#define GPIO_OUT_W1TC_OFFSET 0x00000008
+#define GPIO_OUT_W1TC_DATA_MSB 17
+#define GPIO_OUT_W1TC_DATA_LSB 0
+#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff
+#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
+#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
+
+#define GPIO_ENABLE_ADDRESS 0x0000000c
+#define GPIO_ENABLE_OFFSET 0x0000000c
+#define GPIO_ENABLE_DATA_MSB 17
+#define GPIO_ENABLE_DATA_LSB 0
+#define GPIO_ENABLE_DATA_MASK 0x0003ffff
+#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
+#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
+
+#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010
+#define GPIO_ENABLE_W1TS_OFFSET 0x00000010
+#define GPIO_ENABLE_W1TS_DATA_MSB 17
+#define GPIO_ENABLE_W1TS_DATA_LSB 0
+#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff
+#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
+#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014
+#define GPIO_ENABLE_W1TC_OFFSET 0x00000014
+#define GPIO_ENABLE_W1TC_DATA_MSB 17
+#define GPIO_ENABLE_W1TC_DATA_LSB 0
+#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff
+#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
+#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define GPIO_IN_ADDRESS 0x00000018
+#define GPIO_IN_OFFSET 0x00000018
+#define GPIO_IN_DATA_MSB 17
+#define GPIO_IN_DATA_LSB 0
+#define GPIO_IN_DATA_MASK 0x0003ffff
+#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
+#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
+
+#define GPIO_STATUS_ADDRESS 0x0000001c
+#define GPIO_STATUS_OFFSET 0x0000001c
+#define GPIO_STATUS_INTERRUPT_MSB 17
+#define GPIO_STATUS_INTERRUPT_LSB 0
+#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff
+#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
+#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TS_ADDRESS 0x00000020
+#define GPIO_STATUS_W1TS_OFFSET 0x00000020
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TC_ADDRESS 0x00000024
+#define GPIO_STATUS_W1TC_OFFSET 0x00000024
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define GPIO_PIN0_ADDRESS 0x00000028
+#define GPIO_PIN0_OFFSET 0x00000028
+#define GPIO_PIN0_CONFIG_MSB 12
+#define GPIO_PIN0_CONFIG_LSB 11
+#define GPIO_PIN0_CONFIG_MASK 0x00001800
+#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
+#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN0_INT_TYPE_MSB 9
+#define GPIO_PIN0_INT_TYPE_LSB 7
+#define GPIO_PIN0_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
+#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
+#define GPIO_PIN0_PAD_DRIVER_MSB 2
+#define GPIO_PIN0_PAD_DRIVER_LSB 2
+#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
+#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
+#define GPIO_PIN0_SOURCE_MSB 0
+#define GPIO_PIN0_SOURCE_LSB 0
+#define GPIO_PIN0_SOURCE_MASK 0x00000001
+#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
+#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
+
+#define GPIO_PIN1_ADDRESS 0x0000002c
+#define GPIO_PIN1_OFFSET 0x0000002c
+#define GPIO_PIN1_CONFIG_MSB 12
+#define GPIO_PIN1_CONFIG_LSB 11
+#define GPIO_PIN1_CONFIG_MASK 0x00001800
+#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
+#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN1_INT_TYPE_MSB 9
+#define GPIO_PIN1_INT_TYPE_LSB 7
+#define GPIO_PIN1_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
+#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
+#define GPIO_PIN1_PAD_DRIVER_MSB 2
+#define GPIO_PIN1_PAD_DRIVER_LSB 2
+#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
+#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
+#define GPIO_PIN1_SOURCE_MSB 0
+#define GPIO_PIN1_SOURCE_LSB 0
+#define GPIO_PIN1_SOURCE_MASK 0x00000001
+#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
+#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
+
+#define GPIO_PIN2_ADDRESS 0x00000030
+#define GPIO_PIN2_OFFSET 0x00000030
+#define GPIO_PIN2_CONFIG_MSB 12
+#define GPIO_PIN2_CONFIG_LSB 11
+#define GPIO_PIN2_CONFIG_MASK 0x00001800
+#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
+#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN2_INT_TYPE_MSB 9
+#define GPIO_PIN2_INT_TYPE_LSB 7
+#define GPIO_PIN2_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
+#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
+#define GPIO_PIN2_PAD_DRIVER_MSB 2
+#define GPIO_PIN2_PAD_DRIVER_LSB 2
+#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
+#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
+#define GPIO_PIN2_SOURCE_MSB 0
+#define GPIO_PIN2_SOURCE_LSB 0
+#define GPIO_PIN2_SOURCE_MASK 0x00000001
+#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
+#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
+
+#define GPIO_PIN3_ADDRESS 0x00000034
+#define GPIO_PIN3_OFFSET 0x00000034
+#define GPIO_PIN3_CONFIG_MSB 12
+#define GPIO_PIN3_CONFIG_LSB 11
+#define GPIO_PIN3_CONFIG_MASK 0x00001800
+#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
+#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN3_INT_TYPE_MSB 9
+#define GPIO_PIN3_INT_TYPE_LSB 7
+#define GPIO_PIN3_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
+#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
+#define GPIO_PIN3_PAD_DRIVER_MSB 2
+#define GPIO_PIN3_PAD_DRIVER_LSB 2
+#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
+#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
+#define GPIO_PIN3_SOURCE_MSB 0
+#define GPIO_PIN3_SOURCE_LSB 0
+#define GPIO_PIN3_SOURCE_MASK 0x00000001
+#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
+#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
+
+#define GPIO_PIN4_ADDRESS 0x00000038
+#define GPIO_PIN4_OFFSET 0x00000038
+#define GPIO_PIN4_CONFIG_MSB 12
+#define GPIO_PIN4_CONFIG_LSB 11
+#define GPIO_PIN4_CONFIG_MASK 0x00001800
+#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
+#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN4_INT_TYPE_MSB 9
+#define GPIO_PIN4_INT_TYPE_LSB 7
+#define GPIO_PIN4_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
+#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
+#define GPIO_PIN4_PAD_DRIVER_MSB 2
+#define GPIO_PIN4_PAD_DRIVER_LSB 2
+#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
+#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
+#define GPIO_PIN4_SOURCE_MSB 0
+#define GPIO_PIN4_SOURCE_LSB 0
+#define GPIO_PIN4_SOURCE_MASK 0x00000001
+#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
+#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
+
+#define GPIO_PIN5_ADDRESS 0x0000003c
+#define GPIO_PIN5_OFFSET 0x0000003c
+#define GPIO_PIN5_CONFIG_MSB 12
+#define GPIO_PIN5_CONFIG_LSB 11
+#define GPIO_PIN5_CONFIG_MASK 0x00001800
+#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
+#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN5_INT_TYPE_MSB 9
+#define GPIO_PIN5_INT_TYPE_LSB 7
+#define GPIO_PIN5_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
+#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
+#define GPIO_PIN5_PAD_DRIVER_MSB 2
+#define GPIO_PIN5_PAD_DRIVER_LSB 2
+#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
+#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
+#define GPIO_PIN5_SOURCE_MSB 0
+#define GPIO_PIN5_SOURCE_LSB 0
+#define GPIO_PIN5_SOURCE_MASK 0x00000001
+#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
+#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
+
+#define GPIO_PIN6_ADDRESS 0x00000040
+#define GPIO_PIN6_OFFSET 0x00000040
+#define GPIO_PIN6_CONFIG_MSB 12
+#define GPIO_PIN6_CONFIG_LSB 11
+#define GPIO_PIN6_CONFIG_MASK 0x00001800
+#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
+#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN6_INT_TYPE_MSB 9
+#define GPIO_PIN6_INT_TYPE_LSB 7
+#define GPIO_PIN6_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
+#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
+#define GPIO_PIN6_PAD_DRIVER_MSB 2
+#define GPIO_PIN6_PAD_DRIVER_LSB 2
+#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
+#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
+#define GPIO_PIN6_SOURCE_MSB 0
+#define GPIO_PIN6_SOURCE_LSB 0
+#define GPIO_PIN6_SOURCE_MASK 0x00000001
+#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
+#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
+
+#define GPIO_PIN7_ADDRESS 0x00000044
+#define GPIO_PIN7_OFFSET 0x00000044
+#define GPIO_PIN7_CONFIG_MSB 12
+#define GPIO_PIN7_CONFIG_LSB 11
+#define GPIO_PIN7_CONFIG_MASK 0x00001800
+#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
+#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN7_INT_TYPE_MSB 9
+#define GPIO_PIN7_INT_TYPE_LSB 7
+#define GPIO_PIN7_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
+#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
+#define GPIO_PIN7_PAD_DRIVER_MSB 2
+#define GPIO_PIN7_PAD_DRIVER_LSB 2
+#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
+#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
+#define GPIO_PIN7_SOURCE_MSB 0
+#define GPIO_PIN7_SOURCE_LSB 0
+#define GPIO_PIN7_SOURCE_MASK 0x00000001
+#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
+#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
+
+#define GPIO_PIN8_ADDRESS 0x00000048
+#define GPIO_PIN8_OFFSET 0x00000048
+#define GPIO_PIN8_CONFIG_MSB 12
+#define GPIO_PIN8_CONFIG_LSB 11
+#define GPIO_PIN8_CONFIG_MASK 0x00001800
+#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
+#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN8_INT_TYPE_MSB 9
+#define GPIO_PIN8_INT_TYPE_LSB 7
+#define GPIO_PIN8_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
+#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
+#define GPIO_PIN8_PAD_DRIVER_MSB 2
+#define GPIO_PIN8_PAD_DRIVER_LSB 2
+#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
+#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
+#define GPIO_PIN8_SOURCE_MSB 0
+#define GPIO_PIN8_SOURCE_LSB 0
+#define GPIO_PIN8_SOURCE_MASK 0x00000001
+#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
+#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
+
+#define GPIO_PIN9_ADDRESS 0x0000004c
+#define GPIO_PIN9_OFFSET 0x0000004c
+#define GPIO_PIN9_CONFIG_MSB 12
+#define GPIO_PIN9_CONFIG_LSB 11
+#define GPIO_PIN9_CONFIG_MASK 0x00001800
+#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
+#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN9_INT_TYPE_MSB 9
+#define GPIO_PIN9_INT_TYPE_LSB 7
+#define GPIO_PIN9_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
+#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
+#define GPIO_PIN9_PAD_DRIVER_MSB 2
+#define GPIO_PIN9_PAD_DRIVER_LSB 2
+#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
+#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
+#define GPIO_PIN9_SOURCE_MSB 0
+#define GPIO_PIN9_SOURCE_LSB 0
+#define GPIO_PIN9_SOURCE_MASK 0x00000001
+#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
+#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
+
+#define GPIO_PIN10_ADDRESS 0x00000050
+#define GPIO_PIN10_OFFSET 0x00000050
+#define GPIO_PIN10_CONFIG_MSB 12
+#define GPIO_PIN10_CONFIG_LSB 11
+#define GPIO_PIN10_CONFIG_MASK 0x00001800
+#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
+#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN10_INT_TYPE_MSB 9
+#define GPIO_PIN10_INT_TYPE_LSB 7
+#define GPIO_PIN10_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
+#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
+#define GPIO_PIN10_PAD_DRIVER_MSB 2
+#define GPIO_PIN10_PAD_DRIVER_LSB 2
+#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
+#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
+#define GPIO_PIN10_SOURCE_MSB 0
+#define GPIO_PIN10_SOURCE_LSB 0
+#define GPIO_PIN10_SOURCE_MASK 0x00000001
+#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
+#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
+
+#define GPIO_PIN11_ADDRESS 0x00000054
+#define GPIO_PIN11_OFFSET 0x00000054
+#define GPIO_PIN11_CONFIG_MSB 12
+#define GPIO_PIN11_CONFIG_LSB 11
+#define GPIO_PIN11_CONFIG_MASK 0x00001800
+#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
+#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN11_INT_TYPE_MSB 9
+#define GPIO_PIN11_INT_TYPE_LSB 7
+#define GPIO_PIN11_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
+#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
+#define GPIO_PIN11_PAD_DRIVER_MSB 2
+#define GPIO_PIN11_PAD_DRIVER_LSB 2
+#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
+#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
+#define GPIO_PIN11_SOURCE_MSB 0
+#define GPIO_PIN11_SOURCE_LSB 0
+#define GPIO_PIN11_SOURCE_MASK 0x00000001
+#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
+#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
+
+#define GPIO_PIN12_ADDRESS 0x00000058
+#define GPIO_PIN12_OFFSET 0x00000058
+#define GPIO_PIN12_CONFIG_MSB 12
+#define GPIO_PIN12_CONFIG_LSB 11
+#define GPIO_PIN12_CONFIG_MASK 0x00001800
+#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
+#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN12_INT_TYPE_MSB 9
+#define GPIO_PIN12_INT_TYPE_LSB 7
+#define GPIO_PIN12_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
+#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
+#define GPIO_PIN12_PAD_DRIVER_MSB 2
+#define GPIO_PIN12_PAD_DRIVER_LSB 2
+#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
+#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
+#define GPIO_PIN12_SOURCE_MSB 0
+#define GPIO_PIN12_SOURCE_LSB 0
+#define GPIO_PIN12_SOURCE_MASK 0x00000001
+#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
+#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
+
+#define GPIO_PIN13_ADDRESS 0x0000005c
+#define GPIO_PIN13_OFFSET 0x0000005c
+#define GPIO_PIN13_CONFIG_MSB 12
+#define GPIO_PIN13_CONFIG_LSB 11
+#define GPIO_PIN13_CONFIG_MASK 0x00001800
+#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
+#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN13_INT_TYPE_MSB 9
+#define GPIO_PIN13_INT_TYPE_LSB 7
+#define GPIO_PIN13_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
+#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
+#define GPIO_PIN13_PAD_DRIVER_MSB 2
+#define GPIO_PIN13_PAD_DRIVER_LSB 2
+#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
+#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
+#define GPIO_PIN13_SOURCE_MSB 0
+#define GPIO_PIN13_SOURCE_LSB 0
+#define GPIO_PIN13_SOURCE_MASK 0x00000001
+#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
+#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
+
+#define GPIO_PIN14_ADDRESS 0x00000060
+#define GPIO_PIN14_OFFSET 0x00000060
+#define GPIO_PIN14_CONFIG_MSB 12
+#define GPIO_PIN14_CONFIG_LSB 11
+#define GPIO_PIN14_CONFIG_MASK 0x00001800
+#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
+#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN14_INT_TYPE_MSB 9
+#define GPIO_PIN14_INT_TYPE_LSB 7
+#define GPIO_PIN14_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
+#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
+#define GPIO_PIN14_PAD_DRIVER_MSB 2
+#define GPIO_PIN14_PAD_DRIVER_LSB 2
+#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
+#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
+#define GPIO_PIN14_SOURCE_MSB 0
+#define GPIO_PIN14_SOURCE_LSB 0
+#define GPIO_PIN14_SOURCE_MASK 0x00000001
+#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
+#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
+
+#define GPIO_PIN15_ADDRESS 0x00000064
+#define GPIO_PIN15_OFFSET 0x00000064
+#define GPIO_PIN15_CONFIG_MSB 12
+#define GPIO_PIN15_CONFIG_LSB 11
+#define GPIO_PIN15_CONFIG_MASK 0x00001800
+#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
+#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN15_INT_TYPE_MSB 9
+#define GPIO_PIN15_INT_TYPE_LSB 7
+#define GPIO_PIN15_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
+#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
+#define GPIO_PIN15_PAD_DRIVER_MSB 2
+#define GPIO_PIN15_PAD_DRIVER_LSB 2
+#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
+#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
+#define GPIO_PIN15_SOURCE_MSB 0
+#define GPIO_PIN15_SOURCE_LSB 0
+#define GPIO_PIN15_SOURCE_MASK 0x00000001
+#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
+#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
+
+#define GPIO_PIN16_ADDRESS 0x00000068
+#define GPIO_PIN16_OFFSET 0x00000068
+#define GPIO_PIN16_CONFIG_MSB 12
+#define GPIO_PIN16_CONFIG_LSB 11
+#define GPIO_PIN16_CONFIG_MASK 0x00001800
+#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
+#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN16_INT_TYPE_MSB 9
+#define GPIO_PIN16_INT_TYPE_LSB 7
+#define GPIO_PIN16_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
+#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
+#define GPIO_PIN16_PAD_DRIVER_MSB 2
+#define GPIO_PIN16_PAD_DRIVER_LSB 2
+#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
+#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
+#define GPIO_PIN16_SOURCE_MSB 0
+#define GPIO_PIN16_SOURCE_LSB 0
+#define GPIO_PIN16_SOURCE_MASK 0x00000001
+#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
+#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
+
+#define GPIO_PIN17_ADDRESS 0x0000006c
+#define GPIO_PIN17_OFFSET 0x0000006c
+#define GPIO_PIN17_CONFIG_MSB 12
+#define GPIO_PIN17_CONFIG_LSB 11
+#define GPIO_PIN17_CONFIG_MASK 0x00001800
+#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
+#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN17_INT_TYPE_MSB 9
+#define GPIO_PIN17_INT_TYPE_LSB 7
+#define GPIO_PIN17_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
+#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
+#define GPIO_PIN17_PAD_DRIVER_MSB 2
+#define GPIO_PIN17_PAD_DRIVER_LSB 2
+#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
+#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
+#define GPIO_PIN17_SOURCE_MSB 0
+#define GPIO_PIN17_SOURCE_LSB 0
+#define GPIO_PIN17_SOURCE_MASK 0x00000001
+#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
+#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
+
+#define SDIO_PIN_ADDRESS 0x00000070
+#define SDIO_PIN_OFFSET 0x00000070
+#define SDIO_PIN_PAD_PULL_MSB 3
+#define SDIO_PIN_PAD_PULL_LSB 2
+#define SDIO_PIN_PAD_PULL_MASK 0x0000000c
+#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
+#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
+#define SDIO_PIN_PAD_STRENGTH_MSB 1
+#define SDIO_PIN_PAD_STRENGTH_LSB 0
+#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003
+#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
+#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
+
+#define CLK_REQ_PIN_ADDRESS 0x00000074
+#define CLK_REQ_PIN_OFFSET 0x00000074
+#define CLK_REQ_PIN_ATE_OE_L_MSB 4
+#define CLK_REQ_PIN_ATE_OE_L_LSB 4
+#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010
+#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
+#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
+#define CLK_REQ_PIN_PAD_PULL_MSB 3
+#define CLK_REQ_PIN_PAD_PULL_LSB 2
+#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c
+#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
+#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
+#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1
+#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0
+#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003
+#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
+#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
+
+#define SIGMA_DELTA_ADDRESS 0x00000078
+#define SIGMA_DELTA_OFFSET 0x00000078
+#define SIGMA_DELTA_ENABLE_MSB 16
+#define SIGMA_DELTA_ENABLE_LSB 16
+#define SIGMA_DELTA_ENABLE_MASK 0x00010000
+#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
+#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
+#define SIGMA_DELTA_PRESCALAR_MSB 15
+#define SIGMA_DELTA_PRESCALAR_LSB 8
+#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
+#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
+#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
+#define SIGMA_DELTA_TARGET_MSB 7
+#define SIGMA_DELTA_TARGET_LSB 0
+#define SIGMA_DELTA_TARGET_MASK 0x000000ff
+#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
+#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
+
+#define DEBUG_CONTROL_ADDRESS 0x0000007c
+#define DEBUG_CONTROL_OFFSET 0x0000007c
+#define DEBUG_CONTROL_OBS_OE_L_MSB 1
+#define DEBUG_CONTROL_OBS_OE_L_LSB 1
+#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002
+#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
+#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
+#define DEBUG_CONTROL_ENABLE_MSB 0
+#define DEBUG_CONTROL_ENABLE_LSB 0
+#define DEBUG_CONTROL_ENABLE_MASK 0x00000001
+#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
+#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
+
+#define DEBUG_INPUT_SEL_ADDRESS 0x00000080
+#define DEBUG_INPUT_SEL_OFFSET 0x00000080
+#define DEBUG_INPUT_SEL_SRC_MSB 3
+#define DEBUG_INPUT_SEL_SRC_LSB 0
+#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
+#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
+#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
+
+#define DEBUG_OUT_ADDRESS 0x00000084
+#define DEBUG_OUT_OFFSET 0x00000084
+#define DEBUG_OUT_DATA_MSB 17
+#define DEBUG_OUT_DATA_LSB 0
+#define DEBUG_OUT_DATA_MASK 0x0003ffff
+#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
+#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
+
+#define LA_CONTROL_ADDRESS 0x00000088
+#define LA_CONTROL_OFFSET 0x00000088
+#define LA_CONTROL_RUN_MSB 1
+#define LA_CONTROL_RUN_LSB 1
+#define LA_CONTROL_RUN_MASK 0x00000002
+#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
+#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
+#define LA_CONTROL_TRIGGERED_MSB 0
+#define LA_CONTROL_TRIGGERED_LSB 0
+#define LA_CONTROL_TRIGGERED_MASK 0x00000001
+#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
+#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
+
+#define LA_CLOCK_ADDRESS 0x0000008c
+#define LA_CLOCK_OFFSET 0x0000008c
+#define LA_CLOCK_DIV_MSB 7
+#define LA_CLOCK_DIV_LSB 0
+#define LA_CLOCK_DIV_MASK 0x000000ff
+#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
+#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
+
+#define LA_STATUS_ADDRESS 0x00000090
+#define LA_STATUS_OFFSET 0x00000090
+#define LA_STATUS_INTERRUPT_MSB 0
+#define LA_STATUS_INTERRUPT_LSB 0
+#define LA_STATUS_INTERRUPT_MASK 0x00000001
+#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
+#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
+
+#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094
+#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094
+#define LA_TRIGGER_SAMPLE_COUNT_MSB 15
+#define LA_TRIGGER_SAMPLE_COUNT_LSB 0
+#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff
+#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
+#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
+
+#define LA_TRIGGER_POSITION_ADDRESS 0x00000098
+#define LA_TRIGGER_POSITION_OFFSET 0x00000098
+#define LA_TRIGGER_POSITION_VALUE_MSB 15
+#define LA_TRIGGER_POSITION_VALUE_LSB 0
+#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff
+#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
+#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
+
+#define LA_PRE_TRIGGER_ADDRESS 0x0000009c
+#define LA_PRE_TRIGGER_OFFSET 0x0000009c
+#define LA_PRE_TRIGGER_COUNT_MSB 15
+#define LA_PRE_TRIGGER_COUNT_LSB 0
+#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff
+#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
+#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
+
+#define LA_POST_TRIGGER_ADDRESS 0x000000a0
+#define LA_POST_TRIGGER_OFFSET 0x000000a0
+#define LA_POST_TRIGGER_COUNT_MSB 15
+#define LA_POST_TRIGGER_COUNT_LSB 0
+#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff
+#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
+#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
+
+#define LA_FILTER_CONTROL_ADDRESS 0x000000a4
+#define LA_FILTER_CONTROL_OFFSET 0x000000a4
+#define LA_FILTER_CONTROL_DELTA_MSB 0
+#define LA_FILTER_CONTROL_DELTA_LSB 0
+#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001
+#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
+#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
+
+#define LA_FILTER_DATA_ADDRESS 0x000000a8
+#define LA_FILTER_DATA_OFFSET 0x000000a8
+#define LA_FILTER_DATA_MATCH_MSB 17
+#define LA_FILTER_DATA_MATCH_LSB 0
+#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff
+#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
+#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
+
+#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac
+#define LA_FILTER_WILDCARD_OFFSET 0x000000ac
+#define LA_FILTER_WILDCARD_MATCH_MSB 17
+#define LA_FILTER_WILDCARD_MATCH_LSB 0
+#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff
+#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
+#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0
+#define LA_TRIGGERA_DATA_OFFSET 0x000000b0
+#define LA_TRIGGERA_DATA_MATCH_MSB 17
+#define LA_TRIGGERA_DATA_MATCH_LSB 0
+#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
+#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
+
+#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4
+#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4
+#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17
+#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0
+#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8
+#define LA_TRIGGERB_DATA_OFFSET 0x000000b8
+#define LA_TRIGGERB_DATA_MATCH_MSB 17
+#define LA_TRIGGERB_DATA_MATCH_LSB 0
+#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
+#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
+
+#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc
+#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc
+#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17
+#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0
+#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGER_ADDRESS 0x000000c0
+#define LA_TRIGGER_OFFSET 0x000000c0
+#define LA_TRIGGER_EVENT_MSB 2
+#define LA_TRIGGER_EVENT_LSB 0
+#define LA_TRIGGER_EVENT_MASK 0x00000007
+#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
+#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
+
+#define LA_FIFO_ADDRESS 0x000000c4
+#define LA_FIFO_OFFSET 0x000000c4
+#define LA_FIFO_FULL_MSB 1
+#define LA_FIFO_FULL_LSB 1
+#define LA_FIFO_FULL_MASK 0x00000002
+#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
+#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
+#define LA_FIFO_EMPTY_MSB 0
+#define LA_FIFO_EMPTY_LSB 0
+#define LA_FIFO_EMPTY_MASK 0x00000001
+#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
+#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
+
+#define LA_ADDRESS 0x000000c8
+#define LA_OFFSET 0x000000c8
+#define LA_DATA_MSB 17
+#define LA_DATA_LSB 0
+#define LA_DATA_MASK 0x0003ffff
+#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
+#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK)
+
+#define ANT_PIN_ADDRESS 0x000000d0
+#define ANT_PIN_OFFSET 0x000000d0
+#define ANT_PIN_PAD_PULL_MSB 3
+#define ANT_PIN_PAD_PULL_LSB 2
+#define ANT_PIN_PAD_PULL_MASK 0x0000000c
+#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
+#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
+#define ANT_PIN_PAD_STRENGTH_MSB 1
+#define ANT_PIN_PAD_STRENGTH_LSB 0
+#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003
+#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
+#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
+
+#define ANTD_PIN_ADDRESS 0x000000d4
+#define ANTD_PIN_OFFSET 0x000000d4
+#define ANTD_PIN_PAD_PULL_MSB 1
+#define ANTD_PIN_PAD_PULL_LSB 0
+#define ANTD_PIN_PAD_PULL_MASK 0x00000003
+#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
+#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
+
+#define GPIO_PIN_ADDRESS 0x000000d8
+#define GPIO_PIN_OFFSET 0x000000d8
+#define GPIO_PIN_PAD_PULL_MSB 3
+#define GPIO_PIN_PAD_PULL_LSB 2
+#define GPIO_PIN_PAD_PULL_MASK 0x0000000c
+#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
+#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
+#define GPIO_PIN_PAD_STRENGTH_MSB 1
+#define GPIO_PIN_PAD_STRENGTH_LSB 0
+#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003
+#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
+#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
+
+#define GPIO_H_PIN_ADDRESS 0x000000dc
+#define GPIO_H_PIN_OFFSET 0x000000dc
+#define GPIO_H_PIN_PAD_PULL_MSB 1
+#define GPIO_H_PIN_PAD_PULL_LSB 0
+#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003
+#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
+#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
+
+#define BT_PIN_ADDRESS 0x000000e0
+#define BT_PIN_OFFSET 0x000000e0
+#define BT_PIN_PAD_PULL_MSB 3
+#define BT_PIN_PAD_PULL_LSB 2
+#define BT_PIN_PAD_PULL_MASK 0x0000000c
+#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
+#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
+#define BT_PIN_PAD_STRENGTH_MSB 1
+#define BT_PIN_PAD_STRENGTH_LSB 0
+#define BT_PIN_PAD_STRENGTH_MASK 0x00000003
+#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
+#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
+
+#define BT_WLAN_PIN_ADDRESS 0x000000e4
+#define BT_WLAN_PIN_OFFSET 0x000000e4
+#define BT_WLAN_PIN_PAD_PULL_MSB 1
+#define BT_WLAN_PIN_PAD_PULL_LSB 0
+#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003
+#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
+#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
+
+#define SI_UART_PIN_ADDRESS 0x000000e8
+#define SI_UART_PIN_OFFSET 0x000000e8
+#define SI_UART_PIN_PAD_PULL_MSB 3
+#define SI_UART_PIN_PAD_PULL_LSB 2
+#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c
+#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
+#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
+#define SI_UART_PIN_PAD_STRENGTH_MSB 1
+#define SI_UART_PIN_PAD_STRENGTH_LSB 0
+#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003
+#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
+#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
+
+#define CLK32K_PIN_ADDRESS 0x000000ec
+#define CLK32K_PIN_OFFSET 0x000000ec
+#define CLK32K_PIN_PAD_PULL_MSB 1
+#define CLK32K_PIN_PAD_PULL_LSB 0
+#define CLK32K_PIN_PAD_PULL_MASK 0x00000003
+#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
+#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
+
+#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0
+#define RESET_TUPLE_STATUS_OFFSET 0x000000f0
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_reg_reg_s {
+ volatile unsigned int gpio_out;
+ volatile unsigned int gpio_out_w1ts;
+ volatile unsigned int gpio_out_w1tc;
+ volatile unsigned int gpio_enable;
+ volatile unsigned int gpio_enable_w1ts;
+ volatile unsigned int gpio_enable_w1tc;
+ volatile unsigned int gpio_in;
+ volatile unsigned int gpio_status;
+ volatile unsigned int gpio_status_w1ts;
+ volatile unsigned int gpio_status_w1tc;
+ volatile unsigned int gpio_pin0;
+ volatile unsigned int gpio_pin1;
+ volatile unsigned int gpio_pin2;
+ volatile unsigned int gpio_pin3;
+ volatile unsigned int gpio_pin4;
+ volatile unsigned int gpio_pin5;
+ volatile unsigned int gpio_pin6;
+ volatile unsigned int gpio_pin7;
+ volatile unsigned int gpio_pin8;
+ volatile unsigned int gpio_pin9;
+ volatile unsigned int gpio_pin10;
+ volatile unsigned int gpio_pin11;
+ volatile unsigned int gpio_pin12;
+ volatile unsigned int gpio_pin13;
+ volatile unsigned int gpio_pin14;
+ volatile unsigned int gpio_pin15;
+ volatile unsigned int gpio_pin16;
+ volatile unsigned int gpio_pin17;
+ volatile unsigned int sdio_pin;
+ volatile unsigned int clk_req_pin;
+ volatile unsigned int sigma_delta;
+ volatile unsigned int debug_control;
+ volatile unsigned int debug_input_sel;
+ volatile unsigned int debug_out;
+ volatile unsigned int la_control;
+ volatile unsigned int la_clock;
+ volatile unsigned int la_status;
+ volatile unsigned int la_trigger_sample;
+ volatile unsigned int la_trigger_position;
+ volatile unsigned int la_pre_trigger;
+ volatile unsigned int la_post_trigger;
+ volatile unsigned int la_filter_control;
+ volatile unsigned int la_filter_data;
+ volatile unsigned int la_filter_wildcard;
+ volatile unsigned int la_triggera_data;
+ volatile unsigned int la_triggera_wildcard;
+ volatile unsigned int la_triggerb_data;
+ volatile unsigned int la_triggerb_wildcard;
+ volatile unsigned int la_trigger;
+ volatile unsigned int la_fifo;
+ volatile unsigned int la[2];
+ volatile unsigned int ant_pin;
+ volatile unsigned int antd_pin;
+ volatile unsigned int gpio_pin;
+ volatile unsigned int gpio_h_pin;
+ volatile unsigned int bt_pin;
+ volatile unsigned int bt_wlan_pin;
+ volatile unsigned int si_uart_pin;
+ volatile unsigned int clk32k_pin;
+ volatile unsigned int reset_tuple_status;
+} gpio_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h
new file mode 100644
index 000000000000..20ac2b5c8920
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h
@@ -0,0 +1,405 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_HOST_REG_REG_H_
+#define _MBOX_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS 0x00000400
+#define HOST_INT_STATUS_OFFSET 0x00000400
+#define HOST_INT_STATUS_ERROR_MSB 7
+#define HOST_INT_STATUS_ERROR_LSB 7
+#define HOST_INT_STATUS_ERROR_MASK 0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB 6
+#define HOST_INT_STATUS_CPU_LSB 6
+#define HOST_INT_STATUS_CPU_MASK 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_DRAGON_INT_MSB 5
+#define HOST_INT_STATUS_DRAGON_INT_LSB 5
+#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
+#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
+#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB 4
+#define HOST_INT_STATUS_COUNTER_LSB 4
+#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB 3
+#define HOST_INT_STATUS_MBOX_DATA_LSB 0
+#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS 0x00000401
+#define CPU_INT_STATUS_OFFSET 0x00000401
+#define CPU_INT_STATUS_BIT_MSB 7
+#define CPU_INT_STATUS_BIT_LSB 0
+#define CPU_INT_STATUS_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS 0x00000402
+#define ERROR_INT_STATUS_OFFSET 0x00000402
+#define ERROR_INT_STATUS_SPI_MSB 3
+#define ERROR_INT_STATUS_SPI_LSB 3
+#define ERROR_INT_STATUS_SPI_MASK 0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB 2
+#define ERROR_INT_STATUS_WAKEUP_LSB 2
+#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS 0x00000403
+#define COUNTER_INT_STATUS_OFFSET 0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB 7
+#define COUNTER_INT_STATUS_COUNTER_LSB 0
+#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS 0x00000404
+#define MBOX_FRAME_OFFSET 0x00000404
+#define MBOX_FRAME_RX_EOM_MSB 7
+#define MBOX_FRAME_RX_EOM_LSB 4
+#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB 3
+#define MBOX_FRAME_RX_SOM_LSB 0
+#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS 0x00000408
+#define RX_LOOKAHEAD0_OFFSET 0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB 7
+#define RX_LOOKAHEAD0_DATA_LSB 0
+#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
+#define RX_LOOKAHEAD1_OFFSET 0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB 7
+#define RX_LOOKAHEAD1_DATA_LSB 0
+#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS 0x00000410
+#define RX_LOOKAHEAD2_OFFSET 0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB 7
+#define RX_LOOKAHEAD2_DATA_LSB 0
+#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS 0x00000414
+#define RX_LOOKAHEAD3_OFFSET 0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB 7
+#define RX_LOOKAHEAD3_DATA_LSB 0
+#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS 0x00000418
+#define INT_STATUS_ENABLE_OFFSET 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB 7
+#define INT_STATUS_ENABLE_ERROR_LSB 7
+#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB 6
+#define INT_STATUS_ENABLE_CPU_LSB 6
+#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
+#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
+#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
+#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
+#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB 4
+#define INT_STATUS_ENABLE_COUNTER_LSB 4
+#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS 0x00000420
+#define COUNT_OFFSET 0x00000420
+#define COUNT_VALUE_MSB 7
+#define COUNT_VALUE_LSB 0
+#define COUNT_VALUE_MASK 0x000000ff
+#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS 0x00000440
+#define COUNT_DEC_OFFSET 0x00000440
+#define COUNT_DEC_VALUE_MSB 7
+#define COUNT_DEC_VALUE_LSB 0
+#define COUNT_DEC_VALUE_MASK 0x000000ff
+#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS 0x00000460
+#define SCRATCH_OFFSET 0x00000460
+#define SCRATCH_VALUE_MSB 7
+#define SCRATCH_VALUE_LSB 0
+#define SCRATCH_VALUE_MASK 0x000000ff
+#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS 0x00000468
+#define FIFO_TIMEOUT_OFFSET 0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB 7
+#define FIFO_TIMEOUT_VALUE_LSB 0
+#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS 0x0000046a
+#define DISABLE_SLEEP_OFFSET 0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB 1
+#define DISABLE_SLEEP_FOR_INT_LSB 1
+#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB 0
+#define DISABLE_SLEEP_ON_LSB 0
+#define DISABLE_SLEEP_ON_MASK 0x00000001
+#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS 0x00000470
+#define LOCAL_BUS_OFFSET 0x00000470
+#define LOCAL_BUS_STATE_MSB 1
+#define LOCAL_BUS_STATE_LSB 0
+#define LOCAL_BUS_STATE_MASK 0x00000003
+#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS 0x00000472
+#define INT_WLAN_OFFSET 0x00000472
+#define INT_WLAN_VECTOR_MSB 7
+#define INT_WLAN_VECTOR_LSB 0
+#define INT_WLAN_VECTOR_MASK 0x000000ff
+#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS 0x00000474
+#define WINDOW_DATA_OFFSET 0x00000474
+#define WINDOW_DATA_DATA_MSB 7
+#define WINDOW_DATA_DATA_LSB 0
+#define WINDOW_DATA_DATA_MASK 0x000000ff
+#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB 7
+#define WINDOW_WRITE_ADDR_ADDR_LSB 0
+#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET 0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB 7
+#define WINDOW_READ_ADDR_ADDR_LSB 0
+#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define SPI_CONFIG_ADDRESS 0x00000480
+#define SPI_CONFIG_OFFSET 0x00000480
+#define SPI_CONFIG_SPI_RESET_MSB 4
+#define SPI_CONFIG_SPI_RESET_LSB 4
+#define SPI_CONFIG_SPI_RESET_MASK 0x00000010
+#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
+#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
+#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
+#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
+#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
+#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define SPI_CONFIG_TEST_MODE_MSB 2
+#define SPI_CONFIG_TEST_MODE_LSB 2
+#define SPI_CONFIG_TEST_MODE_MASK 0x00000004
+#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
+#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
+#define SPI_CONFIG_DATA_SIZE_MSB 1
+#define SPI_CONFIG_DATA_SIZE_LSB 0
+#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
+#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
+#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
+
+#define SPI_STATUS_ADDRESS 0x00000481
+#define SPI_STATUS_OFFSET 0x00000481
+#define SPI_STATUS_ADDR_ERR_MSB 3
+#define SPI_STATUS_ADDR_ERR_LSB 3
+#define SPI_STATUS_ADDR_ERR_MASK 0x00000008
+#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
+#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
+#define SPI_STATUS_RD_ERR_MSB 2
+#define SPI_STATUS_RD_ERR_LSB 2
+#define SPI_STATUS_RD_ERR_MASK 0x00000004
+#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
+#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
+#define SPI_STATUS_WR_ERR_MSB 1
+#define SPI_STATUS_WR_ERR_LSB 1
+#define SPI_STATUS_WR_ERR_MASK 0x00000002
+#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
+#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
+#define SPI_STATUS_READY_MSB 0
+#define SPI_STATUS_READY_LSB 0
+#define SPI_STATUS_READY_MASK 0x00000001
+#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
+#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CIS_WINDOW_ADDRESS 0x00000600
+#define CIS_WINDOW_OFFSET 0x00000600
+#define CIS_WINDOW_DATA_MSB 7
+#define CIS_WINDOW_DATA_LSB 0
+#define CIS_WINDOW_DATA_MASK 0x000000ff
+#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_host_reg_reg_s {
+ unsigned char pad0[1024]; /* pad to 0x400 */
+ volatile unsigned char host_int_status;
+ volatile unsigned char cpu_int_status;
+ volatile unsigned char error_int_status;
+ volatile unsigned char counter_int_status;
+ volatile unsigned char mbox_frame;
+ volatile unsigned char rx_lookahead_valid;
+ unsigned char pad1[2]; /* pad to 0x408 */
+ volatile unsigned char rx_lookahead0[4];
+ volatile unsigned char rx_lookahead1[4];
+ volatile unsigned char rx_lookahead2[4];
+ volatile unsigned char rx_lookahead3[4];
+ volatile unsigned char int_status_enable;
+ volatile unsigned char cpu_int_status_enable;
+ volatile unsigned char error_status_enable;
+ volatile unsigned char counter_int_status_enable;
+ unsigned char pad2[4]; /* pad to 0x420 */
+ volatile unsigned char count[8];
+ unsigned char pad3[24]; /* pad to 0x440 */
+ volatile unsigned char count_dec[32];
+ volatile unsigned char scratch[8];
+ volatile unsigned char fifo_timeout;
+ volatile unsigned char fifo_timeout_enable;
+ volatile unsigned char disable_sleep;
+ unsigned char pad4[5]; /* pad to 0x470 */
+ volatile unsigned char local_bus;
+ unsigned char pad5[1]; /* pad to 0x472 */
+ volatile unsigned char int_wlan;
+ unsigned char pad6[1]; /* pad to 0x474 */
+ volatile unsigned char window_data[4];
+ volatile unsigned char window_write_addr[4];
+ volatile unsigned char window_read_addr[4];
+ volatile unsigned char spi_config;
+ volatile unsigned char spi_status;
+ volatile unsigned char non_assoc_sleep_en;
+ unsigned char pad7[381]; /* pad to 0x600 */
+ volatile unsigned char cis_window[512];
+} mbox_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_HOST_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h
new file mode 100644
index 000000000000..d232764d5af6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h
@@ -0,0 +1,500 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_REG_REG_H_
+#define _MBOX_REG_REG_H_
+
+#define MBOX_FIFO_ADDRESS 0x00000000
+#define MBOX_FIFO_OFFSET 0x00000000
+#define MBOX_FIFO_DATA_MSB 19
+#define MBOX_FIFO_DATA_LSB 0
+#define MBOX_FIFO_DATA_MASK 0x000fffff
+#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
+#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
+
+#define MBOX_FIFO_STATUS_ADDRESS 0x00000010
+#define MBOX_FIFO_STATUS_OFFSET 0x00000010
+#define MBOX_FIFO_STATUS_EMPTY_MSB 19
+#define MBOX_FIFO_STATUS_EMPTY_LSB 16
+#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
+#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
+#define MBOX_FIFO_STATUS_FULL_MSB 15
+#define MBOX_FIFO_STATUS_FULL_LSB 12
+#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
+#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
+#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
+
+#define MBOX_DMA_POLICY_ADDRESS 0x00000014
+#define MBOX_DMA_POLICY_OFFSET 0x00000014
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB 2
+#define MBOX_DMA_POLICY_TX_ORDER_LSB 2
+#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB 0
+#define MBOX_DMA_POLICY_RX_ORDER_LSB 0
+#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
+#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_RX_CONTROL_START_MSB 1
+#define MBOX0_DMA_RX_CONTROL_START_LSB 1
+#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
+#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_TX_CONTROL_START_MSB 1
+#define MBOX0_DMA_TX_CONTROL_START_LSB 1
+#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
+#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_RX_CONTROL_START_MSB 1
+#define MBOX1_DMA_RX_CONTROL_START_LSB 1
+#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
+#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_TX_CONTROL_START_MSB 1
+#define MBOX1_DMA_TX_CONTROL_START_LSB 1
+#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
+#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_RX_CONTROL_START_MSB 1
+#define MBOX2_DMA_RX_CONTROL_START_LSB 1
+#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
+#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_TX_CONTROL_START_MSB 1
+#define MBOX2_DMA_TX_CONTROL_START_LSB 1
+#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
+#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_RX_CONTROL_START_MSB 1
+#define MBOX3_DMA_RX_CONTROL_START_LSB 1
+#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
+#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_TX_CONTROL_START_MSB 1
+#define MBOX3_DMA_TX_CONTROL_START_LSB 1
+#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX_INT_STATUS_ADDRESS 0x00000058
+#define MBOX_INT_STATUS_OFFSET 0x00000058
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define MBOX_INT_STATUS_HOST_MSB 7
+#define MBOX_INT_STATUS_HOST_LSB 0
+#define MBOX_INT_STATUS_HOST_MASK 0x000000ff
+#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
+#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
+
+#define MBOX_INT_ENABLE_ADDRESS 0x0000005c
+#define MBOX_INT_ENABLE_OFFSET 0x0000005c
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define MBOX_INT_ENABLE_HOST_MSB 7
+#define MBOX_INT_ENABLE_HOST_LSB 0
+#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
+#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
+#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
+
+#define INT_HOST_ADDRESS 0x00000060
+#define INT_HOST_OFFSET 0x00000060
+#define INT_HOST_VECTOR_MSB 7
+#define INT_HOST_VECTOR_LSB 0
+#define INT_HOST_VECTOR_MASK 0x000000ff
+#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
+#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
+
+#define LOCAL_COUNT_ADDRESS 0x00000080
+#define LOCAL_COUNT_OFFSET 0x00000080
+#define LOCAL_COUNT_VALUE_MSB 7
+#define LOCAL_COUNT_VALUE_LSB 0
+#define LOCAL_COUNT_VALUE_MASK 0x000000ff
+#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
+#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
+
+#define COUNT_INC_ADDRESS 0x000000a0
+#define COUNT_INC_OFFSET 0x000000a0
+#define COUNT_INC_VALUE_MSB 7
+#define COUNT_INC_VALUE_LSB 0
+#define COUNT_INC_VALUE_MASK 0x000000ff
+#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
+#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
+
+#define LOCAL_SCRATCH_ADDRESS 0x000000c0
+#define LOCAL_SCRATCH_OFFSET 0x000000c0
+#define LOCAL_SCRATCH_VALUE_MSB 7
+#define LOCAL_SCRATCH_VALUE_LSB 0
+#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
+#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
+#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
+
+#define USE_LOCAL_BUS_ADDRESS 0x000000e0
+#define USE_LOCAL_BUS_OFFSET 0x000000e0
+#define USE_LOCAL_BUS_PIN_INIT_MSB 0
+#define USE_LOCAL_BUS_PIN_INIT_LSB 0
+#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
+#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define SDIO_CONFIG_ADDRESS 0x000000e4
+#define SDIO_CONFIG_OFFSET 0x000000e4
+#define SDIO_CONFIG_CCCR_IOR1_MSB 0
+#define SDIO_CONFIG_CCCR_IOR1_LSB 0
+#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
+#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define MBOX_DEBUG_ADDRESS 0x000000e8
+#define MBOX_DEBUG_OFFSET 0x000000e8
+#define MBOX_DEBUG_SEL_MSB 2
+#define MBOX_DEBUG_SEL_LSB 0
+#define MBOX_DEBUG_SEL_MASK 0x00000007
+#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
+#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
+
+#define MBOX_FIFO_RESET_ADDRESS 0x000000ec
+#define MBOX_FIFO_RESET_OFFSET 0x000000ec
+#define MBOX_FIFO_RESET_INIT_MSB 0
+#define MBOX_FIFO_RESET_INIT_LSB 0
+#define MBOX_FIFO_RESET_INIT_MASK 0x00000001
+#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
+#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
+
+#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0
+#define MBOX_TXFIFO_POP_OFFSET 0x000000f0
+#define MBOX_TXFIFO_POP_DATA_MSB 0
+#define MBOX_TXFIFO_POP_DATA_LSB 0
+#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001
+#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
+#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
+
+#define MBOX_RXFIFO_POP_ADDRESS 0x00000100
+#define MBOX_RXFIFO_POP_OFFSET 0x00000100
+#define MBOX_RXFIFO_POP_DATA_MSB 0
+#define MBOX_RXFIFO_POP_DATA_LSB 0
+#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001
+#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
+#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
+
+#define SDIO_DEBUG_ADDRESS 0x00000110
+#define SDIO_DEBUG_OFFSET 0x00000110
+#define SDIO_DEBUG_SEL_MSB 3
+#define SDIO_DEBUG_SEL_LSB 0
+#define SDIO_DEBUG_SEL_MASK 0x0000000f
+#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
+#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
+
+#define HOST_IF_WINDOW_ADDRESS 0x00002000
+#define HOST_IF_WINDOW_OFFSET 0x00002000
+#define HOST_IF_WINDOW_DATA_MSB 7
+#define HOST_IF_WINDOW_DATA_LSB 0
+#define HOST_IF_WINDOW_DATA_MASK 0x000000ff
+#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
+#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_reg_reg_s {
+ volatile unsigned int mbox_fifo[4];
+ volatile unsigned int mbox_fifo_status;
+ volatile unsigned int mbox_dma_policy;
+ volatile unsigned int mbox0_dma_rx_descriptor_base;
+ volatile unsigned int mbox0_dma_rx_control;
+ volatile unsigned int mbox0_dma_tx_descriptor_base;
+ volatile unsigned int mbox0_dma_tx_control;
+ volatile unsigned int mbox1_dma_rx_descriptor_base;
+ volatile unsigned int mbox1_dma_rx_control;
+ volatile unsigned int mbox1_dma_tx_descriptor_base;
+ volatile unsigned int mbox1_dma_tx_control;
+ volatile unsigned int mbox2_dma_rx_descriptor_base;
+ volatile unsigned int mbox2_dma_rx_control;
+ volatile unsigned int mbox2_dma_tx_descriptor_base;
+ volatile unsigned int mbox2_dma_tx_control;
+ volatile unsigned int mbox3_dma_rx_descriptor_base;
+ volatile unsigned int mbox3_dma_rx_control;
+ volatile unsigned int mbox3_dma_tx_descriptor_base;
+ volatile unsigned int mbox3_dma_tx_control;
+ volatile unsigned int mbox_int_status;
+ volatile unsigned int mbox_int_enable;
+ volatile unsigned int int_host;
+ unsigned char pad0[28]; /* pad to 0x80 */
+ volatile unsigned int local_count[8];
+ volatile unsigned int count_inc[8];
+ volatile unsigned int local_scratch[8];
+ volatile unsigned int use_local_bus;
+ volatile unsigned int sdio_config;
+ volatile unsigned int mbox_debug;
+ volatile unsigned int mbox_fifo_reset;
+ volatile unsigned int mbox_txfifo_pop[4];
+ volatile unsigned int mbox_rxfifo_pop[4];
+ volatile unsigned int sdio_debug;
+ unsigned char pad1[7916]; /* pad to 0x2000 */
+ volatile unsigned int host_if_window[2048];
+} mbox_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h
new file mode 100644
index 000000000000..cc2cb7350a78
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h
@@ -0,0 +1,1182 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_REG_REG_H_
+#define _RTC_REG_REG_H_
+
+#define RESET_CONTROL_ADDRESS 0x00000000
+#define RESET_CONTROL_OFFSET 0x00000000
+#define RESET_CONTROL_CPU_INIT_RESET_MSB 11
+#define RESET_CONTROL_CPU_INIT_RESET_LSB 11
+#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define RESET_CONTROL_RST_OUT_MSB 9
+#define RESET_CONTROL_RST_OUT_LSB 9
+#define RESET_CONTROL_RST_OUT_MASK 0x00000200
+#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
+#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
+#define RESET_CONTROL_COLD_RST_MSB 8
+#define RESET_CONTROL_COLD_RST_LSB 8
+#define RESET_CONTROL_COLD_RST_MASK 0x00000100
+#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
+#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
+#define RESET_CONTROL_WARM_RST_MSB 7
+#define RESET_CONTROL_WARM_RST_LSB 7
+#define RESET_CONTROL_WARM_RST_MASK 0x00000080
+#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
+#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
+#define RESET_CONTROL_CPU_WARM_RST_MSB 6
+#define RESET_CONTROL_CPU_WARM_RST_LSB 6
+#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
+#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
+#define RESET_CONTROL_MAC_COLD_RST_MSB 5
+#define RESET_CONTROL_MAC_COLD_RST_LSB 5
+#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020
+#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
+#define RESET_CONTROL_MAC_WARM_RST_MSB 4
+#define RESET_CONTROL_MAC_WARM_RST_LSB 4
+#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010
+#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
+#define RESET_CONTROL_MBOX_RST_MSB 2
+#define RESET_CONTROL_MBOX_RST_LSB 2
+#define RESET_CONTROL_MBOX_RST_MASK 0x00000004
+#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
+#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
+#define RESET_CONTROL_UART_RST_MSB 1
+#define RESET_CONTROL_UART_RST_LSB 1
+#define RESET_CONTROL_UART_RST_MASK 0x00000002
+#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
+#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
+#define RESET_CONTROL_SI0_RST_MSB 0
+#define RESET_CONTROL_SI0_RST_LSB 0
+#define RESET_CONTROL_SI0_RST_MASK 0x00000001
+#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
+#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
+
+#define XTAL_CONTROL_ADDRESS 0x00000004
+#define XTAL_CONTROL_OFFSET 0x00000004
+#define XTAL_CONTROL_TCXO_MSB 0
+#define XTAL_CONTROL_TCXO_LSB 0
+#define XTAL_CONTROL_TCXO_MASK 0x00000001
+#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
+#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
+
+#define TCXO_DETECT_ADDRESS 0x00000008
+#define TCXO_DETECT_OFFSET 0x00000008
+#define TCXO_DETECT_PRESENT_MSB 0
+#define TCXO_DETECT_PRESENT_LSB 0
+#define TCXO_DETECT_PRESENT_MASK 0x00000001
+#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
+#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
+
+#define XTAL_TEST_ADDRESS 0x0000000c
+#define XTAL_TEST_OFFSET 0x0000000c
+#define XTAL_TEST_NOTCXODET_MSB 0
+#define XTAL_TEST_NOTCXODET_LSB 0
+#define XTAL_TEST_NOTCXODET_MASK 0x00000001
+#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
+#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
+
+#define QUADRATURE_ADDRESS 0x00000010
+#define QUADRATURE_OFFSET 0x00000010
+#define QUADRATURE_ADC_MSB 5
+#define QUADRATURE_ADC_LSB 4
+#define QUADRATURE_ADC_MASK 0x00000030
+#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
+#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
+#define QUADRATURE_SEL_MSB 2
+#define QUADRATURE_SEL_LSB 2
+#define QUADRATURE_SEL_MASK 0x00000004
+#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
+#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
+#define QUADRATURE_DAC_MSB 1
+#define QUADRATURE_DAC_LSB 0
+#define QUADRATURE_DAC_MASK 0x00000003
+#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
+#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
+
+#define PLL_CONTROL_ADDRESS 0x00000014
+#define PLL_CONTROL_OFFSET 0x00000014
+#define PLL_CONTROL_DIG_TEST_CLK_MSB 20
+#define PLL_CONTROL_DIG_TEST_CLK_LSB 20
+#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB 19
+#define PLL_CONTROL_MAC_OVERRIDE_LSB 19
+#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define PLL_CONTROL_NOPWD_MSB 18
+#define PLL_CONTROL_NOPWD_LSB 18
+#define PLL_CONTROL_NOPWD_MASK 0x00040000
+#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
+#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
+#define PLL_CONTROL_UPDATING_MSB 17
+#define PLL_CONTROL_UPDATING_LSB 17
+#define PLL_CONTROL_UPDATING_MASK 0x00020000
+#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
+#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
+#define PLL_CONTROL_BYPASS_MSB 16
+#define PLL_CONTROL_BYPASS_LSB 16
+#define PLL_CONTROL_BYPASS_MASK 0x00010000
+#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
+#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
+#define PLL_CONTROL_REFDIV_MSB 15
+#define PLL_CONTROL_REFDIV_LSB 12
+#define PLL_CONTROL_REFDIV_MASK 0x0000f000
+#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
+#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
+#define PLL_CONTROL_DIV_MSB 9
+#define PLL_CONTROL_DIV_LSB 0
+#define PLL_CONTROL_DIV_MASK 0x000003ff
+#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
+#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
+
+#define PLL_SETTLE_ADDRESS 0x00000018
+#define PLL_SETTLE_OFFSET 0x00000018
+#define PLL_SETTLE_TIME_MSB 11
+#define PLL_SETTLE_TIME_LSB 0
+#define PLL_SETTLE_TIME_MASK 0x00000fff
+#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
+#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
+
+#define XTAL_SETTLE_ADDRESS 0x0000001c
+#define XTAL_SETTLE_OFFSET 0x0000001c
+#define XTAL_SETTLE_TIME_MSB 7
+#define XTAL_SETTLE_TIME_LSB 0
+#define XTAL_SETTLE_TIME_MASK 0x000000ff
+#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
+#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
+
+#define CPU_CLOCK_ADDRESS 0x00000020
+#define CPU_CLOCK_OFFSET 0x00000020
+#define CPU_CLOCK_STANDARD_MSB 1
+#define CPU_CLOCK_STANDARD_LSB 0
+#define CPU_CLOCK_STANDARD_MASK 0x00000003
+#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
+#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
+
+#define CLOCK_OUT_ADDRESS 0x00000024
+#define CLOCK_OUT_OFFSET 0x00000024
+#define CLOCK_OUT_SELECT_MSB 3
+#define CLOCK_OUT_SELECT_LSB 0
+#define CLOCK_OUT_SELECT_MASK 0x0000000f
+#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
+#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
+
+#define CLOCK_CONTROL_ADDRESS 0x00000028
+#define CLOCK_CONTROL_OFFSET 0x00000028
+#define CLOCK_CONTROL_LF_CLK32_MSB 2
+#define CLOCK_CONTROL_LF_CLK32_LSB 2
+#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004
+#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB)
+#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK)
+#define CLOCK_CONTROL_UART_CLK_MSB 1
+#define CLOCK_CONTROL_UART_CLK_LSB 1
+#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002
+#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
+#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
+#define CLOCK_CONTROL_SI0_CLK_MSB 0
+#define CLOCK_CONTROL_SI0_CLK_LSB 0
+#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
+#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
+#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define BIAS_OVERRIDE_ADDRESS 0x0000002c
+#define BIAS_OVERRIDE_OFFSET 0x0000002c
+#define BIAS_OVERRIDE_ON_MSB 0
+#define BIAS_OVERRIDE_ON_LSB 0
+#define BIAS_OVERRIDE_ON_MASK 0x00000001
+#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
+#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
+
+#define WDT_CONTROL_ADDRESS 0x00000030
+#define WDT_CONTROL_OFFSET 0x00000030
+#define WDT_CONTROL_ACTION_MSB 2
+#define WDT_CONTROL_ACTION_LSB 0
+#define WDT_CONTROL_ACTION_MASK 0x00000007
+#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
+#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
+
+#define WDT_STATUS_ADDRESS 0x00000034
+#define WDT_STATUS_OFFSET 0x00000034
+#define WDT_STATUS_INTERRUPT_MSB 0
+#define WDT_STATUS_INTERRUPT_LSB 0
+#define WDT_STATUS_INTERRUPT_MASK 0x00000001
+#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
+#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
+
+#define WDT_ADDRESS 0x00000038
+#define WDT_OFFSET 0x00000038
+#define WDT_TARGET_MSB 21
+#define WDT_TARGET_LSB 0
+#define WDT_TARGET_MASK 0x003fffff
+#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
+#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
+
+#define WDT_COUNT_ADDRESS 0x0000003c
+#define WDT_COUNT_OFFSET 0x0000003c
+#define WDT_COUNT_VALUE_MSB 21
+#define WDT_COUNT_VALUE_LSB 0
+#define WDT_COUNT_VALUE_MASK 0x003fffff
+#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
+#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
+
+#define WDT_RESET_ADDRESS 0x00000040
+#define WDT_RESET_OFFSET 0x00000040
+#define WDT_RESET_VALUE_MSB 0
+#define WDT_RESET_VALUE_LSB 0
+#define WDT_RESET_VALUE_MASK 0x00000001
+#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
+#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
+
+#define INT_STATUS_ADDRESS 0x00000044
+#define INT_STATUS_OFFSET 0x00000044
+#define INT_STATUS_RTC_POWER_MSB 14
+#define INT_STATUS_RTC_POWER_LSB 14
+#define INT_STATUS_RTC_POWER_MASK 0x00004000
+#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB)
+#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK)
+#define INT_STATUS_MAC_MSB 13
+#define INT_STATUS_MAC_LSB 13
+#define INT_STATUS_MAC_MASK 0x00002000
+#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
+#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
+#define INT_STATUS_MAILBOX_MSB 12
+#define INT_STATUS_MAILBOX_LSB 12
+#define INT_STATUS_MAILBOX_MASK 0x00001000
+#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
+#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
+#define INT_STATUS_RTC_ALARM_MSB 11
+#define INT_STATUS_RTC_ALARM_LSB 11
+#define INT_STATUS_RTC_ALARM_MASK 0x00000800
+#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
+#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
+#define INT_STATUS_HF_TIMER_MSB 10
+#define INT_STATUS_HF_TIMER_LSB 10
+#define INT_STATUS_HF_TIMER_MASK 0x00000400
+#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
+#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
+#define INT_STATUS_LF_TIMER3_MSB 9
+#define INT_STATUS_LF_TIMER3_LSB 9
+#define INT_STATUS_LF_TIMER3_MASK 0x00000200
+#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
+#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
+#define INT_STATUS_LF_TIMER2_MSB 8
+#define INT_STATUS_LF_TIMER2_LSB 8
+#define INT_STATUS_LF_TIMER2_MASK 0x00000100
+#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
+#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
+#define INT_STATUS_LF_TIMER1_MSB 7
+#define INT_STATUS_LF_TIMER1_LSB 7
+#define INT_STATUS_LF_TIMER1_MASK 0x00000080
+#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
+#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
+#define INT_STATUS_LF_TIMER0_MSB 6
+#define INT_STATUS_LF_TIMER0_LSB 6
+#define INT_STATUS_LF_TIMER0_MASK 0x00000040
+#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
+#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
+#define INT_STATUS_KEYPAD_MSB 5
+#define INT_STATUS_KEYPAD_LSB 5
+#define INT_STATUS_KEYPAD_MASK 0x00000020
+#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
+#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
+#define INT_STATUS_SI_MSB 4
+#define INT_STATUS_SI_LSB 4
+#define INT_STATUS_SI_MASK 0x00000010
+#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
+#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
+#define INT_STATUS_GPIO_MSB 3
+#define INT_STATUS_GPIO_LSB 3
+#define INT_STATUS_GPIO_MASK 0x00000008
+#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
+#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
+#define INT_STATUS_UART_MSB 2
+#define INT_STATUS_UART_LSB 2
+#define INT_STATUS_UART_MASK 0x00000004
+#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
+#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
+#define INT_STATUS_ERROR_MSB 1
+#define INT_STATUS_ERROR_LSB 1
+#define INT_STATUS_ERROR_MASK 0x00000002
+#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
+#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
+#define INT_STATUS_WDT_INT_MSB 0
+#define INT_STATUS_WDT_INT_LSB 0
+#define INT_STATUS_WDT_INT_MASK 0x00000001
+#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
+#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
+
+#define LF_TIMER0_ADDRESS 0x00000048
+#define LF_TIMER0_OFFSET 0x00000048
+#define LF_TIMER0_TARGET_MSB 31
+#define LF_TIMER0_TARGET_LSB 0
+#define LF_TIMER0_TARGET_MASK 0xffffffff
+#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
+#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
+
+#define LF_TIMER_COUNT0_ADDRESS 0x0000004c
+#define LF_TIMER_COUNT0_OFFSET 0x0000004c
+#define LF_TIMER_COUNT0_VALUE_MSB 31
+#define LF_TIMER_COUNT0_VALUE_LSB 0
+#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
+#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
+
+#define LF_TIMER_CONTROL0_ADDRESS 0x00000050
+#define LF_TIMER_CONTROL0_OFFSET 0x00000050
+#define LF_TIMER_CONTROL0_ENABLE_MSB 2
+#define LF_TIMER_CONTROL0_ENABLE_LSB 2
+#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL0_RESET_MSB 0
+#define LF_TIMER_CONTROL0_RESET_LSB 0
+#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
+#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
+
+#define LF_TIMER_STATUS0_ADDRESS 0x00000054
+#define LF_TIMER_STATUS0_OFFSET 0x00000054
+#define LF_TIMER_STATUS0_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS0_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define LF_TIMER1_ADDRESS 0x00000058
+#define LF_TIMER1_OFFSET 0x00000058
+#define LF_TIMER1_TARGET_MSB 31
+#define LF_TIMER1_TARGET_LSB 0
+#define LF_TIMER1_TARGET_MASK 0xffffffff
+#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
+#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
+
+#define LF_TIMER_COUNT1_ADDRESS 0x0000005c
+#define LF_TIMER_COUNT1_OFFSET 0x0000005c
+#define LF_TIMER_COUNT1_VALUE_MSB 31
+#define LF_TIMER_COUNT1_VALUE_LSB 0
+#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
+#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
+
+#define LF_TIMER_CONTROL1_ADDRESS 0x00000060
+#define LF_TIMER_CONTROL1_OFFSET 0x00000060
+#define LF_TIMER_CONTROL1_ENABLE_MSB 2
+#define LF_TIMER_CONTROL1_ENABLE_LSB 2
+#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL1_RESET_MSB 0
+#define LF_TIMER_CONTROL1_RESET_LSB 0
+#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
+#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
+
+#define LF_TIMER_STATUS1_ADDRESS 0x00000064
+#define LF_TIMER_STATUS1_OFFSET 0x00000064
+#define LF_TIMER_STATUS1_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS1_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define LF_TIMER2_ADDRESS 0x00000068
+#define LF_TIMER2_OFFSET 0x00000068
+#define LF_TIMER2_TARGET_MSB 31
+#define LF_TIMER2_TARGET_LSB 0
+#define LF_TIMER2_TARGET_MASK 0xffffffff
+#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
+#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
+
+#define LF_TIMER_COUNT2_ADDRESS 0x0000006c
+#define LF_TIMER_COUNT2_OFFSET 0x0000006c
+#define LF_TIMER_COUNT2_VALUE_MSB 31
+#define LF_TIMER_COUNT2_VALUE_LSB 0
+#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
+#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
+
+#define LF_TIMER_CONTROL2_ADDRESS 0x00000070
+#define LF_TIMER_CONTROL2_OFFSET 0x00000070
+#define LF_TIMER_CONTROL2_ENABLE_MSB 2
+#define LF_TIMER_CONTROL2_ENABLE_LSB 2
+#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL2_RESET_MSB 0
+#define LF_TIMER_CONTROL2_RESET_LSB 0
+#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
+#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
+
+#define LF_TIMER_STATUS2_ADDRESS 0x00000074
+#define LF_TIMER_STATUS2_OFFSET 0x00000074
+#define LF_TIMER_STATUS2_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS2_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define LF_TIMER3_ADDRESS 0x00000078
+#define LF_TIMER3_OFFSET 0x00000078
+#define LF_TIMER3_TARGET_MSB 31
+#define LF_TIMER3_TARGET_LSB 0
+#define LF_TIMER3_TARGET_MASK 0xffffffff
+#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
+#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
+
+#define LF_TIMER_COUNT3_ADDRESS 0x0000007c
+#define LF_TIMER_COUNT3_OFFSET 0x0000007c
+#define LF_TIMER_COUNT3_VALUE_MSB 31
+#define LF_TIMER_COUNT3_VALUE_LSB 0
+#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
+#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
+
+#define LF_TIMER_CONTROL3_ADDRESS 0x00000080
+#define LF_TIMER_CONTROL3_OFFSET 0x00000080
+#define LF_TIMER_CONTROL3_ENABLE_MSB 2
+#define LF_TIMER_CONTROL3_ENABLE_LSB 2
+#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL3_RESET_MSB 0
+#define LF_TIMER_CONTROL3_RESET_LSB 0
+#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
+#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
+
+#define LF_TIMER_STATUS3_ADDRESS 0x00000084
+#define LF_TIMER_STATUS3_OFFSET 0x00000084
+#define LF_TIMER_STATUS3_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS3_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define HF_TIMER_ADDRESS 0x00000088
+#define HF_TIMER_OFFSET 0x00000088
+#define HF_TIMER_TARGET_MSB 31
+#define HF_TIMER_TARGET_LSB 12
+#define HF_TIMER_TARGET_MASK 0xfffff000
+#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
+#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
+
+#define HF_TIMER_COUNT_ADDRESS 0x0000008c
+#define HF_TIMER_COUNT_OFFSET 0x0000008c
+#define HF_TIMER_COUNT_VALUE_MSB 31
+#define HF_TIMER_COUNT_VALUE_LSB 12
+#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000
+#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
+#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
+
+#define HF_LF_COUNT_ADDRESS 0x00000090
+#define HF_LF_COUNT_OFFSET 0x00000090
+#define HF_LF_COUNT_VALUE_MSB 31
+#define HF_LF_COUNT_VALUE_LSB 0
+#define HF_LF_COUNT_VALUE_MASK 0xffffffff
+#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
+#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
+
+#define HF_TIMER_CONTROL_ADDRESS 0x00000094
+#define HF_TIMER_CONTROL_OFFSET 0x00000094
+#define HF_TIMER_CONTROL_ENABLE_MSB 3
+#define HF_TIMER_CONTROL_ENABLE_LSB 3
+#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008
+#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
+#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
+#define HF_TIMER_CONTROL_ON_MSB 2
+#define HF_TIMER_CONTROL_ON_LSB 2
+#define HF_TIMER_CONTROL_ON_MASK 0x00000004
+#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
+#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define HF_TIMER_CONTROL_RESET_MSB 0
+#define HF_TIMER_CONTROL_RESET_LSB 0
+#define HF_TIMER_CONTROL_RESET_MASK 0x00000001
+#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
+#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
+
+#define HF_TIMER_STATUS_ADDRESS 0x00000098
+#define HF_TIMER_STATUS_OFFSET 0x00000098
+#define HF_TIMER_STATUS_INTERRUPT_MSB 0
+#define HF_TIMER_STATUS_INTERRUPT_LSB 0
+#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001
+#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define RTC_CONTROL_ADDRESS 0x0000009c
+#define RTC_CONTROL_OFFSET 0x0000009c
+#define RTC_CONTROL_ENABLE_MSB 2
+#define RTC_CONTROL_ENABLE_LSB 2
+#define RTC_CONTROL_ENABLE_MASK 0x00000004
+#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
+#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
+#define RTC_CONTROL_LOAD_RTC_MSB 1
+#define RTC_CONTROL_LOAD_RTC_LSB 1
+#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002
+#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
+#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
+#define RTC_CONTROL_LOAD_ALARM_MSB 0
+#define RTC_CONTROL_LOAD_ALARM_LSB 0
+#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001
+#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
+#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define RTC_TIME_ADDRESS 0x000000a0
+#define RTC_TIME_OFFSET 0x000000a0
+#define RTC_TIME_WEEK_DAY_MSB 26
+#define RTC_TIME_WEEK_DAY_LSB 24
+#define RTC_TIME_WEEK_DAY_MASK 0x07000000
+#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
+#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
+#define RTC_TIME_HOUR_MSB 21
+#define RTC_TIME_HOUR_LSB 16
+#define RTC_TIME_HOUR_MASK 0x003f0000
+#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
+#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
+#define RTC_TIME_MINUTE_MSB 14
+#define RTC_TIME_MINUTE_LSB 8
+#define RTC_TIME_MINUTE_MASK 0x00007f00
+#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
+#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
+#define RTC_TIME_SECOND_MSB 6
+#define RTC_TIME_SECOND_LSB 0
+#define RTC_TIME_SECOND_MASK 0x0000007f
+#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
+#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
+
+#define RTC_DATE_ADDRESS 0x000000a4
+#define RTC_DATE_OFFSET 0x000000a4
+#define RTC_DATE_YEAR_MSB 23
+#define RTC_DATE_YEAR_LSB 16
+#define RTC_DATE_YEAR_MASK 0x00ff0000
+#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
+#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
+#define RTC_DATE_MONTH_MSB 12
+#define RTC_DATE_MONTH_LSB 8
+#define RTC_DATE_MONTH_MASK 0x00001f00
+#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
+#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
+#define RTC_DATE_MONTH_DAY_MSB 5
+#define RTC_DATE_MONTH_DAY_LSB 0
+#define RTC_DATE_MONTH_DAY_MASK 0x0000003f
+#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
+#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_TIME_ADDRESS 0x000000a8
+#define RTC_SET_TIME_OFFSET 0x000000a8
+#define RTC_SET_TIME_WEEK_DAY_MSB 26
+#define RTC_SET_TIME_WEEK_DAY_LSB 24
+#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000
+#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
+#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
+#define RTC_SET_TIME_HOUR_MSB 21
+#define RTC_SET_TIME_HOUR_LSB 16
+#define RTC_SET_TIME_HOUR_MASK 0x003f0000
+#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
+#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
+#define RTC_SET_TIME_MINUTE_MSB 14
+#define RTC_SET_TIME_MINUTE_LSB 8
+#define RTC_SET_TIME_MINUTE_MASK 0x00007f00
+#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
+#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
+#define RTC_SET_TIME_SECOND_MSB 6
+#define RTC_SET_TIME_SECOND_LSB 0
+#define RTC_SET_TIME_SECOND_MASK 0x0000007f
+#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
+#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
+
+#define RTC_SET_DATE_ADDRESS 0x000000ac
+#define RTC_SET_DATE_OFFSET 0x000000ac
+#define RTC_SET_DATE_YEAR_MSB 23
+#define RTC_SET_DATE_YEAR_LSB 16
+#define RTC_SET_DATE_YEAR_MASK 0x00ff0000
+#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
+#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
+#define RTC_SET_DATE_MONTH_MSB 12
+#define RTC_SET_DATE_MONTH_LSB 8
+#define RTC_SET_DATE_MONTH_MASK 0x00001f00
+#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
+#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
+#define RTC_SET_DATE_MONTH_DAY_MSB 5
+#define RTC_SET_DATE_MONTH_DAY_LSB 0
+#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f
+#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
+#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_ALARM_ADDRESS 0x000000b0
+#define RTC_SET_ALARM_OFFSET 0x000000b0
+#define RTC_SET_ALARM_HOUR_MSB 21
+#define RTC_SET_ALARM_HOUR_LSB 16
+#define RTC_SET_ALARM_HOUR_MASK 0x003f0000
+#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
+#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
+#define RTC_SET_ALARM_MINUTE_MSB 14
+#define RTC_SET_ALARM_MINUTE_LSB 8
+#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00
+#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
+#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
+#define RTC_SET_ALARM_SECOND_MSB 6
+#define RTC_SET_ALARM_SECOND_LSB 0
+#define RTC_SET_ALARM_SECOND_MASK 0x0000007f
+#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
+#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
+
+#define RTC_CONFIG_ADDRESS 0x000000b4
+#define RTC_CONFIG_OFFSET 0x000000b4
+#define RTC_CONFIG_BCD_MSB 2
+#define RTC_CONFIG_BCD_LSB 2
+#define RTC_CONFIG_BCD_MASK 0x00000004
+#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
+#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
+#define RTC_CONFIG_TWELVE_HOUR_MSB 1
+#define RTC_CONFIG_TWELVE_HOUR_LSB 1
+#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002
+#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
+#define RTC_CONFIG_DSE_MSB 0
+#define RTC_CONFIG_DSE_LSB 0
+#define RTC_CONFIG_DSE_MASK 0x00000001
+#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
+#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
+
+#define RTC_ALARM_STATUS_ADDRESS 0x000000b8
+#define RTC_ALARM_STATUS_OFFSET 0x000000b8
+#define RTC_ALARM_STATUS_ENABLE_MSB 1
+#define RTC_ALARM_STATUS_ENABLE_LSB 1
+#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002
+#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
+#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB 0
+#define RTC_ALARM_STATUS_INTERRUPT_LSB 0
+#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define UART_WAKEUP_ADDRESS 0x000000bc
+#define UART_WAKEUP_OFFSET 0x000000bc
+#define UART_WAKEUP_ENABLE_MSB 0
+#define UART_WAKEUP_ENABLE_LSB 0
+#define UART_WAKEUP_ENABLE_MASK 0x00000001
+#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
+#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
+
+#define RESET_CAUSE_ADDRESS 0x000000c0
+#define RESET_CAUSE_OFFSET 0x000000c0
+#define RESET_CAUSE_LAST_MSB 2
+#define RESET_CAUSE_LAST_LSB 0
+#define RESET_CAUSE_LAST_MASK 0x00000007
+#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
+#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
+
+#define SYSTEM_SLEEP_ADDRESS 0x000000c4
+#define SYSTEM_SLEEP_OFFSET 0x000000c4
+#define SYSTEM_SLEEP_HOST_IF_MSB 4
+#define SYSTEM_SLEEP_HOST_IF_LSB 4
+#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010
+#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
+#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
+#define SYSTEM_SLEEP_MBOX_MSB 3
+#define SYSTEM_SLEEP_MBOX_LSB 3
+#define SYSTEM_SLEEP_MBOX_MASK 0x00000008
+#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
+#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
+#define SYSTEM_SLEEP_MAC_IF_MSB 2
+#define SYSTEM_SLEEP_MAC_IF_LSB 2
+#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004
+#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
+#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
+#define SYSTEM_SLEEP_LIGHT_MSB 1
+#define SYSTEM_SLEEP_LIGHT_LSB 1
+#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002
+#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
+#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
+#define SYSTEM_SLEEP_DISABLE_MSB 0
+#define SYSTEM_SLEEP_DISABLE_LSB 0
+#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001
+#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+
+#define SDIO_WRAPPER_ADDRESS 0x000000c8
+#define SDIO_WRAPPER_OFFSET 0x000000c8
+#define SDIO_WRAPPER_SLEEP_MSB 3
+#define SDIO_WRAPPER_SLEEP_LSB 3
+#define SDIO_WRAPPER_SLEEP_MASK 0x00000008
+#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
+#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
+#define SDIO_WRAPPER_WAKEUP_MSB 2
+#define SDIO_WRAPPER_WAKEUP_LSB 2
+#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004
+#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
+#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
+#define SDIO_WRAPPER_SOC_ON_MSB 1
+#define SDIO_WRAPPER_SOC_ON_LSB 1
+#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002
+#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
+#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
+#define SDIO_WRAPPER_ON_MSB 0
+#define SDIO_WRAPPER_ON_LSB 0
+#define SDIO_WRAPPER_ON_MASK 0x00000001
+#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
+#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
+
+#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc
+#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc
+#define MAC_SLEEP_CONTROL_ENABLE_MSB 1
+#define MAC_SLEEP_CONTROL_ENABLE_LSB 0
+#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define KEEP_AWAKE_ADDRESS 0x000000d0
+#define KEEP_AWAKE_OFFSET 0x000000d0
+#define KEEP_AWAKE_COUNT_MSB 7
+#define KEEP_AWAKE_COUNT_LSB 0
+#define KEEP_AWAKE_COUNT_MASK 0x000000ff
+#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
+#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
+
+#define LPO_CAL_TIME_ADDRESS 0x000000d4
+#define LPO_CAL_TIME_OFFSET 0x000000d4
+#define LPO_CAL_TIME_LENGTH_MSB 13
+#define LPO_CAL_TIME_LENGTH_LSB 0
+#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff
+#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB)
+#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK)
+
+#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8
+#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define LPO_CAL_ADDRESS 0x000000e0
+#define LPO_CAL_OFFSET 0x000000e0
+#define LPO_CAL_ENABLE_MSB 20
+#define LPO_CAL_ENABLE_LSB 20
+#define LPO_CAL_ENABLE_MASK 0x00100000
+#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB)
+#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
+#define LPO_CAL_COUNT_MSB 19
+#define LPO_CAL_COUNT_LSB 0
+#define LPO_CAL_COUNT_MASK 0x000fffff
+#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB)
+#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK)
+
+#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4
+#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8
+#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8
+#define LPO_CAL_TEST_STATUS_READY_MSB 16
+#define LPO_CAL_TEST_STATUS_READY_LSB 16
+#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000
+#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB)
+#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB 15
+#define LPO_CAL_TEST_STATUS_COUNT_LSB 0
+#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define CHIP_ID_ADDRESS 0x000000ec
+#define CHIP_ID_OFFSET 0x000000ec
+#define CHIP_ID_DEVICE_ID_MSB 31
+#define CHIP_ID_DEVICE_ID_LSB 16
+#define CHIP_ID_DEVICE_ID_MASK 0xffff0000
+#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB)
+#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK)
+#define CHIP_ID_CONFIG_ID_MSB 15
+#define CHIP_ID_CONFIG_ID_LSB 4
+#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0
+#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB)
+#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK)
+#define CHIP_ID_VERSION_ID_MSB 3
+#define CHIP_ID_VERSION_ID_LSB 0
+#define CHIP_ID_VERSION_ID_MASK 0x0000000f
+#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB)
+#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK)
+
+#define DERIVED_RTC_CLK_ADDRESS 0x000000f0
+#define DERIVED_RTC_CLK_OFFSET 0x000000f0
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define DERIVED_RTC_CLK_FORCE_MSB 17
+#define DERIVED_RTC_CLK_FORCE_LSB 16
+#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000
+#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
+#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
+#define DERIVED_RTC_CLK_PERIOD_MSB 15
+#define DERIVED_RTC_CLK_PERIOD_LSB 1
+#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe
+#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
+#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB 1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB 1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c
+#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK)
+
+#define POWER_REG_ADDRESS 0x00000110
+#define POWER_REG_OFFSET 0x00000110
+#define POWER_REG_VLVL_MSB 11
+#define POWER_REG_VLVL_LSB 8
+#define POWER_REG_VLVL_MASK 0x00000f00
+#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB)
+#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK)
+#define POWER_REG_CPU_INT_ENABLE_MSB 7
+#define POWER_REG_CPU_INT_ENABLE_LSB 7
+#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080
+#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB)
+#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK)
+#define POWER_REG_WLAN_ISO_DIS_MSB 6
+#define POWER_REG_WLAN_ISO_DIS_LSB 6
+#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040
+#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB)
+#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK)
+#define POWER_REG_WLAN_ISO_CNTL_MSB 5
+#define POWER_REG_WLAN_ISO_CNTL_LSB 5
+#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020
+#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK)
+#define POWER_REG_RADIO_PWD_EN_MSB 4
+#define POWER_REG_RADIO_PWD_EN_LSB 4
+#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010
+#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB)
+#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK)
+#define POWER_REG_SOC_SCALE_EN_MSB 3
+#define POWER_REG_SOC_SCALE_EN_LSB 3
+#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008
+#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB)
+#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK)
+#define POWER_REG_WLAN_SCALE_EN_MSB 2
+#define POWER_REG_WLAN_SCALE_EN_LSB 2
+#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004
+#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB)
+#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK)
+#define POWER_REG_WLAN_PWD_EN_MSB 1
+#define POWER_REG_WLAN_PWD_EN_LSB 1
+#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002
+#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB)
+#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK)
+#define POWER_REG_POWER_EN_MSB 0
+#define POWER_REG_POWER_EN_LSB 0
+#define POWER_REG_POWER_EN_MASK 0x00000001
+#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB)
+#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK)
+
+#define CORE_CLK_CTRL_ADDRESS 0x00000114
+#define CORE_CLK_CTRL_OFFSET 0x00000114
+#define CORE_CLK_CTRL_DIV_MSB 2
+#define CORE_CLK_CTRL_DIV_LSB 0
+#define CORE_CLK_CTRL_DIV_MASK 0x00000007
+#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB)
+#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK)
+
+#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120
+#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120
+#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7
+#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0
+#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
+#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
+#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140
+#define SDIO_SETUP_CONFIG_OFFSET 0x00000140
+#define SDIO_SETUP_CONFIG_ENABLE_MSB 1
+#define SDIO_SETUP_CONFIG_ENABLE_LSB 1
+#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002
+#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
+#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
+#define SDIO_SETUP_CONFIG_CLEAR_MSB 0
+#define SDIO_SETUP_CONFIG_CLEAR_LSB 0
+#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001
+#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
+#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CONFIG_ADDRESS 0x00000144
+#define CPU_SETUP_CONFIG_OFFSET 0x00000144
+#define CPU_SETUP_CONFIG_ENABLE_MSB 1
+#define CPU_SETUP_CONFIG_ENABLE_LSB 1
+#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002
+#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
+#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
+#define CPU_SETUP_CONFIG_CLEAR_MSB 0
+#define CPU_SETUP_CONFIG_CLEAR_LSB 0
+#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001
+#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
+#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160
+#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160
+#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7
+#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0
+#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
+#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
+#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define BB_SETUP_CONFIG_ADDRESS 0x00000180
+#define BB_SETUP_CONFIG_OFFSET 0x00000180
+#define BB_SETUP_CONFIG_ENABLE_MSB 1
+#define BB_SETUP_CONFIG_ENABLE_LSB 1
+#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002
+#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
+#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
+#define BB_SETUP_CONFIG_CLEAR_MSB 0
+#define BB_SETUP_CONFIG_CLEAR_LSB 0
+#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001
+#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
+#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
+
+#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0
+#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0
+#define BB_SETUP_CIRCUIT_VECTOR_MSB 7
+#define BB_SETUP_CIRCUIT_VECTOR_LSB 0
+#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
+#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
+#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0
+#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_reg_reg_s {
+ volatile unsigned int reset_control;
+ volatile unsigned int xtal_control;
+ volatile unsigned int tcxo_detect;
+ volatile unsigned int xtal_test;
+ volatile unsigned int quadrature;
+ volatile unsigned int pll_control;
+ volatile unsigned int pll_settle;
+ volatile unsigned int xtal_settle;
+ volatile unsigned int cpu_clock;
+ volatile unsigned int clock_out;
+ volatile unsigned int clock_control;
+ volatile unsigned int bias_override;
+ volatile unsigned int wdt_control;
+ volatile unsigned int wdt_status;
+ volatile unsigned int wdt;
+ volatile unsigned int wdt_count;
+ volatile unsigned int wdt_reset;
+ volatile unsigned int int_status;
+ volatile unsigned int lf_timer0;
+ volatile unsigned int lf_timer_count0;
+ volatile unsigned int lf_timer_control0;
+ volatile unsigned int lf_timer_status0;
+ volatile unsigned int lf_timer1;
+ volatile unsigned int lf_timer_count1;
+ volatile unsigned int lf_timer_control1;
+ volatile unsigned int lf_timer_status1;
+ volatile unsigned int lf_timer2;
+ volatile unsigned int lf_timer_count2;
+ volatile unsigned int lf_timer_control2;
+ volatile unsigned int lf_timer_status2;
+ volatile unsigned int lf_timer3;
+ volatile unsigned int lf_timer_count3;
+ volatile unsigned int lf_timer_control3;
+ volatile unsigned int lf_timer_status3;
+ volatile unsigned int hf_timer;
+ volatile unsigned int hf_timer_count;
+ volatile unsigned int hf_lf_count;
+ volatile unsigned int hf_timer_control;
+ volatile unsigned int hf_timer_status;
+ volatile unsigned int rtc_control;
+ volatile unsigned int rtc_time;
+ volatile unsigned int rtc_date;
+ volatile unsigned int rtc_set_time;
+ volatile unsigned int rtc_set_date;
+ volatile unsigned int rtc_set_alarm;
+ volatile unsigned int rtc_config;
+ volatile unsigned int rtc_alarm_status;
+ volatile unsigned int uart_wakeup;
+ volatile unsigned int reset_cause;
+ volatile unsigned int system_sleep;
+ volatile unsigned int sdio_wrapper;
+ volatile unsigned int mac_sleep_control;
+ volatile unsigned int keep_awake;
+ volatile unsigned int lpo_cal_time;
+ volatile unsigned int lpo_init_dividend_int;
+ volatile unsigned int lpo_init_dividend_fraction;
+ volatile unsigned int lpo_cal;
+ volatile unsigned int lpo_cal_test_control;
+ volatile unsigned int lpo_cal_test_status;
+ volatile unsigned int chip_id;
+ volatile unsigned int derived_rtc_clk;
+ volatile unsigned int mac_pcu_slp32_mode;
+ volatile unsigned int mac_pcu_slp32_wake;
+ volatile unsigned int mac_pcu_slp32_inc;
+ volatile unsigned int mac_pcu_slp_mib1;
+ volatile unsigned int mac_pcu_slp_mib2;
+ volatile unsigned int mac_pcu_slp_mib3;
+ volatile unsigned int mac_pcu_slp_beacon;
+ volatile unsigned int power_reg;
+ volatile unsigned int core_clk_ctrl;
+ unsigned char pad0[8]; /* pad to 0x120 */
+ volatile unsigned int sdio_setup_circuit[8];
+ volatile unsigned int sdio_setup_config;
+ volatile unsigned int cpu_setup_config;
+ unsigned char pad1[24]; /* pad to 0x160 */
+ volatile unsigned int cpu_setup_circuit[8];
+ volatile unsigned int bb_setup_config;
+ unsigned char pad2[28]; /* pad to 0x1a0 */
+ volatile unsigned int bb_setup_circuit[8];
+ volatile unsigned int gpio_wakeup_control;
+} rtc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h
new file mode 100644
index 000000000000..44d24661761e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h
@@ -0,0 +1,205 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS 0x00000000
+#define SI_CONFIG_OFFSET 0x00000000
+#define SI_CONFIG_ERR_INT_MSB 19
+#define SI_CONFIG_ERR_INT_LSB 19
+#define SI_CONFIG_ERR_INT_MASK 0x00080000
+#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB 16
+#define SI_CONFIG_I2C_LSB 16
+#define SI_CONFIG_I2C_MASK 0x00010000
+#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB 7
+#define SI_CONFIG_POS_SAMPLE_LSB 7
+#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB 6
+#define SI_CONFIG_POS_DRIVE_LSB 6
+#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB 5
+#define SI_CONFIG_INACTIVE_DATA_LSB 5
+#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB 4
+#define SI_CONFIG_INACTIVE_CLK_LSB 4
+#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB 3
+#define SI_CONFIG_DIVIDER_LSB 0
+#define SI_CONFIG_DIVIDER_MASK 0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS 0x00000004
+#define SI_CS_OFFSET 0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB 10
+#define SI_CS_DONE_ERR_LSB 10
+#define SI_CS_DONE_ERR_MASK 0x00000400
+#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB 9
+#define SI_CS_DONE_INT_LSB 9
+#define SI_CS_DONE_INT_MASK 0x00000200
+#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB 8
+#define SI_CS_START_LSB 8
+#define SI_CS_START_MASK 0x00000100
+#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB 7
+#define SI_CS_RX_CNT_LSB 4
+#define SI_CS_RX_CNT_MASK 0x000000f0
+#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB 3
+#define SI_CS_TX_CNT_LSB 0
+#define SI_CS_TX_CNT_MASK 0x0000000f
+#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS 0x00000008
+#define SI_TX_DATA0_OFFSET 0x00000008
+#define SI_TX_DATA0_DATA3_MSB 31
+#define SI_TX_DATA0_DATA3_LSB 24
+#define SI_TX_DATA0_DATA3_MASK 0xff000000
+#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB 23
+#define SI_TX_DATA0_DATA2_LSB 16
+#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB 15
+#define SI_TX_DATA0_DATA1_LSB 8
+#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB 7
+#define SI_TX_DATA0_DATA0_LSB 0
+#define SI_TX_DATA0_DATA0_MASK 0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS 0x0000000c
+#define SI_TX_DATA1_OFFSET 0x0000000c
+#define SI_TX_DATA1_DATA7_MSB 31
+#define SI_TX_DATA1_DATA7_LSB 24
+#define SI_TX_DATA1_DATA7_MASK 0xff000000
+#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB 23
+#define SI_TX_DATA1_DATA6_LSB 16
+#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB 15
+#define SI_TX_DATA1_DATA5_LSB 8
+#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB 7
+#define SI_TX_DATA1_DATA4_LSB 0
+#define SI_TX_DATA1_DATA4_MASK 0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS 0x00000010
+#define SI_RX_DATA0_OFFSET 0x00000010
+#define SI_RX_DATA0_DATA3_MSB 31
+#define SI_RX_DATA0_DATA3_LSB 24
+#define SI_RX_DATA0_DATA3_MASK 0xff000000
+#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB 23
+#define SI_RX_DATA0_DATA2_LSB 16
+#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB 15
+#define SI_RX_DATA0_DATA1_LSB 8
+#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB 7
+#define SI_RX_DATA0_DATA0_LSB 0
+#define SI_RX_DATA0_DATA0_MASK 0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS 0x00000014
+#define SI_RX_DATA1_OFFSET 0x00000014
+#define SI_RX_DATA1_DATA7_MSB 31
+#define SI_RX_DATA1_DATA7_LSB 24
+#define SI_RX_DATA1_DATA7_MASK 0xff000000
+#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB 23
+#define SI_RX_DATA1_DATA6_LSB 16
+#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB 15
+#define SI_RX_DATA1_DATA5_LSB 8
+#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB 7
+#define SI_RX_DATA1_DATA4_LSB 0
+#define SI_RX_DATA1_DATA4_MASK 0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+ volatile unsigned int si_config;
+ volatile unsigned int si_cs;
+ volatile unsigned int si_tx_data0;
+ volatile unsigned int si_tx_data1;
+ volatile unsigned int si_rx_data0;
+ volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h
new file mode 100644
index 000000000000..db573106dcd2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h
@@ -0,0 +1,346 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define RBR_ADDRESS 0x00000000
+#define RBR_OFFSET 0x00000000
+#define RBR_RBR_MSB 7
+#define RBR_RBR_LSB 0
+#define RBR_RBR_MASK 0x000000ff
+#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
+#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
+
+#define THR_ADDRESS 0x00000000
+#define THR_OFFSET 0x00000000
+#define THR_THR_MSB 7
+#define THR_THR_LSB 0
+#define THR_THR_MASK 0x000000ff
+#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
+#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
+
+#define DLL_ADDRESS 0x00000000
+#define DLL_OFFSET 0x00000000
+#define DLL_DLL_MSB 7
+#define DLL_DLL_LSB 0
+#define DLL_DLL_MASK 0x000000ff
+#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
+#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
+
+#define DLH_ADDRESS 0x00000004
+#define DLH_OFFSET 0x00000004
+#define DLH_DLH_MSB 7
+#define DLH_DLH_LSB 0
+#define DLH_DLH_MASK 0x000000ff
+#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
+#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
+
+#define IER_ADDRESS 0x00000004
+#define IER_OFFSET 0x00000004
+#define IER_EDDSI_MSB 3
+#define IER_EDDSI_LSB 3
+#define IER_EDDSI_MASK 0x00000008
+#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
+#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
+#define IER_ELSI_MSB 2
+#define IER_ELSI_LSB 2
+#define IER_ELSI_MASK 0x00000004
+#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
+#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
+#define IER_ETBEI_MSB 1
+#define IER_ETBEI_LSB 1
+#define IER_ETBEI_MASK 0x00000002
+#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
+#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
+#define IER_ERBFI_MSB 0
+#define IER_ERBFI_LSB 0
+#define IER_ERBFI_MASK 0x00000001
+#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
+#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
+
+#define IIR_ADDRESS 0x00000008
+#define IIR_OFFSET 0x00000008
+#define IIR_FIFO_STATUS_MSB 7
+#define IIR_FIFO_STATUS_LSB 6
+#define IIR_FIFO_STATUS_MASK 0x000000c0
+#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
+#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
+#define IIR_IID_MSB 3
+#define IIR_IID_LSB 0
+#define IIR_IID_MASK 0x0000000f
+#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
+#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
+
+#define FCR_ADDRESS 0x00000008
+#define FCR_OFFSET 0x00000008
+#define FCR_RCVR_TRIG_MSB 7
+#define FCR_RCVR_TRIG_LSB 6
+#define FCR_RCVR_TRIG_MASK 0x000000c0
+#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
+#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
+#define FCR_DMA_MODE_MSB 3
+#define FCR_DMA_MODE_LSB 3
+#define FCR_DMA_MODE_MASK 0x00000008
+#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
+#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
+#define FCR_XMIT_FIFO_RST_MSB 2
+#define FCR_XMIT_FIFO_RST_LSB 2
+#define FCR_XMIT_FIFO_RST_MASK 0x00000004
+#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
+#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
+#define FCR_RCVR_FIFO_RST_MSB 1
+#define FCR_RCVR_FIFO_RST_LSB 1
+#define FCR_RCVR_FIFO_RST_MASK 0x00000002
+#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
+#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
+#define FCR_FIFO_EN_MSB 0
+#define FCR_FIFO_EN_LSB 0
+#define FCR_FIFO_EN_MASK 0x00000001
+#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
+#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
+
+#define LCR_ADDRESS 0x0000000c
+#define LCR_OFFSET 0x0000000c
+#define LCR_DLAB_MSB 7
+#define LCR_DLAB_LSB 7
+#define LCR_DLAB_MASK 0x00000080
+#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
+#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
+#define LCR_BREAK_MSB 6
+#define LCR_BREAK_LSB 6
+#define LCR_BREAK_MASK 0x00000040
+#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
+#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
+#define LCR_EPS_MSB 4
+#define LCR_EPS_LSB 4
+#define LCR_EPS_MASK 0x00000010
+#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
+#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
+#define LCR_PEN_MSB 3
+#define LCR_PEN_LSB 3
+#define LCR_PEN_MASK 0x00000008
+#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
+#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
+#define LCR_STOP_MSB 2
+#define LCR_STOP_LSB 2
+#define LCR_STOP_MASK 0x00000004
+#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
+#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
+#define LCR_CLS_MSB 1
+#define LCR_CLS_LSB 0
+#define LCR_CLS_MASK 0x00000003
+#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
+#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
+
+#define MCR_ADDRESS 0x00000010
+#define MCR_OFFSET 0x00000010
+#define MCR_LOOPBACK_MSB 5
+#define MCR_LOOPBACK_LSB 5
+#define MCR_LOOPBACK_MASK 0x00000020
+#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
+#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
+#define MCR_OUT2_MSB 3
+#define MCR_OUT2_LSB 3
+#define MCR_OUT2_MASK 0x00000008
+#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
+#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
+#define MCR_OUT1_MSB 2
+#define MCR_OUT1_LSB 2
+#define MCR_OUT1_MASK 0x00000004
+#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
+#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
+#define MCR_RTS_MSB 1
+#define MCR_RTS_LSB 1
+#define MCR_RTS_MASK 0x00000002
+#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
+#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
+#define MCR_DTR_MSB 0
+#define MCR_DTR_LSB 0
+#define MCR_DTR_MASK 0x00000001
+#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
+#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
+
+#define LSR_ADDRESS 0x00000014
+#define LSR_OFFSET 0x00000014
+#define LSR_FERR_MSB 7
+#define LSR_FERR_LSB 7
+#define LSR_FERR_MASK 0x00000080
+#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
+#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
+#define LSR_TEMT_MSB 6
+#define LSR_TEMT_LSB 6
+#define LSR_TEMT_MASK 0x00000040
+#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
+#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
+#define LSR_THRE_MSB 5
+#define LSR_THRE_LSB 5
+#define LSR_THRE_MASK 0x00000020
+#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
+#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
+#define LSR_BI_MSB 4
+#define LSR_BI_LSB 4
+#define LSR_BI_MASK 0x00000010
+#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
+#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
+#define LSR_FE_MSB 3
+#define LSR_FE_LSB 3
+#define LSR_FE_MASK 0x00000008
+#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
+#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
+#define LSR_PE_MSB 2
+#define LSR_PE_LSB 2
+#define LSR_PE_MASK 0x00000004
+#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
+#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
+#define LSR_OE_MSB 1
+#define LSR_OE_LSB 1
+#define LSR_OE_MASK 0x00000002
+#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
+#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
+#define LSR_DR_MSB 0
+#define LSR_DR_LSB 0
+#define LSR_DR_MASK 0x00000001
+#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
+#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
+
+#define MSR_ADDRESS 0x00000018
+#define MSR_OFFSET 0x00000018
+#define MSR_DCD_MSB 7
+#define MSR_DCD_LSB 7
+#define MSR_DCD_MASK 0x00000080
+#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
+#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
+#define MSR_RI_MSB 6
+#define MSR_RI_LSB 6
+#define MSR_RI_MASK 0x00000040
+#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
+#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
+#define MSR_DSR_MSB 5
+#define MSR_DSR_LSB 5
+#define MSR_DSR_MASK 0x00000020
+#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
+#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
+#define MSR_CTS_MSB 4
+#define MSR_CTS_LSB 4
+#define MSR_CTS_MASK 0x00000010
+#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
+#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
+#define MSR_DDCD_MSB 3
+#define MSR_DDCD_LSB 3
+#define MSR_DDCD_MASK 0x00000008
+#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
+#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
+#define MSR_TERI_MSB 2
+#define MSR_TERI_LSB 2
+#define MSR_TERI_MASK 0x00000004
+#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
+#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
+#define MSR_DDSR_MSB 1
+#define MSR_DDSR_LSB 1
+#define MSR_DDSR_MASK 0x00000002
+#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
+#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
+#define MSR_DCTS_MSB 0
+#define MSR_DCTS_LSB 0
+#define MSR_DCTS_MASK 0x00000001
+#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
+#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
+
+#define SCR_ADDRESS 0x0000001c
+#define SCR_OFFSET 0x0000001c
+#define SCR_SCR_MSB 7
+#define SCR_SCR_LSB 0
+#define SCR_SCR_MASK 0x000000ff
+#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
+#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
+
+#define SRBR_ADDRESS 0x00000020
+#define SRBR_OFFSET 0x00000020
+#define SRBR_SRBR_MSB 7
+#define SRBR_SRBR_LSB 0
+#define SRBR_SRBR_MASK 0x000000ff
+#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
+#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
+
+#define SIIR_ADDRESS 0x00000028
+#define SIIR_OFFSET 0x00000028
+#define SIIR_SIIR_MSB 7
+#define SIIR_SIIR_LSB 0
+#define SIIR_SIIR_MASK 0x000000ff
+#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
+#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
+
+#define MWR_ADDRESS 0x0000002c
+#define MWR_OFFSET 0x0000002c
+#define MWR_MWR_MSB 31
+#define MWR_MWR_LSB 0
+#define MWR_MWR_MASK 0xffffffff
+#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
+#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
+
+#define SLSR_ADDRESS 0x00000034
+#define SLSR_OFFSET 0x00000034
+#define SLSR_SLSR_MSB 7
+#define SLSR_SLSR_LSB 0
+#define SLSR_SLSR_MASK 0x000000ff
+#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
+#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
+
+#define SMSR_ADDRESS 0x00000038
+#define SMSR_OFFSET 0x00000038
+#define SMSR_SMSR_MSB 7
+#define SMSR_SMSR_LSB 0
+#define SMSR_SMSR_MASK 0x000000ff
+#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
+#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
+
+#define MRR_ADDRESS 0x0000003c
+#define MRR_OFFSET 0x0000003c
+#define MRR_MRR_MSB 31
+#define MRR_MRR_LSB 0
+#define MRR_MRR_MASK 0xffffffff
+#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
+#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+ volatile unsigned int rbr;
+ volatile unsigned int dlh;
+ volatile unsigned int iir;
+ volatile unsigned int lcr;
+ volatile unsigned int mcr;
+ volatile unsigned int lsr;
+ volatile unsigned int msr;
+ volatile unsigned int scr;
+ volatile unsigned int srbr;
+ unsigned char pad0[4]; /* pad to 0x28 */
+ volatile unsigned int siir;
+ volatile unsigned int mwr;
+ unsigned char pad1[4]; /* pad to 0x34 */
+ volatile unsigned int slsr;
+ volatile unsigned int smsr;
+ volatile unsigned int mrr;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h
new file mode 100644
index 000000000000..0c15ebfaeaa6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h
@@ -0,0 +1,95 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_REG_REG_H_
+#define _VMC_REG_REG_H_
+
+#define MC_TCAM_VALID_ADDRESS 0x00000000
+#define MC_TCAM_VALID_OFFSET 0x00000000
+#define MC_TCAM_VALID_BIT_MSB 0
+#define MC_TCAM_VALID_BIT_LSB 0
+#define MC_TCAM_VALID_BIT_MASK 0x00000001
+#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
+#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
+
+#define MC_TCAM_MASK_ADDRESS 0x00000080
+#define MC_TCAM_MASK_OFFSET 0x00000080
+#define MC_TCAM_MASK_SIZE_MSB 2
+#define MC_TCAM_MASK_SIZE_LSB 0
+#define MC_TCAM_MASK_SIZE_MASK 0x00000007
+#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
+#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
+
+#define MC_TCAM_COMPARE_ADDRESS 0x00000100
+#define MC_TCAM_COMPARE_OFFSET 0x00000100
+#define MC_TCAM_COMPARE_KEY_MSB 21
+#define MC_TCAM_COMPARE_KEY_LSB 5
+#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0
+#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
+#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
+
+#define MC_TCAM_TARGET_ADDRESS 0x00000180
+#define MC_TCAM_TARGET_OFFSET 0x00000180
+#define MC_TCAM_TARGET_ADDR_MSB 21
+#define MC_TCAM_TARGET_ADDR_LSB 5
+#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0
+#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
+#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
+
+#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200
+#define ADDR_ERROR_CONTROL_OFFSET 0x00000200
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define ADDR_ERROR_CONTROL_ENABLE_MSB 0
+#define ADDR_ERROR_CONTROL_ENABLE_LSB 0
+#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
+#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define ADDR_ERROR_STATUS_ADDRESS 0x00000204
+#define ADDR_ERROR_STATUS_OFFSET 0x00000204
+#define ADDR_ERROR_STATUS_WRITE_MSB 25
+#define ADDR_ERROR_STATUS_WRITE_LSB 25
+#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
+#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
+#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
+#define ADDR_ERROR_STATUS_ADDRESS_MSB 24
+#define ADDR_ERROR_STATUS_ADDRESS_LSB 0
+#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
+#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_reg_reg_s {
+ volatile unsigned int mc_tcam_valid[32];
+ volatile unsigned int mc_tcam_mask[32];
+ volatile unsigned int mc_tcam_compare[32];
+ volatile unsigned int mc_tcam_target[32];
+ volatile unsigned int addr_error_control;
+ volatile unsigned int addr_error_status;
+} vmc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h
new file mode 100644
index 000000000000..28b972afc8d7
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h
@@ -0,0 +1,83 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_INTF_REG_REG_H_
+#define _ANALOG_INTF_REG_REG_H_
+
+#define SW_OVERRIDE_ADDRESS 0x00000080
+#define SW_OVERRIDE_OFFSET 0x00000080
+#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1
+#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1
+#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002
+#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
+#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
+#define SW_OVERRIDE_ENABLE_MSB 0
+#define SW_OVERRIDE_ENABLE_LSB 0
+#define SW_OVERRIDE_ENABLE_MASK 0x00000001
+#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
+#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
+
+#define SIN_VAL_ADDRESS 0x00000084
+#define SIN_VAL_OFFSET 0x00000084
+#define SIN_VAL_SIN_MSB 0
+#define SIN_VAL_SIN_LSB 0
+#define SIN_VAL_SIN_MASK 0x00000001
+#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
+#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
+
+#define SW_SCLK_ADDRESS 0x00000088
+#define SW_SCLK_OFFSET 0x00000088
+#define SW_SCLK_SW_SCLK_MSB 0
+#define SW_SCLK_SW_SCLK_LSB 0
+#define SW_SCLK_SW_SCLK_MASK 0x00000001
+#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
+#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
+
+#define SW_CNTL_ADDRESS 0x0000008c
+#define SW_CNTL_OFFSET 0x0000008c
+#define SW_CNTL_SW_SCAPTURE_MSB 2
+#define SW_CNTL_SW_SCAPTURE_LSB 2
+#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004
+#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
+#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
+#define SW_CNTL_SW_SUPDATE_MSB 1
+#define SW_CNTL_SW_SUPDATE_LSB 1
+#define SW_CNTL_SW_SUPDATE_MASK 0x00000002
+#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
+#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
+#define SW_CNTL_SW_SOUT_MSB 0
+#define SW_CNTL_SW_SOUT_LSB 0
+#define SW_CNTL_SW_SOUT_MASK 0x00000001
+#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
+#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_reg_reg_s {
+ unsigned char pad0[128]; /* pad to 0x80 */
+ volatile unsigned int sw_override;
+ volatile unsigned int sin_val;
+ volatile unsigned int sw_sclk;
+ volatile unsigned int sw_cntl;
+} analog_intf_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h
new file mode 100644
index 000000000000..c485ac725c2f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h
@@ -0,0 +1,1951 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _ANALOG_REG_REG_H_
+#define _ANALOG_REG_REG_H_
+
+#define SYNTH_SYNTH1_ADDRESS 0x00000000
+#define SYNTH_SYNTH1_OFFSET 0x00000000
+#define SYNTH_SYNTH1_PWD_BIAS_MSB 31
+#define SYNTH_SYNTH1_PWD_BIAS_LSB 31
+#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000
+#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB)
+#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK)
+#define SYNTH_SYNTH1_PWD_CP_MSB 30
+#define SYNTH_SYNTH1_PWD_CP_LSB 30
+#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000
+#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB)
+#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK)
+#define SYNTH_SYNTH1_PWD_VCMON_MSB 29
+#define SYNTH_SYNTH1_PWD_VCMON_LSB 29
+#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000
+#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB)
+#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK)
+#define SYNTH_SYNTH1_PWD_VCO_MSB 28
+#define SYNTH_SYNTH1_PWD_VCO_LSB 28
+#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000
+#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB)
+#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK)
+#define SYNTH_SYNTH1_PWD_PRESC_MSB 27
+#define SYNTH_SYNTH1_PWD_PRESC_LSB 27
+#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000
+#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB)
+#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK)
+#define SYNTH_SYNTH1_PWD_LODIV_MSB 26
+#define SYNTH_SYNTH1_PWD_LODIV_LSB 26
+#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000
+#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB)
+#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK)
+#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25
+#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25
+#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000
+#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB)
+#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK)
+#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24
+#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24
+#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000
+#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB)
+#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23
+#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000
+#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB)
+#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK)
+#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22
+#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22
+#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000
+#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB)
+#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK)
+#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21
+#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20
+#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000
+#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB)
+#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK)
+#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19
+#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18
+#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000
+#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB)
+#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK)
+#define SYNTH_SYNTH1_SLIDINGIF_MSB 17
+#define SYNTH_SYNTH1_SLIDINGIF_LSB 17
+#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000
+#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB)
+#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK)
+#define SYNTH_SYNTH1_SPARE_PWD_MSB 16
+#define SYNTH_SYNTH1_SPARE_PWD_LSB 16
+#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000
+#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB)
+#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15
+#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000
+#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14
+#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14
+#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000
+#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB)
+#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK)
+#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13
+#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13
+#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000
+#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB)
+#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12
+#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10
+#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00
+#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB)
+#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB)
+#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_MSB 5
+#define SYNTH_SYNTH1_MONITOR_FB_LSB 5
+#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020
+#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK)
+#define SYNTH_SYNTH1_MONITOR_REF_MSB 4
+#define SYNTH_SYNTH1_MONITOR_REF_LSB 4
+#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010
+#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB)
+#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB)
+#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB)
+#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB)
+#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK)
+
+#define SYNTH_SYNTH2_ADDRESS 0x00000004
+#define SYNTH_SYNTH2_OFFSET 0x00000004
+#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31
+#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29
+#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000
+#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB)
+#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK)
+#define SYNTH_SYNTH2_VC_HI_REF_MSB 28
+#define SYNTH_SYNTH2_VC_HI_REF_LSB 26
+#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000
+#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB)
+#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK)
+#define SYNTH_SYNTH2_VC_MID_REF_MSB 25
+#define SYNTH_SYNTH2_VC_MID_REF_LSB 23
+#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000
+#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB)
+#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK)
+#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22
+#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20
+#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000
+#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB)
+#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB)
+#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK)
+#define SYNTH_SYNTH2_LOOP_CP_MSB 14
+#define SYNTH_SYNTH2_LOOP_CP_LSB 10
+#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00
+#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB)
+#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK)
+#define SYNTH_SYNTH2_LOOP_RS_MSB 9
+#define SYNTH_SYNTH2_LOOP_RS_LSB 5
+#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0
+#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB)
+#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK)
+#define SYNTH_SYNTH2_LOOP_CS_MSB 4
+#define SYNTH_SYNTH2_LOOP_CS_LSB 3
+#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018
+#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB)
+#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK)
+#define SYNTH_SYNTH2_SPARE_BITS_MSB 2
+#define SYNTH_SYNTH2_SPARE_BITS_LSB 0
+#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007
+#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB)
+#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK)
+
+#define SYNTH_SYNTH3_ADDRESS 0x00000008
+#define SYNTH_SYNTH3_OFFSET 0x00000008
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB)
+#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB)
+#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23
+#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18
+#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
+#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB)
+#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB)
+#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB)
+#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK)
+
+#define SYNTH_SYNTH4_ADDRESS 0x0000000c
+#define SYNTH_SYNTH4_OFFSET 0x0000000c
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB)
+#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK)
+#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30
+#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30
+#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000
+#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB)
+#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB)
+#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB)
+#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK)
+#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27
+#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27
+#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000
+#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB)
+#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26
+#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
+#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB)
+#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK)
+#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25
+#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18
+#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
+#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB)
+#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17
+#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
+#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB)
+#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK)
+#define SYNTH_SYNTH4_REFDIVSEL_MSB 16
+#define SYNTH_SYNTH4_REFDIVSEL_LSB 15
+#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000
+#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB)
+#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK)
+#define SYNTH_SYNTH4_PFDDELAY_MSB 14
+#define SYNTH_SYNTH4_PFDDELAY_LSB 14
+#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000
+#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB)
+#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK)
+#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13
+#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13
+#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000
+#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB)
+#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK)
+#define SYNTH_SYNTH4_PRESCSEL_MSB 12
+#define SYNTH_SYNTH4_PRESCSEL_LSB 11
+#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800
+#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB)
+#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK)
+#define SYNTH_SYNTH4_RESET_PRESC_MSB 10
+#define SYNTH_SYNTH4_RESET_PRESC_LSB 10
+#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400
+#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB)
+#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK)
+#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9
+#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9
+#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200
+#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB)
+#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK)
+#define SYNTH_SYNTH4_SDM_MODE_MSB 8
+#define SYNTH_SYNTH4_SDM_MODE_LSB 8
+#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100
+#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB)
+#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK)
+#define SYNTH_SYNTH4_SDM_DITHER_MSB 7
+#define SYNTH_SYNTH4_SDM_DITHER_LSB 6
+#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0
+#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB)
+#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB)
+#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB)
+#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK)
+#define SYNTH_SYNTH4_SPARE_MISC_MSB 3
+#define SYNTH_SYNTH4_SPARE_MISC_LSB 2
+#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c
+#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB)
+#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1
+#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
+#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB)
+#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB)
+#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK)
+
+#define SYNTH_SYNTH5_ADDRESS 0x00000010
+#define SYNTH_SYNTH5_OFFSET 0x00000010
+#define SYNTH_SYNTH5_LOOP_IP0_MSB 31
+#define SYNTH_SYNTH5_LOOP_IP0_LSB 28
+#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000
+#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB)
+#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK)
+#define SYNTH_SYNTH5_SLOPE_IP_MSB 27
+#define SYNTH_SYNTH5_SLOPE_IP_LSB 25
+#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000
+#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB)
+#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK)
+#define SYNTH_SYNTH5_CPBIAS_MSB 24
+#define SYNTH_SYNTH5_CPBIAS_LSB 23
+#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000
+#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB)
+#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK)
+#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22
+#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22
+#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000
+#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB)
+#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK)
+#define SYNTH_SYNTH5_CPLOWLK_MSB 21
+#define SYNTH_SYNTH5_CPLOWLK_LSB 21
+#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000
+#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB)
+#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20
+#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17
+#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000
+#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB)
+#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK)
+#define SYNTH_SYNTH5_CAPRANGE1_MSB 16
+#define SYNTH_SYNTH5_CAPRANGE1_LSB 13
+#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000
+#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB)
+#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK)
+#define SYNTH_SYNTH5_CAPRANGE2_MSB 12
+#define SYNTH_SYNTH5_CAPRANGE2_LSB 9
+#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00
+#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB)
+#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK)
+#define SYNTH_SYNTH5_CAPRANGE3_MSB 8
+#define SYNTH_SYNTH5_CAPRANGE3_LSB 5
+#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0
+#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB)
+#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB)
+#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK)
+#define SYNTH_SYNTH5_SPARE_MSB 1
+#define SYNTH_SYNTH5_SPARE_LSB 0
+#define SYNTH_SYNTH5_SPARE_MASK 0x00000003
+#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB)
+#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK)
+
+#define SYNTH_SYNTH6_ADDRESS 0x00000014
+#define SYNTH_SYNTH6_OFFSET 0x00000014
+#define SYNTH_SYNTH6_IRCP_MSB 31
+#define SYNTH_SYNTH6_IRCP_LSB 29
+#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000
+#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB)
+#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK)
+#define SYNTH_SYNTH6_IRVCMON_MSB 28
+#define SYNTH_SYNTH6_IRVCMON_LSB 26
+#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000
+#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB)
+#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK)
+#define SYNTH_SYNTH6_IRSPARE_MSB 25
+#define SYNTH_SYNTH6_IRSPARE_LSB 23
+#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000
+#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB)
+#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK)
+#define SYNTH_SYNTH6_ICPRESC_MSB 22
+#define SYNTH_SYNTH6_ICPRESC_LSB 20
+#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000
+#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB)
+#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK)
+#define SYNTH_SYNTH6_ICLODIV_MSB 19
+#define SYNTH_SYNTH6_ICLODIV_LSB 17
+#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000
+#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB)
+#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK)
+#define SYNTH_SYNTH6_ICLOMIX_MSB 16
+#define SYNTH_SYNTH6_ICLOMIX_LSB 14
+#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000
+#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB)
+#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK)
+#define SYNTH_SYNTH6_ICSPAREA_MSB 13
+#define SYNTH_SYNTH6_ICSPAREA_LSB 11
+#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800
+#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB)
+#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK)
+#define SYNTH_SYNTH6_ICSPAREB_MSB 10
+#define SYNTH_SYNTH6_ICSPAREB_LSB 8
+#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700
+#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB)
+#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK)
+#define SYNTH_SYNTH6_ICVCO_MSB 7
+#define SYNTH_SYNTH6_ICVCO_LSB 5
+#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0
+#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB)
+#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK)
+#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4
+#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3
+#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018
+#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB)
+#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK)
+#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2
+#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0
+#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007
+#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB)
+#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK)
+
+#define SYNTH_SYNTH7_ADDRESS 0x00000018
+#define SYNTH_SYNTH7_OFFSET 0x00000018
+#define SYNTH_SYNTH7_SYNTH_ON_MSB 31
+#define SYNTH_SYNTH7_SYNTH_ON_LSB 31
+#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000
+#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB)
+#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB)
+#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK)
+#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26
+#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26
+#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000
+#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB)
+#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB)
+#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK)
+#define SYNTH_SYNTH7_PIN_VC_MSB 24
+#define SYNTH_SYNTH7_PIN_VC_LSB 24
+#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000
+#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB)
+#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK)
+#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23
+#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16
+#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000
+#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB)
+#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK)
+#define SYNTH_SYNTH7_SHORT_R_MSB 15
+#define SYNTH_SYNTH7_SHORT_R_LSB 15
+#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000
+#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB)
+#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK)
+#define SYNTH_SYNTH7_RESET_RFD_MSB 14
+#define SYNTH_SYNTH7_RESET_RFD_LSB 14
+#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000
+#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB)
+#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK)
+#define SYNTH_SYNTH7_RESET_PFD_MSB 13
+#define SYNTH_SYNTH7_RESET_PFD_LSB 13
+#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000
+#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB)
+#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB)
+#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK)
+#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11
+#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11
+#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800
+#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB)
+#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK)
+#define SYNTH_SYNTH7_VC2HIGH_MSB 10
+#define SYNTH_SYNTH7_VC2HIGH_LSB 10
+#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400
+#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB)
+#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK)
+#define SYNTH_SYNTH7_VC2LOW_MSB 9
+#define SYNTH_SYNTH7_VC2LOW_LSB 9
+#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200
+#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB)
+#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK)
+#define SYNTH_SYNTH7_LOOP_IP_MSB 8
+#define SYNTH_SYNTH7_LOOP_IP_LSB 5
+#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0
+#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB)
+#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4
+#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3
+#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018
+#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB)
+#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK)
+#define SYNTH_SYNTH7_SPARE_READ_MSB 2
+#define SYNTH_SYNTH7_SPARE_READ_LSB 0
+#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007
+#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB)
+#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK)
+
+#define SYNTH_SYNTH8_ADDRESS 0x0000001c
+#define SYNTH_SYNTH8_OFFSET 0x0000001c
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB)
+#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK)
+#define SYNTH_SYNTH8_FRACMODE_MSB 30
+#define SYNTH_SYNTH8_FRACMODE_LSB 30
+#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000
+#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB)
+#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK)
+#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29
+#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28
+#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000
+#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB)
+#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK)
+#define SYNTH_SYNTH8_SPARE_MSB 27
+#define SYNTH_SYNTH8_SPARE_LSB 27
+#define SYNTH_SYNTH8_SPARE_MASK 0x08000000
+#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB)
+#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK)
+#define SYNTH_SYNTH8_CHANSEL_MSB 26
+#define SYNTH_SYNTH8_CHANSEL_LSB 18
+#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000
+#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB)
+#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK)
+#define SYNTH_SYNTH8_CHANFRAC_MSB 17
+#define SYNTH_SYNTH8_CHANFRAC_LSB 1
+#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe
+#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB)
+#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0
+#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001
+#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB)
+#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK)
+
+#define RF5G_RF5G1_ADDRESS 0x00000020
+#define RF5G_RF5G1_OFFSET 0x00000020
+#define RF5G_RF5G1_PDTXLO5_MSB 31
+#define RF5G_RF5G1_PDTXLO5_LSB 31
+#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000
+#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB)
+#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK)
+#define RF5G_RF5G1_PDTXMIX5_MSB 30
+#define RF5G_RF5G1_PDTXMIX5_LSB 30
+#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000
+#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB)
+#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK)
+#define RF5G_RF5G1_PDTXBUF5_MSB 29
+#define RF5G_RF5G1_PDTXBUF5_LSB 29
+#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000
+#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB)
+#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK)
+#define RF5G_RF5G1_PDPADRV5_MSB 28
+#define RF5G_RF5G1_PDPADRV5_LSB 28
+#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000
+#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB)
+#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK)
+#define RF5G_RF5G1_PDPAOUT5_MSB 27
+#define RF5G_RF5G1_PDPAOUT5_LSB 27
+#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000
+#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB)
+#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK)
+#define RF5G_RF5G1_TUNE_PADRV5_MSB 26
+#define RF5G_RF5G1_TUNE_PADRV5_LSB 24
+#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000
+#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB)
+#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK)
+#define RF5G_RF5G1_PWDTXPKD_MSB 23
+#define RF5G_RF5G1_PWDTXPKD_LSB 21
+#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000
+#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB)
+#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK)
+#define RF5G_RF5G1_DB5_MSB 20
+#define RF5G_RF5G1_DB5_LSB 18
+#define RF5G_RF5G1_DB5_MASK 0x001c0000
+#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB)
+#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK)
+#define RF5G_RF5G1_OB5_MSB 17
+#define RF5G_RF5G1_OB5_LSB 15
+#define RF5G_RF5G1_OB5_MASK 0x00038000
+#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB)
+#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK)
+#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14
+#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12
+#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000
+#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB)
+#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK)
+#define RF5G_RF5G1_PDLO5DIV_MSB 11
+#define RF5G_RF5G1_PDLO5DIV_LSB 11
+#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800
+#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB)
+#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK)
+#define RF5G_RF5G1_PDLO5MIX_MSB 10
+#define RF5G_RF5G1_PDLO5MIX_LSB 10
+#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400
+#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB)
+#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK)
+#define RF5G_RF5G1_PDQBUF5_MSB 9
+#define RF5G_RF5G1_PDQBUF5_LSB 9
+#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200
+#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB)
+#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK)
+#define RF5G_RF5G1_PDLO5AGC_MSB 8
+#define RF5G_RF5G1_PDLO5AGC_LSB 8
+#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100
+#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB)
+#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK)
+#define RF5G_RF5G1_PDREGLO5_MSB 7
+#define RF5G_RF5G1_PDREGLO5_LSB 7
+#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080
+#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB)
+#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK)
+#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6
+#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4
+#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070
+#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB)
+#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK)
+#define RF5G_RF5G1_LO5CONTROL_MSB 3
+#define RF5G_RF5G1_LO5CONTROL_LSB 3
+#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008
+#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB)
+#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK)
+#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2
+#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2
+#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004
+#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB)
+#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK)
+#define RF5G_RF5G1_SPARE_MSB 1
+#define RF5G_RF5G1_SPARE_LSB 0
+#define RF5G_RF5G1_SPARE_MASK 0x00000003
+#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB)
+#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK)
+
+#define RF5G_RF5G2_ADDRESS 0x00000024
+#define RF5G_RF5G2_OFFSET 0x00000024
+#define RF5G_RF5G2_AGCLO_B_MSB 31
+#define RF5G_RF5G2_AGCLO_B_LSB 29
+#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000
+#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB)
+#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK)
+#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28
+#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26
+#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000
+#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB)
+#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK)
+#define RF5G_RF5G2_PDCMOSLO5_MSB 25
+#define RF5G_RF5G2_PDCMOSLO5_LSB 25
+#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000
+#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB)
+#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK)
+#define RF5G_RF5G2_PDVGM5_MSB 24
+#define RF5G_RF5G2_PDVGM5_LSB 24
+#define RF5G_RF5G2_PDVGM5_MASK 0x01000000
+#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB)
+#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK)
+#define RF5G_RF5G2_PDCSLNA5_MSB 23
+#define RF5G_RF5G2_PDCSLNA5_LSB 23
+#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000
+#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB)
+#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK)
+#define RF5G_RF5G2_PDRFVGA5_MSB 22
+#define RF5G_RF5G2_PDRFVGA5_LSB 22
+#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000
+#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB)
+#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK)
+#define RF5G_RF5G2_PDREGFE5_MSB 21
+#define RF5G_RF5G2_PDREGFE5_LSB 21
+#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000
+#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB)
+#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK)
+#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20
+#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18
+#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000
+#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB)
+#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK)
+#define RF5G_RF5G2_BRFVGA5_MSB 17
+#define RF5G_RF5G2_BRFVGA5_LSB 15
+#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000
+#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB)
+#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK)
+#define RF5G_RF5G2_BCSLNA5_MSB 14
+#define RF5G_RF5G2_BCSLNA5_LSB 12
+#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000
+#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB)
+#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK)
+#define RF5G_RF5G2_BVGM5_MSB 11
+#define RF5G_RF5G2_BVGM5_LSB 9
+#define RF5G_RF5G2_BVGM5_MASK 0x00000e00
+#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB)
+#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK)
+#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8
+#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8
+#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100
+#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB)
+#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK)
+#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7
+#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6
+#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0
+#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB)
+#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK)
+#define RF5G_RF5G2_ENABLE_PCA_MSB 5
+#define RF5G_RF5G2_ENABLE_PCA_LSB 5
+#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020
+#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB)
+#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK)
+#define RF5G_RF5G2_TUNE_LO_MSB 4
+#define RF5G_RF5G2_TUNE_LO_LSB 2
+#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c
+#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB)
+#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK)
+#define RF5G_RF5G2_SPARE_MSB 1
+#define RF5G_RF5G2_SPARE_LSB 0
+#define RF5G_RF5G2_SPARE_MASK 0x00000003
+#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB)
+#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK)
+
+#define RF2G_RF2G1_ADDRESS 0x00000028
+#define RF2G_RF2G1_OFFSET 0x00000028
+#define RF2G_RF2G1_BLNA1_MSB 31
+#define RF2G_RF2G1_BLNA1_LSB 29
+#define RF2G_RF2G1_BLNA1_MASK 0xe0000000
+#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB)
+#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK)
+#define RF2G_RF2G1_BLNA1F_MSB 28
+#define RF2G_RF2G1_BLNA1F_LSB 26
+#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000
+#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB)
+#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK)
+#define RF2G_RF2G1_BLNA1BUF_MSB 25
+#define RF2G_RF2G1_BLNA1BUF_LSB 23
+#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000
+#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB)
+#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK)
+#define RF2G_RF2G1_BLNA2_MSB 22
+#define RF2G_RF2G1_BLNA2_LSB 20
+#define RF2G_RF2G1_BLNA2_MASK 0x00700000
+#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB)
+#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK)
+#define RF2G_RF2G1_DB_MSB 19
+#define RF2G_RF2G1_DB_LSB 17
+#define RF2G_RF2G1_DB_MASK 0x000e0000
+#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB)
+#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK)
+#define RF2G_RF2G1_OB_MSB 16
+#define RF2G_RF2G1_OB_LSB 14
+#define RF2G_RF2G1_OB_MASK 0x0001c000
+#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB)
+#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK)
+#define RF2G_RF2G1_FE_ATB_SEL_MSB 13
+#define RF2G_RF2G1_FE_ATB_SEL_LSB 11
+#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800
+#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB)
+#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK)
+#define RF2G_RF2G1_RF_ATB_SEL_MSB 10
+#define RF2G_RF2G1_RF_ATB_SEL_LSB 8
+#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700
+#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB)
+#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK)
+#define RF2G_RF2G1_SELLNA_MSB 7
+#define RF2G_RF2G1_SELLNA_LSB 7
+#define RF2G_RF2G1_SELLNA_MASK 0x00000080
+#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB)
+#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK)
+#define RF2G_RF2G1_LOCONTROL_MSB 6
+#define RF2G_RF2G1_LOCONTROL_LSB 6
+#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040
+#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB)
+#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK)
+#define RF2G_RF2G1_SHORTLNA2_MSB 5
+#define RF2G_RF2G1_SHORTLNA2_LSB 5
+#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020
+#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB)
+#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK)
+#define RF2G_RF2G1_SPARE_MSB 4
+#define RF2G_RF2G1_SPARE_LSB 0
+#define RF2G_RF2G1_SPARE_MASK 0x0000001f
+#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB)
+#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK)
+
+#define RF2G_RF2G2_ADDRESS 0x0000002c
+#define RF2G_RF2G2_OFFSET 0x0000002c
+#define RF2G_RF2G2_PDCGLNA_MSB 31
+#define RF2G_RF2G2_PDCGLNA_LSB 31
+#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000
+#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB)
+#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK)
+#define RF2G_RF2G2_PDCGLNABUF_MSB 30
+#define RF2G_RF2G2_PDCGLNABUF_LSB 30
+#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000
+#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB)
+#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK)
+#define RF2G_RF2G2_PDCSLNA_MSB 29
+#define RF2G_RF2G2_PDCSLNA_LSB 29
+#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000
+#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB)
+#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK)
+#define RF2G_RF2G2_PDDIV_MSB 28
+#define RF2G_RF2G2_PDDIV_LSB 28
+#define RF2G_RF2G2_PDDIV_MASK 0x10000000
+#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB)
+#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK)
+#define RF2G_RF2G2_PDPADRV_MSB 27
+#define RF2G_RF2G2_PDPADRV_LSB 27
+#define RF2G_RF2G2_PDPADRV_MASK 0x08000000
+#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB)
+#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK)
+#define RF2G_RF2G2_PDPAOUT_MSB 26
+#define RF2G_RF2G2_PDPAOUT_LSB 26
+#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000
+#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB)
+#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK)
+#define RF2G_RF2G2_PDREGLNA_MSB 25
+#define RF2G_RF2G2_PDREGLNA_LSB 25
+#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000
+#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB)
+#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK)
+#define RF2G_RF2G2_PDREGLO_MSB 24
+#define RF2G_RF2G2_PDREGLO_LSB 24
+#define RF2G_RF2G2_PDREGLO_MASK 0x01000000
+#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB)
+#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK)
+#define RF2G_RF2G2_PDRFGM_MSB 23
+#define RF2G_RF2G2_PDRFGM_LSB 23
+#define RF2G_RF2G2_PDRFGM_MASK 0x00800000
+#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB)
+#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK)
+#define RF2G_RF2G2_PDRXLO_MSB 22
+#define RF2G_RF2G2_PDRXLO_LSB 22
+#define RF2G_RF2G2_PDRXLO_MASK 0x00400000
+#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB)
+#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK)
+#define RF2G_RF2G2_PDTXLO_MSB 21
+#define RF2G_RF2G2_PDTXLO_LSB 21
+#define RF2G_RF2G2_PDTXLO_MASK 0x00200000
+#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB)
+#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK)
+#define RF2G_RF2G2_PDTXMIX_MSB 20
+#define RF2G_RF2G2_PDTXMIX_LSB 20
+#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000
+#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB)
+#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK)
+#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19
+#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19
+#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000
+#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB)
+#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK)
+#define RF2G_RF2G2_REGLO_BYPASS_MSB 18
+#define RF2G_RF2G2_REGLO_BYPASS_LSB 18
+#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000
+#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB)
+#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK)
+#define RF2G_RF2G2_ENABLE_PCB_MSB 17
+#define RF2G_RF2G2_ENABLE_PCB_LSB 17
+#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000
+#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB)
+#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK)
+#define RF2G_RF2G2_SPARE_MSB 16
+#define RF2G_RF2G2_SPARE_LSB 0
+#define RF2G_RF2G2_SPARE_MASK 0x0001ffff
+#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB)
+#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK)
+
+#define TOP_GAIN_ADDRESS 0x00000030
+#define TOP_GAIN_OFFSET 0x00000030
+#define TOP_GAIN_TX6DBLOQGAIN_MSB 31
+#define TOP_GAIN_TX6DBLOQGAIN_LSB 30
+#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000
+#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB)
+#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK)
+#define TOP_GAIN_TX1DBLOQGAIN_MSB 29
+#define TOP_GAIN_TX1DBLOQGAIN_LSB 27
+#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000
+#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB)
+#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK)
+#define TOP_GAIN_TXV2IGAIN_MSB 26
+#define TOP_GAIN_TXV2IGAIN_LSB 25
+#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000
+#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB)
+#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK)
+#define TOP_GAIN_PABUF5GN_MSB 24
+#define TOP_GAIN_PABUF5GN_LSB 24
+#define TOP_GAIN_PABUF5GN_MASK 0x01000000
+#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB)
+#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK)
+#define TOP_GAIN_PADRVGN_MSB 23
+#define TOP_GAIN_PADRVGN_LSB 21
+#define TOP_GAIN_PADRVGN_MASK 0x00e00000
+#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB)
+#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK)
+#define TOP_GAIN_PAOUT2GN_MSB 20
+#define TOP_GAIN_PAOUT2GN_LSB 18
+#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000
+#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB)
+#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK)
+#define TOP_GAIN_LNAON_MSB 17
+#define TOP_GAIN_LNAON_LSB 17
+#define TOP_GAIN_LNAON_MASK 0x00020000
+#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB)
+#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK)
+#define TOP_GAIN_LNAGAIN_MSB 16
+#define TOP_GAIN_LNAGAIN_LSB 13
+#define TOP_GAIN_LNAGAIN_MASK 0x0001e000
+#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB)
+#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK)
+#define TOP_GAIN_RFVGA5GAIN_MSB 12
+#define TOP_GAIN_RFVGA5GAIN_LSB 11
+#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800
+#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB)
+#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK)
+#define TOP_GAIN_RFGMGN_MSB 10
+#define TOP_GAIN_RFGMGN_LSB 8
+#define TOP_GAIN_RFGMGN_MASK 0x00000700
+#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB)
+#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK)
+#define TOP_GAIN_RX6DBLOQGAIN_MSB 7
+#define TOP_GAIN_RX6DBLOQGAIN_LSB 6
+#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0
+#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB)
+#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK)
+#define TOP_GAIN_RX1DBLOQGAIN_MSB 5
+#define TOP_GAIN_RX1DBLOQGAIN_LSB 3
+#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038
+#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB)
+#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK)
+#define TOP_GAIN_RX6DBHIQGAIN_MSB 2
+#define TOP_GAIN_RX6DBHIQGAIN_LSB 1
+#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006
+#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB)
+#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK)
+#define TOP_GAIN_SPARE_MSB 0
+#define TOP_GAIN_SPARE_LSB 0
+#define TOP_GAIN_SPARE_MASK 0x00000001
+#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB)
+#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK)
+
+#define TOP_TOP_ADDRESS 0x00000034
+#define TOP_TOP_OFFSET 0x00000034
+#define TOP_TOP_LOCALTXGAIN_MSB 31
+#define TOP_TOP_LOCALTXGAIN_LSB 31
+#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000
+#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB)
+#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK)
+#define TOP_TOP_LOCALRXGAIN_MSB 30
+#define TOP_TOP_LOCALRXGAIN_LSB 30
+#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000
+#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB)
+#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK)
+#define TOP_TOP_LOCALMODE_MSB 29
+#define TOP_TOP_LOCALMODE_LSB 29
+#define TOP_TOP_LOCALMODE_MASK 0x20000000
+#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB)
+#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK)
+#define TOP_TOP_CALFC_MSB 28
+#define TOP_TOP_CALFC_LSB 28
+#define TOP_TOP_CALFC_MASK 0x10000000
+#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB)
+#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK)
+#define TOP_TOP_CALDC_MSB 27
+#define TOP_TOP_CALDC_LSB 27
+#define TOP_TOP_CALDC_MASK 0x08000000
+#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB)
+#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK)
+#define TOP_TOP_CAL_RESIDUE_MSB 26
+#define TOP_TOP_CAL_RESIDUE_LSB 26
+#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000
+#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB)
+#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK)
+#define TOP_TOP_BMODE_MSB 25
+#define TOP_TOP_BMODE_LSB 25
+#define TOP_TOP_BMODE_MASK 0x02000000
+#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB)
+#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK)
+#define TOP_TOP_SYNTHON_MSB 24
+#define TOP_TOP_SYNTHON_LSB 24
+#define TOP_TOP_SYNTHON_MASK 0x01000000
+#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB)
+#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK)
+#define TOP_TOP_RXON_MSB 23
+#define TOP_TOP_RXON_LSB 23
+#define TOP_TOP_RXON_MASK 0x00800000
+#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB)
+#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK)
+#define TOP_TOP_TXON_MSB 22
+#define TOP_TOP_TXON_LSB 22
+#define TOP_TOP_TXON_MASK 0x00400000
+#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB)
+#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK)
+#define TOP_TOP_PAON_MSB 21
+#define TOP_TOP_PAON_LSB 21
+#define TOP_TOP_PAON_MASK 0x00200000
+#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB)
+#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK)
+#define TOP_TOP_CALTX_MSB 20
+#define TOP_TOP_CALTX_LSB 20
+#define TOP_TOP_CALTX_MASK 0x00100000
+#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB)
+#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK)
+#define TOP_TOP_LOCALADDAC_MSB 19
+#define TOP_TOP_LOCALADDAC_LSB 19
+#define TOP_TOP_LOCALADDAC_MASK 0x00080000
+#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB)
+#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK)
+#define TOP_TOP_PWDPLL_MSB 18
+#define TOP_TOP_PWDPLL_LSB 18
+#define TOP_TOP_PWDPLL_MASK 0x00040000
+#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB)
+#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK)
+#define TOP_TOP_PWDADC_MSB 17
+#define TOP_TOP_PWDADC_LSB 17
+#define TOP_TOP_PWDADC_MASK 0x00020000
+#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB)
+#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK)
+#define TOP_TOP_PWDDAC_MSB 16
+#define TOP_TOP_PWDDAC_LSB 16
+#define TOP_TOP_PWDDAC_MASK 0x00010000
+#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB)
+#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK)
+#define TOP_TOP_LOCALXTAL_MSB 15
+#define TOP_TOP_LOCALXTAL_LSB 15
+#define TOP_TOP_LOCALXTAL_MASK 0x00008000
+#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB)
+#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK)
+#define TOP_TOP_PWDCLKIN_MSB 14
+#define TOP_TOP_PWDCLKIN_LSB 14
+#define TOP_TOP_PWDCLKIN_MASK 0x00004000
+#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB)
+#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK)
+#define TOP_TOP_OSCON_MSB 13
+#define TOP_TOP_OSCON_LSB 13
+#define TOP_TOP_OSCON_MASK 0x00002000
+#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB)
+#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK)
+#define TOP_TOP_SCLKEN_FORCE_MSB 12
+#define TOP_TOP_SCLKEN_FORCE_LSB 12
+#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000
+#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB)
+#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK)
+#define TOP_TOP_SYNTHON_FORCE_MSB 11
+#define TOP_TOP_SYNTHON_FORCE_LSB 11
+#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800
+#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB)
+#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK)
+#define TOP_TOP_PDBIAS_MSB 10
+#define TOP_TOP_PDBIAS_LSB 10
+#define TOP_TOP_PDBIAS_MASK 0x00000400
+#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB)
+#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK)
+#define TOP_TOP_DATAOUTSEL_MSB 9
+#define TOP_TOP_DATAOUTSEL_LSB 8
+#define TOP_TOP_DATAOUTSEL_MASK 0x00000300
+#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB)
+#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK)
+#define TOP_TOP_REVID_MSB 7
+#define TOP_TOP_REVID_LSB 5
+#define TOP_TOP_REVID_MASK 0x000000e0
+#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB)
+#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK)
+#define TOP_TOP_INT2PAD_MSB 4
+#define TOP_TOP_INT2PAD_LSB 4
+#define TOP_TOP_INT2PAD_MASK 0x00000010
+#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB)
+#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK)
+#define TOP_TOP_INTH2PAD_MSB 3
+#define TOP_TOP_INTH2PAD_LSB 3
+#define TOP_TOP_INTH2PAD_MASK 0x00000008
+#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB)
+#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK)
+#define TOP_TOP_PAD2GND_MSB 2
+#define TOP_TOP_PAD2GND_LSB 2
+#define TOP_TOP_PAD2GND_MASK 0x00000004
+#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB)
+#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK)
+#define TOP_TOP_INT2GND_MSB 1
+#define TOP_TOP_INT2GND_LSB 1
+#define TOP_TOP_INT2GND_MASK 0x00000002
+#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB)
+#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK)
+#define TOP_TOP_FORCE_XPAON_MSB 0
+#define TOP_TOP_FORCE_XPAON_LSB 0
+#define TOP_TOP_FORCE_XPAON_MASK 0x00000001
+#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB)
+#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK)
+
+#define BIAS_BIAS_SEL_ADDRESS 0x00000038
+#define BIAS_BIAS_SEL_OFFSET 0x00000038
+#define BIAS_BIAS_SEL_PADON_MSB 31
+#define BIAS_BIAS_SEL_PADON_LSB 31
+#define BIAS_BIAS_SEL_PADON_MASK 0x80000000
+#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB)
+#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK)
+#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30
+#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25
+#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000
+#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB)
+#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK)
+#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24
+#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21
+#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000
+#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_SPARE_MSB 20
+#define BIAS_BIAS_SEL_SPARE_LSB 20
+#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000
+#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB)
+#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB)
+#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0
+#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001
+#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB)
+#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK)
+
+#define BIAS_BIAS1_ADDRESS 0x0000003c
+#define BIAS_BIAS1_OFFSET 0x0000003c
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31
+#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29
+#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000
+#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB)
+#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK)
+#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28
+#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26
+#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000
+#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB)
+#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25
+#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23
+#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000
+#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB)
+#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22
+#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20
+#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000
+#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB)
+#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16
+#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000
+#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15
+#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000
+#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB)
+#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14
+#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000
+#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13
+#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11
+#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800
+#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB)
+#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK)
+#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7
+#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5
+#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0
+#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB)
+#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB)
+#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK)
+#define BIAS_BIAS1_SPARE_MSB 1
+#define BIAS_BIAS1_SPARE_LSB 0
+#define BIAS_BIAS1_SPARE_MASK 0x00000003
+#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB)
+#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK)
+
+#define BIAS_BIAS2_ADDRESS 0x00000040
+#define BIAS_BIAS2_OFFSET 0x00000040
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31
+#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29
+#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000
+#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB)
+#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK)
+#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28
+#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26
+#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000
+#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB)
+#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25
+#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23
+#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000
+#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IRPLL25_MSB 22
+#define BIAS_BIAS2_PWD_IRPLL25_LSB 22
+#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000
+#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB)
+#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK)
+#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21
+#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19
+#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000
+#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB)
+#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK)
+#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18
+#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16
+#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000
+#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB)
+#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK)
+#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15
+#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13
+#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000
+#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB)
+#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK)
+#define BIAS_BIAS2_PWD_IRLDO25_MSB 12
+#define BIAS_BIAS2_PWD_IRLDO25_LSB 12
+#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000
+#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB)
+#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB)
+#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8
+#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6
+#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0
+#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB)
+#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB)
+#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK)
+
+#define BIAS_BIAS3_ADDRESS 0x00000044
+#define BIAS_BIAS3_OFFSET 0x00000044
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB)
+#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK)
+#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28
+#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26
+#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000
+#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB)
+#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK)
+#define BIAS_BIAS3_PWD_ICDAC50_MSB 25
+#define BIAS_BIAS3_PWD_ICDAC50_LSB 23
+#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000
+#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB)
+#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK)
+#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22
+#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22
+#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000
+#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_ICBB50_MSB 21
+#define BIAS_BIAS3_PWD_ICBB50_LSB 21
+#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000
+#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB)
+#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK)
+#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20
+#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18
+#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000
+#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB)
+#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK)
+#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17
+#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17
+#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000
+#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB)
+#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK)
+#define BIAS_BIAS3_PWD_IRBB50_MSB 16
+#define BIAS_BIAS3_PWD_IRBB50_LSB 16
+#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000
+#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB)
+#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15
+#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13
+#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000
+#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12
+#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10
+#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00
+#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9
+#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7
+#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380
+#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK)
+#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6
+#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4
+#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070
+#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB)
+#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3
+#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1
+#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e
+#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB)
+#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK)
+#define BIAS_BIAS3_SPARE_MSB 0
+#define BIAS_BIAS3_SPARE_LSB 0
+#define BIAS_BIAS3_SPARE_MASK 0x00000001
+#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB)
+#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK)
+
+#define TXPC_TXPC_ADDRESS 0x00000048
+#define TXPC_TXPC_OFFSET 0x00000048
+#define TXPC_TXPC_SELINTPD_MSB 31
+#define TXPC_TXPC_SELINTPD_LSB 31
+#define TXPC_TXPC_SELINTPD_MASK 0x80000000
+#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB)
+#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK)
+#define TXPC_TXPC_TEST_MSB 30
+#define TXPC_TXPC_TEST_LSB 30
+#define TXPC_TXPC_TEST_MASK 0x40000000
+#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB)
+#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK)
+#define TXPC_TXPC_TESTGAIN_MSB 29
+#define TXPC_TXPC_TESTGAIN_LSB 28
+#define TXPC_TXPC_TESTGAIN_MASK 0x30000000
+#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB)
+#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK)
+#define TXPC_TXPC_TESTDAC_MSB 27
+#define TXPC_TXPC_TESTDAC_LSB 22
+#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000
+#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB)
+#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK)
+#define TXPC_TXPC_TESTPWDPC_MSB 21
+#define TXPC_TXPC_TESTPWDPC_LSB 21
+#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000
+#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB)
+#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK)
+#define TXPC_TXPC_CURHALF_MSB 20
+#define TXPC_TXPC_CURHALF_LSB 20
+#define TXPC_TXPC_CURHALF_MASK 0x00100000
+#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB)
+#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK)
+#define TXPC_TXPC_NEGOUT_MSB 19
+#define TXPC_TXPC_NEGOUT_LSB 19
+#define TXPC_TXPC_NEGOUT_MASK 0x00080000
+#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB)
+#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK)
+#define TXPC_TXPC_CLKDELAY_MSB 18
+#define TXPC_TXPC_CLKDELAY_LSB 18
+#define TXPC_TXPC_CLKDELAY_MASK 0x00040000
+#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB)
+#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK)
+#define TXPC_TXPC_SELMODREF_MSB 17
+#define TXPC_TXPC_SELMODREF_LSB 17
+#define TXPC_TXPC_SELMODREF_MASK 0x00020000
+#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB)
+#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK)
+#define TXPC_TXPC_SELCMOUT_MSB 16
+#define TXPC_TXPC_SELCMOUT_LSB 16
+#define TXPC_TXPC_SELCMOUT_MASK 0x00010000
+#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB)
+#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK)
+#define TXPC_TXPC_TSMODE_MSB 15
+#define TXPC_TXPC_TSMODE_LSB 14
+#define TXPC_TXPC_TSMODE_MASK 0x0000c000
+#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB)
+#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK)
+#define TXPC_TXPC_N_MSB 13
+#define TXPC_TXPC_N_LSB 6
+#define TXPC_TXPC_N_MASK 0x00003fc0
+#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB)
+#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK)
+#define TXPC_TXPC_ON1STSYNTHON_MSB 5
+#define TXPC_TXPC_ON1STSYNTHON_LSB 5
+#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020
+#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB)
+#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK)
+#define TXPC_TXPC_SELINIT_MSB 4
+#define TXPC_TXPC_SELINIT_LSB 3
+#define TXPC_TXPC_SELINIT_MASK 0x00000018
+#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB)
+#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK)
+#define TXPC_TXPC_SELCOUNT_MSB 2
+#define TXPC_TXPC_SELCOUNT_LSB 2
+#define TXPC_TXPC_SELCOUNT_MASK 0x00000004
+#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB)
+#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK)
+#define TXPC_TXPC_ATBSEL_MSB 1
+#define TXPC_TXPC_ATBSEL_LSB 0
+#define TXPC_TXPC_ATBSEL_MASK 0x00000003
+#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB)
+#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK)
+
+#define TXPC_MISC_ADDRESS 0x0000004c
+#define TXPC_MISC_OFFSET 0x0000004c
+#define TXPC_MISC_FLIPBMODE_MSB 31
+#define TXPC_MISC_FLIPBMODE_LSB 31
+#define TXPC_MISC_FLIPBMODE_MASK 0x80000000
+#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB)
+#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK)
+#define TXPC_MISC_LEVEL_MSB 30
+#define TXPC_MISC_LEVEL_LSB 29
+#define TXPC_MISC_LEVEL_MASK 0x60000000
+#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB)
+#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK)
+#define TXPC_MISC_LDO_TEST_MODE_MSB 28
+#define TXPC_MISC_LDO_TEST_MODE_LSB 28
+#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000
+#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB)
+#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK)
+#define TXPC_MISC_NOTCXODET_MSB 27
+#define TXPC_MISC_NOTCXODET_LSB 27
+#define TXPC_MISC_NOTCXODET_MASK 0x08000000
+#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB)
+#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK)
+#define TXPC_MISC_PWDCLKIND_MSB 26
+#define TXPC_MISC_PWDCLKIND_LSB 26
+#define TXPC_MISC_PWDCLKIND_MASK 0x04000000
+#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB)
+#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK)
+#define TXPC_MISC_PWDXINPAD_MSB 25
+#define TXPC_MISC_PWDXINPAD_LSB 25
+#define TXPC_MISC_PWDXINPAD_MASK 0x02000000
+#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB)
+#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK)
+#define TXPC_MISC_LOCALBIAS_MSB 24
+#define TXPC_MISC_LOCALBIAS_LSB 24
+#define TXPC_MISC_LOCALBIAS_MASK 0x01000000
+#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB)
+#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK)
+#define TXPC_MISC_LOCALBIAS2X_MSB 23
+#define TXPC_MISC_LOCALBIAS2X_LSB 23
+#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000
+#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB)
+#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK)
+#define TXPC_MISC_SELTSP_MSB 22
+#define TXPC_MISC_SELTSP_LSB 22
+#define TXPC_MISC_SELTSP_MASK 0x00400000
+#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB)
+#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK)
+#define TXPC_MISC_SELTSN_MSB 21
+#define TXPC_MISC_SELTSN_LSB 21
+#define TXPC_MISC_SELTSN_MASK 0x00200000
+#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB)
+#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK)
+#define TXPC_MISC_SPARE_A_MSB 20
+#define TXPC_MISC_SPARE_A_LSB 18
+#define TXPC_MISC_SPARE_A_MASK 0x001c0000
+#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB)
+#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK)
+#define TXPC_MISC_DECOUT_MSB 17
+#define TXPC_MISC_DECOUT_LSB 8
+#define TXPC_MISC_DECOUT_MASK 0x0003ff00
+#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB)
+#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK)
+#define TXPC_MISC_XTALDIV_MSB 7
+#define TXPC_MISC_XTALDIV_LSB 6
+#define TXPC_MISC_XTALDIV_MASK 0x000000c0
+#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB)
+#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK)
+#define TXPC_MISC_SPARE_MSB 5
+#define TXPC_MISC_SPARE_LSB 0
+#define TXPC_MISC_SPARE_MASK 0x0000003f
+#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB)
+#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK)
+
+#define RXTXBB_RXTXBB1_ADDRESS 0x00000050
+#define RXTXBB_RXTXBB1_OFFSET 0x00000050
+#define RXTXBB_RXTXBB1_SPARE_MSB 31
+#define RXTXBB_RXTXBB1_SPARE_LSB 19
+#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000
+#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB)
+#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK)
+#define RXTXBB_RXTXBB1_FNOTCH_MSB 18
+#define RXTXBB_RXTXBB1_FNOTCH_LSB 17
+#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000
+#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB)
+#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK)
+#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16
+#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9
+#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00
+#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB)
+#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB)
+#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK)
+#define RXTXBB_RXTXBB1_PDV2I_MSB 7
+#define RXTXBB_RXTXBB1_PDV2I_LSB 7
+#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080
+#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB)
+#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK)
+#define RXTXBB_RXTXBB1_PDI2V_MSB 6
+#define RXTXBB_RXTXBB1_PDI2V_LSB 6
+#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040
+#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB)
+#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK)
+#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5
+#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5
+#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020
+#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB)
+#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB)
+#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK)
+#define RXTXBB_RXTXBB1_PDLOQ_MSB 1
+#define RXTXBB_RXTXBB1_PDLOQ_LSB 1
+#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002
+#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB)
+#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK)
+#define RXTXBB_RXTXBB1_PDHIQ_MSB 0
+#define RXTXBB_RXTXBB1_PDHIQ_LSB 0
+#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001
+#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB)
+#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK)
+
+#define RXTXBB_RXTXBB2_ADDRESS 0x00000054
+#define RXTXBB_RXTXBB2_OFFSET 0x00000054
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB)
+#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK)
+#define RXTXBB_RXTXBB2_SPARE_MSB 22
+#define RXTXBB_RXTXBB2_SPARE_LSB 21
+#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000
+#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB)
+#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20
+#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000
+#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19
+#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19
+#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000
+#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB)
+#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB)
+#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK)
+#define RXTXBB_RXTXBB2_CMSEL_MSB 14
+#define RXTXBB_RXTXBB2_CMSEL_LSB 13
+#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000
+#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB)
+#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK)
+#define RXTXBB_RXTXBB2_FILTERFC_MSB 12
+#define RXTXBB_RXTXBB2_FILTERFC_LSB 8
+#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00
+#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB)
+#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB)
+#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB)
+#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB)
+#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB)
+#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK)
+
+#define RXTXBB_RXTXBB3_ADDRESS 0x00000058
+#define RXTXBB_RXTXBB3_OFFSET 0x00000058
+#define RXTXBB_RXTXBB3_SPARE_MSB 31
+#define RXTXBB_RXTXBB3_SPARE_LSB 27
+#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000
+#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB)
+#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB)
+#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK)
+
+#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c
+#define RXTXBB_RXTXBB4_OFFSET 0x0000005c
+#define RXTXBB_RXTXBB4_SPARE_MSB 31
+#define RXTXBB_RXTXBB4_SPARE_LSB 31
+#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000
+#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB)
+#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30
+#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000
+#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB)
+#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29
+#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25
+#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000
+#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB)
+#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK)
+
+#define ADDAC_ADDAC1_ADDRESS 0x00000060
+#define ADDAC_ADDAC1_OFFSET 0x00000060
+#define ADDAC_ADDAC1_PLL_SVREG_MSB 31
+#define ADDAC_ADDAC1_PLL_SVREG_LSB 31
+#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000
+#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB)
+#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK)
+#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30
+#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28
+#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000
+#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB)
+#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK)
+#define ADDAC_ADDAC1_PLL_ATB_MSB 27
+#define ADDAC_ADDAC1_PLL_ATB_LSB 26
+#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000
+#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB)
+#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK)
+#define ADDAC_ADDAC1_PLL_ICP_MSB 25
+#define ADDAC_ADDAC1_PLL_ICP_LSB 23
+#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000
+#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB)
+#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK)
+#define ADDAC_ADDAC1_PLL_FILTER_MSB 22
+#define ADDAC_ADDAC1_PLL_FILTER_LSB 15
+#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000
+#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB)
+#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK)
+#define ADDAC_ADDAC1_PWDPLL_MSB 14
+#define ADDAC_ADDAC1_PWDPLL_LSB 14
+#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000
+#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB)
+#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK)
+#define ADDAC_ADDAC1_PWDADC_MSB 13
+#define ADDAC_ADDAC1_PWDADC_LSB 13
+#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000
+#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB)
+#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK)
+#define ADDAC_ADDAC1_PWDDAC_MSB 12
+#define ADDAC_ADDAC1_PWDDAC_LSB 12
+#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000
+#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB)
+#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK)
+#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11
+#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11
+#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800
+#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB)
+#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK)
+#define ADDAC_ADDAC1_SELMANPWDS_MSB 10
+#define ADDAC_ADDAC1_SELMANPWDS_LSB 10
+#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400
+#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB)
+#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9
+#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200
+#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB)
+#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK)
+#define ADDAC_ADDAC1_CM_SEL_MSB 8
+#define ADDAC_ADDAC1_CM_SEL_LSB 7
+#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180
+#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB)
+#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB)
+#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK)
+#define ADDAC_ADDAC1_SPARE_MSB 5
+#define ADDAC_ADDAC1_SPARE_LSB 0
+#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f
+#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB)
+#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_reg_reg_s {
+ volatile unsigned int synth_synth1;
+ volatile unsigned int synth_synth2;
+ volatile unsigned int synth_synth3;
+ volatile unsigned int synth_synth4;
+ volatile unsigned int synth_synth5;
+ volatile unsigned int synth_synth6;
+ volatile unsigned int synth_synth7;
+ volatile unsigned int synth_synth8;
+ volatile unsigned int rf5g_rf5g1;
+ volatile unsigned int rf5g_rf5g2;
+ volatile unsigned int rf2g_rf2g1;
+ volatile unsigned int rf2g_rf2g2;
+ volatile unsigned int top_gain;
+ volatile unsigned int top_top;
+ volatile unsigned int bias_bias_sel;
+ volatile unsigned int bias_bias1;
+ volatile unsigned int bias_bias2;
+ volatile unsigned int bias_bias3;
+ volatile unsigned int txpc_txpc;
+ volatile unsigned int txpc_misc;
+ volatile unsigned int rxtxbb_rxtxbb1;
+ volatile unsigned int rxtxbb_rxtxbb2;
+ volatile unsigned int rxtxbb_rxtxbb3;
+ volatile unsigned int rxtxbb_rxtxbb4;
+ volatile unsigned int addac_addac1;
+} analog_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h
new file mode 100644
index 000000000000..bba885ed1f08
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h
@@ -0,0 +1,32 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_MAP_H_
+#define _APB_MAP_H_
+
+#define RTC_BASE_ADDRESS 0x00004000
+#define VMC_BASE_ADDRESS 0x00008000
+#define UART_BASE_ADDRESS 0x0000c000
+#define SI_BASE_ADDRESS 0x00010000
+#define GPIO_BASE_ADDRESS 0x00014000
+#define MBOX_BASE_ADDRESS 0x00018000
+#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
+#define MAC_BASE_ADDRESS 0x00020000
+
+#endif /* _APB_MAP_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h
new file mode 100644
index 000000000000..de88e8cc91bb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h
@@ -0,0 +1,996 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_REG_REG_H_
+#define _GPIO_REG_REG_H_
+
+#define GPIO_OUT_ADDRESS 0x00000000
+#define GPIO_OUT_OFFSET 0x00000000
+#define GPIO_OUT_DATA_MSB 17
+#define GPIO_OUT_DATA_LSB 0
+#define GPIO_OUT_DATA_MASK 0x0003ffff
+#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
+#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
+
+#define GPIO_OUT_W1TS_ADDRESS 0x00000004
+#define GPIO_OUT_W1TS_OFFSET 0x00000004
+#define GPIO_OUT_W1TS_DATA_MSB 17
+#define GPIO_OUT_W1TS_DATA_LSB 0
+#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff
+#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
+#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
+
+#define GPIO_OUT_W1TC_ADDRESS 0x00000008
+#define GPIO_OUT_W1TC_OFFSET 0x00000008
+#define GPIO_OUT_W1TC_DATA_MSB 17
+#define GPIO_OUT_W1TC_DATA_LSB 0
+#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff
+#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
+#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
+
+#define GPIO_ENABLE_ADDRESS 0x0000000c
+#define GPIO_ENABLE_OFFSET 0x0000000c
+#define GPIO_ENABLE_DATA_MSB 17
+#define GPIO_ENABLE_DATA_LSB 0
+#define GPIO_ENABLE_DATA_MASK 0x0003ffff
+#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
+#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
+
+#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010
+#define GPIO_ENABLE_W1TS_OFFSET 0x00000010
+#define GPIO_ENABLE_W1TS_DATA_MSB 17
+#define GPIO_ENABLE_W1TS_DATA_LSB 0
+#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff
+#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
+#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014
+#define GPIO_ENABLE_W1TC_OFFSET 0x00000014
+#define GPIO_ENABLE_W1TC_DATA_MSB 17
+#define GPIO_ENABLE_W1TC_DATA_LSB 0
+#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff
+#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
+#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define GPIO_IN_ADDRESS 0x00000018
+#define GPIO_IN_OFFSET 0x00000018
+#define GPIO_IN_DATA_MSB 17
+#define GPIO_IN_DATA_LSB 0
+#define GPIO_IN_DATA_MASK 0x0003ffff
+#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
+#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
+
+#define GPIO_STATUS_ADDRESS 0x0000001c
+#define GPIO_STATUS_OFFSET 0x0000001c
+#define GPIO_STATUS_INTERRUPT_MSB 17
+#define GPIO_STATUS_INTERRUPT_LSB 0
+#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff
+#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
+#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TS_ADDRESS 0x00000020
+#define GPIO_STATUS_W1TS_OFFSET 0x00000020
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define GPIO_STATUS_W1TC_ADDRESS 0x00000024
+#define GPIO_STATUS_W1TC_OFFSET 0x00000024
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define GPIO_PIN0_ADDRESS 0x00000028
+#define GPIO_PIN0_OFFSET 0x00000028
+#define GPIO_PIN0_CONFIG_MSB 12
+#define GPIO_PIN0_CONFIG_LSB 11
+#define GPIO_PIN0_CONFIG_MASK 0x00001800
+#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
+#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN0_INT_TYPE_MSB 9
+#define GPIO_PIN0_INT_TYPE_LSB 7
+#define GPIO_PIN0_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
+#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
+#define GPIO_PIN0_PAD_DRIVER_MSB 2
+#define GPIO_PIN0_PAD_DRIVER_LSB 2
+#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
+#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
+#define GPIO_PIN0_SOURCE_MSB 0
+#define GPIO_PIN0_SOURCE_LSB 0
+#define GPIO_PIN0_SOURCE_MASK 0x00000001
+#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
+#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
+
+#define GPIO_PIN1_ADDRESS 0x0000002c
+#define GPIO_PIN1_OFFSET 0x0000002c
+#define GPIO_PIN1_CONFIG_MSB 12
+#define GPIO_PIN1_CONFIG_LSB 11
+#define GPIO_PIN1_CONFIG_MASK 0x00001800
+#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
+#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN1_INT_TYPE_MSB 9
+#define GPIO_PIN1_INT_TYPE_LSB 7
+#define GPIO_PIN1_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
+#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
+#define GPIO_PIN1_PAD_DRIVER_MSB 2
+#define GPIO_PIN1_PAD_DRIVER_LSB 2
+#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
+#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
+#define GPIO_PIN1_SOURCE_MSB 0
+#define GPIO_PIN1_SOURCE_LSB 0
+#define GPIO_PIN1_SOURCE_MASK 0x00000001
+#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
+#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
+
+#define GPIO_PIN2_ADDRESS 0x00000030
+#define GPIO_PIN2_OFFSET 0x00000030
+#define GPIO_PIN2_CONFIG_MSB 12
+#define GPIO_PIN2_CONFIG_LSB 11
+#define GPIO_PIN2_CONFIG_MASK 0x00001800
+#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
+#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN2_INT_TYPE_MSB 9
+#define GPIO_PIN2_INT_TYPE_LSB 7
+#define GPIO_PIN2_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
+#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
+#define GPIO_PIN2_PAD_DRIVER_MSB 2
+#define GPIO_PIN2_PAD_DRIVER_LSB 2
+#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
+#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
+#define GPIO_PIN2_SOURCE_MSB 0
+#define GPIO_PIN2_SOURCE_LSB 0
+#define GPIO_PIN2_SOURCE_MASK 0x00000001
+#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
+#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
+
+#define GPIO_PIN3_ADDRESS 0x00000034
+#define GPIO_PIN3_OFFSET 0x00000034
+#define GPIO_PIN3_CONFIG_MSB 12
+#define GPIO_PIN3_CONFIG_LSB 11
+#define GPIO_PIN3_CONFIG_MASK 0x00001800
+#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
+#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN3_INT_TYPE_MSB 9
+#define GPIO_PIN3_INT_TYPE_LSB 7
+#define GPIO_PIN3_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
+#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
+#define GPIO_PIN3_PAD_DRIVER_MSB 2
+#define GPIO_PIN3_PAD_DRIVER_LSB 2
+#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
+#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
+#define GPIO_PIN3_SOURCE_MSB 0
+#define GPIO_PIN3_SOURCE_LSB 0
+#define GPIO_PIN3_SOURCE_MASK 0x00000001
+#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
+#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
+
+#define GPIO_PIN4_ADDRESS 0x00000038
+#define GPIO_PIN4_OFFSET 0x00000038
+#define GPIO_PIN4_CONFIG_MSB 12
+#define GPIO_PIN4_CONFIG_LSB 11
+#define GPIO_PIN4_CONFIG_MASK 0x00001800
+#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
+#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN4_INT_TYPE_MSB 9
+#define GPIO_PIN4_INT_TYPE_LSB 7
+#define GPIO_PIN4_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
+#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
+#define GPIO_PIN4_PAD_DRIVER_MSB 2
+#define GPIO_PIN4_PAD_DRIVER_LSB 2
+#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
+#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
+#define GPIO_PIN4_SOURCE_MSB 0
+#define GPIO_PIN4_SOURCE_LSB 0
+#define GPIO_PIN4_SOURCE_MASK 0x00000001
+#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
+#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
+
+#define GPIO_PIN5_ADDRESS 0x0000003c
+#define GPIO_PIN5_OFFSET 0x0000003c
+#define GPIO_PIN5_CONFIG_MSB 12
+#define GPIO_PIN5_CONFIG_LSB 11
+#define GPIO_PIN5_CONFIG_MASK 0x00001800
+#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
+#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN5_INT_TYPE_MSB 9
+#define GPIO_PIN5_INT_TYPE_LSB 7
+#define GPIO_PIN5_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
+#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
+#define GPIO_PIN5_PAD_DRIVER_MSB 2
+#define GPIO_PIN5_PAD_DRIVER_LSB 2
+#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
+#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
+#define GPIO_PIN5_SOURCE_MSB 0
+#define GPIO_PIN5_SOURCE_LSB 0
+#define GPIO_PIN5_SOURCE_MASK 0x00000001
+#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
+#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
+
+#define GPIO_PIN6_ADDRESS 0x00000040
+#define GPIO_PIN6_OFFSET 0x00000040
+#define GPIO_PIN6_CONFIG_MSB 12
+#define GPIO_PIN6_CONFIG_LSB 11
+#define GPIO_PIN6_CONFIG_MASK 0x00001800
+#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
+#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN6_INT_TYPE_MSB 9
+#define GPIO_PIN6_INT_TYPE_LSB 7
+#define GPIO_PIN6_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
+#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
+#define GPIO_PIN6_PAD_DRIVER_MSB 2
+#define GPIO_PIN6_PAD_DRIVER_LSB 2
+#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
+#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
+#define GPIO_PIN6_SOURCE_MSB 0
+#define GPIO_PIN6_SOURCE_LSB 0
+#define GPIO_PIN6_SOURCE_MASK 0x00000001
+#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
+#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
+
+#define GPIO_PIN7_ADDRESS 0x00000044
+#define GPIO_PIN7_OFFSET 0x00000044
+#define GPIO_PIN7_CONFIG_MSB 12
+#define GPIO_PIN7_CONFIG_LSB 11
+#define GPIO_PIN7_CONFIG_MASK 0x00001800
+#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
+#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN7_INT_TYPE_MSB 9
+#define GPIO_PIN7_INT_TYPE_LSB 7
+#define GPIO_PIN7_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
+#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
+#define GPIO_PIN7_PAD_DRIVER_MSB 2
+#define GPIO_PIN7_PAD_DRIVER_LSB 2
+#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
+#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
+#define GPIO_PIN7_SOURCE_MSB 0
+#define GPIO_PIN7_SOURCE_LSB 0
+#define GPIO_PIN7_SOURCE_MASK 0x00000001
+#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
+#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
+
+#define GPIO_PIN8_ADDRESS 0x00000048
+#define GPIO_PIN8_OFFSET 0x00000048
+#define GPIO_PIN8_CONFIG_MSB 12
+#define GPIO_PIN8_CONFIG_LSB 11
+#define GPIO_PIN8_CONFIG_MASK 0x00001800
+#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
+#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN8_INT_TYPE_MSB 9
+#define GPIO_PIN8_INT_TYPE_LSB 7
+#define GPIO_PIN8_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
+#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
+#define GPIO_PIN8_PAD_DRIVER_MSB 2
+#define GPIO_PIN8_PAD_DRIVER_LSB 2
+#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
+#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
+#define GPIO_PIN8_SOURCE_MSB 0
+#define GPIO_PIN8_SOURCE_LSB 0
+#define GPIO_PIN8_SOURCE_MASK 0x00000001
+#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
+#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
+
+#define GPIO_PIN9_ADDRESS 0x0000004c
+#define GPIO_PIN9_OFFSET 0x0000004c
+#define GPIO_PIN9_CONFIG_MSB 12
+#define GPIO_PIN9_CONFIG_LSB 11
+#define GPIO_PIN9_CONFIG_MASK 0x00001800
+#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
+#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN9_INT_TYPE_MSB 9
+#define GPIO_PIN9_INT_TYPE_LSB 7
+#define GPIO_PIN9_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
+#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
+#define GPIO_PIN9_PAD_DRIVER_MSB 2
+#define GPIO_PIN9_PAD_DRIVER_LSB 2
+#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
+#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
+#define GPIO_PIN9_SOURCE_MSB 0
+#define GPIO_PIN9_SOURCE_LSB 0
+#define GPIO_PIN9_SOURCE_MASK 0x00000001
+#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
+#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
+
+#define GPIO_PIN10_ADDRESS 0x00000050
+#define GPIO_PIN10_OFFSET 0x00000050
+#define GPIO_PIN10_CONFIG_MSB 12
+#define GPIO_PIN10_CONFIG_LSB 11
+#define GPIO_PIN10_CONFIG_MASK 0x00001800
+#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
+#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN10_INT_TYPE_MSB 9
+#define GPIO_PIN10_INT_TYPE_LSB 7
+#define GPIO_PIN10_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
+#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
+#define GPIO_PIN10_PAD_DRIVER_MSB 2
+#define GPIO_PIN10_PAD_DRIVER_LSB 2
+#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
+#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
+#define GPIO_PIN10_SOURCE_MSB 0
+#define GPIO_PIN10_SOURCE_LSB 0
+#define GPIO_PIN10_SOURCE_MASK 0x00000001
+#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
+#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
+
+#define GPIO_PIN11_ADDRESS 0x00000054
+#define GPIO_PIN11_OFFSET 0x00000054
+#define GPIO_PIN11_CONFIG_MSB 12
+#define GPIO_PIN11_CONFIG_LSB 11
+#define GPIO_PIN11_CONFIG_MASK 0x00001800
+#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
+#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN11_INT_TYPE_MSB 9
+#define GPIO_PIN11_INT_TYPE_LSB 7
+#define GPIO_PIN11_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
+#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
+#define GPIO_PIN11_PAD_DRIVER_MSB 2
+#define GPIO_PIN11_PAD_DRIVER_LSB 2
+#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
+#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
+#define GPIO_PIN11_SOURCE_MSB 0
+#define GPIO_PIN11_SOURCE_LSB 0
+#define GPIO_PIN11_SOURCE_MASK 0x00000001
+#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
+#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
+
+#define GPIO_PIN12_ADDRESS 0x00000058
+#define GPIO_PIN12_OFFSET 0x00000058
+#define GPIO_PIN12_CONFIG_MSB 12
+#define GPIO_PIN12_CONFIG_LSB 11
+#define GPIO_PIN12_CONFIG_MASK 0x00001800
+#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
+#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN12_INT_TYPE_MSB 9
+#define GPIO_PIN12_INT_TYPE_LSB 7
+#define GPIO_PIN12_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
+#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
+#define GPIO_PIN12_PAD_DRIVER_MSB 2
+#define GPIO_PIN12_PAD_DRIVER_LSB 2
+#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
+#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
+#define GPIO_PIN12_SOURCE_MSB 0
+#define GPIO_PIN12_SOURCE_LSB 0
+#define GPIO_PIN12_SOURCE_MASK 0x00000001
+#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
+#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
+
+#define GPIO_PIN13_ADDRESS 0x0000005c
+#define GPIO_PIN13_OFFSET 0x0000005c
+#define GPIO_PIN13_CONFIG_MSB 12
+#define GPIO_PIN13_CONFIG_LSB 11
+#define GPIO_PIN13_CONFIG_MASK 0x00001800
+#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
+#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN13_INT_TYPE_MSB 9
+#define GPIO_PIN13_INT_TYPE_LSB 7
+#define GPIO_PIN13_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
+#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
+#define GPIO_PIN13_PAD_DRIVER_MSB 2
+#define GPIO_PIN13_PAD_DRIVER_LSB 2
+#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
+#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
+#define GPIO_PIN13_SOURCE_MSB 0
+#define GPIO_PIN13_SOURCE_LSB 0
+#define GPIO_PIN13_SOURCE_MASK 0x00000001
+#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
+#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
+
+#define GPIO_PIN14_ADDRESS 0x00000060
+#define GPIO_PIN14_OFFSET 0x00000060
+#define GPIO_PIN14_CONFIG_MSB 12
+#define GPIO_PIN14_CONFIG_LSB 11
+#define GPIO_PIN14_CONFIG_MASK 0x00001800
+#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
+#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN14_INT_TYPE_MSB 9
+#define GPIO_PIN14_INT_TYPE_LSB 7
+#define GPIO_PIN14_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
+#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
+#define GPIO_PIN14_PAD_DRIVER_MSB 2
+#define GPIO_PIN14_PAD_DRIVER_LSB 2
+#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
+#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
+#define GPIO_PIN14_SOURCE_MSB 0
+#define GPIO_PIN14_SOURCE_LSB 0
+#define GPIO_PIN14_SOURCE_MASK 0x00000001
+#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
+#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
+
+#define GPIO_PIN15_ADDRESS 0x00000064
+#define GPIO_PIN15_OFFSET 0x00000064
+#define GPIO_PIN15_CONFIG_MSB 12
+#define GPIO_PIN15_CONFIG_LSB 11
+#define GPIO_PIN15_CONFIG_MASK 0x00001800
+#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
+#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN15_INT_TYPE_MSB 9
+#define GPIO_PIN15_INT_TYPE_LSB 7
+#define GPIO_PIN15_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
+#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
+#define GPIO_PIN15_PAD_DRIVER_MSB 2
+#define GPIO_PIN15_PAD_DRIVER_LSB 2
+#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
+#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
+#define GPIO_PIN15_SOURCE_MSB 0
+#define GPIO_PIN15_SOURCE_LSB 0
+#define GPIO_PIN15_SOURCE_MASK 0x00000001
+#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
+#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
+
+#define GPIO_PIN16_ADDRESS 0x00000068
+#define GPIO_PIN16_OFFSET 0x00000068
+#define GPIO_PIN16_CONFIG_MSB 12
+#define GPIO_PIN16_CONFIG_LSB 11
+#define GPIO_PIN16_CONFIG_MASK 0x00001800
+#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
+#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN16_INT_TYPE_MSB 9
+#define GPIO_PIN16_INT_TYPE_LSB 7
+#define GPIO_PIN16_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
+#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
+#define GPIO_PIN16_PAD_DRIVER_MSB 2
+#define GPIO_PIN16_PAD_DRIVER_LSB 2
+#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
+#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
+#define GPIO_PIN16_SOURCE_MSB 0
+#define GPIO_PIN16_SOURCE_LSB 0
+#define GPIO_PIN16_SOURCE_MASK 0x00000001
+#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
+#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
+
+#define GPIO_PIN17_ADDRESS 0x0000006c
+#define GPIO_PIN17_OFFSET 0x0000006c
+#define GPIO_PIN17_CONFIG_MSB 12
+#define GPIO_PIN17_CONFIG_LSB 11
+#define GPIO_PIN17_CONFIG_MASK 0x00001800
+#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
+#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define GPIO_PIN17_INT_TYPE_MSB 9
+#define GPIO_PIN17_INT_TYPE_LSB 7
+#define GPIO_PIN17_INT_TYPE_MASK 0x00000380
+#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
+#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
+#define GPIO_PIN17_PAD_DRIVER_MSB 2
+#define GPIO_PIN17_PAD_DRIVER_LSB 2
+#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
+#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
+#define GPIO_PIN17_SOURCE_MSB 0
+#define GPIO_PIN17_SOURCE_LSB 0
+#define GPIO_PIN17_SOURCE_MASK 0x00000001
+#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
+#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
+
+#define SDIO_PIN_ADDRESS 0x00000070
+#define SDIO_PIN_OFFSET 0x00000070
+#define SDIO_PIN_PAD_PULL_MSB 3
+#define SDIO_PIN_PAD_PULL_LSB 2
+#define SDIO_PIN_PAD_PULL_MASK 0x0000000c
+#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
+#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
+#define SDIO_PIN_PAD_STRENGTH_MSB 1
+#define SDIO_PIN_PAD_STRENGTH_LSB 0
+#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003
+#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
+#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
+
+#define CLK_REQ_PIN_ADDRESS 0x00000074
+#define CLK_REQ_PIN_OFFSET 0x00000074
+#define CLK_REQ_PIN_ATE_OE_L_MSB 4
+#define CLK_REQ_PIN_ATE_OE_L_LSB 4
+#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010
+#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
+#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
+#define CLK_REQ_PIN_PAD_PULL_MSB 3
+#define CLK_REQ_PIN_PAD_PULL_LSB 2
+#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c
+#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
+#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
+#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1
+#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0
+#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003
+#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
+#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
+
+#define SIGMA_DELTA_ADDRESS 0x00000078
+#define SIGMA_DELTA_OFFSET 0x00000078
+#define SIGMA_DELTA_ENABLE_MSB 16
+#define SIGMA_DELTA_ENABLE_LSB 16
+#define SIGMA_DELTA_ENABLE_MASK 0x00010000
+#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
+#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
+#define SIGMA_DELTA_PRESCALAR_MSB 15
+#define SIGMA_DELTA_PRESCALAR_LSB 8
+#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
+#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
+#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
+#define SIGMA_DELTA_TARGET_MSB 7
+#define SIGMA_DELTA_TARGET_LSB 0
+#define SIGMA_DELTA_TARGET_MASK 0x000000ff
+#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
+#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
+
+#define DEBUG_CONTROL_ADDRESS 0x0000007c
+#define DEBUG_CONTROL_OFFSET 0x0000007c
+#define DEBUG_CONTROL_OBS_OE_L_MSB 1
+#define DEBUG_CONTROL_OBS_OE_L_LSB 1
+#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002
+#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
+#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
+#define DEBUG_CONTROL_ENABLE_MSB 0
+#define DEBUG_CONTROL_ENABLE_LSB 0
+#define DEBUG_CONTROL_ENABLE_MASK 0x00000001
+#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
+#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
+
+#define DEBUG_INPUT_SEL_ADDRESS 0x00000080
+#define DEBUG_INPUT_SEL_OFFSET 0x00000080
+#define DEBUG_INPUT_SEL_SRC_MSB 3
+#define DEBUG_INPUT_SEL_SRC_LSB 0
+#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
+#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
+#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
+
+#define DEBUG_OUT_ADDRESS 0x00000084
+#define DEBUG_OUT_OFFSET 0x00000084
+#define DEBUG_OUT_DATA_MSB 17
+#define DEBUG_OUT_DATA_LSB 0
+#define DEBUG_OUT_DATA_MASK 0x0003ffff
+#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
+#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
+
+#define LA_CONTROL_ADDRESS 0x00000088
+#define LA_CONTROL_OFFSET 0x00000088
+#define LA_CONTROL_RUN_MSB 1
+#define LA_CONTROL_RUN_LSB 1
+#define LA_CONTROL_RUN_MASK 0x00000002
+#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
+#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
+#define LA_CONTROL_TRIGGERED_MSB 0
+#define LA_CONTROL_TRIGGERED_LSB 0
+#define LA_CONTROL_TRIGGERED_MASK 0x00000001
+#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
+#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
+
+#define LA_CLOCK_ADDRESS 0x0000008c
+#define LA_CLOCK_OFFSET 0x0000008c
+#define LA_CLOCK_DIV_MSB 7
+#define LA_CLOCK_DIV_LSB 0
+#define LA_CLOCK_DIV_MASK 0x000000ff
+#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
+#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
+
+#define LA_STATUS_ADDRESS 0x00000090
+#define LA_STATUS_OFFSET 0x00000090
+#define LA_STATUS_INTERRUPT_MSB 0
+#define LA_STATUS_INTERRUPT_LSB 0
+#define LA_STATUS_INTERRUPT_MASK 0x00000001
+#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
+#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
+
+#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094
+#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094
+#define LA_TRIGGER_SAMPLE_COUNT_MSB 15
+#define LA_TRIGGER_SAMPLE_COUNT_LSB 0
+#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff
+#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
+#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
+
+#define LA_TRIGGER_POSITION_ADDRESS 0x00000098
+#define LA_TRIGGER_POSITION_OFFSET 0x00000098
+#define LA_TRIGGER_POSITION_VALUE_MSB 15
+#define LA_TRIGGER_POSITION_VALUE_LSB 0
+#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff
+#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
+#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
+
+#define LA_PRE_TRIGGER_ADDRESS 0x0000009c
+#define LA_PRE_TRIGGER_OFFSET 0x0000009c
+#define LA_PRE_TRIGGER_COUNT_MSB 15
+#define LA_PRE_TRIGGER_COUNT_LSB 0
+#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff
+#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
+#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
+
+#define LA_POST_TRIGGER_ADDRESS 0x000000a0
+#define LA_POST_TRIGGER_OFFSET 0x000000a0
+#define LA_POST_TRIGGER_COUNT_MSB 15
+#define LA_POST_TRIGGER_COUNT_LSB 0
+#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff
+#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
+#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
+
+#define LA_FILTER_CONTROL_ADDRESS 0x000000a4
+#define LA_FILTER_CONTROL_OFFSET 0x000000a4
+#define LA_FILTER_CONTROL_DELTA_MSB 0
+#define LA_FILTER_CONTROL_DELTA_LSB 0
+#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001
+#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
+#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
+
+#define LA_FILTER_DATA_ADDRESS 0x000000a8
+#define LA_FILTER_DATA_OFFSET 0x000000a8
+#define LA_FILTER_DATA_MATCH_MSB 17
+#define LA_FILTER_DATA_MATCH_LSB 0
+#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff
+#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
+#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
+
+#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac
+#define LA_FILTER_WILDCARD_OFFSET 0x000000ac
+#define LA_FILTER_WILDCARD_MATCH_MSB 17
+#define LA_FILTER_WILDCARD_MATCH_LSB 0
+#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff
+#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
+#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0
+#define LA_TRIGGERA_DATA_OFFSET 0x000000b0
+#define LA_TRIGGERA_DATA_MATCH_MSB 17
+#define LA_TRIGGERA_DATA_MATCH_LSB 0
+#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
+#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
+
+#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4
+#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4
+#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17
+#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0
+#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8
+#define LA_TRIGGERB_DATA_OFFSET 0x000000b8
+#define LA_TRIGGERB_DATA_MATCH_MSB 17
+#define LA_TRIGGERB_DATA_MATCH_LSB 0
+#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
+#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
+
+#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc
+#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc
+#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17
+#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0
+#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff
+#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
+#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
+
+#define LA_TRIGGER_ADDRESS 0x000000c0
+#define LA_TRIGGER_OFFSET 0x000000c0
+#define LA_TRIGGER_EVENT_MSB 2
+#define LA_TRIGGER_EVENT_LSB 0
+#define LA_TRIGGER_EVENT_MASK 0x00000007
+#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
+#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
+
+#define LA_FIFO_ADDRESS 0x000000c4
+#define LA_FIFO_OFFSET 0x000000c4
+#define LA_FIFO_FULL_MSB 1
+#define LA_FIFO_FULL_LSB 1
+#define LA_FIFO_FULL_MASK 0x00000002
+#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
+#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
+#define LA_FIFO_EMPTY_MSB 0
+#define LA_FIFO_EMPTY_LSB 0
+#define LA_FIFO_EMPTY_MASK 0x00000001
+#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
+#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
+
+#define LA_ADDRESS 0x000000c8
+#define LA_OFFSET 0x000000c8
+#define LA_DATA_MSB 17
+#define LA_DATA_LSB 0
+#define LA_DATA_MASK 0x0003ffff
+#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
+#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK)
+
+#define ANT_PIN_ADDRESS 0x000000d0
+#define ANT_PIN_OFFSET 0x000000d0
+#define ANT_PIN_PAD_PULL_MSB 3
+#define ANT_PIN_PAD_PULL_LSB 2
+#define ANT_PIN_PAD_PULL_MASK 0x0000000c
+#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
+#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
+#define ANT_PIN_PAD_STRENGTH_MSB 1
+#define ANT_PIN_PAD_STRENGTH_LSB 0
+#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003
+#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
+#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
+
+#define ANTD_PIN_ADDRESS 0x000000d4
+#define ANTD_PIN_OFFSET 0x000000d4
+#define ANTD_PIN_PAD_PULL_MSB 1
+#define ANTD_PIN_PAD_PULL_LSB 0
+#define ANTD_PIN_PAD_PULL_MASK 0x00000003
+#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
+#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
+
+#define GPIO_PIN_ADDRESS 0x000000d8
+#define GPIO_PIN_OFFSET 0x000000d8
+#define GPIO_PIN_PAD_PULL_MSB 3
+#define GPIO_PIN_PAD_PULL_LSB 2
+#define GPIO_PIN_PAD_PULL_MASK 0x0000000c
+#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
+#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
+#define GPIO_PIN_PAD_STRENGTH_MSB 1
+#define GPIO_PIN_PAD_STRENGTH_LSB 0
+#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003
+#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
+#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
+
+#define GPIO_H_PIN_ADDRESS 0x000000dc
+#define GPIO_H_PIN_OFFSET 0x000000dc
+#define GPIO_H_PIN_PAD_PULL_MSB 1
+#define GPIO_H_PIN_PAD_PULL_LSB 0
+#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003
+#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
+#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
+
+#define BT_PIN_ADDRESS 0x000000e0
+#define BT_PIN_OFFSET 0x000000e0
+#define BT_PIN_PAD_PULL_MSB 3
+#define BT_PIN_PAD_PULL_LSB 2
+#define BT_PIN_PAD_PULL_MASK 0x0000000c
+#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
+#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
+#define BT_PIN_PAD_STRENGTH_MSB 1
+#define BT_PIN_PAD_STRENGTH_LSB 0
+#define BT_PIN_PAD_STRENGTH_MASK 0x00000003
+#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
+#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
+
+#define BT_WLAN_PIN_ADDRESS 0x000000e4
+#define BT_WLAN_PIN_OFFSET 0x000000e4
+#define BT_WLAN_PIN_PAD_PULL_MSB 1
+#define BT_WLAN_PIN_PAD_PULL_LSB 0
+#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003
+#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
+#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
+
+#define SI_UART_PIN_ADDRESS 0x000000e8
+#define SI_UART_PIN_OFFSET 0x000000e8
+#define SI_UART_PIN_PAD_PULL_MSB 3
+#define SI_UART_PIN_PAD_PULL_LSB 2
+#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c
+#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
+#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
+#define SI_UART_PIN_PAD_STRENGTH_MSB 1
+#define SI_UART_PIN_PAD_STRENGTH_LSB 0
+#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003
+#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
+#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
+
+#define CLK32K_PIN_ADDRESS 0x000000ec
+#define CLK32K_PIN_OFFSET 0x000000ec
+#define CLK32K_PIN_PAD_PULL_MSB 1
+#define CLK32K_PIN_PAD_PULL_LSB 0
+#define CLK32K_PIN_PAD_PULL_MASK 0x00000003
+#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
+#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
+
+#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0
+#define RESET_TUPLE_STATUS_OFFSET 0x000000f0
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_reg_reg_s {
+ volatile unsigned int gpio_out;
+ volatile unsigned int gpio_out_w1ts;
+ volatile unsigned int gpio_out_w1tc;
+ volatile unsigned int gpio_enable;
+ volatile unsigned int gpio_enable_w1ts;
+ volatile unsigned int gpio_enable_w1tc;
+ volatile unsigned int gpio_in;
+ volatile unsigned int gpio_status;
+ volatile unsigned int gpio_status_w1ts;
+ volatile unsigned int gpio_status_w1tc;
+ volatile unsigned int gpio_pin0;
+ volatile unsigned int gpio_pin1;
+ volatile unsigned int gpio_pin2;
+ volatile unsigned int gpio_pin3;
+ volatile unsigned int gpio_pin4;
+ volatile unsigned int gpio_pin5;
+ volatile unsigned int gpio_pin6;
+ volatile unsigned int gpio_pin7;
+ volatile unsigned int gpio_pin8;
+ volatile unsigned int gpio_pin9;
+ volatile unsigned int gpio_pin10;
+ volatile unsigned int gpio_pin11;
+ volatile unsigned int gpio_pin12;
+ volatile unsigned int gpio_pin13;
+ volatile unsigned int gpio_pin14;
+ volatile unsigned int gpio_pin15;
+ volatile unsigned int gpio_pin16;
+ volatile unsigned int gpio_pin17;
+ volatile unsigned int sdio_pin;
+ volatile unsigned int clk_req_pin;
+ volatile unsigned int sigma_delta;
+ volatile unsigned int debug_control;
+ volatile unsigned int debug_input_sel;
+ volatile unsigned int debug_out;
+ volatile unsigned int la_control;
+ volatile unsigned int la_clock;
+ volatile unsigned int la_status;
+ volatile unsigned int la_trigger_sample;
+ volatile unsigned int la_trigger_position;
+ volatile unsigned int la_pre_trigger;
+ volatile unsigned int la_post_trigger;
+ volatile unsigned int la_filter_control;
+ volatile unsigned int la_filter_data;
+ volatile unsigned int la_filter_wildcard;
+ volatile unsigned int la_triggera_data;
+ volatile unsigned int la_triggera_wildcard;
+ volatile unsigned int la_triggerb_data;
+ volatile unsigned int la_triggerb_wildcard;
+ volatile unsigned int la_trigger;
+ volatile unsigned int la_fifo;
+ volatile unsigned int la[2];
+ volatile unsigned int ant_pin;
+ volatile unsigned int antd_pin;
+ volatile unsigned int gpio_pin;
+ volatile unsigned int gpio_h_pin;
+ volatile unsigned int bt_pin;
+ volatile unsigned int bt_wlan_pin;
+ volatile unsigned int si_uart_pin;
+ volatile unsigned int clk32k_pin;
+ volatile unsigned int reset_tuple_status;
+} gpio_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h
new file mode 100644
index 000000000000..20ac2b5c8920
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h
@@ -0,0 +1,405 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_HOST_REG_REG_H_
+#define _MBOX_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS 0x00000400
+#define HOST_INT_STATUS_OFFSET 0x00000400
+#define HOST_INT_STATUS_ERROR_MSB 7
+#define HOST_INT_STATUS_ERROR_LSB 7
+#define HOST_INT_STATUS_ERROR_MASK 0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB 6
+#define HOST_INT_STATUS_CPU_LSB 6
+#define HOST_INT_STATUS_CPU_MASK 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_DRAGON_INT_MSB 5
+#define HOST_INT_STATUS_DRAGON_INT_LSB 5
+#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
+#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
+#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB 4
+#define HOST_INT_STATUS_COUNTER_LSB 4
+#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB 3
+#define HOST_INT_STATUS_MBOX_DATA_LSB 0
+#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS 0x00000401
+#define CPU_INT_STATUS_OFFSET 0x00000401
+#define CPU_INT_STATUS_BIT_MSB 7
+#define CPU_INT_STATUS_BIT_LSB 0
+#define CPU_INT_STATUS_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS 0x00000402
+#define ERROR_INT_STATUS_OFFSET 0x00000402
+#define ERROR_INT_STATUS_SPI_MSB 3
+#define ERROR_INT_STATUS_SPI_LSB 3
+#define ERROR_INT_STATUS_SPI_MASK 0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB 2
+#define ERROR_INT_STATUS_WAKEUP_LSB 2
+#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS 0x00000403
+#define COUNTER_INT_STATUS_OFFSET 0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB 7
+#define COUNTER_INT_STATUS_COUNTER_LSB 0
+#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS 0x00000404
+#define MBOX_FRAME_OFFSET 0x00000404
+#define MBOX_FRAME_RX_EOM_MSB 7
+#define MBOX_FRAME_RX_EOM_LSB 4
+#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB 3
+#define MBOX_FRAME_RX_SOM_LSB 0
+#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS 0x00000408
+#define RX_LOOKAHEAD0_OFFSET 0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB 7
+#define RX_LOOKAHEAD0_DATA_LSB 0
+#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
+#define RX_LOOKAHEAD1_OFFSET 0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB 7
+#define RX_LOOKAHEAD1_DATA_LSB 0
+#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS 0x00000410
+#define RX_LOOKAHEAD2_OFFSET 0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB 7
+#define RX_LOOKAHEAD2_DATA_LSB 0
+#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS 0x00000414
+#define RX_LOOKAHEAD3_OFFSET 0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB 7
+#define RX_LOOKAHEAD3_DATA_LSB 0
+#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS 0x00000418
+#define INT_STATUS_ENABLE_OFFSET 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB 7
+#define INT_STATUS_ENABLE_ERROR_LSB 7
+#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB 6
+#define INT_STATUS_ENABLE_CPU_LSB 6
+#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
+#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
+#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
+#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
+#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB 4
+#define INT_STATUS_ENABLE_COUNTER_LSB 4
+#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS 0x00000420
+#define COUNT_OFFSET 0x00000420
+#define COUNT_VALUE_MSB 7
+#define COUNT_VALUE_LSB 0
+#define COUNT_VALUE_MASK 0x000000ff
+#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS 0x00000440
+#define COUNT_DEC_OFFSET 0x00000440
+#define COUNT_DEC_VALUE_MSB 7
+#define COUNT_DEC_VALUE_LSB 0
+#define COUNT_DEC_VALUE_MASK 0x000000ff
+#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS 0x00000460
+#define SCRATCH_OFFSET 0x00000460
+#define SCRATCH_VALUE_MSB 7
+#define SCRATCH_VALUE_LSB 0
+#define SCRATCH_VALUE_MASK 0x000000ff
+#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS 0x00000468
+#define FIFO_TIMEOUT_OFFSET 0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB 7
+#define FIFO_TIMEOUT_VALUE_LSB 0
+#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS 0x0000046a
+#define DISABLE_SLEEP_OFFSET 0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB 1
+#define DISABLE_SLEEP_FOR_INT_LSB 1
+#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB 0
+#define DISABLE_SLEEP_ON_LSB 0
+#define DISABLE_SLEEP_ON_MASK 0x00000001
+#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS 0x00000470
+#define LOCAL_BUS_OFFSET 0x00000470
+#define LOCAL_BUS_STATE_MSB 1
+#define LOCAL_BUS_STATE_LSB 0
+#define LOCAL_BUS_STATE_MASK 0x00000003
+#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS 0x00000472
+#define INT_WLAN_OFFSET 0x00000472
+#define INT_WLAN_VECTOR_MSB 7
+#define INT_WLAN_VECTOR_LSB 0
+#define INT_WLAN_VECTOR_MASK 0x000000ff
+#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS 0x00000474
+#define WINDOW_DATA_OFFSET 0x00000474
+#define WINDOW_DATA_DATA_MSB 7
+#define WINDOW_DATA_DATA_LSB 0
+#define WINDOW_DATA_DATA_MASK 0x000000ff
+#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB 7
+#define WINDOW_WRITE_ADDR_ADDR_LSB 0
+#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET 0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB 7
+#define WINDOW_READ_ADDR_ADDR_LSB 0
+#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define SPI_CONFIG_ADDRESS 0x00000480
+#define SPI_CONFIG_OFFSET 0x00000480
+#define SPI_CONFIG_SPI_RESET_MSB 4
+#define SPI_CONFIG_SPI_RESET_LSB 4
+#define SPI_CONFIG_SPI_RESET_MASK 0x00000010
+#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
+#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
+#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
+#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
+#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
+#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define SPI_CONFIG_TEST_MODE_MSB 2
+#define SPI_CONFIG_TEST_MODE_LSB 2
+#define SPI_CONFIG_TEST_MODE_MASK 0x00000004
+#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
+#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
+#define SPI_CONFIG_DATA_SIZE_MSB 1
+#define SPI_CONFIG_DATA_SIZE_LSB 0
+#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
+#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
+#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
+
+#define SPI_STATUS_ADDRESS 0x00000481
+#define SPI_STATUS_OFFSET 0x00000481
+#define SPI_STATUS_ADDR_ERR_MSB 3
+#define SPI_STATUS_ADDR_ERR_LSB 3
+#define SPI_STATUS_ADDR_ERR_MASK 0x00000008
+#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
+#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
+#define SPI_STATUS_RD_ERR_MSB 2
+#define SPI_STATUS_RD_ERR_LSB 2
+#define SPI_STATUS_RD_ERR_MASK 0x00000004
+#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
+#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
+#define SPI_STATUS_WR_ERR_MSB 1
+#define SPI_STATUS_WR_ERR_LSB 1
+#define SPI_STATUS_WR_ERR_MASK 0x00000002
+#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
+#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
+#define SPI_STATUS_READY_MSB 0
+#define SPI_STATUS_READY_LSB 0
+#define SPI_STATUS_READY_MASK 0x00000001
+#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
+#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CIS_WINDOW_ADDRESS 0x00000600
+#define CIS_WINDOW_OFFSET 0x00000600
+#define CIS_WINDOW_DATA_MSB 7
+#define CIS_WINDOW_DATA_LSB 0
+#define CIS_WINDOW_DATA_MASK 0x000000ff
+#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_host_reg_reg_s {
+ unsigned char pad0[1024]; /* pad to 0x400 */
+ volatile unsigned char host_int_status;
+ volatile unsigned char cpu_int_status;
+ volatile unsigned char error_int_status;
+ volatile unsigned char counter_int_status;
+ volatile unsigned char mbox_frame;
+ volatile unsigned char rx_lookahead_valid;
+ unsigned char pad1[2]; /* pad to 0x408 */
+ volatile unsigned char rx_lookahead0[4];
+ volatile unsigned char rx_lookahead1[4];
+ volatile unsigned char rx_lookahead2[4];
+ volatile unsigned char rx_lookahead3[4];
+ volatile unsigned char int_status_enable;
+ volatile unsigned char cpu_int_status_enable;
+ volatile unsigned char error_status_enable;
+ volatile unsigned char counter_int_status_enable;
+ unsigned char pad2[4]; /* pad to 0x420 */
+ volatile unsigned char count[8];
+ unsigned char pad3[24]; /* pad to 0x440 */
+ volatile unsigned char count_dec[32];
+ volatile unsigned char scratch[8];
+ volatile unsigned char fifo_timeout;
+ volatile unsigned char fifo_timeout_enable;
+ volatile unsigned char disable_sleep;
+ unsigned char pad4[5]; /* pad to 0x470 */
+ volatile unsigned char local_bus;
+ unsigned char pad5[1]; /* pad to 0x472 */
+ volatile unsigned char int_wlan;
+ unsigned char pad6[1]; /* pad to 0x474 */
+ volatile unsigned char window_data[4];
+ volatile unsigned char window_write_addr[4];
+ volatile unsigned char window_read_addr[4];
+ volatile unsigned char spi_config;
+ volatile unsigned char spi_status;
+ volatile unsigned char non_assoc_sleep_en;
+ unsigned char pad7[381]; /* pad to 0x600 */
+ volatile unsigned char cis_window[512];
+} mbox_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_HOST_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h
new file mode 100644
index 000000000000..d232764d5af6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h
@@ -0,0 +1,500 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_REG_REG_H_
+#define _MBOX_REG_REG_H_
+
+#define MBOX_FIFO_ADDRESS 0x00000000
+#define MBOX_FIFO_OFFSET 0x00000000
+#define MBOX_FIFO_DATA_MSB 19
+#define MBOX_FIFO_DATA_LSB 0
+#define MBOX_FIFO_DATA_MASK 0x000fffff
+#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
+#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
+
+#define MBOX_FIFO_STATUS_ADDRESS 0x00000010
+#define MBOX_FIFO_STATUS_OFFSET 0x00000010
+#define MBOX_FIFO_STATUS_EMPTY_MSB 19
+#define MBOX_FIFO_STATUS_EMPTY_LSB 16
+#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
+#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
+#define MBOX_FIFO_STATUS_FULL_MSB 15
+#define MBOX_FIFO_STATUS_FULL_LSB 12
+#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
+#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
+#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
+
+#define MBOX_DMA_POLICY_ADDRESS 0x00000014
+#define MBOX_DMA_POLICY_OFFSET 0x00000014
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB 2
+#define MBOX_DMA_POLICY_TX_ORDER_LSB 2
+#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB 0
+#define MBOX_DMA_POLICY_RX_ORDER_LSB 0
+#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
+#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_RX_CONTROL_START_MSB 1
+#define MBOX0_DMA_RX_CONTROL_START_LSB 1
+#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
+#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX0_DMA_TX_CONTROL_START_MSB 1
+#define MBOX0_DMA_TX_CONTROL_START_LSB 1
+#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
+#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_RX_CONTROL_START_MSB 1
+#define MBOX1_DMA_RX_CONTROL_START_LSB 1
+#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
+#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX1_DMA_TX_CONTROL_START_MSB 1
+#define MBOX1_DMA_TX_CONTROL_START_LSB 1
+#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
+#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_RX_CONTROL_START_MSB 1
+#define MBOX2_DMA_RX_CONTROL_START_LSB 1
+#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
+#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX2_DMA_TX_CONTROL_START_MSB 1
+#define MBOX2_DMA_TX_CONTROL_START_LSB 1
+#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
+#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_RX_CONTROL_START_MSB 1
+#define MBOX3_DMA_RX_CONTROL_START_LSB 1
+#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
+#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
+#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define MBOX3_DMA_TX_CONTROL_START_MSB 1
+#define MBOX3_DMA_TX_CONTROL_START_LSB 1
+#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
+#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define MBOX_INT_STATUS_ADDRESS 0x00000058
+#define MBOX_INT_STATUS_OFFSET 0x00000058
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define MBOX_INT_STATUS_HOST_MSB 7
+#define MBOX_INT_STATUS_HOST_LSB 0
+#define MBOX_INT_STATUS_HOST_MASK 0x000000ff
+#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
+#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
+
+#define MBOX_INT_ENABLE_ADDRESS 0x0000005c
+#define MBOX_INT_ENABLE_OFFSET 0x0000005c
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define MBOX_INT_ENABLE_HOST_MSB 7
+#define MBOX_INT_ENABLE_HOST_LSB 0
+#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
+#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
+#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
+
+#define INT_HOST_ADDRESS 0x00000060
+#define INT_HOST_OFFSET 0x00000060
+#define INT_HOST_VECTOR_MSB 7
+#define INT_HOST_VECTOR_LSB 0
+#define INT_HOST_VECTOR_MASK 0x000000ff
+#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
+#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
+
+#define LOCAL_COUNT_ADDRESS 0x00000080
+#define LOCAL_COUNT_OFFSET 0x00000080
+#define LOCAL_COUNT_VALUE_MSB 7
+#define LOCAL_COUNT_VALUE_LSB 0
+#define LOCAL_COUNT_VALUE_MASK 0x000000ff
+#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
+#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
+
+#define COUNT_INC_ADDRESS 0x000000a0
+#define COUNT_INC_OFFSET 0x000000a0
+#define COUNT_INC_VALUE_MSB 7
+#define COUNT_INC_VALUE_LSB 0
+#define COUNT_INC_VALUE_MASK 0x000000ff
+#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
+#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
+
+#define LOCAL_SCRATCH_ADDRESS 0x000000c0
+#define LOCAL_SCRATCH_OFFSET 0x000000c0
+#define LOCAL_SCRATCH_VALUE_MSB 7
+#define LOCAL_SCRATCH_VALUE_LSB 0
+#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
+#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
+#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
+
+#define USE_LOCAL_BUS_ADDRESS 0x000000e0
+#define USE_LOCAL_BUS_OFFSET 0x000000e0
+#define USE_LOCAL_BUS_PIN_INIT_MSB 0
+#define USE_LOCAL_BUS_PIN_INIT_LSB 0
+#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
+#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define SDIO_CONFIG_ADDRESS 0x000000e4
+#define SDIO_CONFIG_OFFSET 0x000000e4
+#define SDIO_CONFIG_CCCR_IOR1_MSB 0
+#define SDIO_CONFIG_CCCR_IOR1_LSB 0
+#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
+#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define MBOX_DEBUG_ADDRESS 0x000000e8
+#define MBOX_DEBUG_OFFSET 0x000000e8
+#define MBOX_DEBUG_SEL_MSB 2
+#define MBOX_DEBUG_SEL_LSB 0
+#define MBOX_DEBUG_SEL_MASK 0x00000007
+#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
+#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
+
+#define MBOX_FIFO_RESET_ADDRESS 0x000000ec
+#define MBOX_FIFO_RESET_OFFSET 0x000000ec
+#define MBOX_FIFO_RESET_INIT_MSB 0
+#define MBOX_FIFO_RESET_INIT_LSB 0
+#define MBOX_FIFO_RESET_INIT_MASK 0x00000001
+#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
+#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
+
+#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0
+#define MBOX_TXFIFO_POP_OFFSET 0x000000f0
+#define MBOX_TXFIFO_POP_DATA_MSB 0
+#define MBOX_TXFIFO_POP_DATA_LSB 0
+#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001
+#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
+#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
+
+#define MBOX_RXFIFO_POP_ADDRESS 0x00000100
+#define MBOX_RXFIFO_POP_OFFSET 0x00000100
+#define MBOX_RXFIFO_POP_DATA_MSB 0
+#define MBOX_RXFIFO_POP_DATA_LSB 0
+#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001
+#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
+#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
+
+#define SDIO_DEBUG_ADDRESS 0x00000110
+#define SDIO_DEBUG_OFFSET 0x00000110
+#define SDIO_DEBUG_SEL_MSB 3
+#define SDIO_DEBUG_SEL_LSB 0
+#define SDIO_DEBUG_SEL_MASK 0x0000000f
+#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
+#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
+
+#define HOST_IF_WINDOW_ADDRESS 0x00002000
+#define HOST_IF_WINDOW_OFFSET 0x00002000
+#define HOST_IF_WINDOW_DATA_MSB 7
+#define HOST_IF_WINDOW_DATA_LSB 0
+#define HOST_IF_WINDOW_DATA_MASK 0x000000ff
+#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
+#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_reg_reg_s {
+ volatile unsigned int mbox_fifo[4];
+ volatile unsigned int mbox_fifo_status;
+ volatile unsigned int mbox_dma_policy;
+ volatile unsigned int mbox0_dma_rx_descriptor_base;
+ volatile unsigned int mbox0_dma_rx_control;
+ volatile unsigned int mbox0_dma_tx_descriptor_base;
+ volatile unsigned int mbox0_dma_tx_control;
+ volatile unsigned int mbox1_dma_rx_descriptor_base;
+ volatile unsigned int mbox1_dma_rx_control;
+ volatile unsigned int mbox1_dma_tx_descriptor_base;
+ volatile unsigned int mbox1_dma_tx_control;
+ volatile unsigned int mbox2_dma_rx_descriptor_base;
+ volatile unsigned int mbox2_dma_rx_control;
+ volatile unsigned int mbox2_dma_tx_descriptor_base;
+ volatile unsigned int mbox2_dma_tx_control;
+ volatile unsigned int mbox3_dma_rx_descriptor_base;
+ volatile unsigned int mbox3_dma_rx_control;
+ volatile unsigned int mbox3_dma_tx_descriptor_base;
+ volatile unsigned int mbox3_dma_tx_control;
+ volatile unsigned int mbox_int_status;
+ volatile unsigned int mbox_int_enable;
+ volatile unsigned int int_host;
+ unsigned char pad0[28]; /* pad to 0x80 */
+ volatile unsigned int local_count[8];
+ volatile unsigned int count_inc[8];
+ volatile unsigned int local_scratch[8];
+ volatile unsigned int use_local_bus;
+ volatile unsigned int sdio_config;
+ volatile unsigned int mbox_debug;
+ volatile unsigned int mbox_fifo_reset;
+ volatile unsigned int mbox_txfifo_pop[4];
+ volatile unsigned int mbox_rxfifo_pop[4];
+ volatile unsigned int sdio_debug;
+ unsigned char pad1[7916]; /* pad to 0x2000 */
+ volatile unsigned int host_if_window[2048];
+} mbox_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h
new file mode 100644
index 000000000000..cc2cb7350a78
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h
@@ -0,0 +1,1182 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_REG_REG_H_
+#define _RTC_REG_REG_H_
+
+#define RESET_CONTROL_ADDRESS 0x00000000
+#define RESET_CONTROL_OFFSET 0x00000000
+#define RESET_CONTROL_CPU_INIT_RESET_MSB 11
+#define RESET_CONTROL_CPU_INIT_RESET_LSB 11
+#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define RESET_CONTROL_RST_OUT_MSB 9
+#define RESET_CONTROL_RST_OUT_LSB 9
+#define RESET_CONTROL_RST_OUT_MASK 0x00000200
+#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
+#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
+#define RESET_CONTROL_COLD_RST_MSB 8
+#define RESET_CONTROL_COLD_RST_LSB 8
+#define RESET_CONTROL_COLD_RST_MASK 0x00000100
+#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
+#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
+#define RESET_CONTROL_WARM_RST_MSB 7
+#define RESET_CONTROL_WARM_RST_LSB 7
+#define RESET_CONTROL_WARM_RST_MASK 0x00000080
+#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
+#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
+#define RESET_CONTROL_CPU_WARM_RST_MSB 6
+#define RESET_CONTROL_CPU_WARM_RST_LSB 6
+#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
+#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
+#define RESET_CONTROL_MAC_COLD_RST_MSB 5
+#define RESET_CONTROL_MAC_COLD_RST_LSB 5
+#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020
+#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
+#define RESET_CONTROL_MAC_WARM_RST_MSB 4
+#define RESET_CONTROL_MAC_WARM_RST_LSB 4
+#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010
+#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
+#define RESET_CONTROL_MBOX_RST_MSB 2
+#define RESET_CONTROL_MBOX_RST_LSB 2
+#define RESET_CONTROL_MBOX_RST_MASK 0x00000004
+#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
+#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
+#define RESET_CONTROL_UART_RST_MSB 1
+#define RESET_CONTROL_UART_RST_LSB 1
+#define RESET_CONTROL_UART_RST_MASK 0x00000002
+#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
+#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
+#define RESET_CONTROL_SI0_RST_MSB 0
+#define RESET_CONTROL_SI0_RST_LSB 0
+#define RESET_CONTROL_SI0_RST_MASK 0x00000001
+#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
+#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
+
+#define XTAL_CONTROL_ADDRESS 0x00000004
+#define XTAL_CONTROL_OFFSET 0x00000004
+#define XTAL_CONTROL_TCXO_MSB 0
+#define XTAL_CONTROL_TCXO_LSB 0
+#define XTAL_CONTROL_TCXO_MASK 0x00000001
+#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
+#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
+
+#define TCXO_DETECT_ADDRESS 0x00000008
+#define TCXO_DETECT_OFFSET 0x00000008
+#define TCXO_DETECT_PRESENT_MSB 0
+#define TCXO_DETECT_PRESENT_LSB 0
+#define TCXO_DETECT_PRESENT_MASK 0x00000001
+#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
+#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
+
+#define XTAL_TEST_ADDRESS 0x0000000c
+#define XTAL_TEST_OFFSET 0x0000000c
+#define XTAL_TEST_NOTCXODET_MSB 0
+#define XTAL_TEST_NOTCXODET_LSB 0
+#define XTAL_TEST_NOTCXODET_MASK 0x00000001
+#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
+#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
+
+#define QUADRATURE_ADDRESS 0x00000010
+#define QUADRATURE_OFFSET 0x00000010
+#define QUADRATURE_ADC_MSB 5
+#define QUADRATURE_ADC_LSB 4
+#define QUADRATURE_ADC_MASK 0x00000030
+#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
+#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
+#define QUADRATURE_SEL_MSB 2
+#define QUADRATURE_SEL_LSB 2
+#define QUADRATURE_SEL_MASK 0x00000004
+#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
+#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
+#define QUADRATURE_DAC_MSB 1
+#define QUADRATURE_DAC_LSB 0
+#define QUADRATURE_DAC_MASK 0x00000003
+#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
+#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
+
+#define PLL_CONTROL_ADDRESS 0x00000014
+#define PLL_CONTROL_OFFSET 0x00000014
+#define PLL_CONTROL_DIG_TEST_CLK_MSB 20
+#define PLL_CONTROL_DIG_TEST_CLK_LSB 20
+#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB 19
+#define PLL_CONTROL_MAC_OVERRIDE_LSB 19
+#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define PLL_CONTROL_NOPWD_MSB 18
+#define PLL_CONTROL_NOPWD_LSB 18
+#define PLL_CONTROL_NOPWD_MASK 0x00040000
+#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
+#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
+#define PLL_CONTROL_UPDATING_MSB 17
+#define PLL_CONTROL_UPDATING_LSB 17
+#define PLL_CONTROL_UPDATING_MASK 0x00020000
+#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
+#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
+#define PLL_CONTROL_BYPASS_MSB 16
+#define PLL_CONTROL_BYPASS_LSB 16
+#define PLL_CONTROL_BYPASS_MASK 0x00010000
+#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
+#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
+#define PLL_CONTROL_REFDIV_MSB 15
+#define PLL_CONTROL_REFDIV_LSB 12
+#define PLL_CONTROL_REFDIV_MASK 0x0000f000
+#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
+#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
+#define PLL_CONTROL_DIV_MSB 9
+#define PLL_CONTROL_DIV_LSB 0
+#define PLL_CONTROL_DIV_MASK 0x000003ff
+#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
+#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
+
+#define PLL_SETTLE_ADDRESS 0x00000018
+#define PLL_SETTLE_OFFSET 0x00000018
+#define PLL_SETTLE_TIME_MSB 11
+#define PLL_SETTLE_TIME_LSB 0
+#define PLL_SETTLE_TIME_MASK 0x00000fff
+#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
+#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
+
+#define XTAL_SETTLE_ADDRESS 0x0000001c
+#define XTAL_SETTLE_OFFSET 0x0000001c
+#define XTAL_SETTLE_TIME_MSB 7
+#define XTAL_SETTLE_TIME_LSB 0
+#define XTAL_SETTLE_TIME_MASK 0x000000ff
+#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
+#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
+
+#define CPU_CLOCK_ADDRESS 0x00000020
+#define CPU_CLOCK_OFFSET 0x00000020
+#define CPU_CLOCK_STANDARD_MSB 1
+#define CPU_CLOCK_STANDARD_LSB 0
+#define CPU_CLOCK_STANDARD_MASK 0x00000003
+#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
+#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
+
+#define CLOCK_OUT_ADDRESS 0x00000024
+#define CLOCK_OUT_OFFSET 0x00000024
+#define CLOCK_OUT_SELECT_MSB 3
+#define CLOCK_OUT_SELECT_LSB 0
+#define CLOCK_OUT_SELECT_MASK 0x0000000f
+#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
+#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
+
+#define CLOCK_CONTROL_ADDRESS 0x00000028
+#define CLOCK_CONTROL_OFFSET 0x00000028
+#define CLOCK_CONTROL_LF_CLK32_MSB 2
+#define CLOCK_CONTROL_LF_CLK32_LSB 2
+#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004
+#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB)
+#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK)
+#define CLOCK_CONTROL_UART_CLK_MSB 1
+#define CLOCK_CONTROL_UART_CLK_LSB 1
+#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002
+#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
+#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
+#define CLOCK_CONTROL_SI0_CLK_MSB 0
+#define CLOCK_CONTROL_SI0_CLK_LSB 0
+#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
+#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
+#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define BIAS_OVERRIDE_ADDRESS 0x0000002c
+#define BIAS_OVERRIDE_OFFSET 0x0000002c
+#define BIAS_OVERRIDE_ON_MSB 0
+#define BIAS_OVERRIDE_ON_LSB 0
+#define BIAS_OVERRIDE_ON_MASK 0x00000001
+#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
+#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
+
+#define WDT_CONTROL_ADDRESS 0x00000030
+#define WDT_CONTROL_OFFSET 0x00000030
+#define WDT_CONTROL_ACTION_MSB 2
+#define WDT_CONTROL_ACTION_LSB 0
+#define WDT_CONTROL_ACTION_MASK 0x00000007
+#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
+#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
+
+#define WDT_STATUS_ADDRESS 0x00000034
+#define WDT_STATUS_OFFSET 0x00000034
+#define WDT_STATUS_INTERRUPT_MSB 0
+#define WDT_STATUS_INTERRUPT_LSB 0
+#define WDT_STATUS_INTERRUPT_MASK 0x00000001
+#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
+#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
+
+#define WDT_ADDRESS 0x00000038
+#define WDT_OFFSET 0x00000038
+#define WDT_TARGET_MSB 21
+#define WDT_TARGET_LSB 0
+#define WDT_TARGET_MASK 0x003fffff
+#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
+#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
+
+#define WDT_COUNT_ADDRESS 0x0000003c
+#define WDT_COUNT_OFFSET 0x0000003c
+#define WDT_COUNT_VALUE_MSB 21
+#define WDT_COUNT_VALUE_LSB 0
+#define WDT_COUNT_VALUE_MASK 0x003fffff
+#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
+#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
+
+#define WDT_RESET_ADDRESS 0x00000040
+#define WDT_RESET_OFFSET 0x00000040
+#define WDT_RESET_VALUE_MSB 0
+#define WDT_RESET_VALUE_LSB 0
+#define WDT_RESET_VALUE_MASK 0x00000001
+#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
+#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
+
+#define INT_STATUS_ADDRESS 0x00000044
+#define INT_STATUS_OFFSET 0x00000044
+#define INT_STATUS_RTC_POWER_MSB 14
+#define INT_STATUS_RTC_POWER_LSB 14
+#define INT_STATUS_RTC_POWER_MASK 0x00004000
+#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB)
+#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK)
+#define INT_STATUS_MAC_MSB 13
+#define INT_STATUS_MAC_LSB 13
+#define INT_STATUS_MAC_MASK 0x00002000
+#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
+#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
+#define INT_STATUS_MAILBOX_MSB 12
+#define INT_STATUS_MAILBOX_LSB 12
+#define INT_STATUS_MAILBOX_MASK 0x00001000
+#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
+#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
+#define INT_STATUS_RTC_ALARM_MSB 11
+#define INT_STATUS_RTC_ALARM_LSB 11
+#define INT_STATUS_RTC_ALARM_MASK 0x00000800
+#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
+#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
+#define INT_STATUS_HF_TIMER_MSB 10
+#define INT_STATUS_HF_TIMER_LSB 10
+#define INT_STATUS_HF_TIMER_MASK 0x00000400
+#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
+#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
+#define INT_STATUS_LF_TIMER3_MSB 9
+#define INT_STATUS_LF_TIMER3_LSB 9
+#define INT_STATUS_LF_TIMER3_MASK 0x00000200
+#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
+#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
+#define INT_STATUS_LF_TIMER2_MSB 8
+#define INT_STATUS_LF_TIMER2_LSB 8
+#define INT_STATUS_LF_TIMER2_MASK 0x00000100
+#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
+#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
+#define INT_STATUS_LF_TIMER1_MSB 7
+#define INT_STATUS_LF_TIMER1_LSB 7
+#define INT_STATUS_LF_TIMER1_MASK 0x00000080
+#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
+#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
+#define INT_STATUS_LF_TIMER0_MSB 6
+#define INT_STATUS_LF_TIMER0_LSB 6
+#define INT_STATUS_LF_TIMER0_MASK 0x00000040
+#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
+#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
+#define INT_STATUS_KEYPAD_MSB 5
+#define INT_STATUS_KEYPAD_LSB 5
+#define INT_STATUS_KEYPAD_MASK 0x00000020
+#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
+#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
+#define INT_STATUS_SI_MSB 4
+#define INT_STATUS_SI_LSB 4
+#define INT_STATUS_SI_MASK 0x00000010
+#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
+#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
+#define INT_STATUS_GPIO_MSB 3
+#define INT_STATUS_GPIO_LSB 3
+#define INT_STATUS_GPIO_MASK 0x00000008
+#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
+#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
+#define INT_STATUS_UART_MSB 2
+#define INT_STATUS_UART_LSB 2
+#define INT_STATUS_UART_MASK 0x00000004
+#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
+#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
+#define INT_STATUS_ERROR_MSB 1
+#define INT_STATUS_ERROR_LSB 1
+#define INT_STATUS_ERROR_MASK 0x00000002
+#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
+#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
+#define INT_STATUS_WDT_INT_MSB 0
+#define INT_STATUS_WDT_INT_LSB 0
+#define INT_STATUS_WDT_INT_MASK 0x00000001
+#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
+#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
+
+#define LF_TIMER0_ADDRESS 0x00000048
+#define LF_TIMER0_OFFSET 0x00000048
+#define LF_TIMER0_TARGET_MSB 31
+#define LF_TIMER0_TARGET_LSB 0
+#define LF_TIMER0_TARGET_MASK 0xffffffff
+#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
+#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
+
+#define LF_TIMER_COUNT0_ADDRESS 0x0000004c
+#define LF_TIMER_COUNT0_OFFSET 0x0000004c
+#define LF_TIMER_COUNT0_VALUE_MSB 31
+#define LF_TIMER_COUNT0_VALUE_LSB 0
+#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
+#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
+
+#define LF_TIMER_CONTROL0_ADDRESS 0x00000050
+#define LF_TIMER_CONTROL0_OFFSET 0x00000050
+#define LF_TIMER_CONTROL0_ENABLE_MSB 2
+#define LF_TIMER_CONTROL0_ENABLE_LSB 2
+#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL0_RESET_MSB 0
+#define LF_TIMER_CONTROL0_RESET_LSB 0
+#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
+#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
+
+#define LF_TIMER_STATUS0_ADDRESS 0x00000054
+#define LF_TIMER_STATUS0_OFFSET 0x00000054
+#define LF_TIMER_STATUS0_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS0_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define LF_TIMER1_ADDRESS 0x00000058
+#define LF_TIMER1_OFFSET 0x00000058
+#define LF_TIMER1_TARGET_MSB 31
+#define LF_TIMER1_TARGET_LSB 0
+#define LF_TIMER1_TARGET_MASK 0xffffffff
+#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
+#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
+
+#define LF_TIMER_COUNT1_ADDRESS 0x0000005c
+#define LF_TIMER_COUNT1_OFFSET 0x0000005c
+#define LF_TIMER_COUNT1_VALUE_MSB 31
+#define LF_TIMER_COUNT1_VALUE_LSB 0
+#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
+#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
+
+#define LF_TIMER_CONTROL1_ADDRESS 0x00000060
+#define LF_TIMER_CONTROL1_OFFSET 0x00000060
+#define LF_TIMER_CONTROL1_ENABLE_MSB 2
+#define LF_TIMER_CONTROL1_ENABLE_LSB 2
+#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL1_RESET_MSB 0
+#define LF_TIMER_CONTROL1_RESET_LSB 0
+#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
+#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
+
+#define LF_TIMER_STATUS1_ADDRESS 0x00000064
+#define LF_TIMER_STATUS1_OFFSET 0x00000064
+#define LF_TIMER_STATUS1_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS1_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define LF_TIMER2_ADDRESS 0x00000068
+#define LF_TIMER2_OFFSET 0x00000068
+#define LF_TIMER2_TARGET_MSB 31
+#define LF_TIMER2_TARGET_LSB 0
+#define LF_TIMER2_TARGET_MASK 0xffffffff
+#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
+#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
+
+#define LF_TIMER_COUNT2_ADDRESS 0x0000006c
+#define LF_TIMER_COUNT2_OFFSET 0x0000006c
+#define LF_TIMER_COUNT2_VALUE_MSB 31
+#define LF_TIMER_COUNT2_VALUE_LSB 0
+#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
+#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
+
+#define LF_TIMER_CONTROL2_ADDRESS 0x00000070
+#define LF_TIMER_CONTROL2_OFFSET 0x00000070
+#define LF_TIMER_CONTROL2_ENABLE_MSB 2
+#define LF_TIMER_CONTROL2_ENABLE_LSB 2
+#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL2_RESET_MSB 0
+#define LF_TIMER_CONTROL2_RESET_LSB 0
+#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
+#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
+
+#define LF_TIMER_STATUS2_ADDRESS 0x00000074
+#define LF_TIMER_STATUS2_OFFSET 0x00000074
+#define LF_TIMER_STATUS2_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS2_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define LF_TIMER3_ADDRESS 0x00000078
+#define LF_TIMER3_OFFSET 0x00000078
+#define LF_TIMER3_TARGET_MSB 31
+#define LF_TIMER3_TARGET_LSB 0
+#define LF_TIMER3_TARGET_MASK 0xffffffff
+#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
+#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
+
+#define LF_TIMER_COUNT3_ADDRESS 0x0000007c
+#define LF_TIMER_COUNT3_OFFSET 0x0000007c
+#define LF_TIMER_COUNT3_VALUE_MSB 31
+#define LF_TIMER_COUNT3_VALUE_LSB 0
+#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff
+#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
+#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
+
+#define LF_TIMER_CONTROL3_ADDRESS 0x00000080
+#define LF_TIMER_CONTROL3_OFFSET 0x00000080
+#define LF_TIMER_CONTROL3_ENABLE_MSB 2
+#define LF_TIMER_CONTROL3_ENABLE_LSB 2
+#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004
+#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define LF_TIMER_CONTROL3_RESET_MSB 0
+#define LF_TIMER_CONTROL3_RESET_LSB 0
+#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001
+#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
+#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
+
+#define LF_TIMER_STATUS3_ADDRESS 0x00000084
+#define LF_TIMER_STATUS3_OFFSET 0x00000084
+#define LF_TIMER_STATUS3_INTERRUPT_MSB 0
+#define LF_TIMER_STATUS3_INTERRUPT_LSB 0
+#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define HF_TIMER_ADDRESS 0x00000088
+#define HF_TIMER_OFFSET 0x00000088
+#define HF_TIMER_TARGET_MSB 31
+#define HF_TIMER_TARGET_LSB 12
+#define HF_TIMER_TARGET_MASK 0xfffff000
+#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
+#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
+
+#define HF_TIMER_COUNT_ADDRESS 0x0000008c
+#define HF_TIMER_COUNT_OFFSET 0x0000008c
+#define HF_TIMER_COUNT_VALUE_MSB 31
+#define HF_TIMER_COUNT_VALUE_LSB 12
+#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000
+#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
+#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
+
+#define HF_LF_COUNT_ADDRESS 0x00000090
+#define HF_LF_COUNT_OFFSET 0x00000090
+#define HF_LF_COUNT_VALUE_MSB 31
+#define HF_LF_COUNT_VALUE_LSB 0
+#define HF_LF_COUNT_VALUE_MASK 0xffffffff
+#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
+#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
+
+#define HF_TIMER_CONTROL_ADDRESS 0x00000094
+#define HF_TIMER_CONTROL_OFFSET 0x00000094
+#define HF_TIMER_CONTROL_ENABLE_MSB 3
+#define HF_TIMER_CONTROL_ENABLE_LSB 3
+#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008
+#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
+#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
+#define HF_TIMER_CONTROL_ON_MSB 2
+#define HF_TIMER_CONTROL_ON_LSB 2
+#define HF_TIMER_CONTROL_ON_MASK 0x00000004
+#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
+#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define HF_TIMER_CONTROL_RESET_MSB 0
+#define HF_TIMER_CONTROL_RESET_LSB 0
+#define HF_TIMER_CONTROL_RESET_MASK 0x00000001
+#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
+#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
+
+#define HF_TIMER_STATUS_ADDRESS 0x00000098
+#define HF_TIMER_STATUS_OFFSET 0x00000098
+#define HF_TIMER_STATUS_INTERRUPT_MSB 0
+#define HF_TIMER_STATUS_INTERRUPT_LSB 0
+#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001
+#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define RTC_CONTROL_ADDRESS 0x0000009c
+#define RTC_CONTROL_OFFSET 0x0000009c
+#define RTC_CONTROL_ENABLE_MSB 2
+#define RTC_CONTROL_ENABLE_LSB 2
+#define RTC_CONTROL_ENABLE_MASK 0x00000004
+#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
+#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
+#define RTC_CONTROL_LOAD_RTC_MSB 1
+#define RTC_CONTROL_LOAD_RTC_LSB 1
+#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002
+#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
+#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
+#define RTC_CONTROL_LOAD_ALARM_MSB 0
+#define RTC_CONTROL_LOAD_ALARM_LSB 0
+#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001
+#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
+#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define RTC_TIME_ADDRESS 0x000000a0
+#define RTC_TIME_OFFSET 0x000000a0
+#define RTC_TIME_WEEK_DAY_MSB 26
+#define RTC_TIME_WEEK_DAY_LSB 24
+#define RTC_TIME_WEEK_DAY_MASK 0x07000000
+#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
+#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
+#define RTC_TIME_HOUR_MSB 21
+#define RTC_TIME_HOUR_LSB 16
+#define RTC_TIME_HOUR_MASK 0x003f0000
+#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
+#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
+#define RTC_TIME_MINUTE_MSB 14
+#define RTC_TIME_MINUTE_LSB 8
+#define RTC_TIME_MINUTE_MASK 0x00007f00
+#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
+#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
+#define RTC_TIME_SECOND_MSB 6
+#define RTC_TIME_SECOND_LSB 0
+#define RTC_TIME_SECOND_MASK 0x0000007f
+#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
+#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
+
+#define RTC_DATE_ADDRESS 0x000000a4
+#define RTC_DATE_OFFSET 0x000000a4
+#define RTC_DATE_YEAR_MSB 23
+#define RTC_DATE_YEAR_LSB 16
+#define RTC_DATE_YEAR_MASK 0x00ff0000
+#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
+#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
+#define RTC_DATE_MONTH_MSB 12
+#define RTC_DATE_MONTH_LSB 8
+#define RTC_DATE_MONTH_MASK 0x00001f00
+#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
+#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
+#define RTC_DATE_MONTH_DAY_MSB 5
+#define RTC_DATE_MONTH_DAY_LSB 0
+#define RTC_DATE_MONTH_DAY_MASK 0x0000003f
+#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
+#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_TIME_ADDRESS 0x000000a8
+#define RTC_SET_TIME_OFFSET 0x000000a8
+#define RTC_SET_TIME_WEEK_DAY_MSB 26
+#define RTC_SET_TIME_WEEK_DAY_LSB 24
+#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000
+#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
+#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
+#define RTC_SET_TIME_HOUR_MSB 21
+#define RTC_SET_TIME_HOUR_LSB 16
+#define RTC_SET_TIME_HOUR_MASK 0x003f0000
+#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
+#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
+#define RTC_SET_TIME_MINUTE_MSB 14
+#define RTC_SET_TIME_MINUTE_LSB 8
+#define RTC_SET_TIME_MINUTE_MASK 0x00007f00
+#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
+#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
+#define RTC_SET_TIME_SECOND_MSB 6
+#define RTC_SET_TIME_SECOND_LSB 0
+#define RTC_SET_TIME_SECOND_MASK 0x0000007f
+#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
+#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
+
+#define RTC_SET_DATE_ADDRESS 0x000000ac
+#define RTC_SET_DATE_OFFSET 0x000000ac
+#define RTC_SET_DATE_YEAR_MSB 23
+#define RTC_SET_DATE_YEAR_LSB 16
+#define RTC_SET_DATE_YEAR_MASK 0x00ff0000
+#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
+#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
+#define RTC_SET_DATE_MONTH_MSB 12
+#define RTC_SET_DATE_MONTH_LSB 8
+#define RTC_SET_DATE_MONTH_MASK 0x00001f00
+#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
+#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
+#define RTC_SET_DATE_MONTH_DAY_MSB 5
+#define RTC_SET_DATE_MONTH_DAY_LSB 0
+#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f
+#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
+#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define RTC_SET_ALARM_ADDRESS 0x000000b0
+#define RTC_SET_ALARM_OFFSET 0x000000b0
+#define RTC_SET_ALARM_HOUR_MSB 21
+#define RTC_SET_ALARM_HOUR_LSB 16
+#define RTC_SET_ALARM_HOUR_MASK 0x003f0000
+#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
+#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
+#define RTC_SET_ALARM_MINUTE_MSB 14
+#define RTC_SET_ALARM_MINUTE_LSB 8
+#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00
+#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
+#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
+#define RTC_SET_ALARM_SECOND_MSB 6
+#define RTC_SET_ALARM_SECOND_LSB 0
+#define RTC_SET_ALARM_SECOND_MASK 0x0000007f
+#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
+#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
+
+#define RTC_CONFIG_ADDRESS 0x000000b4
+#define RTC_CONFIG_OFFSET 0x000000b4
+#define RTC_CONFIG_BCD_MSB 2
+#define RTC_CONFIG_BCD_LSB 2
+#define RTC_CONFIG_BCD_MASK 0x00000004
+#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
+#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
+#define RTC_CONFIG_TWELVE_HOUR_MSB 1
+#define RTC_CONFIG_TWELVE_HOUR_LSB 1
+#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002
+#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
+#define RTC_CONFIG_DSE_MSB 0
+#define RTC_CONFIG_DSE_LSB 0
+#define RTC_CONFIG_DSE_MASK 0x00000001
+#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
+#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
+
+#define RTC_ALARM_STATUS_ADDRESS 0x000000b8
+#define RTC_ALARM_STATUS_OFFSET 0x000000b8
+#define RTC_ALARM_STATUS_ENABLE_MSB 1
+#define RTC_ALARM_STATUS_ENABLE_LSB 1
+#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002
+#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
+#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB 0
+#define RTC_ALARM_STATUS_INTERRUPT_LSB 0
+#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define UART_WAKEUP_ADDRESS 0x000000bc
+#define UART_WAKEUP_OFFSET 0x000000bc
+#define UART_WAKEUP_ENABLE_MSB 0
+#define UART_WAKEUP_ENABLE_LSB 0
+#define UART_WAKEUP_ENABLE_MASK 0x00000001
+#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
+#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
+
+#define RESET_CAUSE_ADDRESS 0x000000c0
+#define RESET_CAUSE_OFFSET 0x000000c0
+#define RESET_CAUSE_LAST_MSB 2
+#define RESET_CAUSE_LAST_LSB 0
+#define RESET_CAUSE_LAST_MASK 0x00000007
+#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
+#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
+
+#define SYSTEM_SLEEP_ADDRESS 0x000000c4
+#define SYSTEM_SLEEP_OFFSET 0x000000c4
+#define SYSTEM_SLEEP_HOST_IF_MSB 4
+#define SYSTEM_SLEEP_HOST_IF_LSB 4
+#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010
+#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
+#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
+#define SYSTEM_SLEEP_MBOX_MSB 3
+#define SYSTEM_SLEEP_MBOX_LSB 3
+#define SYSTEM_SLEEP_MBOX_MASK 0x00000008
+#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
+#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
+#define SYSTEM_SLEEP_MAC_IF_MSB 2
+#define SYSTEM_SLEEP_MAC_IF_LSB 2
+#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004
+#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
+#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
+#define SYSTEM_SLEEP_LIGHT_MSB 1
+#define SYSTEM_SLEEP_LIGHT_LSB 1
+#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002
+#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
+#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
+#define SYSTEM_SLEEP_DISABLE_MSB 0
+#define SYSTEM_SLEEP_DISABLE_LSB 0
+#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001
+#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+
+#define SDIO_WRAPPER_ADDRESS 0x000000c8
+#define SDIO_WRAPPER_OFFSET 0x000000c8
+#define SDIO_WRAPPER_SLEEP_MSB 3
+#define SDIO_WRAPPER_SLEEP_LSB 3
+#define SDIO_WRAPPER_SLEEP_MASK 0x00000008
+#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
+#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
+#define SDIO_WRAPPER_WAKEUP_MSB 2
+#define SDIO_WRAPPER_WAKEUP_LSB 2
+#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004
+#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
+#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
+#define SDIO_WRAPPER_SOC_ON_MSB 1
+#define SDIO_WRAPPER_SOC_ON_LSB 1
+#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002
+#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
+#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
+#define SDIO_WRAPPER_ON_MSB 0
+#define SDIO_WRAPPER_ON_LSB 0
+#define SDIO_WRAPPER_ON_MASK 0x00000001
+#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
+#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
+
+#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc
+#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc
+#define MAC_SLEEP_CONTROL_ENABLE_MSB 1
+#define MAC_SLEEP_CONTROL_ENABLE_LSB 0
+#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define KEEP_AWAKE_ADDRESS 0x000000d0
+#define KEEP_AWAKE_OFFSET 0x000000d0
+#define KEEP_AWAKE_COUNT_MSB 7
+#define KEEP_AWAKE_COUNT_LSB 0
+#define KEEP_AWAKE_COUNT_MASK 0x000000ff
+#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
+#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
+
+#define LPO_CAL_TIME_ADDRESS 0x000000d4
+#define LPO_CAL_TIME_OFFSET 0x000000d4
+#define LPO_CAL_TIME_LENGTH_MSB 13
+#define LPO_CAL_TIME_LENGTH_LSB 0
+#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff
+#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB)
+#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK)
+
+#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8
+#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define LPO_CAL_ADDRESS 0x000000e0
+#define LPO_CAL_OFFSET 0x000000e0
+#define LPO_CAL_ENABLE_MSB 20
+#define LPO_CAL_ENABLE_LSB 20
+#define LPO_CAL_ENABLE_MASK 0x00100000
+#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB)
+#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
+#define LPO_CAL_COUNT_MSB 19
+#define LPO_CAL_COUNT_LSB 0
+#define LPO_CAL_COUNT_MASK 0x000fffff
+#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB)
+#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK)
+
+#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4
+#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8
+#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8
+#define LPO_CAL_TEST_STATUS_READY_MSB 16
+#define LPO_CAL_TEST_STATUS_READY_LSB 16
+#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000
+#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB)
+#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB 15
+#define LPO_CAL_TEST_STATUS_COUNT_LSB 0
+#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define CHIP_ID_ADDRESS 0x000000ec
+#define CHIP_ID_OFFSET 0x000000ec
+#define CHIP_ID_DEVICE_ID_MSB 31
+#define CHIP_ID_DEVICE_ID_LSB 16
+#define CHIP_ID_DEVICE_ID_MASK 0xffff0000
+#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB)
+#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK)
+#define CHIP_ID_CONFIG_ID_MSB 15
+#define CHIP_ID_CONFIG_ID_LSB 4
+#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0
+#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB)
+#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK)
+#define CHIP_ID_VERSION_ID_MSB 3
+#define CHIP_ID_VERSION_ID_LSB 0
+#define CHIP_ID_VERSION_ID_MASK 0x0000000f
+#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB)
+#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK)
+
+#define DERIVED_RTC_CLK_ADDRESS 0x000000f0
+#define DERIVED_RTC_CLK_OFFSET 0x000000f0
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define DERIVED_RTC_CLK_FORCE_MSB 17
+#define DERIVED_RTC_CLK_FORCE_LSB 16
+#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000
+#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
+#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
+#define DERIVED_RTC_CLK_PERIOD_MSB 15
+#define DERIVED_RTC_CLK_PERIOD_LSB 1
+#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe
+#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
+#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB 1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB 1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c
+#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB)
+#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK)
+
+#define POWER_REG_ADDRESS 0x00000110
+#define POWER_REG_OFFSET 0x00000110
+#define POWER_REG_VLVL_MSB 11
+#define POWER_REG_VLVL_LSB 8
+#define POWER_REG_VLVL_MASK 0x00000f00
+#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB)
+#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK)
+#define POWER_REG_CPU_INT_ENABLE_MSB 7
+#define POWER_REG_CPU_INT_ENABLE_LSB 7
+#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080
+#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB)
+#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK)
+#define POWER_REG_WLAN_ISO_DIS_MSB 6
+#define POWER_REG_WLAN_ISO_DIS_LSB 6
+#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040
+#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB)
+#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK)
+#define POWER_REG_WLAN_ISO_CNTL_MSB 5
+#define POWER_REG_WLAN_ISO_CNTL_LSB 5
+#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020
+#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK)
+#define POWER_REG_RADIO_PWD_EN_MSB 4
+#define POWER_REG_RADIO_PWD_EN_LSB 4
+#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010
+#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB)
+#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK)
+#define POWER_REG_SOC_SCALE_EN_MSB 3
+#define POWER_REG_SOC_SCALE_EN_LSB 3
+#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008
+#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB)
+#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK)
+#define POWER_REG_WLAN_SCALE_EN_MSB 2
+#define POWER_REG_WLAN_SCALE_EN_LSB 2
+#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004
+#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB)
+#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK)
+#define POWER_REG_WLAN_PWD_EN_MSB 1
+#define POWER_REG_WLAN_PWD_EN_LSB 1
+#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002
+#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB)
+#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK)
+#define POWER_REG_POWER_EN_MSB 0
+#define POWER_REG_POWER_EN_LSB 0
+#define POWER_REG_POWER_EN_MASK 0x00000001
+#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB)
+#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK)
+
+#define CORE_CLK_CTRL_ADDRESS 0x00000114
+#define CORE_CLK_CTRL_OFFSET 0x00000114
+#define CORE_CLK_CTRL_DIV_MSB 2
+#define CORE_CLK_CTRL_DIV_LSB 0
+#define CORE_CLK_CTRL_DIV_MASK 0x00000007
+#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB)
+#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK)
+
+#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120
+#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120
+#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7
+#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0
+#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
+#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
+#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140
+#define SDIO_SETUP_CONFIG_OFFSET 0x00000140
+#define SDIO_SETUP_CONFIG_ENABLE_MSB 1
+#define SDIO_SETUP_CONFIG_ENABLE_LSB 1
+#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002
+#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
+#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
+#define SDIO_SETUP_CONFIG_CLEAR_MSB 0
+#define SDIO_SETUP_CONFIG_CLEAR_LSB 0
+#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001
+#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
+#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CONFIG_ADDRESS 0x00000144
+#define CPU_SETUP_CONFIG_OFFSET 0x00000144
+#define CPU_SETUP_CONFIG_ENABLE_MSB 1
+#define CPU_SETUP_CONFIG_ENABLE_LSB 1
+#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002
+#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
+#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
+#define CPU_SETUP_CONFIG_CLEAR_MSB 0
+#define CPU_SETUP_CONFIG_CLEAR_LSB 0
+#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001
+#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
+#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
+
+#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160
+#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160
+#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7
+#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0
+#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
+#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
+#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define BB_SETUP_CONFIG_ADDRESS 0x00000180
+#define BB_SETUP_CONFIG_OFFSET 0x00000180
+#define BB_SETUP_CONFIG_ENABLE_MSB 1
+#define BB_SETUP_CONFIG_ENABLE_LSB 1
+#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002
+#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
+#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
+#define BB_SETUP_CONFIG_CLEAR_MSB 0
+#define BB_SETUP_CONFIG_CLEAR_LSB 0
+#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001
+#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
+#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
+
+#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0
+#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0
+#define BB_SETUP_CIRCUIT_VECTOR_MSB 7
+#define BB_SETUP_CIRCUIT_VECTOR_LSB 0
+#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
+#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
+#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
+
+#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0
+#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_reg_reg_s {
+ volatile unsigned int reset_control;
+ volatile unsigned int xtal_control;
+ volatile unsigned int tcxo_detect;
+ volatile unsigned int xtal_test;
+ volatile unsigned int quadrature;
+ volatile unsigned int pll_control;
+ volatile unsigned int pll_settle;
+ volatile unsigned int xtal_settle;
+ volatile unsigned int cpu_clock;
+ volatile unsigned int clock_out;
+ volatile unsigned int clock_control;
+ volatile unsigned int bias_override;
+ volatile unsigned int wdt_control;
+ volatile unsigned int wdt_status;
+ volatile unsigned int wdt;
+ volatile unsigned int wdt_count;
+ volatile unsigned int wdt_reset;
+ volatile unsigned int int_status;
+ volatile unsigned int lf_timer0;
+ volatile unsigned int lf_timer_count0;
+ volatile unsigned int lf_timer_control0;
+ volatile unsigned int lf_timer_status0;
+ volatile unsigned int lf_timer1;
+ volatile unsigned int lf_timer_count1;
+ volatile unsigned int lf_timer_control1;
+ volatile unsigned int lf_timer_status1;
+ volatile unsigned int lf_timer2;
+ volatile unsigned int lf_timer_count2;
+ volatile unsigned int lf_timer_control2;
+ volatile unsigned int lf_timer_status2;
+ volatile unsigned int lf_timer3;
+ volatile unsigned int lf_timer_count3;
+ volatile unsigned int lf_timer_control3;
+ volatile unsigned int lf_timer_status3;
+ volatile unsigned int hf_timer;
+ volatile unsigned int hf_timer_count;
+ volatile unsigned int hf_lf_count;
+ volatile unsigned int hf_timer_control;
+ volatile unsigned int hf_timer_status;
+ volatile unsigned int rtc_control;
+ volatile unsigned int rtc_time;
+ volatile unsigned int rtc_date;
+ volatile unsigned int rtc_set_time;
+ volatile unsigned int rtc_set_date;
+ volatile unsigned int rtc_set_alarm;
+ volatile unsigned int rtc_config;
+ volatile unsigned int rtc_alarm_status;
+ volatile unsigned int uart_wakeup;
+ volatile unsigned int reset_cause;
+ volatile unsigned int system_sleep;
+ volatile unsigned int sdio_wrapper;
+ volatile unsigned int mac_sleep_control;
+ volatile unsigned int keep_awake;
+ volatile unsigned int lpo_cal_time;
+ volatile unsigned int lpo_init_dividend_int;
+ volatile unsigned int lpo_init_dividend_fraction;
+ volatile unsigned int lpo_cal;
+ volatile unsigned int lpo_cal_test_control;
+ volatile unsigned int lpo_cal_test_status;
+ volatile unsigned int chip_id;
+ volatile unsigned int derived_rtc_clk;
+ volatile unsigned int mac_pcu_slp32_mode;
+ volatile unsigned int mac_pcu_slp32_wake;
+ volatile unsigned int mac_pcu_slp32_inc;
+ volatile unsigned int mac_pcu_slp_mib1;
+ volatile unsigned int mac_pcu_slp_mib2;
+ volatile unsigned int mac_pcu_slp_mib3;
+ volatile unsigned int mac_pcu_slp_beacon;
+ volatile unsigned int power_reg;
+ volatile unsigned int core_clk_ctrl;
+ unsigned char pad0[8]; /* pad to 0x120 */
+ volatile unsigned int sdio_setup_circuit[8];
+ volatile unsigned int sdio_setup_config;
+ volatile unsigned int cpu_setup_config;
+ unsigned char pad1[24]; /* pad to 0x160 */
+ volatile unsigned int cpu_setup_circuit[8];
+ volatile unsigned int bb_setup_config;
+ unsigned char pad2[28]; /* pad to 0x1a0 */
+ volatile unsigned int bb_setup_circuit[8];
+ volatile unsigned int gpio_wakeup_control;
+} rtc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h
new file mode 100644
index 000000000000..44d24661761e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h
@@ -0,0 +1,205 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS 0x00000000
+#define SI_CONFIG_OFFSET 0x00000000
+#define SI_CONFIG_ERR_INT_MSB 19
+#define SI_CONFIG_ERR_INT_LSB 19
+#define SI_CONFIG_ERR_INT_MASK 0x00080000
+#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB 16
+#define SI_CONFIG_I2C_LSB 16
+#define SI_CONFIG_I2C_MASK 0x00010000
+#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB 7
+#define SI_CONFIG_POS_SAMPLE_LSB 7
+#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB 6
+#define SI_CONFIG_POS_DRIVE_LSB 6
+#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB 5
+#define SI_CONFIG_INACTIVE_DATA_LSB 5
+#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB 4
+#define SI_CONFIG_INACTIVE_CLK_LSB 4
+#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB 3
+#define SI_CONFIG_DIVIDER_LSB 0
+#define SI_CONFIG_DIVIDER_MASK 0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS 0x00000004
+#define SI_CS_OFFSET 0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB 10
+#define SI_CS_DONE_ERR_LSB 10
+#define SI_CS_DONE_ERR_MASK 0x00000400
+#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB 9
+#define SI_CS_DONE_INT_LSB 9
+#define SI_CS_DONE_INT_MASK 0x00000200
+#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB 8
+#define SI_CS_START_LSB 8
+#define SI_CS_START_MASK 0x00000100
+#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB 7
+#define SI_CS_RX_CNT_LSB 4
+#define SI_CS_RX_CNT_MASK 0x000000f0
+#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB 3
+#define SI_CS_TX_CNT_LSB 0
+#define SI_CS_TX_CNT_MASK 0x0000000f
+#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS 0x00000008
+#define SI_TX_DATA0_OFFSET 0x00000008
+#define SI_TX_DATA0_DATA3_MSB 31
+#define SI_TX_DATA0_DATA3_LSB 24
+#define SI_TX_DATA0_DATA3_MASK 0xff000000
+#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB 23
+#define SI_TX_DATA0_DATA2_LSB 16
+#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB 15
+#define SI_TX_DATA0_DATA1_LSB 8
+#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB 7
+#define SI_TX_DATA0_DATA0_LSB 0
+#define SI_TX_DATA0_DATA0_MASK 0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS 0x0000000c
+#define SI_TX_DATA1_OFFSET 0x0000000c
+#define SI_TX_DATA1_DATA7_MSB 31
+#define SI_TX_DATA1_DATA7_LSB 24
+#define SI_TX_DATA1_DATA7_MASK 0xff000000
+#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB 23
+#define SI_TX_DATA1_DATA6_LSB 16
+#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB 15
+#define SI_TX_DATA1_DATA5_LSB 8
+#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB 7
+#define SI_TX_DATA1_DATA4_LSB 0
+#define SI_TX_DATA1_DATA4_MASK 0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS 0x00000010
+#define SI_RX_DATA0_OFFSET 0x00000010
+#define SI_RX_DATA0_DATA3_MSB 31
+#define SI_RX_DATA0_DATA3_LSB 24
+#define SI_RX_DATA0_DATA3_MASK 0xff000000
+#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB 23
+#define SI_RX_DATA0_DATA2_LSB 16
+#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB 15
+#define SI_RX_DATA0_DATA1_LSB 8
+#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB 7
+#define SI_RX_DATA0_DATA0_LSB 0
+#define SI_RX_DATA0_DATA0_MASK 0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS 0x00000014
+#define SI_RX_DATA1_OFFSET 0x00000014
+#define SI_RX_DATA1_DATA7_MSB 31
+#define SI_RX_DATA1_DATA7_LSB 24
+#define SI_RX_DATA1_DATA7_MASK 0xff000000
+#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB 23
+#define SI_RX_DATA1_DATA6_LSB 16
+#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB 15
+#define SI_RX_DATA1_DATA5_LSB 8
+#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB 7
+#define SI_RX_DATA1_DATA4_LSB 0
+#define SI_RX_DATA1_DATA4_MASK 0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+ volatile unsigned int si_config;
+ volatile unsigned int si_cs;
+ volatile unsigned int si_tx_data0;
+ volatile unsigned int si_tx_data1;
+ volatile unsigned int si_rx_data0;
+ volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h
new file mode 100644
index 000000000000..db573106dcd2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h
@@ -0,0 +1,346 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define RBR_ADDRESS 0x00000000
+#define RBR_OFFSET 0x00000000
+#define RBR_RBR_MSB 7
+#define RBR_RBR_LSB 0
+#define RBR_RBR_MASK 0x000000ff
+#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
+#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
+
+#define THR_ADDRESS 0x00000000
+#define THR_OFFSET 0x00000000
+#define THR_THR_MSB 7
+#define THR_THR_LSB 0
+#define THR_THR_MASK 0x000000ff
+#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
+#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
+
+#define DLL_ADDRESS 0x00000000
+#define DLL_OFFSET 0x00000000
+#define DLL_DLL_MSB 7
+#define DLL_DLL_LSB 0
+#define DLL_DLL_MASK 0x000000ff
+#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
+#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
+
+#define DLH_ADDRESS 0x00000004
+#define DLH_OFFSET 0x00000004
+#define DLH_DLH_MSB 7
+#define DLH_DLH_LSB 0
+#define DLH_DLH_MASK 0x000000ff
+#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
+#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
+
+#define IER_ADDRESS 0x00000004
+#define IER_OFFSET 0x00000004
+#define IER_EDDSI_MSB 3
+#define IER_EDDSI_LSB 3
+#define IER_EDDSI_MASK 0x00000008
+#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
+#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
+#define IER_ELSI_MSB 2
+#define IER_ELSI_LSB 2
+#define IER_ELSI_MASK 0x00000004
+#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
+#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
+#define IER_ETBEI_MSB 1
+#define IER_ETBEI_LSB 1
+#define IER_ETBEI_MASK 0x00000002
+#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
+#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
+#define IER_ERBFI_MSB 0
+#define IER_ERBFI_LSB 0
+#define IER_ERBFI_MASK 0x00000001
+#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
+#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
+
+#define IIR_ADDRESS 0x00000008
+#define IIR_OFFSET 0x00000008
+#define IIR_FIFO_STATUS_MSB 7
+#define IIR_FIFO_STATUS_LSB 6
+#define IIR_FIFO_STATUS_MASK 0x000000c0
+#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
+#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
+#define IIR_IID_MSB 3
+#define IIR_IID_LSB 0
+#define IIR_IID_MASK 0x0000000f
+#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
+#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
+
+#define FCR_ADDRESS 0x00000008
+#define FCR_OFFSET 0x00000008
+#define FCR_RCVR_TRIG_MSB 7
+#define FCR_RCVR_TRIG_LSB 6
+#define FCR_RCVR_TRIG_MASK 0x000000c0
+#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
+#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
+#define FCR_DMA_MODE_MSB 3
+#define FCR_DMA_MODE_LSB 3
+#define FCR_DMA_MODE_MASK 0x00000008
+#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
+#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
+#define FCR_XMIT_FIFO_RST_MSB 2
+#define FCR_XMIT_FIFO_RST_LSB 2
+#define FCR_XMIT_FIFO_RST_MASK 0x00000004
+#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
+#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
+#define FCR_RCVR_FIFO_RST_MSB 1
+#define FCR_RCVR_FIFO_RST_LSB 1
+#define FCR_RCVR_FIFO_RST_MASK 0x00000002
+#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
+#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
+#define FCR_FIFO_EN_MSB 0
+#define FCR_FIFO_EN_LSB 0
+#define FCR_FIFO_EN_MASK 0x00000001
+#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
+#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
+
+#define LCR_ADDRESS 0x0000000c
+#define LCR_OFFSET 0x0000000c
+#define LCR_DLAB_MSB 7
+#define LCR_DLAB_LSB 7
+#define LCR_DLAB_MASK 0x00000080
+#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
+#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
+#define LCR_BREAK_MSB 6
+#define LCR_BREAK_LSB 6
+#define LCR_BREAK_MASK 0x00000040
+#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
+#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
+#define LCR_EPS_MSB 4
+#define LCR_EPS_LSB 4
+#define LCR_EPS_MASK 0x00000010
+#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
+#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
+#define LCR_PEN_MSB 3
+#define LCR_PEN_LSB 3
+#define LCR_PEN_MASK 0x00000008
+#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
+#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
+#define LCR_STOP_MSB 2
+#define LCR_STOP_LSB 2
+#define LCR_STOP_MASK 0x00000004
+#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
+#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
+#define LCR_CLS_MSB 1
+#define LCR_CLS_LSB 0
+#define LCR_CLS_MASK 0x00000003
+#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
+#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
+
+#define MCR_ADDRESS 0x00000010
+#define MCR_OFFSET 0x00000010
+#define MCR_LOOPBACK_MSB 5
+#define MCR_LOOPBACK_LSB 5
+#define MCR_LOOPBACK_MASK 0x00000020
+#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
+#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
+#define MCR_OUT2_MSB 3
+#define MCR_OUT2_LSB 3
+#define MCR_OUT2_MASK 0x00000008
+#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
+#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
+#define MCR_OUT1_MSB 2
+#define MCR_OUT1_LSB 2
+#define MCR_OUT1_MASK 0x00000004
+#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
+#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
+#define MCR_RTS_MSB 1
+#define MCR_RTS_LSB 1
+#define MCR_RTS_MASK 0x00000002
+#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
+#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
+#define MCR_DTR_MSB 0
+#define MCR_DTR_LSB 0
+#define MCR_DTR_MASK 0x00000001
+#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
+#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
+
+#define LSR_ADDRESS 0x00000014
+#define LSR_OFFSET 0x00000014
+#define LSR_FERR_MSB 7
+#define LSR_FERR_LSB 7
+#define LSR_FERR_MASK 0x00000080
+#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
+#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
+#define LSR_TEMT_MSB 6
+#define LSR_TEMT_LSB 6
+#define LSR_TEMT_MASK 0x00000040
+#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
+#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
+#define LSR_THRE_MSB 5
+#define LSR_THRE_LSB 5
+#define LSR_THRE_MASK 0x00000020
+#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
+#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
+#define LSR_BI_MSB 4
+#define LSR_BI_LSB 4
+#define LSR_BI_MASK 0x00000010
+#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
+#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
+#define LSR_FE_MSB 3
+#define LSR_FE_LSB 3
+#define LSR_FE_MASK 0x00000008
+#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
+#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
+#define LSR_PE_MSB 2
+#define LSR_PE_LSB 2
+#define LSR_PE_MASK 0x00000004
+#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
+#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
+#define LSR_OE_MSB 1
+#define LSR_OE_LSB 1
+#define LSR_OE_MASK 0x00000002
+#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
+#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
+#define LSR_DR_MSB 0
+#define LSR_DR_LSB 0
+#define LSR_DR_MASK 0x00000001
+#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
+#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
+
+#define MSR_ADDRESS 0x00000018
+#define MSR_OFFSET 0x00000018
+#define MSR_DCD_MSB 7
+#define MSR_DCD_LSB 7
+#define MSR_DCD_MASK 0x00000080
+#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
+#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
+#define MSR_RI_MSB 6
+#define MSR_RI_LSB 6
+#define MSR_RI_MASK 0x00000040
+#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
+#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
+#define MSR_DSR_MSB 5
+#define MSR_DSR_LSB 5
+#define MSR_DSR_MASK 0x00000020
+#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
+#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
+#define MSR_CTS_MSB 4
+#define MSR_CTS_LSB 4
+#define MSR_CTS_MASK 0x00000010
+#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
+#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
+#define MSR_DDCD_MSB 3
+#define MSR_DDCD_LSB 3
+#define MSR_DDCD_MASK 0x00000008
+#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
+#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
+#define MSR_TERI_MSB 2
+#define MSR_TERI_LSB 2
+#define MSR_TERI_MASK 0x00000004
+#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
+#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
+#define MSR_DDSR_MSB 1
+#define MSR_DDSR_LSB 1
+#define MSR_DDSR_MASK 0x00000002
+#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
+#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
+#define MSR_DCTS_MSB 0
+#define MSR_DCTS_LSB 0
+#define MSR_DCTS_MASK 0x00000001
+#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
+#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
+
+#define SCR_ADDRESS 0x0000001c
+#define SCR_OFFSET 0x0000001c
+#define SCR_SCR_MSB 7
+#define SCR_SCR_LSB 0
+#define SCR_SCR_MASK 0x000000ff
+#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
+#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
+
+#define SRBR_ADDRESS 0x00000020
+#define SRBR_OFFSET 0x00000020
+#define SRBR_SRBR_MSB 7
+#define SRBR_SRBR_LSB 0
+#define SRBR_SRBR_MASK 0x000000ff
+#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
+#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
+
+#define SIIR_ADDRESS 0x00000028
+#define SIIR_OFFSET 0x00000028
+#define SIIR_SIIR_MSB 7
+#define SIIR_SIIR_LSB 0
+#define SIIR_SIIR_MASK 0x000000ff
+#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
+#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
+
+#define MWR_ADDRESS 0x0000002c
+#define MWR_OFFSET 0x0000002c
+#define MWR_MWR_MSB 31
+#define MWR_MWR_LSB 0
+#define MWR_MWR_MASK 0xffffffff
+#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
+#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
+
+#define SLSR_ADDRESS 0x00000034
+#define SLSR_OFFSET 0x00000034
+#define SLSR_SLSR_MSB 7
+#define SLSR_SLSR_LSB 0
+#define SLSR_SLSR_MASK 0x000000ff
+#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
+#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
+
+#define SMSR_ADDRESS 0x00000038
+#define SMSR_OFFSET 0x00000038
+#define SMSR_SMSR_MSB 7
+#define SMSR_SMSR_LSB 0
+#define SMSR_SMSR_MASK 0x000000ff
+#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
+#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
+
+#define MRR_ADDRESS 0x0000003c
+#define MRR_OFFSET 0x0000003c
+#define MRR_MRR_MSB 31
+#define MRR_MRR_LSB 0
+#define MRR_MRR_MASK 0xffffffff
+#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
+#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+ volatile unsigned int rbr;
+ volatile unsigned int dlh;
+ volatile unsigned int iir;
+ volatile unsigned int lcr;
+ volatile unsigned int mcr;
+ volatile unsigned int lsr;
+ volatile unsigned int msr;
+ volatile unsigned int scr;
+ volatile unsigned int srbr;
+ unsigned char pad0[4]; /* pad to 0x28 */
+ volatile unsigned int siir;
+ volatile unsigned int mwr;
+ unsigned char pad1[4]; /* pad to 0x34 */
+ volatile unsigned int slsr;
+ volatile unsigned int smsr;
+ volatile unsigned int mrr;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h
new file mode 100644
index 000000000000..0c15ebfaeaa6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h
@@ -0,0 +1,95 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_REG_REG_H_
+#define _VMC_REG_REG_H_
+
+#define MC_TCAM_VALID_ADDRESS 0x00000000
+#define MC_TCAM_VALID_OFFSET 0x00000000
+#define MC_TCAM_VALID_BIT_MSB 0
+#define MC_TCAM_VALID_BIT_LSB 0
+#define MC_TCAM_VALID_BIT_MASK 0x00000001
+#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
+#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
+
+#define MC_TCAM_MASK_ADDRESS 0x00000080
+#define MC_TCAM_MASK_OFFSET 0x00000080
+#define MC_TCAM_MASK_SIZE_MSB 2
+#define MC_TCAM_MASK_SIZE_LSB 0
+#define MC_TCAM_MASK_SIZE_MASK 0x00000007
+#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
+#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
+
+#define MC_TCAM_COMPARE_ADDRESS 0x00000100
+#define MC_TCAM_COMPARE_OFFSET 0x00000100
+#define MC_TCAM_COMPARE_KEY_MSB 21
+#define MC_TCAM_COMPARE_KEY_LSB 5
+#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0
+#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
+#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
+
+#define MC_TCAM_TARGET_ADDRESS 0x00000180
+#define MC_TCAM_TARGET_OFFSET 0x00000180
+#define MC_TCAM_TARGET_ADDR_MSB 21
+#define MC_TCAM_TARGET_ADDR_LSB 5
+#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0
+#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
+#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
+
+#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200
+#define ADDR_ERROR_CONTROL_OFFSET 0x00000200
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define ADDR_ERROR_CONTROL_ENABLE_MSB 0
+#define ADDR_ERROR_CONTROL_ENABLE_LSB 0
+#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
+#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define ADDR_ERROR_STATUS_ADDRESS 0x00000204
+#define ADDR_ERROR_STATUS_OFFSET 0x00000204
+#define ADDR_ERROR_STATUS_WRITE_MSB 25
+#define ADDR_ERROR_STATUS_WRITE_LSB 25
+#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
+#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
+#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
+#define ADDR_ERROR_STATUS_ADDRESS_MSB 24
+#define ADDR_ERROR_STATUS_ADDRESS_LSB 0
+#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
+#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_reg_reg_s {
+ volatile unsigned int mc_tcam_valid[32];
+ volatile unsigned int mc_tcam_mask[32];
+ volatile unsigned int mc_tcam_compare[32];
+ volatile unsigned int mc_tcam_target[32];
+ volatile unsigned int addr_error_control;
+ volatile unsigned int addr_error_status;
+} vmc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h
new file mode 100644
index 000000000000..20194688df1d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h
@@ -0,0 +1,3287 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc. All rights reserved */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
+
+
+#ifndef _ANALOG_INTF_ARES_REG_REG_H_
+#define _ANALOG_INTF_ARES_REG_REG_H_
+
+
+/* macros for RXRF_BIAS1 */
+#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_BIAS2 */
+#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB 10
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB 8
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK 0x00000700
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB 13
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB 11
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK 0x00003800
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB 16
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB 14
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK 0x0001c000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB 19
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB 17
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK 0x000e0000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB 22
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB 20
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK 0x00700000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB 25
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB 23
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK 0x03800000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for RXRF_GAINSTAGES */
+#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_AGC */
+#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c
+#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c
+#define PHY_ANALOG_RXRF_AGC_SPARE_MSB 5
+#define PHY_ANALOG_RXRF_AGC_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_AGC_SPARE_MASK 0x0000003f
+#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF1 */
+#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040
+#define PHY_ANALOG_TXRF1_OFFSET 0x00000040
+#define PHY_ANALOG_TXRF1_DCAS2G_MSB 2
+#define PHY_ANALOG_TXRF1_DCAS2G_LSB 0
+#define PHY_ANALOG_TXRF1_DCAS2G_MASK 0x00000007
+#define PHY_ANALOG_TXRF1_DCAS2G_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF1_DCAS2G_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB 5
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB 3
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK 0x00000038
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB 8
+#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB 6
+#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK 0x000001c0
+#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x) (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x) (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB 11
+#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB 9
+#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK 0x00000e00
+#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x) (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB 14
+#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB 12
+#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK 0x00007000
+#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x) (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x) (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF1_DB2G_MSB 17
+#define PHY_ANALOG_TXRF1_DB2G_LSB 15
+#define PHY_ANALOG_TXRF1_DB2G_MASK 0x00038000
+#define PHY_ANALOG_TXRF1_DB2G_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF1_DB2G_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 18
+#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 18
+#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00040000
+#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TXRF1_PDDR2G_MSB 19
+#define PHY_ANALOG_TXRF1_PDDR2G_LSB 19
+#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00080000
+#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 20
+#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 20
+#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00100000
+#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF1_PDLO2G_MSB 21
+#define PHY_ANALOG_TXRF1_PDLO2G_LSB 21
+#define PHY_ANALOG_TXRF1_PDLO2G_MASK 0x00200000
+#define PHY_ANALOG_TXRF1_PDLO2G_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF1_PDLO2G_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30
+#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000
+#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF2 */
+#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044
+#define PHY_ANALOG_TXRF2_OFFSET 0x00000044
+#define PHY_ANALOG_TXRF2_SPARE2_MSB 0
+#define PHY_ANALOG_TXRF2_SPARE2_LSB 0
+#define PHY_ANALOG_TXRF2_SPARE2_MASK 0x00000001
+#define PHY_ANALOG_TXRF2_SPARE2_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF2_SPARE2_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF2_D3B5G_MSB 3
+#define PHY_ANALOG_TXRF2_D3B5G_LSB 1
+#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x0000000e
+#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_TXRF2_D4B5G_MSB 6
+#define PHY_ANALOG_TXRF2_D4B5G_LSB 4
+#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000070
+#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 10
+#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 7
+#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x00000780
+#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x00000780) >> 7)
+#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 7) & 0x00000780)
+#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 11
+#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 11
+#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x00000800
+#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB 12
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB 12
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK 0x00001000
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB 13
+#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB 13
+#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK 0x00002000
+#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB 14
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB 14
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK 0x00004000
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB 15
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB 15
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK 0x00008000
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB 19
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB 16
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK 0x000f0000
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB 23
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB 20
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK 0x00f00000
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x) (((x) & 0x00f00000) >> 20)
+#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x) (((x) << 20) & 0x00f00000)
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB 27
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB 24
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK 0x0f000000
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x) (((x) & 0x0f000000) >> 24)
+#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x) (((x) << 24) & 0x0f000000)
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB 28
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB 28
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK 0x10000000
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TXRF2_OCAS2G_MSB 31
+#define PHY_ANALOG_TXRF2_OCAS2G_LSB 29
+#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF3 */
+#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048
+#define PHY_ANALOG_TXRF3_OFFSET 0x00000048
+#define PHY_ANALOG_TXRF3_SPARE3_MSB 22
+#define PHY_ANALOG_TXRF3_SPARE3_LSB 0
+#define PHY_ANALOG_TXRF3_SPARE3_MASK 0x007fffff
+#define PHY_ANALOG_TXRF3_SPARE3_GET(x) (((x) & 0x007fffff) >> 0)
+#define PHY_ANALOG_TXRF3_SPARE3_SET(x) (((x) << 0) & 0x007fffff)
+#define PHY_ANALOG_TXRF3_CAS5G_MSB 25
+#define PHY_ANALOG_TXRF3_CAS5G_LSB 23
+#define PHY_ANALOG_TXRF3_CAS5G_MASK 0x03800000
+#define PHY_ANALOG_TXRF3_CAS5G_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF3_CAS5G_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF3_OB5G_MSB 28
+#define PHY_ANALOG_TXRF3_OB5G_LSB 26
+#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000
+#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF3_D2B5G_MSB 31
+#define PHY_ANALOG_TXRF3_D2B5G_LSB 29
+#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF4 */
+#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c
+#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 2
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 0
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x00000007
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 5
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 3
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x00000038
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 8
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 6
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x000001c0
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 11
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 9
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x00000e00
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 14
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 12
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x00007000
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 17
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 15
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0x00038000
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF4_FILTR2G_MSB 19
+#define PHY_ANALOG_TXRF4_FILTR2G_LSB 18
+#define PHY_ANALOG_TXRF4_FILTR2G_MASK 0x000c0000
+#define PHY_ANALOG_TXRF4_FILTR2G_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_TXRF4_FILTR2G_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB 20
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB 20
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK 0x00100000
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB 21
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB 21
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK 0x00200000
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF4_PDFB2G_MSB 22
+#define PHY_ANALOG_TXRF4_PDFB2G_LSB 22
+#define PHY_ANALOG_TXRF4_PDFB2G_MASK 0x00400000
+#define PHY_ANALOG_TXRF4_PDFB2G_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF4_PDFB2G_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF4_RDIV5G_MSB 24
+#define PHY_ANALOG_TXRF4_RDIV5G_LSB 23
+#define PHY_ANALOG_TXRF4_RDIV5G_MASK 0x01800000
+#define PHY_ANALOG_TXRF4_RDIV5G_GET(x) (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_TXRF4_RDIV5G_SET(x) (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB 27
+#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB 25
+#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK 0x0e000000
+#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x) (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x) (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB 28
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB 28
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK 0x10000000
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TXRF4_RDIV2G_MSB 30
+#define PHY_ANALOG_TXRF4_RDIV2G_LSB 29
+#define PHY_ANALOG_TXRF4_RDIV2G_MASK 0x60000000
+#define PHY_ANALOG_TXRF4_RDIV2G_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_TXRF4_RDIV2G_SET(x) (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB 31
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB 31
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK 0x80000000
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF5 */
+#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050
+#define PHY_ANALOG_TXRF5_OFFSET 0x00000050
+#define PHY_ANALOG_TXRF5_FBHI2G_MSB 0
+#define PHY_ANALOG_TXRF5_FBHI2G_LSB 0
+#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000001
+#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF5_FBLO2G_MSB 1
+#define PHY_ANALOG_TXRF5_FBLO2G_LSB 1
+#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000002
+#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF5_REFHI2G_MSB 4
+#define PHY_ANALOG_TXRF5_REFHI2G_LSB 2
+#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0000001c
+#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF5_REFLO2G_MSB 7
+#define PHY_ANALOG_TXRF5_REFLO2G_LSB 5
+#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000000e0
+#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 9
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 8
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00000300
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 11
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 10
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x00000c00
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x00000c00) >> 10)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 10) & 0x00000c00)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 13
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 12
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x00003000
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 15
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 14
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x0000c000
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 17
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 16
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0x00030000
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB 19
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB 18
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK 0x000c0000
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB 22
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB 20
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK 0x00700000
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB 25
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB 23
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK 0x03800000
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB 28
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB 26
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK 0x1c000000
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB 31
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB 29
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK 0xe0000000
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF6 */
+#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054
+#define PHY_ANALOG_TXRF6_OFFSET 0x00000054
+#define PHY_ANALOG_TXRF6_SPARE6_MSB 0
+#define PHY_ANALOG_TXRF6_SPARE6_LSB 0
+#define PHY_ANALOG_TXRF6_SPARE6_MASK 0x00000001
+#define PHY_ANALOG_TXRF6_SPARE6_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF6_SPARE6_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB 1
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB 1
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK 0x00000002
+#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB 7
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB 2
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK 0x000000fc
+#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 10
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 8
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00000700
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 11
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 11
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00000800
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 15
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 12
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x0000f000
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 18
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 16
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x00070000
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 21
+#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 19
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x00380000
+#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 22
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 22
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x00400000
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB 23
+#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB 23
+#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK 0x00800000
+#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF6_OFFSET2G_MSB 30
+#define PHY_ANALOG_TXRF6_OFFSET2G_LSB 24
+#define PHY_ANALOG_TXRF6_OFFSET2G_MASK 0x7f000000
+#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x) (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB 31
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB 31
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK 0x80000000
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF7 */
+#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058
+#define PHY_ANALOG_TXRF7_OFFSET 0x00000058
+#define PHY_ANALOG_TXRF7_SPARE7_MSB 1
+#define PHY_ANALOG_TXRF7_SPARE7_LSB 0
+#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003
+#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF8 */
+#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c
+#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c
+#define PHY_ANALOG_TXRF8_SPARE8_MSB 1
+#define PHY_ANALOG_TXRF8_SPARE8_LSB 0
+#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003
+#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF9 */
+#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060
+#define PHY_ANALOG_TXRF9_OFFSET 0x00000060
+#define PHY_ANALOG_TXRF9_SPARE9_MSB 1
+#define PHY_ANALOG_TXRF9_SPARE9_LSB 0
+#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003
+#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF10 */
+#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064
+#define PHY_ANALOG_TXRF10_OFFSET 0x00000064
+#define PHY_ANALOG_TXRF10_SPARE10_MSB 12
+#define PHY_ANALOG_TXRF10_SPARE10_LSB 0
+#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00001fff
+#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00001fff) >> 0)
+#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00001fff)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 13
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 13
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00002000
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 16
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 14
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x0001c000
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 19
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 17
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x000e0000
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 26
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 20
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x07f00000
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x07f00000) >> 20)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 20) & 0x07f00000)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 29
+#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 27
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x38000000
+#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 30
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 30
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x40000000
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 31
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 31
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x80000000
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF11 */
+#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068
+#define PHY_ANALOG_TXRF11_OFFSET 0x00000068
+#define PHY_ANALOG_TXRF11_SPARE11_MSB 1
+#define PHY_ANALOG_TXRF11_SPARE11_LSB 0
+#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003
+#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB 4
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB 2
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK 0x0000001c
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 7
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 5
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x000000e0
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 10
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 8
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x00000700
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 13
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 11
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00003800
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 16
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 14
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x0001c000
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 19
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 17
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x000e0000
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF12 */
+#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c
+#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c
+#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7
+#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0
+#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff
+#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 15
+#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8
+#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x0000ff00
+#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 19
+#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 16
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x000f0000
+#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 22
+#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 20
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x00700000
+#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 25
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 23
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x03800000
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 28
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 26
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x1c000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 31
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 29
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0xe0000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH1 */
+#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080
+#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15
+#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000
+#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000
+#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30
+#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30
+#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000
+#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH2 */
+#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084
+#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB 15
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB 12
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK 0x0000f000
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB 16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB 16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK 0x00010000
+#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH2_CPBIAS_MSB 19
+#define PHY_ANALOG_SYNTH2_CPBIAS_LSB 18
+#define PHY_ANALOG_SYNTH2_CPBIAS_MASK 0x000c0000
+#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH3 */
+#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088
+#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH4 */
+#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c
+#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB 7
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB 6
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK 0x000000c0
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100
+#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12
+#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800
+#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH5 */
+#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090
+#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1
+#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003
+#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_SYNTH5_SPARE5A_MSB 31
+#define PHY_ANALOG_SYNTH5_SPARE5A_LSB 30
+#define PHY_ANALOG_SYNTH5_SPARE5A_MASK 0xc0000000
+#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for SYNTH6 */
+#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094
+#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8
+#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc
+#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2)
+#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9
+#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9
+#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200
+#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400
+#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000
+#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000
+#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15
+#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15
+#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000
+#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24
+#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24
+#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000
+#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31)
+
+/* macros for SYNTH7 */
+#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098
+#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18
+#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc
+#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc)
+#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27
+#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19
+#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000
+#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19)
+#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30
+#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30
+#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000
+#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH8 */
+#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c
+#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31
+#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27
+#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH9 */
+#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0
+#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31
+#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27
+#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH10 */
+#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4
+#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4
+#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 0
+#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0
+#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000001
+#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 3
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 1
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000000e
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB 4
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB 4
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK 0x00000010
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH11 */
+#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8
+#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8
+#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4
+#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0
+#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f
+#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7
+#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0
+#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH12 */
+#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac
+#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac
+#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 17
+#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0
+#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x0003ffff
+#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x0003ffff)
+#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18
+#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18
+#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000
+#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22
+#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000
+#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26
+#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000
+#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30
+#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000
+#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BIAS1 */
+#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0
+#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0
+#define PHY_ANALOG_BIAS1_SPARE1_MSB 6
+#define PHY_ANALOG_BIAS1_SPARE1_LSB 0
+#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f
+#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31
+#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000
+#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000)
+
+/* macros for BIAS2 */
+#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4
+#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4
+#define PHY_ANALOG_BIAS2_SPARE2_MSB 4
+#define PHY_ANALOG_BIAS2_SPARE2_LSB 0
+#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f
+#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB 7
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB 5
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK 0x000000e0
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB 19
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB 17
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK 0x000e0000
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS3 */
+#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8
+#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8
+#define PHY_ANALOG_BIAS3_SPARE3_MSB 1
+#define PHY_ANALOG_BIAS3_SPARE3_LSB 0
+#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003
+#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB 4
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB 2
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK 0x0000001c
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB 13
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB 11
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK 0x00003800
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS4 */
+#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc
+#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc
+#define PHY_ANALOG_BIAS4_SPARE4_MSB 13
+#define PHY_ANALOG_BIAS4_SPARE4_LSB 0
+#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x00003fff
+#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB 22
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB 20
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK 0x00700000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX1 */
+#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100
+#define PHY_ANALOG_RXTX1_OFFSET 0x00000100
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002
+#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18
+#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15
+#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000
+#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30
+#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27
+#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000
+#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000
+#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for RXTX2 */
+#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104
+#define PHY_ANALOG_RXTX2_OFFSET 0x00000104
+#define PHY_ANALOG_RXTX2_BMODE_MSB 0
+#define PHY_ANALOG_RXTX2_BMODE_LSB 0
+#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001
+#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002
+#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2
+#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2
+#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004
+#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX2_BW_ST_MSB 5
+#define PHY_ANALOG_RXTX2_BW_ST_LSB 4
+#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030
+#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX2_TXON_MSB 7
+#define PHY_ANALOG_RXTX2_TXON_LSB 7
+#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080
+#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8
+#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8
+#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100
+#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX2_PAON_MSB 9
+#define PHY_ANALOG_RXTX2_PAON_LSB 9
+#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200
+#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10
+#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10
+#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400
+#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX2_RXON_MSB 11
+#define PHY_ANALOG_RXTX2_RXON_LSB 11
+#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800
+#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12
+#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12
+#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000
+#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RXTX2_AGCON_MSB 13
+#define PHY_ANALOG_RXTX2_AGCON_LSB 13
+#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000
+#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000
+#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX2_TXMOD_MSB 17
+#define PHY_ANALOG_RXTX2_TXMOD_LSB 15
+#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000
+#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25
+#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24
+#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000
+#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28
+#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26
+#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000
+#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31
+#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29
+#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000
+#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX3 */
+#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108
+#define PHY_ANALOG_RXTX3_OFFSET 0x00000108
+#define PHY_ANALOG_RXTX3_SPARE3_MSB 2
+#define PHY_ANALOG_RXTX3_SPARE3_LSB 0
+#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007
+#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 3
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 3
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000008
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX3_DACRSTB_MSB 4
+#define PHY_ANALOG_RXTX3_DACRSTB_LSB 4
+#define PHY_ANALOG_RXTX3_DACRSTB_MASK 0x00000010
+#define PHY_ANALOG_RXTX3_DACRSTB_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXTX3_DACRSTB_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB 5
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB 5
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK 0x00000020
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6
+#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6
+#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040
+#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX3_DACPWD_MSB 7
+#define PHY_ANALOG_RXTX3_DACPWD_LSB 7
+#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080
+#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9
+#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9
+#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200
+#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800)
+#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17
+#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17
+#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000
+#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000
+#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_RXTX3_CALFC_MSB 22
+#define PHY_ANALOG_RXTX3_CALFC_LSB 22
+#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000
+#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000
+#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_RXTX3_CALTX_MSB 24
+#define PHY_ANALOG_RXTX3_CALTX_LSB 24
+#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000
+#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000
+#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_RXTX3_CALPA_MSB 28
+#define PHY_ANALOG_RXTX3_CALPA_LSB 28
+#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000
+#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000
+#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXTX3_SPURON_MSB 30
+#define PHY_ANALOG_RXTX3_SPURON_LSB 30
+#define PHY_ANALOG_RXTX3_SPURON_MASK 0x40000000
+#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB 31
+#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB 31
+#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK 0x80000000
+#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB1 */
+#define PHY_ANALOG_BB1_ADDRESS 0x00000140
+#define PHY_ANALOG_BB1_OFFSET 0x00000140
+#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0
+#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0
+#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001
+#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002
+#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2
+#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2
+#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004
+#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010
+#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100
+#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9
+#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9
+#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200
+#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10
+#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10
+#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400
+#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11
+#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11
+#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800
+#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12
+#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12
+#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000
+#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_BB1_CMSEL_MSB 15
+#define PHY_ANALOG_BB1_CMSEL_LSB 13
+#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000
+#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BB1_ATBSEL_MSB 17
+#define PHY_ANALOG_BB1_ATBSEL_LSB 16
+#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000
+#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000)
+#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29
+#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29
+#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000
+#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31
+#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000
+#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for BB2 */
+#define PHY_ANALOG_BB2_ADDRESS 0x00000144
+#define PHY_ANALOG_BB2_OFFSET 0x00000144
+#define PHY_ANALOG_BB2_SPARE_MSB 6
+#define PHY_ANALOG_BB2_SPARE_LSB 0
+#define PHY_ANALOG_BB2_SPARE_MASK 0x0000007f
+#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BB2_SEL_TEST_MSB 9
+#define PHY_ANALOG_BB2_SEL_TEST_LSB 7
+#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000380
+#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BB2_SCFIR_CAP_MSB 14
+#define PHY_ANALOG_BB2_SCFIR_CAP_LSB 10
+#define PHY_ANALOG_BB2_SCFIR_CAP_MASK 0x00007c00
+#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB 15
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB 15
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK 0x00008000
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_BB2_FNOTCH_MSB 19
+#define PHY_ANALOG_BB2_FNOTCH_LSB 16
+#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000
+#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_BB2_FILTERFC_MSB 25
+#define PHY_ANALOG_BB2_FILTERFC_LSB 21
+#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000
+#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TOP1 */
+#define PHY_ANALOG_TOP1_ADDRESS 0x00000280
+#define PHY_ANALOG_TOP1_OFFSET 0x00000280
+#define PHY_ANALOG_TOP1_SEL_KVCO_MSB 1
+#define PHY_ANALOG_TOP1_SEL_KVCO_LSB 0
+#define PHY_ANALOG_TOP1_SEL_KVCO_MASK 0x00000003
+#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TOP1_PLLATB_MSB 3
+#define PHY_ANALOG_TOP1_PLLATB_LSB 2
+#define PHY_ANALOG_TOP1_PLLATB_MASK 0x0000000c
+#define PHY_ANALOG_TOP1_PLLATB_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_TOP1_PLLATB_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_TOP1_PLL_SVREG_MSB 4
+#define PHY_ANALOG_TOP1_PLL_SVREG_LSB 4
+#define PHY_ANALOG_TOP1_PLL_SVREG_MASK 0x00000010
+#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB 5
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB 5
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK 0x00000020
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP1_PWDPLL_MSB 6
+#define PHY_ANALOG_TOP1_PWDPLL_LSB 6
+#define PHY_ANALOG_TOP1_PWDPLL_MASK 0x00000040
+#define PHY_ANALOG_TOP1_PWDPLL_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP1_PWDPLL_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB 7
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB 7
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK 0x00000080
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB 9
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB 8
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK 0x00000300
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB 11
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB 10
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK 0x00000c00
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x) (((x) & 0x00000c00) >> 10)
+#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x) (((x) << 10) & 0x00000c00)
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB 13
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB 12
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK 0x00003000
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x) (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x) (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB 15
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB 14
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK 0x0000c000
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TOP1_REFDIV_MSB 19
+#define PHY_ANALOG_TOP1_REFDIV_LSB 16
+#define PHY_ANALOG_TOP1_REFDIV_MASK 0x000f0000
+#define PHY_ANALOG_TOP1_REFDIV_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TOP1_REFDIV_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TOP1_DIV_MSB 29
+#define PHY_ANALOG_TOP1_DIV_LSB 20
+#define PHY_ANALOG_TOP1_DIV_MASK 0x3ff00000
+#define PHY_ANALOG_TOP1_DIV_GET(x) (((x) & 0x3ff00000) >> 20)
+#define PHY_ANALOG_TOP1_DIV_SET(x) (((x) << 20) & 0x3ff00000)
+#define PHY_ANALOG_TOP1_PLLBYPASS_MSB 30
+#define PHY_ANALOG_TOP1_PLLBYPASS_LSB 30
+#define PHY_ANALOG_TOP1_PLLBYPASS_MASK 0x40000000
+#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB 31
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB 31
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK 0x80000000
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TOP2 */
+#define PHY_ANALOG_TOP2_ADDRESS 0x00000284
+#define PHY_ANALOG_TOP2_OFFSET 0x00000284
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB 0
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB 0
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK 0x00000001
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TOP2_PLL_LEAK_MSB 4
+#define PHY_ANALOG_TOP2_PLL_LEAK_LSB 1
+#define PHY_ANALOG_TOP2_PLL_LEAK_MASK 0x0000001e
+#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x) (((x) & 0x0000001e) >> 1)
+#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x) (((x) << 1) & 0x0000001e)
+#define PHY_ANALOG_TOP2_PLLFRAC_MSB 19
+#define PHY_ANALOG_TOP2_PLLFRAC_LSB 5
+#define PHY_ANALOG_TOP2_PLLFRAC_MASK 0x000fffe0
+#define PHY_ANALOG_TOP2_PLLFRAC_GET(x) (((x) & 0x000fffe0) >> 5)
+#define PHY_ANALOG_TOP2_PLLFRAC_SET(x) (((x) << 5) & 0x000fffe0)
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB 20
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB 20
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK 0x00100000
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP2_PLLICP_MSB 23
+#define PHY_ANALOG_TOP2_PLLICP_LSB 21
+#define PHY_ANALOG_TOP2_PLLICP_MASK 0x00e00000
+#define PHY_ANALOG_TOP2_PLLICP_GET(x) (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_TOP2_PLLICP_SET(x) (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_TOP2_PLLFILTER_MSB 31
+#define PHY_ANALOG_TOP2_PLLFILTER_LSB 24
+#define PHY_ANALOG_TOP2_PLLFILTER_MASK 0xff000000
+#define PHY_ANALOG_TOP2_PLLFILTER_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_ANALOG_TOP2_PLLFILTER_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for TOP3 */
+#define PHY_ANALOG_TOP3_ADDRESS 0x00000288
+#define PHY_ANALOG_TOP3_OFFSET 0x00000288
+#define PHY_ANALOG_TOP3_INT2GND_MSB 0
+#define PHY_ANALOG_TOP3_INT2GND_LSB 0
+#define PHY_ANALOG_TOP3_INT2GND_MASK 0x00000001
+#define PHY_ANALOG_TOP3_INT2GND_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TOP3_INT2GND_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TOP3_PWDPALCLK_MSB 1
+#define PHY_ANALOG_TOP3_PWDPALCLK_LSB 1
+#define PHY_ANALOG_TOP3_PWDPALCLK_MASK 0x00000002
+#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB 2
+#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB 2
+#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK 0x00000004
+#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TOP3_PWDV2I_MSB 3
+#define PHY_ANALOG_TOP3_PWDV2I_LSB 3
+#define PHY_ANALOG_TOP3_PWDV2I_MASK 0x00000008
+#define PHY_ANALOG_TOP3_PWDV2I_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TOP3_PWDV2I_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TOP3_PWDBIAS_MSB 4
+#define PHY_ANALOG_TOP3_PWDBIAS_LSB 4
+#define PHY_ANALOG_TOP3_PWDBIAS_MASK 0x00000010
+#define PHY_ANALOG_TOP3_PWDBIAS_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP3_PWDBIAS_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP3_PWDBG_MSB 5
+#define PHY_ANALOG_TOP3_PWDBG_LSB 5
+#define PHY_ANALOG_TOP3_PWDBG_MASK 0x00000020
+#define PHY_ANALOG_TOP3_PWDBG_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP3_PWDBG_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB 6
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB 6
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK 0x00000040
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB 7
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB 7
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK 0x00000080
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB 8
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB 8
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK 0x00000100
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB 9
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB 9
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK 0x00000200
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB 10
+#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB 10
+#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK 0x00000400
+#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB 11
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB 11
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK 0x00000800
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB 12
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB 12
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK 0x00001000
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB 13
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB 13
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK 0x00002000
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB 15
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB 14
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK 0x0000c000
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB 22
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB 16
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK 0x007f0000
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16)
+#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000)
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB 29
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB 23
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK 0x3f800000
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23)
+#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000)
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB 30
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB 30
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK 0x40000000
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP3_TCXODET_MSB 31
+#define PHY_ANALOG_TOP3_TCXODET_LSB 31
+#define PHY_ANALOG_TOP3_TCXODET_MASK 0x80000000
+#define PHY_ANALOG_TOP3_TCXODET_GET(x) (((x) & 0x80000000) >> 31)
+
+/* macros for TOP4 */
+#define PHY_ANALOG_TOP4_ADDRESS 0x0000028c
+#define PHY_ANALOG_TOP4_OFFSET 0x0000028c
+#define PHY_ANALOG_TOP4_SPARE4_MSB 19
+#define PHY_ANALOG_TOP4_SPARE4_LSB 0
+#define PHY_ANALOG_TOP4_SPARE4_MASK 0x000fffff
+#define PHY_ANALOG_TOP4_SPARE4_GET(x) (((x) & 0x000fffff) >> 0)
+#define PHY_ANALOG_TOP4_SPARE4_SET(x) (((x) << 0) & 0x000fffff)
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB 20
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB 20
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK 0x00100000
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB 21
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB 21
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK 0x00200000
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB 22
+#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB 22
+#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK 0x00400000
+#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB 23
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB 23
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK 0x00800000
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB 24
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB 24
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK 0x01000000
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB 25
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB 25
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK 0x02000000
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB 26
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB 26
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK 0x04000000
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_TOP4_ENBTCLK_MSB 27
+#define PHY_ANALOG_TOP4_ENBTCLK_LSB 27
+#define PHY_ANALOG_TOP4_ENBTCLK_MASK 0x08000000
+#define PHY_ANALOG_TOP4_ENBTCLK_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_TOP4_ENBTCLK_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_TOP4_PAD2GND_MSB 28
+#define PHY_ANALOG_TOP4_PAD2GND_LSB 28
+#define PHY_ANALOG_TOP4_PAD2GND_MASK 0x10000000
+#define PHY_ANALOG_TOP4_PAD2GND_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TOP4_PAD2GND_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TOP4_INTH2PAD_MSB 29
+#define PHY_ANALOG_TOP4_INTH2PAD_LSB 29
+#define PHY_ANALOG_TOP4_INTH2PAD_MASK 0x20000000
+#define PHY_ANALOG_TOP4_INTH2PAD_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_TOP4_INTH2PAD_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_TOP4_INTH2GND_MSB 30
+#define PHY_ANALOG_TOP4_INTH2GND_LSB 30
+#define PHY_ANALOG_TOP4_INTH2GND_MASK 0x40000000
+#define PHY_ANALOG_TOP4_INTH2GND_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_TOP4_INTH2GND_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_TOP4_INT2PAD_MSB 31
+#define PHY_ANALOG_TOP4_INT2PAD_LSB 31
+#define PHY_ANALOG_TOP4_INT2PAD_MASK 0x80000000
+#define PHY_ANALOG_TOP4_INT2PAD_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TOP4_INT2PAD_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for rbist_cntrl */
+#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000)
+
+/* macros for tx_dc_offset */
+#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000)
+
+/* macros for tx_tonegen0 */
+#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for tx_tonegen1 */
+#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for tx_lftonegen0 */
+#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for tx_linear_ramp_i */
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for tx_linear_ramp_q */
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for tx_prbs_mag */
+#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000)
+
+/* macros for tx_prbs_seed_i */
+#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
+
+/* macros for tx_prbs_seed_q */
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
+
+/* macros for cmac_dc_cancel */
+#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000)
+
+/* macros for cmac_dc_offset */
+#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_corr */
+#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00)
+
+/* macros for cmac_power */
+#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_cross_corr */
+#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_i2q2 */
+#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_power_hpf */
+#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0)
+
+/* macros for rxdac_set1 */
+#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000)
+
+/* macros for rxdac_set2 */
+#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000)
+
+/* macros for rxdac_long_shift */
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00)
+
+/* macros for cmac_results_i */
+#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for cmac_results_q */
+#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for PMU1 */
+#define PHY_ANALOG_PMU1_ADDRESS 0x00000740
+#define PHY_ANALOG_PMU1_OFFSET 0x00000740
+#define PHY_ANALOG_PMU1_SPARE_MSB 10
+#define PHY_ANALOG_PMU1_SPARE_LSB 0
+#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff
+#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000
+#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14
+#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14
+#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000
+#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000
+#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000
+#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for PMU2 */
+#define PHY_ANALOG_PMU2_ADDRESS 0x00000744
+#define PHY_ANALOG_PMU2_OFFSET 0x00000744
+#define PHY_ANALOG_PMU2_SPARE_MSB 7
+#define PHY_ANALOG_PMU2_SPARE_LSB 0
+#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff
+#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27
+#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25
+#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000
+#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000
+#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_ares_reg_reg_s {
+ volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */
+ volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */
+ volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */
+ volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */
+ volatile char pad__0[0x30]; /* 0x10 - 0x40 */
+ volatile unsigned int TXRF1; /* 0x40 - 0x44 */
+ volatile unsigned int TXRF2; /* 0x44 - 0x48 */
+ volatile unsigned int TXRF3; /* 0x48 - 0x4c */
+ volatile unsigned int TXRF4; /* 0x4c - 0x50 */
+ volatile unsigned int TXRF5; /* 0x50 - 0x54 */
+ volatile unsigned int TXRF6; /* 0x54 - 0x58 */
+ volatile unsigned int TXRF7; /* 0x58 - 0x5c */
+ volatile unsigned int TXRF8; /* 0x5c - 0x60 */
+ volatile unsigned int TXRF9; /* 0x60 - 0x64 */
+ volatile unsigned int TXRF10; /* 0x64 - 0x68 */
+ volatile unsigned int TXRF11; /* 0x68 - 0x6c */
+ volatile unsigned int TXRF12; /* 0x6c - 0x70 */
+ volatile char pad__1[0x10]; /* 0x70 - 0x80 */
+ volatile unsigned int SYNTH1; /* 0x80 - 0x84 */
+ volatile unsigned int SYNTH2; /* 0x84 - 0x88 */
+ volatile unsigned int SYNTH3; /* 0x88 - 0x8c */
+ volatile unsigned int SYNTH4; /* 0x8c - 0x90 */
+ volatile unsigned int SYNTH5; /* 0x90 - 0x94 */
+ volatile unsigned int SYNTH6; /* 0x94 - 0x98 */
+ volatile unsigned int SYNTH7; /* 0x98 - 0x9c */
+ volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */
+ volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */
+ volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */
+ volatile unsigned int SYNTH11; /* 0xa8 - 0xac */
+ volatile unsigned int SYNTH12; /* 0xac - 0xb0 */
+ volatile char pad__2[0x10]; /* 0xb0 - 0xc0 */
+ volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */
+ volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */
+ volatile unsigned int BIAS3; /* 0xc8 - 0xcc */
+ volatile unsigned int BIAS4; /* 0xcc - 0xd0 */
+ volatile char pad__3[0x30]; /* 0xd0 - 0x100 */
+ volatile unsigned int RXTX1; /* 0x100 - 0x104 */
+ volatile unsigned int RXTX2; /* 0x104 - 0x108 */
+ volatile unsigned int RXTX3; /* 0x108 - 0x10c */
+ volatile char pad__4[0x34]; /* 0x10c - 0x140 */
+ volatile unsigned int BB1; /* 0x140 - 0x144 */
+ volatile unsigned int BB2; /* 0x144 - 0x148 */
+ volatile char pad__5[0x138]; /* 0x148 - 0x280 */
+ volatile unsigned int TOP1; /* 0x280 - 0x284 */
+ volatile unsigned int TOP2; /* 0x284 - 0x288 */
+ volatile unsigned int TOP3; /* 0x288 - 0x28c */
+ volatile unsigned int TOP4; /* 0x28c - 0x290 */
+ volatile char pad__6[0xf0]; /* 0x290 - 0x380 */
+ volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */
+ volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */
+ volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */
+ volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */
+ volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */
+ volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */
+ volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */
+ volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */
+ volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */
+ volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */
+ volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */
+ volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */
+ volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */
+ volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */
+ volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */
+ volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */
+ volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */
+ volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */
+ volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */
+ volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */
+ volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */
+ volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */
+ volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */
+ volatile unsigned int PMU1; /* 0x740 - 0x744 */
+ volatile unsigned int PMU2; /* 0x744 - 0x748 */
+} analog_intf_ares_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
new file mode 100644
index 000000000000..55ed918fa6ec
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
@@ -0,0 +1,3670 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc. All rights reserved */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
+
+
+#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
+#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
+
+
+/* macros for RXRF_BIAS1 */
+#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_BIAS2 */
+#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB 10
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB 8
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK 0x00000700
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB 13
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB 11
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK 0x00003800
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB 16
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB 14
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK 0x0001c000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB 19
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB 17
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK 0x000e0000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB 22
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB 20
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK 0x00700000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB 25
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB 23
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK 0x03800000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for RXRF_GAINSTAGES */
+#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28)
+#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for RXRF_AGC */
+#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c
+#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB 0
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB 0
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK 0x00000001
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB 1
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB 1
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK 0x00000002
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB 2
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB 2
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK 0x00000004
+#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB 3
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB 3
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK 0x00000008
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB 4
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB 4
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK 0x00000010
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB 5
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB 5
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK 0x00000020
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25)
+#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF1 */
+#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040
+#define PHY_ANALOG_TXRF1_OFFSET 0x00000040
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB 0
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB 0
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK 0x00000001
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB 1
+#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB 1
+#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK 0x00000002
+#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB 2
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB 2
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK 0x00000004
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB 3
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB 3
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK 0x00000008
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB 7
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB 4
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK 0x000000f0
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB 11
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB 8
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK 0x00000f00
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB 15
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB 12
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK 0x0000f000
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB 16
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB 16
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK 0x00010000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 17
+#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 17
+#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00020000
+#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_TXRF1_PDDR2G_MSB 18
+#define PHY_ANALOG_TXRF1_PDDR2G_LSB 18
+#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00040000
+#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 19
+#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 19
+#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00080000
+#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB 20
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB 20
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK 0x00100000
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB 21
+#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB 21
+#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK 0x00200000
+#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30
+#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24
+#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000
+#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF2 */
+#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044
+#define PHY_ANALOG_TXRF2_OFFSET 0x00000044
+#define PHY_ANALOG_TXRF2_D3B5G_MSB 2
+#define PHY_ANALOG_TXRF2_D3B5G_LSB 0
+#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x00000007
+#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF2_D4B5G_MSB 5
+#define PHY_ANALOG_TXRF2_D4B5G_LSB 3
+#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000038
+#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_TXRF2_OCAS2G_MSB 8
+#define PHY_ANALOG_TXRF2_OCAS2G_LSB 6
+#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0x000001c0
+#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0x000001c0) >> 6)
+#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 6) & 0x000001c0)
+#define PHY_ANALOG_TXRF2_DCAS2G_MSB 11
+#define PHY_ANALOG_TXRF2_DCAS2G_LSB 9
+#define PHY_ANALOG_TXRF2_DCAS2G_MASK 0x00000e00
+#define PHY_ANALOG_TXRF2_DCAS2G_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_TXRF2_DCAS2G_SET(x) (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB 14
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB 12
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK 0x00007000
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x) (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x) (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB 17
+#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB 15
+#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK 0x00038000
+#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB 20
+#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB 18
+#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK 0x001c0000
+#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x) (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x) (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB 23
+#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB 21
+#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK 0x00e00000
+#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x) (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x) (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_TXRF2_DB2G_MSB 26
+#define PHY_ANALOG_TXRF2_DB2G_LSB 24
+#define PHY_ANALOG_TXRF2_DB2G_MASK 0x07000000
+#define PHY_ANALOG_TXRF2_DB2G_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_TXRF2_DB2G_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 30
+#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 27
+#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x78000000
+#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 31
+#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 31
+#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x80000000
+#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF3 */
+#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048
+#define PHY_ANALOG_TXRF3_OFFSET 0x00000048
+#define PHY_ANALOG_TXRF3_FILTR2G_MSB 1
+#define PHY_ANALOG_TXRF3_FILTR2G_LSB 0
+#define PHY_ANALOG_TXRF3_FILTR2G_MASK 0x00000003
+#define PHY_ANALOG_TXRF3_FILTR2G_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF3_FILTR2G_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB 2
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB 2
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK 0x00000004
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB 3
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB 3
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK 0x00000008
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF3_PDFB2G_MSB 4
+#define PHY_ANALOG_TXRF3_PDFB2G_LSB 4
+#define PHY_ANALOG_TXRF3_PDFB2G_MASK 0x00000010
+#define PHY_ANALOG_TXRF3_PDFB2G_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TXRF3_PDFB2G_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TXRF3_RDIV5G_MSB 6
+#define PHY_ANALOG_TXRF3_RDIV5G_LSB 5
+#define PHY_ANALOG_TXRF3_RDIV5G_MASK 0x00000060
+#define PHY_ANALOG_TXRF3_RDIV5G_GET(x) (((x) & 0x00000060) >> 5)
+#define PHY_ANALOG_TXRF3_RDIV5G_SET(x) (((x) << 5) & 0x00000060)
+#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB 9
+#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB 7
+#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK 0x00000380
+#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB 10
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB 10
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK 0x00000400
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_TXRF3_RDIV2G_MSB 12
+#define PHY_ANALOG_TXRF3_RDIV2G_LSB 11
+#define PHY_ANALOG_TXRF3_RDIV2G_MASK 0x00001800
+#define PHY_ANALOG_TXRF3_RDIV2G_GET(x) (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_TXRF3_RDIV2G_SET(x) (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB 13
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB 13
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK 0x00002000
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF3_OCAS5G_MSB 16
+#define PHY_ANALOG_TXRF3_OCAS5G_LSB 14
+#define PHY_ANALOG_TXRF3_OCAS5G_MASK 0x0001c000
+#define PHY_ANALOG_TXRF3_OCAS5G_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF3_OCAS5G_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF3_D2CAS5G_MSB 19
+#define PHY_ANALOG_TXRF3_D2CAS5G_LSB 17
+#define PHY_ANALOG_TXRF3_D2CAS5G_MASK 0x000e0000
+#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF3_D3CAS5G_MSB 22
+#define PHY_ANALOG_TXRF3_D3CAS5G_LSB 20
+#define PHY_ANALOG_TXRF3_D3CAS5G_MASK 0x00700000
+#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF3_D4CAS5G_MSB 25
+#define PHY_ANALOG_TXRF3_D4CAS5G_LSB 23
+#define PHY_ANALOG_TXRF3_D4CAS5G_MASK 0x03800000
+#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF3_OB5G_MSB 28
+#define PHY_ANALOG_TXRF3_OB5G_LSB 26
+#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000
+#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF3_D2B5G_MSB 31
+#define PHY_ANALOG_TXRF3_D2B5G_LSB 29
+#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF4 */
+#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c
+#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB 1
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB 0
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK 0x00000003
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB 4
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB 2
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK 0x0000001c
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB 7
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB 5
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK 0x000000e0
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB 10
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB 8
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK 0x00000700
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB 13
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB 11
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK 0x00003800
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 16
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 14
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x0001c000
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 19
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 17
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x000e0000
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 22
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 20
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x00700000
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 25
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 23
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x03800000
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 28
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 26
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x1c000000
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 31
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 29
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF5 */
+#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050
+#define PHY_ANALOG_TXRF5_OFFSET 0x00000050
+#define PHY_ANALOG_TXRF5_SPARE5_MSB 0
+#define PHY_ANALOG_TXRF5_SPARE5_LSB 0
+#define PHY_ANALOG_TXRF5_SPARE5_MASK 0x00000001
+#define PHY_ANALOG_TXRF5_SPARE5_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF5_SPARE5_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB 1
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB 1
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK 0x00000002
+#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_TXRF5_FBHI2G_MSB 2
+#define PHY_ANALOG_TXRF5_FBHI2G_LSB 2
+#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000004
+#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_TXRF5_FBLO2G_MSB 3
+#define PHY_ANALOG_TXRF5_FBLO2G_LSB 3
+#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000008
+#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB 4
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB 4
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK 0x00000010
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB 5
+#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB 5
+#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK 0x00000020
+#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TXRF5_OFFSET2G_MSB 12
+#define PHY_ANALOG_TXRF5_OFFSET2G_LSB 6
+#define PHY_ANALOG_TXRF5_OFFSET2G_MASK 0x00001fc0
+#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x) (((x) & 0x00001fc0) >> 6)
+#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x) (((x) << 6) & 0x00001fc0)
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB 13
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB 13
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK 0x00002000
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TXRF5_REFHI2G_MSB 16
+#define PHY_ANALOG_TXRF5_REFHI2G_LSB 14
+#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0001c000
+#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF5_REFLO2G_MSB 19
+#define PHY_ANALOG_TXRF5_REFLO2G_LSB 17
+#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000e0000
+#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB 21
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB 20
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK 0x00300000
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x) (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x) (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 23
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 22
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00c00000
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 25
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 24
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x03000000
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 27
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 26
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x0c000000
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 29
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 28
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x30000000
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 31
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 30
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0xc0000000
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for TXRF6 */
+#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054
+#define PHY_ANALOG_TXRF6_OFFSET 0x00000054
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB 0
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB 0
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK 0x00000001
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB 8
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB 1
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK 0x000001fe
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x) (((x) & 0x000001fe) >> 1)
+#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x) (((x) << 1) & 0x000001fe)
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB 10
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB 9
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK 0x00000600
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x) (((x) & 0x00000600) >> 9)
+#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x) (((x) << 9) & 0x00000600)
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB 11
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB 11
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK 0x00000800
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 14
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 12
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00007000
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00007000) >> 12)
+#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 12) & 0x00007000)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 15
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 15
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00008000
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB 19
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB 16
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK 0x000f0000
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 23
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 20
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x00f00000
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x00f00000) >> 20)
+#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 20) & 0x00f00000)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 26
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 24
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x07000000
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 30
+#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 27
+#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x78000000
+#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 31
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 31
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x80000000
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for TXRF7 */
+#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058
+#define PHY_ANALOG_TXRF7_OFFSET 0x00000058
+#define PHY_ANALOG_TXRF7_SPARE7_MSB 1
+#define PHY_ANALOG_TXRF7_SPARE7_LSB 0
+#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003
+#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF8 */
+#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c
+#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c
+#define PHY_ANALOG_TXRF8_SPARE8_MSB 1
+#define PHY_ANALOG_TXRF8_SPARE8_LSB 0
+#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003
+#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF9 */
+#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060
+#define PHY_ANALOG_TXRF9_OFFSET 0x00000060
+#define PHY_ANALOG_TXRF9_SPARE9_MSB 1
+#define PHY_ANALOG_TXRF9_SPARE9_LSB 0
+#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003
+#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for TXRF10 */
+#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064
+#define PHY_ANALOG_TXRF10_OFFSET 0x00000064
+#define PHY_ANALOG_TXRF10_SPARE10_MSB 2
+#define PHY_ANALOG_TXRF10_SPARE10_LSB 0
+#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00000007
+#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 3
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 3
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00000008
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 6
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 4
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x00000070
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x00000070) >> 4)
+#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 4) & 0x00000070)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 9
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 7
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x00000380
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 16
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 10
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x0001fc00
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x0001fc00) >> 10)
+#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 10) & 0x0001fc00)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 19
+#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 17
+#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x000e0000
+#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 20
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 20
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x00100000
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 21
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 21
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x00200000
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB 27
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB 22
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK 0x0fc00000
+#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x) (((x) & 0x0fc00000) >> 22)
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB 31
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB 28
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK 0xf0000000
+#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x) (((x) & 0xf0000000) >> 28)
+
+/* macros for TXRF11 */
+#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068
+#define PHY_ANALOG_TXRF11_OFFSET 0x00000068
+#define PHY_ANALOG_TXRF11_SPARE11_MSB 1
+#define PHY_ANALOG_TXRF11_SPARE11_LSB 0
+#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003
+#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 4
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 2
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x0000001c
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 7
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 5
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x000000e0
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 10
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 8
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00000700
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 13
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 11
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x00003800
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 16
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 14
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x0001c000
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB 19
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB 17
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK 0x000e0000
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for TXRF12 */
+#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c
+#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c
+#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7
+#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0
+#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff
+#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 9
+#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8
+#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x00000300
+#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 13
+#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 10
+#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x00003c00
+#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x00003c00) >> 10)
+#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 10) & 0x00003c00)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 16
+#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 14
+#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x0001c000
+#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 19
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 17
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x000e0000
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB 22
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB 20
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK 0x00700000
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 25
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 23
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x03800000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 28
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 26
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0x1c000000
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB 31
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB 29
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK 0xe0000000
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH1 */
+#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080
+#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15
+#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13
+#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000
+#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19)
+#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28
+#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000
+#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30
+#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30
+#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000
+#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH2 */
+#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084
+#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB 15
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB 12
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK 0x0000f000
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB 16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB 16
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK 0x00010000
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB 19
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB 18
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK 0x000c0000
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for SYNTH3 */
+#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088
+#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH4 */
+#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c
+#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB 7
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB 6
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK 0x000000c0
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8
+#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100
+#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12
+#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11
+#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800
+#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11)
+#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18)
+#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH5 */
+#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090
+#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1
+#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0
+#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003
+#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18)
+#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21)
+#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27)
+#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000)
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB 31
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB 30
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK 0xc0000000
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for SYNTH6 */
+#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094
+#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003
+#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8
+#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2
+#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc
+#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2)
+#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9
+#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9
+#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200
+#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10
+#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400
+#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800
+#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000
+#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13
+#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000
+#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14
+#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000
+#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15
+#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15
+#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000
+#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000
+#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24
+#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24
+#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000
+#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000
+#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000
+#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000
+#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000
+#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31)
+
+/* macros for SYNTH7 */
+#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098
+#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18
+#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2
+#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc
+#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2)
+#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc)
+#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27
+#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19
+#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000
+#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19)
+#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28)
+#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000)
+#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30
+#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30
+#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000
+#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH8 */
+#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c
+#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1)
+#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31
+#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27
+#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH9 */
+#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0
+#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31
+#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27
+#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH10 */
+#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4
+#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4
+#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 1
+#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0
+#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000003
+#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 4
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 2
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000001c
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH11 */
+#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8
+#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8
+#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4
+#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0
+#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f
+#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7
+#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6
+#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0
+#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14)
+#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18)
+#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH12 */
+#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac
+#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac
+#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 9
+#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0
+#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x000003ff
+#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB 13
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB 10
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK 0x00003c00
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x) (((x) & 0x00003c00) >> 10)
+#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x) (((x) << 10) & 0x00003c00)
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB 14
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB 14
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK 0x00004000
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB 16
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB 15
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK 0x00018000
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x) (((x) & 0x00018000) >> 15)
+#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x) (((x) << 15) & 0x00018000)
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB 17
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB 17
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK 0x00020000
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18
+#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18
+#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000
+#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22
+#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19
+#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000
+#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26
+#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23
+#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000
+#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30
+#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27
+#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000
+#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for SYNTH13 */
+#define PHY_ANALOG_SYNTH13_ADDRESS 0x000000b0
+#define PHY_ANALOG_SYNTH13_OFFSET 0x000000b0
+#define PHY_ANALOG_SYNTH13_SPARE13A_MSB 0
+#define PHY_ANALOG_SYNTH13_SPARE13A_LSB 0
+#define PHY_ANALOG_SYNTH13_SPARE13A_MASK 0x00000001
+#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB 3
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB 1
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK 0x0000000e
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB 7
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB 4
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK 0x000000f0
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB 11
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB 8
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK 0x00000f00
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB 16
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB 12
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK 0x0001f000
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB 21
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB 17
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK 0x003e0000
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x) (((x) << 17) & 0x003e0000)
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB 26
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB 22
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK 0x07c00000
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x) (((x) & 0x07c00000) >> 22)
+#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x) (((x) << 22) & 0x07c00000)
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB 31
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB 27
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK 0xf8000000
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for SYNTH14 */
+#define PHY_ANALOG_SYNTH14_ADDRESS 0x000000b4
+#define PHY_ANALOG_SYNTH14_OFFSET 0x000000b4
+#define PHY_ANALOG_SYNTH14_SPARE14A_MSB 1
+#define PHY_ANALOG_SYNTH14_SPARE14A_LSB 0
+#define PHY_ANALOG_SYNTH14_SPARE14A_MASK 0x00000003
+#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB 3
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB 2
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK 0x0000000c
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB 5
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB 4
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK 0x00000030
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB 7
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB 6
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK 0x000000c0
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB 9
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB 8
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK 0x00000300
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB 10
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB 10
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK 0x00000400
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB 11
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB 11
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK 0x00000800
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB 12
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB 12
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK 0x00001000
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB 13
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB 13
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK 0x00002000
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB 16
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB 14
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK 0x0001c000
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB 19
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB 17
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK 0x000e0000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB 22
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB 20
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK 0x00700000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB 25
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB 23
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK 0x03800000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB 28
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB 26
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK 0x1c000000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB 31
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB 29
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK 0xe0000000
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS1 */
+#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0
+#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0
+#define PHY_ANALOG_BIAS1_SPARE1_MSB 6
+#define PHY_ANALOG_BIAS1_SPARE1_LSB 0
+#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f
+#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10)
+#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22)
+#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31
+#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25
+#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000
+#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25)
+#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000)
+
+/* macros for BIAS2 */
+#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4
+#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4
+#define PHY_ANALOG_BIAS2_SPARE2_MSB 4
+#define PHY_ANALOG_BIAS2_SPARE2_LSB 0
+#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f
+#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB 7
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB 5
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK 0x000000e0
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB 19
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB 17
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK 0x000e0000
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS3 */
+#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8
+#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8
+#define PHY_ANALOG_BIAS3_SPARE3_MSB 1
+#define PHY_ANALOG_BIAS3_SPARE3_LSB 0
+#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003
+#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB 4
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB 2
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK 0x0000001c
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB 13
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB 11
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK 0x00003800
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for BIAS4 */
+#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc
+#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc
+#define PHY_ANALOG_BIAS4_SPARE4_MSB 10
+#define PHY_ANALOG_BIAS4_SPARE4_LSB 0
+#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x000007ff
+#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB 13
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB 11
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK 0x00003800
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x) (((x) & 0x00003800) >> 11)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x) (((x) << 11) & 0x00003800)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB 22
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB 20
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK 0x00700000
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x) (((x) & 0x00700000) >> 20)
+#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x) (((x) << 20) & 0x00700000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX1 */
+#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100
+#define PHY_ANALOG_RXTX1_OFFSET 0x00000100
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1
+#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002
+#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2)
+#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12)
+#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18
+#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15
+#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000
+#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15)
+#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19)
+#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23)
+#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000)
+#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30
+#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27
+#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000
+#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31
+#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000
+#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for RXTX2 */
+#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104
+#define PHY_ANALOG_RXTX2_OFFSET 0x00000104
+#define PHY_ANALOG_RXTX2_BMODE_MSB 0
+#define PHY_ANALOG_RXTX2_BMODE_LSB 0
+#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001
+#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1
+#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002
+#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2
+#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2
+#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004
+#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX2_BW_ST_MSB 5
+#define PHY_ANALOG_RXTX2_BW_ST_LSB 4
+#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030
+#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX2_TXON_MSB 7
+#define PHY_ANALOG_RXTX2_TXON_LSB 7
+#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080
+#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8
+#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8
+#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100
+#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX2_PAON_MSB 9
+#define PHY_ANALOG_RXTX2_PAON_LSB 9
+#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200
+#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10
+#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10
+#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400
+#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX2_RXON_MSB 11
+#define PHY_ANALOG_RXTX2_RXON_LSB 11
+#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800
+#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12
+#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12
+#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000
+#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RXTX2_AGCON_MSB 13
+#define PHY_ANALOG_RXTX2_AGCON_LSB 13
+#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000
+#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14
+#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000
+#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RXTX2_TXMOD_MSB 17
+#define PHY_ANALOG_RXTX2_TXMOD_LSB 15
+#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000
+#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15)
+#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25
+#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24
+#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000
+#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28
+#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26
+#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000
+#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000)
+#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31
+#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29
+#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000
+#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for RXTX3 */
+#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108
+#define PHY_ANALOG_RXTX3_OFFSET 0x00000108
+#define PHY_ANALOG_RXTX3_SPARE3_MSB 2
+#define PHY_ANALOG_RXTX3_SPARE3_LSB 0
+#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007
+#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_RXTX3_SPURON_MSB 3
+#define PHY_ANALOG_RXTX3_SPURON_LSB 3
+#define PHY_ANALOG_RXTX3_SPURON_MASK 0x00000008
+#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB 4
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB 4
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK 0x00000010
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 5
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 5
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000020
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6
+#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6
+#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040
+#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RXTX3_DACPWD_MSB 7
+#define PHY_ANALOG_RXTX3_DACPWD_LSB 7
+#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080
+#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9
+#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9
+#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200
+#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11)
+#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800)
+#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17
+#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17
+#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000
+#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19
+#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000
+#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20
+#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_RXTX3_CALFC_MSB 22
+#define PHY_ANALOG_RXTX3_CALFC_LSB 22
+#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000
+#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23
+#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000
+#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_RXTX3_CALTX_MSB 24
+#define PHY_ANALOG_RXTX3_CALTX_LSB 24
+#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000
+#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25
+#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000
+#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_RXTX3_CALPA_MSB 28
+#define PHY_ANALOG_RXTX3_CALPA_LSB 28
+#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000
+#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29
+#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000
+#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_RXTX3_TURBOADC_MSB 30
+#define PHY_ANALOG_RXTX3_TURBOADC_LSB 30
+#define PHY_ANALOG_RXTX3_TURBOADC_MASK 0x40000000
+#define PHY_ANALOG_RXTX3_TURBOADC_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_RXTX3_TURBOADC_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB 31
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB 31
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK 0x80000000
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB1 */
+#define PHY_ANALOG_BB1_ADDRESS 0x00000140
+#define PHY_ANALOG_BB1_OFFSET 0x00000140
+#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0
+#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0
+#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001
+#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1
+#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002
+#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2
+#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2
+#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004
+#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4
+#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010
+#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8
+#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100
+#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9
+#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9
+#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200
+#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10
+#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10
+#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400
+#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11
+#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11
+#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800
+#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12
+#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12
+#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000
+#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_BB1_CMSEL_MSB 15
+#define PHY_ANALOG_BB1_CMSEL_LSB 13
+#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000
+#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_ANALOG_BB1_ATBSEL_MSB 17
+#define PHY_ANALOG_BB1_ATBSEL_LSB 16
+#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000
+#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19)
+#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000)
+#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29
+#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29
+#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000
+#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31
+#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30
+#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000
+#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for BB2 */
+#define PHY_ANALOG_BB2_ADDRESS 0x00000144
+#define PHY_ANALOG_BB2_OFFSET 0x00000144
+#define PHY_ANALOG_BB2_SPARE_MSB 3
+#define PHY_ANALOG_BB2_SPARE_LSB 0
+#define PHY_ANALOG_BB2_SPARE_MASK 0x0000000f
+#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB 7
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB 4
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK 0x000000f0
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_ANALOG_BB2_SEL_TEST_MSB 9
+#define PHY_ANALOG_BB2_SEL_TEST_LSB 8
+#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000300
+#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB 14
+#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB 10
+#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK 0x00007c00
+#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB 15
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB 15
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK 0x00008000
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_BB2_FNOTCH_MSB 19
+#define PHY_ANALOG_BB2_FNOTCH_LSB 16
+#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000
+#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_BB2_FILTERFC_MSB 25
+#define PHY_ANALOG_BB2_FILTERFC_LSB 21
+#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000
+#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB3 */
+#define PHY_ANALOG_BB3_ADDRESS 0x00000148
+#define PHY_ANALOG_BB3_OFFSET 0x00000148
+#define PHY_ANALOG_BB3_SPARE_MSB 15
+#define PHY_ANALOG_BB3_SPARE_LSB 0
+#define PHY_ANALOG_BB3_SPARE_MASK 0x0000ffff
+#define PHY_ANALOG_BB3_SPARE_GET(x) (((x) & 0x0000ffff) >> 0)
+#define PHY_ANALOG_BB3_SPARE_SET(x) (((x) << 0) & 0x0000ffff)
+#define PHY_ANALOG_BB3_FILTERFC_MSB 20
+#define PHY_ANALOG_BB3_FILTERFC_LSB 16
+#define PHY_ANALOG_BB3_FILTERFC_MASK 0x001f0000
+#define PHY_ANALOG_BB3_FILTERFC_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB 25
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB 21
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK 0x03e00000
+#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x) (((x) & 0x03e00000) >> 21)
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB 30
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB 26
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK 0x7c000000
+#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x) (((x) & 0x7c000000) >> 26)
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB 31
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB 31
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK 0x80000000
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for PLLCLKMODA */
+#define PHY_ANALOG_PLLCLKMODA_ADDRESS 0x00000280
+#define PHY_ANALOG_PLLCLKMODA_OFFSET 0x00000280
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB 0
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB 0
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK 0x00000001
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB 1
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB 1
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK 0x00000002
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB 16
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB 2
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK 0x0001fffc
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x) (((x) & 0x0001fffc) >> 2)
+#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x) (((x) << 2) & 0x0001fffc)
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB 20
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB 17
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK 0x001e0000
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x) (((x) & 0x001e0000) >> 17)
+#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x) (((x) << 17) & 0x001e0000)
+#define PHY_ANALOG_PLLCLKMODA_DIV_MSB 30
+#define PHY_ANALOG_PLLCLKMODA_DIV_LSB 21
+#define PHY_ANALOG_PLLCLKMODA_DIV_MASK 0x7fe00000
+#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x) (((x) & 0x7fe00000) >> 21)
+#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x) (((x) << 21) & 0x7fe00000)
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB 31
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB 31
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK 0x80000000
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for PLLCLKMODA2 */
+#define PHY_ANALOG_PLLCLKMODA2_ADDRESS 0x00000284
+#define PHY_ANALOG_PLLCLKMODA2_OFFSET 0x00000284
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB 3
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB 0
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK 0x0000000f
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB 4
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB 4
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK 0x00000010
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB 5
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB 5
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK 0x00000020
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB 6
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB 6
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK 0x00000040
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB 8
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB 7
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK 0x00000180
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x) (((x) & 0x00000180) >> 7)
+#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x) (((x) << 7) & 0x00000180)
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB 12
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB 9
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK 0x00001e00
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x) (((x) & 0x00001e00) >> 9)
+#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x) (((x) << 9) & 0x00001e00)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB 13
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB 13
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK 0x00002000
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB 14
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB 14
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK 0x00004000
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB 15
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB 15
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK 0x00008000
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB 17
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB 16
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK 0x00030000
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x) (((x) & 0x00030000) >> 16)
+#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x) (((x) << 16) & 0x00030000)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB 18
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB 18
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK 0x00040000
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB 19
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB 19
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK 0x00080000
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB 20
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB 20
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK 0x00100000
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB 21
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB 21
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK 0x00200000
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB 23
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB 22
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK 0x00c00000
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB 26
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB 24
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK 0x07000000
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB 31
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB 27
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK 0xf8000000
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for TOP */
+#define PHY_ANALOG_TOP_ADDRESS 0x00000288
+#define PHY_ANALOG_TOP_OFFSET 0x00000288
+#define PHY_ANALOG_TOP_SPARE_MSB 2
+#define PHY_ANALOG_TOP_SPARE_LSB 0
+#define PHY_ANALOG_TOP_SPARE_MASK 0x00000007
+#define PHY_ANALOG_TOP_SPARE_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_TOP_SPARE_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_TOP_PWDBIAS_MSB 3
+#define PHY_ANALOG_TOP_PWDBIAS_LSB 3
+#define PHY_ANALOG_TOP_PWDBIAS_MASK 0x00000008
+#define PHY_ANALOG_TOP_PWDBIAS_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_TOP_PWDBIAS_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB 4
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB 4
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK 0x00000010
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_TOP_XPAON2_MSB 5
+#define PHY_ANALOG_TOP_XPAON2_LSB 5
+#define PHY_ANALOG_TOP_XPAON2_MASK 0x00000020
+#define PHY_ANALOG_TOP_XPAON2_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_TOP_XPAON2_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_TOP_XPAON5_MSB 6
+#define PHY_ANALOG_TOP_XPAON5_LSB 6
+#define PHY_ANALOG_TOP_XPAON5_MASK 0x00000040
+#define PHY_ANALOG_TOP_XPAON5_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_TOP_XPAON5_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_TOP_XPASHORT2GND_MSB 7
+#define PHY_ANALOG_TOP_XPASHORT2GND_LSB 7
+#define PHY_ANALOG_TOP_XPASHORT2GND_MASK 0x00000080
+#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_TOP_XPABIASLVL_MSB 11
+#define PHY_ANALOG_TOP_XPABIASLVL_LSB 8
+#define PHY_ANALOG_TOP_XPABIASLVL_MASK 0x00000f00
+#define PHY_ANALOG_TOP_XPABIASLVL_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TOP_XPABIASLVL_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TOP_XPABIAS_EN_MSB 12
+#define PHY_ANALOG_TOP_XPABIAS_EN_LSB 12
+#define PHY_ANALOG_TOP_XPABIAS_EN_MASK 0x00001000
+#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_TOP_ATBSELECT_MSB 13
+#define PHY_ANALOG_TOP_ATBSELECT_LSB 13
+#define PHY_ANALOG_TOP_ATBSELECT_MASK 0x00002000
+#define PHY_ANALOG_TOP_ATBSELECT_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_TOP_ATBSELECT_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_TOP_LOCAL_XPA_MSB 14
+#define PHY_ANALOG_TOP_LOCAL_XPA_LSB 14
+#define PHY_ANALOG_TOP_LOCAL_XPA_MASK 0x00004000
+#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB 15
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB 15
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK 0x00008000
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB 16
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB 16
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK 0x00010000
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB 17
+#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB 17
+#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK 0x00020000
+#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB 18
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB 18
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK 0x00040000
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB 19
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB 19
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK 0x00080000
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_TOP_PAD2GND_MSB 20
+#define PHY_ANALOG_TOP_PAD2GND_LSB 20
+#define PHY_ANALOG_TOP_PAD2GND_MASK 0x00100000
+#define PHY_ANALOG_TOP_PAD2GND_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_ANALOG_TOP_PAD2GND_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_ANALOG_TOP_INTH2PAD_MSB 21
+#define PHY_ANALOG_TOP_INTH2PAD_LSB 21
+#define PHY_ANALOG_TOP_INTH2PAD_MASK 0x00200000
+#define PHY_ANALOG_TOP_INTH2PAD_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_ANALOG_TOP_INTH2PAD_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_ANALOG_TOP_INTH2GND_MSB 22
+#define PHY_ANALOG_TOP_INTH2GND_LSB 22
+#define PHY_ANALOG_TOP_INTH2GND_MASK 0x00400000
+#define PHY_ANALOG_TOP_INTH2GND_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_TOP_INTH2GND_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_TOP_INT2PAD_MSB 23
+#define PHY_ANALOG_TOP_INT2PAD_LSB 23
+#define PHY_ANALOG_TOP_INT2PAD_MASK 0x00800000
+#define PHY_ANALOG_TOP_INT2PAD_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_TOP_INT2PAD_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_TOP_INT2GND_MSB 24
+#define PHY_ANALOG_TOP_INT2GND_LSB 24
+#define PHY_ANALOG_TOP_INT2GND_MASK 0x01000000
+#define PHY_ANALOG_TOP_INT2GND_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_TOP_INT2GND_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_TOP_PWDPALCLK_MSB 25
+#define PHY_ANALOG_TOP_PWDPALCLK_LSB 25
+#define PHY_ANALOG_TOP_PWDPALCLK_MASK 0x02000000
+#define PHY_ANALOG_TOP_PWDPALCLK_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_ANALOG_TOP_PWDPALCLK_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB 26
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB 26
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK 0x04000000
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB 27
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB 27
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK 0x08000000
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB 28
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB 28
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK 0x10000000
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB 29
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB 29
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK 0x20000000
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_TOP_CLK_SEL_MSB 31
+#define PHY_ANALOG_TOP_CLK_SEL_LSB 30
+#define PHY_ANALOG_TOP_CLK_SEL_MASK 0xc0000000
+#define PHY_ANALOG_TOP_CLK_SEL_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_ANALOG_TOP_CLK_SEL_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for THERM */
+#define PHY_ANALOG_THERM_ADDRESS 0x0000028c
+#define PHY_ANALOG_THERM_OFFSET 0x0000028c
+#define PHY_ANALOG_THERM_LOREG_LVL_MSB 2
+#define PHY_ANALOG_THERM_LOREG_LVL_LSB 0
+#define PHY_ANALOG_THERM_LOREG_LVL_MASK 0x00000007
+#define PHY_ANALOG_THERM_LOREG_LVL_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_ANALOG_THERM_LOREG_LVL_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_ANALOG_THERM_RFREG_LVL_MSB 5
+#define PHY_ANALOG_THERM_RFREG_LVL_LSB 3
+#define PHY_ANALOG_THERM_RFREG_LVL_MASK 0x00000038
+#define PHY_ANALOG_THERM_RFREG_LVL_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_ANALOG_THERM_RFREG_LVL_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB 6
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB 6
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK 0x00000040
+#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB 14
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB 7
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK 0x00007f80
+#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x) (((x) & 0x00007f80) >> 7)
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB 22
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB 15
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK 0x007f8000
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x) (((x) & 0x007f8000) >> 15)
+#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x) (((x) << 15) & 0x007f8000)
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB 23
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB 23
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK 0x00800000
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB 24
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB 24
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK 0x01000000
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_ANALOG_THERM_THERMSEL_MSB 26
+#define PHY_ANALOG_THERM_THERMSEL_LSB 25
+#define PHY_ANALOG_THERM_THERMSEL_MASK 0x06000000
+#define PHY_ANALOG_THERM_THERMSEL_GET(x) (((x) & 0x06000000) >> 25)
+#define PHY_ANALOG_THERM_THERMSEL_SET(x) (((x) << 25) & 0x06000000)
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB 27
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB 27
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK 0x08000000
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_ANALOG_THERM_THERMSTART_MSB 28
+#define PHY_ANALOG_THERM_THERMSTART_LSB 28
+#define PHY_ANALOG_THERM_THERMSTART_MASK 0x10000000
+#define PHY_ANALOG_THERM_THERMSTART_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_THERM_THERMSTART_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB 29
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB 29
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK 0x20000000
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_ANALOG_THERM_THERMON_MSB 30
+#define PHY_ANALOG_THERM_THERMON_LSB 30
+#define PHY_ANALOG_THERM_THERMON_MASK 0x40000000
+#define PHY_ANALOG_THERM_THERMON_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_THERM_THERMON_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_THERM_LOCAL_THERM_MSB 31
+#define PHY_ANALOG_THERM_LOCAL_THERM_LSB 31
+#define PHY_ANALOG_THERM_LOCAL_THERM_MASK 0x80000000
+#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for XTAL */
+#define PHY_ANALOG_XTAL_ADDRESS 0x00000290
+#define PHY_ANALOG_XTAL_OFFSET 0x00000290
+#define PHY_ANALOG_XTAL_SPARE_MSB 5
+#define PHY_ANALOG_XTAL_SPARE_LSB 0
+#define PHY_ANALOG_XTAL_SPARE_MASK 0x0000003f
+#define PHY_ANALOG_XTAL_SPARE_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_ANALOG_XTAL_SPARE_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB 6
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB 6
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK 0x00000040
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB 7
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB 7
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK 0x00000080
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB 8
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB 8
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK 0x00000100
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB 9
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB 9
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK 0x00000200
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB 10
+#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB 10
+#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK 0x00000400
+#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB 11
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB 11
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK 0x00000800
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB 12
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB 12
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK 0x00001000
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB 13
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB 13
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK 0x00002000
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB 15
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB 14
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK 0x0000c000
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB 22
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB 16
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK 0x007f0000
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16)
+#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000)
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB 29
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB 23
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK 0x3f800000
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23)
+#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000)
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB 30
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB 30
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK 0x40000000
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_ANALOG_XTAL_TCXODET_MSB 31
+#define PHY_ANALOG_XTAL_TCXODET_LSB 31
+#define PHY_ANALOG_XTAL_TCXODET_MASK 0x80000000
+#define PHY_ANALOG_XTAL_TCXODET_GET(x) (((x) & 0x80000000) >> 31)
+
+/* macros for rbist_cntrl */
+#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000)
+
+/* macros for tx_dc_offset */
+#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16)
+#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000)
+
+/* macros for tx_tonegen0 */
+#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for tx_tonegen1 */
+#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for tx_lftonegen0 */
+#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for tx_linear_ramp_i */
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for tx_linear_ramp_q */
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for tx_prbs_mag */
+#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000)
+
+/* macros for tx_prbs_seed_i */
+#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
+
+/* macros for tx_prbs_seed_q */
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
+#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
+
+/* macros for cmac_dc_cancel */
+#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16)
+#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000)
+
+/* macros for cmac_dc_offset */
+#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_corr */
+#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00)
+
+/* macros for cmac_power */
+#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_cross_corr */
+#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_i2q2 */
+#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+
+/* macros for cmac_power_hpf */
+#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0)
+
+/* macros for rxdac_set1 */
+#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000)
+
+/* macros for rxdac_set2 */
+#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24)
+#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000)
+
+/* macros for rxdac_long_shift */
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00)
+
+/* macros for cmac_results_i */
+#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for cmac_results_q */
+#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for PMU1 */
+#define PHY_ANALOG_PMU1_ADDRESS 0x00000740
+#define PHY_ANALOG_PMU1_OFFSET 0x00000740
+#define PHY_ANALOG_PMU1_SPARE_MSB 10
+#define PHY_ANALOG_PMU1_SPARE_LSB 0
+#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff
+#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12
+#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000
+#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14
+#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14
+#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000
+#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16
+#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000
+#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26)
+#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28
+#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000
+#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29)
+#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000)
+
+/* macros for PMU2 */
+#define PHY_ANALOG_PMU2_ADDRESS 0x00000744
+#define PHY_ANALOG_PMU2_OFFSET 0x00000744
+#define PHY_ANALOG_PMU2_SPARE_MSB 7
+#define PHY_ANALOG_PMU2_SPARE_LSB 0
+#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff
+#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17)
+#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20)
+#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23)
+#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000)
+#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27
+#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25
+#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000
+#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25)
+#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28
+#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000
+#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct analog_intf_athr_wlan_reg_reg_s {
+ volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */
+ volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */
+ volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */
+ volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */
+ volatile char pad__0[0x30]; /* 0x10 - 0x40 */
+ volatile unsigned int TXRF1; /* 0x40 - 0x44 */
+ volatile unsigned int TXRF2; /* 0x44 - 0x48 */
+ volatile unsigned int TXRF3; /* 0x48 - 0x4c */
+ volatile unsigned int TXRF4; /* 0x4c - 0x50 */
+ volatile unsigned int TXRF5; /* 0x50 - 0x54 */
+ volatile unsigned int TXRF6; /* 0x54 - 0x58 */
+ volatile unsigned int TXRF7; /* 0x58 - 0x5c */
+ volatile unsigned int TXRF8; /* 0x5c - 0x60 */
+ volatile unsigned int TXRF9; /* 0x60 - 0x64 */
+ volatile unsigned int TXRF10; /* 0x64 - 0x68 */
+ volatile unsigned int TXRF11; /* 0x68 - 0x6c */
+ volatile unsigned int TXRF12; /* 0x6c - 0x70 */
+ volatile char pad__1[0x10]; /* 0x70 - 0x80 */
+ volatile unsigned int SYNTH1; /* 0x80 - 0x84 */
+ volatile unsigned int SYNTH2; /* 0x84 - 0x88 */
+ volatile unsigned int SYNTH3; /* 0x88 - 0x8c */
+ volatile unsigned int SYNTH4; /* 0x8c - 0x90 */
+ volatile unsigned int SYNTH5; /* 0x90 - 0x94 */
+ volatile unsigned int SYNTH6; /* 0x94 - 0x98 */
+ volatile unsigned int SYNTH7; /* 0x98 - 0x9c */
+ volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */
+ volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */
+ volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */
+ volatile unsigned int SYNTH11; /* 0xa8 - 0xac */
+ volatile unsigned int SYNTH12; /* 0xac - 0xb0 */
+ volatile unsigned int SYNTH13; /* 0xb0 - 0xb4 */
+ volatile unsigned int SYNTH14; /* 0xb4 - 0xb8 */
+ volatile char pad__2[0x8]; /* 0xb8 - 0xc0 */
+ volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */
+ volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */
+ volatile unsigned int BIAS3; /* 0xc8 - 0xcc */
+ volatile unsigned int BIAS4; /* 0xcc - 0xd0 */
+ volatile char pad__3[0x30]; /* 0xd0 - 0x100 */
+ volatile unsigned int RXTX1; /* 0x100 - 0x104 */
+ volatile unsigned int RXTX2; /* 0x104 - 0x108 */
+ volatile unsigned int RXTX3; /* 0x108 - 0x10c */
+ volatile char pad__4[0x34]; /* 0x10c - 0x140 */
+ volatile unsigned int BB1; /* 0x140 - 0x144 */
+ volatile unsigned int BB2; /* 0x144 - 0x148 */
+ volatile unsigned int BB3; /* 0x148 - 0x14c */
+ volatile char pad__5[0x134]; /* 0x14c - 0x280 */
+ volatile unsigned int PLLCLKMODA; /* 0x280 - 0x284 */
+ volatile unsigned int PLLCLKMODA2; /* 0x284 - 0x288 */
+ volatile unsigned int TOP; /* 0x288 - 0x28c */
+ volatile unsigned int THERM; /* 0x28c - 0x290 */
+ volatile unsigned int XTAL; /* 0x290 - 0x294 */
+ volatile char pad__6[0xec]; /* 0x294 - 0x380 */
+ volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */
+ volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */
+ volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */
+ volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */
+ volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */
+ volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */
+ volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */
+ volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */
+ volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */
+ volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */
+ volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */
+ volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */
+ volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */
+ volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */
+ volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */
+ volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */
+ volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */
+ volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */
+ volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */
+ volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */
+ volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */
+ volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */
+ volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */
+ volatile unsigned int PMU1; /* 0x740 - 0x744 */
+ volatile unsigned int PMU2; /* 0x744 - 0x748 */
+} analog_intf_athr_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h
new file mode 100644
index 000000000000..7e6320d28ac6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h
@@ -0,0 +1,33 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "analog_intf_athr_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h
new file mode 100644
index 000000000000..143460719bbf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h
@@ -0,0 +1,36 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _APB_ATHR_WLAN_MAP_H_
+#define _APB_ATHR_WLAN_MAP_H_
+
+#define WLAN_RTC_BASE_ADDRESS 0x00004000
+#define WLAN_VMC_BASE_ADDRESS 0x00008000
+#define WLAN_UART_BASE_ADDRESS 0x0000c000
+#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000
+#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000
+#define WLAN_SI_BASE_ADDRESS 0x00010000
+#define WLAN_GPIO_BASE_ADDRESS 0x00014000
+#define WLAN_MBOX_BASE_ADDRESS 0x00018000
+#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
+#define WLAN_MAC_BASE_ADDRESS 0x00020000
+#define WLAN_RDMA_BASE_ADDRESS 0x00030100
+#define EFUSE_BASE_ADDRESS 0x00031000
+
+#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h
new file mode 100644
index 000000000000..6c85e2643d24
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h
@@ -0,0 +1,44 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "apb_athr_wlan_map.h"
+
+
+#ifndef BT_HEADERS
+
+#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
+#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS
+#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS
+#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS
+#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS
+#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
+#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
+#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS
+#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
+#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
+#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h
new file mode 100644
index 000000000000..61827bc79cba
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h
@@ -0,0 +1,7072 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+/* Copyright (C) 2009 Denali Software Inc. All rights reserved */
+/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
+
+
+#ifndef _BB_LC_REG_REG_H_
+#define _BB_LC_REG_REG_H_
+
+
+/* macros for BB_test_controls */
+#define PHY_BB_TEST_CONTROLS_ADDRESS 0x00009800
+#define PHY_BB_TEST_CONTROLS_OFFSET 0x00009800
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0x0000000f
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x00000010
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x00000060
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & 0x00000060) >> 5)
+#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((x) << 5) & 0x00000060)
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x00000300
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x00000400
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x00002000
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x00008000
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x00020000
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x00040000
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x00780000
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & 0x00780000) >> 19)
+#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((x) << 19) & 0x00780000)
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x00800000
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x01000000
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for BB_gen_controls */
+#define PHY_BB_GEN_CONTROLS_ADDRESS 0x00009804
+#define PHY_BB_GEN_CONTROLS_OFFSET 0x00009804
+#define PHY_BB_GEN_CONTROLS_TURBO_MSB 0
+#define PHY_BB_GEN_CONTROLS_TURBO_LSB 0
+#define PHY_BB_GEN_CONTROLS_TURBO_MASK 0x00000001
+#define PHY_BB_GEN_CONTROLS_TURBO_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_GEN_CONTROLS_TURBO_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB 1
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB 1
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK 0x00000002
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB 2
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB 2
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK 0x00000004
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB 3
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB 3
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK 0x00000008
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB 4
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB 4
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK 0x00000010
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB 5
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB 5
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK 0x00000020
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB 6
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB 6
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK 0x00000040
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 7
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 7
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x00000080
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB 8
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB 8
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK 0x00000100
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB 9
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB 9
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK 0x00000200
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 10
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 10
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x00000400
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB 11
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB 11
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK 0x00000800
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x) (((x) << 11) & 0x00000800)
+
+/* macros for BB_test_controls_status */
+#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS 0x00009808
+#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET 0x00009808
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x00000001
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x00000002
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x0000001c
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & 0x0000001c) >> 2)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((x) << 2) & 0x0000001c)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x00000060
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & 0x00000060) >> 5)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((x) << 5) & 0x00000060)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x00000080
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x00000100
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x00000200
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x00003c00
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & 0x00003c00) >> 10)
+#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((x) << 10) & 0x00003c00)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x00004000
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x00008000
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x00070000
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x00080000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x00800000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x08000000
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 30
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0x60000000
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((x) << 29) & 0x60000000)
+
+/* macros for BB_timing_controls_1 */
+#define PHY_BB_TIMING_CONTROLS_1_ADDRESS 0x0000980c
+#define PHY_BB_TIMING_CONTROLS_1_OFFSET 0x0000980c
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x0000007f
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x00001f80
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & 0x00001f80) >> 7)
+#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((x) << 7) & 0x00001f80)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB 16
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB 13
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK 0x0001e000
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x) (((x) & 0x0001e000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x) (((x) << 13) & 0x0001e000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB 17
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB 17
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK 0x00020000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0x000c0000
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x00300000
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & 0x00300000) >> 20)
+#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((x) << 20) & 0x00300000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x00400000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x00800000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x01000000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x06000000
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & 0x06000000) >> 25)
+#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((x) << 25) & 0x06000000)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x08000000
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((x) << 29) & 0x60000000)
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_controls_2 */
+#define PHY_BB_TIMING_CONTROLS_2_ADDRESS 0x00009810
+#define PHY_BB_TIMING_CONTROLS_2_OFFSET 0x00009810
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0x00000fff
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((x) << 0) & 0x00000fff)
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x00001000
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x00002000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB 14
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB 14
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK 0x00004000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x00008000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x007f0000
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & 0x007f0000) >> 16)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((x) << 16) & 0x007f0000)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x07000000
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x08000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_controls_3 */
+#define PHY_BB_TIMING_CONTROLS_3_ADDRESS 0x00009814
+#define PHY_BB_TIMING_CONTROLS_3_OFFSET 0x00009814
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0x000000ff
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x00000100
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x00000200
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x00000400
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x00000800
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x00001000
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x0001e000
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & 0x0001e000) >> 13)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((x) << 13) & 0x0001e000)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & 0xfffe0000) >> 17)
+#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((x) << 17) & 0xfffe0000)
+
+/* macros for BB_D2_chip_id */
+#define PHY_BB_D2_CHIP_ID_ADDRESS 0x00009818
+#define PHY_BB_D2_CHIP_ID_OFFSET 0x00009818
+#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB 7
+#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB 0
+#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK 0x000000ff
+#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_D2_CHIP_ID_ID_MSB 31
+#define PHY_BB_D2_CHIP_ID_ID_LSB 8
+#define PHY_BB_D2_CHIP_ID_ID_MASK 0xffffff00
+#define PHY_BB_D2_CHIP_ID_ID_GET(x) (((x) & 0xffffff00) >> 8)
+
+/* macros for BB_active */
+#define PHY_BB_ACTIVE_ADDRESS 0x0000981c
+#define PHY_BB_ACTIVE_OFFSET 0x0000981c
+#define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0
+#define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0
+#define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x00000001
+#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((x) << 0) & 0x00000001)
+
+/* macros for BB_tx_timing_1 */
+#define PHY_BB_TX_TIMING_1_ADDRESS 0x00009820
+#define PHY_BB_TX_TIMING_1_OFFSET 0x00009820
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0x000000ff
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0x0000ff00
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0x00ff0000
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_tx_timing_2 */
+#define PHY_BB_TX_TIMING_2_ADDRESS 0x00009824
+#define PHY_BB_TX_TIMING_2_OFFSET 0x00009824
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0x000000ff
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0x0000ff00
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0x00ff0000
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_tx_timing_3 */
+#define PHY_BB_TX_TIMING_3_ADDRESS 0x00009828
+#define PHY_BB_TX_TIMING_3_OFFSET 0x00009828
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0x000000ff
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0x0000ff00
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0x00ff0000
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_addac_parallel_control */
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS 0x0000982c
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET 0x0000982c
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x00001000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x00002000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x00008000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_xpa_timing_control */
+#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS 0x00009834
+#define PHY_BB_XPA_TIMING_CONTROL_OFFSET 0x00009834
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0x000000ff
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0x0000ff00
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0x00ff0000
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_misc_pa_control */
+#define PHY_BB_MISC_PA_CONTROL_ADDRESS 0x00009838
+#define PHY_BB_MISC_PA_CONTROL_OFFSET 0x00009838
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x00000001
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x00000002
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x00000004
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x00000008
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((x) << 3) & 0x00000008)
+
+/* macros for BB_tstdac_constant */
+#define PHY_BB_TSTDAC_CONSTANT_ADDRESS 0x0000983c
+#define PHY_BB_TSTDAC_CONSTANT_OFFSET 0x0000983c
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x000007ff
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & 0x000007ff) >> 0)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((x) << 0) & 0x000007ff)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x003ff800
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & 0x003ff800) >> 11)
+#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((x) << 11) & 0x003ff800)
+
+/* macros for BB_find_signal_low */
+#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS 0x00009840
+#define PHY_BB_FIND_SIGNAL_LOW_OFFSET 0x00009840
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x0000003f
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0x00000fc0
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0x000ff000
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & 0x000ff000) >> 12)
+#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((x) << 12) & 0x000ff000)
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0x00f00000
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & 0x00f00000) >> 20)
+#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((x) << 20) & 0x00f00000)
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for BB_settling_time */
+#define PHY_BB_SETTLING_TIME_ADDRESS 0x00009844
+#define PHY_BB_SETTLING_TIME_OFFSET 0x00009844
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB 6
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB 0
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK 0x0000007f
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB 13
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB 7
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK 0x00003f80
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x) (((x) & 0x00003f80) >> 7)
+#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x) (((x) << 7) & 0x00003f80)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB 19
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB 14
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK 0x000fc000
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x) (((x) << 14) & 0x000fc000)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB 25
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB 20
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK 0x03f00000
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x) (((x) & 0x03f00000) >> 20)
+#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x) (((x) << 20) & 0x03f00000)
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB 29
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB 26
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK 0x3c000000
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x) (((x) & 0x3c000000) >> 26)
+#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x) (((x) << 26) & 0x3c000000)
+
+/* macros for BB_gain_force_max_gains_b0 */
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS 0x00009848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET 0x00009848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB 13
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB 7
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK 0x00003f80
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x) (((x) & 0x00003f80) >> 7)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x) (((x) << 7) & 0x00003f80)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB 20
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB 14
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK 0x001fc000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x) (((x) & 0x001fc000) >> 14)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x) (((x) << 14) & 0x001fc000)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB 21
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB 21
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK 0x00200000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB 31
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB 31
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK 0x80000000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_gains_min_offsets_b0 */
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS 0x0000984c
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET 0x0000984c
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB 6
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB 0
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK 0x0000007f
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB 11
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB 7
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK 0x00000f80
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x) (((x) & 0x00000f80) >> 7)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x) (((x) << 7) & 0x00000f80)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB 16
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB 12
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK 0x0001f000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB 24
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB 17
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK 0x01fe0000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x) (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x) (((x) << 17) & 0x01fe0000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB 25
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB 25
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK 0x02000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB 26
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB 26
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK 0x04000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x) (((x) << 26) & 0x04000000)
+
+/* macros for BB_desired_sigsize */
+#define PHY_BB_DESIRED_SIGSIZE_ADDRESS 0x00009850
+#define PHY_BB_DESIRED_SIGSIZE_OFFSET 0x00009850
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB 7
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB 0
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK 0x000000ff
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB 27
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB 20
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK 0x0ff00000
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x) (((x) & 0x0ff00000) >> 20)
+#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x) (((x) << 20) & 0x0ff00000)
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB 29
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB 28
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK 0x30000000
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x) (((x) & 0x30000000) >> 28)
+#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x) (((x) << 28) & 0x30000000)
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB 30
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB 30
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK 0x40000000
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB 31
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB 31
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK 0x80000000
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_3a */
+#define PHY_BB_TIMING_CONTROL_3A_ADDRESS 0x00009854
+#define PHY_BB_TIMING_CONTROL_3A_OFFSET 0x00009854
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB 6
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB 0
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK 0x0000007f
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x) (((x) << 0) & 0x0000007f)
+
+/* macros for BB_find_signal */
+#define PHY_BB_FIND_SIGNAL_ADDRESS 0x00009858
+#define PHY_BB_FIND_SIGNAL_OFFSET 0x00009858
+#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB 5
+#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB 0
+#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK 0x0000003f
+#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_FIND_SIGNAL_RELPWR_MSB 11
+#define PHY_BB_FIND_SIGNAL_RELPWR_LSB 6
+#define PHY_BB_FIND_SIGNAL_RELPWR_MASK 0x00000fc0
+#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB 17
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB 12
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK 0x0003f000
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB 25
+#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB 18
+#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK 0x03fc0000
+#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x) (((x) & 0x03fc0000) >> 18)
+#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x) (((x) << 18) & 0x03fc0000)
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB 31
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB 26
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK 0xfc000000
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for BB_agc */
+#define PHY_BB_AGC_ADDRESS 0x0000985c
+#define PHY_BB_AGC_OFFSET 0x0000985c
+#define PHY_BB_AGC_COARSEPWR_CONST_MSB 6
+#define PHY_BB_AGC_COARSEPWR_CONST_LSB 0
+#define PHY_BB_AGC_COARSEPWR_CONST_MASK 0x0000007f
+#define PHY_BB_AGC_COARSEPWR_CONST_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_AGC_COARSEPWR_CONST_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_BB_AGC_COARSE_LOW_MSB 14
+#define PHY_BB_AGC_COARSE_LOW_LSB 7
+#define PHY_BB_AGC_COARSE_LOW_MASK 0x00007f80
+#define PHY_BB_AGC_COARSE_LOW_GET(x) (((x) & 0x00007f80) >> 7)
+#define PHY_BB_AGC_COARSE_LOW_SET(x) (((x) << 7) & 0x00007f80)
+#define PHY_BB_AGC_COARSE_HIGH_MSB 21
+#define PHY_BB_AGC_COARSE_HIGH_LSB 15
+#define PHY_BB_AGC_COARSE_HIGH_MASK 0x003f8000
+#define PHY_BB_AGC_COARSE_HIGH_GET(x) (((x) & 0x003f8000) >> 15)
+#define PHY_BB_AGC_COARSE_HIGH_SET(x) (((x) << 15) & 0x003f8000)
+#define PHY_BB_AGC_QUICK_DROP_MSB 29
+#define PHY_BB_AGC_QUICK_DROP_LSB 22
+#define PHY_BB_AGC_QUICK_DROP_MASK 0x3fc00000
+#define PHY_BB_AGC_QUICK_DROP_GET(x) (((x) & 0x3fc00000) >> 22)
+#define PHY_BB_AGC_QUICK_DROP_SET(x) (((x) << 22) & 0x3fc00000)
+#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB 31
+#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB 30
+#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK 0xc0000000
+#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for BB_agc_control */
+#define PHY_BB_AGC_CONTROL_ADDRESS 0x00009860
+#define PHY_BB_AGC_CONTROL_OFFSET 0x00009860
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x00000001
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x00000002
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x00000038
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x000003c0
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & 0x000003c0) >> 6)
+#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((x) << 6) & 0x000003c0)
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x00000400
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x00000800
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB 12
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB 12
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK 0x00001000
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB 13
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB 13
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK 0x00002000
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x00008000
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x00010000
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x00020000
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x00040000
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x00080000
+#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x00100000
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((x) << 20) & 0x00100000)
+
+/* macros for BB_cca_b0 */
+#define PHY_BB_CCA_B0_ADDRESS 0x00009864
+#define PHY_BB_CCA_B0_OFFSET 0x00009864
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB 8
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB 0
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK 0x000001ff
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x) (((x) & 0x000001ff) >> 0)
+#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x) (((x) << 0) & 0x000001ff)
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB 11
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB 9
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK 0x00000e00
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x) (((x) << 9) & 0x00000e00)
+#define PHY_BB_CCA_B0_CF_THRESH62_MSB 19
+#define PHY_BB_CCA_B0_CF_THRESH62_LSB 12
+#define PHY_BB_CCA_B0_CF_THRESH62_MASK 0x000ff000
+#define PHY_BB_CCA_B0_CF_THRESH62_GET(x) (((x) & 0x000ff000) >> 12)
+#define PHY_BB_CCA_B0_CF_THRESH62_SET(x) (((x) << 12) & 0x000ff000)
+#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB 28
+#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB 20
+#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK 0x1ff00000
+#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x) (((x) & 0x1ff00000) >> 20)
+
+/* macros for BB_sfcorr */
+#define PHY_BB_SFCORR_ADDRESS 0x00009868
+#define PHY_BB_SFCORR_OFFSET 0x00009868
+#define PHY_BB_SFCORR_M2COUNT_THR_MSB 4
+#define PHY_BB_SFCORR_M2COUNT_THR_LSB 0
+#define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x0000001f
+#define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB 10
+#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB 5
+#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK 0x000007e0
+#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x) (((x) & 0x000007e0) >> 5)
+#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x) (((x) << 5) & 0x000007e0)
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB 16
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB 11
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK 0x0001f800
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x) (((x) & 0x0001f800) >> 11)
+#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x) (((x) << 11) & 0x0001f800)
+#define PHY_BB_SFCORR_M1_THRES_MSB 23
+#define PHY_BB_SFCORR_M1_THRES_LSB 17
+#define PHY_BB_SFCORR_M1_THRES_MASK 0x00fe0000
+#define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_SFCORR_M1_THRES_SET(x) (((x) << 17) & 0x00fe0000)
+#define PHY_BB_SFCORR_M2_THRES_MSB 30
+#define PHY_BB_SFCORR_M2_THRES_LSB 24
+#define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000
+#define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_BB_SFCORR_M2_THRES_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for BB_self_corr_low */
+#define PHY_BB_SELF_CORR_LOW_ADDRESS 0x0000986c
+#define PHY_BB_SELF_CORR_LOW_OFFSET 0x0000986c
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x00000001
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0x000000fe
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & 0x000000fe) >> 1)
+#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((x) << 1) & 0x000000fe)
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x00003f00
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x001fc000
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & 0x001fc000) >> 14)
+#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((x) << 14) & 0x001fc000)
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0x0fe00000
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((x) << 21) & 0x0fe00000)
+
+/* macros for BB_synth_control */
+#define PHY_BB_SYNTH_CONTROL_ADDRESS 0x00009874
+#define PHY_BB_SYNTH_CONTROL_OFFSET 0x00009874
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x0001ffff
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & 0x0001ffff) >> 0)
+#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((x) << 0) & 0x0001ffff)
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x03fe0000
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & 0x03fe0000) >> 17)
+#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((x) << 17) & 0x03fe0000)
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0x0c000000
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & 0x0c000000) >> 26)
+#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((x) << 26) & 0x0c000000)
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((x) << 30) & 0x40000000)
+
+/* macros for BB_addac_clk_select */
+#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS 0x00009878
+#define PHY_BB_ADDAC_CLK_SELECT_OFFSET 0x00009878
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 2
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0x0000000c
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB 5
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB 4
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK 0x00000030
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x) (((x) << 4) & 0x00000030)
+
+/* macros for BB_pll_cntl */
+#define PHY_BB_PLL_CNTL_ADDRESS 0x0000987c
+#define PHY_BB_PLL_CNTL_OFFSET 0x0000987c
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x000003ff
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x00003c00
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & 0x00003c00) >> 10)
+#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((x) << 10) & 0x00003c00)
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0x0000c000
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x00010000
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0x0ffe0000
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & 0x0ffe0000) >> 17)
+#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((x) << 17) & 0x0ffe0000)
+
+/* macros for BB_vit_spur_mask_A */
+#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS 0x00009900
+#define PHY_BB_VIT_SPUR_MASK_A_OFFSET 0x00009900
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB 9
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB 0
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK 0x000003ff
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB 16
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB 10
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK 0x0001fc00
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x) (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x) (((x) << 10) & 0x0001fc00)
+
+/* macros for BB_vit_spur_mask_B */
+#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS 0x00009904
+#define PHY_BB_VIT_SPUR_MASK_B_OFFSET 0x00009904
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB 9
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB 0
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK 0x000003ff
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB 16
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB 10
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK 0x0001fc00
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x) (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x) (((x) << 10) & 0x0001fc00)
+
+/* macros for BB_pilot_spur_mask */
+#define PHY_BB_PILOT_SPUR_MASK_ADDRESS 0x00009908
+#define PHY_BB_PILOT_SPUR_MASK_OFFSET 0x00009908
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB 4
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB 0
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK 0x0000001f
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB 11
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB 5
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK 0x00000fe0
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB 16
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB 12
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK 0x0001f000
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB 23
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB 17
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK 0x00fe0000
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000)
+
+/* macros for BB_chan_spur_mask */
+#define PHY_BB_CHAN_SPUR_MASK_ADDRESS 0x0000990c
+#define PHY_BB_CHAN_SPUR_MASK_OFFSET 0x0000990c
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB 4
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB 0
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK 0x0000001f
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB 11
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB 5
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK 0x00000fe0
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB 16
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB 12
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK 0x0001f000
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB 23
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB 17
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK 0x00fe0000
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17)
+#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000)
+
+/* macros for BB_spectral_scan */
+#define PHY_BB_SPECTRAL_SCAN_ADDRESS 0x00009910
+#define PHY_BB_SPECTRAL_SCAN_OFFSET 0x00009910
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x00000001
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x00000002
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB 2
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB 2
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK 0x00000004
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB 3
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB 3
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK 0x00000008
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB 7
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB 4
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK 0x000000f0
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0x0000ff00
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0x0fff0000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & 0x0fff0000) >> 16)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((x) << 16) & 0x0fff0000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB 28
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB 28
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK 0x10000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB 30
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB 30
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK 0x40000000
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x) (((x) << 30) & 0x40000000)
+
+/* macros for BB_analog_power_on_time */
+#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS 0x00009914
+#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET 0x00009914
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x00003fff
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((x) << 0) & 0x00003fff)
+
+/* macros for BB_search_start_delay */
+#define PHY_BB_SEARCH_START_DELAY_ADDRESS 0x00009918
+#define PHY_BB_SEARCH_START_DELAY_OFFSET 0x00009918
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB 11
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB 0
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK 0x00000fff
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x) (((x) << 0) & 0x00000fff)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB 12
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB 12
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK 0x00001000
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB 13
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB 13
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK 0x00002000
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x) (((x) << 13) & 0x00002000)
+
+/* macros for BB_max_rx_length */
+#define PHY_BB_MAX_RX_LENGTH_ADDRESS 0x0000991c
+#define PHY_BB_MAX_RX_LENGTH_OFFSET 0x0000991c
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0x00000fff
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((x) << 0) & 0x00000fff)
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & 0x3ffff000) >> 12)
+#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((x) << 12) & 0x3ffff000)
+
+/* macros for BB_timing_control_4 */
+#define PHY_BB_TIMING_CONTROL_4_ADDRESS 0x00009920
+#define PHY_BB_TIMING_CONTROL_4_OFFSET 0x00009920
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0x0000f000
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x00010000
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x001e0000
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & 0x001e0000) >> 17)
+#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((x) << 17) & 0x001e0000)
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0x0fe00000
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((x) << 21) & 0x0fe00000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB 30
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB 30
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK 0x40000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_5 */
+#define PHY_BB_TIMING_CONTROL_5_ADDRESS 0x00009924
+#define PHY_BB_TIMING_CONTROL_5_OFFSET 0x00009924
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x00000001
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0x000000fe
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & 0x000000fe) >> 1)
+#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((x) << 1) & 0x000000fe)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x00008000
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x007f0000
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & 0x007f0000) >> 16)
+#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((x) << 16) & 0x007f0000)
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & 0x3f800000) >> 23)
+#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((x) << 23) & 0x3f800000)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB 30
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB 30
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK 0x40000000
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB 31
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB 31
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK 0x80000000
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_phyonly_warm_reset */
+#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS 0x00009928
+#define PHY_BB_PHYONLY_WARM_RESET_OFFSET 0x00009928
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB 0
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB 0
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK 0x00000001
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x) (((x) << 0) & 0x00000001)
+
+/* macros for BB_phyonly_control */
+#define PHY_BB_PHYONLY_CONTROL_ADDRESS 0x0000992c
+#define PHY_BB_PHYONLY_CONTROL_OFFSET 0x0000992c
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x00000001
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x00000002
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB 2
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB 2
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK 0x00000004
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x00000008
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x00000010
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x00000020
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x00000040
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x00000080
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((x) << 7) & 0x00000080)
+
+/* macros for BB_powertx_rate1 */
+#define PHY_BB_POWERTX_RATE1_ADDRESS 0x00009934
+#define PHY_BB_POWERTX_RATE1_OFFSET 0x00009934
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB 5
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB 0
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB 13
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB 8
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB 21
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB 16
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB 29
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB 24
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate2 */
+#define PHY_BB_POWERTX_RATE2_ADDRESS 0x00009938
+#define PHY_BB_POWERTX_RATE2_OFFSET 0x00009938
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB 5
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB 0
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB 13
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB 8
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB 21
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB 16
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB 29
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB 24
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_max */
+#define PHY_BB_POWERTX_MAX_ADDRESS 0x0000993c
+#define PHY_BB_POWERTX_MAX_OFFSET 0x0000993c
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB 6
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB 6
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK 0x00000040
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x) (((x) << 6) & 0x00000040)
+
+/* macros for BB_extension_radar */
+#define PHY_BB_EXTENSION_RADAR_ADDRESS 0x00009940
+#define PHY_BB_EXTENSION_RADAR_OFFSET 0x00009940
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB 13
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB 8
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK 0x00003f00
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB 14
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB 14
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK 0x00004000
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB 22
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB 15
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK 0x007f8000
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x) (((x) & 0x007f8000) >> 15)
+#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x) (((x) << 15) & 0x007f8000)
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 30
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0x7f800000
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & 0x7f800000) >> 23)
+#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((x) << 23) & 0x7f800000)
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB 31
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB 31
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK 0x80000000
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_frame_control */
+#define PHY_BB_FRAME_CONTROL_ADDRESS 0x00009944
+#define PHY_BB_FRAME_CONTROL_OFFSET 0x00009944
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x00000003
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB 2
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB 2
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK 0x00000004
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x00000038
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0x000000c0
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0x0000ff00
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x00010000
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x00020000
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x00040000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB 19
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB 19
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK 0x00080000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x00100000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x00200000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x00400000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x00800000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x01000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x02000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x04000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x08000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB 28
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB 28
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK 0x10000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_timing_control_6 */
+#define PHY_BB_TIMING_CONTROL_6_ADDRESS 0x00009948
+#define PHY_BB_TIMING_CONTROL_6_OFFSET 0x00009948
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0x000000ff
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x00007f00
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & 0x00007f00) >> 8)
+#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((x) << 8) & 0x00007f00)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x001f8000
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & 0x001f8000) >> 15)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((x) << 15) & 0x001f8000)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0x0fe00000
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((x) << 21) & 0x0fe00000)
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB 31
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB 28
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK 0xf0000000
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x) (((x) & 0xf0000000) >> 28)
+#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x) (((x) << 28) & 0xf0000000)
+
+/* macros for BB_spur_mask_controls */
+#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS 0x0000994c
+#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET 0x0000994c
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0x000000ff
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x00000100
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x00020000
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x03fc0000
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & 0x03fc0000) >> 18)
+#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((x) << 18) & 0x03fc0000)
+
+/* macros for BB_rx_iq_corr_b0 */
+#define PHY_BB_RX_IQ_CORR_B0_ADDRESS 0x00009950
+#define PHY_BB_RX_IQ_CORR_B0_OFFSET 0x00009950
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB 6
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB 0
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK 0x0000007f
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB 13
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB 7
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK 0x00003f80
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x00003f80) >> 7)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x) (((x) << 7) & 0x00003f80)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 14
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 14
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x00004000
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 21
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 15
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x003f8000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x003f8000) >> 15)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 15) & 0x003f8000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 28
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 22
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x1fc00000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((x) << 22) & 0x1fc00000)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB 29
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB 29
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x20000000
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((x) << 29) & 0x20000000)
+
+/* macros for BB_radar_detection */
+#define PHY_BB_RADAR_DETECTION_ADDRESS 0x00009954
+#define PHY_BB_RADAR_DETECTION_OFFSET 0x00009954
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x00000001
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB 5
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB 1
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK 0x0000003e
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x) (((x) & 0x0000003e) >> 1)
+#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x) (((x) << 1) & 0x0000003e)
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0x00000fc0
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x0003f000
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB 23
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB 18
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK 0x00fc0000
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x) (((x) << 18) & 0x00fc0000)
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((x) << 24) & 0x7f000000)
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB 31
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB 31
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK 0x80000000
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_radar_detection_2 */
+#define PHY_BB_RADAR_DETECTION_2_ADDRESS 0x00009958
+#define PHY_BB_RADAR_DETECTION_2_OFFSET 0x00009958
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB 7
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB 0
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK 0x000000ff
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x00001f00
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((x) << 8) & 0x00001f00)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 13
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 13
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x00002000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB 14
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB 14
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK 0x00004000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB 15
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB 15
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK 0x00008000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB 21
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB 16
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK 0x003f0000
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB 22
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB 22
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK 0x00400000
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB 23
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB 23
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK 0x00800000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB 26
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB 24
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK 0x07000000
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x) (((x) & 0x07000000) >> 24)
+#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x) (((x) << 24) & 0x07000000)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x08000000
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((x) << 27) & 0x08000000)
+
+/* macros for BB_tx_phase_ramp_b0 */
+#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS 0x0000995c
+#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET 0x0000995c
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x00000001
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x0000007e
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & 0x0000007e) >> 1)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((x) << 1) & 0x0000007e)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x0001ff80
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & 0x0001ff80) >> 7)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((x) << 7) & 0x0001ff80)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x01fe0000
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((x) << 17) & 0x01fe0000)
+
+/* macros for BB_switch_table_chn_b0 */
+#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS 0x00009960
+#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET 0x00009960
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x00000003
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0x0000000c
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x00000030
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0x000000c0
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((x) << 6) & 0x000000c0)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x00000300
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0x00000c00
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & 0x00000c00) >> 10)
+#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((x) << 10) & 0x00000c00)
+
+/* macros for BB_switch_table_com1 */
+#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS 0x00009964
+#define PHY_BB_SWITCH_TABLE_COM1_OFFSET 0x00009964
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 3
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x0000000f
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 7
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 4
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0x000000f0
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 11
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 8
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0x00000f00
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 15
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 12
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x0000f000
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((x) << 12) & 0x0000f000)
+
+/* macros for BB_cca_ctrl_2_b0 */
+#define PHY_BB_CCA_CTRL_2_B0_ADDRESS 0x00009968
+#define PHY_BB_CCA_CTRL_2_B0_OFFSET 0x00009968
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB 8
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB 0
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK 0x000001ff
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x) (((x) & 0x000001ff) >> 0)
+#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x) (((x) << 0) & 0x000001ff)
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB 9
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB 9
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK 0x00000200
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB 17
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB 10
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK 0x0003fc00
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x) (((x) & 0x0003fc00) >> 10)
+#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x) (((x) << 10) & 0x0003fc00)
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB 18
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB 18
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK 0x00040000
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x) (((x) << 18) & 0x00040000)
+
+/* macros for BB_switch_table_com2 */
+#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS 0x0000996c
+#define PHY_BB_SWITCH_TABLE_COM2_OFFSET 0x0000996c
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB 3
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB 0
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK 0x0000000f
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB 7
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB 4
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK 0x000000f0
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB 11
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB 8
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK 0x00000f00
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB 15
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB 12
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK 0x0000f000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB 19
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB 16
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK 0x000f0000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB 23
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB 20
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK 0x00f00000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x) (((x) & 0x00f00000) >> 20)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x) (((x) << 20) & 0x00f00000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB 27
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB 24
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK 0x0f000000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x) (((x) & 0x0f000000) >> 24)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x) (((x) << 24) & 0x0f000000)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB 31
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB 28
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK 0xf0000000
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x) (((x) & 0xf0000000) >> 28)
+#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x) (((x) << 28) & 0xf0000000)
+
+/* macros for BB_restart */
+#define PHY_BB_RESTART_ADDRESS 0x00009970
+#define PHY_BB_RESTART_OFFSET 0x00009970
+#define PHY_BB_RESTART_ENABLE_RESTART_MSB 0
+#define PHY_BB_RESTART_ENABLE_RESTART_LSB 0
+#define PHY_BB_RESTART_ENABLE_RESTART_MASK 0x00000001
+#define PHY_BB_RESTART_ENABLE_RESTART_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_RESTART_ENABLE_RESTART_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB 5
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB 1
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK 0x0000003e
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x) (((x) & 0x0000003e) >> 1)
+#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x) (((x) << 1) & 0x0000003e)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB 6
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB 6
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK 0x00000040
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB 11
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB 7
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK 0x00000f80
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x) (((x) & 0x00000f80) >> 7)
+#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x) (((x) << 7) & 0x00000f80)
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB 17
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB 12
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK 0x0003f000
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB 20
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB 18
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK 0x001c0000
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x) (((x) & 0x001c0000) >> 18)
+#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x) (((x) << 18) & 0x001c0000)
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB 21
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB 21
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK 0x00200000
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB 28
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB 22
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK 0x1fc00000
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x) (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x) (((x) << 22) & 0x1fc00000)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB 29
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB 29
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK 0x20000000
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB 30
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB 30
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK 0x40000000
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB 31
+#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB 31
+#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK 0x80000000
+#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_scrambler_seed */
+#define PHY_BB_SCRAMBLER_SEED_ADDRESS 0x00009978
+#define PHY_BB_SCRAMBLER_SEED_OFFSET 0x00009978
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x0000007f
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((x) << 0) & 0x0000007f)
+
+/* macros for BB_rfbus_request */
+#define PHY_BB_RFBUS_REQUEST_ADDRESS 0x0000997c
+#define PHY_BB_RFBUS_REQUEST_OFFSET 0x0000997c
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x00000001
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((x) << 0) & 0x00000001)
+
+/* macros for BB_timing_control_11 */
+#define PHY_BB_TIMING_CONTROL_11_ADDRESS 0x000099a0
+#define PHY_BB_TIMING_CONTROL_11_OFFSET 0x000099a0
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB 19
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB 0
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK 0x000fffff
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x) (((x) & 0x000fffff) >> 0)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x) (((x) << 0) & 0x000fffff)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & 0x3ff00000) >> 20)
+#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((x) << 20) & 0x3ff00000)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_multichain_enable */
+#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS 0x000099a4
+#define PHY_BB_MULTICHAIN_ENABLE_OFFSET 0x000099a4
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 2
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007)
+
+/* macros for BB_multichain_control */
+#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS 0x000099a8
+#define PHY_BB_MULTICHAIN_CONTROL_OFFSET 0x000099a8
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x00000001
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0x000000fe
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & 0x000000fe) >> 1)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((x) << 1) & 0x000000fe)
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x00000100
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x00000200
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x001ffc00
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & 0x001ffc00) >> 10)
+#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((x) << 10) & 0x001ffc00)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & 0x1fc00000) >> 22)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((x) << 22) & 0x1fc00000)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((x) << 29) & 0x20000000)
+
+/* macros for BB_multichain_gain_ctrl */
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS 0x000099ac
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET 0x000099ac
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB 7
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB 0
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK 0x000000ff
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB 8
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB 8
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK 0x00000100
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB 14
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB 9
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK 0x00007e00
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x) (((x) & 0x00007e00) >> 9)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x) (((x) << 9) & 0x00007e00)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB 20
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB 15
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK 0x001f8000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x) (((x) & 0x001f8000) >> 15)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x) (((x) << 15) & 0x001f8000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB 21
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB 21
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK 0x00200000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB 22
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB 22
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK 0x00400000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB 23
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB 23
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK 0x00800000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x) (((x) << 23) & 0x00800000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB 24
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB 24
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK 0x01000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB 26
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB 25
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK 0x06000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x) (((x) & 0x06000000) >> 25)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x) (((x) << 25) & 0x06000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB 28
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB 27
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK 0x18000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x) (((x) & 0x18000000) >> 27)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x) (((x) << 27) & 0x18000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB 29
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB 29
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK 0x20000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB 30
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB 30
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK 0x40000000
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x) (((x) << 30) & 0x40000000)
+
+/* macros for BB_adc_gain_dc_corr_b0 */
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS 0x000099b4
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET 0x000099b4
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 5
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x0000003f
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 11
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 6
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x00000fc0
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 20
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 12
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x001ff000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & 0x001ff000) >> 12)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((x) << 12) & 0x001ff000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 29
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 21
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & 0x3fe00000) >> 21)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((x) << 21) & 0x3fe00000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 30
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 30
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 31
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 31
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x80000000
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_ext_chan_pwr_thr_1 */
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS 0x000099b8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET 0x000099b8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB 7
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB 0
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK 0x000000ff
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB 15
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB 8
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK 0x0000ff00
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB 20
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB 16
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK 0x001f0000
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB 26
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB 21
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK 0x07e00000
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x) (((x) & 0x07e00000) >> 21)
+#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x) (((x) << 21) & 0x07e00000)
+
+/* macros for BB_ext_chan_pwr_thr_2_b0 */
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS 0x000099bc
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET 0x000099bc
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB 8
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB 0
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK 0x000001ff
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x) (((x) & 0x000001ff) >> 0)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x) (((x) << 0) & 0x000001ff)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB 15
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB 9
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK 0x0000fe00
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x) (((x) & 0x0000fe00) >> 9)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x) (((x) << 9) & 0x0000fe00)
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB 24
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB 16
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK 0x01ff0000
+#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x) (((x) & 0x01ff0000) >> 16)
+
+/* macros for BB_ext_chan_scorr_thr */
+#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS 0x000099c0
+#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET 0x000099c0
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB 6
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB 0
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK 0x0000007f
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x) (((x) & 0x0000007f) >> 0)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x) (((x) << 0) & 0x0000007f)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB 13
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB 7
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK 0x00003f80
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x) (((x) & 0x00003f80) >> 7)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x) (((x) << 7) & 0x00003f80)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB 20
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB 14
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK 0x001fc000
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x) (((x) & 0x001fc000) >> 14)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x) (((x) << 14) & 0x001fc000)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB 27
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB 21
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK 0x0fe00000
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x) (((x) & 0x0fe00000) >> 21)
+#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x) (((x) << 21) & 0x0fe00000)
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB 28
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB 28
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK 0x10000000
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x) (((x) << 28) & 0x10000000)
+
+/* macros for BB_ext_chan_detect_win */
+#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS 0x000099c4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET 0x000099c4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB 3
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB 0
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK 0x0000000f
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB 7
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB 4
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK 0x000000f0
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB 12
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB 8
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK 0x00001f00
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x) (((x) << 8) & 0x00001f00)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB 15
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB 13
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK 0x0000e000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x) (((x) & 0x0000e000) >> 13)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x) (((x) << 13) & 0x0000e000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB 18
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB 16
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK 0x00070000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB 24
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB 19
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK 0x01f80000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x) (((x) & 0x01f80000) >> 19)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x) (((x) << 19) & 0x01f80000)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB 28
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB 25
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK 0x1e000000
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x) (((x) & 0x1e000000) >> 25)
+#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x) (((x) << 25) & 0x1e000000)
+
+/* macros for BB_pwr_thr_20_40_det */
+#define PHY_BB_PWR_THR_20_40_DET_ADDRESS 0x000099c8
+#define PHY_BB_PWR_THR_20_40_DET_OFFSET 0x000099c8
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB 4
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB 0
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK 0x0000001f
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB 10
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB 5
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK 0x000007e0
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x) (((x) & 0x000007e0) >> 5)
+#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x) (((x) << 5) & 0x000007e0)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB 15
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB 11
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK 0x0000f800
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x) (((x) & 0x0000f800) >> 11)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x) (((x) << 11) & 0x0000f800)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB 23
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB 16
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK 0x00ff0000
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB 28
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB 24
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK 0x1f000000
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x) (((x) & 0x1f000000) >> 24)
+#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x) (((x) << 24) & 0x1f000000)
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB 29
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB 29
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK 0x20000000
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB 30
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB 30
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK 0x40000000
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x) (((x) << 30) & 0x40000000)
+
+/* macros for BB_short_gi_delta_slope */
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS 0x000099d0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET 0x000099d0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB 3
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB 0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK 0x0000000f
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB 18
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB 4
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK 0x0007fff0
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x) (((x) & 0x0007fff0) >> 4)
+#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x) (((x) << 4) & 0x0007fff0)
+
+/* macros for BB_chaninfo_ctrl */
+#define PHY_BB_CHANINFO_CTRL_ADDRESS 0x000099dc
+#define PHY_BB_CHANINFO_CTRL_OFFSET 0x000099dc
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x00000002
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((x) << 1) & 0x00000002)
+
+/* macros for BB_heavy_clip_ctrl */
+#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS 0x000099e0
+#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET 0x000099e0
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB 8
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB 0
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK 0x000001ff
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x) (((x) & 0x000001ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x) (((x) << 0) & 0x000001ff)
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB 9
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB 9
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK 0x00000200
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x) (((x) << 9) & 0x00000200)
+
+/* macros for BB_heavy_clip_20 */
+#define PHY_BB_HEAVY_CLIP_20_ADDRESS 0x000099e4
+#define PHY_BB_HEAVY_CLIP_20_OFFSET 0x000099e4
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB 7
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB 0
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK 0x000000ff
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB 15
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB 8
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK 0x0000ff00
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB 23
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB 16
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK 0x00ff0000
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB 31
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB 24
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK 0xff000000
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_heavy_clip_40 */
+#define PHY_BB_HEAVY_CLIP_40_ADDRESS 0x000099e8
+#define PHY_BB_HEAVY_CLIP_40_OFFSET 0x000099e8
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB 7
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB 0
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK 0x000000ff
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB 15
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB 8
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK 0x0000ff00
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB 23
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB 16
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK 0x00ff0000
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB 31
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB 24
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK 0xff000000
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_rifs_srch */
+#define PHY_BB_RIFS_SRCH_ADDRESS 0x000099ec
+#define PHY_BB_RIFS_SRCH_OFFSET 0x000099ec
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB 7
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB 0
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK 0x000000ff
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB 15
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB 8
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK 0x0000ff00
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB 25
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB 16
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK 0x03ff0000
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x) (((x) & 0x03ff0000) >> 16)
+#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x) (((x) << 16) & 0x03ff0000)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB 26
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB 26
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK 0x04000000
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB 27
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB 27
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK 0x08000000
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x) (((x) << 27) & 0x08000000)
+
+/* macros for BB_iq_adc_cal_mode */
+#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS 0x000099f0
+#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET 0x000099f0
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x00000003
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & 0x00000003) >> 0)
+#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((x) << 0) & 0x00000003)
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x00000004
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((x) << 2) & 0x00000004)
+
+/* macros for BB_per_chain_csd */
+#define PHY_BB_PER_CHAIN_CSD_ADDRESS 0x000099fc
+#define PHY_BB_PER_CHAIN_CSD_OFFSET 0x000099fc
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB 4
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB 0
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK 0x0000001f
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB 9
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB 5
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK 0x000003e0
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB 14
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB 10
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK 0x00007c00
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x) (((x) << 10) & 0x00007c00)
+
+/* macros for BB_rx_ocgain */
+#define PHY_BB_RX_OCGAIN_ADDRESS 0x00009a00
+#define PHY_BB_RX_OCGAIN_OFFSET 0x00009a00
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB 31
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB 0
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK 0xffffffff
+#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_crc */
+#define PHY_BB_TX_CRC_ADDRESS 0x00009c00
+#define PHY_BB_TX_CRC_OFFSET 0x00009c00
+#define PHY_BB_TX_CRC_TX_CRC_MSB 15
+#define PHY_BB_TX_CRC_TX_CRC_LSB 0
+#define PHY_BB_TX_CRC_TX_CRC_MASK 0x0000ffff
+#define PHY_BB_TX_CRC_TX_CRC_GET(x) (((x) & 0x0000ffff) >> 0)
+
+/* macros for BB_iq_adc_meas_0_b0 */
+#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS 0x00009c10
+#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET 0x00009c10
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_1_b0 */
+#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS 0x00009c14
+#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET 0x00009c14
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_2_b0 */
+#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS 0x00009c18
+#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET 0x00009c18
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_iq_adc_meas_3_b0 */
+#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS 0x00009c1c
+#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET 0x00009c1c
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff
+#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & 0xffffffff) >> 0)
+
+/* macros for BB_rfbus_grant */
+#define PHY_BB_RFBUS_GRANT_ADDRESS 0x00009c20
+#define PHY_BB_RFBUS_GRANT_OFFSET 0x00009c20
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x00000001
+#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1
+#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1
+#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x00000002
+#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & 0x00000002) >> 1)
+
+/* macros for BB_tstadc */
+#define PHY_BB_TSTADC_ADDRESS 0x00009c24
+#define PHY_BB_TSTADC_OFFSET 0x00009c24
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB 9
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB 0
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK 0x000003ff
+#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB 19
+#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB 10
+#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK 0x000ffc00
+#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10)
+
+/* macros for BB_tstdac */
+#define PHY_BB_TSTDAC_ADDRESS 0x00009c28
+#define PHY_BB_TSTDAC_OFFSET 0x00009c28
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 9
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0x000003ff
+#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 19
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 10
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0x000ffc00
+#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10)
+
+/* macros for BB_illegal_tx_rate */
+#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS 0x00009c30
+#define PHY_BB_ILLEGAL_TX_RATE_OFFSET 0x00009c30
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB 0
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB 0
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK 0x00000001
+#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x) (((x) & 0x00000001) >> 0)
+
+/* macros for BB_spur_report_b0 */
+#define PHY_BB_SPUR_REPORT_B0_ADDRESS 0x00009c34
+#define PHY_BB_SPUR_REPORT_B0_OFFSET 0x00009c34
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0x000000ff
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0x0000ff00
+#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000
+#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & 0xffff0000) >> 16)
+
+/* macros for BB_channel_status */
+#define PHY_BB_CHANNEL_STATUS_ADDRESS 0x00009c38
+#define PHY_BB_CHANNEL_STATUS_OFFSET 0x00009c38
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x00000001
+#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x00000002
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x00000004
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x00000008
+#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x00000030
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0x000000c0
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & 0x000000c0) >> 6)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x00000300
+#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 13
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 10
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x00003c00
+#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & 0x00003c00) >> 10)
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 16
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 14
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x0001c000
+#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & 0x0001c000) >> 14)
+
+/* macros for BB_rssi_b0 */
+#define PHY_BB_RSSI_B0_ADDRESS 0x00009c3c
+#define PHY_BB_RSSI_B0_OFFSET 0x00009c3c
+#define PHY_BB_RSSI_B0_RSSI_0_MSB 7
+#define PHY_BB_RSSI_B0_RSSI_0_LSB 0
+#define PHY_BB_RSSI_B0_RSSI_0_MASK 0x000000ff
+#define PHY_BB_RSSI_B0_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB 15
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB 8
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK 0x0000ff00
+#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x) (((x) & 0x0000ff00) >> 8)
+
+/* macros for BB_spur_est_cck_report_b0 */
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS 0x00009c40
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET 0x00009c40
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB 7
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB 0
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK 0x000000ff
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB 15
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB 8
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK 0x0000ff00
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB 23
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB 16
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK 0x00ff0000
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB 31
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB 24
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK 0xff000000
+#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x) (((x) & 0xff000000) >> 24)
+
+/* macros for BB_chan_info_noise_pwr */
+#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS 0x00009cac
+#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET 0x00009cac
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB 11
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB 0
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK 0x00000fff
+#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x) (((x) & 0x00000fff) >> 0)
+
+/* macros for BB_chan_info_gain_diff */
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS 0x00009cb0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET 0x00009cb0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB 11
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB 0
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK 0x00000fff
+#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x) (((x) & 0x00000fff) >> 0)
+
+/* macros for BB_chan_info_fine_timing */
+#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS 0x00009cb4
+#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET 0x00009cb4
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0x00000fff
+#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x003ff000
+#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & 0x003ff000) >> 12)
+
+/* macros for BB_chan_info_gain_b0 */
+#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS 0x00009cb8
+#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET 0x00009cb8
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0x000000ff
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0x0000ff00
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 16
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 16
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x00010000
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 17
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 17
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x00020000
+#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & 0x00020000) >> 17)
+
+/* macros for BB_chan_info_chan_tab_b0 */
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS 0x00009cbc
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET 0x00009cbc
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB 5
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB 0
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK 0x0000003f
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB 11
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB 6
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK 0x00000fc0
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB 15
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB 12
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK 0x0000f000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB 21
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB 16
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK 0x003f0000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB 27
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB 22
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK 0x0fc00000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x) (((x) & 0x0fc00000) >> 22)
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB 31
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB 28
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK 0xf0000000
+#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x) (((x) & 0xf0000000) >> 28)
+
+/* macros for BB_paprd_am2am_mask */
+#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS 0x00009de4
+#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET 0x00009de4
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 24
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x01ffffff
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_am2pm_mask */
+#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS 0x00009de8
+#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET 0x00009de8
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 24
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x01ffffff
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_ht40_mask */
+#define PHY_BB_PAPRD_HT40_MASK_ADDRESS 0x00009dec
+#define PHY_BB_PAPRD_HT40_MASK_OFFSET 0x00009dec
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 24
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x01ffffff
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
+#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((x) << 0) & 0x01ffffff)
+
+/* macros for BB_paprd_ctrl0 */
+#define PHY_BB_PAPRD_CTRL0_ADDRESS 0x00009df0
+#define PHY_BB_PAPRD_CTRL0_OFFSET 0x00009df0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB 0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB 0
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK 0x00000001
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB 1
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB 1
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK 0x00000002
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB 26
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB 2
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK 0x07fffffc
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x) (((x) & 0x07fffffc) >> 2)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x) (((x) << 2) & 0x07fffffc)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB 31
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB 27
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK 0xf8000000
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x) (((x) & 0xf8000000) >> 27)
+#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x) (((x) << 27) & 0xf8000000)
+
+/* macros for BB_paprd_ctrl1 */
+#define PHY_BB_PAPRD_CTRL1_ADDRESS 0x00009df4
+#define PHY_BB_PAPRD_CTRL1_OFFSET 0x00009df4
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB 0
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB 0
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK 0x00000001
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB 1
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB 1
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK 0x00000002
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB 2
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB 2
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK 0x00000004
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB 8
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB 3
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK 0x000001f8
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x) (((x) & 0x000001f8) >> 3)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x) (((x) << 3) & 0x000001f8)
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB 16
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB 9
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK 0x0001fe00
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x) (((x) & 0x0001fe00) >> 9)
+#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x) (((x) << 9) & 0x0001fe00)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB 26
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB 17
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK 0x07fe0000
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x) (((x) & 0x07fe0000) >> 17)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x) (((x) << 17) & 0x07fe0000)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB 27
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB 27
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK 0x08000000
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x) (((x) << 27) & 0x08000000)
+
+/* macros for BB_pa_gain123 */
+#define PHY_BB_PA_GAIN123_ADDRESS 0x00009df8
+#define PHY_BB_PA_GAIN123_OFFSET 0x00009df8
+#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB 9
+#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB 0
+#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK 0x000003ff
+#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB 19
+#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB 10
+#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK 0x000ffc00
+#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x) (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x) (((x) << 10) & 0x000ffc00)
+#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB 29
+#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB 20
+#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK 0x3ff00000
+#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x) (((x) & 0x3ff00000) >> 20)
+#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x) (((x) << 20) & 0x3ff00000)
+
+/* macros for BB_pa_gain45 */
+#define PHY_BB_PA_GAIN45_ADDRESS 0x00009dfc
+#define PHY_BB_PA_GAIN45_OFFSET 0x00009dfc
+#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB 9
+#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB 0
+#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK 0x000003ff
+#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB 19
+#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB 10
+#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK 0x000ffc00
+#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x) (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x) (((x) << 10) & 0x000ffc00)
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB 24
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB 20
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK 0x01f00000
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x) (((x) << 20) & 0x01f00000)
+
+/* macros for BB_paprd_pre_post_scale_0 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS 0x00009e00
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET 0x00009e00
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_1 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS 0x00009e04
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET 0x00009e04
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_2 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS 0x00009e08
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET 0x00009e08
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_3 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS 0x00009e0c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET 0x00009e0c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_4 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS 0x00009e10
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET 0x00009e10
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_5 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS 0x00009e14
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET 0x00009e14
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_6 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS 0x00009e18
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET 0x00009e18
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_pre_post_scale_7 */
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS 0x00009e1c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET 0x00009e1c
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB 17
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB 0
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK 0x0003ffff
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x) (((x) & 0x0003ffff) >> 0)
+#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x) (((x) << 0) & 0x0003ffff)
+
+/* macros for BB_paprd_mem_tab */
+#define PHY_BB_PAPRD_MEM_TAB_ADDRESS 0x00009e20
+#define PHY_BB_PAPRD_MEM_TAB_OFFSET 0x00009e20
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB 21
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB 0
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK 0x003fffff
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x) (((x) & 0x003fffff) >> 0)
+#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x) (((x) << 0) & 0x003fffff)
+
+/* macros for BB_peak_det_ctrl_1 */
+#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS 0x0000a000
+#define PHY_BB_PEAK_DET_CTRL_1_OFFSET 0x0000a000
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB 0
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB 0
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK 0x00000001
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB 1
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB 1
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK 0x00000002
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB 7
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB 2
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK 0x000000fc
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x) (((x) & 0x000000fc) >> 2)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x) (((x) << 2) & 0x000000fc)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB 12
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB 8
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK 0x00001f00
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x) (((x) & 0x00001f00) >> 8)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x) (((x) << 8) & 0x00001f00)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB 17
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB 13
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK 0x0003e000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x) (((x) & 0x0003e000) >> 13)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x) (((x) << 13) & 0x0003e000)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB 22
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB 18
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK 0x007c0000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x) (((x) & 0x007c0000) >> 18)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x) (((x) << 18) & 0x007c0000)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB 29
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB 23
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK 0x3f800000
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x) (((x) & 0x3f800000) >> 23)
+#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x) (((x) << 23) & 0x3f800000)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB 30
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB 30
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK 0x40000000
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB 31
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB 31
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK 0x80000000
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_peak_det_ctrl_2 */
+#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS 0x0000a004
+#define PHY_BB_PEAK_DET_CTRL_2_OFFSET 0x0000a004
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB 9
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB 0
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK 0x000003ff
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB 14
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB 10
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK 0x00007c00
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB 19
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB 15
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK 0x000f8000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x) (((x) & 0x000f8000) >> 15)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x) (((x) << 15) & 0x000f8000)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB 24
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB 20
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK 0x01f00000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB 29
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB 25
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK 0x3e000000
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_rx_gain_bounds_1 */
+#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS 0x0000a008
+#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET 0x0000a008
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB 7
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB 0
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK 0x000000ff
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB 15
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB 8
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK 0x0000ff00
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB 23
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB 16
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK 0x00ff0000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB 24
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB 24
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK 0x01000000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB 25
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB 25
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK 0x02000000
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x) (((x) << 25) & 0x02000000)
+
+/* macros for BB_rx_gain_bounds_2 */
+#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS 0x0000a00c
+#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET 0x0000a00c
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB 7
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB 0
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK 0x000000ff
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB 15
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB 8
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK 0x0000ff00
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB 23
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB 16
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK 0x00ff0000
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB 31
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB 24
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK 0xff000000
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_peak_det_cal_ctrl */
+#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS 0x0000a010
+#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET 0x0000a010
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB 5
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB 0
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK 0x0000003f
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB 11
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB 6
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK 0x00000fc0
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB 13
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB 12
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK 0x00003000
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12)
+#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000)
+
+/* macros for BB_agc_dig_dc_ctrl */
+#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS 0x0000a014
+#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET 0x0000a014
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB 0
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB 0
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK 0x00000001
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB 3
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB 1
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK 0x0000000e
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB 9
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB 4
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK 0x000003f0
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x) (((x) & 0x000003f0) >> 4)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x) (((x) << 4) & 0x000003f0)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB 31
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB 16
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK 0xffff0000
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x) (((x) & 0xffff0000) >> 16)
+#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x) (((x) << 16) & 0xffff0000)
+
+/* macros for BB_agc_dig_dc_status_i_b0 */
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS 0x0000a018
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET 0x0000a018
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB 8
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB 0
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK 0x000001ff
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x) (((x) & 0x000001ff) >> 0)
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB 17
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB 9
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK 0x0003fe00
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x) (((x) & 0x0003fe00) >> 9)
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB 26
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB 18
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK 0x07fc0000
+#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x) (((x) & 0x07fc0000) >> 18)
+
+/* macros for BB_agc_dig_dc_status_q_b0 */
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS 0x0000a01c
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET 0x0000a01c
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB 8
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB 0
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK 0x000001ff
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x) (((x) & 0x000001ff) >> 0)
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB 17
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB 9
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK 0x0003fe00
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x) (((x) & 0x0003fe00) >> 9)
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB 26
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB 18
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK 0x07fc0000
+#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x) (((x) & 0x07fc0000) >> 18)
+
+/* macros for BB_bbb_txfir_0 */
+#define PHY_BB_BBB_TXFIR_0_ADDRESS 0x0000a1f4
+#define PHY_BB_BBB_TXFIR_0_OFFSET 0x0000a1f4
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0x0000000f
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0x00000f00
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x001f0000
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & 0x1f000000) >> 24)
+#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((x) << 24) & 0x1f000000)
+
+/* macros for BB_bbb_txfir_1 */
+#define PHY_BB_BBB_TXFIR_1_ADDRESS 0x0000a1f8
+#define PHY_BB_BBB_TXFIR_1_OFFSET 0x0000a1f8
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x0000003f
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x00003f00
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x007f0000
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & 0x007f0000) >> 16)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((x) << 16) & 0x007f0000)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((x) << 24) & 0x7f000000)
+
+/* macros for BB_bbb_txfir_2 */
+#define PHY_BB_BBB_TXFIR_2_ADDRESS 0x0000a1fc
+#define PHY_BB_BBB_TXFIR_2_OFFSET 0x0000a1fc
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0x000000ff
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0x0000ff00
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0x00ff0000
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_modes_select */
+#define PHY_BB_MODES_SELECT_ADDRESS 0x0000a200
+#define PHY_BB_MODES_SELECT_OFFSET 0x0000a200
+#define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0
+#define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0
+#define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x00000001
+#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x00000004
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x00000020
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x00000040
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x00000080
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x00000100
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((x) << 8) & 0x00000100)
+
+/* macros for BB_bbb_tx_ctrl */
+#define PHY_BB_BBB_TX_CTRL_ADDRESS 0x0000a204
+#define PHY_BB_BBB_TX_CTRL_OFFSET 0x0000a204
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x00000001
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x00000002
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0x0000000c
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x00000010
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x00000020
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x000001c0
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & 0x000001c0) >> 6)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((x) << 6) & 0x000001c0)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0x00000e00
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & 0x00000e00) >> 9)
+#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((x) << 9) & 0x00000e00)
+
+/* macros for BB_bbb_sig_detect */
+#define PHY_BB_BBB_SIG_DETECT_ADDRESS 0x0000a208
+#define PHY_BB_BBB_SIG_DETECT_OFFSET 0x0000a208
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB 5
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB 0
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK 0x0000003f
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB 12
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB 6
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK 0x00001fc0
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x) (((x) & 0x00001fc0) >> 6)
+#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x) (((x) << 6) & 0x00001fc0)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB 13
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB 13
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK 0x00002000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB 14
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB 14
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK 0x00004000
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB 15
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB 15
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK 0x00008000
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB 16
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB 16
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK 0x00010000
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB 17
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB 17
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK 0x00020000
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB 18
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB 18
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK 0x00040000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB 19
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB 19
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK 0x00080000
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB 20
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB 20
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK 0x00100000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB 21
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB 21
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK 0x00200000
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB 22
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB 22
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK 0x00400000
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB 31
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB 31
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK 0x80000000
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_ext_atten_switch_ctl_b0 */
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS 0x0000a20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET 0x0000a20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB 5
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB 0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK 0x0000003f
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB 11
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB 6
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK 0x00000fc0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB 16
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB 12
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK 0x0001f000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB 21
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB 17
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK 0x003e0000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x) (((x) << 17) & 0x003e0000)
+
+/* macros for BB_bbb_rx_ctrl_1 */
+#define PHY_BB_BBB_RX_CTRL_1_ADDRESS 0x0000a210
+#define PHY_BB_BBB_RX_CTRL_1_OFFSET 0x0000a210
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB 2
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB 0
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK 0x00000007
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB 7
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB 3
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK 0x000000f8
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x) (((x) & 0x000000f8) >> 3)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x) (((x) << 3) & 0x000000f8)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB 10
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB 8
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK 0x00000700
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x) (((x) & 0x00000700) >> 8)
+#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x) (((x) << 8) & 0x00000700)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB 15
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB 11
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK 0x0000f800
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x) (((x) & 0x0000f800) >> 11)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x) (((x) << 11) & 0x0000f800)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB 20
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB 16
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK 0x001f0000
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB 23
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB 21
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK 0x00e00000
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x) (((x) & 0x00e00000) >> 21)
+#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x) (((x) << 21) & 0x00e00000)
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB 30
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB 24
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK 0x7f000000
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x) (((x) & 0x7f000000) >> 24)
+#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x) (((x) << 24) & 0x7f000000)
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB 31
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB 31
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK 0x80000000
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_bbb_rx_ctrl_2 */
+#define PHY_BB_BBB_RX_CTRL_2_ADDRESS 0x0000a214
+#define PHY_BB_BBB_RX_CTRL_2_OFFSET 0x0000a214
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB 5
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB 0
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK 0x0000003f
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB 11
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB 6
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK 0x00000fc0
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB 16
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB 12
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK 0x0001f000
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB 21
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB 17
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK 0x003e0000
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x) (((x) << 17) & 0x003e0000)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB 25
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB 22
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK 0x03c00000
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x) (((x) & 0x03c00000) >> 22)
+#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x) (((x) << 22) & 0x03c00000)
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB 31
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB 26
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK 0xfc000000
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x) (((x) & 0xfc000000) >> 26)
+#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x) (((x) << 26) & 0xfc000000)
+
+/* macros for BB_bbb_rx_ctrl_3 */
+#define PHY_BB_BBB_RX_CTRL_3_ADDRESS 0x0000a218
+#define PHY_BB_BBB_RX_CTRL_3_OFFSET 0x0000a218
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB 7
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB 0
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK 0x000000ff
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB 15
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB 8
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK 0x0000ff00
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB 23
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB 16
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK 0x00ff0000
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x) (((x) << 16) & 0x00ff0000)
+
+/* macros for BB_bbb_rx_ctrl_4 */
+#define PHY_BB_BBB_RX_CTRL_4_ADDRESS 0x0000a21c
+#define PHY_BB_BBB_RX_CTRL_4_OFFSET 0x0000a21c
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB 3
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB 0
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK 0x0000000f
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB 15
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB 4
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK 0x0000fff0
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x) (((x) & 0x0000fff0) >> 4)
+#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x) (((x) << 4) & 0x0000fff0)
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB 16
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB 16
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK 0x00010000
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB 17
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB 17
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK 0x00020000
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB 18
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB 18
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK 0x00040000
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB 24
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB 19
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK 0x01f80000
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x) (((x) & 0x01f80000) >> 19)
+#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x) (((x) << 19) & 0x01f80000)
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB 30
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB 25
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK 0x7e000000
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x) (((x) & 0x7e000000) >> 25)
+#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x) (((x) << 25) & 0x7e000000)
+
+/* macros for BB_bbb_rx_ctrl_5 */
+#define PHY_BB_BBB_RX_CTRL_5_ADDRESS 0x0000a220
+#define PHY_BB_BBB_RX_CTRL_5_OFFSET 0x0000a220
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB 4
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB 0
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK 0x0000001f
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB 9
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB 5
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK 0x000003e0
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB 15
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB 10
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK 0x0000fc00
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x) (((x) & 0x0000fc00) >> 10)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x) (((x) << 10) & 0x0000fc00)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB 20
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB 16
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK 0x001f0000
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB 26
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB 21
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK 0x07e00000
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x) (((x) & 0x07e00000) >> 21)
+#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x) (((x) << 21) & 0x07e00000)
+
+/* macros for BB_bbb_rx_ctrl_6 */
+#define PHY_BB_BBB_RX_CTRL_6_ADDRESS 0x0000a224
+#define PHY_BB_BBB_RX_CTRL_6_OFFSET 0x0000a224
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB 9
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB 0
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK 0x000003ff
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB 10
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB 10
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK 0x00000400
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB 20
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB 11
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK 0x001ff800
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x) (((x) & 0x001ff800) >> 11)
+#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x) (((x) << 11) & 0x001ff800)
+
+/* macros for BB_bbb_dagc_ctrl */
+#define PHY_BB_BBB_DAGC_CTRL_ADDRESS 0x0000a228
+#define PHY_BB_BBB_DAGC_CTRL_OFFSET 0x0000a228
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB 0
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB 0
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK 0x00000001
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB 8
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB 1
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK 0x000001fe
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x) (((x) & 0x000001fe) >> 1)
+#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x) (((x) << 1) & 0x000001fe)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB 9
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB 9
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK 0x00000200
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB 16
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB 10
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK 0x0001fc00
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x) (((x) & 0x0001fc00) >> 10)
+#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x) (((x) << 10) & 0x0001fc00)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB 17
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB 17
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK 0x00020000
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB 23
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB 18
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK 0x00fc0000
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x) (((x) << 18) & 0x00fc0000)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB 27
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB 24
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK 0x0f000000
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x) (((x) & 0x0f000000) >> 24)
+#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x) (((x) << 24) & 0x0f000000)
+
+/* macros for BB_force_clken_cck */
+#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS 0x0000a22c
+#define PHY_BB_FORCE_CLKEN_CCK_OFFSET 0x0000a22c
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB 0
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB 0
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK 0x00000001
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB 1
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB 1
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK 0x00000002
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB 2
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB 2
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK 0x00000004
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB 3
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB 3
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK 0x00000008
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB 4
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB 4
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK 0x00000010
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB 5
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB 5
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK 0x00000020
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x) (((x) << 5) & 0x00000020)
+
+/* macros for BB_rx_clear_delay */
+#define PHY_BB_RX_CLEAR_DELAY_ADDRESS 0x0000a230
+#define PHY_BB_RX_CLEAR_DELAY_OFFSET 0x0000a230
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB 9
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB 0
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK 0x000003ff
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x) (((x) << 0) & 0x000003ff)
+
+/* macros for BB_powertx_rate3 */
+#define PHY_BB_POWERTX_RATE3_ADDRESS 0x0000a234
+#define PHY_BB_POWERTX_RATE3_OFFSET 0x0000a234
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB 5
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB 0
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB 21
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB 16
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB 29
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB 24
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate4 */
+#define PHY_BB_POWERTX_RATE4_ADDRESS 0x0000a238
+#define PHY_BB_POWERTX_RATE4_OFFSET 0x0000a238
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB 5
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB 0
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB 13
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB 8
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB 21
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB 16
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB 29
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB 24
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_cck_spur_mit */
+#define PHY_BB_CCK_SPUR_MIT_ADDRESS 0x0000a240
+#define PHY_BB_CCK_SPUR_MIT_OFFSET 0x0000a240
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB 0
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB 0
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK 0x00000001
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB 8
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB 1
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK 0x000001fe
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x) (((x) & 0x000001fe) >> 1)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x) (((x) << 1) & 0x000001fe)
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB 28
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB 9
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK 0x1ffffe00
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x) (((x) & 0x1ffffe00) >> 9)
+#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x) (((x) << 9) & 0x1ffffe00)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB 30
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB 29
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK 0x60000000
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x) (((x) << 29) & 0x60000000)
+
+/* macros for BB_panic_watchdog_status */
+#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS 0x0000a244
+#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET 0x0000a244
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB 2
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB 0
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK 0x00000007
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB 3
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB 3
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK 0x00000008
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB 7
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB 4
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK 0x000000f0
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB 11
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB 8
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK 0x00000f00
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x) (((x) & 0x00000f00) >> 8)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x) (((x) << 8) & 0x00000f00)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB 15
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB 12
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK 0x0000f000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB 19
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB 16
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK 0x000f0000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x) (((x) & 0x000f0000) >> 16)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x) (((x) << 16) & 0x000f0000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB 23
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB 20
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK 0x00f00000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x) (((x) & 0x00f00000) >> 20)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x) (((x) << 20) & 0x00f00000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB 27
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB 24
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK 0x0f000000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x) (((x) & 0x0f000000) >> 24)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x) (((x) << 24) & 0x0f000000)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB 31
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB 28
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK 0xf0000000
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x) (((x) & 0xf0000000) >> 28)
+#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x) (((x) << 28) & 0xf0000000)
+
+/* macros for BB_panic_watchdog_ctrl_1 */
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS 0x0000a248
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET 0x0000a248
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB 0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB 0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK 0x00000001
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB 1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB 1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK 0x00000002
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB 15
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB 2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK 0x0000fffc
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x) (((x) & 0x0000fffc) >> 2)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x) (((x) << 2) & 0x0000fffc)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB 31
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB 16
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK 0xffff0000
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x) (((x) & 0xffff0000) >> 16)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x) (((x) << 16) & 0xffff0000)
+
+/* macros for BB_panic_watchdog_ctrl_2 */
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS 0x0000a24c
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET 0x0000a24c
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x00000001
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB 1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB 1
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK 0x00000002
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB 2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB 2
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK 0x00000004
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x) (((x) << 2) & 0x00000004)
+
+/* macros for BB_iqcorr_ctrl_cck */
+#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS 0x0000a250
+#define PHY_BB_IQCORR_CTRL_CCK_OFFSET 0x0000a250
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB 4
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB 0
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK 0x0000001f
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB 10
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB 5
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK 0x000007e0
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x) (((x) & 0x000007e0) >> 5)
+#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x) (((x) << 5) & 0x000007e0)
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB 11
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB 11
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK 0x00000800
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB 13
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB 12
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK 0x00003000
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12)
+#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000)
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB 15
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB 14
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK 0x0000c000
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB 20
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB 16
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK 0x001f0000
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB 21
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB 21
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK 0x00200000
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x) (((x) << 21) & 0x00200000)
+
+/* macros for BB_bluetooth_cntl */
+#define PHY_BB_BLUETOOTH_CNTL_ADDRESS 0x0000a254
+#define PHY_BB_BLUETOOTH_CNTL_OFFSET 0x0000a254
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x00000001
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x00000002
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((x) << 1) & 0x00000002)
+
+/* macros for BB_tpc_1 */
+#define PHY_BB_TPC_1_ADDRESS 0x0000a258
+#define PHY_BB_TPC_1_OFFSET 0x0000a258
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB 0
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB 0
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK 0x00000001
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB 5
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB 1
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK 0x0000003e
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x) (((x) & 0x0000003e) >> 1)
+#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x) (((x) << 1) & 0x0000003e)
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB 13
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB 6
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK 0x00003fc0
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x) (((x) & 0x00003fc0) >> 6)
+#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x) (((x) << 6) & 0x00003fc0)
+#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB 15
+#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB 14
+#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK 0x0000c000
+#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x) (((x) & 0x0000c000) >> 14)
+#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x) (((x) << 14) & 0x0000c000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB 17
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB 16
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK 0x00030000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x) (((x) & 0x00030000) >> 16)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x) (((x) << 16) & 0x00030000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB 19
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB 18
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK 0x000c0000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x) (((x) & 0x000c0000) >> 18)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x) (((x) << 18) & 0x000c0000)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB 21
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB 20
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK 0x00300000
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x) (((x) & 0x00300000) >> 20)
+#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x) (((x) << 20) & 0x00300000)
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB 22
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB 22
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK 0x00400000
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB 28
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB 23
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK 0x1f800000
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x) (((x) & 0x1f800000) >> 23)
+#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x) (((x) << 23) & 0x1f800000)
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB 29
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB 29
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK 0x20000000
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB 31
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB 30
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK 0xc0000000
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x) (((x) & 0xc0000000) >> 30)
+#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x) (((x) << 30) & 0xc0000000)
+
+/* macros for BB_tpc_2 */
+#define PHY_BB_TPC_2_ADDRESS 0x0000a25c
+#define PHY_BB_TPC_2_OFFSET 0x0000a25c
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0x000000ff
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0x0000ff00
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0x00ff0000
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((x) << 16) & 0x00ff0000)
+
+/* macros for BB_tpc_3 */
+#define PHY_BB_TPC_3_ADDRESS 0x0000a260
+#define PHY_BB_TPC_3_OFFSET 0x0000a260
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0x000000ff
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0x0000ff00
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB 18
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB 16
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK 0x00070000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB 21
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB 19
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK 0x00380000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x) (((x) & 0x00380000) >> 19)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x) (((x) << 19) & 0x00380000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 24
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 22
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0x01c00000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & 0x01c00000) >> 22)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((x) << 22) & 0x01c00000)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 27
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 25
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x0e000000
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & 0x0e000000) >> 25)
+#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((x) << 25) & 0x0e000000)
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 31
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 31
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x80000000
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_tpc_4_b0 */
+#define PHY_BB_TPC_4_B0_ADDRESS 0x0000a264
+#define PHY_BB_TPC_4_B0_OFFSET 0x0000a264
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB 0
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB 0
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK 0x00000001
+#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB 8
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB 1
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK 0x000001fe
+#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x) (((x) & 0x000001fe) >> 1)
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB 13
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB 9
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK 0x00003e00
+#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x) (((x) & 0x00003e00) >> 9)
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB 19
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB 14
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK 0x000fc000
+#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x) (((x) & 0x000fc000) >> 14)
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB 24
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB 20
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK 0x01f00000
+#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB 30
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB 25
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK 0x7e000000
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x) (((x) & 0x7e000000) >> 25)
+#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x) (((x) << 25) & 0x7e000000)
+
+/* macros for BB_analog_swap */
+#define PHY_BB_ANALOG_SWAP_ADDRESS 0x0000a268
+#define PHY_BB_ANALOG_SWAP_OFFSET 0x0000a268
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x00000007
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x00000038
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & 0x00000038) >> 3)
+#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((x) << 3) & 0x00000038)
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x00000040
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x00000080
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x00000100
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((x) << 8) & 0x00000100)
+
+/* macros for BB_tpc_5_b0 */
+#define PHY_BB_TPC_5_B0_ADDRESS 0x0000a26c
+#define PHY_BB_TPC_5_B0_OFFSET 0x0000a26c
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB 3
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB 0
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK 0x0000000f
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB 9
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB 4
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK 0x000003f0
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x) (((x) & 0x000003f0) >> 4)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x) (((x) << 4) & 0x000003f0)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB 15
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB 10
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK 0x0000fc00
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x) (((x) & 0x0000fc00) >> 10)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x) (((x) << 10) & 0x0000fc00)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB 21
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB 16
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK 0x003f0000
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB 27
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB 22
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK 0x0fc00000
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x) (((x) & 0x0fc00000) >> 22)
+#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x) (((x) << 22) & 0x0fc00000)
+
+/* macros for BB_tpc_6_b0 */
+#define PHY_BB_TPC_6_B0_ADDRESS 0x0000a270
+#define PHY_BB_TPC_6_B0_OFFSET 0x0000a270
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB 5
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB 0
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK 0x0000003f
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB 11
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB 6
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK 0x00000fc0
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB 17
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB 12
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK 0x0003f000
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB 23
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB 18
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK 0x00fc0000
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x) (((x) << 18) & 0x00fc0000)
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB 25
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB 24
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK 0x03000000
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB 28
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB 26
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK 0x1c000000
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x) (((x) & 0x1c000000) >> 26)
+#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x) (((x) << 26) & 0x1c000000)
+
+/* macros for BB_tpc_7 */
+#define PHY_BB_TPC_7_ADDRESS 0x0000a274
+#define PHY_BB_TPC_7_OFFSET 0x0000a274
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x0000003f
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB 11
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB 6
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK 0x00000fc0
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 12
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 12
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x00001000
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 13
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 13
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x00002000
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 14
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 14
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x00004000
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 15
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 15
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x00008000
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((x) << 15) & 0x00008000)
+
+/* macros for BB_tpc_8 */
+#define PHY_BB_TPC_8_ADDRESS 0x0000a278
+#define PHY_BB_TPC_8_OFFSET 0x0000a278
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB 4
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB 0
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK 0x0000001f
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB 9
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB 5
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK 0x000003e0
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB 14
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB 10
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK 0x00007c00
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB 19
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB 15
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK 0x000f8000
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x) (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x) (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB 24
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB 20
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK 0x01f00000
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB 29
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB 25
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK 0x3e000000
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_9 */
+#define PHY_BB_TPC_9_ADDRESS 0x0000a27c
+#define PHY_BB_TPC_9_OFFSET 0x0000a27c
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB 4
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB 0
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK 0x0000001f
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB 9
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB 5
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK 0x000003e0
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB 14
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB 10
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK 0x00007c00
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB 20
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB 20
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK 0x00100000
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB 26
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB 21
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK 0x07e00000
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x) (((x) & 0x07e00000) >> 21)
+#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x) (((x) << 21) & 0x07e00000)
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 30
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 27
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x78000000
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((x) << 27) & 0x78000000)
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB 31
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB 31
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK 0x80000000
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_pdadc_tab_b0 */
+#define PHY_BB_PDADC_TAB_B0_ADDRESS 0x0000a280
+#define PHY_BB_PDADC_TAB_B0_OFFSET 0x0000a280
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB 31
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB 0
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK 0xffffffff
+#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_tab_b0 */
+#define PHY_BB_CL_TAB_B0_ADDRESS 0x0000a300
+#define PHY_BB_CL_TAB_B0_OFFSET 0x0000a300
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x0000001f
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0x0000ffe0
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & 0x0000ffe0) >> 5)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((x) << 5) & 0x0000ffe0)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x07ff0000
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & 0x07ff0000) >> 16)
+#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((x) << 16) & 0x07ff0000)
+#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30
+#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27
+#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000
+#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & 0x78000000) >> 27)
+#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((x) << 27) & 0x78000000)
+
+/* macros for BB_cl_map_0_b0 */
+#define PHY_BB_CL_MAP_0_B0_ADDRESS 0x0000a340
+#define PHY_BB_CL_MAP_0_B0_OFFSET 0x0000a340
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_1_b0 */
+#define PHY_BB_CL_MAP_1_B0_ADDRESS 0x0000a344
+#define PHY_BB_CL_MAP_1_B0_OFFSET 0x0000a344
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_2_b0 */
+#define PHY_BB_CL_MAP_2_B0_ADDRESS 0x0000a348
+#define PHY_BB_CL_MAP_2_B0_OFFSET 0x0000a348
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_3_b0 */
+#define PHY_BB_CL_MAP_3_B0_ADDRESS 0x0000a34c
+#define PHY_BB_CL_MAP_3_B0_OFFSET 0x0000a34c
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_cal_ctrl */
+#define PHY_BB_CL_CAL_CTRL_ADDRESS 0x0000a358
+#define PHY_BB_CL_CAL_CTRL_OFFSET 0x0000a358
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x00000001
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x00000002
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0x0000000c
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0x000000f0
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & 0x000000f0) >> 4)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((x) << 4) & 0x000000f0)
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0x0000ff00
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x003f0000
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & 0x3fc00000) >> 22)
+#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((x) << 22) & 0x3fc00000)
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((x) << 30) & 0x40000000)
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_cl_map_pal_0_b0 */
+#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS 0x0000a35c
+#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET 0x0000a35c
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB 31
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB 0
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK 0xffffffff
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_1_b0 */
+#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS 0x0000a360
+#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET 0x0000a360
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB 31
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB 0
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK 0xffffffff
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_2_b0 */
+#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS 0x0000a364
+#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET 0x0000a364
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB 31
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB 0
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK 0xffffffff
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_cl_map_pal_3_b0 */
+#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS 0x0000a368
+#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET 0x0000a368
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB 31
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB 0
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK 0xffffffff
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_rifs */
+#define PHY_BB_RIFS_ADDRESS 0x0000a388
+#define PHY_BB_RIFS_OFFSET 0x0000a388
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB 25
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB 25
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK 0x02000000
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x04000000
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB 27
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB 27
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK 0x08000000
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x) (((x) << 27) & 0x08000000)
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB 28
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB 28
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK 0x10000000
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x) (((x) << 28) & 0x10000000)
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB 29
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB 29
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK 0x20000000
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x) (((x) & 0x20000000) >> 29)
+#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x) (((x) << 29) & 0x20000000)
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB 30
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB 30
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK 0x40000000
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x) (((x) & 0x40000000) >> 30)
+#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x) (((x) << 30) & 0x40000000)
+
+/* macros for BB_powertx_rate5 */
+#define PHY_BB_POWERTX_RATE5_ADDRESS 0x0000a38c
+#define PHY_BB_POWERTX_RATE5_OFFSET 0x0000a38c
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB 5
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB 0
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB 13
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB 8
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB 21
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB 16
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB 29
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB 24
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate6 */
+#define PHY_BB_POWERTX_RATE6_ADDRESS 0x0000a390
+#define PHY_BB_POWERTX_RATE6_OFFSET 0x0000a390
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB 5
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB 0
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB 13
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB 8
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB 21
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB 16
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB 29
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB 24
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_tpc_10 */
+#define PHY_BB_TPC_10_ADDRESS 0x0000a394
+#define PHY_BB_TPC_10_OFFSET 0x0000a394
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB 4
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB 0
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK 0x0000001f
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB 9
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB 5
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK 0x000003e0
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB 14
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB 10
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK 0x00007c00
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB 19
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB 15
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK 0x000f8000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x) (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x) (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB 24
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB 20
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK 0x01f00000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB 29
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB 25
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK 0x3e000000
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_11_b0 */
+#define PHY_BB_TPC_11_B0_ADDRESS 0x0000a398
+#define PHY_BB_TPC_11_B0_OFFSET 0x0000a398
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB 4
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB 0
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK 0x0000001f
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB 9
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB 5
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK 0x000003e0
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 23
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 16
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0x00ff0000
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB 31
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB 24
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK 0xff000000
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x) (((x) & 0xff000000) >> 24)
+#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x) (((x) << 24) & 0xff000000)
+
+/* macros for BB_cal_chain_mask */
+#define PHY_BB_CAL_CHAIN_MASK_ADDRESS 0x0000a39c
+#define PHY_BB_CAL_CHAIN_MASK_OFFSET 0x0000a39c
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 2
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0x00000007
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007)
+
+/* macros for BB_powertx_sub */
+#define PHY_BB_POWERTX_SUB_ADDRESS 0x0000a3bc
+#define PHY_BB_POWERTX_SUB_OFFSET 0x0000a3bc
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 5
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 0
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x0000003f
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((x) << 0) & 0x0000003f)
+
+/* macros for BB_powertx_rate7 */
+#define PHY_BB_POWERTX_RATE7_ADDRESS 0x0000a3c0
+#define PHY_BB_POWERTX_RATE7_OFFSET 0x0000a3c0
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB 5
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB 0
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB 13
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB 8
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB 21
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB 16
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB 29
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB 24
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate8 */
+#define PHY_BB_POWERTX_RATE8_ADDRESS 0x0000a3c4
+#define PHY_BB_POWERTX_RATE8_OFFSET 0x0000a3c4
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB 5
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB 0
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB 13
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB 8
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB 21
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB 16
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB 29
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB 24
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate9 */
+#define PHY_BB_POWERTX_RATE9_ADDRESS 0x0000a3c8
+#define PHY_BB_POWERTX_RATE9_OFFSET 0x0000a3c8
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB 5
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB 0
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB 13
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB 8
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB 21
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB 16
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB 29
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB 24
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate10 */
+#define PHY_BB_POWERTX_RATE10_ADDRESS 0x0000a3cc
+#define PHY_BB_POWERTX_RATE10_OFFSET 0x0000a3cc
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB 5
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB 0
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB 13
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB 8
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB 21
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB 16
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB 29
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB 24
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate11 */
+#define PHY_BB_POWERTX_RATE11_ADDRESS 0x0000a3d0
+#define PHY_BB_POWERTX_RATE11_OFFSET 0x0000a3d0
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB 5
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB 0
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB 13
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB 8
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB 21
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB 16
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB 29
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB 24
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_powertx_rate12 */
+#define PHY_BB_POWERTX_RATE12_ADDRESS 0x0000a3d4
+#define PHY_BB_POWERTX_RATE12_OFFSET 0x0000a3d4
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB 5
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB 0
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK 0x0000003f
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB 13
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB 8
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK 0x00003f00
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB 21
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB 16
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK 0x003f0000
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB 29
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB 24
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK 0x3f000000
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_force_analog */
+#define PHY_BB_FORCE_ANALOG_ADDRESS 0x0000a3d8
+#define PHY_BB_FORCE_ANALOG_OFFSET 0x0000a3d8
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x00000001
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0x0000000e
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB 4
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB 4
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK 0x00000010
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB 7
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB 5
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK 0x000000e0
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x) (((x) & 0x000000e0) >> 5)
+#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x) (((x) << 5) & 0x000000e0)
+
+/* macros for BB_tpc_12 */
+#define PHY_BB_TPC_12_ADDRESS 0x0000a3dc
+#define PHY_BB_TPC_12_OFFSET 0x0000a3dc
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB 4
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB 0
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK 0x0000001f
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB 9
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB 5
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK 0x000003e0
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB 14
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB 10
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK 0x00007c00
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB 19
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB 15
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK 0x000f8000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x) (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x) (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB 24
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB 20
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK 0x01f00000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB 29
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB 25
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK 0x3e000000
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_13 */
+#define PHY_BB_TPC_13_ADDRESS 0x0000a3e0
+#define PHY_BB_TPC_13_OFFSET 0x0000a3e0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB 4
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB 0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK 0x0000001f
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB 9
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB 5
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK 0x000003e0
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x) (((x) << 5) & 0x000003e0)
+
+/* macros for BB_tpc_14 */
+#define PHY_BB_TPC_14_ADDRESS 0x0000a3e4
+#define PHY_BB_TPC_14_OFFSET 0x0000a3e4
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB 4
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB 0
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK 0x0000001f
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB 9
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB 5
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK 0x000003e0
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB 14
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB 10
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK 0x00007c00
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB 19
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB 15
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK 0x000f8000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x) (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x) (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB 24
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB 20
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK 0x01f00000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB 29
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB 25
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK 0x3e000000
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_15 */
+#define PHY_BB_TPC_15_ADDRESS 0x0000a3e8
+#define PHY_BB_TPC_15_OFFSET 0x0000a3e8
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB 4
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB 0
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK 0x0000001f
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x) (((x) & 0x0000001f) >> 0)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x) (((x) << 0) & 0x0000001f)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB 9
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB 5
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK 0x000003e0
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x) (((x) & 0x000003e0) >> 5)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x) (((x) << 5) & 0x000003e0)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB 14
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB 10
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK 0x00007c00
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x) (((x) & 0x00007c00) >> 10)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x) (((x) << 10) & 0x00007c00)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB 19
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB 15
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK 0x000f8000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x) (((x) & 0x000f8000) >> 15)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x) (((x) << 15) & 0x000f8000)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB 24
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB 20
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK 0x01f00000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB 29
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB 25
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK 0x3e000000
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_tpc_16 */
+#define PHY_BB_TPC_16_ADDRESS 0x0000a3ec
+#define PHY_BB_TPC_16_OFFSET 0x0000a3ec
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB 13
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB 8
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK 0x00003f00
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x) (((x) & 0x00003f00) >> 8)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x) (((x) << 8) & 0x00003f00)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB 21
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB 16
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK 0x003f0000
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x) (((x) & 0x003f0000) >> 16)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x) (((x) << 16) & 0x003f0000)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB 29
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB 24
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK 0x3f000000
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x) (((x) & 0x3f000000) >> 24)
+#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x) (((x) << 24) & 0x3f000000)
+
+/* macros for BB_tpc_17 */
+#define PHY_BB_TPC_17_ADDRESS 0x0000a3f0
+#define PHY_BB_TPC_17_OFFSET 0x0000a3f0
+#define PHY_BB_TPC_17_ENABLE_PAL_MSB 0
+#define PHY_BB_TPC_17_ENABLE_PAL_LSB 0
+#define PHY_BB_TPC_17_ENABLE_PAL_MASK 0x00000001
+#define PHY_BB_TPC_17_ENABLE_PAL_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_17_ENABLE_PAL_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB 1
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB 1
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK 0x00000002
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB 2
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB 2
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK 0x00000004
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB 3
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB 3
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK 0x00000008
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB 9
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB 4
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK 0x000003f0
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x) (((x) & 0x000003f0) >> 4)
+#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x) (((x) << 4) & 0x000003f0)
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB 10
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB 10
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK 0x00000400
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB 16
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB 11
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK 0x0001f800
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x) (((x) & 0x0001f800) >> 11)
+#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x) (((x) << 11) & 0x0001f800)
+
+/* macros for BB_tpc_18 */
+#define PHY_BB_TPC_18_ADDRESS 0x0000a3f4
+#define PHY_BB_TPC_18_OFFSET 0x0000a3f4
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB 7
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB 0
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK 0x000000ff
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB 15
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB 8
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK 0x0000ff00
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 16
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 16
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x00010000
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((x) << 16) & 0x00010000)
+
+/* macros for BB_tpc_19 */
+#define PHY_BB_TPC_19_ADDRESS 0x0000a3f8
+#define PHY_BB_TPC_19_OFFSET 0x0000a3f8
+#define PHY_BB_TPC_19_ALPHA_THERM_MSB 7
+#define PHY_BB_TPC_19_ALPHA_THERM_LSB 0
+#define PHY_BB_TPC_19_ALPHA_THERM_MASK 0x000000ff
+#define PHY_BB_TPC_19_ALPHA_THERM_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_TPC_19_ALPHA_THERM_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB 15
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB 8
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK 0x0000ff00
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_TPC_19_ALPHA_VOLT_MSB 20
+#define PHY_BB_TPC_19_ALPHA_VOLT_LSB 16
+#define PHY_BB_TPC_19_ALPHA_VOLT_MASK 0x001f0000
+#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x) (((x) << 16) & 0x001f0000)
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB 25
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB 21
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK 0x03e00000
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x) (((x) & 0x03e00000) >> 21)
+#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x) (((x) << 21) & 0x03e00000)
+
+/* macros for BB_tpc_20 */
+#define PHY_BB_TPC_20_ADDRESS 0x0000a3fc
+#define PHY_BB_TPC_20_OFFSET 0x0000a3fc
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB 0
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB 0
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK 0x00000001
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB 1
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB 1
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK 0x00000002
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB 2
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB 2
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK 0x00000004
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x) (((x) << 2) & 0x00000004)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB 3
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB 3
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK 0x00000008
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x) (((x) << 3) & 0x00000008)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB 4
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB 4
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK 0x00000010
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x) (((x) & 0x00000010) >> 4)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x) (((x) << 4) & 0x00000010)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB 5
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB 5
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK 0x00000020
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x) (((x) & 0x00000020) >> 5)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x) (((x) << 5) & 0x00000020)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB 6
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB 6
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK 0x00000040
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x) (((x) & 0x00000040) >> 6)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x) (((x) << 6) & 0x00000040)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB 7
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB 7
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK 0x00000080
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x) (((x) & 0x00000080) >> 7)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x) (((x) << 7) & 0x00000080)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB 8
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB 8
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK 0x00000100
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB 9
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB 9
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK 0x00000200
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB 10
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB 10
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK 0x00000400
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB 11
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB 11
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK 0x00000800
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB 12
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB 12
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK 0x00001000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x) (((x) & 0x00001000) >> 12)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x) (((x) << 12) & 0x00001000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB 13
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB 13
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK 0x00002000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x) (((x) & 0x00002000) >> 13)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x) (((x) << 13) & 0x00002000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB 14
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB 14
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK 0x00004000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x) (((x) & 0x00004000) >> 14)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x) (((x) << 14) & 0x00004000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB 15
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB 15
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK 0x00008000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB 16
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB 16
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK 0x00010000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x) (((x) & 0x00010000) >> 16)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x) (((x) << 16) & 0x00010000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB 17
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB 17
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK 0x00020000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x) (((x) & 0x00020000) >> 17)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x) (((x) << 17) & 0x00020000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB 18
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB 18
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK 0x00040000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x) (((x) & 0x00040000) >> 18)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x) (((x) << 18) & 0x00040000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB 19
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB 19
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK 0x00080000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x) (((x) & 0x00080000) >> 19)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x) (((x) << 19) & 0x00080000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB 20
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB 20
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK 0x00100000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x) (((x) & 0x00100000) >> 20)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x) (((x) << 20) & 0x00100000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB 21
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB 21
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK 0x00200000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x) (((x) & 0x00200000) >> 21)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x) (((x) << 21) & 0x00200000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB 22
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB 22
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK 0x00400000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x) (((x) & 0x00400000) >> 22)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x) (((x) << 22) & 0x00400000)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB 23
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB 23
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK 0x00800000
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x) (((x) & 0x00800000) >> 23)
+#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x) (((x) << 23) & 0x00800000)
+
+/* macros for BB_tx_gain_tab_1 */
+#define PHY_BB_TX_GAIN_TAB_1_ADDRESS 0x0000a400
+#define PHY_BB_TX_GAIN_TAB_1_OFFSET 0x0000a400
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB 31
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB 0
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_2 */
+#define PHY_BB_TX_GAIN_TAB_2_ADDRESS 0x0000a404
+#define PHY_BB_TX_GAIN_TAB_2_OFFSET 0x0000a404
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB 31
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB 0
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_3 */
+#define PHY_BB_TX_GAIN_TAB_3_ADDRESS 0x0000a408
+#define PHY_BB_TX_GAIN_TAB_3_OFFSET 0x0000a408
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB 31
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB 0
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_4 */
+#define PHY_BB_TX_GAIN_TAB_4_ADDRESS 0x0000a40c
+#define PHY_BB_TX_GAIN_TAB_4_OFFSET 0x0000a40c
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB 31
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB 0
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_5 */
+#define PHY_BB_TX_GAIN_TAB_5_ADDRESS 0x0000a410
+#define PHY_BB_TX_GAIN_TAB_5_OFFSET 0x0000a410
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB 31
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB 0
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_6 */
+#define PHY_BB_TX_GAIN_TAB_6_ADDRESS 0x0000a414
+#define PHY_BB_TX_GAIN_TAB_6_OFFSET 0x0000a414
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB 31
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB 0
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_7 */
+#define PHY_BB_TX_GAIN_TAB_7_ADDRESS 0x0000a418
+#define PHY_BB_TX_GAIN_TAB_7_OFFSET 0x0000a418
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB 31
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB 0
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_8 */
+#define PHY_BB_TX_GAIN_TAB_8_ADDRESS 0x0000a41c
+#define PHY_BB_TX_GAIN_TAB_8_OFFSET 0x0000a41c
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB 31
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB 0
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_9 */
+#define PHY_BB_TX_GAIN_TAB_9_ADDRESS 0x0000a420
+#define PHY_BB_TX_GAIN_TAB_9_OFFSET 0x0000a420
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB 31
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB 0
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_10 */
+#define PHY_BB_TX_GAIN_TAB_10_ADDRESS 0x0000a424
+#define PHY_BB_TX_GAIN_TAB_10_OFFSET 0x0000a424
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB 31
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB 0
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_11 */
+#define PHY_BB_TX_GAIN_TAB_11_ADDRESS 0x0000a428
+#define PHY_BB_TX_GAIN_TAB_11_OFFSET 0x0000a428
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB 31
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB 0
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_12 */
+#define PHY_BB_TX_GAIN_TAB_12_ADDRESS 0x0000a42c
+#define PHY_BB_TX_GAIN_TAB_12_OFFSET 0x0000a42c
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB 31
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB 0
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_13 */
+#define PHY_BB_TX_GAIN_TAB_13_ADDRESS 0x0000a430
+#define PHY_BB_TX_GAIN_TAB_13_OFFSET 0x0000a430
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB 31
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB 0
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_14 */
+#define PHY_BB_TX_GAIN_TAB_14_ADDRESS 0x0000a434
+#define PHY_BB_TX_GAIN_TAB_14_OFFSET 0x0000a434
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB 31
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB 0
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_15 */
+#define PHY_BB_TX_GAIN_TAB_15_ADDRESS 0x0000a438
+#define PHY_BB_TX_GAIN_TAB_15_OFFSET 0x0000a438
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB 31
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB 0
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_16 */
+#define PHY_BB_TX_GAIN_TAB_16_ADDRESS 0x0000a43c
+#define PHY_BB_TX_GAIN_TAB_16_OFFSET 0x0000a43c
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB 31
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB 0
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_17 */
+#define PHY_BB_TX_GAIN_TAB_17_ADDRESS 0x0000a440
+#define PHY_BB_TX_GAIN_TAB_17_OFFSET 0x0000a440
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB 31
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB 0
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_18 */
+#define PHY_BB_TX_GAIN_TAB_18_ADDRESS 0x0000a444
+#define PHY_BB_TX_GAIN_TAB_18_OFFSET 0x0000a444
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB 31
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB 0
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_19 */
+#define PHY_BB_TX_GAIN_TAB_19_ADDRESS 0x0000a448
+#define PHY_BB_TX_GAIN_TAB_19_OFFSET 0x0000a448
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB 31
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB 0
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_20 */
+#define PHY_BB_TX_GAIN_TAB_20_ADDRESS 0x0000a44c
+#define PHY_BB_TX_GAIN_TAB_20_OFFSET 0x0000a44c
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB 31
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB 0
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_21 */
+#define PHY_BB_TX_GAIN_TAB_21_ADDRESS 0x0000a450
+#define PHY_BB_TX_GAIN_TAB_21_OFFSET 0x0000a450
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB 31
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB 0
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_22 */
+#define PHY_BB_TX_GAIN_TAB_22_ADDRESS 0x0000a454
+#define PHY_BB_TX_GAIN_TAB_22_OFFSET 0x0000a454
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB 31
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB 0
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_23 */
+#define PHY_BB_TX_GAIN_TAB_23_ADDRESS 0x0000a458
+#define PHY_BB_TX_GAIN_TAB_23_OFFSET 0x0000a458
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB 31
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB 0
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_24 */
+#define PHY_BB_TX_GAIN_TAB_24_ADDRESS 0x0000a45c
+#define PHY_BB_TX_GAIN_TAB_24_OFFSET 0x0000a45c
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB 31
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB 0
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_25 */
+#define PHY_BB_TX_GAIN_TAB_25_ADDRESS 0x0000a460
+#define PHY_BB_TX_GAIN_TAB_25_OFFSET 0x0000a460
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB 31
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB 0
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_26 */
+#define PHY_BB_TX_GAIN_TAB_26_ADDRESS 0x0000a464
+#define PHY_BB_TX_GAIN_TAB_26_OFFSET 0x0000a464
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB 31
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB 0
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_27 */
+#define PHY_BB_TX_GAIN_TAB_27_ADDRESS 0x0000a468
+#define PHY_BB_TX_GAIN_TAB_27_OFFSET 0x0000a468
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB 31
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB 0
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_28 */
+#define PHY_BB_TX_GAIN_TAB_28_ADDRESS 0x0000a46c
+#define PHY_BB_TX_GAIN_TAB_28_OFFSET 0x0000a46c
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB 31
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB 0
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_29 */
+#define PHY_BB_TX_GAIN_TAB_29_ADDRESS 0x0000a470
+#define PHY_BB_TX_GAIN_TAB_29_OFFSET 0x0000a470
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB 31
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB 0
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_30 */
+#define PHY_BB_TX_GAIN_TAB_30_ADDRESS 0x0000a474
+#define PHY_BB_TX_GAIN_TAB_30_OFFSET 0x0000a474
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB 31
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB 0
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_31 */
+#define PHY_BB_TX_GAIN_TAB_31_ADDRESS 0x0000a478
+#define PHY_BB_TX_GAIN_TAB_31_OFFSET 0x0000a478
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB 31
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB 0
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_32 */
+#define PHY_BB_TX_GAIN_TAB_32_ADDRESS 0x0000a47c
+#define PHY_BB_TX_GAIN_TAB_32_OFFSET 0x0000a47c
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB 31
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB 0
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_1 */
+#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS 0x0000a480
+#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET 0x0000a480
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_2 */
+#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS 0x0000a484
+#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET 0x0000a484
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_3 */
+#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS 0x0000a488
+#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET 0x0000a488
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_4 */
+#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS 0x0000a48c
+#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET 0x0000a48c
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_5 */
+#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS 0x0000a490
+#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET 0x0000a490
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_6 */
+#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS 0x0000a494
+#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET 0x0000a494
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_7 */
+#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS 0x0000a498
+#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET 0x0000a498
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_8 */
+#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS 0x0000a49c
+#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET 0x0000a49c
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_9 */
+#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS 0x0000a4a0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET 0x0000a4a0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_10 */
+#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS 0x0000a4a4
+#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET 0x0000a4a4
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_11 */
+#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS 0x0000a4a8
+#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET 0x0000a4a8
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_12 */
+#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS 0x0000a4ac
+#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET 0x0000a4ac
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_13 */
+#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS 0x0000a4b0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET 0x0000a4b0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_14 */
+#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS 0x0000a4b4
+#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET 0x0000a4b4
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_15 */
+#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS 0x0000a4b8
+#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET 0x0000a4b8
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_16 */
+#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS 0x0000a4bc
+#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET 0x0000a4bc
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_17 */
+#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS 0x0000a4c0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET 0x0000a4c0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_18 */
+#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS 0x0000a4c4
+#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET 0x0000a4c4
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_19 */
+#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS 0x0000a4c8
+#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET 0x0000a4c8
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_20 */
+#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS 0x0000a4cc
+#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET 0x0000a4cc
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_21 */
+#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS 0x0000a4d0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET 0x0000a4d0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_22 */
+#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS 0x0000a4d4
+#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET 0x0000a4d4
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_23 */
+#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS 0x0000a4d8
+#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET 0x0000a4d8
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_24 */
+#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS 0x0000a4dc
+#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET 0x0000a4dc
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_25 */
+#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS 0x0000a4e0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET 0x0000a4e0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_26 */
+#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS 0x0000a4e4
+#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET 0x0000a4e4
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_27 */
+#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS 0x0000a4e8
+#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET 0x0000a4e8
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_28 */
+#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS 0x0000a4ec
+#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET 0x0000a4ec
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_29 */
+#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS 0x0000a4f0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET 0x0000a4f0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_30 */
+#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS 0x0000a4f4
+#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET 0x0000a4f4
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_31 */
+#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS 0x0000a4f8
+#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET 0x0000a4f8
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_tx_gain_tab_pal_32 */
+#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS 0x0000a4fc
+#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET 0x0000a4fc
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB 31
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB 0
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK 0xffffffff
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_caltx_gain_set_0 */
+#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS 0x0000a518
+#define PHY_BB_CALTX_GAIN_SET_0_OFFSET 0x0000a518
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_2 */
+#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS 0x0000a51c
+#define PHY_BB_CALTX_GAIN_SET_2_OFFSET 0x0000a51c
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_4 */
+#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS 0x0000a520
+#define PHY_BB_CALTX_GAIN_SET_4_OFFSET 0x0000a520
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_6 */
+#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS 0x0000a524
+#define PHY_BB_CALTX_GAIN_SET_6_OFFSET 0x0000a524
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_8 */
+#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS 0x0000a528
+#define PHY_BB_CALTX_GAIN_SET_8_OFFSET 0x0000a528
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_10 */
+#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS 0x0000a52c
+#define PHY_BB_CALTX_GAIN_SET_10_OFFSET 0x0000a52c
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_12 */
+#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS 0x0000a530
+#define PHY_BB_CALTX_GAIN_SET_12_OFFSET 0x0000a530
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_14 */
+#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS 0x0000a534
+#define PHY_BB_CALTX_GAIN_SET_14_OFFSET 0x0000a534
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_16 */
+#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS 0x0000a538
+#define PHY_BB_CALTX_GAIN_SET_16_OFFSET 0x0000a538
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_18 */
+#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS 0x0000a53c
+#define PHY_BB_CALTX_GAIN_SET_18_OFFSET 0x0000a53c
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_20 */
+#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS 0x0000a540
+#define PHY_BB_CALTX_GAIN_SET_20_OFFSET 0x0000a540
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_22 */
+#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS 0x0000a544
+#define PHY_BB_CALTX_GAIN_SET_22_OFFSET 0x0000a544
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_24 */
+#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS 0x0000a548
+#define PHY_BB_CALTX_GAIN_SET_24_OFFSET 0x0000a548
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_26 */
+#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS 0x0000a54c
+#define PHY_BB_CALTX_GAIN_SET_26_OFFSET 0x0000a54c
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_28 */
+#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS 0x0000a550
+#define PHY_BB_CALTX_GAIN_SET_28_OFFSET 0x0000a550
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_caltx_gain_set_30 */
+#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS 0x0000a554
+#define PHY_BB_CALTX_GAIN_SET_30_OFFSET 0x0000a554
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB 13
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB 0
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK 0x00003fff
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB 27
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB 14
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK 0x0fffc000
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiqcal_meas_b0 */
+#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS 0x0000a558
+#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET 0x0000a558
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB 11
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB 0
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK 0x00000fff
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB 23
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB 12
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK 0x00fff000
+#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x) (((x) & 0x00fff000) >> 12)
+
+/* macros for BB_txiqcal_start */
+#define PHY_BB_TXIQCAL_START_ADDRESS 0x0000a6d8
+#define PHY_BB_TXIQCAL_START_OFFSET 0x0000a6d8
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB 0
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB 0
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK 0x00000001
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x) (((x) << 0) & 0x00000001)
+
+/* macros for BB_txiqcal_control_0 */
+#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS 0x0000a6dc
+#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET 0x0000a6dc
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB 0
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB 0
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK 0x00000001
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x0000007e
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & 0x0000007e) >> 1)
+#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((x) << 1) & 0x0000007e)
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x00001f80
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & 0x00001f80) >> 7)
+#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((x) << 7) & 0x00001f80)
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x0007e000
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & 0x0007e000) >> 13)
+#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((x) << 13) & 0x0007e000)
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x00780000
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & 0x00780000) >> 19)
+#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((x) << 19) & 0x00780000)
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & 0x3f800000) >> 23)
+#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((x) << 23) & 0x3f800000)
+
+/* macros for BB_txiqcal_control_1 */
+#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS 0x0000a6e0
+#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET 0x0000a6e0
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x0000003f
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0x00000fc0
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x0003f000
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 24
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x01fc0000
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & 0x01fc0000) >> 18)
+#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((x) << 18) & 0x01fc0000)
+
+/* macros for BB_txiqcal_control_2 */
+#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS 0x0000a6e4
+#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET 0x0000a6e4
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB 3
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB 0
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK 0x0000000f
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x) (((x) & 0x0000000f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x) (((x) << 0) & 0x0000000f)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x000001f0
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & 0x000001f0) >> 4)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((x) << 4) & 0x000001f0)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x00003e00
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & 0x00003e00) >> 9)
+#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((x) << 9) & 0x00003e00)
+
+/* macros for BB_txiqcal_control_3 */
+#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS 0x0000a6e8
+#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET 0x0000a6e8
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x0000003f
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0x00000fc0
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x003ff000
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & 0x003ff000) >> 12)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((x) << 12) & 0x003ff000)
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0x00c00000
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB 24
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB 24
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK 0x01000000
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x) (((x) << 24) & 0x01000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB 26
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB 25
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK 0x06000000
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x) (((x) & 0x06000000) >> 25)
+#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x) (((x) << 25) & 0x06000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB 28
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB 27
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK 0x18000000
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x) (((x) & 0x18000000) >> 27)
+#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x) (((x) << 27) & 0x18000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 29
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x60000000
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & 0x60000000) >> 29)
+#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((x) << 29) & 0x60000000)
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & 0x80000000) >> 31)
+#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((x) << 31) & 0x80000000)
+
+/* macros for BB_txiq_corr_coeff_01_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS 0x0000a6ec
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET 0x0000a6ec
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_23_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS 0x0000a6f0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET 0x0000a6f0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_45_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS 0x0000a6f4
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET 0x0000a6f4
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_67_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS 0x0000a6f8
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET 0x0000a6f8
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_89_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS 0x0000a6fc
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET 0x0000a6fc
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_ab_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS 0x0000a700
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET 0x0000a700
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_cd_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS 0x0000a704
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET 0x0000a704
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_txiq_corr_coeff_ef_b0 */
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS 0x0000a708
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET 0x0000a708
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB 13
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB 0
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK 0x00003fff
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x) (((x) & 0x00003fff) >> 0)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x) (((x) << 0) & 0x00003fff)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB 27
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB 14
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK 0x0fffc000
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x) (((x) & 0x0fffc000) >> 14)
+#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x) (((x) << 14) & 0x0fffc000)
+
+/* macros for BB_cal_rxbb_gain_tbl_0 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS 0x0000a70c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET 0x0000a70c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_4 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS 0x0000a710
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET 0x0000a710
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_8 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS 0x0000a714
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET 0x0000a714
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_12 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS 0x0000a718
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET 0x0000a718
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_16 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS 0x0000a71c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET 0x0000a71c
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_20 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS 0x0000a720
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET 0x0000a720
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 11
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 6
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0x00000fc0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 17
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 12
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0x0003f000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((x) << 12) & 0x0003f000)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 23
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 18
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0x00fc0000
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & 0x00fc0000) >> 18)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((x) << 18) & 0x00fc0000)
+
+/* macros for BB_cal_rxbb_gain_tbl_24 */
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS 0x0000a724
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET 0x0000a724
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 5
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0x0000003f
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((x) << 0) & 0x0000003f)
+
+/* macros for BB_txiqcal_status_b0 */
+#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS 0x0000a728
+#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET 0x0000a728
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x00000001
+#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x0000003e
+#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & 0x0000003e) >> 1)
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0x00000fc0
+#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x0003f000
+#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & 0x0003f000) >> 12)
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 24
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0x01fc0000
+#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & 0x01fc0000) >> 18)
+
+/* macros for BB_paprd_trainer_cntl1 */
+#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS 0x0000a72c
+#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET 0x0000a72c
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB 0
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB 0
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK 0x00000001
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB 7
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB 1
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK 0x000000fe
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x) (((x) & 0x000000fe) >> 1)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x) (((x) << 1) & 0x000000fe)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB 8
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB 8
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK 0x00000100
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x) (((x) & 0x00000100) >> 8)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x) (((x) << 8) & 0x00000100)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB 9
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB 9
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK 0x00000200
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x) (((x) & 0x00000200) >> 9)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x) (((x) << 9) & 0x00000200)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB 10
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB 10
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK 0x00000400
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x) (((x) & 0x00000400) >> 10)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x) (((x) << 10) & 0x00000400)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB 11
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB 11
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK 0x00000800
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x) (((x) << 11) & 0x00000800)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB 18
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB 12
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK 0x0007f000
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x) (((x) & 0x0007f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x) (((x) << 12) & 0x0007f000)
+
+/* macros for BB_paprd_trainer_cntl2 */
+#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS 0x0000a730
+#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET 0x0000a730
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB 31
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB 0
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK 0xffffffff
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x) (((x) & 0xffffffff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_paprd_trainer_cntl3 */
+#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS 0x0000a734
+#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET 0x0000a734
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB 5
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB 0
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK 0x0000003f
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB 11
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB 6
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK 0x00000fc0
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB 16
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB 12
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK 0x0001f000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB 19
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB 17
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK 0x000e0000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x) (((x) & 0x000e0000) >> 17)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x) (((x) << 17) & 0x000e0000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB 23
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB 20
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK 0x00f00000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x) (((x) & 0x00f00000) >> 20)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x) (((x) << 20) & 0x00f00000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB 27
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB 24
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK 0x0f000000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x) (((x) & 0x0f000000) >> 24)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x) (((x) << 24) & 0x0f000000)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB 28
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB 28
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK 0x10000000
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x) (((x) & 0x10000000) >> 28)
+#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x) (((x) << 28) & 0x10000000)
+
+/* macros for BB_paprd_trainer_cntl4 */
+#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS 0x0000a738
+#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET 0x0000a738
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB 11
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB 0
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK 0x00000fff
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x) (((x) << 0) & 0x00000fff)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB 15
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB 12
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK 0x0000f000
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x) (((x) & 0x0000f000) >> 12)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x) (((x) << 12) & 0x0000f000)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB 25
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB 16
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK 0x03ff0000
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x) (((x) & 0x03ff0000) >> 16)
+#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x) (((x) << 16) & 0x03ff0000)
+
+/* macros for BB_paprd_trainer_stat1 */
+#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS 0x0000a73c
+#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET 0x0000a73c
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB 0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB 0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK 0x00000001
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB 1
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB 1
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK 0x00000002
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB 2
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB 2
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK 0x00000004
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x) (((x) & 0x00000004) >> 2)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB 3
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB 3
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK 0x00000008
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x) (((x) & 0x00000008) >> 3)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB 8
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB 4
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK 0x000001f0
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x) (((x) & 0x000001f0) >> 4)
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB 16
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB 9
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK 0x0001fe00
+#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x) (((x) & 0x0001fe00) >> 9)
+
+/* macros for BB_paprd_trainer_stat2 */
+#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS 0x0000a740
+#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET 0x0000a740
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB 15
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB 0
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK 0x0000ffff
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x) (((x) & 0x0000ffff) >> 0)
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB 20
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB 16
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK 0x001f0000
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x) (((x) & 0x001f0000) >> 16)
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB 22
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB 21
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK 0x00600000
+#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x) (((x) & 0x00600000) >> 21)
+
+/* macros for BB_paprd_trainer_stat3 */
+#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS 0x0000a744
+#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET 0x0000a744
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB 19
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB 0
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK 0x000fffff
+#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x) (((x) & 0x000fffff) >> 0)
+
+/* macros for BB_fcal_1 */
+#define PHY_BB_FCAL_1_ADDRESS 0x0000a7d8
+#define PHY_BB_FCAL_1_OFFSET 0x0000a7d8
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x000003ff
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & 0x000003ff) >> 0)
+#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((x) << 0) & 0x000003ff)
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0x000ffc00
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & 0x000ffc00) >> 10)
+#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((x) << 10) & 0x000ffc00)
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x01f00000
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & 0x01f00000) >> 20)
+#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((x) << 20) & 0x01f00000)
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & 0x3e000000) >> 25)
+#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((x) << 25) & 0x3e000000)
+
+/* macros for BB_fcal_2_b0 */
+#define PHY_BB_FCAL_2_B0_ADDRESS 0x0000a7dc
+#define PHY_BB_FCAL_2_B0_OFFSET 0x0000a7dc
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x00000007
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & 0x00000007) >> 0)
+#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((x) << 0) & 0x00000007)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0x000000f8
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & 0x000000f8) >> 3)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((x) << 3) & 0x000000f8)
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x00000300
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & 0x00000300) >> 8)
+#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((x) << 8) & 0x00000300)
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 12
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x00001c00
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & 0x00001c00) >> 10)
+#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((x) << 10) & 0x00001c00)
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 14
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 13
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0x00006000
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & 0x00006000) >> 13)
+#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((x) << 13) & 0x00006000)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 15
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 15
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x00008000
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & 0x00008000) >> 15)
+#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((x) << 15) & 0x00008000)
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 18
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 16
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0x00070000
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & 0x00070000) >> 16)
+#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((x) << 16) & 0x00070000)
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x01f00000
+#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & 0x01f00000) >> 20)
+
+/* macros for BB_radar_bw_filter */
+#define PHY_BB_RADAR_BW_FILTER_ADDRESS 0x0000a7e0
+#define PHY_BB_RADAR_BW_FILTER_OFFSET 0x0000a7e0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB 0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB 0
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK 0x00000001
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB 1
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB 1
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK 0x00000002
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x) (((x) & 0x00000002) >> 1)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x) (((x) << 1) & 0x00000002)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB 3
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB 2
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK 0x0000000c
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB 5
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB 4
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK 0x00000030
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB 14
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB 8
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK 0x00007f00
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x) (((x) & 0x00007f00) >> 8)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x) (((x) << 8) & 0x00007f00)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB 20
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB 15
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK 0x001f8000
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x) (((x) & 0x001f8000) >> 15)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x) (((x) << 15) & 0x001f8000)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB 26
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB 21
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK 0x07e00000
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x) (((x) & 0x07e00000) >> 21)
+#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x) (((x) << 21) & 0x07e00000)
+
+/* macros for BB_dft_tone_ctrl_b0 */
+#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS 0x0000a7e4
+#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET 0x0000a7e4
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x00000001
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0x0000000c
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & 0x0000000c) >> 2)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((x) << 2) & 0x0000000c)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x00001ff0
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & 0x00001ff0) >> 4)
+#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((x) << 4) & 0x00001ff0)
+
+/* macros for BB_therm_adc_1 */
+#define PHY_BB_THERM_ADC_1_ADDRESS 0x0000a7e8
+#define PHY_BB_THERM_ADC_1_OFFSET 0x0000a7e8
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB 7
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB 0
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK 0x000000ff
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB 15
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB 8
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK 0x0000ff00
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x) (((x) << 8) & 0x0000ff00)
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB 23
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB 16
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK 0x00ff0000
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x) (((x) & 0x00ff0000) >> 16)
+#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x) (((x) << 16) & 0x00ff0000)
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB 25
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB 24
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK 0x03000000
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x) (((x) & 0x03000000) >> 24)
+#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x) (((x) << 24) & 0x03000000)
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 26
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 26
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x04000000
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((x) << 26) & 0x04000000)
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 27
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 27
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x08000000
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & 0x08000000) >> 27)
+#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((x) << 27) & 0x08000000)
+
+/* macros for BB_therm_adc_2 */
+#define PHY_BB_THERM_ADC_2_ADDRESS 0x0000a7ec
+#define PHY_BB_THERM_ADC_2_OFFSET 0x0000a7ec
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB 11
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB 0
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK 0x00000fff
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x) (((x) & 0x00000fff) >> 0)
+#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x) (((x) << 0) & 0x00000fff)
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB 21
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB 12
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK 0x003ff000
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x) (((x) & 0x003ff000) >> 12)
+#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x) (((x) << 12) & 0x003ff000)
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB 31
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB 22
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK 0xffc00000
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x) (((x) & 0xffc00000) >> 22)
+#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x) (((x) << 22) & 0xffc00000)
+
+/* macros for BB_therm_adc_3 */
+#define PHY_BB_THERM_ADC_3_ADDRESS 0x0000a7f0
+#define PHY_BB_THERM_ADC_3_OFFSET 0x0000a7f0
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB 7
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB 0
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK 0x000000ff
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x) (((x) << 0) & 0x000000ff)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB 16
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB 8
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK 0x0001ff00
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x) (((x) & 0x0001ff00) >> 8)
+#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x) (((x) << 8) & 0x0001ff00)
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB 29
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB 17
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK 0x3ffe0000
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x) (((x) & 0x3ffe0000) >> 17)
+#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x) (((x) << 17) & 0x3ffe0000)
+
+/* macros for BB_therm_adc_4 */
+#define PHY_BB_THERM_ADC_4_ADDRESS 0x0000a7f4
+#define PHY_BB_THERM_ADC_4_OFFSET 0x0000a7f4
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB 7
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB 0
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK 0x000000ff
+#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB 15
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB 8
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK 0x0000ff00
+#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x) (((x) & 0x0000ff00) >> 8)
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB 23
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB 16
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK 0x00ff0000
+#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x) (((x) & 0x00ff0000) >> 16)
+
+/* macros for BB_tx_forced_gain */
+#define PHY_BB_TX_FORCED_GAIN_ADDRESS 0x0000a7f8
+#define PHY_BB_TX_FORCED_GAIN_OFFSET 0x0000a7f8
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x00000001
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & 0x00000001) >> 0)
+#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((x) << 0) & 0x00000001)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 3
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x0000000e
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & 0x0000000e) >> 1)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((x) << 1) & 0x0000000e)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 5
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 4
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x00000030
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & 0x00000030) >> 4)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((x) << 4) & 0x00000030)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 9
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 6
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x000003c0
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & 0x000003c0) >> 6)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((x) << 6) & 0x000003c0)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB 13
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB 10
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK 0x00003c00
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x) (((x) & 0x00003c00) >> 10)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x) (((x) << 10) & 0x00003c00)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB 17
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB 14
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK 0x0003c000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x) (((x) & 0x0003c000) >> 14)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x) (((x) << 14) & 0x0003c000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB 21
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB 18
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK 0x003c0000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x) (((x) & 0x003c0000) >> 18)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x) (((x) << 18) & 0x003c0000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB 23
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB 22
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK 0x00c00000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x) (((x) & 0x00c00000) >> 22)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x) (((x) << 22) & 0x00c00000)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 24
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 24
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x01000000
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & 0x01000000) >> 24)
+#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((x) << 24) & 0x01000000)
+
+/* macros for BB_eco_ctrl */
+#define PHY_BB_ECO_CTRL_ADDRESS 0x0000a7fc
+#define PHY_BB_ECO_CTRL_OFFSET 0x0000a7fc
+#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 7
+#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0
+#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0x000000ff
+#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & 0x000000ff) >> 0)
+#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((x) << 0) & 0x000000ff)
+
+/* macros for BB_gain_force_max_gains_b1 */
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS 0x0000a848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET 0x0000a848
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB 13
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB 7
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK 0x00003f80
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x) (((x) & 0x00003f80) >> 7)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x) (((x) << 7) & 0x00003f80)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB 20
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB 14
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK 0x001fc000
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x) (((x) & 0x001fc000) >> 14)
+#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x) (((x) << 14) & 0x001fc000)
+
+/* macros for BB_gains_min_offsets_b1 */
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS 0x0000a84c
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET 0x0000a84c
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB 24
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB 17
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK 0x01fe0000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x) (((x) & 0x01fe0000) >> 17)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x) (((x) << 17) & 0x01fe0000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB 25
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB 25
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK 0x02000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x) (((x) & 0x02000000) >> 25)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x) (((x) << 25) & 0x02000000)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB 26
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB 26
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK 0x04000000
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x) (((x) & 0x04000000) >> 26)
+#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x) (((x) << 26) & 0x04000000)
+
+/* macros for BB_rx_ocgain2 */
+#define PHY_BB_RX_OCGAIN2_ADDRESS 0x0000aa00
+#define PHY_BB_RX_OCGAIN2_OFFSET 0x0000aa00
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB 31
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB 0
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK 0xffffffff
+#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x) (((x) << 0) & 0xffffffff)
+
+/* macros for BB_ext_atten_switch_ctl_b1 */
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS 0x0000b20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET 0x0000b20c
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB 5
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB 0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK 0x0000003f
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x) (((x) & 0x0000003f) >> 0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x) (((x) << 0) & 0x0000003f)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB 11
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB 6
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK 0x00000fc0
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x) (((x) & 0x00000fc0) >> 6)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x) (((x) << 6) & 0x00000fc0)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB 16
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB 12
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK 0x0001f000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x) (((x) & 0x0001f000) >> 12)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x) (((x) << 12) & 0x0001f000)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB 21
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB 17
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK 0x003e0000
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x) (((x) & 0x003e0000) >> 17)
+#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x) (((x) << 17) & 0x003e0000)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct bb_lc_reg_reg_s {
+ volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */
+ volatile unsigned int BB_test_controls; /* 0x9800 - 0x9804 */
+ volatile unsigned int BB_gen_controls; /* 0x9804 - 0x9808 */
+ volatile unsigned int BB_test_controls_status; /* 0x9808 - 0x980c */
+ volatile unsigned int BB_timing_controls_1; /* 0x980c - 0x9810 */
+ volatile unsigned int BB_timing_controls_2; /* 0x9810 - 0x9814 */
+ volatile unsigned int BB_timing_controls_3; /* 0x9814 - 0x9818 */
+ volatile unsigned int BB_D2_chip_id; /* 0x9818 - 0x981c */
+ volatile unsigned int BB_active; /* 0x981c - 0x9820 */
+ volatile unsigned int BB_tx_timing_1; /* 0x9820 - 0x9824 */
+ volatile unsigned int BB_tx_timing_2; /* 0x9824 - 0x9828 */
+ volatile unsigned int BB_tx_timing_3; /* 0x9828 - 0x982c */
+ volatile unsigned int BB_addac_parallel_control; /* 0x982c - 0x9830 */
+ volatile char pad__1[0x4]; /* 0x9830 - 0x9834 */
+ volatile unsigned int BB_xpa_timing_control; /* 0x9834 - 0x9838 */
+ volatile unsigned int BB_misc_pa_control; /* 0x9838 - 0x983c */
+ volatile unsigned int BB_tstdac_constant; /* 0x983c - 0x9840 */
+ volatile unsigned int BB_find_signal_low; /* 0x9840 - 0x9844 */
+ volatile unsigned int BB_settling_time; /* 0x9844 - 0x9848 */
+ volatile unsigned int BB_gain_force_max_gains_b0; /* 0x9848 - 0x984c */
+ volatile unsigned int BB_gains_min_offsets_b0; /* 0x984c - 0x9850 */
+ volatile unsigned int BB_desired_sigsize; /* 0x9850 - 0x9854 */
+ volatile unsigned int BB_timing_control_3a; /* 0x9854 - 0x9858 */
+ volatile unsigned int BB_find_signal; /* 0x9858 - 0x985c */
+ volatile unsigned int BB_agc; /* 0x985c - 0x9860 */
+ volatile unsigned int BB_agc_control; /* 0x9860 - 0x9864 */
+ volatile unsigned int BB_cca_b0; /* 0x9864 - 0x9868 */
+ volatile unsigned int BB_sfcorr; /* 0x9868 - 0x986c */
+ volatile unsigned int BB_self_corr_low; /* 0x986c - 0x9870 */
+ volatile char pad__2[0x4]; /* 0x9870 - 0x9874 */
+ volatile unsigned int BB_synth_control; /* 0x9874 - 0x9878 */
+ volatile unsigned int BB_addac_clk_select; /* 0x9878 - 0x987c */
+ volatile unsigned int BB_pll_cntl; /* 0x987c - 0x9880 */
+ volatile char pad__3[0x80]; /* 0x9880 - 0x9900 */
+ volatile unsigned int BB_vit_spur_mask_A; /* 0x9900 - 0x9904 */
+ volatile unsigned int BB_vit_spur_mask_B; /* 0x9904 - 0x9908 */
+ volatile unsigned int BB_pilot_spur_mask; /* 0x9908 - 0x990c */
+ volatile unsigned int BB_chan_spur_mask; /* 0x990c - 0x9910 */
+ volatile unsigned int BB_spectral_scan; /* 0x9910 - 0x9914 */
+ volatile unsigned int BB_analog_power_on_time; /* 0x9914 - 0x9918 */
+ volatile unsigned int BB_search_start_delay; /* 0x9918 - 0x991c */
+ volatile unsigned int BB_max_rx_length; /* 0x991c - 0x9920 */
+ volatile unsigned int BB_timing_control_4; /* 0x9920 - 0x9924 */
+ volatile unsigned int BB_timing_control_5; /* 0x9924 - 0x9928 */
+ volatile unsigned int BB_phyonly_warm_reset; /* 0x9928 - 0x992c */
+ volatile unsigned int BB_phyonly_control; /* 0x992c - 0x9930 */
+ volatile char pad__4[0x4]; /* 0x9930 - 0x9934 */
+ volatile unsigned int BB_powertx_rate1; /* 0x9934 - 0x9938 */
+ volatile unsigned int BB_powertx_rate2; /* 0x9938 - 0x993c */
+ volatile unsigned int BB_powertx_max; /* 0x993c - 0x9940 */
+ volatile unsigned int BB_extension_radar; /* 0x9940 - 0x9944 */
+ volatile unsigned int BB_frame_control; /* 0x9944 - 0x9948 */
+ volatile unsigned int BB_timing_control_6; /* 0x9948 - 0x994c */
+ volatile unsigned int BB_spur_mask_controls; /* 0x994c - 0x9950 */
+ volatile unsigned int BB_rx_iq_corr_b0; /* 0x9950 - 0x9954 */
+ volatile unsigned int BB_radar_detection; /* 0x9954 - 0x9958 */
+ volatile unsigned int BB_radar_detection_2; /* 0x9958 - 0x995c */
+ volatile unsigned int BB_tx_phase_ramp_b0; /* 0x995c - 0x9960 */
+ volatile unsigned int BB_switch_table_chn_b0; /* 0x9960 - 0x9964 */
+ volatile unsigned int BB_switch_table_com1; /* 0x9964 - 0x9968 */
+ volatile unsigned int BB_cca_ctrl_2_b0; /* 0x9968 - 0x996c */
+ volatile unsigned int BB_switch_table_com2; /* 0x996c - 0x9970 */
+ volatile unsigned int BB_restart; /* 0x9970 - 0x9974 */
+ volatile char pad__5[0x4]; /* 0x9974 - 0x9978 */
+ volatile unsigned int BB_scrambler_seed; /* 0x9978 - 0x997c */
+ volatile unsigned int BB_rfbus_request; /* 0x997c - 0x9980 */
+ volatile char pad__6[0x20]; /* 0x9980 - 0x99a0 */
+ volatile unsigned int BB_timing_control_11; /* 0x99a0 - 0x99a4 */
+ volatile unsigned int BB_multichain_enable; /* 0x99a4 - 0x99a8 */
+ volatile unsigned int BB_multichain_control; /* 0x99a8 - 0x99ac */
+ volatile unsigned int BB_multichain_gain_ctrl; /* 0x99ac - 0x99b0 */
+ volatile char pad__7[0x4]; /* 0x99b0 - 0x99b4 */
+ volatile unsigned int BB_adc_gain_dc_corr_b0; /* 0x99b4 - 0x99b8 */
+ volatile unsigned int BB_ext_chan_pwr_thr_1; /* 0x99b8 - 0x99bc */
+ volatile unsigned int BB_ext_chan_pwr_thr_2_b0; /* 0x99bc - 0x99c0 */
+ volatile unsigned int BB_ext_chan_scorr_thr; /* 0x99c0 - 0x99c4 */
+ volatile unsigned int BB_ext_chan_detect_win; /* 0x99c4 - 0x99c8 */
+ volatile unsigned int BB_pwr_thr_20_40_det; /* 0x99c8 - 0x99cc */
+ volatile char pad__8[0x4]; /* 0x99cc - 0x99d0 */
+ volatile unsigned int BB_short_gi_delta_slope; /* 0x99d0 - 0x99d4 */
+ volatile char pad__9[0x8]; /* 0x99d4 - 0x99dc */
+ volatile unsigned int BB_chaninfo_ctrl; /* 0x99dc - 0x99e0 */
+ volatile unsigned int BB_heavy_clip_ctrl; /* 0x99e0 - 0x99e4 */
+ volatile unsigned int BB_heavy_clip_20; /* 0x99e4 - 0x99e8 */
+ volatile unsigned int BB_heavy_clip_40; /* 0x99e8 - 0x99ec */
+ volatile unsigned int BB_rifs_srch; /* 0x99ec - 0x99f0 */
+ volatile unsigned int BB_iq_adc_cal_mode; /* 0x99f0 - 0x99f4 */
+ volatile char pad__10[0x8]; /* 0x99f4 - 0x99fc */
+ volatile unsigned int BB_per_chain_csd; /* 0x99fc - 0x9a00 */
+ volatile unsigned int BB_rx_ocgain[128]; /* 0x9a00 - 0x9c00 */
+ volatile unsigned int BB_tx_crc; /* 0x9c00 - 0x9c04 */
+ volatile char pad__11[0xc]; /* 0x9c04 - 0x9c10 */
+ volatile unsigned int BB_iq_adc_meas_0_b0; /* 0x9c10 - 0x9c14 */
+ volatile unsigned int BB_iq_adc_meas_1_b0; /* 0x9c14 - 0x9c18 */
+ volatile unsigned int BB_iq_adc_meas_2_b0; /* 0x9c18 - 0x9c1c */
+ volatile unsigned int BB_iq_adc_meas_3_b0; /* 0x9c1c - 0x9c20 */
+ volatile unsigned int BB_rfbus_grant; /* 0x9c20 - 0x9c24 */
+ volatile unsigned int BB_tstadc; /* 0x9c24 - 0x9c28 */
+ volatile unsigned int BB_tstdac; /* 0x9c28 - 0x9c2c */
+ volatile char pad__12[0x4]; /* 0x9c2c - 0x9c30 */
+ volatile unsigned int BB_illegal_tx_rate; /* 0x9c30 - 0x9c34 */
+ volatile unsigned int BB_spur_report_b0; /* 0x9c34 - 0x9c38 */
+ volatile unsigned int BB_channel_status; /* 0x9c38 - 0x9c3c */
+ volatile unsigned int BB_rssi_b0; /* 0x9c3c - 0x9c40 */
+ volatile unsigned int BB_spur_est_cck_report_b0; /* 0x9c40 - 0x9c44 */
+ volatile char pad__13[0x68]; /* 0x9c44 - 0x9cac */
+ volatile unsigned int BB_chan_info_noise_pwr; /* 0x9cac - 0x9cb0 */
+ volatile unsigned int BB_chan_info_gain_diff; /* 0x9cb0 - 0x9cb4 */
+ volatile unsigned int BB_chan_info_fine_timing; /* 0x9cb4 - 0x9cb8 */
+ volatile unsigned int BB_chan_info_gain_b0; /* 0x9cb8 - 0x9cbc */
+ volatile unsigned int BB_chan_info_chan_tab_b0[60]; /* 0x9cbc - 0x9dac */
+ volatile char pad__14[0x38]; /* 0x9dac - 0x9de4 */
+ volatile unsigned int BB_paprd_am2am_mask; /* 0x9de4 - 0x9de8 */
+ volatile unsigned int BB_paprd_am2pm_mask; /* 0x9de8 - 0x9dec */
+ volatile unsigned int BB_paprd_ht40_mask; /* 0x9dec - 0x9df0 */
+ volatile unsigned int BB_paprd_ctrl0; /* 0x9df0 - 0x9df4 */
+ volatile unsigned int BB_paprd_ctrl1; /* 0x9df4 - 0x9df8 */
+ volatile unsigned int BB_pa_gain123; /* 0x9df8 - 0x9dfc */
+ volatile unsigned int BB_pa_gain45; /* 0x9dfc - 0x9e00 */
+ volatile unsigned int BB_paprd_pre_post_scale_0; /* 0x9e00 - 0x9e04 */
+ volatile unsigned int BB_paprd_pre_post_scale_1; /* 0x9e04 - 0x9e08 */
+ volatile unsigned int BB_paprd_pre_post_scale_2; /* 0x9e08 - 0x9e0c */
+ volatile unsigned int BB_paprd_pre_post_scale_3; /* 0x9e0c - 0x9e10 */
+ volatile unsigned int BB_paprd_pre_post_scale_4; /* 0x9e10 - 0x9e14 */
+ volatile unsigned int BB_paprd_pre_post_scale_5; /* 0x9e14 - 0x9e18 */
+ volatile unsigned int BB_paprd_pre_post_scale_6; /* 0x9e18 - 0x9e1c */
+ volatile unsigned int BB_paprd_pre_post_scale_7; /* 0x9e1c - 0x9e20 */
+ volatile unsigned int BB_paprd_mem_tab[120]; /* 0x9e20 - 0xa000 */
+ volatile unsigned int BB_peak_det_ctrl_1; /* 0xa000 - 0xa004 */
+ volatile unsigned int BB_peak_det_ctrl_2; /* 0xa004 - 0xa008 */
+ volatile unsigned int BB_rx_gain_bounds_1; /* 0xa008 - 0xa00c */
+ volatile unsigned int BB_rx_gain_bounds_2; /* 0xa00c - 0xa010 */
+ volatile unsigned int BB_peak_det_cal_ctrl; /* 0xa010 - 0xa014 */
+ volatile unsigned int BB_agc_dig_dc_ctrl; /* 0xa014 - 0xa018 */
+ volatile unsigned int BB_agc_dig_dc_status_i_b0; /* 0xa018 - 0xa01c */
+ volatile unsigned int BB_agc_dig_dc_status_q_b0; /* 0xa01c - 0xa020 */
+ volatile char pad__15[0x1d4]; /* 0xa020 - 0xa1f4 */
+ volatile unsigned int BB_bbb_txfir_0; /* 0xa1f4 - 0xa1f8 */
+ volatile unsigned int BB_bbb_txfir_1; /* 0xa1f8 - 0xa1fc */
+ volatile unsigned int BB_bbb_txfir_2; /* 0xa1fc - 0xa200 */
+ volatile unsigned int BB_modes_select; /* 0xa200 - 0xa204 */
+ volatile unsigned int BB_bbb_tx_ctrl; /* 0xa204 - 0xa208 */
+ volatile unsigned int BB_bbb_sig_detect; /* 0xa208 - 0xa20c */
+ volatile unsigned int BB_ext_atten_switch_ctl_b0; /* 0xa20c - 0xa210 */
+ volatile unsigned int BB_bbb_rx_ctrl_1; /* 0xa210 - 0xa214 */
+ volatile unsigned int BB_bbb_rx_ctrl_2; /* 0xa214 - 0xa218 */
+ volatile unsigned int BB_bbb_rx_ctrl_3; /* 0xa218 - 0xa21c */
+ volatile unsigned int BB_bbb_rx_ctrl_4; /* 0xa21c - 0xa220 */
+ volatile unsigned int BB_bbb_rx_ctrl_5; /* 0xa220 - 0xa224 */
+ volatile unsigned int BB_bbb_rx_ctrl_6; /* 0xa224 - 0xa228 */
+ volatile unsigned int BB_bbb_dagc_ctrl; /* 0xa228 - 0xa22c */
+ volatile unsigned int BB_force_clken_cck; /* 0xa22c - 0xa230 */
+ volatile unsigned int BB_rx_clear_delay; /* 0xa230 - 0xa234 */
+ volatile unsigned int BB_powertx_rate3; /* 0xa234 - 0xa238 */
+ volatile unsigned int BB_powertx_rate4; /* 0xa238 - 0xa23c */
+ volatile char pad__16[0x4]; /* 0xa23c - 0xa240 */
+ volatile unsigned int BB_cck_spur_mit; /* 0xa240 - 0xa244 */
+ volatile unsigned int BB_panic_watchdog_status; /* 0xa244 - 0xa248 */
+ volatile unsigned int BB_panic_watchdog_ctrl_1; /* 0xa248 - 0xa24c */
+ volatile unsigned int BB_panic_watchdog_ctrl_2; /* 0xa24c - 0xa250 */
+ volatile unsigned int BB_iqcorr_ctrl_cck; /* 0xa250 - 0xa254 */
+ volatile unsigned int BB_bluetooth_cntl; /* 0xa254 - 0xa258 */
+ volatile unsigned int BB_tpc_1; /* 0xa258 - 0xa25c */
+ volatile unsigned int BB_tpc_2; /* 0xa25c - 0xa260 */
+ volatile unsigned int BB_tpc_3; /* 0xa260 - 0xa264 */
+ volatile unsigned int BB_tpc_4_b0; /* 0xa264 - 0xa268 */
+ volatile unsigned int BB_analog_swap; /* 0xa268 - 0xa26c */
+ volatile unsigned int BB_tpc_5_b0; /* 0xa26c - 0xa270 */
+ volatile unsigned int BB_tpc_6_b0; /* 0xa270 - 0xa274 */
+ volatile unsigned int BB_tpc_7; /* 0xa274 - 0xa278 */
+ volatile unsigned int BB_tpc_8; /* 0xa278 - 0xa27c */
+ volatile unsigned int BB_tpc_9; /* 0xa27c - 0xa280 */
+ volatile unsigned int BB_pdadc_tab_b0[32]; /* 0xa280 - 0xa300 */
+ volatile unsigned int BB_cl_tab_b0[16]; /* 0xa300 - 0xa340 */
+ volatile unsigned int BB_cl_map_0_b0; /* 0xa340 - 0xa344 */
+ volatile unsigned int BB_cl_map_1_b0; /* 0xa344 - 0xa348 */
+ volatile unsigned int BB_cl_map_2_b0; /* 0xa348 - 0xa34c */
+ volatile unsigned int BB_cl_map_3_b0; /* 0xa34c - 0xa350 */
+ volatile char pad__17[0x8]; /* 0xa350 - 0xa358 */
+ volatile unsigned int BB_cl_cal_ctrl; /* 0xa358 - 0xa35c */
+ volatile unsigned int BB_cl_map_pal_0_b0; /* 0xa35c - 0xa360 */
+ volatile unsigned int BB_cl_map_pal_1_b0; /* 0xa360 - 0xa364 */
+ volatile unsigned int BB_cl_map_pal_2_b0; /* 0xa364 - 0xa368 */
+ volatile unsigned int BB_cl_map_pal_3_b0; /* 0xa368 - 0xa36c */
+ volatile char pad__18[0x1c]; /* 0xa36c - 0xa388 */
+ volatile unsigned int BB_rifs; /* 0xa388 - 0xa38c */
+ volatile unsigned int BB_powertx_rate5; /* 0xa38c - 0xa390 */
+ volatile unsigned int BB_powertx_rate6; /* 0xa390 - 0xa394 */
+ volatile unsigned int BB_tpc_10; /* 0xa394 - 0xa398 */
+ volatile unsigned int BB_tpc_11_b0; /* 0xa398 - 0xa39c */
+ volatile unsigned int BB_cal_chain_mask; /* 0xa39c - 0xa3a0 */
+ volatile char pad__19[0x1c]; /* 0xa3a0 - 0xa3bc */
+ volatile unsigned int BB_powertx_sub; /* 0xa3bc - 0xa3c0 */
+ volatile unsigned int BB_powertx_rate7; /* 0xa3c0 - 0xa3c4 */
+ volatile unsigned int BB_powertx_rate8; /* 0xa3c4 - 0xa3c8 */
+ volatile unsigned int BB_powertx_rate9; /* 0xa3c8 - 0xa3cc */
+ volatile unsigned int BB_powertx_rate10; /* 0xa3cc - 0xa3d0 */
+ volatile unsigned int BB_powertx_rate11; /* 0xa3d0 - 0xa3d4 */
+ volatile unsigned int BB_powertx_rate12; /* 0xa3d4 - 0xa3d8 */
+ volatile unsigned int BB_force_analog; /* 0xa3d8 - 0xa3dc */
+ volatile unsigned int BB_tpc_12; /* 0xa3dc - 0xa3e0 */
+ volatile unsigned int BB_tpc_13; /* 0xa3e0 - 0xa3e4 */
+ volatile unsigned int BB_tpc_14; /* 0xa3e4 - 0xa3e8 */
+ volatile unsigned int BB_tpc_15; /* 0xa3e8 - 0xa3ec */
+ volatile unsigned int BB_tpc_16; /* 0xa3ec - 0xa3f0 */
+ volatile unsigned int BB_tpc_17; /* 0xa3f0 - 0xa3f4 */
+ volatile unsigned int BB_tpc_18; /* 0xa3f4 - 0xa3f8 */
+ volatile unsigned int BB_tpc_19; /* 0xa3f8 - 0xa3fc */
+ volatile unsigned int BB_tpc_20; /* 0xa3fc - 0xa400 */
+ volatile unsigned int BB_tx_gain_tab_1; /* 0xa400 - 0xa404 */
+ volatile unsigned int BB_tx_gain_tab_2; /* 0xa404 - 0xa408 */
+ volatile unsigned int BB_tx_gain_tab_3; /* 0xa408 - 0xa40c */
+ volatile unsigned int BB_tx_gain_tab_4; /* 0xa40c - 0xa410 */
+ volatile unsigned int BB_tx_gain_tab_5; /* 0xa410 - 0xa414 */
+ volatile unsigned int BB_tx_gain_tab_6; /* 0xa414 - 0xa418 */
+ volatile unsigned int BB_tx_gain_tab_7; /* 0xa418 - 0xa41c */
+ volatile unsigned int BB_tx_gain_tab_8; /* 0xa41c - 0xa420 */
+ volatile unsigned int BB_tx_gain_tab_9; /* 0xa420 - 0xa424 */
+ volatile unsigned int BB_tx_gain_tab_10; /* 0xa424 - 0xa428 */
+ volatile unsigned int BB_tx_gain_tab_11; /* 0xa428 - 0xa42c */
+ volatile unsigned int BB_tx_gain_tab_12; /* 0xa42c - 0xa430 */
+ volatile unsigned int BB_tx_gain_tab_13; /* 0xa430 - 0xa434 */
+ volatile unsigned int BB_tx_gain_tab_14; /* 0xa434 - 0xa438 */
+ volatile unsigned int BB_tx_gain_tab_15; /* 0xa438 - 0xa43c */
+ volatile unsigned int BB_tx_gain_tab_16; /* 0xa43c - 0xa440 */
+ volatile unsigned int BB_tx_gain_tab_17; /* 0xa440 - 0xa444 */
+ volatile unsigned int BB_tx_gain_tab_18; /* 0xa444 - 0xa448 */
+ volatile unsigned int BB_tx_gain_tab_19; /* 0xa448 - 0xa44c */
+ volatile unsigned int BB_tx_gain_tab_20; /* 0xa44c - 0xa450 */
+ volatile unsigned int BB_tx_gain_tab_21; /* 0xa450 - 0xa454 */
+ volatile unsigned int BB_tx_gain_tab_22; /* 0xa454 - 0xa458 */
+ volatile unsigned int BB_tx_gain_tab_23; /* 0xa458 - 0xa45c */
+ volatile unsigned int BB_tx_gain_tab_24; /* 0xa45c - 0xa460 */
+ volatile unsigned int BB_tx_gain_tab_25; /* 0xa460 - 0xa464 */
+ volatile unsigned int BB_tx_gain_tab_26; /* 0xa464 - 0xa468 */
+ volatile unsigned int BB_tx_gain_tab_27; /* 0xa468 - 0xa46c */
+ volatile unsigned int BB_tx_gain_tab_28; /* 0xa46c - 0xa470 */
+ volatile unsigned int BB_tx_gain_tab_29; /* 0xa470 - 0xa474 */
+ volatile unsigned int BB_tx_gain_tab_30; /* 0xa474 - 0xa478 */
+ volatile unsigned int BB_tx_gain_tab_31; /* 0xa478 - 0xa47c */
+ volatile unsigned int BB_tx_gain_tab_32; /* 0xa47c - 0xa480 */
+ volatile unsigned int BB_tx_gain_tab_pal_1; /* 0xa480 - 0xa484 */
+ volatile unsigned int BB_tx_gain_tab_pal_2; /* 0xa484 - 0xa488 */
+ volatile unsigned int BB_tx_gain_tab_pal_3; /* 0xa488 - 0xa48c */
+ volatile unsigned int BB_tx_gain_tab_pal_4; /* 0xa48c - 0xa490 */
+ volatile unsigned int BB_tx_gain_tab_pal_5; /* 0xa490 - 0xa494 */
+ volatile unsigned int BB_tx_gain_tab_pal_6; /* 0xa494 - 0xa498 */
+ volatile unsigned int BB_tx_gain_tab_pal_7; /* 0xa498 - 0xa49c */
+ volatile unsigned int BB_tx_gain_tab_pal_8; /* 0xa49c - 0xa4a0 */
+ volatile unsigned int BB_tx_gain_tab_pal_9; /* 0xa4a0 - 0xa4a4 */
+ volatile unsigned int BB_tx_gain_tab_pal_10; /* 0xa4a4 - 0xa4a8 */
+ volatile unsigned int BB_tx_gain_tab_pal_11; /* 0xa4a8 - 0xa4ac */
+ volatile unsigned int BB_tx_gain_tab_pal_12; /* 0xa4ac - 0xa4b0 */
+ volatile unsigned int BB_tx_gain_tab_pal_13; /* 0xa4b0 - 0xa4b4 */
+ volatile unsigned int BB_tx_gain_tab_pal_14; /* 0xa4b4 - 0xa4b8 */
+ volatile unsigned int BB_tx_gain_tab_pal_15; /* 0xa4b8 - 0xa4bc */
+ volatile unsigned int BB_tx_gain_tab_pal_16; /* 0xa4bc - 0xa4c0 */
+ volatile unsigned int BB_tx_gain_tab_pal_17; /* 0xa4c0 - 0xa4c4 */
+ volatile unsigned int BB_tx_gain_tab_pal_18; /* 0xa4c4 - 0xa4c8 */
+ volatile unsigned int BB_tx_gain_tab_pal_19; /* 0xa4c8 - 0xa4cc */
+ volatile unsigned int BB_tx_gain_tab_pal_20; /* 0xa4cc - 0xa4d0 */
+ volatile unsigned int BB_tx_gain_tab_pal_21; /* 0xa4d0 - 0xa4d4 */
+ volatile unsigned int BB_tx_gain_tab_pal_22; /* 0xa4d4 - 0xa4d8 */
+ volatile unsigned int BB_tx_gain_tab_pal_23; /* 0xa4d8 - 0xa4dc */
+ volatile unsigned int BB_tx_gain_tab_pal_24; /* 0xa4dc - 0xa4e0 */
+ volatile unsigned int BB_tx_gain_tab_pal_25; /* 0xa4e0 - 0xa4e4 */
+ volatile unsigned int BB_tx_gain_tab_pal_26; /* 0xa4e4 - 0xa4e8 */
+ volatile unsigned int BB_tx_gain_tab_pal_27; /* 0xa4e8 - 0xa4ec */
+ volatile unsigned int BB_tx_gain_tab_pal_28; /* 0xa4ec - 0xa4f0 */
+ volatile unsigned int BB_tx_gain_tab_pal_29; /* 0xa4f0 - 0xa4f4 */
+ volatile unsigned int BB_tx_gain_tab_pal_30; /* 0xa4f4 - 0xa4f8 */
+ volatile unsigned int BB_tx_gain_tab_pal_31; /* 0xa4f8 - 0xa4fc */
+ volatile unsigned int BB_tx_gain_tab_pal_32; /* 0xa4fc - 0xa500 */
+ volatile char pad__20[0x18]; /* 0xa500 - 0xa518 */
+ volatile unsigned int BB_caltx_gain_set_0; /* 0xa518 - 0xa51c */
+ volatile unsigned int BB_caltx_gain_set_2; /* 0xa51c - 0xa520 */
+ volatile unsigned int BB_caltx_gain_set_4; /* 0xa520 - 0xa524 */
+ volatile unsigned int BB_caltx_gain_set_6; /* 0xa524 - 0xa528 */
+ volatile unsigned int BB_caltx_gain_set_8; /* 0xa528 - 0xa52c */
+ volatile unsigned int BB_caltx_gain_set_10; /* 0xa52c - 0xa530 */
+ volatile unsigned int BB_caltx_gain_set_12; /* 0xa530 - 0xa534 */
+ volatile unsigned int BB_caltx_gain_set_14; /* 0xa534 - 0xa538 */
+ volatile unsigned int BB_caltx_gain_set_16; /* 0xa538 - 0xa53c */
+ volatile unsigned int BB_caltx_gain_set_18; /* 0xa53c - 0xa540 */
+ volatile unsigned int BB_caltx_gain_set_20; /* 0xa540 - 0xa544 */
+ volatile unsigned int BB_caltx_gain_set_22; /* 0xa544 - 0xa548 */
+ volatile unsigned int BB_caltx_gain_set_24; /* 0xa548 - 0xa54c */
+ volatile unsigned int BB_caltx_gain_set_26; /* 0xa54c - 0xa550 */
+ volatile unsigned int BB_caltx_gain_set_28; /* 0xa550 - 0xa554 */
+ volatile unsigned int BB_caltx_gain_set_30; /* 0xa554 - 0xa558 */
+ volatile unsigned int BB_txiqcal_meas_b0[96]; /* 0xa558 - 0xa6d8 */
+ volatile unsigned int BB_txiqcal_start; /* 0xa6d8 - 0xa6dc */
+ volatile unsigned int BB_txiqcal_control_0; /* 0xa6dc - 0xa6e0 */
+ volatile unsigned int BB_txiqcal_control_1; /* 0xa6e0 - 0xa6e4 */
+ volatile unsigned int BB_txiqcal_control_2; /* 0xa6e4 - 0xa6e8 */
+ volatile unsigned int BB_txiqcal_control_3; /* 0xa6e8 - 0xa6ec */
+ volatile unsigned int BB_txiq_corr_coeff_01_b0; /* 0xa6ec - 0xa6f0 */
+ volatile unsigned int BB_txiq_corr_coeff_23_b0; /* 0xa6f0 - 0xa6f4 */
+ volatile unsigned int BB_txiq_corr_coeff_45_b0; /* 0xa6f4 - 0xa6f8 */
+ volatile unsigned int BB_txiq_corr_coeff_67_b0; /* 0xa6f8 - 0xa6fc */
+ volatile unsigned int BB_txiq_corr_coeff_89_b0; /* 0xa6fc - 0xa700 */
+ volatile unsigned int BB_txiq_corr_coeff_ab_b0; /* 0xa700 - 0xa704 */
+ volatile unsigned int BB_txiq_corr_coeff_cd_b0; /* 0xa704 - 0xa708 */
+ volatile unsigned int BB_txiq_corr_coeff_ef_b0; /* 0xa708 - 0xa70c */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_0; /* 0xa70c - 0xa710 */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_4; /* 0xa710 - 0xa714 */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_8; /* 0xa714 - 0xa718 */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_12; /* 0xa718 - 0xa71c */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_16; /* 0xa71c - 0xa720 */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_20; /* 0xa720 - 0xa724 */
+ volatile unsigned int BB_cal_rxbb_gain_tbl_24; /* 0xa724 - 0xa728 */
+ volatile unsigned int BB_txiqcal_status_b0; /* 0xa728 - 0xa72c */
+ volatile unsigned int BB_paprd_trainer_cntl1; /* 0xa72c - 0xa730 */
+ volatile unsigned int BB_paprd_trainer_cntl2; /* 0xa730 - 0xa734 */
+ volatile unsigned int BB_paprd_trainer_cntl3; /* 0xa734 - 0xa738 */
+ volatile unsigned int BB_paprd_trainer_cntl4; /* 0xa738 - 0xa73c */
+ volatile unsigned int BB_paprd_trainer_stat1; /* 0xa73c - 0xa740 */
+ volatile unsigned int BB_paprd_trainer_stat2; /* 0xa740 - 0xa744 */
+ volatile unsigned int BB_paprd_trainer_stat3; /* 0xa744 - 0xa748 */
+ volatile char pad__21[0x90]; /* 0xa748 - 0xa7d8 */
+ volatile unsigned int BB_fcal_1; /* 0xa7d8 - 0xa7dc */
+ volatile unsigned int BB_fcal_2_b0; /* 0xa7dc - 0xa7e0 */
+ volatile unsigned int BB_radar_bw_filter; /* 0xa7e0 - 0xa7e4 */
+ volatile unsigned int BB_dft_tone_ctrl_b0; /* 0xa7e4 - 0xa7e8 */
+ volatile unsigned int BB_therm_adc_1; /* 0xa7e8 - 0xa7ec */
+ volatile unsigned int BB_therm_adc_2; /* 0xa7ec - 0xa7f0 */
+ volatile unsigned int BB_therm_adc_3; /* 0xa7f0 - 0xa7f4 */
+ volatile unsigned int BB_therm_adc_4; /* 0xa7f4 - 0xa7f8 */
+ volatile unsigned int BB_tx_forced_gain; /* 0xa7f8 - 0xa7fc */
+ volatile unsigned int BB_eco_ctrl; /* 0xa7fc - 0xa800 */
+ volatile char pad__22[0x48]; /* 0xa800 - 0xa848 */
+ volatile unsigned int BB_gain_force_max_gains_b1; /* 0xa848 - 0xa84c */
+ volatile unsigned int BB_gains_min_offsets_b1; /* 0xa84c - 0xa850 */
+ volatile char pad__23[0x1b0]; /* 0xa850 - 0xaa00 */
+ volatile unsigned int BB_rx_ocgain2[128]; /* 0xaa00 - 0xac00 */
+ volatile char pad__24[0x60c]; /* 0xac00 - 0xb20c */
+ volatile unsigned int BB_ext_atten_switch_ctl_b1; /* 0xb20c - 0xb210 */
+} bb_lc_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _BB_LC_REG_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h
new file mode 100644
index 000000000000..4905152f0c0a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h
@@ -0,0 +1,104 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _EFUSE_REG_REG_H_
+#define _EFUSE_REG_REG_H_
+
+#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
+#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
+#define EFUSE_WR_ENABLE_REG_V_MSB 0
+#define EFUSE_WR_ENABLE_REG_V_LSB 0
+#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
+#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
+#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
+#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
+#define EFUSE_INT_ENABLE_REG_V_MSB 0
+#define EFUSE_INT_ENABLE_REG_V_LSB 0
+#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
+#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
+#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
+#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
+#define EFUSE_INT_STATUS_REG_V_MSB 0
+#define EFUSE_INT_STATUS_REG_V_LSB 0
+#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
+#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
+#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
+
+#define BITMASK_WR_REG_ADDRESS 0x0000000c
+#define BITMASK_WR_REG_OFFSET 0x0000000c
+#define BITMASK_WR_REG_V_MSB 31
+#define BITMASK_WR_REG_V_LSB 0
+#define BITMASK_WR_REG_V_MASK 0xffffffff
+#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
+#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
+
+#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
+#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
+#define VDDQ_SETTLE_TIME_REG_V_MSB 31
+#define VDDQ_SETTLE_TIME_REG_V_LSB 0
+#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
+#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
+#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
+
+#define RD_STROBE_PW_REG_ADDRESS 0x00000014
+#define RD_STROBE_PW_REG_OFFSET 0x00000014
+#define RD_STROBE_PW_REG_V_MSB 31
+#define RD_STROBE_PW_REG_V_LSB 0
+#define RD_STROBE_PW_REG_V_MASK 0xffffffff
+#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
+#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
+
+#define PG_STROBE_PW_REG_ADDRESS 0x00000018
+#define PG_STROBE_PW_REG_OFFSET 0x00000018
+#define PG_STROBE_PW_REG_V_MSB 31
+#define PG_STROBE_PW_REG_V_LSB 0
+#define PG_STROBE_PW_REG_V_MASK 0xffffffff
+#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
+#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
+
+#define EFUSE_INTF_ADDRESS 0x00000800
+#define EFUSE_INTF_OFFSET 0x00000800
+#define EFUSE_INTF_R_MSB 31
+#define EFUSE_INTF_R_LSB 0
+#define EFUSE_INTF_R_MASK 0xffffffff
+#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
+#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct efuse_reg_reg_s {
+ volatile unsigned int efuse_wr_enable_reg;
+ volatile unsigned int efuse_int_enable_reg;
+ volatile unsigned int efuse_int_status_reg;
+ volatile unsigned int bitmask_wr_reg;
+ volatile unsigned int vddq_settle_time_reg;
+ volatile unsigned int rd_strobe_pw_reg;
+ volatile unsigned int pg_strobe_pw_reg;
+ unsigned char pad0[2020]; /* pad to 0x800 */
+ volatile unsigned int efuse_intf[512];
+} efuse_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _EFUSE_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
new file mode 100644
index 000000000000..60ea43b7806e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
@@ -0,0 +1,1249 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _GPIO_ATHR_WLAN_REG_REG_H_
+#define _GPIO_ATHR_WLAN_REG_REG_H_
+
+#define WLAN_GPIO_OUT_ADDRESS 0x00000000
+#define WLAN_GPIO_OUT_OFFSET 0x00000000
+#define WLAN_GPIO_OUT_DATA_MSB 25
+#define WLAN_GPIO_OUT_DATA_LSB 0
+#define WLAN_GPIO_OUT_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_OUT_DATA_GET(x) (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB)
+#define WLAN_GPIO_OUT_DATA_SET(x) (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK)
+
+#define WLAN_GPIO_OUT_W1TS_ADDRESS 0x00000004
+#define WLAN_GPIO_OUT_W1TS_OFFSET 0x00000004
+#define WLAN_GPIO_OUT_W1TS_DATA_MSB 25
+#define WLAN_GPIO_OUT_W1TS_DATA_LSB 0
+#define WLAN_GPIO_OUT_W1TS_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_OUT_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB)
+#define WLAN_GPIO_OUT_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK)
+
+#define WLAN_GPIO_OUT_W1TC_ADDRESS 0x00000008
+#define WLAN_GPIO_OUT_W1TC_OFFSET 0x00000008
+#define WLAN_GPIO_OUT_W1TC_DATA_MSB 25
+#define WLAN_GPIO_OUT_W1TC_DATA_LSB 0
+#define WLAN_GPIO_OUT_W1TC_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_OUT_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB)
+#define WLAN_GPIO_OUT_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_ADDRESS 0x0000000c
+#define WLAN_GPIO_ENABLE_OFFSET 0x0000000c
+#define WLAN_GPIO_ENABLE_DATA_MSB 25
+#define WLAN_GPIO_ENABLE_DATA_LSB 0
+#define WLAN_GPIO_ENABLE_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_ENABLE_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB)
+#define WLAN_GPIO_ENABLE_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_W1TS_ADDRESS 0x00000010
+#define WLAN_GPIO_ENABLE_W1TS_OFFSET 0x00000010
+#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB 25
+#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB 0
+#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB)
+#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK)
+
+#define WLAN_GPIO_ENABLE_W1TC_ADDRESS 0x00000014
+#define WLAN_GPIO_ENABLE_W1TC_OFFSET 0x00000014
+#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB 25
+#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB 0
+#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB)
+#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK)
+
+#define WLAN_GPIO_IN_ADDRESS 0x00000018
+#define WLAN_GPIO_IN_OFFSET 0x00000018
+#define WLAN_GPIO_IN_DATA_MSB 25
+#define WLAN_GPIO_IN_DATA_LSB 0
+#define WLAN_GPIO_IN_DATA_MASK 0x03ffffff
+#define WLAN_GPIO_IN_DATA_GET(x) (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB)
+#define WLAN_GPIO_IN_DATA_SET(x) (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK)
+
+#define WLAN_GPIO_STATUS_ADDRESS 0x0000001c
+#define WLAN_GPIO_STATUS_OFFSET 0x0000001c
+#define WLAN_GPIO_STATUS_INTERRUPT_MSB 25
+#define WLAN_GPIO_STATUS_INTERRUPT_LSB 0
+#define WLAN_GPIO_STATUS_INTERRUPT_MASK 0x03ffffff
+#define WLAN_GPIO_STATUS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK)
+
+#define WLAN_GPIO_STATUS_W1TS_ADDRESS 0x00000020
+#define WLAN_GPIO_STATUS_W1TS_OFFSET 0x00000020
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB 25
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB 0
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK 0x03ffffff
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK)
+
+#define WLAN_GPIO_STATUS_W1TC_ADDRESS 0x00000024
+#define WLAN_GPIO_STATUS_W1TC_OFFSET 0x00000024
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB 25
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB 0
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK 0x03ffffff
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB)
+#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK)
+
+#define WLAN_GPIO_PIN0_ADDRESS 0x00000028
+#define WLAN_GPIO_PIN0_OFFSET 0x00000028
+#define WLAN_GPIO_PIN0_CONFIG_MSB 13
+#define WLAN_GPIO_PIN0_CONFIG_LSB 11
+#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN0_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB)
+#define WLAN_GPIO_PIN0_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK)
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN0_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN0_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN0_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN0_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN0_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN0_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN0_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN0_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN0_SOURCE_MSB 0
+#define WLAN_GPIO_PIN0_SOURCE_LSB 0
+#define WLAN_GPIO_PIN0_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN0_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB)
+#define WLAN_GPIO_PIN0_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
+#define WLAN_GPIO_PIN1_OFFSET 0x0000002c
+#define WLAN_GPIO_PIN1_CONFIG_MSB 13
+#define WLAN_GPIO_PIN1_CONFIG_LSB 11
+#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN1_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB)
+#define WLAN_GPIO_PIN1_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK)
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN1_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN1_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN1_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN1_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN1_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN1_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN1_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN1_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN1_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN1_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN1_SOURCE_MSB 0
+#define WLAN_GPIO_PIN1_SOURCE_LSB 0
+#define WLAN_GPIO_PIN1_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN1_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB)
+#define WLAN_GPIO_PIN1_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN2_ADDRESS 0x00000030
+#define WLAN_GPIO_PIN2_OFFSET 0x00000030
+#define WLAN_GPIO_PIN2_CONFIG_MSB 13
+#define WLAN_GPIO_PIN2_CONFIG_LSB 11
+#define WLAN_GPIO_PIN2_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN2_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB)
+#define WLAN_GPIO_PIN2_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK)
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN2_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN2_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN2_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN2_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN2_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN2_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN2_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN2_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN2_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN2_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN2_SOURCE_MSB 0
+#define WLAN_GPIO_PIN2_SOURCE_LSB 0
+#define WLAN_GPIO_PIN2_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN2_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB)
+#define WLAN_GPIO_PIN2_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN3_ADDRESS 0x00000034
+#define WLAN_GPIO_PIN3_OFFSET 0x00000034
+#define WLAN_GPIO_PIN3_CONFIG_MSB 13
+#define WLAN_GPIO_PIN3_CONFIG_LSB 11
+#define WLAN_GPIO_PIN3_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN3_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB)
+#define WLAN_GPIO_PIN3_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK)
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN3_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN3_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN3_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN3_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN3_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN3_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN3_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN3_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN3_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN3_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN3_SOURCE_MSB 0
+#define WLAN_GPIO_PIN3_SOURCE_LSB 0
+#define WLAN_GPIO_PIN3_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN3_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB)
+#define WLAN_GPIO_PIN3_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN4_ADDRESS 0x00000038
+#define WLAN_GPIO_PIN4_OFFSET 0x00000038
+#define WLAN_GPIO_PIN4_CONFIG_MSB 13
+#define WLAN_GPIO_PIN4_CONFIG_LSB 11
+#define WLAN_GPIO_PIN4_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN4_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB)
+#define WLAN_GPIO_PIN4_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK)
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN4_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN4_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN4_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN4_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN4_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN4_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN4_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN4_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN4_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN4_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN4_SOURCE_MSB 0
+#define WLAN_GPIO_PIN4_SOURCE_LSB 0
+#define WLAN_GPIO_PIN4_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN4_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB)
+#define WLAN_GPIO_PIN4_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN5_ADDRESS 0x0000003c
+#define WLAN_GPIO_PIN5_OFFSET 0x0000003c
+#define WLAN_GPIO_PIN5_CONFIG_MSB 13
+#define WLAN_GPIO_PIN5_CONFIG_LSB 11
+#define WLAN_GPIO_PIN5_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN5_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB)
+#define WLAN_GPIO_PIN5_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK)
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN5_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN5_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN5_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN5_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN5_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN5_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN5_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN5_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN5_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN5_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN5_SOURCE_MSB 0
+#define WLAN_GPIO_PIN5_SOURCE_LSB 0
+#define WLAN_GPIO_PIN5_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN5_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB)
+#define WLAN_GPIO_PIN5_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN6_ADDRESS 0x00000040
+#define WLAN_GPIO_PIN6_OFFSET 0x00000040
+#define WLAN_GPIO_PIN6_CONFIG_MSB 13
+#define WLAN_GPIO_PIN6_CONFIG_LSB 11
+#define WLAN_GPIO_PIN6_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN6_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB)
+#define WLAN_GPIO_PIN6_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK)
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN6_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN6_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN6_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN6_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN6_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN6_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN6_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN6_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN6_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN6_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN6_SOURCE_MSB 0
+#define WLAN_GPIO_PIN6_SOURCE_LSB 0
+#define WLAN_GPIO_PIN6_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN6_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB)
+#define WLAN_GPIO_PIN6_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN7_ADDRESS 0x00000044
+#define WLAN_GPIO_PIN7_OFFSET 0x00000044
+#define WLAN_GPIO_PIN7_CONFIG_MSB 13
+#define WLAN_GPIO_PIN7_CONFIG_LSB 11
+#define WLAN_GPIO_PIN7_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN7_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB)
+#define WLAN_GPIO_PIN7_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK)
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN7_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN7_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN7_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN7_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN7_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN7_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN7_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN7_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN7_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN7_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN7_SOURCE_MSB 0
+#define WLAN_GPIO_PIN7_SOURCE_LSB 0
+#define WLAN_GPIO_PIN7_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN7_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB)
+#define WLAN_GPIO_PIN7_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN8_ADDRESS 0x00000048
+#define WLAN_GPIO_PIN8_OFFSET 0x00000048
+#define WLAN_GPIO_PIN8_CONFIG_MSB 13
+#define WLAN_GPIO_PIN8_CONFIG_LSB 11
+#define WLAN_GPIO_PIN8_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN8_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB)
+#define WLAN_GPIO_PIN8_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK)
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN8_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN8_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN8_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN8_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN8_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN8_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN8_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN8_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN8_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN8_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN8_SOURCE_MSB 0
+#define WLAN_GPIO_PIN8_SOURCE_LSB 0
+#define WLAN_GPIO_PIN8_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN8_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB)
+#define WLAN_GPIO_PIN8_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN9_ADDRESS 0x0000004c
+#define WLAN_GPIO_PIN9_OFFSET 0x0000004c
+#define WLAN_GPIO_PIN9_CONFIG_MSB 13
+#define WLAN_GPIO_PIN9_CONFIG_LSB 11
+#define WLAN_GPIO_PIN9_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN9_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB)
+#define WLAN_GPIO_PIN9_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK)
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN9_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN9_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN9_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN9_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN9_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN9_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN9_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN9_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN9_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN9_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN9_SOURCE_MSB 0
+#define WLAN_GPIO_PIN9_SOURCE_LSB 0
+#define WLAN_GPIO_PIN9_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN9_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB)
+#define WLAN_GPIO_PIN9_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN10_ADDRESS 0x00000050
+#define WLAN_GPIO_PIN10_OFFSET 0x00000050
+#define WLAN_GPIO_PIN10_CONFIG_MSB 13
+#define WLAN_GPIO_PIN10_CONFIG_LSB 11
+#define WLAN_GPIO_PIN10_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN10_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB)
+#define WLAN_GPIO_PIN10_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK)
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN10_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN10_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN10_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN10_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN10_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN10_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN10_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN10_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN10_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN10_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN10_SOURCE_MSB 0
+#define WLAN_GPIO_PIN10_SOURCE_LSB 0
+#define WLAN_GPIO_PIN10_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN10_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB)
+#define WLAN_GPIO_PIN10_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN11_ADDRESS 0x00000054
+#define WLAN_GPIO_PIN11_OFFSET 0x00000054
+#define WLAN_GPIO_PIN11_CONFIG_MSB 13
+#define WLAN_GPIO_PIN11_CONFIG_LSB 11
+#define WLAN_GPIO_PIN11_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN11_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB)
+#define WLAN_GPIO_PIN11_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK)
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN11_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN11_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN11_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN11_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN11_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN11_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN11_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN11_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN11_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN11_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN11_SOURCE_MSB 0
+#define WLAN_GPIO_PIN11_SOURCE_LSB 0
+#define WLAN_GPIO_PIN11_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN11_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB)
+#define WLAN_GPIO_PIN11_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN12_ADDRESS 0x00000058
+#define WLAN_GPIO_PIN12_OFFSET 0x00000058
+#define WLAN_GPIO_PIN12_CONFIG_MSB 13
+#define WLAN_GPIO_PIN12_CONFIG_LSB 11
+#define WLAN_GPIO_PIN12_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN12_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB)
+#define WLAN_GPIO_PIN12_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK)
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN12_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN12_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN12_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN12_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN12_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN12_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN12_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN12_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN12_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN12_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN12_SOURCE_MSB 0
+#define WLAN_GPIO_PIN12_SOURCE_LSB 0
+#define WLAN_GPIO_PIN12_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN12_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB)
+#define WLAN_GPIO_PIN12_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
+#define WLAN_GPIO_PIN13_OFFSET 0x0000005c
+#define WLAN_GPIO_PIN13_CONFIG_MSB 13
+#define WLAN_GPIO_PIN13_CONFIG_LSB 11
+#define WLAN_GPIO_PIN13_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN13_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB)
+#define WLAN_GPIO_PIN13_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK)
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN13_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN13_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN13_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN13_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN13_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN13_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN13_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN13_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN13_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN13_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN13_SOURCE_MSB 0
+#define WLAN_GPIO_PIN13_SOURCE_LSB 0
+#define WLAN_GPIO_PIN13_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN13_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB)
+#define WLAN_GPIO_PIN13_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN14_ADDRESS 0x00000060
+#define WLAN_GPIO_PIN14_OFFSET 0x00000060
+#define WLAN_GPIO_PIN14_CONFIG_MSB 13
+#define WLAN_GPIO_PIN14_CONFIG_LSB 11
+#define WLAN_GPIO_PIN14_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN14_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB)
+#define WLAN_GPIO_PIN14_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK)
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN14_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN14_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN14_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN14_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN14_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN14_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN14_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN14_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN14_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN14_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN14_SOURCE_MSB 0
+#define WLAN_GPIO_PIN14_SOURCE_LSB 0
+#define WLAN_GPIO_PIN14_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN14_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB)
+#define WLAN_GPIO_PIN14_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN15_ADDRESS 0x00000064
+#define WLAN_GPIO_PIN15_OFFSET 0x00000064
+#define WLAN_GPIO_PIN15_CONFIG_MSB 13
+#define WLAN_GPIO_PIN15_CONFIG_LSB 11
+#define WLAN_GPIO_PIN15_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN15_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB)
+#define WLAN_GPIO_PIN15_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK)
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN15_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN15_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN15_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN15_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN15_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN15_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN15_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN15_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN15_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN15_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN15_SOURCE_MSB 0
+#define WLAN_GPIO_PIN15_SOURCE_LSB 0
+#define WLAN_GPIO_PIN15_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN15_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB)
+#define WLAN_GPIO_PIN15_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN16_ADDRESS 0x00000068
+#define WLAN_GPIO_PIN16_OFFSET 0x00000068
+#define WLAN_GPIO_PIN16_CONFIG_MSB 13
+#define WLAN_GPIO_PIN16_CONFIG_LSB 11
+#define WLAN_GPIO_PIN16_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN16_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB)
+#define WLAN_GPIO_PIN16_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK)
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN16_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN16_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN16_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN16_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN16_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN16_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN16_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN16_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN16_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN16_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN16_SOURCE_MSB 0
+#define WLAN_GPIO_PIN16_SOURCE_LSB 0
+#define WLAN_GPIO_PIN16_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN16_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB)
+#define WLAN_GPIO_PIN16_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN17_ADDRESS 0x0000006c
+#define WLAN_GPIO_PIN17_OFFSET 0x0000006c
+#define WLAN_GPIO_PIN17_CONFIG_MSB 13
+#define WLAN_GPIO_PIN17_CONFIG_LSB 11
+#define WLAN_GPIO_PIN17_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN17_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB)
+#define WLAN_GPIO_PIN17_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK)
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN17_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN17_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN17_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN17_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN17_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN17_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN17_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN17_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN17_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN17_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN17_SOURCE_MSB 0
+#define WLAN_GPIO_PIN17_SOURCE_LSB 0
+#define WLAN_GPIO_PIN17_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN17_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB)
+#define WLAN_GPIO_PIN17_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN18_ADDRESS 0x00000070
+#define WLAN_GPIO_PIN18_OFFSET 0x00000070
+#define WLAN_GPIO_PIN18_CONFIG_MSB 13
+#define WLAN_GPIO_PIN18_CONFIG_LSB 11
+#define WLAN_GPIO_PIN18_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN18_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB)
+#define WLAN_GPIO_PIN18_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK)
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN18_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN18_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN18_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN18_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN18_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN18_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN18_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN18_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN18_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN18_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN18_SOURCE_MSB 0
+#define WLAN_GPIO_PIN18_SOURCE_LSB 0
+#define WLAN_GPIO_PIN18_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN18_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB)
+#define WLAN_GPIO_PIN18_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN19_ADDRESS 0x00000074
+#define WLAN_GPIO_PIN19_OFFSET 0x00000074
+#define WLAN_GPIO_PIN19_CONFIG_MSB 13
+#define WLAN_GPIO_PIN19_CONFIG_LSB 11
+#define WLAN_GPIO_PIN19_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN19_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB)
+#define WLAN_GPIO_PIN19_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK)
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN19_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN19_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN19_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN19_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN19_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN19_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN19_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN19_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN19_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN19_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN19_SOURCE_MSB 0
+#define WLAN_GPIO_PIN19_SOURCE_LSB 0
+#define WLAN_GPIO_PIN19_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN19_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB)
+#define WLAN_GPIO_PIN19_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN20_ADDRESS 0x00000078
+#define WLAN_GPIO_PIN20_OFFSET 0x00000078
+#define WLAN_GPIO_PIN20_CONFIG_MSB 13
+#define WLAN_GPIO_PIN20_CONFIG_LSB 11
+#define WLAN_GPIO_PIN20_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN20_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB)
+#define WLAN_GPIO_PIN20_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK)
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN20_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN20_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN20_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN20_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN20_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN20_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN20_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN20_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN20_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN20_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN20_SOURCE_MSB 0
+#define WLAN_GPIO_PIN20_SOURCE_LSB 0
+#define WLAN_GPIO_PIN20_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN20_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB)
+#define WLAN_GPIO_PIN20_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN21_ADDRESS 0x0000007c
+#define WLAN_GPIO_PIN21_OFFSET 0x0000007c
+#define WLAN_GPIO_PIN21_CONFIG_MSB 13
+#define WLAN_GPIO_PIN21_CONFIG_LSB 11
+#define WLAN_GPIO_PIN21_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN21_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB)
+#define WLAN_GPIO_PIN21_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK)
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN21_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN21_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN21_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN21_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN21_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN21_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN21_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN21_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN21_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN21_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN21_SOURCE_MSB 0
+#define WLAN_GPIO_PIN21_SOURCE_LSB 0
+#define WLAN_GPIO_PIN21_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN21_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB)
+#define WLAN_GPIO_PIN21_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN22_ADDRESS 0x00000080
+#define WLAN_GPIO_PIN22_OFFSET 0x00000080
+#define WLAN_GPIO_PIN22_CONFIG_MSB 13
+#define WLAN_GPIO_PIN22_CONFIG_LSB 11
+#define WLAN_GPIO_PIN22_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN22_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB)
+#define WLAN_GPIO_PIN22_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK)
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN22_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN22_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN22_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN22_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN22_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN22_PAD_PULL_MSB 6
+#define WLAN_GPIO_PIN22_PAD_PULL_LSB 5
+#define WLAN_GPIO_PIN22_PAD_PULL_MASK 0x00000060
+#define WLAN_GPIO_PIN22_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB)
+#define WLAN_GPIO_PIN22_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK)
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB 4
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB 3
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK 0x00000018
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB)
+#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK)
+#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN22_SOURCE_MSB 0
+#define WLAN_GPIO_PIN22_SOURCE_LSB 0
+#define WLAN_GPIO_PIN22_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN22_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB)
+#define WLAN_GPIO_PIN22_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN23_ADDRESS 0x00000084
+#define WLAN_GPIO_PIN23_OFFSET 0x00000084
+#define WLAN_GPIO_PIN23_CONFIG_MSB 13
+#define WLAN_GPIO_PIN23_CONFIG_LSB 11
+#define WLAN_GPIO_PIN23_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN23_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB)
+#define WLAN_GPIO_PIN23_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK)
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN23_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN23_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN23_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN23_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN23_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN23_SOURCE_MSB 0
+#define WLAN_GPIO_PIN23_SOURCE_LSB 0
+#define WLAN_GPIO_PIN23_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN23_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB)
+#define WLAN_GPIO_PIN23_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN24_ADDRESS 0x00000088
+#define WLAN_GPIO_PIN24_OFFSET 0x00000088
+#define WLAN_GPIO_PIN24_CONFIG_MSB 13
+#define WLAN_GPIO_PIN24_CONFIG_LSB 11
+#define WLAN_GPIO_PIN24_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN24_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB)
+#define WLAN_GPIO_PIN24_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK)
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN24_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN24_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN24_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN24_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN24_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN24_SOURCE_MSB 0
+#define WLAN_GPIO_PIN24_SOURCE_LSB 0
+#define WLAN_GPIO_PIN24_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN24_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB)
+#define WLAN_GPIO_PIN24_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK)
+
+#define WLAN_GPIO_PIN25_ADDRESS 0x0000008c
+#define WLAN_GPIO_PIN25_OFFSET 0x0000008c
+#define WLAN_GPIO_PIN25_CONFIG_MSB 13
+#define WLAN_GPIO_PIN25_CONFIG_LSB 11
+#define WLAN_GPIO_PIN25_CONFIG_MASK 0x00003800
+#define WLAN_GPIO_PIN25_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB)
+#define WLAN_GPIO_PIN25_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK)
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB 10
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB 10
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK 0x00000400
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB)
+#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK)
+#define WLAN_GPIO_PIN25_INT_TYPE_MSB 9
+#define WLAN_GPIO_PIN25_INT_TYPE_LSB 7
+#define WLAN_GPIO_PIN25_INT_TYPE_MASK 0x00000380
+#define WLAN_GPIO_PIN25_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB)
+#define WLAN_GPIO_PIN25_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK)
+#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB 2
+#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB 2
+#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK 0x00000004
+#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB)
+#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK)
+#define WLAN_GPIO_PIN25_SOURCE_MSB 0
+#define WLAN_GPIO_PIN25_SOURCE_LSB 0
+#define WLAN_GPIO_PIN25_SOURCE_MASK 0x00000001
+#define WLAN_GPIO_PIN25_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB)
+#define WLAN_GPIO_PIN25_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK)
+
+#define SDIO_ADDRESS 0x00000090
+#define SDIO_OFFSET 0x00000090
+#define SDIO_PINS_EN_MSB 0
+#define SDIO_PINS_EN_LSB 0
+#define SDIO_PINS_EN_MASK 0x00000001
+#define SDIO_PINS_EN_GET(x) (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB)
+#define SDIO_PINS_EN_SET(x) (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK)
+
+#define FUNC_BUS_ADDRESS 0x00000094
+#define FUNC_BUS_OFFSET 0x00000094
+#define FUNC_BUS_GPIO_MODE_MSB 22
+#define FUNC_BUS_GPIO_MODE_LSB 22
+#define FUNC_BUS_GPIO_MODE_MASK 0x00400000
+#define FUNC_BUS_GPIO_MODE_GET(x) (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB)
+#define FUNC_BUS_GPIO_MODE_SET(x) (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK)
+#define FUNC_BUS_OE_L_MSB 21
+#define FUNC_BUS_OE_L_LSB 0
+#define FUNC_BUS_OE_L_MASK 0x003fffff
+#define FUNC_BUS_OE_L_GET(x) (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB)
+#define FUNC_BUS_OE_L_SET(x) (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK)
+
+#define WL_SOC_APB_ADDRESS 0x00000098
+#define WL_SOC_APB_OFFSET 0x00000098
+#define WL_SOC_APB_TOGGLE_MSB 0
+#define WL_SOC_APB_TOGGLE_LSB 0
+#define WL_SOC_APB_TOGGLE_MASK 0x00000001
+#define WL_SOC_APB_TOGGLE_GET(x) (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB)
+#define WL_SOC_APB_TOGGLE_SET(x) (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK)
+
+#define WLAN_SIGMA_DELTA_ADDRESS 0x0000009c
+#define WLAN_SIGMA_DELTA_OFFSET 0x0000009c
+#define WLAN_SIGMA_DELTA_ENABLE_MSB 16
+#define WLAN_SIGMA_DELTA_ENABLE_LSB 16
+#define WLAN_SIGMA_DELTA_ENABLE_MASK 0x00010000
+#define WLAN_SIGMA_DELTA_ENABLE_GET(x) (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB)
+#define WLAN_SIGMA_DELTA_ENABLE_SET(x) (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK)
+#define WLAN_SIGMA_DELTA_PRESCALAR_MSB 15
+#define WLAN_SIGMA_DELTA_PRESCALAR_LSB 8
+#define WLAN_SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
+#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x) (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB)
+#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x) (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK)
+#define WLAN_SIGMA_DELTA_TARGET_MSB 7
+#define WLAN_SIGMA_DELTA_TARGET_LSB 0
+#define WLAN_SIGMA_DELTA_TARGET_MASK 0x000000ff
+#define WLAN_SIGMA_DELTA_TARGET_GET(x) (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB)
+#define WLAN_SIGMA_DELTA_TARGET_SET(x) (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK)
+
+#define WL_BOOTSTRAP_ADDRESS 0x000000a0
+#define WL_BOOTSTRAP_OFFSET 0x000000a0
+#define WL_BOOTSTRAP_STATUS_MSB 22
+#define WL_BOOTSTRAP_STATUS_LSB 0
+#define WL_BOOTSTRAP_STATUS_MASK 0x007fffff
+#define WL_BOOTSTRAP_STATUS_GET(x) (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB)
+#define WL_BOOTSTRAP_STATUS_SET(x) (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK)
+
+#define CLOCK_GPIO_ADDRESS 0x000000a4
+#define CLOCK_GPIO_OFFSET 0x000000a4
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB 2
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB 2
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK 0x00000004
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x) (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB)
+#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x) (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK)
+#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB 1
+#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB 1
+#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK 0x00000002
+#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB 0
+#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0x00000001
+#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
+
+#define WLAN_DEBUG_CONTROL_ADDRESS 0x000000a8
+#define WLAN_DEBUG_CONTROL_OFFSET 0x000000a8
+#define WLAN_DEBUG_CONTROL_ENABLE_MSB 0
+#define WLAN_DEBUG_CONTROL_ENABLE_LSB 0
+#define WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001
+#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB)
+#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK)
+
+#define WLAN_DEBUG_INPUT_SEL_ADDRESS 0x000000ac
+#define WLAN_DEBUG_INPUT_SEL_OFFSET 0x000000ac
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB 5
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB 4
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK 0x00000030
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK)
+#define WLAN_DEBUG_INPUT_SEL_SRC_MSB 3
+#define WLAN_DEBUG_INPUT_SEL_SRC_LSB 0
+#define WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
+#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK)
+
+#define WLAN_DEBUG_OUT_ADDRESS 0x000000b0
+#define WLAN_DEBUG_OUT_OFFSET 0x000000b0
+#define WLAN_DEBUG_OUT_DATA_MSB 17
+#define WLAN_DEBUG_OUT_DATA_LSB 0
+#define WLAN_DEBUG_OUT_DATA_MASK 0x0003ffff
+#define WLAN_DEBUG_OUT_DATA_GET(x) (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
+#define WLAN_DEBUG_OUT_DATA_SET(x) (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
+
+#define WLAN_RESET_TUPLE_STATUS_ADDRESS 0x000000b4
+#define WLAN_RESET_TUPLE_STATUS_OFFSET 0x000000b4
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
+#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
+#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
+
+#define ANTENNA_SLEEP_CONTROL_ADDRESS 0x000000b8
+#define ANTENNA_SLEEP_CONTROL_OFFSET 0x000000b8
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB 14
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB 10
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK 0x00007c00
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB)
+#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK)
+#define ANTENNA_SLEEP_CONTROL_VALUE_MSB 9
+#define ANTENNA_SLEEP_CONTROL_VALUE_LSB 5
+#define ANTENNA_SLEEP_CONTROL_VALUE_MASK 0x000003e0
+#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB)
+#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK)
+#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB 4
+#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB 0
+#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK 0x0000001f
+#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB)
+#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct gpio_athr_wlan_reg_reg_s {
+ volatile unsigned int wlan_gpio_out;
+ volatile unsigned int wlan_gpio_out_w1ts;
+ volatile unsigned int wlan_gpio_out_w1tc;
+ volatile unsigned int wlan_gpio_enable;
+ volatile unsigned int wlan_gpio_enable_w1ts;
+ volatile unsigned int wlan_gpio_enable_w1tc;
+ volatile unsigned int wlan_gpio_in;
+ volatile unsigned int wlan_gpio_status;
+ volatile unsigned int wlan_gpio_status_w1ts;
+ volatile unsigned int wlan_gpio_status_w1tc;
+ volatile unsigned int wlan_gpio_pin0;
+ volatile unsigned int wlan_gpio_pin1;
+ volatile unsigned int wlan_gpio_pin2;
+ volatile unsigned int wlan_gpio_pin3;
+ volatile unsigned int wlan_gpio_pin4;
+ volatile unsigned int wlan_gpio_pin5;
+ volatile unsigned int wlan_gpio_pin6;
+ volatile unsigned int wlan_gpio_pin7;
+ volatile unsigned int wlan_gpio_pin8;
+ volatile unsigned int wlan_gpio_pin9;
+ volatile unsigned int wlan_gpio_pin10;
+ volatile unsigned int wlan_gpio_pin11;
+ volatile unsigned int wlan_gpio_pin12;
+ volatile unsigned int wlan_gpio_pin13;
+ volatile unsigned int wlan_gpio_pin14;
+ volatile unsigned int wlan_gpio_pin15;
+ volatile unsigned int wlan_gpio_pin16;
+ volatile unsigned int wlan_gpio_pin17;
+ volatile unsigned int wlan_gpio_pin18;
+ volatile unsigned int wlan_gpio_pin19;
+ volatile unsigned int wlan_gpio_pin20;
+ volatile unsigned int wlan_gpio_pin21;
+ volatile unsigned int wlan_gpio_pin22;
+ volatile unsigned int wlan_gpio_pin23;
+ volatile unsigned int wlan_gpio_pin24;
+ volatile unsigned int wlan_gpio_pin25;
+ volatile unsigned int sdio;
+ volatile unsigned int func_bus;
+ volatile unsigned int wl_soc_apb;
+ volatile unsigned int wlan_sigma_delta;
+ volatile unsigned int wl_bootstrap;
+ volatile unsigned int clock_gpio;
+ volatile unsigned int wlan_debug_control;
+ volatile unsigned int wlan_debug_input_sel;
+ volatile unsigned int wlan_debug_out;
+ volatile unsigned int wlan_reset_tuple_status;
+ volatile unsigned int antenna_sleep_control;
+} gpio_athr_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _GPIO_ATHR_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h
new file mode 100644
index 000000000000..2d5c1cd22aa6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h
@@ -0,0 +1,1090 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "gpio_athr_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS
+#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET
+#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB
+#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB
+#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK
+#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x)
+#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x)
+#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS
+#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET
+#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB
+#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB
+#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK
+#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x)
+#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x)
+#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS
+#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET
+#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB
+#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB
+#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK
+#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x)
+#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x)
+#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS
+#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET
+#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB
+#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB
+#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK
+#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x)
+#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x)
+#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS
+#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET
+#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB
+#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB
+#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK
+#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x)
+#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x)
+#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS
+#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET
+#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB
+#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB
+#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK
+#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x)
+#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x)
+#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS
+#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET
+#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB
+#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB
+#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK
+#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x)
+#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x)
+#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS
+#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET
+#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB
+#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB
+#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK
+#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x)
+#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x)
+#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS
+#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET
+#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB
+#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB
+#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK
+#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x)
+#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x)
+#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS
+#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET
+#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB
+#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB
+#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK
+#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x)
+#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x)
+#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS
+#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET
+#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB
+#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
+#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
+#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x)
+#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x)
+#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB
+#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB
+#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK
+#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB
+#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB
+#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK
+#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x)
+#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x)
+#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB
+#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
+#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
+#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x)
+#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x)
+#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB
+#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB
+#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK
+#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x)
+#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x)
+#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB
+#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB
+#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK
+#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x)
+#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x)
+#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB
+#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB
+#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK
+#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x)
+#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x)
+#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS
+#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET
+#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB
+#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB
+#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
+#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x)
+#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x)
+#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB
+#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB
+#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK
+#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB
+#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB
+#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK
+#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x)
+#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x)
+#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB
+#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB
+#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK
+#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x)
+#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x)
+#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB
+#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB
+#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK
+#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x)
+#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x)
+#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB
+#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB
+#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK
+#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x)
+#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x)
+#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB
+#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB
+#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK
+#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x)
+#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x)
+#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS
+#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET
+#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB
+#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB
+#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK
+#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x)
+#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x)
+#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB
+#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB
+#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK
+#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB
+#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB
+#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK
+#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x)
+#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x)
+#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB
+#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB
+#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK
+#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x)
+#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x)
+#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB
+#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB
+#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK
+#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x)
+#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x)
+#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB
+#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB
+#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK
+#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x)
+#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x)
+#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB
+#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB
+#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK
+#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x)
+#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x)
+#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS
+#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET
+#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB
+#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB
+#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK
+#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x)
+#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x)
+#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB
+#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB
+#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK
+#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB
+#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB
+#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK
+#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x)
+#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x)
+#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB
+#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB
+#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK
+#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x)
+#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x)
+#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB
+#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB
+#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK
+#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x)
+#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x)
+#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB
+#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB
+#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK
+#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x)
+#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x)
+#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB
+#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB
+#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK
+#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x)
+#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x)
+#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS
+#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET
+#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB
+#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB
+#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK
+#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x)
+#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x)
+#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB
+#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB
+#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK
+#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB
+#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB
+#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK
+#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x)
+#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x)
+#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB
+#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB
+#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK
+#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x)
+#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x)
+#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB
+#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB
+#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK
+#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x)
+#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x)
+#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB
+#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB
+#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK
+#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x)
+#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x)
+#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB
+#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB
+#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK
+#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x)
+#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x)
+#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS
+#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET
+#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB
+#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB
+#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK
+#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x)
+#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x)
+#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB
+#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB
+#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK
+#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB
+#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB
+#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK
+#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x)
+#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x)
+#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB
+#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB
+#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK
+#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x)
+#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x)
+#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB
+#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB
+#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK
+#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x)
+#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x)
+#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB
+#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB
+#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK
+#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x)
+#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x)
+#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB
+#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB
+#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK
+#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x)
+#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x)
+#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS
+#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET
+#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB
+#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB
+#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK
+#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x)
+#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x)
+#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB
+#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB
+#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK
+#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB
+#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB
+#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK
+#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x)
+#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x)
+#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB
+#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB
+#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK
+#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x)
+#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x)
+#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB
+#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB
+#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK
+#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x)
+#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x)
+#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB
+#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB
+#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK
+#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x)
+#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x)
+#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB
+#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB
+#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK
+#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x)
+#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x)
+#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS
+#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET
+#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB
+#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB
+#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK
+#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x)
+#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x)
+#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB
+#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB
+#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK
+#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB
+#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB
+#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK
+#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x)
+#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x)
+#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB
+#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB
+#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK
+#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x)
+#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x)
+#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB
+#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB
+#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK
+#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x)
+#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x)
+#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB
+#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB
+#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK
+#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x)
+#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x)
+#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB
+#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB
+#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK
+#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x)
+#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x)
+#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS
+#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET
+#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB
+#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB
+#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK
+#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x)
+#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x)
+#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB
+#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB
+#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK
+#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB
+#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB
+#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK
+#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x)
+#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x)
+#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB
+#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB
+#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK
+#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x)
+#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x)
+#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB
+#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB
+#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK
+#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x)
+#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x)
+#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB
+#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB
+#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK
+#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x)
+#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x)
+#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB
+#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB
+#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK
+#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x)
+#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x)
+#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS
+#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET
+#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB
+#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB
+#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK
+#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x)
+#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x)
+#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB
+#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB
+#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK
+#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB
+#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB
+#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK
+#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x)
+#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x)
+#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB
+#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB
+#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK
+#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x)
+#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x)
+#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB
+#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB
+#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK
+#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x)
+#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x)
+#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB
+#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB
+#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK
+#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x)
+#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x)
+#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB
+#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB
+#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK
+#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x)
+#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x)
+#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS
+#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET
+#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB
+#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB
+#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK
+#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x)
+#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x)
+#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB
+#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB
+#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK
+#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB
+#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB
+#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK
+#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x)
+#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x)
+#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB
+#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB
+#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK
+#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x)
+#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x)
+#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB
+#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB
+#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK
+#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x)
+#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x)
+#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB
+#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB
+#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK
+#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x)
+#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x)
+#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB
+#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB
+#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK
+#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x)
+#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x)
+#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS
+#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET
+#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB
+#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB
+#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK
+#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x)
+#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x)
+#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB
+#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB
+#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK
+#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB
+#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB
+#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK
+#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x)
+#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x)
+#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB
+#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB
+#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK
+#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x)
+#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x)
+#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB
+#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB
+#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK
+#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x)
+#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x)
+#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB
+#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB
+#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK
+#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x)
+#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x)
+#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB
+#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB
+#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK
+#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x)
+#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x)
+#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS
+#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET
+#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB
+#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB
+#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK
+#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x)
+#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x)
+#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB
+#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB
+#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK
+#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB
+#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB
+#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK
+#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x)
+#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x)
+#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB
+#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB
+#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK
+#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x)
+#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x)
+#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB
+#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB
+#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK
+#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x)
+#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x)
+#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB
+#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB
+#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK
+#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x)
+#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x)
+#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB
+#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB
+#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK
+#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x)
+#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x)
+#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS
+#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET
+#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB
+#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB
+#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK
+#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x)
+#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x)
+#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB
+#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB
+#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK
+#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB
+#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB
+#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK
+#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x)
+#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x)
+#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB
+#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB
+#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK
+#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x)
+#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x)
+#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB
+#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB
+#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK
+#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x)
+#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x)
+#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB
+#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB
+#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK
+#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x)
+#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x)
+#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB
+#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB
+#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK
+#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x)
+#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x)
+#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS
+#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET
+#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB
+#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB
+#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK
+#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x)
+#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x)
+#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB
+#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB
+#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK
+#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB
+#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB
+#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK
+#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x)
+#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x)
+#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB
+#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB
+#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK
+#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x)
+#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x)
+#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB
+#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB
+#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK
+#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x)
+#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x)
+#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB
+#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB
+#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK
+#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x)
+#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x)
+#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB
+#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB
+#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK
+#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x)
+#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x)
+#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS
+#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET
+#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB
+#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB
+#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK
+#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x)
+#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x)
+#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB
+#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB
+#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK
+#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB
+#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB
+#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK
+#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x)
+#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x)
+#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB
+#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB
+#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK
+#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x)
+#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x)
+#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB
+#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB
+#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK
+#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x)
+#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x)
+#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB
+#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB
+#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK
+#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x)
+#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x)
+#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB
+#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB
+#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK
+#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x)
+#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x)
+#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS
+#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET
+#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB
+#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB
+#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK
+#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x)
+#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x)
+#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB
+#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB
+#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK
+#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB
+#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB
+#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK
+#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x)
+#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x)
+#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB
+#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB
+#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK
+#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x)
+#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x)
+#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB
+#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB
+#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK
+#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x)
+#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x)
+#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB
+#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB
+#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK
+#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x)
+#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x)
+#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB
+#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB
+#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK
+#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x)
+#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x)
+#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS
+#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET
+#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB
+#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB
+#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK
+#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x)
+#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x)
+#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB
+#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB
+#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK
+#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB
+#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB
+#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK
+#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x)
+#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x)
+#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB
+#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB
+#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK
+#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x)
+#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x)
+#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB
+#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB
+#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK
+#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x)
+#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x)
+#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB
+#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB
+#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK
+#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x)
+#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x)
+#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB
+#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB
+#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK
+#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x)
+#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x)
+#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS
+#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET
+#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB
+#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB
+#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK
+#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x)
+#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x)
+#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB
+#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB
+#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK
+#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB
+#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB
+#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK
+#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x)
+#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x)
+#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB
+#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB
+#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK
+#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x)
+#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x)
+#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB
+#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB
+#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK
+#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x)
+#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x)
+#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB
+#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB
+#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK
+#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x)
+#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x)
+#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB
+#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB
+#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK
+#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x)
+#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x)
+#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS
+#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET
+#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB
+#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB
+#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK
+#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x)
+#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x)
+#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB
+#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB
+#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK
+#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB
+#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB
+#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK
+#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x)
+#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x)
+#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB
+#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB
+#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK
+#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x)
+#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x)
+#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB
+#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB
+#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK
+#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x)
+#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x)
+#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB
+#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB
+#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK
+#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x)
+#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x)
+#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB
+#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB
+#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK
+#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x)
+#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x)
+#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS
+#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET
+#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB
+#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB
+#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK
+#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x)
+#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x)
+#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB
+#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB
+#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK
+#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB
+#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB
+#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK
+#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x)
+#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x)
+#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB
+#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB
+#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK
+#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x)
+#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x)
+#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB
+#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB
+#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK
+#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x)
+#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x)
+#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB
+#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB
+#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK
+#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x)
+#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x)
+#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB
+#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB
+#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK
+#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x)
+#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x)
+#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS
+#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET
+#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB
+#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB
+#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK
+#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x)
+#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x)
+#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB
+#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB
+#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK
+#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB
+#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB
+#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK
+#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x)
+#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x)
+#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB
+#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB
+#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK
+#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x)
+#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x)
+#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB
+#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB
+#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK
+#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x)
+#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x)
+#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB
+#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB
+#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK
+#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x)
+#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x)
+#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB
+#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB
+#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK
+#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x)
+#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x)
+#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS
+#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET
+#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB
+#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB
+#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK
+#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x)
+#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x)
+#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB
+#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB
+#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK
+#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB
+#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB
+#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK
+#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x)
+#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x)
+#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB
+#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB
+#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK
+#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x)
+#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x)
+#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB
+#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB
+#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK
+#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x)
+#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x)
+#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB
+#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB
+#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK
+#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x)
+#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x)
+#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB
+#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB
+#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK
+#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x)
+#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x)
+#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS
+#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET
+#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB
+#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB
+#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK
+#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x)
+#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x)
+#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB
+#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB
+#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK
+#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB
+#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB
+#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK
+#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x)
+#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x)
+#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB
+#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB
+#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK
+#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x)
+#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x)
+#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB
+#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB
+#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK
+#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x)
+#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x)
+#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS
+#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET
+#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB
+#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB
+#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK
+#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x)
+#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x)
+#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB
+#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB
+#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK
+#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB
+#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB
+#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK
+#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x)
+#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x)
+#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB
+#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB
+#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK
+#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x)
+#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x)
+#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB
+#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB
+#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK
+#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x)
+#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x)
+#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS
+#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET
+#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB
+#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB
+#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK
+#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x)
+#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x)
+#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB
+#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB
+#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK
+#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x)
+#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x)
+#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB
+#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB
+#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK
+#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x)
+#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x)
+#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB
+#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB
+#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK
+#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x)
+#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x)
+#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB
+#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB
+#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK
+#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x)
+#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x)
+#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS
+#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET
+#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB
+#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB
+#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK
+#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x)
+#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x)
+#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB
+#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB
+#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK
+#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x)
+#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x)
+#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB
+#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB
+#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK
+#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x)
+#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x)
+#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS
+#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET
+#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB
+#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB
+#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK
+#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x)
+#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x)
+#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS
+#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET
+#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB
+#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB
+#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK
+#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x)
+#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x)
+#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB
+#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB
+#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK
+#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x)
+#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x)
+#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS
+#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET
+#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB
+#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB
+#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK
+#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x)
+#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x)
+#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS
+#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x)
+#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x)
+#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h
new file mode 100644
index 000000000000..f700d41851c6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h
@@ -0,0 +1,587 @@
+//
+// Copyright (c) 2002-2009 Atheros Communications Inc.
+// All rights reserved.
+// $ATH_LICENSE_TMAC_DMAGET_C$
+//
+
+/*****************************************************************************/
+/* AR6003 WLAN MAC DMA register definitions */
+/*****************************************************************************/
+
+#ifndef _AR6000_DMAREG_H_
+#define _AR6000_DMAREG_H_
+
+/*
+ * Definitions for the Atheros AR6003 chipset.
+ */
+
+/* DMA Control and Interrupt Registers */
+#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */
+#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */
+#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */
+#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */
+
+#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */
+
+#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */
+#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */
+#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */
+#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */
+#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */
+#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */
+#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
+#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */
+#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */
+
+#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */
+#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF
+
+#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */
+#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */
+#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */
+
+#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */
+#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
+#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
+
+#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */
+#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
+#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
+
+#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */
+#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */
+#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */
+#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
+#define MAC_DMA_FTRIG_64B 0x00000010 /* default */
+#define MAC_DMA_FTRIG_128B 0x00000020
+#define MAC_DMA_FTRIG_192B 0x00000030
+#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */
+#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
+
+#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */
+#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */
+#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
+#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
+#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
+
+#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */
+#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */
+#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */
+#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */
+#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */
+
+#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */
+#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
+
+#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */
+#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
+
+#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */
+#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
+#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
+ /* for which frame completions will cause */
+ /* a reset of the no frame xmit'd timeout */
+
+#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */
+#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
+
+#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */
+#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
+
+#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */
+#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */
+#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */
+#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
+#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
+#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */
+
+
+#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */
+/*
+ * Interrupt Status Registers
+ *
+ * Only the bits in the ISR_P register and the IMR_P registers
+ * control whether the MAC's INTA# output is asserted. The bits in
+ * the secondary interrupt status/mask registers control what bits
+ * are set in the primary interrupt status register; however the
+ * IMR_S* registers DO NOT determine whether INTA# is asserted.
+ * That is INTA# is asserted only when the logical AND of ISR_P
+ * and IMR_P is non-zero. The secondary interrupt mask/status
+ * registers affect what bits are set in ISR_P but they do not
+ * directly affect whether INTA# is asserted.
+ */
+#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
+#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
+#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */
+#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
+#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
+#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
+#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
+#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
+#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
+#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
+#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
+#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
+#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
+#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */
+#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
+#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
+#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */
+#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */
+#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
+#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
+#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */
+#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
+#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
+#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
+#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
+#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
+#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
+#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
+#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */
+#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
+#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
+
+#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */
+#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */
+#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0
+#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
+#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16
+
+#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */
+#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */
+#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0
+#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
+#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16
+
+#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */
+#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */
+#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800
+#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000
+#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000
+#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
+#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
+#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000
+#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000
+#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000
+#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
+#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000
+#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
+#define MAC_DMA_ISR_S2_CST_MASK 0x00400000
+#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000
+#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */
+#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */
+#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
+#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
+#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */
+#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */
+#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
+
+#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */
+#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+
+#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */
+#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
+
+#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */
+#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
+#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
+#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
+#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
+#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
+#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
+#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
+#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
+#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
+#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000
+#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
+#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
+#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
+#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
+#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
+#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
+#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
+
+#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */
+/*
+ * Interrupt Mask Registers
+ *
+ * Only the bits in the IMR control whether the MAC's INTA#
+ * output will be asserted. The bits in the secondary interrupt
+ * mask registers control what bits get set in the primary
+ * interrupt status register; however the IMR_S* registers
+ * DO NOT determine whether INTA# is asserted.
+ */
+#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
+#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
+#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */
+#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
+#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
+#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
+#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
+#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
+#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
+#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
+#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
+#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
+#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
+#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */
+#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
+#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
+#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */
+#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */
+#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
+#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
+#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */
+#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
+#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */
+#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
+#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
+#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
+#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
+#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
+#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/
+#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
+#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
+
+#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */
+#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */
+#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0
+#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */
+#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16
+
+#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */
+#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */
+#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0
+#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */
+#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16
+
+#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */
+#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0
+#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800
+#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000
+#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000
+#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
+#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
+#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000
+#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000
+#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000
+#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
+#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000
+#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
+#define MAC_DMA_IMR_S2_CST_MASK 0x00400000
+#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000
+#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */
+#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */
+#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
+#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
+#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */
+#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */
+#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
+
+#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */
+#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16
+
+#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */
+#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
+
+#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */
+#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
+#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
+#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
+#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
+#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
+#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
+#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
+#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i))
+#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000
+#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
+#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
+#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
+#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
+#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
+#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
+#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
+#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
+
+#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */
+
+/* Shadow copies with read-and-clear access */
+#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */
+#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */
+#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */
+#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */
+#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */
+#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */
+
+#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */
+#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */
+#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */
+/* QCU registers */
+
+#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */
+#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */
+#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */
+#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */
+#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */
+#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */
+#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */
+#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */
+#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */
+#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */
+#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */
+#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */
+#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */
+#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */
+
+
+#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */
+#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */
+#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */
+#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */
+#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */
+#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */
+#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */
+
+#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */
+#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */
+
+#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */
+#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */
+#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */
+#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */
+#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
+#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
+#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
+#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */
+#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr
+ (empty q) */
+#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr
+ (empty beacon q) */
+#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */
+#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */
+#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
+#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */
+#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */
+
+#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */
+#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */
+#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */
+
+#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */
+
+/* DCU registers */
+
+#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */
+#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */
+#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */
+#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */
+#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */
+#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */
+#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */
+#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */
+#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */
+#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */
+#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
+
+#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */
+
+
+#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */
+#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
+#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */
+#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0
+#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */
+#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10
+#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */
+#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20
+/*
+ * Note: even though this field is 8 bits wide the
+ * maximum supported AIFS value is 0xFc. Setting the AIFS value
+ * to 0xFd 0xFe, or 0xFf will not work correctly and will cause
+ * the DCU to hang.
+ */
+#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */
+
+#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */
+#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */
+#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */
+#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */
+#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */
+#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */
+#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */
+#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */
+#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */
+#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */
+#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */
+#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0
+#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */
+#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8
+#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */
+#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14
+
+#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */
+
+#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */
+#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */
+#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */
+#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */
+#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */
+#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */
+#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */
+#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */
+#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */
+#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */
+#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */
+#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */
+#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */
+
+#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */
+#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
+#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */
+#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
+#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000
+
+#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */
+#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D0_EOL_ADDRESS 0x00001180
+#define MAC_DMA_D1_EOL_ADDRESS 0x00001184
+#define MAC_DMA_D2_EOL_ADDRESS 0x00001188
+#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C
+#define MAC_DMA_D4_EOL_ADDRESS 0x00001190
+#define MAC_DMA_D5_EOL_ADDRESS 0x00001194
+#define MAC_DMA_D6_EOL_ADDRESS 0x00001198
+#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C
+#define MAC_DMA_D8_EOL_ADDRESS 0x00001200
+#define MAC_DMA_D9_EOL_ADDRESS 0x00001204
+#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
+
+#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */
+#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0
+#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series
+ station RTS/data failure
+ count reset policy */
+#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series
+ CW reset policy */
+#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */
+
+#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */
+#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */
+#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor
+ setting */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision
+ handling policy */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */
+#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */
+#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
+#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */
+#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */
+#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */
+#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */
+#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */
+
+#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */
+
+
+
+#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */
+#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */
+
+#endif /* _AR6000_DMMAEG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h
new file mode 100644
index 000000000000..9825b7b984fa
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h
@@ -0,0 +1,3061 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MAC_PCU_REG_H_
+#define _MAC_PCU_REG_H_
+
+#define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000
+#define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB)
+#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK)
+
+#define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004
+#define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK)
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB)
+#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK)
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB)
+#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK)
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB)
+#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK)
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB)
+#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK)
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB)
+#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK)
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB)
+#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK)
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB)
+#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK)
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB)
+#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK)
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB)
+#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK)
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB)
+#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK)
+#define MAC_PCU_STA_ADDR_U16_PCF_MSB 20
+#define MAC_PCU_STA_ADDR_U16_PCF_LSB 20
+#define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000
+#define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB)
+#define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK)
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB)
+#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK)
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB)
+#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17
+#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17
+#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000
+#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK)
+#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16
+#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16
+#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000
+#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB)
+#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK)
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB)
+#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK)
+
+#define MAC_PCU_BSSID_L32_ADDRESS 0x00008008
+#define MAC_PCU_BSSID_L32_OFFSET 0x00000008
+#define MAC_PCU_BSSID_L32_ADDR_MSB 31
+#define MAC_PCU_BSSID_L32_ADDR_LSB 0
+#define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff
+#define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB)
+#define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK)
+
+#define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c
+#define MAC_PCU_BSSID_U16_OFFSET 0x0000000c
+#define MAC_PCU_BSSID_U16_AID_MSB 26
+#define MAC_PCU_BSSID_U16_AID_LSB 16
+#define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000
+#define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB)
+#define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK)
+#define MAC_PCU_BSSID_U16_ADDR_MSB 15
+#define MAC_PCU_BSSID_U16_ADDR_LSB 0
+#define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff
+#define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB)
+#define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK)
+
+#define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010
+#define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB)
+#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK)
+
+#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014
+#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB)
+#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK)
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB)
+#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK)
+
+#define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018
+#define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018
+#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29
+#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29
+#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000
+#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB)
+#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK)
+
+#define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c
+#define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB)
+#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK)
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB)
+#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK)
+#define MAC_PCU_USEC_LATENCY_USEC_MSB 7
+#define MAC_PCU_USEC_LATENCY_USEC_LSB 0
+#define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff
+#define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB)
+#define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK)
+
+#define PCU_MAX_CFP_DUR_ADDRESS 0x00008020
+#define PCU_MAX_CFP_DUR_OFFSET 0x00000020
+#define PCU_MAX_CFP_DUR_VALUE_MSB 15
+#define PCU_MAX_CFP_DUR_VALUE_LSB 0
+#define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff
+#define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB)
+#define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK)
+
+#define MAC_PCU_RX_FILTER_ADDRESS 0x00008024
+#define MAC_PCU_RX_FILTER_OFFSET 0x00000024
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB)
+#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK)
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB)
+#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK)
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB)
+#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK)
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB)
+#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK)
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB)
+#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK)
+#define MAC_PCU_RX_FILTER_PS_POLL_MSB 14
+#define MAC_PCU_RX_FILTER_PS_POLL_LSB 14
+#define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000
+#define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB)
+#define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK)
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB)
+#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK)
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB)
+#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB)
+#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK)
+#define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9
+#define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9
+#define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200
+#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB)
+#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK)
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB)
+#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK)
+#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7
+#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7
+#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080
+#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB)
+#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK)
+#define MAC_PCU_RX_FILTER_XR_POLL_MSB 6
+#define MAC_PCU_RX_FILTER_XR_POLL_LSB 6
+#define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040
+#define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB)
+#define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK)
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB)
+#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK)
+#define MAC_PCU_RX_FILTER_BEACON_MSB 4
+#define MAC_PCU_RX_FILTER_BEACON_LSB 4
+#define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010
+#define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB)
+#define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK)
+#define MAC_PCU_RX_FILTER_CONTROL_MSB 3
+#define MAC_PCU_RX_FILTER_CONTROL_LSB 3
+#define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008
+#define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB)
+#define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK)
+#define MAC_PCU_RX_FILTER_BROADCAST_MSB 2
+#define MAC_PCU_RX_FILTER_BROADCAST_LSB 2
+#define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004
+#define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB)
+#define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK)
+#define MAC_PCU_RX_FILTER_MULTICAST_MSB 1
+#define MAC_PCU_RX_FILTER_MULTICAST_LSB 1
+#define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002
+#define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB)
+#define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK)
+#define MAC_PCU_RX_FILTER_UNICAST_MSB 0
+#define MAC_PCU_RX_FILTER_UNICAST_LSB 0
+#define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001
+#define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB)
+#define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK)
+
+#define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028
+#define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB)
+#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK)
+
+#define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c
+#define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB)
+#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK)
+
+#define MAC_PCU_DIAG_SW_ADDRESS 0x00008030
+#define MAC_PCU_DIAG_SW_OFFSET 0x00000030
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB)
+#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK)
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB)
+#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK)
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB)
+#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK)
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB)
+#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK)
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB)
+#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK)
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB)
+#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK)
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB)
+#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK)
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB)
+#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB)
+#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK)
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB)
+#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK)
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB)
+#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK)
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB)
+#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK)
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB)
+#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK)
+#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6
+#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6
+#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040
+#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB)
+#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK)
+#define MAC_PCU_DIAG_SW_HALT_RX_MSB 5
+#define MAC_PCU_DIAG_SW_HALT_RX_LSB 5
+#define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020
+#define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB)
+#define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK)
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB)
+#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK)
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB)
+#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK)
+#define MAC_PCU_DIAG_SW_NO_CTS_MSB 2
+#define MAC_PCU_DIAG_SW_NO_CTS_LSB 2
+#define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004
+#define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB)
+#define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK)
+#define MAC_PCU_DIAG_SW_NO_ACK_MSB 1
+#define MAC_PCU_DIAG_SW_NO_ACK_LSB 1
+#define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002
+#define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB)
+#define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK)
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB)
+#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK)
+
+#define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034
+#define MAC_PCU_TST_ADDAC_OFFSET 0x00000034
+#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20
+#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20
+#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000
+#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB)
+#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK)
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB)
+#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK)
+#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18
+#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18
+#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000
+#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB)
+#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK)
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB)
+#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK)
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB)
+#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK)
+#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14
+#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14
+#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000
+#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB)
+#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK)
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB)
+#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK)
+#define MAC_PCU_TST_ADDAC_LOOP_MSB 2
+#define MAC_PCU_TST_ADDAC_LOOP_LSB 2
+#define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004
+#define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB)
+#define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK)
+#define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1
+#define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1
+#define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002
+#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB)
+#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK)
+#define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0
+#define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0
+#define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001
+#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB)
+#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK)
+
+#define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038
+#define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB)
+#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK)
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB)
+#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK)
+#define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23
+#define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0
+#define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff
+#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB)
+#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK)
+
+#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c
+#define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB)
+#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK)
+#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15
+#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0
+#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff
+#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB)
+#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK)
+
+#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040
+#define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB)
+#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK)
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB)
+#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK)
+
+#define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044
+#define MAC_PCU_GATED_CLKS_OFFSET 0x00000044
+#define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3
+#define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3
+#define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008
+#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK)
+#define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2
+#define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2
+#define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004
+#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK)
+#define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1
+#define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1
+#define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002
+#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB)
+#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK)
+
+#define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048
+#define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048
+#define MAC_PCU_OBS_BUS_2_VALUE_MSB 17
+#define MAC_PCU_OBS_BUS_2_VALUE_LSB 0
+#define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff
+#define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB)
+#define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK)
+
+#define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c
+#define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c
+#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30
+#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25
+#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000
+#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24
+#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20
+#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000
+#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB)
+#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK)
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB)
+#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK)
+#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5
+#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5
+#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020
+#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB)
+#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK)
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB)
+#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK)
+#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2
+#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2
+#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004
+#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB)
+#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK)
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB)
+#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK)
+
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB)
+#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK)
+
+#define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054
+#define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB)
+#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK)
+
+#define MAC_PCU_NAV_ADDRESS 0x00008058
+#define MAC_PCU_NAV_OFFSET 0x00000058
+#define MAC_PCU_NAV_VALUE_MSB 25
+#define MAC_PCU_NAV_VALUE_LSB 0
+#define MAC_PCU_NAV_VALUE_MASK 0x03ffffff
+#define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB)
+#define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK)
+
+#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c
+#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB)
+#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK)
+
+#define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060
+#define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064
+#define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068
+#define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB)
+#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK)
+
+#define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c
+#define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c
+#define MAC_PCU_BEACON_CNT_VALUE_MSB 15
+#define MAC_PCU_BEACON_CNT_VALUE_LSB 0
+#define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff
+#define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB)
+#define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK)
+
+#define MAC_PCU_XRMODE_ADDRESS 0x00008070
+#define MAC_PCU_XRMODE_OFFSET 0x00000070
+#define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31
+#define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20
+#define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000
+#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB)
+#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK)
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB)
+#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK)
+#define MAC_PCU_XRMODE_POLL_TYPE_MSB 5
+#define MAC_PCU_XRMODE_POLL_TYPE_LSB 0
+#define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f
+#define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB)
+#define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK)
+
+#define MAC_PCU_XRDEL_ADDRESS 0x00008074
+#define MAC_PCU_XRDEL_OFFSET 0x00000074
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB)
+#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK)
+#define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15
+#define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0
+#define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff
+#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB)
+#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK)
+
+#define MAC_PCU_XRTO_ADDRESS 0x00008078
+#define MAC_PCU_XRTO_OFFSET 0x00000078
+#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31
+#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16
+#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000
+#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB)
+#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK)
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB)
+#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK)
+
+#define MAC_PCU_XRCRP_ADDRESS 0x0000807c
+#define MAC_PCU_XRCRP_OFFSET 0x0000007c
+#define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31
+#define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16
+#define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000
+#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB)
+#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK)
+#define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0
+#define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0
+#define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001
+#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB)
+#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK)
+
+#define MAC_PCU_XRSTMP_ADDRESS 0x00008080
+#define MAC_PCU_XRSTMP_OFFSET 0x00000080
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB)
+#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB)
+#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK)
+
+#define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084
+#define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB)
+#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK)
+
+#define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088
+#define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB)
+#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK)
+
+#define MAC_PCU_TPC_ADDRESS 0x0000808c
+#define MAC_PCU_TPC_OFFSET 0x0000008c
+#define MAC_PCU_TPC_CHIRP_PWR_MSB 21
+#define MAC_PCU_TPC_CHIRP_PWR_LSB 16
+#define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000
+#define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB)
+#define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK)
+#define MAC_PCU_TPC_CTS_PWR_MSB 13
+#define MAC_PCU_TPC_CTS_PWR_LSB 8
+#define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00
+#define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB)
+#define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK)
+#define MAC_PCU_TPC_ACK_PWR_MSB 5
+#define MAC_PCU_TPC_ACK_PWR_LSB 0
+#define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f
+#define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB)
+#define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK)
+
+#define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090
+#define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090
+#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31
+#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0
+#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff
+#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB)
+#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK)
+
+#define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094
+#define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094
+#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31
+#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0
+#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff
+#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB)
+#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK)
+
+#define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098
+#define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB)
+#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK)
+
+#define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c
+#define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c
+#define MAC_PCU_CYCLE_CNT_VALUE_MSB 31
+#define MAC_PCU_CYCLE_CNT_VALUE_LSB 0
+#define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff
+#define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB)
+#define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK)
+
+#define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0
+#define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB)
+#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK)
+
+#define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4
+#define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4
+#define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31
+#define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16
+#define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000
+#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB)
+#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK)
+
+#define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8
+#define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB)
+#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK)
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB)
+#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK)
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB)
+#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK)
+
+#define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac
+#define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK)
+
+#define MAC_PCU_XRLAT_ADDRESS 0x000080b0
+#define MAC_PCU_XRLAT_OFFSET 0x000000b0
+#define MAC_PCU_XRLAT_VALUE_MSB 11
+#define MAC_PCU_XRLAT_VALUE_LSB 0
+#define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff
+#define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB)
+#define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK)
+
+#define MAC_PCU_RXBUF_ADDRESS 0x000080b4
+#define MAC_PCU_RXBUF_OFFSET 0x000000b4
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB)
+#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK)
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB)
+#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK)
+
+#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8
+#define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB)
+#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK)
+
+#define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc
+#define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB)
+#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK)
+
+#define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0
+#define MAC_PCU_MISC_MODE_OFFSET 0x000000c0
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK)
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB)
+#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK)
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB)
+#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK)
+#define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27
+#define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27
+#define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000
+#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB)
+#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK)
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB)
+#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK)
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB)
+#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK)
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB)
+#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK)
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB)
+#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK)
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB)
+#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK)
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB)
+#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK)
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB)
+#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK)
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB)
+#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK)
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB)
+#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK)
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB)
+#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK)
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB)
+#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK)
+
+#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4
+#define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB)
+#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK)
+
+#define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8
+#define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB)
+#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc
+#define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4
+#define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK)
+
+#define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc
+#define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc
+#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15
+#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0
+#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff
+#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB)
+#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4
+#define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec
+#define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11
+#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10
+#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00
+#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK)
+
+#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4
+#define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB)
+#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK)
+
+#define MAC_PCU_TXSIFS_ADDRESS 0x000080f8
+#define MAC_PCU_TXSIFS_OFFSET 0x000000f8
+#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14
+#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12
+#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000
+#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB)
+#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK)
+#define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11
+#define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8
+#define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00
+#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB)
+#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK)
+#define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7
+#define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0
+#define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff
+#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB)
+#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK)
+
+#define MAC_PCU_TXOP_X_ADDRESS 0x000080fc
+#define MAC_PCU_TXOP_X_OFFSET 0x000000fc
+#define MAC_PCU_TXOP_X_VALUE_MSB 7
+#define MAC_PCU_TXOP_X_VALUE_LSB 0
+#define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff
+#define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB)
+#define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK)
+
+#define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100
+#define MAC_PCU_TXOP_0_3_OFFSET 0x00000100
+#define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31
+#define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24
+#define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000
+#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23
+#define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16
+#define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000
+#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15
+#define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8
+#define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00
+#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK)
+#define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7
+#define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0
+#define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff
+#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB)
+#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK)
+
+#define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104
+#define MAC_PCU_TXOP_4_7_OFFSET 0x00000104
+#define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31
+#define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24
+#define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000
+#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23
+#define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16
+#define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000
+#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15
+#define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8
+#define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00
+#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK)
+#define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7
+#define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0
+#define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff
+#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB)
+#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK)
+
+#define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108
+#define MAC_PCU_TXOP_8_11_OFFSET 0x00000108
+#define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31
+#define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24
+#define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000
+#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23
+#define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16
+#define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000
+#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15
+#define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8
+#define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00
+#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK)
+#define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7
+#define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0
+#define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff
+#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB)
+#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK)
+
+#define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c
+#define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c
+#define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31
+#define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24
+#define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000
+#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23
+#define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16
+#define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000
+#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15
+#define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8
+#define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00
+#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK)
+#define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7
+#define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0
+#define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff
+#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB)
+#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110
+#define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2
+#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2
+#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004
+#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK)
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114
+#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK)
+
+#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118
+#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB)
+#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK)
+
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB)
+#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK)
+
+#define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120
+#define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB)
+#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK)
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB)
+#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK)
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB)
+#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK)
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB)
+#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK)
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB)
+#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK)
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB)
+#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK)
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB)
+#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK)
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB)
+#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK)
+
+#define MAC_PCU_20_40_MODE_ADDRESS 0x00008124
+#define MAC_PCU_20_40_MODE_OFFSET 0x00000124
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB)
+#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK)
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB)
+#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK)
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB)
+#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK)
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB)
+#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK)
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB)
+#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK)
+
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB)
+#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK)
+
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB)
+#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK)
+
+#define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130
+#define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB)
+#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK)
+
+#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134
+#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB)
+#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK)
+
+#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138
+#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB)
+#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK)
+
+#define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c
+#define MAC_PCU_TX_TIMER_OFFSET 0x0000013c
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK)
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK)
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB)
+#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK)
+#define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14
+#define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0
+#define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff
+#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB)
+#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK)
+
+#define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140
+#define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB)
+#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK)
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB)
+#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK)
+
+#define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144
+#define MAC_PCU_MISC_MODE2_OFFSET 0x00000144
+#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31
+#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28
+#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000
+#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK)
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB)
+#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK)
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB)
+#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB)
+#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB)
+#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK)
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB)
+#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20
+#define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20
+#define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000
+#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK)
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB)
+#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK)
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB)
+#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK)
+#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17
+#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17
+#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000
+#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB)
+#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK)
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB)
+#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK)
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB)
+#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK)
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB)
+#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK)
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5
+#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5
+#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020
+#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3
+#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3
+#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008
+#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB)
+#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK)
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB)
+#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK)
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK)
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB)
+#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK)
+
+#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148
+#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB)
+#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK)
+
+#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c
+#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB)
+#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK)
+
+#define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150
+#define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB)
+#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK)
+
+#define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154
+#define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154
+#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15
+#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0
+#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff
+#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB)
+#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB)
+#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK)
+
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB)
+#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB)
+#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164
+#define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB)
+#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK)
+
+#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168
+#define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB)
+#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK)
+
+#define MAC_PCU_BT_BT_ADDRESS 0x00008200
+#define MAC_PCU_BT_BT_OFFSET 0x00000200
+#define MAC_PCU_BT_BT_WEIGHT_MSB 31
+#define MAC_PCU_BT_BT_WEIGHT_LSB 0
+#define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff
+#define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK)
+
+#define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300
+#define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK)
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB)
+#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_1_ADDRESS 0x00008304
+#define MAC_PCU_BT_WL_1_OFFSET 0x00000304
+#define MAC_PCU_BT_WL_1_WEIGHT_MSB 31
+#define MAC_PCU_BT_WL_1_WEIGHT_LSB 0
+#define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff
+#define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_2_ADDRESS 0x00008308
+#define MAC_PCU_BT_WL_2_OFFSET 0x00000308
+#define MAC_PCU_BT_WL_2_WEIGHT_MSB 31
+#define MAC_PCU_BT_WL_2_WEIGHT_LSB 0
+#define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff
+#define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c
+#define MAC_PCU_BT_WL_3_OFFSET 0x0000030c
+#define MAC_PCU_BT_WL_3_WEIGHT_MSB 31
+#define MAC_PCU_BT_WL_3_WEIGHT_LSB 0
+#define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff
+#define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK)
+
+#define MAC_PCU_BT_WL_4_ADDRESS 0x00008310
+#define MAC_PCU_BT_WL_4_OFFSET 0x00000310
+#define MAC_PCU_BT_WL_4_WEIGHT_MSB 31
+#define MAC_PCU_BT_WL_4_WEIGHT_LSB 0
+#define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff
+#define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB)
+#define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK)
+
+#define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314
+#define MAC_PCU_COEX_EPTA_OFFSET 0x00000314
+#define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12
+#define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6
+#define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0
+#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB)
+#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK)
+#define MAC_PCU_COEX_EPTA_LINKID_MSB 5
+#define MAC_PCU_COEX_EPTA_LINKID_LSB 0
+#define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f
+#define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB)
+#define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318
+#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c
+#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320
+#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK)
+
+#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324
+#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB)
+#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328
+#define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c
+#define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330
+#define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK)
+
+#define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334
+#define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB)
+#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338
+#define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB)
+#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB)
+#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK)
+
+#define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c
+#define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c
+#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17
+#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0
+#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff
+#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340
+#define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340
+#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26
+#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0
+#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff
+#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK)
+
+#define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344
+#define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344
+#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23
+#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0
+#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff
+#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB)
+#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK)
+
+#define HT_HALF_GI_RATE1_ADDRESS 0x00008348
+#define HT_HALF_GI_RATE1_OFFSET 0x00000348
+#define HT_HALF_GI_RATE1_MCS3_MSB 31
+#define HT_HALF_GI_RATE1_MCS3_LSB 24
+#define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000
+#define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB)
+#define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK)
+#define HT_HALF_GI_RATE1_MCS2_MSB 23
+#define HT_HALF_GI_RATE1_MCS2_LSB 16
+#define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000
+#define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB)
+#define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK)
+#define HT_HALF_GI_RATE1_MCS1_MSB 15
+#define HT_HALF_GI_RATE1_MCS1_LSB 8
+#define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00
+#define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB)
+#define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK)
+#define HT_HALF_GI_RATE1_MCS0_MSB 7
+#define HT_HALF_GI_RATE1_MCS0_LSB 0
+#define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff
+#define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB)
+#define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK)
+
+#define HT_HALF_GI_RATE2_ADDRESS 0x0000834c
+#define HT_HALF_GI_RATE2_OFFSET 0x0000034c
+#define HT_HALF_GI_RATE2_MCS7_MSB 31
+#define HT_HALF_GI_RATE2_MCS7_LSB 24
+#define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000
+#define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB)
+#define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK)
+#define HT_HALF_GI_RATE2_MCS6_MSB 23
+#define HT_HALF_GI_RATE2_MCS6_LSB 16
+#define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000
+#define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB)
+#define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK)
+#define HT_HALF_GI_RATE2_MCS5_MSB 15
+#define HT_HALF_GI_RATE2_MCS5_LSB 8
+#define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00
+#define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB)
+#define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK)
+#define HT_HALF_GI_RATE2_MCS4_MSB 7
+#define HT_HALF_GI_RATE2_MCS4_LSB 0
+#define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff
+#define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB)
+#define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK)
+
+#define HT_FULL_GI_RATE1_ADDRESS 0x00008350
+#define HT_FULL_GI_RATE1_OFFSET 0x00000350
+#define HT_FULL_GI_RATE1_MCS3_MSB 31
+#define HT_FULL_GI_RATE1_MCS3_LSB 24
+#define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000
+#define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB)
+#define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK)
+#define HT_FULL_GI_RATE1_MCS2_MSB 23
+#define HT_FULL_GI_RATE1_MCS2_LSB 16
+#define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000
+#define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB)
+#define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK)
+#define HT_FULL_GI_RATE1_MCS1_MSB 15
+#define HT_FULL_GI_RATE1_MCS1_LSB 8
+#define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00
+#define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB)
+#define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK)
+#define HT_FULL_GI_RATE1_MCS0_MSB 7
+#define HT_FULL_GI_RATE1_MCS0_LSB 0
+#define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff
+#define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB)
+#define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK)
+
+#define HT_FULL_GI_RATE2_ADDRESS 0x00008354
+#define HT_FULL_GI_RATE2_OFFSET 0x00000354
+#define HT_FULL_GI_RATE2_MCS7_MSB 31
+#define HT_FULL_GI_RATE2_MCS7_LSB 24
+#define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000
+#define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB)
+#define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK)
+#define HT_FULL_GI_RATE2_MCS6_MSB 23
+#define HT_FULL_GI_RATE2_MCS6_LSB 16
+#define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000
+#define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB)
+#define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK)
+#define HT_FULL_GI_RATE2_MCS5_MSB 15
+#define HT_FULL_GI_RATE2_MCS5_LSB 8
+#define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00
+#define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB)
+#define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK)
+#define HT_FULL_GI_RATE2_MCS4_MSB 7
+#define HT_FULL_GI_RATE2_MCS4_LSB 0
+#define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff
+#define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB)
+#define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK)
+
+#define LEGACY_RATE1_ADDRESS 0x00008358
+#define LEGACY_RATE1_OFFSET 0x00000358
+#define LEGACY_RATE1_RATE12_MSB 29
+#define LEGACY_RATE1_RATE12_LSB 24
+#define LEGACY_RATE1_RATE12_MASK 0x3f000000
+#define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB)
+#define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK)
+#define LEGACY_RATE1_RATE11_MSB 23
+#define LEGACY_RATE1_RATE11_LSB 18
+#define LEGACY_RATE1_RATE11_MASK 0x00fc0000
+#define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB)
+#define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK)
+#define LEGACY_RATE1_RATE10_MSB 17
+#define LEGACY_RATE1_RATE10_LSB 12
+#define LEGACY_RATE1_RATE10_MASK 0x0003f000
+#define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB)
+#define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK)
+#define LEGACY_RATE1_RATE9_MSB 11
+#define LEGACY_RATE1_RATE9_LSB 6
+#define LEGACY_RATE1_RATE9_MASK 0x00000fc0
+#define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB)
+#define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK)
+#define LEGACY_RATE1_RATE8_MSB 5
+#define LEGACY_RATE1_RATE8_LSB 0
+#define LEGACY_RATE1_RATE8_MASK 0x0000003f
+#define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB)
+#define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK)
+
+#define LEGACY_RATE2_ADDRESS 0x0000835c
+#define LEGACY_RATE2_OFFSET 0x0000035c
+#define LEGACY_RATE2_RATE25_MSB 29
+#define LEGACY_RATE2_RATE25_LSB 24
+#define LEGACY_RATE2_RATE25_MASK 0x3f000000
+#define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB)
+#define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK)
+#define LEGACY_RATE2_RATE24_MSB 23
+#define LEGACY_RATE2_RATE24_LSB 18
+#define LEGACY_RATE2_RATE24_MASK 0x00fc0000
+#define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB)
+#define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK)
+#define LEGACY_RATE2_RATE15_MSB 17
+#define LEGACY_RATE2_RATE15_LSB 12
+#define LEGACY_RATE2_RATE15_MASK 0x0003f000
+#define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB)
+#define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK)
+#define LEGACY_RATE2_RATE14_MSB 11
+#define LEGACY_RATE2_RATE14_LSB 6
+#define LEGACY_RATE2_RATE14_MASK 0x00000fc0
+#define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB)
+#define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK)
+#define LEGACY_RATE2_RATE13_MSB 5
+#define LEGACY_RATE2_RATE13_LSB 0
+#define LEGACY_RATE2_RATE13_MASK 0x0000003f
+#define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB)
+#define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK)
+
+#define LEGACY_RATE3_ADDRESS 0x00008360
+#define LEGACY_RATE3_OFFSET 0x00000360
+#define LEGACY_RATE3_RATE30_MSB 29
+#define LEGACY_RATE3_RATE30_LSB 24
+#define LEGACY_RATE3_RATE30_MASK 0x3f000000
+#define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB)
+#define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK)
+#define LEGACY_RATE3_RATE29_MSB 23
+#define LEGACY_RATE3_RATE29_LSB 18
+#define LEGACY_RATE3_RATE29_MASK 0x00fc0000
+#define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB)
+#define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK)
+#define LEGACY_RATE3_RATE28_MSB 17
+#define LEGACY_RATE3_RATE28_LSB 12
+#define LEGACY_RATE3_RATE28_MASK 0x0003f000
+#define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB)
+#define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK)
+#define LEGACY_RATE3_RATE27_MSB 11
+#define LEGACY_RATE3_RATE27_LSB 6
+#define LEGACY_RATE3_RATE27_MASK 0x00000fc0
+#define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB)
+#define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK)
+#define LEGACY_RATE3_RATE26_MSB 5
+#define LEGACY_RATE3_RATE26_LSB 0
+#define LEGACY_RATE3_RATE26_MASK 0x0000003f
+#define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB)
+#define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK)
+
+#define RX_INT_FILTER_ADDRESS 0x00008364
+#define RX_INT_FILTER_OFFSET 0x00000364
+#define RX_INT_FILTER_BEACON_MSB 17
+#define RX_INT_FILTER_BEACON_LSB 17
+#define RX_INT_FILTER_BEACON_MASK 0x00020000
+#define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB)
+#define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK)
+#define RX_INT_FILTER_AMPDU_MSB 16
+#define RX_INT_FILTER_AMPDU_LSB 16
+#define RX_INT_FILTER_AMPDU_MASK 0x00010000
+#define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB)
+#define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK)
+#define RX_INT_FILTER_EOSP_MSB 15
+#define RX_INT_FILTER_EOSP_LSB 15
+#define RX_INT_FILTER_EOSP_MASK 0x00008000
+#define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB)
+#define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK)
+#define RX_INT_FILTER_LENGTH_LOW_MSB 14
+#define RX_INT_FILTER_LENGTH_LOW_LSB 14
+#define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000
+#define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB)
+#define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK)
+#define RX_INT_FILTER_LENGTH_HIGH_MSB 13
+#define RX_INT_FILTER_LENGTH_HIGH_LSB 13
+#define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000
+#define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB)
+#define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK)
+#define RX_INT_FILTER_RSSI_MSB 12
+#define RX_INT_FILTER_RSSI_LSB 12
+#define RX_INT_FILTER_RSSI_MASK 0x00001000
+#define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB)
+#define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK)
+#define RX_INT_FILTER_RATE_LOW_MSB 11
+#define RX_INT_FILTER_RATE_LOW_LSB 11
+#define RX_INT_FILTER_RATE_LOW_MASK 0x00000800
+#define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB)
+#define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK)
+#define RX_INT_FILTER_RATE_HIGH_MSB 10
+#define RX_INT_FILTER_RATE_HIGH_LSB 10
+#define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400
+#define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB)
+#define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK)
+#define RX_INT_FILTER_MORE_FRAG_MSB 9
+#define RX_INT_FILTER_MORE_FRAG_LSB 9
+#define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200
+#define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB)
+#define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK)
+#define RX_INT_FILTER_MORE_DATA_MSB 8
+#define RX_INT_FILTER_MORE_DATA_LSB 8
+#define RX_INT_FILTER_MORE_DATA_MASK 0x00000100
+#define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB)
+#define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK)
+#define RX_INT_FILTER_RETRY_MSB 7
+#define RX_INT_FILTER_RETRY_LSB 7
+#define RX_INT_FILTER_RETRY_MASK 0x00000080
+#define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB)
+#define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK)
+#define RX_INT_FILTER_CTS_MSB 6
+#define RX_INT_FILTER_CTS_LSB 6
+#define RX_INT_FILTER_CTS_MASK 0x00000040
+#define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB)
+#define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK)
+#define RX_INT_FILTER_ACK_MSB 5
+#define RX_INT_FILTER_ACK_LSB 5
+#define RX_INT_FILTER_ACK_MASK 0x00000020
+#define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB)
+#define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK)
+#define RX_INT_FILTER_RTS_MSB 4
+#define RX_INT_FILTER_RTS_LSB 4
+#define RX_INT_FILTER_RTS_MASK 0x00000010
+#define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB)
+#define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK)
+#define RX_INT_FILTER_MCAST_MSB 3
+#define RX_INT_FILTER_MCAST_LSB 3
+#define RX_INT_FILTER_MCAST_MASK 0x00000008
+#define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB)
+#define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK)
+#define RX_INT_FILTER_BCAST_MSB 2
+#define RX_INT_FILTER_BCAST_LSB 2
+#define RX_INT_FILTER_BCAST_MASK 0x00000004
+#define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB)
+#define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK)
+#define RX_INT_FILTER_DIRECTED_MSB 1
+#define RX_INT_FILTER_DIRECTED_LSB 1
+#define RX_INT_FILTER_DIRECTED_MASK 0x00000002
+#define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB)
+#define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK)
+#define RX_INT_FILTER_ENABLE_MSB 0
+#define RX_INT_FILTER_ENABLE_LSB 0
+#define RX_INT_FILTER_ENABLE_MASK 0x00000001
+#define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB)
+#define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK)
+
+#define RX_INT_OVERFLOW_ADDRESS 0x00008368
+#define RX_INT_OVERFLOW_OFFSET 0x00000368
+#define RX_INT_OVERFLOW_STATUS_MSB 0
+#define RX_INT_OVERFLOW_STATUS_LSB 0
+#define RX_INT_OVERFLOW_STATUS_MASK 0x00000001
+#define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB)
+#define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK)
+
+#define RX_FILTER_THRESH_ADDRESS 0x0000836c
+#define RX_FILTER_THRESH_OFFSET 0x0000036c
+#define RX_FILTER_THRESH_RSSI_LOW_MSB 23
+#define RX_FILTER_THRESH_RSSI_LOW_LSB 16
+#define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000
+#define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB)
+#define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK)
+#define RX_FILTER_THRESH_RATE_LOW_MSB 15
+#define RX_FILTER_THRESH_RATE_LOW_LSB 8
+#define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00
+#define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB)
+#define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK)
+#define RX_FILTER_THRESH_RATE_HIGH_MSB 7
+#define RX_FILTER_THRESH_RATE_HIGH_LSB 0
+#define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff
+#define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB)
+#define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK)
+
+#define RX_FILTER_THRESH1_ADDRESS 0x00008370
+#define RX_FILTER_THRESH1_OFFSET 0x00000370
+#define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23
+#define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12
+#define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000
+#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB)
+#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK)
+#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11
+#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0
+#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff
+#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB)
+#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH0_ADDRESS 0x00008374
+#define RX_PRIORITY_THRESH0_OFFSET 0x00000374
+#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31
+#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24
+#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000
+#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB)
+#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK)
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15
+#define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8
+#define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00
+#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB)
+#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK)
+#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7
+#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0
+#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff
+#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB)
+#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH1_ADDRESS 0x00008378
+#define RX_PRIORITY_THRESH1_OFFSET 0x00000378
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB)
+#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK)
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB)
+#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c
+#define RX_PRIORITY_THRESH2_OFFSET 0x0000037c
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK)
+
+#define RX_PRIORITY_THRESH3_ADDRESS 0x00008380
+#define RX_PRIORITY_THRESH3_OFFSET 0x00000380
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB)
+#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384
+#define RX_PRIORITY_OFFSET0_OFFSET 0x00000384
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB)
+#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK)
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB)
+#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388
+#define RX_PRIORITY_OFFSET1_OFFSET 0x00000388
+#define RX_PRIORITY_OFFSET1_RTS_MSB 29
+#define RX_PRIORITY_OFFSET1_RTS_LSB 24
+#define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB)
+#define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK)
+#define RX_PRIORITY_OFFSET1_RETX_MSB 23
+#define RX_PRIORITY_OFFSET1_RETX_LSB 18
+#define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000
+#define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB)
+#define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK)
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB)
+#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK)
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB)
+#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK)
+
+#define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c
+#define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c
+#define RX_PRIORITY_OFFSET2_BEACON_MSB 29
+#define RX_PRIORITY_OFFSET2_BEACON_LSB 24
+#define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB)
+#define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK)
+#define RX_PRIORITY_OFFSET2_MGMT_MSB 23
+#define RX_PRIORITY_OFFSET2_MGMT_LSB 18
+#define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000
+#define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB)
+#define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK)
+#define RX_PRIORITY_OFFSET2_ATIM_MSB 17
+#define RX_PRIORITY_OFFSET2_ATIM_LSB 12
+#define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB)
+#define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK)
+#define RX_PRIORITY_OFFSET2_PRESP_MSB 11
+#define RX_PRIORITY_OFFSET2_PRESP_LSB 6
+#define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0
+#define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB)
+#define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK)
+#define RX_PRIORITY_OFFSET2_XCAST_MSB 5
+#define RX_PRIORITY_OFFSET2_XCAST_LSB 0
+#define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f
+#define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB)
+#define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK)
+
+#define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390
+#define RX_PRIORITY_OFFSET3_OFFSET 0x00000390
+#define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29
+#define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24
+#define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB)
+#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK)
+#define RX_PRIORITY_OFFSET3_AMSDU_MSB 23
+#define RX_PRIORITY_OFFSET3_AMSDU_LSB 18
+#define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000
+#define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB)
+#define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK)
+#define RX_PRIORITY_OFFSET3_AMPDU_MSB 17
+#define RX_PRIORITY_OFFSET3_AMPDU_LSB 12
+#define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB)
+#define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK)
+#define RX_PRIORITY_OFFSET3_EOSP_MSB 11
+#define RX_PRIORITY_OFFSET3_EOSP_LSB 6
+#define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0
+#define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB)
+#define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK)
+#define RX_PRIORITY_OFFSET3_MORE_MSB 5
+#define RX_PRIORITY_OFFSET3_MORE_LSB 0
+#define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f
+#define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB)
+#define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK)
+
+#define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394
+#define RX_PRIORITY_OFFSET4_OFFSET 0x00000394
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB)
+#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK)
+#define RX_PRIORITY_OFFSET4_NULL_MSB 11
+#define RX_PRIORITY_OFFSET4_NULL_LSB 6
+#define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0
+#define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB)
+#define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK)
+#define RX_PRIORITY_OFFSET4_PREQ_MSB 5
+#define RX_PRIORITY_OFFSET4_PREQ_LSB 0
+#define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f
+#define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB)
+#define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK)
+
+#define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398
+#define RX_PRIORITY_OFFSET5_OFFSET 0x00000398
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK)
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB)
+#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK)
+
+#define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c
+#define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c
+#define MAC_PCU_BSSID2_L32_ADDR_MSB 31
+#define MAC_PCU_BSSID2_L32_ADDR_LSB 0
+#define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff
+#define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB)
+#define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK)
+
+#define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0
+#define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0
+#define MAC_PCU_BSSID2_U16_ENABLE_MSB 16
+#define MAC_PCU_BSSID2_U16_ENABLE_LSB 16
+#define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000
+#define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB)
+#define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK)
+#define MAC_PCU_BSSID2_U16_ADDR_MSB 15
+#define MAC_PCU_BSSID2_U16_ADDR_LSB 0
+#define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff
+#define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB)
+#define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK)
+
+#define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4
+#define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB)
+#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8
+#define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB)
+#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac
+#define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB)
+#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0
+#define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB)
+#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK)
+
+#define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400
+#define MAC_PCU_TXBUF_BA_OFFSET 0x00000400
+#define MAC_PCU_TXBUF_BA_DATA_MSB 31
+#define MAC_PCU_TXBUF_BA_DATA_LSB 0
+#define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff
+#define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB)
+#define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK)
+
+#define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800
+#define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800
+#define MAC_PCU_KEY_CACHE_1_DATA_MSB 31
+#define MAC_PCU_KEY_CACHE_1_DATA_LSB 0
+#define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff
+#define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB)
+#define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800
+#define MAC_PCU_BASEBAND_0_OFFSET 0x00001800
+#define MAC_PCU_BASEBAND_0_DATA_MSB 31
+#define MAC_PCU_BASEBAND_0_DATA_LSB 0
+#define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff
+#define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB)
+#define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000
+#define MAC_PCU_BASEBAND_1_OFFSET 0x00002000
+#define MAC_PCU_BASEBAND_1_DATA_MSB 31
+#define MAC_PCU_BASEBAND_1_DATA_LSB 0
+#define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff
+#define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB)
+#define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000
+#define MAC_PCU_BASEBAND_2_OFFSET 0x00004000
+#define MAC_PCU_BASEBAND_2_DATA_MSB 31
+#define MAC_PCU_BASEBAND_2_DATA_LSB 0
+#define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff
+#define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB)
+#define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK)
+
+#define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000
+#define MAC_PCU_BASEBAND_3_OFFSET 0x00005000
+#define MAC_PCU_BASEBAND_3_DATA_MSB 31
+#define MAC_PCU_BASEBAND_3_DATA_LSB 0
+#define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff
+#define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB)
+#define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK)
+
+#define MAC_PCU_BUF_ADDRESS 0x0000e000
+#define MAC_PCU_BUF_OFFSET 0x00006000
+#define MAC_PCU_BUF_DATA_MSB 31
+#define MAC_PCU_BUF_DATA_LSB 0
+#define MAC_PCU_BUF_DATA_MASK 0xffffffff
+#define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB)
+#define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mac_pcu_reg_s {
+ volatile unsigned int mac_pcu_sta_addr_l32;
+ volatile unsigned int mac_pcu_sta_addr_u16;
+ volatile unsigned int mac_pcu_bssid_l32;
+ volatile unsigned int mac_pcu_bssid_u16;
+ volatile unsigned int mac_pcu_bcn_rssi_ave;
+ volatile unsigned int mac_pcu_ack_cts_timeout;
+ volatile unsigned int mac_pcu_bcn_rssi_ctl;
+ volatile unsigned int mac_pcu_usec_latency;
+ volatile unsigned int pcu_max_cfp_dur;
+ volatile unsigned int mac_pcu_rx_filter;
+ volatile unsigned int mac_pcu_mcast_filter_l32;
+ volatile unsigned int mac_pcu_mcast_filter_u32;
+ volatile unsigned int mac_pcu_diag_sw;
+ volatile unsigned int mac_pcu_tst_addac;
+ volatile unsigned int mac_pcu_def_antenna;
+ volatile unsigned int mac_pcu_aes_mute_mask_0;
+ volatile unsigned int mac_pcu_aes_mute_mask_1;
+ volatile unsigned int mac_pcu_gated_clks;
+ volatile unsigned int mac_pcu_obs_bus_2;
+ volatile unsigned int mac_pcu_obs_bus_1;
+ volatile unsigned int mac_pcu_dym_mimo_pwr_save;
+ volatile unsigned int mac_pcu_last_beacon_tsf;
+ volatile unsigned int mac_pcu_nav;
+ volatile unsigned int mac_pcu_rts_success_cnt;
+ volatile unsigned int mac_pcu_rts_fail_cnt;
+ volatile unsigned int mac_pcu_ack_fail_cnt;
+ volatile unsigned int mac_pcu_fcs_fail_cnt;
+ volatile unsigned int mac_pcu_beacon_cnt;
+ volatile unsigned int mac_pcu_xrmode;
+ volatile unsigned int mac_pcu_xrdel;
+ volatile unsigned int mac_pcu_xrto;
+ volatile unsigned int mac_pcu_xrcrp;
+ volatile unsigned int mac_pcu_xrstmp;
+ volatile unsigned int mac_pcu_addr1_mask_l32;
+ volatile unsigned int mac_pcu_addr1_mask_u16;
+ volatile unsigned int mac_pcu_tpc;
+ volatile unsigned int mac_pcu_tx_frame_cnt;
+ volatile unsigned int mac_pcu_rx_frame_cnt;
+ volatile unsigned int mac_pcu_rx_clear_cnt;
+ volatile unsigned int mac_pcu_cycle_cnt;
+ volatile unsigned int mac_pcu_quiet_time_1;
+ volatile unsigned int mac_pcu_quiet_time_2;
+ volatile unsigned int mac_pcu_qos_no_ack;
+ volatile unsigned int mac_pcu_phy_error_mask;
+ volatile unsigned int mac_pcu_xrlat;
+ volatile unsigned int mac_pcu_rxbuf;
+ volatile unsigned int mac_pcu_mic_qos_control;
+ volatile unsigned int mac_pcu_mic_qos_select;
+ volatile unsigned int mac_pcu_misc_mode;
+ volatile unsigned int mac_pcu_filter_ofdm_cnt;
+ volatile unsigned int mac_pcu_filter_cck_cnt;
+ volatile unsigned int mac_pcu_phy_err_cnt_1;
+ volatile unsigned int mac_pcu_phy_err_cnt_1_mask;
+ volatile unsigned int mac_pcu_phy_err_cnt_2;
+ volatile unsigned int mac_pcu_phy_err_cnt_2_mask;
+ volatile unsigned int mac_pcu_tsf_threshold;
+ volatile unsigned int mac_pcu_phy_error_eifs_mask;
+ volatile unsigned int mac_pcu_phy_err_cnt_3;
+ volatile unsigned int mac_pcu_phy_err_cnt_3_mask;
+ volatile unsigned int mac_pcu_bluetooth_mode;
+ volatile unsigned int mac_pcu_bluetooth_weights;
+ volatile unsigned int mac_pcu_bluetooth_mode2;
+ volatile unsigned int mac_pcu_txsifs;
+ volatile unsigned int mac_pcu_txop_x;
+ volatile unsigned int mac_pcu_txop_0_3;
+ volatile unsigned int mac_pcu_txop_4_7;
+ volatile unsigned int mac_pcu_txop_8_11;
+ volatile unsigned int mac_pcu_txop_12_15;
+ volatile unsigned int mac_pcu_logic_analyzer;
+ volatile unsigned int mac_pcu_logic_analyzer_32l;
+ volatile unsigned int mac_pcu_logic_analyzer_16u;
+ volatile unsigned int mac_pcu_phy_err_cnt_mask_cont;
+ volatile unsigned int mac_pcu_azimuth_mode;
+ volatile unsigned int mac_pcu_20_40_mode;
+ volatile unsigned int mac_pcu_rx_clear_diff_cnt;
+ volatile unsigned int mac_pcu_self_gen_antenna_mask;
+ volatile unsigned int mac_pcu_ba_bar_control;
+ volatile unsigned int mac_pcu_legacy_plcp_spoof;
+ volatile unsigned int mac_pcu_phy_error_mask_cont;
+ volatile unsigned int mac_pcu_tx_timer;
+ volatile unsigned int mac_pcu_txbuf_ctrl;
+ volatile unsigned int mac_pcu_misc_mode2;
+ volatile unsigned int mac_pcu_alt_aes_mute_mask;
+ volatile unsigned int mac_pcu_azimuth_time_stamp;
+ volatile unsigned int mac_pcu_max_cfp_dur;
+ volatile unsigned int mac_pcu_hcf_timeout;
+ volatile unsigned int mac_pcu_bluetooth_weights2;
+ volatile unsigned int mac_pcu_bluetooth_tsf_bt_active;
+ volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority;
+ volatile unsigned int mac_pcu_bluetooth_mode3;
+ volatile unsigned int mac_pcu_bluetooth_mode4;
+ unsigned char pad0[148]; /* pad to 0x200 */
+ volatile unsigned int mac_pcu_bt_bt[64];
+ volatile unsigned int mac_pcu_bt_bt_async;
+ volatile unsigned int mac_pcu_bt_wl_1;
+ volatile unsigned int mac_pcu_bt_wl_2;
+ volatile unsigned int mac_pcu_bt_wl_3;
+ volatile unsigned int mac_pcu_bt_wl_4;
+ volatile unsigned int mac_pcu_coex_epta;
+ volatile unsigned int mac_pcu_coex_lnamaxgain1;
+ volatile unsigned int mac_pcu_coex_lnamaxgain2;
+ volatile unsigned int mac_pcu_coex_lnamaxgain3;
+ volatile unsigned int mac_pcu_coex_lnamaxgain4;
+ volatile unsigned int mac_pcu_basic_rate_set0;
+ volatile unsigned int mac_pcu_basic_rate_set1;
+ volatile unsigned int mac_pcu_basic_rate_set2;
+ volatile unsigned int mac_pcu_basic_rate_set3;
+ volatile unsigned int mac_pcu_rx_int_status0;
+ volatile unsigned int mac_pcu_rx_int_status1;
+ volatile unsigned int mac_pcu_rx_int_status2;
+ volatile unsigned int mac_pcu_rx_int_status3;
+ volatile unsigned int ht_half_gi_rate1;
+ volatile unsigned int ht_half_gi_rate2;
+ volatile unsigned int ht_full_gi_rate1;
+ volatile unsigned int ht_full_gi_rate2;
+ volatile unsigned int legacy_rate1;
+ volatile unsigned int legacy_rate2;
+ volatile unsigned int legacy_rate3;
+ volatile unsigned int rx_int_filter;
+ volatile unsigned int rx_int_overflow;
+ volatile unsigned int rx_filter_thresh;
+ volatile unsigned int rx_filter_thresh1;
+ volatile unsigned int rx_priority_thresh0;
+ volatile unsigned int rx_priority_thresh1;
+ volatile unsigned int rx_priority_thresh2;
+ volatile unsigned int rx_priority_thresh3;
+ volatile unsigned int rx_priority_offset0;
+ volatile unsigned int rx_priority_offset1;
+ volatile unsigned int rx_priority_offset2;
+ volatile unsigned int rx_priority_offset3;
+ volatile unsigned int rx_priority_offset4;
+ volatile unsigned int rx_priority_offset5;
+ volatile unsigned int mac_pcu_bssid2_l32;
+ volatile unsigned int mac_pcu_bssid2_u16;
+ volatile unsigned int mac_pcu_tsf1_status_l32;
+ volatile unsigned int mac_pcu_tsf1_status_u32;
+ volatile unsigned int mac_pcu_tsf2_status_l32;
+ volatile unsigned int mac_pcu_tsf2_status_u32;
+ unsigned char pad1[76]; /* pad to 0x400 */
+ volatile unsigned int mac_pcu_txbuf_ba[64];
+ unsigned char pad2[768]; /* pad to 0x800 */
+ volatile unsigned int mac_pcu_key_cache_1[256];
+ unsigned char pad3[3072]; /* pad to 0x1800 */
+ volatile unsigned int mac_pcu_baseband_0[512];
+ volatile unsigned int mac_pcu_baseband_1[2048];
+ volatile unsigned int mac_pcu_baseband_2[1024];
+ volatile unsigned int mac_pcu_baseband_3[1024];
+ volatile unsigned int mac_pcu_buf[512];
+} mac_pcu_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MAC_PCU_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h
new file mode 100644
index 000000000000..e84e2e011ca2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h
@@ -0,0 +1,33 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "mbox_wlan_host_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h
new file mode 100644
index 000000000000..2ac8528987d4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h
@@ -0,0 +1,556 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "mbox_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
+#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET
+#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB
+#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB
+#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK
+#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x)
+#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x)
+#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS
+#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET
+#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB
+#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB
+#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK
+#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)
+#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)
+#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB
+#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB
+#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK
+#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x)
+#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x)
+#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS
+#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET
+#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB
+#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB
+#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK
+#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)
+#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)
+#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB
+#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB
+#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK
+#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)
+#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)
+#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB
+#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB
+#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK
+#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)
+#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)
+#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB
+#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB
+#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK
+#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)
+#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS
+#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET
+#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB
+#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB
+#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK
+#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)
+#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)
+#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB
+#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB
+#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK
+#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS
+#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET
+#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB
+#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB
+#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK
+#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)
+#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)
+#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB
+#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB
+#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK
+#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS
+#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET
+#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB
+#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB
+#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK
+#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)
+#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)
+#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB
+#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB
+#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK
+#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS
+#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET
+#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB
+#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB
+#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK
+#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)
+#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)
+#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB
+#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB
+#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK
+#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS
+#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET
+#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB
+#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB
+#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK
+#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)
+#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)
+#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB
+#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB
+#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK
+#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS
+#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET
+#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB
+#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB
+#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK
+#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)
+#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)
+#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB
+#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB
+#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK
+#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS
+#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET
+#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB
+#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB
+#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK
+#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)
+#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)
+#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB
+#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB
+#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK
+#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)
+#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)
+#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB
+#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB
+#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK
+#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)
+#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS
+#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET
+#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB
+#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB
+#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK
+#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)
+#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)
+#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB
+#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB
+#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK
+#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)
+#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)
+#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB
+#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB
+#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK
+#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)
+#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)
+#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS
+#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB
+#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB
+#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK
+#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)
+#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB
+#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB
+#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK
+#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
+#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
+#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
+#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB
+#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB
+#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK
+#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)
+#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)
+#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB
+#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB
+#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK
+#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x)
+#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x)
+#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS
+#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
+#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB
+#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB
+#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK
+#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
+#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
+#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
+#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB
+#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB
+#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK
+#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
+#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
+#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB
+#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB
+#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK
+#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x)
+#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x)
+#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS
+#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET
+#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB
+#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB
+#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK
+#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x)
+#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x)
+#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS
+#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET
+#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB
+#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB
+#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK
+#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x)
+#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x)
+#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS
+#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET
+#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB
+#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB
+#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK
+#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x)
+#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x)
+#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS
+#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET
+#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB
+#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB
+#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK
+#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x)
+#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x)
+#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS
+#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET
+#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB
+#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB
+#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK
+#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)
+#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)
+#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS
+#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET
+#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB
+#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB
+#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK
+#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)
+#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)
+#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS
+#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET
+#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB
+#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB
+#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK
+#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x)
+#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x)
+#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS
+#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET
+#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB
+#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB
+#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK
+#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x)
+#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x)
+#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS
+#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET
+#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB
+#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB
+#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK
+#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x)
+#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x)
+#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS
+#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET
+#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB
+#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB
+#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK
+#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x)
+#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x)
+#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS
+#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET
+#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB
+#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB
+#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK
+#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x)
+#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x)
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS
+#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET
+#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB
+#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB
+#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK
+#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB
+#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB
+#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK
+#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)
+#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB
+#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB
+#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK
+#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)
+#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
+#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS
+#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET
+#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB
+#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB
+#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK
+#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB
+#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB
+#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK
+#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)
+#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB
+#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB
+#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK
+#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)
+#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)
+#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS
+#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET
+#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB
+#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB
+#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK
+#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x)
+#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x)
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
+#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
+#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
+#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB
+#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB
+#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK
+#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x)
+#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x)
+#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS
+#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
+#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
+#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
+#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
+#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
+#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
+#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS
+#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET
+#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB
+#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB
+#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK
+#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
+#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
new file mode 100644
index 000000000000..dbad49ea0a01
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
@@ -0,0 +1,518 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_WLAN_HOST_REG_REG_H_
+#define _MBOX_WLAN_HOST_REG_REG_H_
+
+#define HOST_INT_STATUS_ADDRESS 0x00000400
+#define HOST_INT_STATUS_OFFSET 0x00000400
+#define HOST_INT_STATUS_ERROR_MSB 7
+#define HOST_INT_STATUS_ERROR_LSB 7
+#define HOST_INT_STATUS_ERROR_MASK 0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_CPU_MSB 6
+#define HOST_INT_STATUS_CPU_LSB 6
+#define HOST_INT_STATUS_CPU_MASK 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_INT_MSB 5
+#define HOST_INT_STATUS_INT_LSB 5
+#define HOST_INT_STATUS_INT_MASK 0x00000020
+#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
+#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
+#define HOST_INT_STATUS_COUNTER_MSB 4
+#define HOST_INT_STATUS_COUNTER_LSB 4
+#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_MSB 3
+#define HOST_INT_STATUS_MBOX_DATA_LSB 0
+#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
+#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
+#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ADDRESS 0x00000401
+#define CPU_INT_STATUS_OFFSET 0x00000401
+#define CPU_INT_STATUS_BIT_MSB 7
+#define CPU_INT_STATUS_BIT_LSB 0
+#define CPU_INT_STATUS_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
+#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
+
+#define ERROR_INT_STATUS_ADDRESS 0x00000402
+#define ERROR_INT_STATUS_OFFSET 0x00000402
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_SPI_MSB 3
+#define ERROR_INT_STATUS_SPI_LSB 3
+#define ERROR_INT_STATUS_SPI_MASK 0x00000008
+#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
+#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
+#define ERROR_INT_STATUS_WAKEUP_MSB 2
+#define ERROR_INT_STATUS_WAKEUP_LSB 2
+#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ADDRESS 0x00000403
+#define COUNTER_INT_STATUS_OFFSET 0x00000403
+#define COUNTER_INT_STATUS_COUNTER_MSB 7
+#define COUNTER_INT_STATUS_COUNTER_LSB 0
+#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
+#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
+#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
+
+#define MBOX_FRAME_ADDRESS 0x00000404
+#define MBOX_FRAME_OFFSET 0x00000404
+#define MBOX_FRAME_RX_EOM_MSB 7
+#define MBOX_FRAME_RX_EOM_LSB 4
+#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
+#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
+#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
+#define MBOX_FRAME_RX_SOM_MSB 3
+#define MBOX_FRAME_RX_SOM_LSB 0
+#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
+#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
+#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
+
+#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
+#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
+#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
+#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
+#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
+#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
+#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
+
+#define HOST_INT_STATUS2_ADDRESS 0x00000406
+#define HOST_INT_STATUS2_OFFSET 0x00000406
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
+#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
+#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
+#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0
+#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0
+#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001
+#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
+#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
+
+#define GMBOX_RX_AVAIL_ADDRESS 0x00000407
+#define GMBOX_RX_AVAIL_OFFSET 0x00000407
+#define GMBOX_RX_AVAIL_BYTE_MSB 6
+#define GMBOX_RX_AVAIL_BYTE_LSB 0
+#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f
+#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
+#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
+
+#define RX_LOOKAHEAD0_ADDRESS 0x00000408
+#define RX_LOOKAHEAD0_OFFSET 0x00000408
+#define RX_LOOKAHEAD0_DATA_MSB 7
+#define RX_LOOKAHEAD0_DATA_LSB 0
+#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
+#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
+
+#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
+#define RX_LOOKAHEAD1_OFFSET 0x0000040c
+#define RX_LOOKAHEAD1_DATA_MSB 7
+#define RX_LOOKAHEAD1_DATA_LSB 0
+#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
+#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
+
+#define RX_LOOKAHEAD2_ADDRESS 0x00000410
+#define RX_LOOKAHEAD2_OFFSET 0x00000410
+#define RX_LOOKAHEAD2_DATA_MSB 7
+#define RX_LOOKAHEAD2_DATA_LSB 0
+#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
+#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
+
+#define RX_LOOKAHEAD3_ADDRESS 0x00000414
+#define RX_LOOKAHEAD3_OFFSET 0x00000414
+#define RX_LOOKAHEAD3_DATA_MSB 7
+#define RX_LOOKAHEAD3_DATA_LSB 0
+#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
+#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
+#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
+
+#define INT_STATUS_ENABLE_ADDRESS 0x00000418
+#define INT_STATUS_ENABLE_OFFSET 0x00000418
+#define INT_STATUS_ENABLE_ERROR_MSB 7
+#define INT_STATUS_ENABLE_ERROR_LSB 7
+#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_MSB 6
+#define INT_STATUS_ENABLE_CPU_LSB 6
+#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_INT_MSB 5
+#define INT_STATUS_ENABLE_INT_LSB 5
+#define INT_STATUS_ENABLE_INT_MASK 0x00000020
+#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
+#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
+#define INT_STATUS_ENABLE_COUNTER_MSB 4
+#define INT_STATUS_ENABLE_COUNTER_LSB 4
+#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
+#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
+#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
+#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
+#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
+#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
+#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
+#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNT_ADDRESS 0x00000420
+#define COUNT_OFFSET 0x00000420
+#define COUNT_VALUE_MSB 7
+#define COUNT_VALUE_LSB 0
+#define COUNT_VALUE_MASK 0x000000ff
+#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
+#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
+
+#define COUNT_DEC_ADDRESS 0x00000440
+#define COUNT_DEC_OFFSET 0x00000440
+#define COUNT_DEC_VALUE_MSB 7
+#define COUNT_DEC_VALUE_LSB 0
+#define COUNT_DEC_VALUE_MASK 0x000000ff
+#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
+#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
+
+#define SCRATCH_ADDRESS 0x00000460
+#define SCRATCH_OFFSET 0x00000460
+#define SCRATCH_VALUE_MSB 7
+#define SCRATCH_VALUE_LSB 0
+#define SCRATCH_VALUE_MASK 0x000000ff
+#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
+#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ADDRESS 0x00000468
+#define FIFO_TIMEOUT_OFFSET 0x00000468
+#define FIFO_TIMEOUT_VALUE_MSB 7
+#define FIFO_TIMEOUT_VALUE_LSB 0
+#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
+#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
+#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
+
+#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
+#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
+#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
+#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
+#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
+#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
+
+#define DISABLE_SLEEP_ADDRESS 0x0000046a
+#define DISABLE_SLEEP_OFFSET 0x0000046a
+#define DISABLE_SLEEP_FOR_INT_MSB 1
+#define DISABLE_SLEEP_FOR_INT_LSB 1
+#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
+#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
+#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
+#define DISABLE_SLEEP_ON_MSB 0
+#define DISABLE_SLEEP_ON_LSB 0
+#define DISABLE_SLEEP_ON_MASK 0x00000001
+#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
+#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
+
+#define LOCAL_BUS_ADDRESS 0x00000470
+#define LOCAL_BUS_OFFSET 0x00000470
+#define LOCAL_BUS_STATE_MSB 1
+#define LOCAL_BUS_STATE_LSB 0
+#define LOCAL_BUS_STATE_MASK 0x00000003
+#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
+#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
+
+#define INT_WLAN_ADDRESS 0x00000472
+#define INT_WLAN_OFFSET 0x00000472
+#define INT_WLAN_VECTOR_MSB 7
+#define INT_WLAN_VECTOR_LSB 0
+#define INT_WLAN_VECTOR_MASK 0x000000ff
+#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
+#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
+
+#define WINDOW_DATA_ADDRESS 0x00000474
+#define WINDOW_DATA_OFFSET 0x00000474
+#define WINDOW_DATA_DATA_MSB 7
+#define WINDOW_DATA_DATA_LSB 0
+#define WINDOW_DATA_DATA_MASK 0x000000ff
+#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
+#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
+
+#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
+#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
+#define WINDOW_WRITE_ADDR_ADDR_MSB 7
+#define WINDOW_WRITE_ADDR_ADDR_LSB 0
+#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
+#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
+#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
+
+#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
+#define WINDOW_READ_ADDR_OFFSET 0x0000047c
+#define WINDOW_READ_ADDR_ADDR_MSB 7
+#define WINDOW_READ_ADDR_ADDR_LSB 0
+#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
+#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
+#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
+
+#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480
+#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
+#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
+#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
+#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
+#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
+
+#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481
+#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2
+#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2
+#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004
+#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1
+#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1
+#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002
+#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
+#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
+#define HOST_CTRL_SPI_STATUS_READY_MSB 0
+#define HOST_CTRL_SPI_STATUS_READY_LSB 0
+#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001
+#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
+#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
+
+#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
+#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
+#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
+#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
+#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
+#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
+#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
+
+#define CPU_DBG_SEL_ADDRESS 0x00000483
+#define CPU_DBG_SEL_OFFSET 0x00000483
+#define CPU_DBG_SEL_BIT_MSB 5
+#define CPU_DBG_SEL_BIT_LSB 0
+#define CPU_DBG_SEL_BIT_MASK 0x0000003f
+#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
+#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
+
+#define CPU_DBG_ADDRESS 0x00000484
+#define CPU_DBG_OFFSET 0x00000484
+#define CPU_DBG_DATA_MSB 7
+#define CPU_DBG_DATA_LSB 0
+#define CPU_DBG_DATA_MASK 0x000000ff
+#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
+#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
+
+#define INT_STATUS2_ENABLE_ADDRESS 0x00000488
+#define INT_STATUS2_ENABLE_OFFSET 0x00000488
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
+#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0
+#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0
+#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001
+#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
+#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
+
+#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490
+#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490
+#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7
+#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0
+#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff
+#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
+#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
+
+#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498
+#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
+#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
+
+#define CIS_WINDOW_ADDRESS 0x00000600
+#define CIS_WINDOW_OFFSET 0x00000600
+#define CIS_WINDOW_DATA_MSB 7
+#define CIS_WINDOW_DATA_LSB 0
+#define CIS_WINDOW_DATA_MASK 0x000000ff
+#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
+#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_wlan_host_reg_reg_s {
+ unsigned char pad0[1024]; /* pad to 0x400 */
+ volatile unsigned char host_int_status;
+ volatile unsigned char cpu_int_status;
+ volatile unsigned char error_int_status;
+ volatile unsigned char counter_int_status;
+ volatile unsigned char mbox_frame;
+ volatile unsigned char rx_lookahead_valid;
+ volatile unsigned char host_int_status2;
+ volatile unsigned char gmbox_rx_avail;
+ volatile unsigned char rx_lookahead0[4];
+ volatile unsigned char rx_lookahead1[4];
+ volatile unsigned char rx_lookahead2[4];
+ volatile unsigned char rx_lookahead3[4];
+ volatile unsigned char int_status_enable;
+ volatile unsigned char cpu_int_status_enable;
+ volatile unsigned char error_status_enable;
+ volatile unsigned char counter_int_status_enable;
+ unsigned char pad1[4]; /* pad to 0x420 */
+ volatile unsigned char count[8];
+ unsigned char pad2[24]; /* pad to 0x440 */
+ volatile unsigned char count_dec[32];
+ volatile unsigned char scratch[8];
+ volatile unsigned char fifo_timeout;
+ volatile unsigned char fifo_timeout_enable;
+ volatile unsigned char disable_sleep;
+ unsigned char pad3[5]; /* pad to 0x470 */
+ volatile unsigned char local_bus;
+ unsigned char pad4[1]; /* pad to 0x472 */
+ volatile unsigned char int_wlan;
+ unsigned char pad5[1]; /* pad to 0x474 */
+ volatile unsigned char window_data[4];
+ volatile unsigned char window_write_addr[4];
+ volatile unsigned char window_read_addr[4];
+ volatile unsigned char host_ctrl_spi_config;
+ volatile unsigned char host_ctrl_spi_status;
+ volatile unsigned char non_assoc_sleep_en;
+ volatile unsigned char cpu_dbg_sel;
+ volatile unsigned char cpu_dbg[4];
+ volatile unsigned char int_status2_enable;
+ unsigned char pad6[7]; /* pad to 0x490 */
+ volatile unsigned char gmbox_rx_lookahead[8];
+ volatile unsigned char gmbox_rx_lookahead_mux;
+ unsigned char pad7[359]; /* pad to 0x600 */
+ volatile unsigned char cis_window[512];
+} mbox_wlan_host_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_WLAN_HOST_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h
new file mode 100644
index 000000000000..55d20216ec11
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h
@@ -0,0 +1,634 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _MBOX_WLAN_REG_REG_H_
+#define _MBOX_WLAN_REG_REG_H_
+
+#define WLAN_MBOX_FIFO_ADDRESS 0x00000000
+#define WLAN_MBOX_FIFO_OFFSET 0x00000000
+#define WLAN_MBOX_FIFO_DATA_MSB 19
+#define WLAN_MBOX_FIFO_DATA_LSB 0
+#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff
+#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB)
+#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK)
+
+#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010
+#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB)
+#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK)
+#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15
+#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12
+#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
+#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB)
+#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK)
+
+#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014
+#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB)
+#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK)
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB)
+#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
+#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
+#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
+#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
+#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
+#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
+#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
+#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK)
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
+#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK)
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058
+#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK)
+#define WLAN_MBOX_INT_STATUS_HOST_MSB 7
+#define WLAN_MBOX_INT_STATUS_HOST_LSB 0
+#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff
+#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB)
+#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK)
+
+#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c
+#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7
+#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0
+#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff
+#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB)
+#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK)
+
+#define WLAN_INT_HOST_ADDRESS 0x00000060
+#define WLAN_INT_HOST_OFFSET 0x00000060
+#define WLAN_INT_HOST_VECTOR_MSB 7
+#define WLAN_INT_HOST_VECTOR_LSB 0
+#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff
+#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB)
+#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK)
+
+#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080
+#define WLAN_LOCAL_COUNT_OFFSET 0x00000080
+#define WLAN_LOCAL_COUNT_VALUE_MSB 7
+#define WLAN_LOCAL_COUNT_VALUE_LSB 0
+#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff
+#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB)
+#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK)
+
+#define WLAN_COUNT_INC_ADDRESS 0x000000a0
+#define WLAN_COUNT_INC_OFFSET 0x000000a0
+#define WLAN_COUNT_INC_VALUE_MSB 7
+#define WLAN_COUNT_INC_VALUE_LSB 0
+#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff
+#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB)
+#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK)
+
+#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0
+#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0
+#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7
+#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0
+#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff
+#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB)
+#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK)
+
+#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0
+#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB)
+#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK)
+
+#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4
+#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB)
+#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK)
+
+#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8
+#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8
+#define WLAN_MBOX_DEBUG_SEL_MSB 2
+#define WLAN_MBOX_DEBUG_SEL_LSB 0
+#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007
+#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB)
+#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK)
+
+#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec
+#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec
+#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0
+#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0
+#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001
+#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB)
+#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK)
+
+#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0
+#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0
+#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0
+#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0
+#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001
+#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB)
+#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK)
+
+#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100
+#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100
+#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0
+#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0
+#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001
+#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB)
+#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK)
+
+#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110
+#define WLAN_SDIO_DEBUG_OFFSET 0x00000110
+#define WLAN_SDIO_DEBUG_SEL_MSB 3
+#define WLAN_SDIO_DEBUG_SEL_LSB 0
+#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f
+#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB)
+#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK)
+
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118
+#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120
+#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124
+#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK)
+
+#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128
+#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+
+#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000
+#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000
+#define WLAN_HOST_IF_WINDOW_DATA_MSB 7
+#define WLAN_HOST_IF_WINDOW_DATA_LSB 0
+#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff
+#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
+#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct mbox_wlan_reg_reg_s {
+ volatile unsigned int wlan_mbox_fifo[4];
+ volatile unsigned int wlan_mbox_fifo_status;
+ volatile unsigned int wlan_mbox_dma_policy;
+ volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
+ volatile unsigned int wlan_mbox0_dma_rx_control;
+ volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
+ volatile unsigned int wlan_mbox0_dma_tx_control;
+ volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
+ volatile unsigned int wlan_mbox1_dma_rx_control;
+ volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
+ volatile unsigned int wlan_mbox1_dma_tx_control;
+ volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
+ volatile unsigned int wlan_mbox2_dma_rx_control;
+ volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
+ volatile unsigned int wlan_mbox2_dma_tx_control;
+ volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
+ volatile unsigned int wlan_mbox3_dma_rx_control;
+ volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
+ volatile unsigned int wlan_mbox3_dma_tx_control;
+ volatile unsigned int wlan_mbox_int_status;
+ volatile unsigned int wlan_mbox_int_enable;
+ volatile unsigned int wlan_int_host;
+ unsigned char pad0[28]; /* pad to 0x80 */
+ volatile unsigned int wlan_local_count[8];
+ volatile unsigned int wlan_count_inc[8];
+ volatile unsigned int wlan_local_scratch[8];
+ volatile unsigned int wlan_use_local_bus;
+ volatile unsigned int wlan_sdio_config;
+ volatile unsigned int wlan_mbox_debug;
+ volatile unsigned int wlan_mbox_fifo_reset;
+ volatile unsigned int wlan_mbox_txfifo_pop[4];
+ volatile unsigned int wlan_mbox_rxfifo_pop[4];
+ volatile unsigned int wlan_sdio_debug;
+ volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
+ volatile unsigned int wlan_gmbox0_dma_rx_control;
+ volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
+ volatile unsigned int wlan_gmbox0_dma_tx_control;
+ volatile unsigned int wlan_gmbox_int_status;
+ volatile unsigned int wlan_gmbox_int_enable;
+ unsigned char pad1[7892]; /* pad to 0x2000 */
+ volatile unsigned int wlan_host_if_window[2048];
+} mbox_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _MBOX_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h
new file mode 100644
index 000000000000..cbf4acfa7925
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h
@@ -0,0 +1,560 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RDMA_REG_REG_H_
+#define _RDMA_REG_REG_H_
+
+#define DMA_CONFIG_ADDRESS 0x00000000
+#define DMA_CONFIG_OFFSET 0x00000000
+#define DMA_CONFIG_WLBB_PWD_EN_MSB 4
+#define DMA_CONFIG_WLBB_PWD_EN_LSB 4
+#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010
+#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
+#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
+#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3
+#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3
+#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008
+#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
+#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
+#define DMA_CONFIG_ENABLE_RETENTION_MSB 2
+#define DMA_CONFIG_ENABLE_RETENTION_LSB 2
+#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004
+#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
+#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
+#define DMA_CONFIG_RTC_PRIORITY_MSB 1
+#define DMA_CONFIG_RTC_PRIORITY_LSB 1
+#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002
+#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
+#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
+#define DMA_CONFIG_DMA_TYPE_MSB 0
+#define DMA_CONFIG_DMA_TYPE_LSB 0
+#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001
+#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
+#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
+
+#define DMA_CONTROL_ADDRESS 0x00000004
+#define DMA_CONTROL_OFFSET 0x00000004
+#define DMA_CONTROL_START_MSB 1
+#define DMA_CONTROL_START_LSB 1
+#define DMA_CONTROL_START_MASK 0x00000002
+#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
+#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
+#define DMA_CONTROL_STOP_MSB 0
+#define DMA_CONTROL_STOP_LSB 0
+#define DMA_CONTROL_STOP_MASK 0x00000001
+#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
+#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
+
+#define DMA_SRC_ADDRESS 0x00000008
+#define DMA_SRC_OFFSET 0x00000008
+#define DMA_SRC_ADDR_MSB 31
+#define DMA_SRC_ADDR_LSB 2
+#define DMA_SRC_ADDR_MASK 0xfffffffc
+#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
+#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
+
+#define DMA_DEST_ADDRESS 0x0000000c
+#define DMA_DEST_OFFSET 0x0000000c
+#define DMA_DEST_ADDR_MSB 31
+#define DMA_DEST_ADDR_LSB 2
+#define DMA_DEST_ADDR_MASK 0xfffffffc
+#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
+#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
+
+#define DMA_LENGTH_ADDRESS 0x00000010
+#define DMA_LENGTH_OFFSET 0x00000010
+#define DMA_LENGTH_WORDS_MSB 11
+#define DMA_LENGTH_WORDS_LSB 0
+#define DMA_LENGTH_WORDS_MASK 0x00000fff
+#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
+#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
+
+#define VMC_BASE_ADDRESS 0x00000014
+#define VMC_BASE_OFFSET 0x00000014
+#define VMC_BASE_ADDR_MSB 31
+#define VMC_BASE_ADDR_LSB 2
+#define VMC_BASE_ADDR_MASK 0xfffffffc
+#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
+#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
+
+#define INDIRECT_REG_ADDRESS 0x00000018
+#define INDIRECT_REG_OFFSET 0x00000018
+#define INDIRECT_REG_ID_MSB 31
+#define INDIRECT_REG_ID_LSB 2
+#define INDIRECT_REG_ID_MASK 0xfffffffc
+#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
+#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
+
+#define INDIRECT_RETURN_ADDRESS 0x0000001c
+#define INDIRECT_RETURN_OFFSET 0x0000001c
+#define INDIRECT_RETURN_ADDR_MSB 31
+#define INDIRECT_RETURN_ADDR_LSB 2
+#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc
+#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
+#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
+
+#define RDMA_REGION_0__ADDRESS 0x00000020
+#define RDMA_REGION_0__OFFSET 0x00000020
+#define RDMA_REGION_0__ADDR_MSB 31
+#define RDMA_REGION_0__ADDR_LSB 13
+#define RDMA_REGION_0__ADDR_MASK 0xffffe000
+#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
+#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
+#define RDMA_REGION_0__LENGTH_MSB 12
+#define RDMA_REGION_0__LENGTH_LSB 2
+#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
+#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
+#define RDMA_REGION_0__INDI_MSB 1
+#define RDMA_REGION_0__INDI_LSB 1
+#define RDMA_REGION_0__INDI_MASK 0x00000002
+#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
+#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
+#define RDMA_REGION_0__NEXT_MSB 0
+#define RDMA_REGION_0__NEXT_LSB 0
+#define RDMA_REGION_0__NEXT_MASK 0x00000001
+#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
+#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
+
+#define RDMA_REGION_1__ADDRESS 0x00000024
+#define RDMA_REGION_1__OFFSET 0x00000024
+#define RDMA_REGION_1__ADDR_MSB 31
+#define RDMA_REGION_1__ADDR_LSB 13
+#define RDMA_REGION_1__ADDR_MASK 0xffffe000
+#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
+#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
+#define RDMA_REGION_1__LENGTH_MSB 12
+#define RDMA_REGION_1__LENGTH_LSB 2
+#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
+#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
+#define RDMA_REGION_1__INDI_MSB 1
+#define RDMA_REGION_1__INDI_LSB 1
+#define RDMA_REGION_1__INDI_MASK 0x00000002
+#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
+#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
+#define RDMA_REGION_1__NEXT_MSB 0
+#define RDMA_REGION_1__NEXT_LSB 0
+#define RDMA_REGION_1__NEXT_MASK 0x00000001
+#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
+#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
+
+#define RDMA_REGION_2__ADDRESS 0x00000028
+#define RDMA_REGION_2__OFFSET 0x00000028
+#define RDMA_REGION_2__ADDR_MSB 31
+#define RDMA_REGION_2__ADDR_LSB 13
+#define RDMA_REGION_2__ADDR_MASK 0xffffe000
+#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
+#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
+#define RDMA_REGION_2__LENGTH_MSB 12
+#define RDMA_REGION_2__LENGTH_LSB 2
+#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
+#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
+#define RDMA_REGION_2__INDI_MSB 1
+#define RDMA_REGION_2__INDI_LSB 1
+#define RDMA_REGION_2__INDI_MASK 0x00000002
+#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
+#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
+#define RDMA_REGION_2__NEXT_MSB 0
+#define RDMA_REGION_2__NEXT_LSB 0
+#define RDMA_REGION_2__NEXT_MASK 0x00000001
+#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
+#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
+
+#define RDMA_REGION_3__ADDRESS 0x0000002c
+#define RDMA_REGION_3__OFFSET 0x0000002c
+#define RDMA_REGION_3__ADDR_MSB 31
+#define RDMA_REGION_3__ADDR_LSB 13
+#define RDMA_REGION_3__ADDR_MASK 0xffffe000
+#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
+#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
+#define RDMA_REGION_3__LENGTH_MSB 12
+#define RDMA_REGION_3__LENGTH_LSB 2
+#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
+#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
+#define RDMA_REGION_3__INDI_MSB 1
+#define RDMA_REGION_3__INDI_LSB 1
+#define RDMA_REGION_3__INDI_MASK 0x00000002
+#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
+#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
+#define RDMA_REGION_3__NEXT_MSB 0
+#define RDMA_REGION_3__NEXT_LSB 0
+#define RDMA_REGION_3__NEXT_MASK 0x00000001
+#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
+#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
+
+#define RDMA_REGION_4__ADDRESS 0x00000030
+#define RDMA_REGION_4__OFFSET 0x00000030
+#define RDMA_REGION_4__ADDR_MSB 31
+#define RDMA_REGION_4__ADDR_LSB 13
+#define RDMA_REGION_4__ADDR_MASK 0xffffe000
+#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
+#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
+#define RDMA_REGION_4__LENGTH_MSB 12
+#define RDMA_REGION_4__LENGTH_LSB 2
+#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
+#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
+#define RDMA_REGION_4__INDI_MSB 1
+#define RDMA_REGION_4__INDI_LSB 1
+#define RDMA_REGION_4__INDI_MASK 0x00000002
+#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
+#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
+#define RDMA_REGION_4__NEXT_MSB 0
+#define RDMA_REGION_4__NEXT_LSB 0
+#define RDMA_REGION_4__NEXT_MASK 0x00000001
+#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
+#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
+
+#define RDMA_REGION_5__ADDRESS 0x00000034
+#define RDMA_REGION_5__OFFSET 0x00000034
+#define RDMA_REGION_5__ADDR_MSB 31
+#define RDMA_REGION_5__ADDR_LSB 13
+#define RDMA_REGION_5__ADDR_MASK 0xffffe000
+#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
+#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
+#define RDMA_REGION_5__LENGTH_MSB 12
+#define RDMA_REGION_5__LENGTH_LSB 2
+#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
+#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
+#define RDMA_REGION_5__INDI_MSB 1
+#define RDMA_REGION_5__INDI_LSB 1
+#define RDMA_REGION_5__INDI_MASK 0x00000002
+#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
+#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
+#define RDMA_REGION_5__NEXT_MSB 0
+#define RDMA_REGION_5__NEXT_LSB 0
+#define RDMA_REGION_5__NEXT_MASK 0x00000001
+#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
+#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
+
+#define RDMA_REGION_6__ADDRESS 0x00000038
+#define RDMA_REGION_6__OFFSET 0x00000038
+#define RDMA_REGION_6__ADDR_MSB 31
+#define RDMA_REGION_6__ADDR_LSB 13
+#define RDMA_REGION_6__ADDR_MASK 0xffffe000
+#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
+#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
+#define RDMA_REGION_6__LENGTH_MSB 12
+#define RDMA_REGION_6__LENGTH_LSB 2
+#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
+#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
+#define RDMA_REGION_6__INDI_MSB 1
+#define RDMA_REGION_6__INDI_LSB 1
+#define RDMA_REGION_6__INDI_MASK 0x00000002
+#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
+#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
+#define RDMA_REGION_6__NEXT_MSB 0
+#define RDMA_REGION_6__NEXT_LSB 0
+#define RDMA_REGION_6__NEXT_MASK 0x00000001
+#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
+#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
+
+#define RDMA_REGION_7__ADDRESS 0x0000003c
+#define RDMA_REGION_7__OFFSET 0x0000003c
+#define RDMA_REGION_7__ADDR_MSB 31
+#define RDMA_REGION_7__ADDR_LSB 13
+#define RDMA_REGION_7__ADDR_MASK 0xffffe000
+#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
+#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
+#define RDMA_REGION_7__LENGTH_MSB 12
+#define RDMA_REGION_7__LENGTH_LSB 2
+#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
+#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
+#define RDMA_REGION_7__INDI_MSB 1
+#define RDMA_REGION_7__INDI_LSB 1
+#define RDMA_REGION_7__INDI_MASK 0x00000002
+#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
+#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
+#define RDMA_REGION_7__NEXT_MSB 0
+#define RDMA_REGION_7__NEXT_LSB 0
+#define RDMA_REGION_7__NEXT_MASK 0x00000001
+#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
+#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
+
+#define RDMA_REGION_8__ADDRESS 0x00000040
+#define RDMA_REGION_8__OFFSET 0x00000040
+#define RDMA_REGION_8__ADDR_MSB 31
+#define RDMA_REGION_8__ADDR_LSB 13
+#define RDMA_REGION_8__ADDR_MASK 0xffffe000
+#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
+#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
+#define RDMA_REGION_8__LENGTH_MSB 12
+#define RDMA_REGION_8__LENGTH_LSB 2
+#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
+#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
+#define RDMA_REGION_8__INDI_MSB 1
+#define RDMA_REGION_8__INDI_LSB 1
+#define RDMA_REGION_8__INDI_MASK 0x00000002
+#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
+#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
+#define RDMA_REGION_8__NEXT_MSB 0
+#define RDMA_REGION_8__NEXT_LSB 0
+#define RDMA_REGION_8__NEXT_MASK 0x00000001
+#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
+#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
+
+#define RDMA_REGION_9__ADDRESS 0x00000044
+#define RDMA_REGION_9__OFFSET 0x00000044
+#define RDMA_REGION_9__ADDR_MSB 31
+#define RDMA_REGION_9__ADDR_LSB 13
+#define RDMA_REGION_9__ADDR_MASK 0xffffe000
+#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
+#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
+#define RDMA_REGION_9__LENGTH_MSB 12
+#define RDMA_REGION_9__LENGTH_LSB 2
+#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
+#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
+#define RDMA_REGION_9__INDI_MSB 1
+#define RDMA_REGION_9__INDI_LSB 1
+#define RDMA_REGION_9__INDI_MASK 0x00000002
+#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
+#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
+#define RDMA_REGION_9__NEXT_MSB 0
+#define RDMA_REGION_9__NEXT_LSB 0
+#define RDMA_REGION_9__NEXT_MASK 0x00000001
+#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
+#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
+
+#define RDMA_REGION_10__ADDRESS 0x00000048
+#define RDMA_REGION_10__OFFSET 0x00000048
+#define RDMA_REGION_10__ADDR_MSB 31
+#define RDMA_REGION_10__ADDR_LSB 13
+#define RDMA_REGION_10__ADDR_MASK 0xffffe000
+#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
+#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
+#define RDMA_REGION_10__LENGTH_MSB 12
+#define RDMA_REGION_10__LENGTH_LSB 2
+#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
+#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
+#define RDMA_REGION_10__INDI_MSB 1
+#define RDMA_REGION_10__INDI_LSB 1
+#define RDMA_REGION_10__INDI_MASK 0x00000002
+#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
+#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
+#define RDMA_REGION_10__NEXT_MSB 0
+#define RDMA_REGION_10__NEXT_LSB 0
+#define RDMA_REGION_10__NEXT_MASK 0x00000001
+#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
+#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
+
+#define RDMA_REGION_11__ADDRESS 0x0000004c
+#define RDMA_REGION_11__OFFSET 0x0000004c
+#define RDMA_REGION_11__ADDR_MSB 31
+#define RDMA_REGION_11__ADDR_LSB 13
+#define RDMA_REGION_11__ADDR_MASK 0xffffe000
+#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
+#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
+#define RDMA_REGION_11__LENGTH_MSB 12
+#define RDMA_REGION_11__LENGTH_LSB 2
+#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
+#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
+#define RDMA_REGION_11__INDI_MSB 1
+#define RDMA_REGION_11__INDI_LSB 1
+#define RDMA_REGION_11__INDI_MASK 0x00000002
+#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
+#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
+#define RDMA_REGION_11__NEXT_MSB 0
+#define RDMA_REGION_11__NEXT_LSB 0
+#define RDMA_REGION_11__NEXT_MASK 0x00000001
+#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
+#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
+
+#define RDMA_REGION_12__ADDRESS 0x00000050
+#define RDMA_REGION_12__OFFSET 0x00000050
+#define RDMA_REGION_12__ADDR_MSB 31
+#define RDMA_REGION_12__ADDR_LSB 13
+#define RDMA_REGION_12__ADDR_MASK 0xffffe000
+#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
+#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
+#define RDMA_REGION_12__LENGTH_MSB 12
+#define RDMA_REGION_12__LENGTH_LSB 2
+#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
+#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
+#define RDMA_REGION_12__INDI_MSB 1
+#define RDMA_REGION_12__INDI_LSB 1
+#define RDMA_REGION_12__INDI_MASK 0x00000002
+#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
+#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
+#define RDMA_REGION_12__NEXT_MSB 0
+#define RDMA_REGION_12__NEXT_LSB 0
+#define RDMA_REGION_12__NEXT_MASK 0x00000001
+#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
+#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
+
+#define RDMA_REGION_13__ADDRESS 0x00000054
+#define RDMA_REGION_13__OFFSET 0x00000054
+#define RDMA_REGION_13__ADDR_MSB 31
+#define RDMA_REGION_13__ADDR_LSB 13
+#define RDMA_REGION_13__ADDR_MASK 0xffffe000
+#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
+#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
+#define RDMA_REGION_13__LENGTH_MSB 12
+#define RDMA_REGION_13__LENGTH_LSB 2
+#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
+#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
+#define RDMA_REGION_13__INDI_MSB 1
+#define RDMA_REGION_13__INDI_LSB 1
+#define RDMA_REGION_13__INDI_MASK 0x00000002
+#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
+#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
+#define RDMA_REGION_13__NEXT_MSB 0
+#define RDMA_REGION_13__NEXT_LSB 0
+#define RDMA_REGION_13__NEXT_MASK 0x00000001
+#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
+#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
+
+#define RDMA_REGION_14__ADDRESS 0x00000058
+#define RDMA_REGION_14__OFFSET 0x00000058
+#define RDMA_REGION_14__ADDR_MSB 31
+#define RDMA_REGION_14__ADDR_LSB 13
+#define RDMA_REGION_14__ADDR_MASK 0xffffe000
+#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
+#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
+#define RDMA_REGION_14__LENGTH_MSB 12
+#define RDMA_REGION_14__LENGTH_LSB 2
+#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
+#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
+#define RDMA_REGION_14__INDI_MSB 1
+#define RDMA_REGION_14__INDI_LSB 1
+#define RDMA_REGION_14__INDI_MASK 0x00000002
+#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
+#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
+#define RDMA_REGION_14__NEXT_MSB 0
+#define RDMA_REGION_14__NEXT_LSB 0
+#define RDMA_REGION_14__NEXT_MASK 0x00000001
+#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
+#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
+
+#define RDMA_REGION_15__ADDRESS 0x0000005c
+#define RDMA_REGION_15__OFFSET 0x0000005c
+#define RDMA_REGION_15__ADDR_MSB 31
+#define RDMA_REGION_15__ADDR_LSB 13
+#define RDMA_REGION_15__ADDR_MASK 0xffffe000
+#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
+#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
+#define RDMA_REGION_15__LENGTH_MSB 12
+#define RDMA_REGION_15__LENGTH_LSB 2
+#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc
+#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
+#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
+#define RDMA_REGION_15__INDI_MSB 1
+#define RDMA_REGION_15__INDI_LSB 1
+#define RDMA_REGION_15__INDI_MASK 0x00000002
+#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
+#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
+#define RDMA_REGION_15__NEXT_MSB 0
+#define RDMA_REGION_15__NEXT_LSB 0
+#define RDMA_REGION_15__NEXT_MASK 0x00000001
+#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
+#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
+
+#define DMA_STATUS_ADDRESS 0x00000060
+#define DMA_STATUS_OFFSET 0x00000060
+#define DMA_STATUS_ERROR_CODE_MSB 14
+#define DMA_STATUS_ERROR_CODE_LSB 4
+#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0
+#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
+#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
+#define DMA_STATUS_ERROR_MSB 3
+#define DMA_STATUS_ERROR_LSB 3
+#define DMA_STATUS_ERROR_MASK 0x00000008
+#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
+#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
+#define DMA_STATUS_DONE_MSB 2
+#define DMA_STATUS_DONE_LSB 2
+#define DMA_STATUS_DONE_MASK 0x00000004
+#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
+#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
+#define DMA_STATUS_STOPPED_MSB 1
+#define DMA_STATUS_STOPPED_LSB 1
+#define DMA_STATUS_STOPPED_MASK 0x00000002
+#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
+#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
+#define DMA_STATUS_RUNNING_MSB 0
+#define DMA_STATUS_RUNNING_LSB 0
+#define DMA_STATUS_RUNNING_MASK 0x00000001
+#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
+#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
+
+#define DMA_INT_EN_ADDRESS 0x00000064
+#define DMA_INT_EN_OFFSET 0x00000064
+#define DMA_INT_EN_ERROR_ENA_MSB 3
+#define DMA_INT_EN_ERROR_ENA_LSB 3
+#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008
+#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
+#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
+#define DMA_INT_EN_DONE_ENA_MSB 2
+#define DMA_INT_EN_DONE_ENA_LSB 2
+#define DMA_INT_EN_DONE_ENA_MASK 0x00000004
+#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
+#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
+#define DMA_INT_EN_STOPPED_ENA_MSB 1
+#define DMA_INT_EN_STOPPED_ENA_LSB 1
+#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002
+#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
+#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rdma_reg_reg_s {
+ volatile unsigned int dma_config;
+ volatile unsigned int dma_control;
+ volatile unsigned int dma_src;
+ volatile unsigned int dma_dest;
+ volatile unsigned int dma_length;
+ volatile unsigned int vmc_base;
+ volatile unsigned int indirect_reg;
+ volatile unsigned int indirect_return;
+ volatile unsigned int rdma_region_0_;
+ volatile unsigned int rdma_region_1_;
+ volatile unsigned int rdma_region_2_;
+ volatile unsigned int rdma_region_3_;
+ volatile unsigned int rdma_region_4_;
+ volatile unsigned int rdma_region_5_;
+ volatile unsigned int rdma_region_6_;
+ volatile unsigned int rdma_region_7_;
+ volatile unsigned int rdma_region_8_;
+ volatile unsigned int rdma_region_9_;
+ volatile unsigned int rdma_region_10_;
+ volatile unsigned int rdma_region_11_;
+ volatile unsigned int rdma_region_12_;
+ volatile unsigned int rdma_region_13_;
+ volatile unsigned int rdma_region_14_;
+ volatile unsigned int rdma_region_15_;
+ volatile unsigned int dma_status;
+ volatile unsigned int dma_int_en;
+} rdma_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RDMA_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h
new file mode 100644
index 000000000000..312af9284b7c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h
@@ -0,0 +1,971 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "rtc_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
+#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET
+#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB
+#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB
+#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK
+#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x)
+#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x)
+#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB
+#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB
+#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK
+#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)
+#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)
+#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB
+#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB
+#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK
+#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)
+#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)
+#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB
+#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB
+#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK
+#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x)
+#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x)
+#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB
+#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB
+#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK
+#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x)
+#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x)
+#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB
+#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB
+#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK
+#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x)
+#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x)
+#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB
+#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB
+#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK
+#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x)
+#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x)
+#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB
+#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB
+#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK
+#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x)
+#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x)
+#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB
+#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB
+#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK
+#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)
+#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)
+#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB
+#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB
+#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK
+#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)
+#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)
+#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB
+#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB
+#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK
+#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)
+#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)
+#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB
+#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB
+#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK
+#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x)
+#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x)
+#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB
+#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB
+#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK
+#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x)
+#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x)
+#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB
+#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB
+#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
+#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
+#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
+#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
+#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
+#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
+#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
+#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
+#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
+#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
+#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
+#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
+#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
+#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
+#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
+#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
+#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
+#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
+#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
+#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
+#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
+#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
+#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
+#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
+#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
+#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
+#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
+#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
+#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
+#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
+#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
+#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
+#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
+#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
+#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
+#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
+#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
+#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
+#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
+#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
+#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
+#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
+#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
+#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
+#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
+#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
+#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
+#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
+#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
+#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
+#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
+#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
+#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
+#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
+#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
+#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
+#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
+#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
+#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
+#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
+#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
+#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
+#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
+#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
+#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
+#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
+#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
+#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
+#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
+#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
+#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
+#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
+#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
+#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
+#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
+#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
+#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
+#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
+#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
+#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
+#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
+#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
+#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
+#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
+#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
+#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
+#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
+#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
+#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
+#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
+#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
+#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
+#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
+#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
+#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
+#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB
+#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK
+#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x)
+#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x)
+#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS
+#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET
+#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB
+#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB
+#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK
+#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x)
+#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x)
+#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS
+#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET
+#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB
+#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB
+#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK
+#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)
+#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)
+#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB
+#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB
+#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
+#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
+#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
+#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
+#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
+#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
+#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
+#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
+#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
+#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
+#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
+#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
+#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
+#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
+#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
+#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
+#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
+#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
+#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
+#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
+#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
+#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
+#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
+#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
+#define WDT_ADDRESS WLAN_WDT_ADDRESS
+#define WDT_OFFSET WLAN_WDT_OFFSET
+#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
+#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
+#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
+#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
+#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
+#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
+#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
+#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
+#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
+#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
+#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
+#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
+#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
+#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
+#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
+#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
+#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
+#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
+#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
+#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
+#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
+#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
+#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
+#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
+#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
+#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
+#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
+#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
+#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
+#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
+#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
+#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
+#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
+#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
+#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
+#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
+#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
+#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
+#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
+#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
+#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
+#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
+#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
+#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
+#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
+#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
+#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
+#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
+#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
+#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
+#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
+#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
+#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
+#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
+#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
+#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
+#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
+#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
+#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
+#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
+#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
+#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
+#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
+#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
+#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
+#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
+#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
+#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
+#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
+#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
+#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
+#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
+#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
+#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
+#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
+#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
+#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
+#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
+#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
+#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
+#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
+#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
+#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
+#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
+#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
+#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
+#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
+#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
+#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
+#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
+#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
+#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
+#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
+#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
+#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
+#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
+#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
+#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
+#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
+#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
+#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
+#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
+#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
+#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
+#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
+#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
+#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
+#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
+#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
+#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
+#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
+#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
+#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
+#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
+#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
+#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
+#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
+#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
+#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
+#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
+#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
+#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
+#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
+#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
+#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
+#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
+#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
+#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
+#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
+#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
+#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
+#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
+#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
+#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
+#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
+#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
+#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
+#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
+#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
+#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
+#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
+#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
+#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
+#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
+#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
+#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
+#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
+#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
+#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
+#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
+#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
+#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
+#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
+#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
+#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
+#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
+#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
+#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
+#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
+#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
+#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
+#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
+#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
+#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
+#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
+#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
+#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
+#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
+#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
+#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
+#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
+#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
+#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
+#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
+#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
+#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
+#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
+#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
+#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
+#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
+#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
+#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
+#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
+#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
+#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
+#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
+#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
+#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
+#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
+#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
+#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
+#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
+#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
+#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
+#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
+#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
+#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
+#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
+#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
+#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
+#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
+#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
+#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
+#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
+#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
+#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
+#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
+#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
+#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
+#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
+#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
+#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
+#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
+#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
+#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
+#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
+#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
+#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
+#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
+#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
+#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
+#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
+#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
+#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
+#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
+#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
+#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
+#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
+#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
+#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
+#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
+#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
+#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
+#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
+#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
+#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
+#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
+#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
+#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
+#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
+#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
+#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
+#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
+#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
+#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
+#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
+#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
+#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
+#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
+#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
+#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
+#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
+#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
+#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
+#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
+#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
+#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
+#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
+#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
+#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
+#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
+#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
+#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
+#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
+#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
+#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
+#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
+#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
+#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
+#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
+#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
+#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
+#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
+#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
+#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
+#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
+#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
+#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
+#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
+#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
+#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
+#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
+#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
+#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
+#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
+#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
+#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
+#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
+#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
+#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
+#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
+#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
+#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
+#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
+#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
+#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
+#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
+#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
+#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
+#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
+#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
+#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
+#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
+#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
+#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
+#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
+#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
+#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
+#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
+#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
+#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
+#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
+#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
+#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
+#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
+#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
+#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
+#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
+#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
+#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
+#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
+#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
+#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
+#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
+#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
+#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
+#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
+#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
+#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
+#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
+#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
+#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
+#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
+#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
+#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
+#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
+#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
+#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
+#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
+#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
+#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
+#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
+#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
+#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
+#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
+#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
+#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
+#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
+#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
+#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
+#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
+#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
+#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
+#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
+#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
+#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
+#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
+#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
+#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
+#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
+#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
+#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
+#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
+#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
+#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
+#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
+#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
+#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
+#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
+#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
+#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
+#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
+#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
+#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
+#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
+#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
+#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
+#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
+#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
+#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
+#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
+#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
+#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
+#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
+#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
+#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
+#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
+#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
+#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
+#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
+#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
+#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
+#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
+#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
+#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
+#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
+#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
+#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
+#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
+#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
+#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
+#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
+#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
+#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
+#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
+#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
+#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
+#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
+#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
+#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
+#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
+#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
+#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
+#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
+#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
+#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
+#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
+#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
+#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
+#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
+#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
+#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
+#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
+#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
+#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
+#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
+#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
+#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
+#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
+#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
+#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
+#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
+#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
+#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
+#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
+#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
+#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
+#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
+#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
+#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
+#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
+#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
+#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
+#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
+#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
+#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
+#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
+#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
+#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
+#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
+#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
+#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
+#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
+#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
+#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
+#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
+#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
+#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
+#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
+#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
+#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
+#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
+#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB
+#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK
+#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x)
+#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x)
+#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS
+#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET
+#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB
+#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB
+#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK
+#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)
+#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)
+#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB
+#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB
+#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK
+#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x)
+#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x)
+#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB
+#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB
+#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK
+#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)
+#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)
+#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB
+#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB
+#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK
+#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x)
+#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x)
+#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB
+#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB
+#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
+#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
+#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
+#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
+#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
+#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
+#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
+#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
+#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
+#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
+#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
+#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
+#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
+#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
+#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
+#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
+#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
+#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
+#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
+#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
+#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
+#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
+#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
+#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
+#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
+#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
+#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
+#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
+#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
+#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
+#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
+#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
+#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
+#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
+#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
+#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
+#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
+#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
+#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
+#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
+#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
+#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
+#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
+#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
+#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
+#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
+#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
+#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
+#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
+#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB
+#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK
+#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)
+#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)
+#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS
+#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)
+#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)
+#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS
+#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET
+#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB
+#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB
+#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK
+#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x)
+#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x)
+#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB
+#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB
+#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
+#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
+#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
+#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
+#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
+#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
+#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
+#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
+#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
+#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
+#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
+#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
+#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
+#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
+#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
+#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
+#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
+#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
+#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
+#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
+#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
+#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
+#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
+#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
+#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
+#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
+#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
+#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
+#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
+#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
+#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
+#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
+#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
+#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
+#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
+#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
+#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
+#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
+#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
+#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
+#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
+#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
+#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
+#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
+#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
+#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
+#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
+#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
+#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
+#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
+#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
+#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
+#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
+#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
+#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
+#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
+#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
+#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
+#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
+#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
+#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
+#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
+#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
+#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
+#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
+#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
+#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
+#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
+#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
+#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
+#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
+#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
+#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
+#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
+#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
+#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
+#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
+#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
+#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
+#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
+#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
+#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
+#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
+#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
+#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
+#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
+#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
+#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
+#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
+#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
+#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
+#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
+#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
+#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
+#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
+#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
+#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
+#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
+#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
+#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
+#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
+#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
+#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
+#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
+#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
+#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
+#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
+#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
+#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
+#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
+#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
+#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
+#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
+#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
+#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
+#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
+#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
+#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
+#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
+#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
+#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
+#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
+#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
+#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
+#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
+#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
+#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
+#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
+#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
+#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h
new file mode 100644
index 000000000000..c215f2e78809
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h
@@ -0,0 +1,2061 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _RTC_WLAN_REG_REG_H_
+#define _RTC_WLAN_REG_REG_H_
+
+#define WLAN_RESET_CONTROL_ADDRESS 0x00000000
+#define WLAN_RESET_CONTROL_OFFSET 0x00000000
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB)
+#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK)
+#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13
+#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13
+#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000
+#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12
+#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12
+#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000
+#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB)
+#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK)
+#define WLAN_RESET_CONTROL_RST_OUT_MSB 9
+#define WLAN_RESET_CONTROL_RST_OUT_LSB 9
+#define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200
+#define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB)
+#define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK)
+#define WLAN_RESET_CONTROL_COLD_RST_MSB 8
+#define WLAN_RESET_CONTROL_COLD_RST_LSB 8
+#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100
+#define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_WARM_RST_MSB 7
+#define WLAN_RESET_CONTROL_WARM_RST_LSB 7
+#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080
+#define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB)
+#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB)
+#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK)
+#define WLAN_RESET_CONTROL_MBOX_RST_MSB 2
+#define WLAN_RESET_CONTROL_MBOX_RST_LSB 2
+#define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004
+#define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB)
+#define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK)
+#define WLAN_RESET_CONTROL_UART_RST_MSB 1
+#define WLAN_RESET_CONTROL_UART_RST_LSB 1
+#define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002
+#define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB)
+#define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK)
+#define WLAN_RESET_CONTROL_SI0_RST_MSB 0
+#define WLAN_RESET_CONTROL_SI0_RST_LSB 0
+#define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001
+#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB)
+#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK)
+
+#define WLAN_XTAL_CONTROL_ADDRESS 0x00000004
+#define WLAN_XTAL_CONTROL_OFFSET 0x00000004
+#define WLAN_XTAL_CONTROL_TCXO_MSB 0
+#define WLAN_XTAL_CONTROL_TCXO_LSB 0
+#define WLAN_XTAL_CONTROL_TCXO_MASK 0x00000001
+#define WLAN_XTAL_CONTROL_TCXO_GET(x) (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB)
+#define WLAN_XTAL_CONTROL_TCXO_SET(x) (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK)
+
+#define WLAN_TCXO_DETECT_ADDRESS 0x00000008
+#define WLAN_TCXO_DETECT_OFFSET 0x00000008
+#define WLAN_TCXO_DETECT_PRESENT_MSB 0
+#define WLAN_TCXO_DETECT_PRESENT_LSB 0
+#define WLAN_TCXO_DETECT_PRESENT_MASK 0x00000001
+#define WLAN_TCXO_DETECT_PRESENT_GET(x) (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB)
+#define WLAN_TCXO_DETECT_PRESENT_SET(x) (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK)
+
+#define WLAN_XTAL_TEST_ADDRESS 0x0000000c
+#define WLAN_XTAL_TEST_OFFSET 0x0000000c
+#define WLAN_XTAL_TEST_NOTCXODET_MSB 0
+#define WLAN_XTAL_TEST_NOTCXODET_LSB 0
+#define WLAN_XTAL_TEST_NOTCXODET_MASK 0x00000001
+#define WLAN_XTAL_TEST_NOTCXODET_GET(x) (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB)
+#define WLAN_XTAL_TEST_NOTCXODET_SET(x) (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK)
+
+#define WLAN_QUADRATURE_ADDRESS 0x00000010
+#define WLAN_QUADRATURE_OFFSET 0x00000010
+#define WLAN_QUADRATURE_ADC_MSB 7
+#define WLAN_QUADRATURE_ADC_LSB 4
+#define WLAN_QUADRATURE_ADC_MASK 0x000000f0
+#define WLAN_QUADRATURE_ADC_GET(x) (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB)
+#define WLAN_QUADRATURE_ADC_SET(x) (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK)
+#define WLAN_QUADRATURE_SEL_MSB 2
+#define WLAN_QUADRATURE_SEL_LSB 2
+#define WLAN_QUADRATURE_SEL_MASK 0x00000004
+#define WLAN_QUADRATURE_SEL_GET(x) (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB)
+#define WLAN_QUADRATURE_SEL_SET(x) (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK)
+#define WLAN_QUADRATURE_DAC_MSB 1
+#define WLAN_QUADRATURE_DAC_LSB 0
+#define WLAN_QUADRATURE_DAC_MASK 0x00000003
+#define WLAN_QUADRATURE_DAC_GET(x) (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB)
+#define WLAN_QUADRATURE_DAC_SET(x) (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK)
+
+#define WLAN_PLL_CONTROL_ADDRESS 0x00000014
+#define WLAN_PLL_CONTROL_OFFSET 0x00000014
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB 20
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB 20
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB)
+#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK)
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB 19
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB 19
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB)
+#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK)
+#define WLAN_PLL_CONTROL_NOPWD_MSB 18
+#define WLAN_PLL_CONTROL_NOPWD_LSB 18
+#define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
+#define WLAN_PLL_CONTROL_NOPWD_GET(x) (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
+#define WLAN_PLL_CONTROL_NOPWD_SET(x) (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
+#define WLAN_PLL_CONTROL_UPDATING_MSB 17
+#define WLAN_PLL_CONTROL_UPDATING_LSB 17
+#define WLAN_PLL_CONTROL_UPDATING_MASK 0x00020000
+#define WLAN_PLL_CONTROL_UPDATING_GET(x) (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB)
+#define WLAN_PLL_CONTROL_UPDATING_SET(x) (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK)
+#define WLAN_PLL_CONTROL_BYPASS_MSB 16
+#define WLAN_PLL_CONTROL_BYPASS_LSB 16
+#define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
+#define WLAN_PLL_CONTROL_BYPASS_GET(x) (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
+#define WLAN_PLL_CONTROL_BYPASS_SET(x) (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
+#define WLAN_PLL_CONTROL_REFDIV_MSB 15
+#define WLAN_PLL_CONTROL_REFDIV_LSB 12
+#define WLAN_PLL_CONTROL_REFDIV_MASK 0x0000f000
+#define WLAN_PLL_CONTROL_REFDIV_GET(x) (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
+#define WLAN_PLL_CONTROL_REFDIV_SET(x) (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
+#define WLAN_PLL_CONTROL_DIV_MSB 9
+#define WLAN_PLL_CONTROL_DIV_LSB 0
+#define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
+#define WLAN_PLL_CONTROL_DIV_GET(x) (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
+#define WLAN_PLL_CONTROL_DIV_SET(x) (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
+
+#define WLAN_PLL_SETTLE_ADDRESS 0x00000018
+#define WLAN_PLL_SETTLE_OFFSET 0x00000018
+#define WLAN_PLL_SETTLE_TIME_MSB 11
+#define WLAN_PLL_SETTLE_TIME_LSB 0
+#define WLAN_PLL_SETTLE_TIME_MASK 0x00000fff
+#define WLAN_PLL_SETTLE_TIME_GET(x) (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
+#define WLAN_PLL_SETTLE_TIME_SET(x) (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
+
+#define WLAN_XTAL_SETTLE_ADDRESS 0x0000001c
+#define WLAN_XTAL_SETTLE_OFFSET 0x0000001c
+#define WLAN_XTAL_SETTLE_TIME_MSB 7
+#define WLAN_XTAL_SETTLE_TIME_LSB 0
+#define WLAN_XTAL_SETTLE_TIME_MASK 0x000000ff
+#define WLAN_XTAL_SETTLE_TIME_GET(x) (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB)
+#define WLAN_XTAL_SETTLE_TIME_SET(x) (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK)
+
+#define WLAN_CPU_CLOCK_ADDRESS 0x00000020
+#define WLAN_CPU_CLOCK_OFFSET 0x00000020
+#define WLAN_CPU_CLOCK_STANDARD_MSB 1
+#define WLAN_CPU_CLOCK_STANDARD_LSB 0
+#define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003
+#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB)
+#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK)
+
+#define WLAN_CLOCK_OUT_ADDRESS 0x00000024
+#define WLAN_CLOCK_OUT_OFFSET 0x00000024
+#define WLAN_CLOCK_OUT_SELECT_MSB 3
+#define WLAN_CLOCK_OUT_SELECT_LSB 0
+#define WLAN_CLOCK_OUT_SELECT_MASK 0x0000000f
+#define WLAN_CLOCK_OUT_SELECT_GET(x) (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB)
+#define WLAN_CLOCK_OUT_SELECT_SET(x) (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK)
+
+#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028
+#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028
+#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2
+#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2
+#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004
+#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB)
+#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK)
+#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0
+#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0
+#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
+#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB)
+#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define WLAN_BIAS_OVERRIDE_ADDRESS 0x0000002c
+#define WLAN_BIAS_OVERRIDE_OFFSET 0x0000002c
+#define WLAN_BIAS_OVERRIDE_ON_MSB 0
+#define WLAN_BIAS_OVERRIDE_ON_LSB 0
+#define WLAN_BIAS_OVERRIDE_ON_MASK 0x00000001
+#define WLAN_BIAS_OVERRIDE_ON_GET(x) (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB)
+#define WLAN_BIAS_OVERRIDE_ON_SET(x) (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK)
+
+#define WLAN_WDT_CONTROL_ADDRESS 0x00000030
+#define WLAN_WDT_CONTROL_OFFSET 0x00000030
+#define WLAN_WDT_CONTROL_ACTION_MSB 2
+#define WLAN_WDT_CONTROL_ACTION_LSB 0
+#define WLAN_WDT_CONTROL_ACTION_MASK 0x00000007
+#define WLAN_WDT_CONTROL_ACTION_GET(x) (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB)
+#define WLAN_WDT_CONTROL_ACTION_SET(x) (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK)
+
+#define WLAN_WDT_STATUS_ADDRESS 0x00000034
+#define WLAN_WDT_STATUS_OFFSET 0x00000034
+#define WLAN_WDT_STATUS_INTERRUPT_MSB 0
+#define WLAN_WDT_STATUS_INTERRUPT_LSB 0
+#define WLAN_WDT_STATUS_INTERRUPT_MASK 0x00000001
+#define WLAN_WDT_STATUS_INTERRUPT_GET(x) (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB)
+#define WLAN_WDT_STATUS_INTERRUPT_SET(x) (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK)
+
+#define WLAN_WDT_ADDRESS 0x00000038
+#define WLAN_WDT_OFFSET 0x00000038
+#define WLAN_WDT_TARGET_MSB 21
+#define WLAN_WDT_TARGET_LSB 0
+#define WLAN_WDT_TARGET_MASK 0x003fffff
+#define WLAN_WDT_TARGET_GET(x) (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB)
+#define WLAN_WDT_TARGET_SET(x) (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK)
+
+#define WLAN_WDT_COUNT_ADDRESS 0x0000003c
+#define WLAN_WDT_COUNT_OFFSET 0x0000003c
+#define WLAN_WDT_COUNT_VALUE_MSB 21
+#define WLAN_WDT_COUNT_VALUE_LSB 0
+#define WLAN_WDT_COUNT_VALUE_MASK 0x003fffff
+#define WLAN_WDT_COUNT_VALUE_GET(x) (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB)
+#define WLAN_WDT_COUNT_VALUE_SET(x) (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK)
+
+#define WLAN_WDT_RESET_ADDRESS 0x00000040
+#define WLAN_WDT_RESET_OFFSET 0x00000040
+#define WLAN_WDT_RESET_VALUE_MSB 0
+#define WLAN_WDT_RESET_VALUE_LSB 0
+#define WLAN_WDT_RESET_VALUE_MASK 0x00000001
+#define WLAN_WDT_RESET_VALUE_GET(x) (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB)
+#define WLAN_WDT_RESET_VALUE_SET(x) (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK)
+
+#define WLAN_INT_STATUS_ADDRESS 0x00000044
+#define WLAN_INT_STATUS_OFFSET 0x00000044
+#define WLAN_INT_STATUS_HCI_UART_MSB 21
+#define WLAN_INT_STATUS_HCI_UART_LSB 21
+#define WLAN_INT_STATUS_HCI_UART_MASK 0x00200000
+#define WLAN_INT_STATUS_HCI_UART_GET(x) (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB)
+#define WLAN_INT_STATUS_HCI_UART_SET(x) (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK)
+#define WLAN_INT_STATUS_THERM_MSB 20
+#define WLAN_INT_STATUS_THERM_LSB 20
+#define WLAN_INT_STATUS_THERM_MASK 0x00100000
+#define WLAN_INT_STATUS_THERM_GET(x) (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB)
+#define WLAN_INT_STATUS_THERM_SET(x) (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK)
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB 19
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB 19
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00080000
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB)
+#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK)
+#define WLAN_INT_STATUS_UART_MBOX_MSB 18
+#define WLAN_INT_STATUS_UART_MBOX_LSB 18
+#define WLAN_INT_STATUS_UART_MBOX_MASK 0x00040000
+#define WLAN_INT_STATUS_UART_MBOX_GET(x) (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB)
+#define WLAN_INT_STATUS_UART_MBOX_SET(x) (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK)
+#define WLAN_INT_STATUS_GENERIC_MBOX_MSB 17
+#define WLAN_INT_STATUS_GENERIC_MBOX_LSB 17
+#define WLAN_INT_STATUS_GENERIC_MBOX_MASK 0x00020000
+#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x) (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB)
+#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x) (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK)
+#define WLAN_INT_STATUS_RDMA_MSB 16
+#define WLAN_INT_STATUS_RDMA_LSB 16
+#define WLAN_INT_STATUS_RDMA_MASK 0x00010000
+#define WLAN_INT_STATUS_RDMA_GET(x) (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB)
+#define WLAN_INT_STATUS_RDMA_SET(x) (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK)
+#define WLAN_INT_STATUS_BTCOEX_MSB 15
+#define WLAN_INT_STATUS_BTCOEX_LSB 15
+#define WLAN_INT_STATUS_BTCOEX_MASK 0x00008000
+#define WLAN_INT_STATUS_BTCOEX_GET(x) (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB)
+#define WLAN_INT_STATUS_BTCOEX_SET(x) (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK)
+#define WLAN_INT_STATUS_RTC_POWER_MSB 14
+#define WLAN_INT_STATUS_RTC_POWER_LSB 14
+#define WLAN_INT_STATUS_RTC_POWER_MASK 0x00004000
+#define WLAN_INT_STATUS_RTC_POWER_GET(x) (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB)
+#define WLAN_INT_STATUS_RTC_POWER_SET(x) (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK)
+#define WLAN_INT_STATUS_MAC_MSB 13
+#define WLAN_INT_STATUS_MAC_LSB 13
+#define WLAN_INT_STATUS_MAC_MASK 0x00002000
+#define WLAN_INT_STATUS_MAC_GET(x) (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB)
+#define WLAN_INT_STATUS_MAC_SET(x) (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK)
+#define WLAN_INT_STATUS_MAILBOX_MSB 12
+#define WLAN_INT_STATUS_MAILBOX_LSB 12
+#define WLAN_INT_STATUS_MAILBOX_MASK 0x00001000
+#define WLAN_INT_STATUS_MAILBOX_GET(x) (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB)
+#define WLAN_INT_STATUS_MAILBOX_SET(x) (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK)
+#define WLAN_INT_STATUS_RTC_ALARM_MSB 11
+#define WLAN_INT_STATUS_RTC_ALARM_LSB 11
+#define WLAN_INT_STATUS_RTC_ALARM_MASK 0x00000800
+#define WLAN_INT_STATUS_RTC_ALARM_GET(x) (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB)
+#define WLAN_INT_STATUS_RTC_ALARM_SET(x) (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK)
+#define WLAN_INT_STATUS_HF_TIMER_MSB 10
+#define WLAN_INT_STATUS_HF_TIMER_LSB 10
+#define WLAN_INT_STATUS_HF_TIMER_MASK 0x00000400
+#define WLAN_INT_STATUS_HF_TIMER_GET(x) (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB)
+#define WLAN_INT_STATUS_HF_TIMER_SET(x) (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK)
+#define WLAN_INT_STATUS_LF_TIMER3_MSB 9
+#define WLAN_INT_STATUS_LF_TIMER3_LSB 9
+#define WLAN_INT_STATUS_LF_TIMER3_MASK 0x00000200
+#define WLAN_INT_STATUS_LF_TIMER3_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB)
+#define WLAN_INT_STATUS_LF_TIMER3_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK)
+#define WLAN_INT_STATUS_LF_TIMER2_MSB 8
+#define WLAN_INT_STATUS_LF_TIMER2_LSB 8
+#define WLAN_INT_STATUS_LF_TIMER2_MASK 0x00000100
+#define WLAN_INT_STATUS_LF_TIMER2_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB)
+#define WLAN_INT_STATUS_LF_TIMER2_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK)
+#define WLAN_INT_STATUS_LF_TIMER1_MSB 7
+#define WLAN_INT_STATUS_LF_TIMER1_LSB 7
+#define WLAN_INT_STATUS_LF_TIMER1_MASK 0x00000080
+#define WLAN_INT_STATUS_LF_TIMER1_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB)
+#define WLAN_INT_STATUS_LF_TIMER1_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK)
+#define WLAN_INT_STATUS_LF_TIMER0_MSB 6
+#define WLAN_INT_STATUS_LF_TIMER0_LSB 6
+#define WLAN_INT_STATUS_LF_TIMER0_MASK 0x00000040
+#define WLAN_INT_STATUS_LF_TIMER0_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB)
+#define WLAN_INT_STATUS_LF_TIMER0_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK)
+#define WLAN_INT_STATUS_KEYPAD_MSB 5
+#define WLAN_INT_STATUS_KEYPAD_LSB 5
+#define WLAN_INT_STATUS_KEYPAD_MASK 0x00000020
+#define WLAN_INT_STATUS_KEYPAD_GET(x) (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB)
+#define WLAN_INT_STATUS_KEYPAD_SET(x) (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK)
+#define WLAN_INT_STATUS_SI_MSB 4
+#define WLAN_INT_STATUS_SI_LSB 4
+#define WLAN_INT_STATUS_SI_MASK 0x00000010
+#define WLAN_INT_STATUS_SI_GET(x) (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB)
+#define WLAN_INT_STATUS_SI_SET(x) (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK)
+#define WLAN_INT_STATUS_GPIO_MSB 3
+#define WLAN_INT_STATUS_GPIO_LSB 3
+#define WLAN_INT_STATUS_GPIO_MASK 0x00000008
+#define WLAN_INT_STATUS_GPIO_GET(x) (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB)
+#define WLAN_INT_STATUS_GPIO_SET(x) (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK)
+#define WLAN_INT_STATUS_UART_MSB 2
+#define WLAN_INT_STATUS_UART_LSB 2
+#define WLAN_INT_STATUS_UART_MASK 0x00000004
+#define WLAN_INT_STATUS_UART_GET(x) (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB)
+#define WLAN_INT_STATUS_UART_SET(x) (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK)
+#define WLAN_INT_STATUS_ERROR_MSB 1
+#define WLAN_INT_STATUS_ERROR_LSB 1
+#define WLAN_INT_STATUS_ERROR_MASK 0x00000002
+#define WLAN_INT_STATUS_ERROR_GET(x) (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB)
+#define WLAN_INT_STATUS_ERROR_SET(x) (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK)
+#define WLAN_INT_STATUS_WDT_INT_MSB 0
+#define WLAN_INT_STATUS_WDT_INT_LSB 0
+#define WLAN_INT_STATUS_WDT_INT_MASK 0x00000001
+#define WLAN_INT_STATUS_WDT_INT_GET(x) (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB)
+#define WLAN_INT_STATUS_WDT_INT_SET(x) (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK)
+
+#define WLAN_LF_TIMER0_ADDRESS 0x00000048
+#define WLAN_LF_TIMER0_OFFSET 0x00000048
+#define WLAN_LF_TIMER0_TARGET_MSB 31
+#define WLAN_LF_TIMER0_TARGET_LSB 0
+#define WLAN_LF_TIMER0_TARGET_MASK 0xffffffff
+#define WLAN_LF_TIMER0_TARGET_GET(x) (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB)
+#define WLAN_LF_TIMER0_TARGET_SET(x) (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT0_ADDRESS 0x0000004c
+#define WLAN_LF_TIMER_COUNT0_OFFSET 0x0000004c
+#define WLAN_LF_TIMER_COUNT0_VALUE_MSB 31
+#define WLAN_LF_TIMER_COUNT0_VALUE_LSB 0
+#define WLAN_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff
+#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL0_ADDRESS 0x00000050
+#define WLAN_LF_TIMER_CONTROL0_OFFSET 0x00000050
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB 2
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB 2
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL0_RESET_MSB 0
+#define WLAN_LF_TIMER_CONTROL0_RESET_LSB 0
+#define WLAN_LF_TIMER_CONTROL0_RESET_MASK 0x00000001
+#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS0_ADDRESS 0x00000054
+#define WLAN_LF_TIMER_STATUS0_OFFSET 0x00000054
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB 0
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB 0
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER1_ADDRESS 0x00000058
+#define WLAN_LF_TIMER1_OFFSET 0x00000058
+#define WLAN_LF_TIMER1_TARGET_MSB 31
+#define WLAN_LF_TIMER1_TARGET_LSB 0
+#define WLAN_LF_TIMER1_TARGET_MASK 0xffffffff
+#define WLAN_LF_TIMER1_TARGET_GET(x) (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB)
+#define WLAN_LF_TIMER1_TARGET_SET(x) (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT1_ADDRESS 0x0000005c
+#define WLAN_LF_TIMER_COUNT1_OFFSET 0x0000005c
+#define WLAN_LF_TIMER_COUNT1_VALUE_MSB 31
+#define WLAN_LF_TIMER_COUNT1_VALUE_LSB 0
+#define WLAN_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff
+#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL1_ADDRESS 0x00000060
+#define WLAN_LF_TIMER_CONTROL1_OFFSET 0x00000060
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB 2
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB 2
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL1_RESET_MSB 0
+#define WLAN_LF_TIMER_CONTROL1_RESET_LSB 0
+#define WLAN_LF_TIMER_CONTROL1_RESET_MASK 0x00000001
+#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS1_ADDRESS 0x00000064
+#define WLAN_LF_TIMER_STATUS1_OFFSET 0x00000064
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB 0
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB 0
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER2_ADDRESS 0x00000068
+#define WLAN_LF_TIMER2_OFFSET 0x00000068
+#define WLAN_LF_TIMER2_TARGET_MSB 31
+#define WLAN_LF_TIMER2_TARGET_LSB 0
+#define WLAN_LF_TIMER2_TARGET_MASK 0xffffffff
+#define WLAN_LF_TIMER2_TARGET_GET(x) (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB)
+#define WLAN_LF_TIMER2_TARGET_SET(x) (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT2_ADDRESS 0x0000006c
+#define WLAN_LF_TIMER_COUNT2_OFFSET 0x0000006c
+#define WLAN_LF_TIMER_COUNT2_VALUE_MSB 31
+#define WLAN_LF_TIMER_COUNT2_VALUE_LSB 0
+#define WLAN_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff
+#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL2_ADDRESS 0x00000070
+#define WLAN_LF_TIMER_CONTROL2_OFFSET 0x00000070
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB 2
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB 2
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL2_RESET_MSB 0
+#define WLAN_LF_TIMER_CONTROL2_RESET_LSB 0
+#define WLAN_LF_TIMER_CONTROL2_RESET_MASK 0x00000001
+#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS2_ADDRESS 0x00000074
+#define WLAN_LF_TIMER_STATUS2_OFFSET 0x00000074
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB 0
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB 0
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define WLAN_LF_TIMER3_ADDRESS 0x00000078
+#define WLAN_LF_TIMER3_OFFSET 0x00000078
+#define WLAN_LF_TIMER3_TARGET_MSB 31
+#define WLAN_LF_TIMER3_TARGET_LSB 0
+#define WLAN_LF_TIMER3_TARGET_MASK 0xffffffff
+#define WLAN_LF_TIMER3_TARGET_GET(x) (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB)
+#define WLAN_LF_TIMER3_TARGET_SET(x) (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK)
+
+#define WLAN_LF_TIMER_COUNT3_ADDRESS 0x0000007c
+#define WLAN_LF_TIMER_COUNT3_OFFSET 0x0000007c
+#define WLAN_LF_TIMER_COUNT3_VALUE_MSB 31
+#define WLAN_LF_TIMER_COUNT3_VALUE_LSB 0
+#define WLAN_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff
+#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB)
+#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK)
+
+#define WLAN_LF_TIMER_CONTROL3_ADDRESS 0x00000080
+#define WLAN_LF_TIMER_CONTROL3_OFFSET 0x00000080
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB 2
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB 2
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB)
+#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK)
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define WLAN_LF_TIMER_CONTROL3_RESET_MSB 0
+#define WLAN_LF_TIMER_CONTROL3_RESET_LSB 0
+#define WLAN_LF_TIMER_CONTROL3_RESET_MASK 0x00000001
+#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB)
+#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK)
+
+#define WLAN_LF_TIMER_STATUS3_ADDRESS 0x00000084
+#define WLAN_LF_TIMER_STATUS3_OFFSET 0x00000084
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB 0
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB 0
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define WLAN_HF_TIMER_ADDRESS 0x00000088
+#define WLAN_HF_TIMER_OFFSET 0x00000088
+#define WLAN_HF_TIMER_TARGET_MSB 31
+#define WLAN_HF_TIMER_TARGET_LSB 12
+#define WLAN_HF_TIMER_TARGET_MASK 0xfffff000
+#define WLAN_HF_TIMER_TARGET_GET(x) (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB)
+#define WLAN_HF_TIMER_TARGET_SET(x) (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK)
+
+#define WLAN_HF_TIMER_COUNT_ADDRESS 0x0000008c
+#define WLAN_HF_TIMER_COUNT_OFFSET 0x0000008c
+#define WLAN_HF_TIMER_COUNT_VALUE_MSB 31
+#define WLAN_HF_TIMER_COUNT_VALUE_LSB 12
+#define WLAN_HF_TIMER_COUNT_VALUE_MASK 0xfffff000
+#define WLAN_HF_TIMER_COUNT_VALUE_GET(x) (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB)
+#define WLAN_HF_TIMER_COUNT_VALUE_SET(x) (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK)
+
+#define WLAN_HF_LF_COUNT_ADDRESS 0x00000090
+#define WLAN_HF_LF_COUNT_OFFSET 0x00000090
+#define WLAN_HF_LF_COUNT_VALUE_MSB 31
+#define WLAN_HF_LF_COUNT_VALUE_LSB 0
+#define WLAN_HF_LF_COUNT_VALUE_MASK 0xffffffff
+#define WLAN_HF_LF_COUNT_VALUE_GET(x) (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB)
+#define WLAN_HF_LF_COUNT_VALUE_SET(x) (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK)
+
+#define WLAN_HF_TIMER_CONTROL_ADDRESS 0x00000094
+#define WLAN_HF_TIMER_CONTROL_OFFSET 0x00000094
+#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB 3
+#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB 3
+#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008
+#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB)
+#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK)
+#define WLAN_HF_TIMER_CONTROL_ON_MSB 2
+#define WLAN_HF_TIMER_CONTROL_ON_LSB 2
+#define WLAN_HF_TIMER_CONTROL_ON_MASK 0x00000004
+#define WLAN_HF_TIMER_CONTROL_ON_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB)
+#define WLAN_HF_TIMER_CONTROL_ON_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK)
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define WLAN_HF_TIMER_CONTROL_RESET_MSB 0
+#define WLAN_HF_TIMER_CONTROL_RESET_LSB 0
+#define WLAN_HF_TIMER_CONTROL_RESET_MASK 0x00000001
+#define WLAN_HF_TIMER_CONTROL_RESET_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB)
+#define WLAN_HF_TIMER_CONTROL_RESET_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK)
+
+#define WLAN_HF_TIMER_STATUS_ADDRESS 0x00000098
+#define WLAN_HF_TIMER_STATUS_OFFSET 0x00000098
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB 0
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB 0
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB)
+#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define WLAN_RTC_CONTROL_ADDRESS 0x0000009c
+#define WLAN_RTC_CONTROL_OFFSET 0x0000009c
+#define WLAN_RTC_CONTROL_ENABLE_MSB 2
+#define WLAN_RTC_CONTROL_ENABLE_LSB 2
+#define WLAN_RTC_CONTROL_ENABLE_MASK 0x00000004
+#define WLAN_RTC_CONTROL_ENABLE_GET(x) (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB)
+#define WLAN_RTC_CONTROL_ENABLE_SET(x) (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK)
+#define WLAN_RTC_CONTROL_LOAD_RTC_MSB 1
+#define WLAN_RTC_CONTROL_LOAD_RTC_LSB 1
+#define WLAN_RTC_CONTROL_LOAD_RTC_MASK 0x00000002
+#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB)
+#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK)
+#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB 0
+#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB 0
+#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001
+#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB)
+#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define WLAN_RTC_TIME_ADDRESS 0x000000a0
+#define WLAN_RTC_TIME_OFFSET 0x000000a0
+#define WLAN_RTC_TIME_WEEK_DAY_MSB 26
+#define WLAN_RTC_TIME_WEEK_DAY_LSB 24
+#define WLAN_RTC_TIME_WEEK_DAY_MASK 0x07000000
+#define WLAN_RTC_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB)
+#define WLAN_RTC_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK)
+#define WLAN_RTC_TIME_HOUR_MSB 21
+#define WLAN_RTC_TIME_HOUR_LSB 16
+#define WLAN_RTC_TIME_HOUR_MASK 0x003f0000
+#define WLAN_RTC_TIME_HOUR_GET(x) (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB)
+#define WLAN_RTC_TIME_HOUR_SET(x) (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK)
+#define WLAN_RTC_TIME_MINUTE_MSB 14
+#define WLAN_RTC_TIME_MINUTE_LSB 8
+#define WLAN_RTC_TIME_MINUTE_MASK 0x00007f00
+#define WLAN_RTC_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB)
+#define WLAN_RTC_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK)
+#define WLAN_RTC_TIME_SECOND_MSB 6
+#define WLAN_RTC_TIME_SECOND_LSB 0
+#define WLAN_RTC_TIME_SECOND_MASK 0x0000007f
+#define WLAN_RTC_TIME_SECOND_GET(x) (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB)
+#define WLAN_RTC_TIME_SECOND_SET(x) (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK)
+
+#define WLAN_RTC_DATE_ADDRESS 0x000000a4
+#define WLAN_RTC_DATE_OFFSET 0x000000a4
+#define WLAN_RTC_DATE_YEAR_MSB 23
+#define WLAN_RTC_DATE_YEAR_LSB 16
+#define WLAN_RTC_DATE_YEAR_MASK 0x00ff0000
+#define WLAN_RTC_DATE_YEAR_GET(x) (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB)
+#define WLAN_RTC_DATE_YEAR_SET(x) (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK)
+#define WLAN_RTC_DATE_MONTH_MSB 12
+#define WLAN_RTC_DATE_MONTH_LSB 8
+#define WLAN_RTC_DATE_MONTH_MASK 0x00001f00
+#define WLAN_RTC_DATE_MONTH_GET(x) (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB)
+#define WLAN_RTC_DATE_MONTH_SET(x) (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK)
+#define WLAN_RTC_DATE_MONTH_DAY_MSB 5
+#define WLAN_RTC_DATE_MONTH_DAY_LSB 0
+#define WLAN_RTC_DATE_MONTH_DAY_MASK 0x0000003f
+#define WLAN_RTC_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB)
+#define WLAN_RTC_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK)
+
+#define WLAN_RTC_SET_TIME_ADDRESS 0x000000a8
+#define WLAN_RTC_SET_TIME_OFFSET 0x000000a8
+#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB 26
+#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB 24
+#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000
+#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB)
+#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK)
+#define WLAN_RTC_SET_TIME_HOUR_MSB 21
+#define WLAN_RTC_SET_TIME_HOUR_LSB 16
+#define WLAN_RTC_SET_TIME_HOUR_MASK 0x003f0000
+#define WLAN_RTC_SET_TIME_HOUR_GET(x) (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB)
+#define WLAN_RTC_SET_TIME_HOUR_SET(x) (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK)
+#define WLAN_RTC_SET_TIME_MINUTE_MSB 14
+#define WLAN_RTC_SET_TIME_MINUTE_LSB 8
+#define WLAN_RTC_SET_TIME_MINUTE_MASK 0x00007f00
+#define WLAN_RTC_SET_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB)
+#define WLAN_RTC_SET_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK)
+#define WLAN_RTC_SET_TIME_SECOND_MSB 6
+#define WLAN_RTC_SET_TIME_SECOND_LSB 0
+#define WLAN_RTC_SET_TIME_SECOND_MASK 0x0000007f
+#define WLAN_RTC_SET_TIME_SECOND_GET(x) (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB)
+#define WLAN_RTC_SET_TIME_SECOND_SET(x) (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK)
+
+#define WLAN_RTC_SET_DATE_ADDRESS 0x000000ac
+#define WLAN_RTC_SET_DATE_OFFSET 0x000000ac
+#define WLAN_RTC_SET_DATE_YEAR_MSB 23
+#define WLAN_RTC_SET_DATE_YEAR_LSB 16
+#define WLAN_RTC_SET_DATE_YEAR_MASK 0x00ff0000
+#define WLAN_RTC_SET_DATE_YEAR_GET(x) (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB)
+#define WLAN_RTC_SET_DATE_YEAR_SET(x) (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK)
+#define WLAN_RTC_SET_DATE_MONTH_MSB 12
+#define WLAN_RTC_SET_DATE_MONTH_LSB 8
+#define WLAN_RTC_SET_DATE_MONTH_MASK 0x00001f00
+#define WLAN_RTC_SET_DATE_MONTH_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB)
+#define WLAN_RTC_SET_DATE_MONTH_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK)
+#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB 5
+#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB 0
+#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f
+#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB)
+#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define WLAN_RTC_SET_ALARM_ADDRESS 0x000000b0
+#define WLAN_RTC_SET_ALARM_OFFSET 0x000000b0
+#define WLAN_RTC_SET_ALARM_HOUR_MSB 21
+#define WLAN_RTC_SET_ALARM_HOUR_LSB 16
+#define WLAN_RTC_SET_ALARM_HOUR_MASK 0x003f0000
+#define WLAN_RTC_SET_ALARM_HOUR_GET(x) (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB)
+#define WLAN_RTC_SET_ALARM_HOUR_SET(x) (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK)
+#define WLAN_RTC_SET_ALARM_MINUTE_MSB 14
+#define WLAN_RTC_SET_ALARM_MINUTE_LSB 8
+#define WLAN_RTC_SET_ALARM_MINUTE_MASK 0x00007f00
+#define WLAN_RTC_SET_ALARM_MINUTE_GET(x) (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB)
+#define WLAN_RTC_SET_ALARM_MINUTE_SET(x) (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK)
+#define WLAN_RTC_SET_ALARM_SECOND_MSB 6
+#define WLAN_RTC_SET_ALARM_SECOND_LSB 0
+#define WLAN_RTC_SET_ALARM_SECOND_MASK 0x0000007f
+#define WLAN_RTC_SET_ALARM_SECOND_GET(x) (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB)
+#define WLAN_RTC_SET_ALARM_SECOND_SET(x) (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK)
+
+#define WLAN_RTC_CONFIG_ADDRESS 0x000000b4
+#define WLAN_RTC_CONFIG_OFFSET 0x000000b4
+#define WLAN_RTC_CONFIG_BCD_MSB 2
+#define WLAN_RTC_CONFIG_BCD_LSB 2
+#define WLAN_RTC_CONFIG_BCD_MASK 0x00000004
+#define WLAN_RTC_CONFIG_BCD_GET(x) (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB)
+#define WLAN_RTC_CONFIG_BCD_SET(x) (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK)
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB 1
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB 1
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB)
+#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK)
+#define WLAN_RTC_CONFIG_DSE_MSB 0
+#define WLAN_RTC_CONFIG_DSE_LSB 0
+#define WLAN_RTC_CONFIG_DSE_MASK 0x00000001
+#define WLAN_RTC_CONFIG_DSE_GET(x) (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB)
+#define WLAN_RTC_CONFIG_DSE_SET(x) (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK)
+
+#define WLAN_RTC_ALARM_STATUS_ADDRESS 0x000000b8
+#define WLAN_RTC_ALARM_STATUS_OFFSET 0x000000b8
+#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB 1
+#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB 1
+#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002
+#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB)
+#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK)
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB 0
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB 0
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define WLAN_UART_WAKEUP_ADDRESS 0x000000bc
+#define WLAN_UART_WAKEUP_OFFSET 0x000000bc
+#define WLAN_UART_WAKEUP_ENABLE_MSB 0
+#define WLAN_UART_WAKEUP_ENABLE_LSB 0
+#define WLAN_UART_WAKEUP_ENABLE_MASK 0x00000001
+#define WLAN_UART_WAKEUP_ENABLE_GET(x) (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB)
+#define WLAN_UART_WAKEUP_ENABLE_SET(x) (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK)
+
+#define WLAN_RESET_CAUSE_ADDRESS 0x000000c0
+#define WLAN_RESET_CAUSE_OFFSET 0x000000c0
+#define WLAN_RESET_CAUSE_LAST_MSB 2
+#define WLAN_RESET_CAUSE_LAST_LSB 0
+#define WLAN_RESET_CAUSE_LAST_MASK 0x00000007
+#define WLAN_RESET_CAUSE_LAST_GET(x) (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB)
+#define WLAN_RESET_CAUSE_LAST_SET(x) (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK)
+
+#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4
+#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4
+#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010
+#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB)
+#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK)
+#define WLAN_SYSTEM_SLEEP_MBOX_MSB 3
+#define WLAN_SYSTEM_SLEEP_MBOX_LSB 3
+#define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008
+#define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB)
+#define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK)
+#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2
+#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2
+#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004
+#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB)
+#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK)
+#define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1
+#define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1
+#define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002
+#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB)
+#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK)
+#define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
+#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB)
+#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK)
+
+#define WLAN_SDIO_WRAPPER_ADDRESS 0x000000c8
+#define WLAN_SDIO_WRAPPER_OFFSET 0x000000c8
+#define WLAN_SDIO_WRAPPER_SLEEP_MSB 3
+#define WLAN_SDIO_WRAPPER_SLEEP_LSB 3
+#define WLAN_SDIO_WRAPPER_SLEEP_MASK 0x00000008
+#define WLAN_SDIO_WRAPPER_SLEEP_GET(x) (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB)
+#define WLAN_SDIO_WRAPPER_SLEEP_SET(x) (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK)
+#define WLAN_SDIO_WRAPPER_WAKEUP_MSB 2
+#define WLAN_SDIO_WRAPPER_WAKEUP_LSB 2
+#define WLAN_SDIO_WRAPPER_WAKEUP_MASK 0x00000004
+#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x) (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB)
+#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK)
+#define WLAN_SDIO_WRAPPER_SOC_ON_MSB 1
+#define WLAN_SDIO_WRAPPER_SOC_ON_LSB 1
+#define WLAN_SDIO_WRAPPER_SOC_ON_MASK 0x00000002
+#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB)
+#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK)
+#define WLAN_SDIO_WRAPPER_ON_MSB 0
+#define WLAN_SDIO_WRAPPER_ON_LSB 0
+#define WLAN_SDIO_WRAPPER_ON_MASK 0x00000001
+#define WLAN_SDIO_WRAPPER_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB)
+#define WLAN_SDIO_WRAPPER_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK)
+
+#define WLAN_MAC_SLEEP_CONTROL_ADDRESS 0x000000cc
+#define WLAN_MAC_SLEEP_CONTROL_OFFSET 0x000000cc
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB 1
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB 0
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB)
+#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK)
+
+#define WLAN_KEEP_AWAKE_ADDRESS 0x000000d0
+#define WLAN_KEEP_AWAKE_OFFSET 0x000000d0
+#define WLAN_KEEP_AWAKE_COUNT_MSB 7
+#define WLAN_KEEP_AWAKE_COUNT_LSB 0
+#define WLAN_KEEP_AWAKE_COUNT_MASK 0x000000ff
+#define WLAN_KEEP_AWAKE_COUNT_GET(x) (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB)
+#define WLAN_KEEP_AWAKE_COUNT_SET(x) (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK)
+
+#define WLAN_LPO_CAL_TIME_ADDRESS 0x000000d4
+#define WLAN_LPO_CAL_TIME_OFFSET 0x000000d4
+#define WLAN_LPO_CAL_TIME_LENGTH_MSB 13
+#define WLAN_LPO_CAL_TIME_LENGTH_LSB 0
+#define WLAN_LPO_CAL_TIME_LENGTH_MASK 0x00003fff
+#define WLAN_LPO_CAL_TIME_LENGTH_GET(x) (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB)
+#define WLAN_LPO_CAL_TIME_LENGTH_SET(x) (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK)
+
+#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8
+#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define WLAN_LPO_CAL_ADDRESS 0x000000e0
+#define WLAN_LPO_CAL_OFFSET 0x000000e0
+#define WLAN_LPO_CAL_ENABLE_MSB 20
+#define WLAN_LPO_CAL_ENABLE_LSB 20
+#define WLAN_LPO_CAL_ENABLE_MASK 0x00100000
+#define WLAN_LPO_CAL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB)
+#define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK)
+#define WLAN_LPO_CAL_COUNT_MSB 19
+#define WLAN_LPO_CAL_COUNT_LSB 0
+#define WLAN_LPO_CAL_COUNT_MASK 0x000fffff
+#define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB)
+#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK)
+
+#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4
+#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB 5
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB 5
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8
+#define WLAN_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8
+#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB 16
+#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB 16
+#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000
+#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB)
+#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK)
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB 15
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB 0
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define WLAN_CHIP_ID_ADDRESS 0x000000ec
+#define WLAN_CHIP_ID_OFFSET 0x000000ec
+#define WLAN_CHIP_ID_DEVICE_ID_MSB 31
+#define WLAN_CHIP_ID_DEVICE_ID_LSB 16
+#define WLAN_CHIP_ID_DEVICE_ID_MASK 0xffff0000
+#define WLAN_CHIP_ID_DEVICE_ID_GET(x) (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB)
+#define WLAN_CHIP_ID_DEVICE_ID_SET(x) (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK)
+#define WLAN_CHIP_ID_CONFIG_ID_MSB 15
+#define WLAN_CHIP_ID_CONFIG_ID_LSB 4
+#define WLAN_CHIP_ID_CONFIG_ID_MASK 0x0000fff0
+#define WLAN_CHIP_ID_CONFIG_ID_GET(x) (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB)
+#define WLAN_CHIP_ID_CONFIG_ID_SET(x) (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK)
+#define WLAN_CHIP_ID_VERSION_ID_MSB 3
+#define WLAN_CHIP_ID_VERSION_ID_LSB 0
+#define WLAN_CHIP_ID_VERSION_ID_MASK 0x0000000f
+#define WLAN_CHIP_ID_VERSION_ID_GET(x) (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB)
+#define WLAN_CHIP_ID_VERSION_ID_SET(x) (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK)
+
+#define WLAN_DERIVED_RTC_CLK_ADDRESS 0x000000f0
+#define WLAN_DERIVED_RTC_CLK_OFFSET 0x000000f0
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
+#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
+#define WLAN_DERIVED_RTC_CLK_FORCE_MSB 17
+#define WLAN_DERIVED_RTC_CLK_FORCE_LSB 16
+#define WLAN_DERIVED_RTC_CLK_FORCE_MASK 0x00030000
+#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB)
+#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK)
+#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB 15
+#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB 1
+#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe
+#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB)
+#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK)
+
+#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4
+#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB)
+#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK)
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB)
+#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK)
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB 22
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB 22
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK 0x00400000
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x) (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB)
+#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x) (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB 21
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB)
+#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK)
+#define MAC_PCU_SLP32_MODE_ENABLE_MSB 20
+#define MAC_PCU_SLP32_MODE_ENABLE_LSB 20
+#define MAC_PCU_SLP32_MODE_ENABLE_MASK 0x00100000
+#define MAC_PCU_SLP32_MODE_ENABLE_GET(x) (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB)
+#define MAC_PCU_SLP32_MODE_ENABLE_SET(x) (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
+#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
+
+#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8
+#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
+#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
+
+#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc
+#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc
+#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19
+#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0
+#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff
+#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
+#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
+
+#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100
+#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
+#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104
+#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
+#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
+
+#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108
+#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108
+#define MAC_PCU_SLP_MIB3_PENDING_MSB 1
+#define MAC_PCU_SLP_MIB3_PENDING_LSB 1
+#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002
+#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
+#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0
+#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001
+#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
+#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
+
+#define WLAN_POWER_REG_ADDRESS 0x0000010c
+#define WLAN_POWER_REG_OFFSET 0x0000010c
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB)
+#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK)
+#define WLAN_POWER_REG_DEBUG_EN_MSB 14
+#define WLAN_POWER_REG_DEBUG_EN_LSB 14
+#define WLAN_POWER_REG_DEBUG_EN_MASK 0x00004000
+#define WLAN_POWER_REG_DEBUG_EN_GET(x) (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB)
+#define WLAN_POWER_REG_DEBUG_EN_SET(x) (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK)
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB 13
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB 13
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK)
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB 12
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB 12
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK)
+#define WLAN_POWER_REG_VLVL_MSB 11
+#define WLAN_POWER_REG_VLVL_LSB 8
+#define WLAN_POWER_REG_VLVL_MASK 0x00000f00
+#define WLAN_POWER_REG_VLVL_GET(x) (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB)
+#define WLAN_POWER_REG_VLVL_SET(x) (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK)
+#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB 7
+#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB 7
+#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080
+#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB)
+#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB 6
+#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB 6
+#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040
+#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB 5
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB 5
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK)
+#define WLAN_POWER_REG_RADIO_PWD_EN_MSB 4
+#define WLAN_POWER_REG_RADIO_PWD_EN_LSB 4
+#define WLAN_POWER_REG_RADIO_PWD_EN_MASK 0x00000010
+#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB)
+#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK)
+#define WLAN_POWER_REG_SOC_ISO_EN_MSB 3
+#define WLAN_POWER_REG_SOC_ISO_EN_LSB 3
+#define WLAN_POWER_REG_SOC_ISO_EN_MASK 0x00000008
+#define WLAN_POWER_REG_SOC_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB)
+#define WLAN_POWER_REG_SOC_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK)
+#define WLAN_POWER_REG_WLAN_ISO_EN_MSB 2
+#define WLAN_POWER_REG_WLAN_ISO_EN_LSB 2
+#define WLAN_POWER_REG_WLAN_ISO_EN_MASK 0x00000004
+#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB)
+#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK)
+#define WLAN_POWER_REG_WLAN_PWD_EN_MSB 1
+#define WLAN_POWER_REG_WLAN_PWD_EN_LSB 1
+#define WLAN_POWER_REG_WLAN_PWD_EN_MASK 0x00000002
+#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB)
+#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK)
+#define WLAN_POWER_REG_POWER_EN_MSB 0
+#define WLAN_POWER_REG_POWER_EN_LSB 0
+#define WLAN_POWER_REG_POWER_EN_MASK 0x00000001
+#define WLAN_POWER_REG_POWER_EN_GET(x) (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB)
+#define WLAN_POWER_REG_POWER_EN_SET(x) (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK)
+
+#define WLAN_CORE_CLK_CTRL_ADDRESS 0x00000110
+#define WLAN_CORE_CLK_CTRL_OFFSET 0x00000110
+#define WLAN_CORE_CLK_CTRL_DIV_MSB 2
+#define WLAN_CORE_CLK_CTRL_DIV_LSB 0
+#define WLAN_CORE_CLK_CTRL_DIV_MASK 0x00000007
+#define WLAN_CORE_CLK_CTRL_DIV_GET(x) (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB)
+#define WLAN_CORE_CLK_CTRL_DIV_SET(x) (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK)
+
+#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114
+#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+#define HT_ADDRESS 0x00000118
+#define HT_OFFSET 0x00000118
+#define HT_MODE_MSB 0
+#define HT_MODE_LSB 0
+#define HT_MODE_MASK 0x00000001
+#define HT_MODE_GET(x) (((x) & HT_MODE_MASK) >> HT_MODE_LSB)
+#define HT_MODE_SET(x) (((x) << HT_MODE_LSB) & HT_MODE_MASK)
+
+#define MAC_PCU_TSF_L32_ADDRESS 0x0000011c
+#define MAC_PCU_TSF_L32_OFFSET 0x0000011c
+#define MAC_PCU_TSF_L32_VALUE_MSB 31
+#define MAC_PCU_TSF_L32_VALUE_LSB 0
+#define MAC_PCU_TSF_L32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB)
+#define MAC_PCU_TSF_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF_U32_ADDRESS 0x00000120
+#define MAC_PCU_TSF_U32_OFFSET 0x00000120
+#define MAC_PCU_TSF_U32_VALUE_MSB 31
+#define MAC_PCU_TSF_U32_VALUE_LSB 0
+#define MAC_PCU_TSF_U32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB)
+#define MAC_PCU_TSF_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK)
+
+#define MAC_PCU_WBTIMER_ADDRESS 0x00000124
+#define MAC_PCU_WBTIMER_OFFSET 0x00000124
+#define MAC_PCU_WBTIMER_VALUE_MSB 31
+#define MAC_PCU_WBTIMER_VALUE_LSB 0
+#define MAC_PCU_WBTIMER_VALUE_MASK 0xffffffff
+#define MAC_PCU_WBTIMER_VALUE_GET(x) (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB)
+#define MAC_PCU_WBTIMER_VALUE_SET(x) (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_ADDRESS 0x00000140
+#define MAC_PCU_GENERIC_TIMERS_OFFSET 0x00000140
+#define MAC_PCU_GENERIC_TIMERS_DATA_MSB 31
+#define MAC_PCU_GENERIC_TIMERS_DATA_LSB 0
+#define MAC_PCU_GENERIC_TIMERS_DATA_MASK 0xffffffff
+#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB)
+#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS 0x00000180
+#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET 0x00000180
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB 15
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB 0
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK 0x0000ffff
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS2_ADDRESS 0x000001c0
+#define MAC_PCU_GENERIC_TIMERS2_OFFSET 0x000001c0
+#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB 31
+#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB 0
+#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK 0xffffffff
+#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB)
+#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS 0x00000200
+#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET 0x00000200
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB 15
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB 0
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK)
+
+#define MAC_PCU_SLP1_ADDRESS 0x00000204
+#define MAC_PCU_SLP1_OFFSET 0x00000204
+#define MAC_PCU_SLP1_ASSUME_DTIM_MSB 19
+#define MAC_PCU_SLP1_ASSUME_DTIM_LSB 19
+#define MAC_PCU_SLP1_ASSUME_DTIM_MASK 0x00080000
+#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x) (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB)
+#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x) (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK)
+#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB 15
+#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB 0
+#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK 0x0000ffff
+#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB)
+#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK)
+
+#define MAC_PCU_SLP2_ADDRESS 0x00000208
+#define MAC_PCU_SLP2_OFFSET 0x00000208
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB 15
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB 0
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK 0x0000ffff
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB)
+#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK)
+
+#define MAC_PCU_RESET_TSF_ADDRESS 0x0000020c
+#define MAC_PCU_RESET_TSF_OFFSET 0x0000020c
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB 25
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB 25
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK 0x02000000
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB)
+#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK)
+#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB 24
+#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB 24
+#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK 0x01000000
+#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB)
+#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK)
+
+#define MAC_PCU_TSF_ADD_PLL_ADDRESS 0x00000210
+#define MAC_PCU_TSF_ADD_PLL_OFFSET 0x00000210
+#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB 7
+#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB 0
+#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK 0x000000ff
+#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x) (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB)
+#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x) (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK)
+
+#define SLEEP_RETENTION_ADDRESS 0x00000214
+#define SLEEP_RETENTION_OFFSET 0x00000214
+#define SLEEP_RETENTION_TIME_MSB 9
+#define SLEEP_RETENTION_TIME_LSB 2
+#define SLEEP_RETENTION_TIME_MASK 0x000003fc
+#define SLEEP_RETENTION_TIME_GET(x) (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB)
+#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK)
+#define SLEEP_RETENTION_MODE_MSB 1
+#define SLEEP_RETENTION_MODE_LSB 1
+#define SLEEP_RETENTION_MODE_MASK 0x00000002
+#define SLEEP_RETENTION_MODE_GET(x) (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB)
+#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK)
+#define SLEEP_RETENTION_ENABLE_MSB 0
+#define SLEEP_RETENTION_ENABLE_LSB 0
+#define SLEEP_RETENTION_ENABLE_MASK 0x00000001
+#define SLEEP_RETENTION_ENABLE_GET(x) (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB)
+#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK)
+
+#define BTCOEXCTRL_ADDRESS 0x00000218
+#define BTCOEXCTRL_OFFSET 0x00000218
+#define BTCOEXCTRL_WBTIMER_ENABLE_MSB 26
+#define BTCOEXCTRL_WBTIMER_ENABLE_LSB 26
+#define BTCOEXCTRL_WBTIMER_ENABLE_MASK 0x04000000
+#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x) (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB)
+#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x) (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK)
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB 25
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB 25
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK 0x02000000
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x) (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB)
+#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x) (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK)
+#define BTCOEXCTRL_PTA_MODE_MSB 24
+#define BTCOEXCTRL_PTA_MODE_LSB 23
+#define BTCOEXCTRL_PTA_MODE_MASK 0x01800000
+#define BTCOEXCTRL_PTA_MODE_GET(x) (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB)
+#define BTCOEXCTRL_PTA_MODE_SET(x) (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK)
+#define BTCOEXCTRL_FREQ_TIME_MSB 22
+#define BTCOEXCTRL_FREQ_TIME_LSB 18
+#define BTCOEXCTRL_FREQ_TIME_MASK 0x007c0000
+#define BTCOEXCTRL_FREQ_TIME_GET(x) (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB)
+#define BTCOEXCTRL_FREQ_TIME_SET(x) (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK)
+#define BTCOEXCTRL_PRIORITY_TIME_MSB 17
+#define BTCOEXCTRL_PRIORITY_TIME_LSB 12
+#define BTCOEXCTRL_PRIORITY_TIME_MASK 0x0003f000
+#define BTCOEXCTRL_PRIORITY_TIME_GET(x) (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB)
+#define BTCOEXCTRL_PRIORITY_TIME_SET(x) (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK)
+#define BTCOEXCTRL_SYNC_DET_EN_MSB 11
+#define BTCOEXCTRL_SYNC_DET_EN_LSB 11
+#define BTCOEXCTRL_SYNC_DET_EN_MASK 0x00000800
+#define BTCOEXCTRL_SYNC_DET_EN_GET(x) (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB)
+#define BTCOEXCTRL_SYNC_DET_EN_SET(x) (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK)
+#define BTCOEXCTRL_IDLE_CNT_EN_MSB 10
+#define BTCOEXCTRL_IDLE_CNT_EN_LSB 10
+#define BTCOEXCTRL_IDLE_CNT_EN_MASK 0x00000400
+#define BTCOEXCTRL_IDLE_CNT_EN_GET(x) (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB)
+#define BTCOEXCTRL_IDLE_CNT_EN_SET(x) (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK)
+#define BTCOEXCTRL_FRAME_CNT_EN_MSB 9
+#define BTCOEXCTRL_FRAME_CNT_EN_LSB 9
+#define BTCOEXCTRL_FRAME_CNT_EN_MASK 0x00000200
+#define BTCOEXCTRL_FRAME_CNT_EN_GET(x) (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB)
+#define BTCOEXCTRL_FRAME_CNT_EN_SET(x) (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK)
+#define BTCOEXCTRL_CLK_CNT_EN_MSB 8
+#define BTCOEXCTRL_CLK_CNT_EN_LSB 8
+#define BTCOEXCTRL_CLK_CNT_EN_MASK 0x00000100
+#define BTCOEXCTRL_CLK_CNT_EN_GET(x) (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB)
+#define BTCOEXCTRL_CLK_CNT_EN_SET(x) (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK)
+#define BTCOEXCTRL_GAP_MSB 7
+#define BTCOEXCTRL_GAP_LSB 0
+#define BTCOEXCTRL_GAP_MASK 0x000000ff
+#define BTCOEXCTRL_GAP_GET(x) (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB)
+#define BTCOEXCTRL_GAP_SET(x) (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK)
+
+#define WBSYNC_PRIORITY1_ADDRESS 0x0000021c
+#define WBSYNC_PRIORITY1_OFFSET 0x0000021c
+#define WBSYNC_PRIORITY1_BITMAP_MSB 31
+#define WBSYNC_PRIORITY1_BITMAP_LSB 0
+#define WBSYNC_PRIORITY1_BITMAP_MASK 0xffffffff
+#define WBSYNC_PRIORITY1_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB)
+#define WBSYNC_PRIORITY1_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK)
+
+#define WBSYNC_PRIORITY2_ADDRESS 0x00000220
+#define WBSYNC_PRIORITY2_OFFSET 0x00000220
+#define WBSYNC_PRIORITY2_BITMAP_MSB 31
+#define WBSYNC_PRIORITY2_BITMAP_LSB 0
+#define WBSYNC_PRIORITY2_BITMAP_MASK 0xffffffff
+#define WBSYNC_PRIORITY2_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB)
+#define WBSYNC_PRIORITY2_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK)
+
+#define WBSYNC_PRIORITY3_ADDRESS 0x00000224
+#define WBSYNC_PRIORITY3_OFFSET 0x00000224
+#define WBSYNC_PRIORITY3_BITMAP_MSB 31
+#define WBSYNC_PRIORITY3_BITMAP_LSB 0
+#define WBSYNC_PRIORITY3_BITMAP_MASK 0xffffffff
+#define WBSYNC_PRIORITY3_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB)
+#define WBSYNC_PRIORITY3_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK)
+
+#define BTCOEX0_ADDRESS 0x00000228
+#define BTCOEX0_OFFSET 0x00000228
+#define BTCOEX0_SYNC_DUR_MSB 7
+#define BTCOEX0_SYNC_DUR_LSB 0
+#define BTCOEX0_SYNC_DUR_MASK 0x000000ff
+#define BTCOEX0_SYNC_DUR_GET(x) (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB)
+#define BTCOEX0_SYNC_DUR_SET(x) (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK)
+
+#define BTCOEX1_ADDRESS 0x0000022c
+#define BTCOEX1_OFFSET 0x0000022c
+#define BTCOEX1_CLK_THRES_MSB 20
+#define BTCOEX1_CLK_THRES_LSB 0
+#define BTCOEX1_CLK_THRES_MASK 0x001fffff
+#define BTCOEX1_CLK_THRES_GET(x) (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB)
+#define BTCOEX1_CLK_THRES_SET(x) (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK)
+
+#define BTCOEX2_ADDRESS 0x00000230
+#define BTCOEX2_OFFSET 0x00000230
+#define BTCOEX2_FRAME_THRES_MSB 7
+#define BTCOEX2_FRAME_THRES_LSB 0
+#define BTCOEX2_FRAME_THRES_MASK 0x000000ff
+#define BTCOEX2_FRAME_THRES_GET(x) (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB)
+#define BTCOEX2_FRAME_THRES_SET(x) (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK)
+
+#define BTCOEX3_ADDRESS 0x00000234
+#define BTCOEX3_OFFSET 0x00000234
+#define BTCOEX3_CLK_CNT_MSB 20
+#define BTCOEX3_CLK_CNT_LSB 0
+#define BTCOEX3_CLK_CNT_MASK 0x001fffff
+#define BTCOEX3_CLK_CNT_GET(x) (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB)
+#define BTCOEX3_CLK_CNT_SET(x) (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK)
+
+#define BTCOEX4_ADDRESS 0x00000238
+#define BTCOEX4_OFFSET 0x00000238
+#define BTCOEX4_FRAME_CNT_MSB 7
+#define BTCOEX4_FRAME_CNT_LSB 0
+#define BTCOEX4_FRAME_CNT_MASK 0x000000ff
+#define BTCOEX4_FRAME_CNT_GET(x) (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB)
+#define BTCOEX4_FRAME_CNT_SET(x) (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK)
+
+#define BTCOEX5_ADDRESS 0x0000023c
+#define BTCOEX5_OFFSET 0x0000023c
+#define BTCOEX5_IDLE_CNT_MSB 15
+#define BTCOEX5_IDLE_CNT_LSB 0
+#define BTCOEX5_IDLE_CNT_MASK 0x0000ffff
+#define BTCOEX5_IDLE_CNT_GET(x) (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB)
+#define BTCOEX5_IDLE_CNT_SET(x) (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK)
+
+#define BTCOEX6_ADDRESS 0x00000240
+#define BTCOEX6_OFFSET 0x00000240
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB 31
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB 0
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK 0xffffffff
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x) (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB)
+#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x) (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK)
+
+#define LOCK_ADDRESS 0x00000244
+#define LOCK_OFFSET 0x00000244
+#define LOCK_TLOCK_SLAVE_MSB 31
+#define LOCK_TLOCK_SLAVE_LSB 24
+#define LOCK_TLOCK_SLAVE_MASK 0xff000000
+#define LOCK_TLOCK_SLAVE_GET(x) (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB)
+#define LOCK_TLOCK_SLAVE_SET(x) (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK)
+#define LOCK_TUNLOCK_SLAVE_MSB 23
+#define LOCK_TUNLOCK_SLAVE_LSB 16
+#define LOCK_TUNLOCK_SLAVE_MASK 0x00ff0000
+#define LOCK_TUNLOCK_SLAVE_GET(x) (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB)
+#define LOCK_TUNLOCK_SLAVE_SET(x) (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK)
+#define LOCK_TLOCK_MASTER_MSB 15
+#define LOCK_TLOCK_MASTER_LSB 8
+#define LOCK_TLOCK_MASTER_MASK 0x0000ff00
+#define LOCK_TLOCK_MASTER_GET(x) (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB)
+#define LOCK_TLOCK_MASTER_SET(x) (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK)
+#define LOCK_TUNLOCK_MASTER_MSB 7
+#define LOCK_TUNLOCK_MASTER_LSB 0
+#define LOCK_TUNLOCK_MASTER_MASK 0x000000ff
+#define LOCK_TUNLOCK_MASTER_GET(x) (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB)
+#define LOCK_TUNLOCK_MASTER_SET(x) (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK)
+
+#define NOLOCK_PRIORITY_ADDRESS 0x00000248
+#define NOLOCK_PRIORITY_OFFSET 0x00000248
+#define NOLOCK_PRIORITY_BITMAP_MSB 31
+#define NOLOCK_PRIORITY_BITMAP_LSB 0
+#define NOLOCK_PRIORITY_BITMAP_MASK 0xffffffff
+#define NOLOCK_PRIORITY_BITMAP_GET(x) (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB)
+#define NOLOCK_PRIORITY_BITMAP_SET(x) (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK)
+
+#define WBSYNC_ADDRESS 0x0000024c
+#define WBSYNC_OFFSET 0x0000024c
+#define WBSYNC_BTCLOCK_MSB 31
+#define WBSYNC_BTCLOCK_LSB 0
+#define WBSYNC_BTCLOCK_MASK 0xffffffff
+#define WBSYNC_BTCLOCK_GET(x) (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB)
+#define WBSYNC_BTCLOCK_SET(x) (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK)
+
+#define WBSYNC1_ADDRESS 0x00000250
+#define WBSYNC1_OFFSET 0x00000250
+#define WBSYNC1_BTCLOCK_MSB 31
+#define WBSYNC1_BTCLOCK_LSB 0
+#define WBSYNC1_BTCLOCK_MASK 0xffffffff
+#define WBSYNC1_BTCLOCK_GET(x) (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB)
+#define WBSYNC1_BTCLOCK_SET(x) (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK)
+
+#define WBSYNC2_ADDRESS 0x00000254
+#define WBSYNC2_OFFSET 0x00000254
+#define WBSYNC2_BTCLOCK_MSB 31
+#define WBSYNC2_BTCLOCK_LSB 0
+#define WBSYNC2_BTCLOCK_MASK 0xffffffff
+#define WBSYNC2_BTCLOCK_GET(x) (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB)
+#define WBSYNC2_BTCLOCK_SET(x) (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK)
+
+#define WBSYNC3_ADDRESS 0x00000258
+#define WBSYNC3_OFFSET 0x00000258
+#define WBSYNC3_BTCLOCK_MSB 31
+#define WBSYNC3_BTCLOCK_LSB 0
+#define WBSYNC3_BTCLOCK_MASK 0xffffffff
+#define WBSYNC3_BTCLOCK_GET(x) (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB)
+#define WBSYNC3_BTCLOCK_SET(x) (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK)
+
+#define WB_TIMER_TARGET_ADDRESS 0x0000025c
+#define WB_TIMER_TARGET_OFFSET 0x0000025c
+#define WB_TIMER_TARGET_VALUE_MSB 31
+#define WB_TIMER_TARGET_VALUE_LSB 0
+#define WB_TIMER_TARGET_VALUE_MASK 0xffffffff
+#define WB_TIMER_TARGET_VALUE_GET(x) (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB)
+#define WB_TIMER_TARGET_VALUE_SET(x) (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK)
+
+#define WB_TIMER_SLOP_ADDRESS 0x00000260
+#define WB_TIMER_SLOP_OFFSET 0x00000260
+#define WB_TIMER_SLOP_VALUE_MSB 9
+#define WB_TIMER_SLOP_VALUE_LSB 0
+#define WB_TIMER_SLOP_VALUE_MASK 0x000003ff
+#define WB_TIMER_SLOP_VALUE_GET(x) (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB)
+#define WB_TIMER_SLOP_VALUE_SET(x) (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK)
+
+#define BTCOEX_INT_EN_ADDRESS 0x00000264
+#define BTCOEX_INT_EN_OFFSET 0x00000264
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB 11
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB 11
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK 0x00000800
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB)
+#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK)
+#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB 10
+#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB 10
+#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK 0x00000400
+#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB)
+#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK)
+#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB 9
+#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB 9
+#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK 0x00000200
+#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB)
+#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK)
+#define BTCOEX_INT_EN_ST_MESG_RECV_MSB 8
+#define BTCOEX_INT_EN_ST_MESG_RECV_LSB 8
+#define BTCOEX_INT_EN_ST_MESG_RECV_MASK 0x00000100
+#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x) (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB)
+#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x) (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK)
+#define BTCOEX_INT_EN_WB_TIMER_MSB 7
+#define BTCOEX_INT_EN_WB_TIMER_LSB 7
+#define BTCOEX_INT_EN_WB_TIMER_MASK 0x00000080
+#define BTCOEX_INT_EN_WB_TIMER_GET(x) (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB)
+#define BTCOEX_INT_EN_WB_TIMER_SET(x) (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK)
+#define BTCOEX_INT_EN_NOSYNC_MSB 4
+#define BTCOEX_INT_EN_NOSYNC_LSB 4
+#define BTCOEX_INT_EN_NOSYNC_MASK 0x00000010
+#define BTCOEX_INT_EN_NOSYNC_GET(x) (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB)
+#define BTCOEX_INT_EN_NOSYNC_SET(x) (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK)
+#define BTCOEX_INT_EN_SYNC_MSB 3
+#define BTCOEX_INT_EN_SYNC_LSB 3
+#define BTCOEX_INT_EN_SYNC_MASK 0x00000008
+#define BTCOEX_INT_EN_SYNC_GET(x) (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB)
+#define BTCOEX_INT_EN_SYNC_SET(x) (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK)
+#define BTCOEX_INT_EN_END_MSB 2
+#define BTCOEX_INT_EN_END_LSB 2
+#define BTCOEX_INT_EN_END_MASK 0x00000004
+#define BTCOEX_INT_EN_END_GET(x) (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB)
+#define BTCOEX_INT_EN_END_SET(x) (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK)
+#define BTCOEX_INT_EN_FRAME_CNT_MSB 1
+#define BTCOEX_INT_EN_FRAME_CNT_LSB 1
+#define BTCOEX_INT_EN_FRAME_CNT_MASK 0x00000002
+#define BTCOEX_INT_EN_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB)
+#define BTCOEX_INT_EN_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK)
+#define BTCOEX_INT_EN_CLK_CNT_MSB 0
+#define BTCOEX_INT_EN_CLK_CNT_LSB 0
+#define BTCOEX_INT_EN_CLK_CNT_MASK 0x00000001
+#define BTCOEX_INT_EN_CLK_CNT_GET(x) (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB)
+#define BTCOEX_INT_EN_CLK_CNT_SET(x) (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK)
+
+#define BTCOEX_INT_STAT_ADDRESS 0x00000268
+#define BTCOEX_INT_STAT_OFFSET 0x00000268
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB 11
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB 11
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK 0x00000800
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB)
+#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK)
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB 10
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB 10
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK 0x00000400
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB)
+#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK)
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB 9
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB 9
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK 0x00000200
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB)
+#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK)
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB 8
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB 8
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK 0x00000100
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB)
+#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK)
+#define BTCOEX_INT_STAT_WB_TIMER_MSB 7
+#define BTCOEX_INT_STAT_WB_TIMER_LSB 7
+#define BTCOEX_INT_STAT_WB_TIMER_MASK 0x00000080
+#define BTCOEX_INT_STAT_WB_TIMER_GET(x) (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB)
+#define BTCOEX_INT_STAT_WB_TIMER_SET(x) (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK)
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB 6
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB 6
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK 0x00000040
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB)
+#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK)
+#define BTCOEX_INT_STAT_BTPRIORITY_MSB 5
+#define BTCOEX_INT_STAT_BTPRIORITY_LSB 5
+#define BTCOEX_INT_STAT_BTPRIORITY_MASK 0x00000020
+#define BTCOEX_INT_STAT_BTPRIORITY_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB)
+#define BTCOEX_INT_STAT_BTPRIORITY_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK)
+#define BTCOEX_INT_STAT_NOSYNC_MSB 4
+#define BTCOEX_INT_STAT_NOSYNC_LSB 4
+#define BTCOEX_INT_STAT_NOSYNC_MASK 0x00000010
+#define BTCOEX_INT_STAT_NOSYNC_GET(x) (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB)
+#define BTCOEX_INT_STAT_NOSYNC_SET(x) (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK)
+#define BTCOEX_INT_STAT_SYNC_MSB 3
+#define BTCOEX_INT_STAT_SYNC_LSB 3
+#define BTCOEX_INT_STAT_SYNC_MASK 0x00000008
+#define BTCOEX_INT_STAT_SYNC_GET(x) (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB)
+#define BTCOEX_INT_STAT_SYNC_SET(x) (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK)
+#define BTCOEX_INT_STAT_END_MSB 2
+#define BTCOEX_INT_STAT_END_LSB 2
+#define BTCOEX_INT_STAT_END_MASK 0x00000004
+#define BTCOEX_INT_STAT_END_GET(x) (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB)
+#define BTCOEX_INT_STAT_END_SET(x) (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK)
+#define BTCOEX_INT_STAT_FRAME_CNT_MSB 1
+#define BTCOEX_INT_STAT_FRAME_CNT_LSB 1
+#define BTCOEX_INT_STAT_FRAME_CNT_MASK 0x00000002
+#define BTCOEX_INT_STAT_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB)
+#define BTCOEX_INT_STAT_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK)
+#define BTCOEX_INT_STAT_CLK_CNT_MSB 0
+#define BTCOEX_INT_STAT_CLK_CNT_LSB 0
+#define BTCOEX_INT_STAT_CLK_CNT_MASK 0x00000001
+#define BTCOEX_INT_STAT_CLK_CNT_GET(x) (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB)
+#define BTCOEX_INT_STAT_CLK_CNT_SET(x) (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK)
+
+#define BTPRIORITY_INT_EN_ADDRESS 0x0000026c
+#define BTPRIORITY_INT_EN_OFFSET 0x0000026c
+#define BTPRIORITY_INT_EN_BITMAP_MSB 31
+#define BTPRIORITY_INT_EN_BITMAP_LSB 0
+#define BTPRIORITY_INT_EN_BITMAP_MASK 0xffffffff
+#define BTPRIORITY_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB)
+#define BTPRIORITY_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK)
+
+#define BTPRIORITY_INT_STAT_ADDRESS 0x00000270
+#define BTPRIORITY_INT_STAT_OFFSET 0x00000270
+#define BTPRIORITY_INT_STAT_BITMAP_MSB 31
+#define BTPRIORITY_INT_STAT_BITMAP_LSB 0
+#define BTPRIORITY_INT_STAT_BITMAP_MASK 0xffffffff
+#define BTPRIORITY_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB)
+#define BTPRIORITY_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK)
+
+#define BTPRIORITY_STOMP_INT_EN_ADDRESS 0x00000274
+#define BTPRIORITY_STOMP_INT_EN_OFFSET 0x00000274
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB 31
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB 0
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK 0xffffffff
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB)
+#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK)
+
+#define BTPRIORITY_STOMP_INT_STAT_ADDRESS 0x00000278
+#define BTPRIORITY_STOMP_INT_STAT_OFFSET 0x00000278
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB 31
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB 0
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK 0xffffffff
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB)
+#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK)
+
+#define MAC_PCU_BMISS_TIMEOUT_ADDRESS 0x0000027c
+#define MAC_PCU_BMISS_TIMEOUT_OFFSET 0x0000027c
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB 24
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB 24
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB)
+#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK)
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB 23
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB 0
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK 0x00ffffff
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB)
+#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK)
+
+#define MAC_PCU_CAB_AWAKE_ADDRESS 0x00000280
+#define MAC_PCU_CAB_AWAKE_OFFSET 0x00000280
+#define MAC_PCU_CAB_AWAKE_ENABLE_MSB 16
+#define MAC_PCU_CAB_AWAKE_ENABLE_LSB 16
+#define MAC_PCU_CAB_AWAKE_ENABLE_MASK 0x00010000
+#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x) (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB)
+#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x) (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK)
+#define MAC_PCU_CAB_AWAKE_DURATION_MSB 15
+#define MAC_PCU_CAB_AWAKE_DURATION_LSB 0
+#define MAC_PCU_CAB_AWAKE_DURATION_MASK 0x0000ffff
+#define MAC_PCU_CAB_AWAKE_DURATION_GET(x) (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB)
+#define MAC_PCU_CAB_AWAKE_DURATION_SET(x) (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK)
+
+#define LP_PERF_COUNTER_ADDRESS 0x00000284
+#define LP_PERF_COUNTER_OFFSET 0x00000284
+#define LP_PERF_COUNTER_EN_MSB 0
+#define LP_PERF_COUNTER_EN_LSB 0
+#define LP_PERF_COUNTER_EN_MASK 0x00000001
+#define LP_PERF_COUNTER_EN_GET(x) (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB)
+#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK)
+
+#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288
+#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288
+#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31
+#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0
+#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff
+#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB)
+#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK)
+
+#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c
+#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c
+#define LP_PERF_DEEP_SLEEP_CNT_MSB 31
+#define LP_PERF_DEEP_SLEEP_CNT_LSB 0
+#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff
+#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB)
+#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK)
+
+#define LP_PERF_ON_ADDRESS 0x00000290
+#define LP_PERF_ON_OFFSET 0x00000290
+#define LP_PERF_ON_CNT_MSB 31
+#define LP_PERF_ON_CNT_LSB 0
+#define LP_PERF_ON_CNT_MASK 0xffffffff
+#define LP_PERF_ON_CNT_GET(x) (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB)
+#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK)
+
+#define ST_64_BIT_ADDRESS 0x00000294
+#define ST_64_BIT_OFFSET 0x00000294
+#define ST_64_BIT_TIMEOUT_MSB 26
+#define ST_64_BIT_TIMEOUT_LSB 9
+#define ST_64_BIT_TIMEOUT_MASK 0x07fffe00
+#define ST_64_BIT_TIMEOUT_GET(x) (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB)
+#define ST_64_BIT_TIMEOUT_SET(x) (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK)
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB 8
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB 8
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK 0x00000100
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB)
+#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK)
+#define ST_64_BIT_DRIVE_MODE_MSB 7
+#define ST_64_BIT_DRIVE_MODE_LSB 7
+#define ST_64_BIT_DRIVE_MODE_MASK 0x00000080
+#define ST_64_BIT_DRIVE_MODE_GET(x) (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB)
+#define ST_64_BIT_DRIVE_MODE_SET(x) (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK)
+#define ST_64_BIT_CLOCK_GATE_MSB 6
+#define ST_64_BIT_CLOCK_GATE_LSB 6
+#define ST_64_BIT_CLOCK_GATE_MASK 0x00000040
+#define ST_64_BIT_CLOCK_GATE_GET(x) (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB)
+#define ST_64_BIT_CLOCK_GATE_SET(x) (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK)
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB 5
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB 1
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK 0x0000003e
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x) (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB)
+#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x) (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK)
+#define ST_64_BIT_MODE_MSB 0
+#define ST_64_BIT_MODE_LSB 0
+#define ST_64_BIT_MODE_MASK 0x00000001
+#define ST_64_BIT_MODE_GET(x) (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB)
+#define ST_64_BIT_MODE_SET(x) (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK)
+
+#define MESSAGE_WR_ADDRESS 0x00000298
+#define MESSAGE_WR_OFFSET 0x00000298
+#define MESSAGE_WR_TYPE_MSB 31
+#define MESSAGE_WR_TYPE_LSB 0
+#define MESSAGE_WR_TYPE_MASK 0xffffffff
+#define MESSAGE_WR_TYPE_GET(x) (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB)
+#define MESSAGE_WR_TYPE_SET(x) (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK)
+
+#define MESSAGE_WR_P_ADDRESS 0x0000029c
+#define MESSAGE_WR_P_OFFSET 0x0000029c
+#define MESSAGE_WR_P_PARAMETER_MSB 31
+#define MESSAGE_WR_P_PARAMETER_LSB 0
+#define MESSAGE_WR_P_PARAMETER_MASK 0xffffffff
+#define MESSAGE_WR_P_PARAMETER_GET(x) (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB)
+#define MESSAGE_WR_P_PARAMETER_SET(x) (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK)
+
+#define MESSAGE_RD_ADDRESS 0x000002a0
+#define MESSAGE_RD_OFFSET 0x000002a0
+#define MESSAGE_RD_TYPE_MSB 31
+#define MESSAGE_RD_TYPE_LSB 0
+#define MESSAGE_RD_TYPE_MASK 0xffffffff
+#define MESSAGE_RD_TYPE_GET(x) (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB)
+#define MESSAGE_RD_TYPE_SET(x) (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK)
+
+#define MESSAGE_RD_P_ADDRESS 0x000002a4
+#define MESSAGE_RD_P_OFFSET 0x000002a4
+#define MESSAGE_RD_P_PARAMETER_MSB 31
+#define MESSAGE_RD_P_PARAMETER_LSB 0
+#define MESSAGE_RD_P_PARAMETER_MASK 0xffffffff
+#define MESSAGE_RD_P_PARAMETER_GET(x) (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB)
+#define MESSAGE_RD_P_PARAMETER_SET(x) (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK)
+
+#define CHIP_MODE_ADDRESS 0x000002a8
+#define CHIP_MODE_OFFSET 0x000002a8
+#define CHIP_MODE_BIT_MSB 1
+#define CHIP_MODE_BIT_LSB 0
+#define CHIP_MODE_BIT_MASK 0x00000003
+#define CHIP_MODE_BIT_GET(x) (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB)
+#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK)
+
+#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac
+#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac
+#define CLK_REQ_FALL_EDGE_EN_MSB 31
+#define CLK_REQ_FALL_EDGE_EN_LSB 31
+#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000
+#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB)
+#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK)
+#define CLK_REQ_FALL_EDGE_DELAY_MSB 7
+#define CLK_REQ_FALL_EDGE_DELAY_LSB 0
+#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff
+#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB)
+#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK)
+
+#define OTP_ADDRESS 0x000002b0
+#define OTP_OFFSET 0x000002b0
+#define OTP_LDO25_EN_MSB 1
+#define OTP_LDO25_EN_LSB 1
+#define OTP_LDO25_EN_MASK 0x00000002
+#define OTP_LDO25_EN_GET(x) (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB)
+#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK)
+#define OTP_VDD12_EN_MSB 0
+#define OTP_VDD12_EN_LSB 0
+#define OTP_VDD12_EN_MASK 0x00000001
+#define OTP_VDD12_EN_GET(x) (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB)
+#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK)
+
+#define OTP_STATUS_ADDRESS 0x000002b4
+#define OTP_STATUS_OFFSET 0x000002b4
+#define OTP_STATUS_LDO25_EN_READY_MSB 1
+#define OTP_STATUS_LDO25_EN_READY_LSB 1
+#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002
+#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB)
+#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK)
+#define OTP_STATUS_VDD12_EN_READY_MSB 0
+#define OTP_STATUS_VDD12_EN_READY_LSB 0
+#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001
+#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB)
+#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK)
+
+#define PMU_ADDRESS 0x000002b8
+#define PMU_OFFSET 0x000002b8
+#define PMU_REG_WAKEUP_TIME_SEL_MSB 1
+#define PMU_REG_WAKEUP_TIME_SEL_LSB 0
+#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003
+#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB)
+#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK)
+
+#define PMU_CONFIG_ADDRESS 0x000002c0
+#define PMU_CONFIG_OFFSET 0x000002c0
+#define PMU_CONFIG_VALUE_MSB 15
+#define PMU_CONFIG_VALUE_LSB 0
+#define PMU_CONFIG_VALUE_MASK 0x0000ffff
+#define PMU_CONFIG_VALUE_GET(x) (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB)
+#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK)
+
+#define PMU_BYPASS_ADDRESS 0x000002c8
+#define PMU_BYPASS_OFFSET 0x000002c8
+#define PMU_BYPASS_SWREG_MSB 2
+#define PMU_BYPASS_SWREG_LSB 2
+#define PMU_BYPASS_SWREG_MASK 0x00000004
+#define PMU_BYPASS_SWREG_GET(x) (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB)
+#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK)
+#define PMU_BYPASS_DREG_MSB 1
+#define PMU_BYPASS_DREG_LSB 1
+#define PMU_BYPASS_DREG_MASK 0x00000002
+#define PMU_BYPASS_DREG_GET(x) (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB)
+#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK)
+#define PMU_BYPASS_PAREG_MSB 0
+#define PMU_BYPASS_PAREG_LSB 0
+#define PMU_BYPASS_PAREG_MASK 0x00000001
+#define PMU_BYPASS_PAREG_GET(x) (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB)
+#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK)
+
+#define MAC_PCU_TSF2_L32_ADDRESS 0x000002cc
+#define MAC_PCU_TSF2_L32_OFFSET 0x000002cc
+#define MAC_PCU_TSF2_L32_VALUE_MSB 31
+#define MAC_PCU_TSF2_L32_VALUE_LSB 0
+#define MAC_PCU_TSF2_L32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF2_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB)
+#define MAC_PCU_TSF2_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK)
+
+#define MAC_PCU_TSF2_U32_ADDRESS 0x000002d0
+#define MAC_PCU_TSF2_U32_OFFSET 0x000002d0
+#define MAC_PCU_TSF2_U32_VALUE_MSB 31
+#define MAC_PCU_TSF2_U32_VALUE_LSB 0
+#define MAC_PCU_TSF2_U32_VALUE_MASK 0xffffffff
+#define MAC_PCU_TSF2_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB)
+#define MAC_PCU_TSF2_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK)
+
+#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS 0x000002d4
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET 0x000002d4
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB 19
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB 0
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB)
+#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK)
+
+#define MAC_PCU_DIRECT_CONNECT_ADDRESS 0x000002d8
+#define MAC_PCU_DIRECT_CONNECT_OFFSET 0x000002d8
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB)
+#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK)
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB)
+#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK)
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB)
+#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK)
+
+#define THERM_CTRL1_ADDRESS 0x000002dc
+#define THERM_CTRL1_OFFSET 0x000002dc
+#define THERM_CTRL1_BYPASS_MSB 16
+#define THERM_CTRL1_BYPASS_LSB 16
+#define THERM_CTRL1_BYPASS_MASK 0x00010000
+#define THERM_CTRL1_BYPASS_GET(x) (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB)
+#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK)
+#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15
+#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12
+#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000
+#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB)
+#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK)
+#define THERM_CTRL1_WIDTH_MSB 11
+#define THERM_CTRL1_WIDTH_LSB 5
+#define THERM_CTRL1_WIDTH_MASK 0x00000fe0
+#define THERM_CTRL1_WIDTH_GET(x) (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB)
+#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK)
+#define THERM_CTRL1_TYPE_MSB 4
+#define THERM_CTRL1_TYPE_LSB 3
+#define THERM_CTRL1_TYPE_MASK 0x00000018
+#define THERM_CTRL1_TYPE_GET(x) (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB)
+#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK)
+#define THERM_CTRL1_MEASURE_MSB 2
+#define THERM_CTRL1_MEASURE_LSB 2
+#define THERM_CTRL1_MEASURE_MASK 0x00000004
+#define THERM_CTRL1_MEASURE_GET(x) (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB)
+#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK)
+#define THERM_CTRL1_INT_EN_MSB 1
+#define THERM_CTRL1_INT_EN_LSB 1
+#define THERM_CTRL1_INT_EN_MASK 0x00000002
+#define THERM_CTRL1_INT_EN_GET(x) (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB)
+#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK)
+#define THERM_CTRL1_INT_STATUS_MSB 0
+#define THERM_CTRL1_INT_STATUS_LSB 0
+#define THERM_CTRL1_INT_STATUS_MASK 0x00000001
+#define THERM_CTRL1_INT_STATUS_GET(x) (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB)
+#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK)
+
+#define THERM_CTRL2_ADDRESS 0x000002e0
+#define THERM_CTRL2_OFFSET 0x000002e0
+#define THERM_CTRL2_ADC_OFF_MSB 25
+#define THERM_CTRL2_ADC_OFF_LSB 25
+#define THERM_CTRL2_ADC_OFF_MASK 0x02000000
+#define THERM_CTRL2_ADC_OFF_GET(x) (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB)
+#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK)
+#define THERM_CTRL2_ADC_ON_MSB 24
+#define THERM_CTRL2_ADC_ON_LSB 24
+#define THERM_CTRL2_ADC_ON_MASK 0x01000000
+#define THERM_CTRL2_ADC_ON_GET(x) (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB)
+#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK)
+#define THERM_CTRL2_SAMPLE_MSB 23
+#define THERM_CTRL2_SAMPLE_LSB 16
+#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000
+#define THERM_CTRL2_SAMPLE_GET(x) (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB)
+#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK)
+#define THERM_CTRL2_HIGH_MSB 15
+#define THERM_CTRL2_HIGH_LSB 8
+#define THERM_CTRL2_HIGH_MASK 0x0000ff00
+#define THERM_CTRL2_HIGH_GET(x) (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB)
+#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK)
+#define THERM_CTRL2_LOW_MSB 7
+#define THERM_CTRL2_LOW_LSB 0
+#define THERM_CTRL2_LOW_MASK 0x000000ff
+#define THERM_CTRL2_LOW_GET(x) (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB)
+#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK)
+
+#define THERM_CTRL3_ADDRESS 0x000002e4
+#define THERM_CTRL3_OFFSET 0x000002e4
+#define THERM_CTRL3_ADC_GAIN_MSB 16
+#define THERM_CTRL3_ADC_GAIN_LSB 8
+#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00
+#define THERM_CTRL3_ADC_GAIN_GET(x) (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB)
+#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK)
+#define THERM_CTRL3_ADC_OFFSET_MSB 7
+#define THERM_CTRL3_ADC_OFFSET_LSB 0
+#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff
+#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB)
+#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct rtc_wlan_reg_reg_s {
+ volatile unsigned int wlan_reset_control;
+ volatile unsigned int wlan_xtal_control;
+ volatile unsigned int wlan_tcxo_detect;
+ volatile unsigned int wlan_xtal_test;
+ volatile unsigned int wlan_quadrature;
+ volatile unsigned int wlan_pll_control;
+ volatile unsigned int wlan_pll_settle;
+ volatile unsigned int wlan_xtal_settle;
+ volatile unsigned int wlan_cpu_clock;
+ volatile unsigned int wlan_clock_out;
+ volatile unsigned int wlan_clock_control;
+ volatile unsigned int wlan_bias_override;
+ volatile unsigned int wlan_wdt_control;
+ volatile unsigned int wlan_wdt_status;
+ volatile unsigned int wlan_wdt;
+ volatile unsigned int wlan_wdt_count;
+ volatile unsigned int wlan_wdt_reset;
+ volatile unsigned int wlan_int_status;
+ volatile unsigned int wlan_lf_timer0;
+ volatile unsigned int wlan_lf_timer_count0;
+ volatile unsigned int wlan_lf_timer_control0;
+ volatile unsigned int wlan_lf_timer_status0;
+ volatile unsigned int wlan_lf_timer1;
+ volatile unsigned int wlan_lf_timer_count1;
+ volatile unsigned int wlan_lf_timer_control1;
+ volatile unsigned int wlan_lf_timer_status1;
+ volatile unsigned int wlan_lf_timer2;
+ volatile unsigned int wlan_lf_timer_count2;
+ volatile unsigned int wlan_lf_timer_control2;
+ volatile unsigned int wlan_lf_timer_status2;
+ volatile unsigned int wlan_lf_timer3;
+ volatile unsigned int wlan_lf_timer_count3;
+ volatile unsigned int wlan_lf_timer_control3;
+ volatile unsigned int wlan_lf_timer_status3;
+ volatile unsigned int wlan_hf_timer;
+ volatile unsigned int wlan_hf_timer_count;
+ volatile unsigned int wlan_hf_lf_count;
+ volatile unsigned int wlan_hf_timer_control;
+ volatile unsigned int wlan_hf_timer_status;
+ volatile unsigned int wlan_rtc_control;
+ volatile unsigned int wlan_rtc_time;
+ volatile unsigned int wlan_rtc_date;
+ volatile unsigned int wlan_rtc_set_time;
+ volatile unsigned int wlan_rtc_set_date;
+ volatile unsigned int wlan_rtc_set_alarm;
+ volatile unsigned int wlan_rtc_config;
+ volatile unsigned int wlan_rtc_alarm_status;
+ volatile unsigned int wlan_uart_wakeup;
+ volatile unsigned int wlan_reset_cause;
+ volatile unsigned int wlan_system_sleep;
+ volatile unsigned int wlan_sdio_wrapper;
+ volatile unsigned int wlan_mac_sleep_control;
+ volatile unsigned int wlan_keep_awake;
+ volatile unsigned int wlan_lpo_cal_time;
+ volatile unsigned int wlan_lpo_init_dividend_int;
+ volatile unsigned int wlan_lpo_init_dividend_fraction;
+ volatile unsigned int wlan_lpo_cal;
+ volatile unsigned int wlan_lpo_cal_test_control;
+ volatile unsigned int wlan_lpo_cal_test_status;
+ volatile unsigned int wlan_chip_id;
+ volatile unsigned int wlan_derived_rtc_clk;
+ volatile unsigned int mac_pcu_slp32_mode;
+ volatile unsigned int mac_pcu_slp32_wake;
+ volatile unsigned int mac_pcu_slp32_inc;
+ volatile unsigned int mac_pcu_slp_mib1;
+ volatile unsigned int mac_pcu_slp_mib2;
+ volatile unsigned int mac_pcu_slp_mib3;
+ volatile unsigned int wlan_power_reg;
+ volatile unsigned int wlan_core_clk_ctrl;
+ volatile unsigned int wlan_gpio_wakeup_control;
+ volatile unsigned int ht;
+ volatile unsigned int mac_pcu_tsf_l32;
+ volatile unsigned int mac_pcu_tsf_u32;
+ volatile unsigned int mac_pcu_wbtimer;
+ unsigned char pad0[24]; /* pad to 0x140 */
+ volatile unsigned int mac_pcu_generic_timers[16];
+ volatile unsigned int mac_pcu_generic_timers_mode;
+ unsigned char pad1[60]; /* pad to 0x1c0 */
+ volatile unsigned int mac_pcu_generic_timers2[16];
+ volatile unsigned int mac_pcu_generic_timers_mode2;
+ volatile unsigned int mac_pcu_slp1;
+ volatile unsigned int mac_pcu_slp2;
+ volatile unsigned int mac_pcu_reset_tsf;
+ volatile unsigned int mac_pcu_tsf_add_pll;
+ volatile unsigned int sleep_retention;
+ volatile unsigned int btcoexctrl;
+ volatile unsigned int wbsync_priority1;
+ volatile unsigned int wbsync_priority2;
+ volatile unsigned int wbsync_priority3;
+ volatile unsigned int btcoex0;
+ volatile unsigned int btcoex1;
+ volatile unsigned int btcoex2;
+ volatile unsigned int btcoex3;
+ volatile unsigned int btcoex4;
+ volatile unsigned int btcoex5;
+ volatile unsigned int btcoex6;
+ volatile unsigned int lock;
+ volatile unsigned int nolock_priority;
+ volatile unsigned int wbsync;
+ volatile unsigned int wbsync1;
+ volatile unsigned int wbsync2;
+ volatile unsigned int wbsync3;
+ volatile unsigned int wb_timer_target;
+ volatile unsigned int wb_timer_slop;
+ volatile unsigned int btcoex_int_en;
+ volatile unsigned int btcoex_int_stat;
+ volatile unsigned int btpriority_int_en;
+ volatile unsigned int btpriority_int_stat;
+ volatile unsigned int btpriority_stomp_int_en;
+ volatile unsigned int btpriority_stomp_int_stat;
+ volatile unsigned int mac_pcu_bmiss_timeout;
+ volatile unsigned int mac_pcu_cab_awake;
+ volatile unsigned int lp_perf_counter;
+ volatile unsigned int lp_perf_light_sleep;
+ volatile unsigned int lp_perf_deep_sleep;
+ volatile unsigned int lp_perf_on;
+ volatile unsigned int st_64_bit;
+ volatile unsigned int message_wr;
+ volatile unsigned int message_wr_p;
+ volatile unsigned int message_rd;
+ volatile unsigned int message_rd_p;
+ volatile unsigned int chip_mode;
+ volatile unsigned int clk_req_fall_edge;
+ volatile unsigned int otp;
+ volatile unsigned int otp_status;
+ volatile unsigned int pmu;
+ unsigned char pad2[4]; /* pad to 0x2c0 */
+ volatile unsigned int pmu_config[2];
+ volatile unsigned int pmu_bypass;
+ volatile unsigned int mac_pcu_tsf2_l32;
+ volatile unsigned int mac_pcu_tsf2_u32;
+ volatile unsigned int mac_pcu_generic_timers_mode3;
+ volatile unsigned int mac_pcu_direct_connect;
+ volatile unsigned int therm_ctrl1;
+ volatile unsigned int therm_ctrl2;
+ volatile unsigned int therm_ctrl3;
+} rtc_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h
new file mode 100644
index 000000000000..44d24661761e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h
@@ -0,0 +1,205 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _SI_REG_REG_H_
+#define _SI_REG_REG_H_
+
+#define SI_CONFIG_ADDRESS 0x00000000
+#define SI_CONFIG_OFFSET 0x00000000
+#define SI_CONFIG_ERR_INT_MSB 19
+#define SI_CONFIG_ERR_INT_LSB 19
+#define SI_CONFIG_ERR_INT_MASK 0x00080000
+#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
+#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
+#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
+#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
+#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_MSB 16
+#define SI_CONFIG_I2C_LSB 16
+#define SI_CONFIG_I2C_MASK 0x00010000
+#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_MSB 7
+#define SI_CONFIG_POS_SAMPLE_LSB 7
+#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
+#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_POS_DRIVE_MSB 6
+#define SI_CONFIG_POS_DRIVE_LSB 6
+#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
+#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
+#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
+#define SI_CONFIG_INACTIVE_DATA_MSB 5
+#define SI_CONFIG_INACTIVE_DATA_LSB 5
+#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
+#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_INACTIVE_CLK_MSB 4
+#define SI_CONFIG_INACTIVE_CLK_LSB 4
+#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
+#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_DIVIDER_MSB 3
+#define SI_CONFIG_DIVIDER_LSB 0
+#define SI_CONFIG_DIVIDER_MASK 0x0000000f
+#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+
+#define SI_CS_ADDRESS 0x00000004
+#define SI_CS_OFFSET 0x00000004
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
+#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
+#define SI_CS_DONE_ERR_MSB 10
+#define SI_CS_DONE_ERR_LSB 10
+#define SI_CS_DONE_ERR_MASK 0x00000400
+#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
+#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MSB 9
+#define SI_CS_DONE_INT_LSB 9
+#define SI_CS_DONE_INT_MASK 0x00000200
+#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
+#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
+#define SI_CS_START_MSB 8
+#define SI_CS_START_LSB 8
+#define SI_CS_START_MASK 0x00000100
+#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
+#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_MSB 7
+#define SI_CS_RX_CNT_LSB 4
+#define SI_CS_RX_CNT_MASK 0x000000f0
+#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_MSB 3
+#define SI_CS_TX_CNT_LSB 0
+#define SI_CS_TX_CNT_MASK 0x0000000f
+#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#define SI_TX_DATA0_ADDRESS 0x00000008
+#define SI_TX_DATA0_OFFSET 0x00000008
+#define SI_TX_DATA0_DATA3_MSB 31
+#define SI_TX_DATA0_DATA3_LSB 24
+#define SI_TX_DATA0_DATA3_MASK 0xff000000
+#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
+#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
+#define SI_TX_DATA0_DATA2_MSB 23
+#define SI_TX_DATA0_DATA2_LSB 16
+#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
+#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
+#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
+#define SI_TX_DATA0_DATA1_MSB 15
+#define SI_TX_DATA0_DATA1_LSB 8
+#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
+#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
+#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
+#define SI_TX_DATA0_DATA0_MSB 7
+#define SI_TX_DATA0_DATA0_LSB 0
+#define SI_TX_DATA0_DATA0_MASK 0x000000ff
+#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
+#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
+
+#define SI_TX_DATA1_ADDRESS 0x0000000c
+#define SI_TX_DATA1_OFFSET 0x0000000c
+#define SI_TX_DATA1_DATA7_MSB 31
+#define SI_TX_DATA1_DATA7_LSB 24
+#define SI_TX_DATA1_DATA7_MASK 0xff000000
+#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
+#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
+#define SI_TX_DATA1_DATA6_MSB 23
+#define SI_TX_DATA1_DATA6_LSB 16
+#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
+#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
+#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
+#define SI_TX_DATA1_DATA5_MSB 15
+#define SI_TX_DATA1_DATA5_LSB 8
+#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
+#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
+#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
+#define SI_TX_DATA1_DATA4_MSB 7
+#define SI_TX_DATA1_DATA4_LSB 0
+#define SI_TX_DATA1_DATA4_MASK 0x000000ff
+#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
+#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
+
+#define SI_RX_DATA0_ADDRESS 0x00000010
+#define SI_RX_DATA0_OFFSET 0x00000010
+#define SI_RX_DATA0_DATA3_MSB 31
+#define SI_RX_DATA0_DATA3_LSB 24
+#define SI_RX_DATA0_DATA3_MASK 0xff000000
+#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
+#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
+#define SI_RX_DATA0_DATA2_MSB 23
+#define SI_RX_DATA0_DATA2_LSB 16
+#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
+#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
+#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
+#define SI_RX_DATA0_DATA1_MSB 15
+#define SI_RX_DATA0_DATA1_LSB 8
+#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
+#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
+#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
+#define SI_RX_DATA0_DATA0_MSB 7
+#define SI_RX_DATA0_DATA0_LSB 0
+#define SI_RX_DATA0_DATA0_MASK 0x000000ff
+#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
+#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
+
+#define SI_RX_DATA1_ADDRESS 0x00000014
+#define SI_RX_DATA1_OFFSET 0x00000014
+#define SI_RX_DATA1_DATA7_MSB 31
+#define SI_RX_DATA1_DATA7_LSB 24
+#define SI_RX_DATA1_DATA7_MASK 0xff000000
+#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
+#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
+#define SI_RX_DATA1_DATA6_MSB 23
+#define SI_RX_DATA1_DATA6_LSB 16
+#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
+#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
+#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
+#define SI_RX_DATA1_DATA5_MSB 15
+#define SI_RX_DATA1_DATA5_LSB 8
+#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
+#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
+#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
+#define SI_RX_DATA1_DATA4_MSB 7
+#define SI_RX_DATA1_DATA4_LSB 0
+#define SI_RX_DATA1_DATA4_MASK 0x000000ff
+#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
+#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct si_reg_reg_s {
+ volatile unsigned int si_config;
+ volatile unsigned int si_cs;
+ volatile unsigned int si_tx_data0;
+ volatile unsigned int si_tx_data1;
+ volatile unsigned int si_rx_data0;
+ volatile unsigned int si_rx_data1;
+} si_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _SI_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h
new file mode 100644
index 000000000000..9e01b6a0875a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h
@@ -0,0 +1,256 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UART_REG_REG_H_
+#define _UART_REG_REG_H_
+
+#define UART_DATA_ADDRESS 0x00000000
+#define UART_DATA_OFFSET 0x00000000
+#define UART_DATA_TX_CSR_MSB 9
+#define UART_DATA_TX_CSR_LSB 9
+#define UART_DATA_TX_CSR_MASK 0x00000200
+#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
+#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
+#define UART_DATA_RX_CSR_MSB 8
+#define UART_DATA_RX_CSR_LSB 8
+#define UART_DATA_RX_CSR_MASK 0x00000100
+#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
+#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
+#define UART_DATA_TXRX_DATA_MSB 7
+#define UART_DATA_TXRX_DATA_LSB 0
+#define UART_DATA_TXRX_DATA_MASK 0x000000ff
+#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
+#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
+
+#define UART_CONTROL_ADDRESS 0x00000004
+#define UART_CONTROL_OFFSET 0x00000004
+#define UART_CONTROL_RX_BUSY_MSB 15
+#define UART_CONTROL_RX_BUSY_LSB 15
+#define UART_CONTROL_RX_BUSY_MASK 0x00008000
+#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
+#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
+#define UART_CONTROL_TX_BUSY_MSB 14
+#define UART_CONTROL_TX_BUSY_LSB 14
+#define UART_CONTROL_TX_BUSY_MASK 0x00004000
+#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
+#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
+#define UART_CONTROL_HOST_INT_ENABLE_MSB 13
+#define UART_CONTROL_HOST_INT_ENABLE_LSB 13
+#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000
+#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
+#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
+#define UART_CONTROL_HOST_INT_MSB 12
+#define UART_CONTROL_HOST_INT_LSB 12
+#define UART_CONTROL_HOST_INT_MASK 0x00001000
+#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
+#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
+#define UART_CONTROL_TX_BREAK_MSB 11
+#define UART_CONTROL_TX_BREAK_LSB 11
+#define UART_CONTROL_TX_BREAK_MASK 0x00000800
+#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
+#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
+#define UART_CONTROL_RX_BREAK_MSB 10
+#define UART_CONTROL_RX_BREAK_LSB 10
+#define UART_CONTROL_RX_BREAK_MASK 0x00000400
+#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
+#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
+#define UART_CONTROL_SERIAL_TX_READY_MSB 9
+#define UART_CONTROL_SERIAL_TX_READY_LSB 9
+#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200
+#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
+#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
+#define UART_CONTROL_TX_READY_ORIDE_MSB 8
+#define UART_CONTROL_TX_READY_ORIDE_LSB 8
+#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100
+#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
+#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
+#define UART_CONTROL_RX_READY_ORIDE_MSB 7
+#define UART_CONTROL_RX_READY_ORIDE_LSB 7
+#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080
+#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
+#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
+#define UART_CONTROL_DMA_ENABLE_MSB 6
+#define UART_CONTROL_DMA_ENABLE_LSB 6
+#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040
+#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
+#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
+#define UART_CONTROL_FLOW_ENABLE_MSB 5
+#define UART_CONTROL_FLOW_ENABLE_LSB 5
+#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020
+#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
+#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
+#define UART_CONTROL_FLOW_INVERT_MSB 4
+#define UART_CONTROL_FLOW_INVERT_LSB 4
+#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010
+#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
+#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
+#define UART_CONTROL_IFC_ENABLE_MSB 3
+#define UART_CONTROL_IFC_ENABLE_LSB 3
+#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008
+#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
+#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
+#define UART_CONTROL_IFC_DCE_MSB 2
+#define UART_CONTROL_IFC_DCE_LSB 2
+#define UART_CONTROL_IFC_DCE_MASK 0x00000004
+#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
+#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
+#define UART_CONTROL_PARITY_ENABLE_MSB 1
+#define UART_CONTROL_PARITY_ENABLE_LSB 1
+#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002
+#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
+#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
+#define UART_CONTROL_PARITY_EVEN_MSB 0
+#define UART_CONTROL_PARITY_EVEN_LSB 0
+#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001
+#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
+#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
+
+#define UART_CLKDIV_ADDRESS 0x00000008
+#define UART_CLKDIV_OFFSET 0x00000008
+#define UART_CLKDIV_CLK_SCALE_MSB 23
+#define UART_CLKDIV_CLK_SCALE_LSB 16
+#define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000
+#define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB)
+#define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK)
+#define UART_CLKDIV_CLK_STEP_MSB 15
+#define UART_CLKDIV_CLK_STEP_LSB 0
+#define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff
+#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
+#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
+
+#define UART_INT_ADDRESS 0x0000000c
+#define UART_INT_OFFSET 0x0000000c
+#define UART_INT_TX_EMPTY_INT_MSB 9
+#define UART_INT_TX_EMPTY_INT_LSB 9
+#define UART_INT_TX_EMPTY_INT_MASK 0x00000200
+#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
+#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
+#define UART_INT_RX_FULL_INT_MSB 8
+#define UART_INT_RX_FULL_INT_LSB 8
+#define UART_INT_RX_FULL_INT_MASK 0x00000100
+#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
+#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
+#define UART_INT_RX_BREAK_OFF_INT_MSB 7
+#define UART_INT_RX_BREAK_OFF_INT_LSB 7
+#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080
+#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
+#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
+#define UART_INT_RX_BREAK_ON_INT_MSB 6
+#define UART_INT_RX_BREAK_ON_INT_LSB 6
+#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040
+#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
+#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
+#define UART_INT_RX_PARITY_ERR_INT_MSB 5
+#define UART_INT_RX_PARITY_ERR_INT_LSB 5
+#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020
+#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
+#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
+#define UART_INT_TX_OFLOW_ERR_INT_MSB 4
+#define UART_INT_TX_OFLOW_ERR_INT_LSB 4
+#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010
+#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
+#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
+#define UART_INT_RX_OFLOW_ERR_INT_MSB 3
+#define UART_INT_RX_OFLOW_ERR_INT_LSB 3
+#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008
+#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
+#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
+#define UART_INT_RX_FRAMING_ERR_INT_MSB 2
+#define UART_INT_RX_FRAMING_ERR_INT_LSB 2
+#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004
+#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
+#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
+#define UART_INT_TX_READY_INT_MSB 1
+#define UART_INT_TX_READY_INT_LSB 1
+#define UART_INT_TX_READY_INT_MASK 0x00000002
+#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
+#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
+#define UART_INT_RX_VALID_INT_MSB 0
+#define UART_INT_RX_VALID_INT_LSB 0
+#define UART_INT_RX_VALID_INT_MASK 0x00000001
+#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
+#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
+
+#define UART_INT_EN_ADDRESS 0x00000010
+#define UART_INT_EN_OFFSET 0x00000010
+#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9
+#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9
+#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200
+#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
+#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
+#define UART_INT_EN_RX_FULL_INT_EN_MSB 8
+#define UART_INT_EN_RX_FULL_INT_EN_LSB 8
+#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100
+#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
+#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
+#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
+#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
+#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
+#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
+#define UART_INT_EN_TX_READY_INT_EN_MSB 1
+#define UART_INT_EN_TX_READY_INT_EN_LSB 1
+#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002
+#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
+#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
+#define UART_INT_EN_RX_VALID_INT_EN_MSB 0
+#define UART_INT_EN_RX_VALID_INT_EN_LSB 0
+#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001
+#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
+#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct uart_reg_reg_s {
+ volatile unsigned int uart_data;
+ volatile unsigned int uart_control;
+ volatile unsigned int uart_clkdiv;
+ volatile unsigned int uart_int;
+ volatile unsigned int uart_int_en;
+} uart_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UART_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h
new file mode 100644
index 000000000000..d8a07b30043b
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h
@@ -0,0 +1,33 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "umbox_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h
new file mode 100644
index 000000000000..9b63f5f40757
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h
@@ -0,0 +1,318 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _UMBOX_WLAN_REG_REG_H_
+#define _UMBOX_WLAN_REG_REG_H_
+
+#define UMBOX_FIFO_ADDRESS 0x00000000
+#define UMBOX_FIFO_OFFSET 0x00000000
+#define UMBOX_FIFO_DATA_MSB 8
+#define UMBOX_FIFO_DATA_LSB 0
+#define UMBOX_FIFO_DATA_MASK 0x000001ff
+#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
+#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
+
+#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008
+#define UMBOX_FIFO_STATUS_OFFSET 0x00000008
+#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3
+#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3
+#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008
+#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
+#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
+#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2
+#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2
+#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004
+#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
+#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
+#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1
+#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1
+#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002
+#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
+#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
+#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0
+#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0
+#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001
+#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
+#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
+
+#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c
+#define UMBOX_DMA_POLICY_OFFSET 0x0000000c
+#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3
+#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3
+#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
+#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
+#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
+#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2
+#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2
+#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
+#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
+#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
+#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1
+#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1
+#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
+#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
+#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
+#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0
+#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0
+#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
+#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
+#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
+
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014
+#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014
+#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
+#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
+#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
+#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
+#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
+#define UMBOX0_DMA_RX_CONTROL_START_MSB 1
+#define UMBOX0_DMA_RX_CONTROL_START_LSB 1
+#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
+#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
+#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
+#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0
+#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0
+#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
+#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
+#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
+
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
+#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
+
+#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c
+#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c
+#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
+#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
+#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
+#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
+#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
+#define UMBOX0_DMA_TX_CONTROL_START_MSB 1
+#define UMBOX0_DMA_TX_CONTROL_START_LSB 1
+#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
+#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
+#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
+#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0
+#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0
+#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
+#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
+#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
+
+#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020
+#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
+#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
+#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7
+#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0
+#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff
+#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
+#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
+
+#define UMBOX_INT_STATUS_ADDRESS 0x00000024
+#define UMBOX_INT_STATUS_OFFSET 0x00000024
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
+#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
+#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3
+#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3
+#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008
+#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
+#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
+#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
+#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
+#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
+#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
+#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
+#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
+#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
+
+#define UMBOX_INT_ENABLE_ADDRESS 0x00000028
+#define UMBOX_INT_ENABLE_OFFSET 0x00000028
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
+#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
+#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
+#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
+#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
+#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
+#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
+
+#define UMBOX_DEBUG_ADDRESS 0x0000002c
+#define UMBOX_DEBUG_OFFSET 0x0000002c
+#define UMBOX_DEBUG_SEL_MSB 2
+#define UMBOX_DEBUG_SEL_LSB 0
+#define UMBOX_DEBUG_SEL_MASK 0x00000007
+#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
+#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
+
+#define UMBOX_FIFO_RESET_ADDRESS 0x00000030
+#define UMBOX_FIFO_RESET_OFFSET 0x00000030
+#define UMBOX_FIFO_RESET_INIT_MSB 0
+#define UMBOX_FIFO_RESET_INIT_LSB 0
+#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001
+#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
+#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
+
+#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034
+#define UMBOX_HCI_FRAMER_OFFSET 0x00000034
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
+#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
+#define UMBOX_HCI_FRAMER_ENABLE_MSB 5
+#define UMBOX_HCI_FRAMER_ENABLE_LSB 5
+#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020
+#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
+#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
+#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
+#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3
+#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3
+#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008
+#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
+#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
+#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2
+#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2
+#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004
+#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
+#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
+#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct umbox_wlan_reg_reg_s {
+ volatile unsigned int umbox_fifo[2];
+ volatile unsigned int umbox_fifo_status;
+ volatile unsigned int umbox_dma_policy;
+ volatile unsigned int umbox0_dma_rx_descriptor_base;
+ volatile unsigned int umbox0_dma_rx_control;
+ volatile unsigned int umbox0_dma_tx_descriptor_base;
+ volatile unsigned int umbox0_dma_tx_control;
+ volatile unsigned int umbox_fifo_timeout;
+ volatile unsigned int umbox_int_status;
+ volatile unsigned int umbox_int_enable;
+ volatile unsigned int umbox_debug;
+ volatile unsigned int umbox_fifo_reset;
+ volatile unsigned int umbox_hci_framer;
+} umbox_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _UMBOX_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h
new file mode 100644
index 000000000000..2d7b6aa06911
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h
@@ -0,0 +1,163 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifdef WLAN_HEADERS
+
+#include "vmc_wlan_reg.h"
+
+
+#ifndef BT_HEADERS
+
+#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS
+#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET
+#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB
+#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB
+#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK
+#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x)
+#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x)
+#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS
+#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET
+#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB
+#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB
+#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK
+#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x)
+#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x)
+#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS
+#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET
+#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB
+#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB
+#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK
+#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x)
+#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x)
+#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS
+#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)
+#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)
+#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB
+#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB
+#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK
+#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
+#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS
+#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET
+#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB
+#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB
+#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK
+#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)
+#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB
+#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB
+#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK
+#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
+#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
+#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS
+#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
+#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS
+#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET
+#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB
+#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB
+#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK
+#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)
+#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)
+#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB
+#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB
+#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK
+#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)
+#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
+#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
+#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS
+#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x)
+#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x)
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x)
+#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x)
+#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS
+#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET
+#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB
+#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB
+#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK
+#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x)
+#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x)
+#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS
+#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET
+#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB
+#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB
+#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK
+#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x)
+#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x)
+#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS
+#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET
+#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB
+#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB
+#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK
+#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x)
+#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x)
+#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS
+#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET
+#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB
+#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB
+#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK
+#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)
+#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)
+#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS
+#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET
+#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB
+#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB
+#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK
+#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)
+#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)
+#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS
+#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET
+#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB
+#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB
+#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK
+#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)
+#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)
+#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS
+#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET
+#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB
+#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB
+#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK
+#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)
+#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)
+
+
+#endif
+#endif
+
+
+
diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h
new file mode 100644
index 000000000000..ff6d14545cd0
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h
@@ -0,0 +1,191 @@
+// ------------------------------------------------------------------
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+// ------------------------------------------------------------------
+//===================================================================
+// Author(s): ="Atheros"
+//===================================================================
+
+
+#ifndef _VMC_WLAN_REG_REG_H_
+#define _VMC_WLAN_REG_REG_H_
+
+#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000
+#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000
+#define WLAN_MC_BCAM_VALID_BIT_MSB 0
+#define WLAN_MC_BCAM_VALID_BIT_LSB 0
+#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001
+#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB)
+#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK)
+
+#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200
+#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200
+#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19
+#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2
+#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc
+#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB)
+#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK)
+
+#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400
+#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400
+#define WLAN_MC_BCAM_TARGET_INST_MSB 31
+#define WLAN_MC_BCAM_TARGET_INST_LSB 0
+#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff
+#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB)
+#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK)
+
+#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600
+#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
+#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604
+#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB)
+#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK)
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608
+#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB)
+#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK)
+
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c
+#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK)
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB)
+#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK)
+
+#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610
+#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB)
+#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK)
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB)
+#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK)
+
+#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614
+#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614
+#define WLAN_CPU_PERF_CNT_EN_MSB 0
+#define WLAN_CPU_PERF_CNT_EN_LSB 0
+#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001
+#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB)
+#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK)
+
+#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618
+#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618
+#define WLAN_CPU_INST_FETCH_CNT_MSB 31
+#define WLAN_CPU_INST_FETCH_CNT_LSB 0
+#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff
+#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB)
+#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK)
+
+#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c
+#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c
+#define WLAN_CPU_DATA_FETCH_CNT_MSB 31
+#define WLAN_CPU_DATA_FETCH_CNT_LSB 0
+#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff
+#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB)
+#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK)
+
+#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620
+#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620
+#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11
+#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0
+#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff
+#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624
+#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624
+#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11
+#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0
+#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff
+#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628
+#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628
+#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11
+#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0
+#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff
+#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK)
+
+#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c
+#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c
+#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11
+#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0
+#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff
+#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB)
+#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK)
+
+
+#ifndef __ASSEMBLER__
+
+typedef struct vmc_wlan_reg_reg_s {
+ volatile unsigned int wlan_mc_bcam_valid[128];
+ volatile unsigned int wlan_mc_bcam_compare[128];
+ volatile unsigned int wlan_mc_bcam_target[128];
+ volatile unsigned int wlan_apb_addr_error_control;
+ volatile unsigned int wlan_apb_addr_error_status;
+ volatile unsigned int wlan_ahb_addr_error_control;
+ volatile unsigned int wlan_ahb_addr_error_status;
+ volatile unsigned int wlan_bcam_conflict_error;
+ volatile unsigned int wlan_cpu_perf_cnt;
+ volatile unsigned int wlan_cpu_inst_fetch;
+ volatile unsigned int wlan_cpu_data_fetch;
+ volatile unsigned int wlan_cpu_ram1_conflict;
+ volatile unsigned int wlan_cpu_ram2_conflict;
+ volatile unsigned int wlan_cpu_ram3_conflict;
+ volatile unsigned int wlan_cpu_ram4_conflict;
+} vmc_wlan_reg_reg_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _VMC_WLAN_REG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/a_config.h b/drivers/net/wireless/ath6kl/include/a_config.h
new file mode 100644
index 000000000000..8f9ccf7d1a29
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_config.h
@@ -0,0 +1,45 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_config.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains software configuration options that enables
+// specific software "features"
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_CONFIG_H_
+#define _A_CONFIG_H_
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/config.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/config.h"
+#endif
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/config_linux.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/config_rexos.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/win/config_win.h"
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/a_debug.h b/drivers/net/wireless/ath6kl/include/a_debug.h
new file mode 100644
index 000000000000..f8f7a2cdf5d3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_debug.h
@@ -0,0 +1,215 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_debug.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DEBUG_H_
+#define _A_DEBUG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <a_types.h>
+#include <a_osapi.h>
+
+ /* standard debug print masks bits 0..7 */
+#define ATH_DEBUG_ERR (1 << 0) /* errors */
+#define ATH_DEBUG_WARN (1 << 1) /* warnings */
+#define ATH_DEBUG_INFO (1 << 2) /* informational (module startup info) */
+#define ATH_DEBUG_TRC (1 << 3) /* generic function call tracing */
+#define ATH_DEBUG_RSVD1 (1 << 4)
+#define ATH_DEBUG_RSVD2 (1 << 5)
+#define ATH_DEBUG_RSVD3 (1 << 6)
+#define ATH_DEBUG_RSVD4 (1 << 7)
+
+#define ATH_DEBUG_MASK_DEFAULTS (ATH_DEBUG_ERR | ATH_DEBUG_WARN)
+#define ATH_DEBUG_ANY 0xFFFF
+
+ /* other aliases used throughout */
+#define ATH_DEBUG_ERROR ATH_DEBUG_ERR
+#define ATH_LOG_ERR ATH_DEBUG_ERR
+#define ATH_LOG_INF ATH_DEBUG_INFO
+#define ATH_LOG_TRC ATH_DEBUG_TRC
+#define ATH_DEBUG_TRACE ATH_DEBUG_TRC
+#define ATH_DEBUG_INIT ATH_DEBUG_INFO
+
+ /* bits 8..31 are module-specific masks */
+#define ATH_DEBUG_MODULE_MASK_SHIFT 8
+
+ /* macro to make a module-specific masks */
+#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+/* Debug support on a per-module basis
+ *
+ * Usage:
+ *
+ * Each module can utilize it's own debug mask variable. A set of commonly used
+ * masks are provided (ERRORS, WARNINGS, TRACE etc..). It is up to each module
+ * to define module-specific masks using the macros above.
+ *
+ * Each module defines a single debug mask variable debug_XXX where the "name" of the module is
+ * common to all C-files within that module. This requires every C-file that includes a_debug.h
+ * to define the module name in that file.
+ *
+ * Example:
+ *
+ * #define ATH_MODULE_NAME htc
+ * #include "a_debug.h"
+ *
+ * This will define a debug mask structure called debug_htc and all debug macros will reference this
+ * variable.
+ *
+ * A module can define module-specific bit masks using the ATH_DEBUG_MAKE_MODULE_MASK() macro:
+ *
+ * #define ATH_DEBUG_MY_MASK1 ATH_DEBUG_MAKE_MODULE_MASK(0)
+ * #define ATH_DEBUG_MY_MASK2 ATH_DEBUG_MAKE_MODULE_MASK(1)
+ *
+ * The instantiation of the debug structure should be made by the module. When a module is
+ * instantiated, the module can set a description string, a default mask and an array of description
+ * entries containing information on each module-defined debug mask.
+ * NOTE: The instantiation is statically allocated, only one instance can exist per module.
+ *
+ * Example:
+ *
+ *
+ * #define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
+ *
+ * #ifdef DEBUG
+ * static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
+ * { ATH_DEBUG_BMI , "BMI Tracing"}, <== description of the module specific mask
+ * };
+ *
+ * ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
+ * "bmi" <== module name
+ * "Boot Manager Interface", <== description of module
+ * ATH_DEBUG_MASK_DEFAULTS, <== defaults
+ * ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
+ * bmi_debug_desc);
+ *
+ * #endif
+ *
+ * A module can optionally register it's debug module information in order for other tools to change the
+ * bit mask at runtime. A module can call A_REGISTER_MODULE_DEBUG_INFO() in it's module
+ * init code. This macro can be called multiple times without consequence. The debug info maintains
+ * state to indicate whether the information was previously registered.
+ *
+ * */
+
+#define ATH_DEBUG_MAX_MASK_DESC_LENGTH 32
+#define ATH_DEBUG_MAX_MOD_DESC_LENGTH 64
+
+typedef struct {
+ A_UINT32 Mask;
+ A_CHAR Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH];
+} ATH_DEBUG_MASK_DESCRIPTION;
+
+#define ATH_DEBUG_INFO_FLAGS_REGISTERED (1 << 0)
+
+typedef struct _ATH_DEBUG_MODULE_DBG_INFO{
+ struct _ATH_DEBUG_MODULE_DBG_INFO *pNext;
+ A_CHAR ModuleName[16];
+ A_CHAR ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH];
+ A_UINT32 Flags;
+ A_UINT32 CurrentMask;
+ int MaxDescriptions;
+ ATH_DEBUG_MASK_DESCRIPTION *pMaskDescriptions; /* pointer to array of descriptions */
+} ATH_DEBUG_MODULE_DBG_INFO;
+
+#define ATH_DEBUG_DESCRIPTION_COUNT(d) (int)((sizeof((d))) / (sizeof(ATH_DEBUG_MASK_DESCRIPTION)))
+
+#define GET_ATH_MODULE_DEBUG_VAR_NAME(s) _XGET_ATH_MODULE_NAME_DEBUG_(s)
+#define GET_ATH_MODULE_DEBUG_VAR_MASK(s) _XGET_ATH_MODULE_NAME_DEBUG_(s).CurrentMask
+#define _XGET_ATH_MODULE_NAME_DEBUG_(s) debug_ ## s
+
+#ifdef DEBUG
+
+ /* for source files that will instantiate the debug variables */
+#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) \
+ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) = \
+ {NULL,(name),(moddesc),0,(initmask),count,(descriptions)}
+
+#ifdef ATH_MODULE_NAME
+extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(ATH_MODULE_NAME);
+#define AR_DEBUG_LVL_CHECK(lvl) (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (lvl))
+#endif /* ATH_MODULE_NAME */
+
+#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) GET_ATH_MODULE_DEBUG_VAR_MASK(s) = (lvl)
+
+#define ATH_DEBUG_DECLARE_EXTERN(s) \
+ extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s)
+
+#define AR_DEBUG_PRINTBUF(buffer, length, desc) DebugDumpBytes(buffer,length,desc)
+
+
+#define AR_DEBUG_ASSERT A_ASSERT
+
+void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
+void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
+#define A_DUMP_MODULE_DEBUG_INFO(s) a_dump_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
+#define A_REGISTER_MODULE_DEBUG_INFO(s) a_register_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
+
+#else /* !DEBUG */
+ /* NON DEBUG */
+#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions)
+#define AR_DEBUG_LVL_CHECK(lvl) 0
+#define AR_DEBUG_PRINTBUF(buffer, length, desc)
+#define AR_DEBUG_ASSERT(test)
+#define ATH_DEBUG_DECLARE_EXTERN(s)
+#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl)
+#define A_DUMP_MODULE_DEBUG_INFO(s)
+#define A_REGISTER_MODULE_DEBUG_INFO(s)
+
+#endif
+
+A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask);
+A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask);
+void a_dump_module_debug_info_by_name(A_CHAR *module_name);
+void a_module_debug_support_init(void);
+void a_module_debug_support_cleanup(void);
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/debug.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/debug.h"
+#endif
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/debug_linux.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/debug_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/debug_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include <debug_win.h>
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/a_drv.h b/drivers/net/wireless/ath6kl/include/a_drv.h
new file mode 100644
index 000000000000..f7a6afe91993
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_drv.h
@@ -0,0 +1,46 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_drv.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DRV_H_
+#define _A_DRV_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/athdrv_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/athdrv_rexos.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/athdrv.h"
+#endif
+
+#endif /* _ADRV_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/a_drv_api.h b/drivers/net/wireless/ath6kl/include/a_drv_api.h
new file mode 100644
index 000000000000..b3dd4f5635b4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_drv_api.h
@@ -0,0 +1,228 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_drv_api.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_DRV_API_H_
+#define _A_DRV_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/****************************************************************************/
+/** **/
+/** WMI related hooks **/
+/** **/
+/****************************************************************************/
+/****************************************************************************/
+
+#include <ar6000_api.h>
+
+#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \
+ ar6000_channelList_rx((devt), (numChan), (chanList))
+
+#define A_WMI_SET_NUMDATAENDPTS(devt, num) \
+ ar6000_set_numdataendpts((devt), (num))
+
+#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \
+ ar6000_control_tx((devt), (osbuf), (streamID))
+
+#define A_WMI_TARGETSTATS_EVENT(devt, pStats, len) \
+ ar6000_targetStats_event((devt), (pStats), (len))
+
+#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \
+ ar6000_scanComplete_event((devt), (status))
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+
+#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \
+ ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_DSET_CLOSE(devt, access_cookie) \
+ ar6000_dset_close((devt), (access_cookie))
+
+#endif
+
+#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
+ ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
+ ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
+
+#define A_WMI_PSPOLL_EVENT(devt, aid)\
+ ar6000_pspoll_event((devt),(aid))
+
+#define A_WMI_DTIMEXPIRY_EVENT(devt)\
+ ar6000_dtimexpiry_event((devt))
+
+#ifdef WAPI_ENABLE
+#define A_WMI_WAPI_REKEY_EVENT(devt, type, mac)\
+ ap_wapi_rekey_event((devt),(type),(mac))
+#endif
+
+#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \
+ ar6000_regDomain_event((devt), (regCode))
+
+#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \
+ ar6000_neighborReport_event((devt), (numAps), (info))
+
+#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \
+ ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
+
+#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \
+ ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
+
+#define A_WMI_BITRATE_RX(devt, rateKbps) \
+ ar6000_bitrate_rx((devt), (rateKbps))
+
+#define A_WMI_TXPWR_RX(devt, txPwr) \
+ ar6000_txPwr_rx((devt), (txPwr))
+
+#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \
+ ar6000_ready_event((devt), (datap), (phyCap), (ver))
+
+#define A_WMI_DBGLOG_INIT_DONE(ar) \
+ ar6000_dbglog_init_done(ar);
+
+#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \
+ ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
+
+#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \
+ ar6000_reportError_event((devt), (errorVal))
+
+#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
+ ar6000_roam_tbl_event((devt), (pTbl))
+
+#define A_WMI_ROAM_DATA_EVENT(devt, p) \
+ ar6000_roam_data_event((devt), (p))
+
+#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \
+ ar6000_wow_list_event((devt), (num_filters), (wow_filters))
+
+#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \
+ ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
+
+#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \
+ ar6000_channel_change_event((devt), (oldChannel), (newChannel))
+
+#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \
+ ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list))
+
+#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \
+ ar6000_peer_event ((devt), (eventCode), (bssid))
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+
+#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
+ ar6000_gpio_intr_rx((intr_mask), (input_values))
+
+#define A_WMI_GPIO_DATA_RX(reg_id, value) \
+ ar6000_gpio_data_rx((reg_id), (value))
+
+#define A_WMI_GPIO_ACK_RX() \
+ ar6000_gpio_ack_rx()
+
+#endif
+
+#ifdef SEND_EVENT_TO_APP
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
+ ar6000_send_event_to_app((ar), (eventId), (datap), (len))
+
+#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \
+ ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len))
+
+#else
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
+#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len)
+
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
+ ar6000_tcmd_rx_report_event((devt), (results), (len))
+#endif
+
+#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \
+ ar6000_hbChallengeResp_event((devt), (cookie), (source))
+
+#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
+ ar6000_tx_retry_err_event((devt))
+
+#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
+ ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
+
+#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
+ ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
+
+#define A_WMI_RATEMASK_RX(devt, ratemask) \
+ ar6000_ratemask_rx((devt), (ratemask))
+
+#define A_WMI_KEEPALIVE_RX(devt, configured) \
+ ar6000_keepalive_rx((devt), (configured))
+
+#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \
+ ar6000_bssInfo_event_rx((ar), (datap), (len))
+
+#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
+ ar6000_dbglog_event((ar), (dropped), (buffer), (length));
+
+#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
+ ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
+
+#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
+ ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
+#define A_WMI_Ac2EndpointID(devht, ac)\
+ ar6000_ac2_endpoint_id((devht), (ac))
+
+#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, cmd)\
+ ar6000_aggr_rcv_addba_req_evt((devt), (cmd))
+#define A_WMI_AGGR_RECV_ADDBA_RESP_EVT(devt, cmd)\
+ ar6000_aggr_rcv_addba_resp_evt((devt), (cmd))
+#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, cmd)\
+ ar6000_aggr_rcv_delba_req_evt((devt), (cmd))
+#define A_WMI_HCI_EVENT_EVT(devt, cmd)\
+ ar6000_hci_event_rcv_evt((devt), (cmd))
+
+#define A_WMI_Endpoint2Ac(devt, ep) \
+ ar6000_endpoint_id2_ac((devt), (ep))
+
+#define A_WMI_BTCOEX_CONFIG_EVENT(devt, evt, len)\
+ ar6000_btcoex_config_event((devt), (evt), (len))
+
+#define A_WMI_BTCOEX_STATS_EVENT(devt, datap, len)\
+ ar6000_btcoex_stats_event((devt), (datap), (len))
+
+/****************************************************************************/
+/****************************************************************************/
+/** **/
+/** HTC related hooks **/
+/** **/
+/****************************************************************************/
+/****************************************************************************/
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count))
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/a_hci.h b/drivers/net/wireless/ath6kl/include/a_hci.h
new file mode 100644
index 000000000000..b1a66308d828
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_hci.h
@@ -0,0 +1,668 @@
+//-
+// Copyright (c) 2009 Atheros Communications Inc.
+// All rights reserved.
+// $ATH_LICENSE_TARGET_C$
+//
+//
+
+
+#ifndef __A_HCI_H__
+#define __A_HCI_H__
+
+#define HCI_CMD_OGF_MASK 0x3F
+#define HCI_CMD_OGF_SHIFT 10
+#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK)
+
+#define HCI_CMD_OCF_MASK 0x3FF
+#define HCI_CMD_OCF_SHIFT 0
+#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK)
+
+#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \
+ (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT)
+
+
+/*======== HCI Opcode groups ===============*/
+#define OGF_NOP 0x00
+#define OGF_LINK_CONTROL 0x01
+#define OGF_LINK_POLICY 0x03
+#define OGF_INFO_PARAMS 0x04
+#define OGF_STATUS 0x05
+#define OGF_TESTING 0x06
+#define OGF_BLUETOOTH 0x3E
+#define OGF_VENDOR_DEBUG 0x3F
+
+
+
+#define OCF_NOP 0x00
+
+
+/*===== Link Control Commands Opcode===================*/
+#define OCF_HCI_Create_Physical_Link 0x35
+#define OCF_HCI_Accept_Physical_Link_Req 0x36
+#define OCF_HCI_Disconnect_Physical_Link 0x37
+#define OCF_HCI_Create_Logical_Link 0x38
+#define OCF_HCI_Accept_Logical_Link 0x39
+#define OCF_HCI_Disconnect_Logical_Link 0x3A
+#define OCF_HCI_Logical_Link_Cancel 0x3B
+#define OCF_HCI_Flow_Spec_Modify 0x3C
+
+
+
+/*===== Link Policy Commands Opcode====================*/
+#define OCF_HCI_Set_Event_Mask 0x01
+#define OCF_HCI_Reset 0x03
+#define OCF_HCI_Read_Conn_Accept_Timeout 0x15
+#define OCF_HCI_Write_Conn_Accept_Timeout 0x16
+#define OCF_HCI_Read_Link_Supervision_Timeout 0x36
+#define OCF_HCI_Write_Link_Supervision_Timeout 0x37
+#define OCF_HCI_Enhanced_Flush 0x5F
+#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61
+#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62
+#define OCF_HCI_Set_Event_Mask_Page_2 0x63
+#define OCF_HCI_Read_Location_Data 0x64
+#define OCF_HCI_Write_Location_Data 0x65
+#define OCF_HCI_Read_Flow_Control_Mode 0x66
+#define OCF_HCI_Write_Flow_Control_Mode 0x67
+#define OCF_HCI_Read_BE_Flush_Timeout 0x69
+#define OCF_HCI_Write_BE_Flush_Timeout 0x6A
+#define OCF_HCI_Short_Range_Mode 0x6B
+
+
+/*======== Info Commands Opcode========================*/
+#define OCF_HCI_Read_Local_Ver_Info 0x01
+#define OCF_HCI_Read_Local_Supported_Cmds 0x02
+#define OCF_HCI_Read_Data_Block_Size 0x0A
+/*======== Status Commands Opcode======================*/
+#define OCF_HCI_Read_Failed_Contact_Counter 0x01
+#define OCF_HCI_Reset_Failed_Contact_Counter 0x02
+#define OCF_HCI_Read_Link_Quality 0x03
+#define OCF_HCI_Read_RSSI 0x05
+#define OCF_HCI_Read_Local_AMP_Info 0x09
+#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A
+#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B
+
+
+/*======= AMP_ASSOC Specific TLV tags =================*/
+#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1
+#define AMP_ASSOC_PREF_CHAN_LIST 0x2
+#define AMP_ASSOC_CONNECTED_CHAN 0x3
+#define AMP_ASSOC_PAL_CAPABILITIES 0x4
+#define AMP_ASSOC_PAL_VERSION 0x5
+
+
+/*========= PAL Events =================================*/
+#define PAL_COMMAND_COMPLETE_EVENT 0x0E
+#define PAL_COMMAND_STATUS_EVENT 0x0F
+#define PAL_HARDWARE_ERROR_EVENT 0x10
+#define PAL_FLUSH_OCCURRED_EVENT 0x11
+#define PAL_LOOPBACK_EVENT 0x19
+#define PAL_BUFFER_OVERFLOW_EVENT 0x1A
+#define PAL_QOS_VIOLATION_EVENT 0x1E
+#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39
+#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40
+#define PAL_CHANNEL_SELECT_EVENT 0x41
+#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42
+#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43
+#define PAL_PHY_LINK_RECOVERY_EVENT 0x44
+#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45
+#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46
+#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47
+#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48
+#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C
+#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D
+/*======== End of PAL events definiton =================*/
+
+
+/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/
+#define Timer_Conn_Accept_TO 0x01
+#define Timer_Link_Supervision_TO 0x02
+
+#define NUM_HCI_COMMAND_PKTS 0x1
+
+
+/*====== NOP Cmd ============================*/
+#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP)
+
+
+/*===== Link Control Commands================*/
+#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL)
+#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL)
+#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL)
+#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL)
+#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL)
+#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL)
+
+
+/*===== Link Policy Commands ================*/
+#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY)
+#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY)
+#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY)
+#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY)
+#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY)
+#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY)
+#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY)
+#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY)
+#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY)
+#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY)
+#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY)
+#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY)
+
+
+/*===== Info Commands =====================*/
+#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS)
+#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS)
+#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS)
+
+/*===== Status Commands =====================*/
+#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS)
+#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS)
+#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS)
+#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS)
+#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS)
+
+/*====== End of cmd definitions =============*/
+
+
+
+/*===== Timeouts(private - can't come from HCI)=================*/
+#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG)
+#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG)
+
+/*----- PAL Constants (Sec 6 of Doc)------------------------*/
+#define Max80211_PAL_PDU_Size 1492
+#define Max80211_AMP_ASSOC_Len 672
+#define MinGUserPrio 4
+#define MaxGUserPrio 7
+#define BEUserPrio0 0
+#define BEUserPrio1 3
+#define Max80211BeaconPeriod 2000 /* in millisec */
+#define ShortRangeModePowerMax 4 /* dBm */
+
+/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/
+typedef enum {
+ ACL_DATA = 0x01,
+ ACTIVITY_REPORT,
+ SECURED_FRAMES,
+ LINK_SUPERVISION_REQ,
+ LINK_SUPERVISION_RESP,
+}PAL_PROTOCOL_IDENTIFIERS;
+
+#define HCI_CMD_HDR_SZ 3
+#define HCI_EVENT_HDR_SIZE 2
+#define MAX_EVT_PKT_SZ 255
+#define AMP_ASSOC_MAX_FRAG_SZ 248
+#define AMP_MAX_GUARANTEED_BW 20000
+
+#define DEFAULT_CONN_ACCPT_TO 5000
+#define DEFAULT_LL_ACCPT_TO 5000
+#define DEFAULT_LSTO 10000
+
+#define PACKET_BASED_FLOW_CONTROL_MODE 0x00
+#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01
+
+#define SERVICE_TYPE_BEST_EFFORT 0x01
+#define SERVICE_TYPE_GUARANTEED 0x02
+
+#define MAC_ADDR_LEN 6
+#define LINK_KEY_LEN 32
+
+typedef enum {
+ ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00,
+ ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01,
+ ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02,
+ ACL_DATA_PB_COMPLETE_PDU = 0x03,
+} ACL_DATA_PB_FLAGS;
+#define ACL_DATA_PB_FLAGS_SHIFT 12
+
+typedef enum {
+ ACL_DATA_BC_POINT_TO_POINT = 0x00,
+} ACL_DATA_BC_FLAGS;
+#define ACL_DATA_BC_FLAGS_SHIFT 14
+
+/* Command pkt */
+typedef struct hci_cmd_pkt_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 params[255];
+} POSTPACK HCI_CMD_PKT;
+
+#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */
+/* Data pkt */
+typedef struct hci_acl_data_pkt_t {
+ A_UINT16 hdl_and_flags;
+ A_UINT16 data_len;
+ A_UINT8 data[Max80211_PAL_PDU_Size];
+} POSTPACK HCI_ACL_DATA_PKT;
+
+/* Event pkt */
+typedef struct hci_event_pkt_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 params[256];
+} POSTPACK HCI_EVENT_PKT;
+
+
+/*============== HCI Command definitions ======================= */
+typedef struct hci_cmd_phy_link_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+ A_UINT8 link_key_len;
+ A_UINT8 link_key_type;
+ A_UINT8 link_key[LINK_KEY_LEN];
+} POSTPACK HCI_CMD_PHY_LINK;
+
+typedef struct hci_cmd_write_rem_amp_assoc_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+ A_UINT16 len_so_far;
+ A_UINT16 amp_assoc_remaining_len;
+ A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
+} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC;
+
+
+typedef struct hci_cmd_opcode_hdl_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT16 hdl;
+} POSTPACK HCI_CMD_READ_LINK_QUAL,
+ HCI_CMD_FLUSH,
+ HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT;
+
+typedef struct hci_cmd_read_local_amp_assoc_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+ A_UINT16 len_so_far;
+ A_UINT16 max_rem_amp_assoc_len;
+} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC;
+
+
+typedef struct hci_cmd_set_event_mask_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT64 mask;
+}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2;
+
+
+typedef struct hci_cmd_enhanced_flush_t{
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT16 hdl;
+ A_UINT8 type;
+} POSTPACK HCI_CMD_ENHANCED_FLUSH;
+
+
+typedef struct hci_cmd_write_timeout_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT16 timeout;
+} POSTPACK HCI_CMD_WRITE_TIMEOUT;
+
+typedef struct hci_cmd_write_link_supervision_timeout_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT16 hdl;
+ A_UINT16 timeout;
+} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT;
+
+typedef struct hci_cmd_write_flow_control_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 mode;
+} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL;
+
+typedef struct location_data_cfg_t {
+ A_UINT8 reg_domain_aware;
+ A_UINT8 reg_domain[3];
+ A_UINT8 reg_options;
+} POSTPACK LOCATION_DATA_CFG;
+
+typedef struct hci_cmd_write_location_data_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ LOCATION_DATA_CFG cfg;
+} POSTPACK HCI_CMD_WRITE_LOCATION_DATA;
+
+
+typedef struct flow_spec_t {
+ A_UINT8 id;
+ A_UINT8 service_type;
+ A_UINT16 max_sdu;
+ A_UINT32 sdu_inter_arrival_time;
+ A_UINT32 access_latency;
+ A_UINT32 flush_timeout;
+} POSTPACK FLOW_SPEC;
+
+
+typedef struct hci_cmd_create_logical_link_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+ FLOW_SPEC tx_flow_spec;
+ FLOW_SPEC rx_flow_spec;
+} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK;
+
+typedef struct hci_cmd_flow_spec_modify_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT16 hdl;
+ FLOW_SPEC tx_flow_spec;
+ FLOW_SPEC rx_flow_spec;
+} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY;
+
+typedef struct hci_cmd_logical_link_cancel_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+ A_UINT8 tx_flow_spec_id;
+} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL;
+
+typedef struct hci_cmd_disconnect_logical_link_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT16 logical_link_hdl;
+} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK;
+
+typedef struct hci_cmd_disconnect_phy_link_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK;
+
+typedef struct hci_cmd_srm_t {
+ A_UINT16 opcode;
+ A_UINT8 param_length;
+ A_UINT8 phy_link_hdl;
+ A_UINT8 mode;
+} POSTPACK HCI_CMD_SHORT_RANGE_MODE;
+/*============== HCI Command definitions end ======================= */
+
+
+
+/*============== HCI Event definitions ============================= */
+
+/* Command complete event */
+typedef struct hci_event_cmd_complete_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 num_hci_cmd_pkts;
+ A_UINT16 opcode;
+ A_UINT8 params[255];
+} POSTPACK HCI_EVENT_CMD_COMPLETE;
+
+
+/* Command status event */
+typedef struct hci_event_cmd_status_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT8 num_hci_cmd_pkts;
+ A_UINT16 opcode;
+} POSTPACK HCI_EVENT_CMD_STATUS;
+
+/* Hardware Error event */
+typedef struct hci_event_hw_err_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 hw_err_code;
+} POSTPACK HCI_EVENT_HW_ERR;
+
+/* Flush occured event */
+/* Qos Violation event */
+typedef struct hci_event_handle_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT16 handle;
+} POSTPACK HCI_EVENT_FLUSH_OCCRD,
+ HCI_EVENT_QOS_VIOLATION;
+
+/* Loopback command event */
+typedef struct hci_loopback_cmd_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 params[252];
+} POSTPACK HCI_EVENT_LOOPBACK_CMD;
+
+/* Data buffer overflow event */
+typedef struct hci_data_buf_overflow_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 link_type;
+} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW;
+
+/* Enhanced Flush complete event */
+typedef struct hci_enhanced_flush_complt_t{
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT16 hdl;
+} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT;
+
+/* Channel select event */
+typedef struct hci_event_chan_select_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 phy_link_hdl;
+} POSTPACK HCI_EVENT_CHAN_SELECT;
+
+/* Physical Link Complete event */
+typedef struct hci_event_phy_link_complete_event_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT8 phy_link_hdl;
+} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE;
+
+/* Logical Link complete event */
+typedef struct hci_event_logical_link_complete_event_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT16 logical_link_hdl;
+ A_UINT8 phy_hdl;
+ A_UINT8 tx_flow_id;
+} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT;
+
+/* Disconnect Logical Link complete event */
+typedef struct hci_event_disconnect_logical_link_event_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT16 logical_link_hdl;
+ A_UINT8 reason;
+} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT;
+
+/* Disconnect Physical Link complete event */
+typedef struct hci_event_disconnect_phy_link_complete_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT8 phy_link_hdl;
+ A_UINT8 reason;
+} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE;
+
+typedef struct hci_event_physical_link_loss_early_warning_t{
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 phy_hdl;
+ A_UINT8 reason;
+} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING;
+
+typedef struct hci_event_physical_link_recovery_t{
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 phy_hdl;
+} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY;
+
+
+/* Flow spec modify complete event */
+/* Flush event */
+typedef struct hci_event_status_handle_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT16 handle;
+} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY,
+ HCI_EVENT_FLUSH;
+
+
+/* Num of completed data blocks event */
+typedef struct hci_event_num_of_compl_data_blks_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT16 num_data_blks;
+ A_UINT8 num_handles;
+ A_UINT8 params[255];
+} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS;
+
+/* Short range mode change complete event */
+typedef struct hci_srm_cmpl_t {
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT8 phy_link;
+ A_UINT8 state;
+} POSTPACK HCI_EVENT_SRM_COMPL;
+
+typedef struct hci_event_amp_status_change_t{
+ A_UINT8 event_code;
+ A_UINT8 param_len;
+ A_UINT8 status;
+ A_UINT8 amp_status;
+} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE;
+
+/*============== Event definitions end =========================== */
+
+
+typedef struct local_amp_info_resp_t {
+ A_UINT8 status;
+ A_UINT8 amp_status;
+ A_UINT32 total_bw; /* kbps */
+ A_UINT32 max_guranteed_bw; /* kbps */
+ A_UINT32 min_latency;
+ A_UINT32 max_pdu_size;
+ A_UINT8 amp_type;
+ A_UINT16 pal_capabilities;
+ A_UINT16 amp_assoc_len;
+ A_UINT32 max_flush_timeout; /* in ms */
+ A_UINT32 be_flush_timeout; /* in ms */
+} POSTPACK LOCAL_AMP_INFO;
+
+typedef struct amp_assoc_cmd_resp_t{
+ A_UINT8 status;
+ A_UINT8 phy_hdl;
+ A_UINT16 amp_assoc_len;
+ A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
+}POSTPACK AMP_ASSOC_CMD_RESP;
+
+
+enum PAL_HCI_CMD_STATUS {
+ PAL_HCI_CMD_PROCESSED,
+ PAL_HCI_CMD_IGNORED
+};
+
+
+/*============= HCI Error Codes =======================*/
+#define HCI_SUCCESS 0x00
+#define HCI_ERR_UNKNOW_CMD 0x01
+#define HCI_ERR_UNKNOWN_CONN_ID 0x02
+#define HCI_ERR_HW_FAILURE 0x03
+#define HCI_ERR_PAGE_TIMEOUT 0x04
+#define HCI_ERR_AUTH_FAILURE 0x05
+#define HCI_ERR_KEY_MISSING 0x06
+#define HCI_ERR_MEM_CAP_EXECED 0x07
+#define HCI_ERR_CON_TIMEOUT 0x08
+#define HCI_ERR_CON_LIMIT_EXECED 0x09
+#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B
+#define HCI_ERR_COMMAND_DISALLOWED 0x0C
+#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D
+#define HCI_ERR_CONN_REJ_BY_SEC 0x0E
+#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F
+#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10
+#define HCI_ERR_UNSUPPORT_FEATURE 0x11
+#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12
+#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13
+#define HCI_ERR_CON_TERM_BY_HOST 0x16
+#define HCI_ERR_UNSPECIFIED_ERROR 0x1F
+#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25
+#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27
+#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C
+#define HCI_ERR_QOS_REJECTED 0x2D
+#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39
+
+/*============= HCI Error Codes End =======================*/
+
+
+/* Following are event return parameters.. part of HCI events
+ */
+typedef struct timeout_read_t {
+ A_UINT8 status;
+ A_UINT16 timeout;
+}POSTPACK TIMEOUT_INFO;
+
+typedef struct link_supervision_timeout_read_t {
+ A_UINT8 status;
+ A_UINT16 hdl;
+ A_UINT16 timeout;
+}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO;
+
+typedef struct status_hdl_t {
+ A_UINT8 status;
+ A_UINT16 hdl;
+}POSTPACK INFO_STATUS_HDL;
+
+typedef struct write_remote_amp_assoc_t{
+ A_UINT8 status;
+ A_UINT8 hdl;
+}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO;
+
+typedef struct read_loc_info_t {
+ A_UINT8 status;
+ LOCATION_DATA_CFG loc;
+}POSTPACK READ_LOC_INFO;
+
+typedef struct read_flow_ctrl_mode_t {
+ A_UINT8 status;
+ A_UINT8 mode;
+}POSTPACK READ_FLWCTRL_INFO;
+
+typedef struct read_data_blk_size_t {
+ A_UINT8 status;
+ A_UINT16 max_acl_data_pkt_len;
+ A_UINT16 data_block_len;
+ A_UINT16 total_num_data_blks;
+}POSTPACK READ_DATA_BLK_SIZE_INFO;
+
+/* Read Link quality info */
+typedef struct link_qual_t {
+ A_UINT8 status;
+ A_UINT16 hdl;
+ A_UINT8 link_qual;
+} POSTPACK READ_LINK_QUAL_INFO,
+ READ_RSSI_INFO;
+
+typedef struct ll_cancel_resp_t {
+ A_UINT8 status;
+ A_UINT8 phy_link_hdl;
+ A_UINT8 tx_flow_spec_id;
+} POSTPACK LL_CANCEL_RESP;
+
+typedef struct read_local_ver_info_t {
+ A_UINT8 status;
+ A_UINT8 hci_version;
+ A_UINT16 hci_revision;
+ A_UINT8 pal_version;
+ A_UINT16 manf_name;
+ A_UINT16 pal_sub_ver;
+} POSTPACK READ_LOCAL_VER_INFO;
+
+
+#endif /* __A_HCI_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/a_osapi.h b/drivers/net/wireless/ath6kl/include/a_osapi.h
new file mode 100644
index 000000000000..17138cec2f77
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_osapi.h
@@ -0,0 +1,53 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_osapi.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_OSAPI_H_
+#define _A_OSAPI_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/osapi_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/osapi.h"
+#include "../os/windows/include/netbuf.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/osapi.h"
+#include "../os/windows/include/netbuf.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/osapi_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/osapi_win.h"
+#include "../os/win_art/include/netbuf.h"
+#endif
+
+#ifdef WIN_NWF
+#include <osapi_win.h>
+#endif
+
+#endif /* _OSAPI_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/a_types.h b/drivers/net/wireless/ath6kl/include/a_types.h
new file mode 100644
index 000000000000..bf4f1a485b45
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/a_types.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// <copyright file="a_types.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions of the basic atheros data types.
+// It is used to map the data types in atheros files to a platform specific
+// type.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _A_TYPES_H_
+#define _A_TYPES_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/athtypes_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athtypes.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athtypes.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/athtypes_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/athtypes_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include <athtypes_win.h>
+#endif
+
+#endif /* _ATHTYPES_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/aggr_recv_api.h b/drivers/net/wireless/ath6kl/include/aggr_recv_api.h
new file mode 100644
index 000000000000..185354eddcde
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/aggr_recv_api.h
@@ -0,0 +1,136 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef __AGGR_RECV_API_H__
+#define __AGGR_RECV_API_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (* RX_CALLBACK)(void * dev, void *osbuf);
+
+typedef void (* ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, A_UINT16 num);
+
+/*
+ * aggr_init:
+ * Initialises the data structures, allocates data queues and
+ * os buffers. Netbuf allocator is the input param, used by the
+ * aggr module for allocation of NETBUFs from driver context.
+ * These NETBUFs are used for AMSDU processing.
+ * Returns the context for the aggr module.
+ */
+void *
+aggr_init(ALLOC_NETBUFS netbuf_allocator);
+
+
+/*
+ * aggr_register_rx_dispatcher:
+ * Registers OS call back function to deliver the
+ * frames to OS. This is generally the topmost layer of
+ * the driver context, after which the frames go to
+ * IP stack via the call back function.
+ * This dispatcher is active only when aggregation is ON.
+ */
+void
+aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn);
+
+
+/*
+ * aggr_process_bar:
+ * When target receives BAR, it communicates to host driver
+ * for modifying window parameters. Target indicates this via the
+ * event: WMI_ADDBA_REQ_EVENTID. Host will dequeue all frames
+ * up to the indicated sequence number.
+ */
+void
+aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no);
+
+
+/*
+ * aggr_recv_addba_req_evt:
+ * This event is to initiate/modify the receive side window.
+ * Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup
+ * recv re-ordering queues. Target will negotiate ADDBA with peer,
+ * and indicate via this event after succesfully completing the
+ * negotiation. This happens in two situations:
+ * 1. Initial setup of aggregation
+ * 2. Renegotiation of current recv window.
+ * Window size for re-ordering is limited by target buffer
+ * space, which is reflected in win_sz.
+ * (Re)Start the periodic timer to deliver long standing frames,
+ * in hold_q to OS.
+ */
+void
+aggr_recv_addba_req_evt(void * cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz);
+
+
+/*
+ * aggr_recv_delba_req_evt:
+ * Target indicates deletion of a BA window for a tid via the
+ * WMI_DELBA_EVENTID. Host would deliver all the frames in the
+ * hold_q, reset tid config and disable the periodic timer, if
+ * aggr is not enabled on any tid.
+ */
+void
+aggr_recv_delba_req_evt(void * cntxt, A_UINT8 tid);
+
+
+
+/*
+ * aggr_process_recv_frm:
+ * Called only for data frames. When aggr is ON for a tid, the buffer
+ * is always consumed, and osbuf would be NULL. For a non-aggr case,
+ * osbuf is not modified.
+ * AMSDU frames are consumed and are later freed. They are sliced and
+ * diced to individual frames and dispatched to stack.
+ * After consuming a osbuf(when aggr is ON), a previously registered
+ * callback may be called to deliver frames in order.
+ */
+void
+aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf);
+
+
+/*
+ * aggr_module_destroy:
+ * Frees up all the queues and frames in them. Releases the cntxt to OS.
+ */
+void
+aggr_module_destroy(void *cntxt);
+
+/*
+ * Dumps the aggregation stats
+ */
+void
+aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf);
+
+/*
+ * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
+ * hold Q state. Examples include when a Connect event or disconnect event is
+ * received.
+ */
+void
+aggr_reset_state(void *cntxt);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AGGR_RECV_API_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/ar3kconfig.h b/drivers/net/wireless/ath6kl/include/ar3kconfig.h
new file mode 100644
index 000000000000..8d7bf2a6ec75
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar3kconfig.h
@@ -0,0 +1,58 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar3Kconfig.h" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/* AR3K module configuration APIs for HCI-bridge operation */
+
+#ifndef AR3KCONFIG_H_
+#define AR3KCONFIG_H_
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT (1 << 0)
+#define AR3K_CONFIG_FLAG_SET_AR3K_BAUD (1 << 1)
+#define AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY (1 << 2)
+#define AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP (1 << 3)
+
+
+typedef struct {
+ A_UINT32 Flags; /* config flags */
+ void *pHCIDev; /* HCI bridge device */
+ HCI_TRANSPORT_PROPERTIES *pHCIProps; /* HCI bridge props */
+ HIF_DEVICE *pHIFDevice; /* HIF layer device */
+
+ A_UINT32 AR3KBaudRate; /* AR3K operational baud rate */
+ A_UINT16 AR6KScale; /* AR6K UART scale value */
+ A_UINT16 AR6KStep; /* AR6K UART step value */
+ struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */
+} AR3K_CONFIG_INFO;
+
+A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfigInfo);
+
+A_STATUS AR3KConfigureExit(void *config);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*AR3KCONFIG_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/ar6000_api.h b/drivers/net/wireless/ath6kl/include/ar6000_api.h
new file mode 100644
index 000000000000..431520fb0b1c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar6000_api.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6000_api.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the API to access the OS dependent atheros host driver
+// by the WMI or WLAN generic modules.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _AR6000_API_H_
+#define _AR6000_API_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "../os/linux/include/ar6xapi_linux.h"
+#endif
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#ifdef REXOS
+#include "../os/rexos/include/common/ar6xapi_rexos.h"
+#endif
+
+#if defined ART_WIN
+#include "../os/win_art/include/ar6xapi_win.h"
+#endif
+
+#ifdef WIN_NWF
+#include "../os/windows/include/ar6xapi.h"
+#endif
+
+#endif /* _AR6000_API_H */
+
diff --git a/drivers/net/wireless/ath6kl/include/ar6000_diag.h b/drivers/net/wireless/ath6kl/include/ar6000_diag.h
new file mode 100644
index 000000000000..ae87e2b23b6e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar6000_diag.h
@@ -0,0 +1,44 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar6000_diag.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef AR6000_DIAG_H_
+#define AR6000_DIAG_H_
+
+
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval);
+
+void
+ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs);
+
+#endif /*AR6000_DIAG_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/ar6kap_common.h b/drivers/net/wireless/ath6kl/include/ar6kap_common.h
new file mode 100644
index 000000000000..87b183c45bf5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ar6kap_common.h
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+
+// <copyright file="ar6kap_common.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+
+//==============================================================================
+
+// This file contains the definitions of common AP mode data structures.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _AR6KAP_COMMON_H_
+#define _AR6KAP_COMMON_H_
+/*
+ * Used with AR6000_XIOCTL_AP_GET_STA_LIST
+ */
+typedef struct {
+ A_UINT8 mac[ATH_MAC_LEN];
+ A_UINT8 aid;
+ A_UINT8 keymgmt;
+ A_UINT8 ucipher;
+ A_UINT8 auth;
+} station_t;
+typedef struct {
+ station_t sta[AP_MAX_NUM_STA];
+} ap_get_sta_t;
+#endif /* _AR6KAP_COMMON_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/athbtfilter.h b/drivers/net/wireless/ath6kl/include/athbtfilter.h
new file mode 100644
index 000000000000..4ea3fa5b2f5d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athbtfilter.h
@@ -0,0 +1,129 @@
+//------------------------------------------------------------------------------
+// <copyright file="athbtfilter.h" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Public Bluetooth filter APIs
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef ATHBTFILTER_H_
+#define ATHBTFILTER_H_
+
+
+typedef enum _ATHBT_HCI_CTRL_TYPE {
+ ATHBT_HCI_COMMAND = 0,
+ ATHBT_HCI_EVENT = 1,
+} ATHBT_HCI_CTRL_TYPE;
+
+typedef enum _ATHBT_STATE_INDICATION {
+ ATH_BT_NOOP = 0,
+ ATH_BT_INQUIRY = 1,
+ ATH_BT_CONNECT = 2,
+ ATH_BT_SCO = 3,
+ ATH_BT_ACL = 4,
+ ATH_BT_A2DP = 5,
+ ATH_BT_ESCO = 6,
+ /* new states go here.. */
+
+ ATH_BT_MAX_STATE_INDICATION
+} ATHBT_STATE_INDICATION;
+
+ /* filter function for OUTGOING commands and INCOMMING events */
+typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length);
+
+ /* filter function for OUTGOING data HCI packets */
+typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length);
+
+typedef enum _ATHBT_STATE {
+ STATE_OFF = 0,
+ STATE_ON = 1,
+ STATE_MAX
+} ATHBT_STATE;
+
+ /* BT state indication (when filter functions are not used) */
+
+typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion);
+
+typedef struct _ATHBT_FILTER_INSTANCE {
+#ifdef UNDER_CE
+ WCHAR *pWlanAdapterName; /* filled in by user */
+#else
+ A_CHAR *pWlanAdapterName; /* filled in by user */
+#endif /* UNDER_CE */
+ int FilterEnabled; /* filtering is enabled */
+ int Attached; /* filter library is attached */
+ void *pContext; /* private context for filter library */
+ ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */
+ ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */
+ ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */
+ ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */
+} ATH_BT_FILTER_INSTANCE;
+
+
+/* API MACROS */
+
+#define AthBtFilterHciCommand(instance,packet,length) \
+ if ((instance)->FilterEnabled) { \
+ (instance)->pFilterCmdEvents((instance)->pContext, \
+ ATHBT_HCI_COMMAND, \
+ (unsigned char *)(packet), \
+ (length)); \
+ }
+
+#define AthBtFilterHciEvent(instance,packet,length) \
+ if ((instance)->FilterEnabled) { \
+ (instance)->pFilterCmdEvents((instance)->pContext, \
+ ATHBT_HCI_EVENT, \
+ (unsigned char *)(packet), \
+ (length)); \
+ }
+
+#define AthBtFilterHciAclDataOut(instance,packet,length) \
+ if ((instance)->FilterEnabled) { \
+ (instance)->pFilterAclDataOut((instance)->pContext, \
+ (unsigned char *)(packet), \
+ (length)); \
+ }
+
+#define AthBtFilterHciAclDataIn(instance,packet,length) \
+ if ((instance)->FilterEnabled) { \
+ (instance)->pFilterAclDataIn((instance)->pContext, \
+ (unsigned char *)(packet), \
+ (length)); \
+ }
+
+/* if filtering is not desired, the application can indicate the state directly using this
+ * macro:
+ */
+#define AthBtIndicateState(instance,indication,state) \
+ if ((instance)->FilterEnabled) { \
+ (instance)->pIndicateState((instance)->pContext, \
+ (indication), \
+ (state), \
+ 0); \
+ }
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* API prototypes */
+int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance, A_UINT32 flags);
+void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*ATHBTFILTER_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/athdefs.h b/drivers/net/wireless/ath6kl/include/athdefs.h
new file mode 100644
index 000000000000..cc8bb3cc81be
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athdefs.h
@@ -0,0 +1,80 @@
+//------------------------------------------------------------------------------
+// <copyright file="athdefs.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __ATHDEFS_H__
+#define __ATHDEFS_H__
+
+/*
+ * This file contains definitions that may be used across both
+ * Host and Target software. Nothing here is module-dependent
+ * or platform-dependent.
+ */
+
+/*
+ * Generic error codes that can be used by hw, sta, ap, sim, dk
+ * and any other environments. Since these are enums, feel free to
+ * add any more codes that you need.
+ */
+
+typedef enum {
+ A_ERROR = -1, /* Generic error return */
+ A_OK = 0, /* success */
+ /* Following values start at 1 */
+ A_DEVICE_NOT_FOUND, /* not able to find PCI device */
+ A_NO_MEMORY, /* not able to allocate memory, not available */
+ A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
+ A_NO_FREE_DESC, /* no free descriptors available */
+ A_BAD_ADDRESS, /* address does not match descriptor */
+ A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
+ A_REGS_NOT_MAPPED, /* registers not correctly mapped */
+ A_EPERM, /* Not superuser */
+ A_EACCES, /* Access denied */
+ A_ENOENT, /* No such entry, search failed, etc. */
+ A_EEXIST, /* The object already exists (can't create) */
+ A_EFAULT, /* Bad address fault */
+ A_EBUSY, /* Object is busy */
+ A_EINVAL, /* Invalid parameter */
+ A_EMSGSIZE, /* Inappropriate message buffer length */
+ A_ECANCELED, /* Operation canceled */
+ A_ENOTSUP, /* Operation not supported */
+ A_ECOMM, /* Communication error on send */
+ A_EPROTO, /* Protocol error */
+ A_ENODEV, /* No such device */
+ A_EDEVNOTUP, /* device is not UP */
+ A_NO_RESOURCE, /* No resources for requested operation */
+ A_HARDWARE, /* Hardware failure */
+ A_PENDING, /* Asynchronous routine; will send up results la
+ter (typically in callback) */
+ A_EBADCHANNEL, /* The channel cannot be used */
+ A_DECRYPT_ERROR, /* Decryption error */
+ A_PHY_ERROR, /* RX PHY error */
+ A_CONSUMED /* Object was consumed */
+} A_STATUS;
+
+#define A_SUCCESS(x) (x == A_OK)
+#define A_FAILED(x) (!A_SUCCESS(x))
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif /* __ATHDEFS_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/athendpack.h b/drivers/net/wireless/ath6kl/include/athendpack.h
new file mode 100644
index 000000000000..b0c7e1425f74
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athendpack.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="athendpack.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// end compiler-specific structure packing
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athendpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athendpack.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athendpack.h"
+#endif /* WINCE */
+
+#ifdef WIN_NWF
+#include <athendpack_win.h>
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/athstartpack.h b/drivers/net/wireless/ath6kl/include/athstartpack.h
new file mode 100644
index 000000000000..04b3cc240b35
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/athstartpack.h
@@ -0,0 +1,47 @@
+//------------------------------------------------------------------------------
+// <copyright file="athstartpack.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// start compiler-specific structure packing
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athstartpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+#ifdef UNDER_NWIFI
+#include "../os/windows/include/athstartpack.h"
+#endif
+
+#ifdef ATHR_CE_LEGACY
+#include "../os/windows/include/athstartpack.h"
+#endif /* WINCE */
+
+#ifdef WIN_NWF
+#include <athstartpack_win.h>
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/bmi.h b/drivers/net/wireless/ath6kl/include/bmi.h
new file mode 100644
index 000000000000..64e817ed6929
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/bmi.h
@@ -0,0 +1,128 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// BMI declarations and prototypes
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _BMI_H_
+#define _BMI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "hif.h"
+#include "a_osapi.h"
+#include "bmi_msg.h"
+
+void
+BMIInit(void);
+
+A_STATUS
+BMIDone(HIF_DEVICE *device);
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param);
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+ A_UINT32 address);
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param);
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 param);
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+ A_UINT32 ROM_addr,
+ A_UINT32 RAM_addr,
+ A_UINT32 nbytes,
+ A_UINT32 do_activate,
+ A_UINT32 *patch_id);
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+ A_UINT32 rompatch_id);
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list);
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list);
+
+A_STATUS
+BMILZStreamStart(HIF_DEVICE *device,
+ A_UINT32 address);
+
+A_STATUS
+BMILZData(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIFastDownload(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIRawWrite(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIRawRead(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_BOOL want_timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BMI_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/bmi_msg.h b/drivers/net/wireless/ath6kl/include/bmi_msg.h
new file mode 100644
index 000000000000..1f48389f9664
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/bmi_msg.h
@@ -0,0 +1,231 @@
+//------------------------------------------------------------------------------
+// <copyright file="bmi_msg.h" company="Atheros">
+// Copyright (c) 2004-2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __BMI_MSG_H__
+#define __BMI_MSG_H__
+
+/*
+ * Bootloader Messaging Interface (BMI)
+ *
+ * BMI is a very simple messaging interface used during initialization
+ * to read memory, write memory, execute code, and to define an
+ * application entry PC.
+ *
+ * It is used to download an application to AR6K, to provide
+ * patches to code that is already resident on AR6K, and generally
+ * to examine and modify state. The Host has an opportunity to use
+ * BMI only once during bootup. Once the Host issues a BMI_DONE
+ * command, this opportunity ends.
+ *
+ * The Host writes BMI requests to mailbox0, and reads BMI responses
+ * from mailbox0. BMI requests all begin with a command
+ * (see below for specific commands), and are followed by
+ * command-specific data.
+ *
+ * Flow control:
+ * The Host can only issue a command once the Target gives it a
+ * "BMI Command Credit", using AR6K Counter #4. As soon as the
+ * Target has completed a command, it issues another BMI Command
+ * Credit (so the Host can issue the next command).
+ *
+ * BMI handles all required Target-side cache flushing.
+ */
+
+
+/* Maximum data size used for BMI transfers */
+#define BMI_DATASZ_MAX 256
+
+/* BMI Commands */
+
+#define BMI_NO_COMMAND 0
+
+#define BMI_DONE 1
+ /*
+ * Semantics: Host is done using BMI
+ * Request format:
+ * A_UINT32 command (BMI_DONE)
+ * Response format: none
+ */
+
+#define BMI_READ_MEMORY 2
+ /*
+ * Semantics: Host reads AR6K memory
+ * Request format:
+ * A_UINT32 command (BMI_READ_MEMORY)
+ * A_UINT32 address
+ * A_UINT32 length, at most BMI_DATASZ_MAX
+ * Response format:
+ * A_UINT8 data[length]
+ */
+
+#define BMI_WRITE_MEMORY 3
+ /*
+ * Semantics: Host writes AR6K memory
+ * Request format:
+ * A_UINT32 command (BMI_WRITE_MEMORY)
+ * A_UINT32 address
+ * A_UINT32 length, at most BMI_DATASZ_MAX
+ * A_UINT8 data[length]
+ * Response format: none
+ */
+
+#define BMI_EXECUTE 4
+ /*
+ * Semantics: Causes AR6K to execute code
+ * Request format:
+ * A_UINT32 command (BMI_EXECUTE)
+ * A_UINT32 address
+ * A_UINT32 parameter
+ * Response format:
+ * A_UINT32 return value
+ */
+
+#define BMI_SET_APP_START 5
+ /*
+ * Semantics: Set Target application starting address
+ * Request format:
+ * A_UINT32 command (BMI_SET_APP_START)
+ * A_UINT32 address
+ * Response format: none
+ */
+
+#define BMI_READ_SOC_REGISTER 6
+ /*
+ * Semantics: Read a 32-bit Target SOC register.
+ * Request format:
+ * A_UINT32 command (BMI_READ_REGISTER)
+ * A_UINT32 address
+ * Response format:
+ * A_UINT32 value
+ */
+
+#define BMI_WRITE_SOC_REGISTER 7
+ /*
+ * Semantics: Write a 32-bit Target SOC register.
+ * Request format:
+ * A_UINT32 command (BMI_WRITE_REGISTER)
+ * A_UINT32 address
+ * A_UINT32 value
+ *
+ * Response format: none
+ */
+
+#define BMI_GET_TARGET_ID 8
+#define BMI_GET_TARGET_INFO 8
+ /*
+ * Semantics: Fetch the 4-byte Target information
+ * Request format:
+ * A_UINT32 command (BMI_GET_TARGET_ID/INFO)
+ * Response format1 (old firmware):
+ * A_UINT32 TargetVersionID
+ * Response format2 (newer firmware):
+ * A_UINT32 TARGET_VERSION_SENTINAL
+ * struct bmi_target_info;
+ */
+
+struct bmi_target_info {
+ A_UINT32 target_info_byte_count; /* size of this structure */
+ A_UINT32 target_ver; /* Target Version ID */
+ A_UINT32 target_type; /* Target type */
+};
+#define TARGET_VERSION_SENTINAL 0xffffffff
+#define TARGET_TYPE_AR6001 1
+#define TARGET_TYPE_AR6002 2
+#define TARGET_TYPE_AR6003 3
+
+
+#define BMI_ROMPATCH_INSTALL 9
+ /*
+ * Semantics: Install a ROM Patch.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_INSTALL)
+ * A_UINT32 Target ROM Address
+ * A_UINT32 Target RAM Address or Value (depending on Target Type)
+ * A_UINT32 Size, in bytes
+ * A_UINT32 Activate? 1-->activate;
+ * 0-->install but do not activate
+ * Response format:
+ * A_UINT32 PatchID
+ */
+
+#define BMI_ROMPATCH_UNINSTALL 10
+ /*
+ * Semantics: Uninstall a previously-installed ROM Patch,
+ * automatically deactivating, if necessary.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
+ * A_UINT32 PatchID
+ *
+ * Response format: none
+ */
+
+#define BMI_ROMPATCH_ACTIVATE 11
+ /*
+ * Semantics: Activate a list of previously-installed ROM Patches.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
+ * A_UINT32 rompatch_count
+ * A_UINT32 PatchID[rompatch_count]
+ *
+ * Response format: none
+ */
+
+#define BMI_ROMPATCH_DEACTIVATE 12
+ /*
+ * Semantics: Deactivate a list of active ROM Patches.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
+ * A_UINT32 rompatch_count
+ * A_UINT32 PatchID[rompatch_count]
+ *
+ * Response format: none
+ */
+
+
+#define BMI_LZ_STREAM_START 13
+ /*
+ * Semantics: Begin an LZ-compressed stream of input
+ * which is to be uncompressed by the Target to an
+ * output buffer at address. The output buffer must
+ * be sufficiently large to hold the uncompressed
+ * output from the compressed input stream. This BMI
+ * command should be followed by a series of 1 or more
+ * BMI_LZ_DATA commands.
+ * A_UINT32 command (BMI_LZ_STREAM_START)
+ * A_UINT32 address
+ * Note: Not supported on all versions of ROM firmware.
+ */
+
+#define BMI_LZ_DATA 14
+ /*
+ * Semantics: Host writes AR6K memory with LZ-compressed
+ * data which is uncompressed by the Target. This command
+ * must be preceded by a BMI_LZ_STREAM_START command. A series
+ * of BMI_LZ_DATA commands are considered part of a single
+ * input stream until another BMI_LZ_STREAM_START is issued.
+ * Request format:
+ * A_UINT32 command (BMI_LZ_DATA)
+ * A_UINT32 length (of compressed data),
+ * at most BMI_DATASZ_MAX
+ * A_UINT8 CompressedData[length]
+ * Response format: none
+ * Note: Not supported on all versions of ROM firmware.
+ */
+
+#endif /* __BMI_MSG_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/btcoexGpio.h b/drivers/net/wireless/ath6kl/include/btcoexGpio.h
new file mode 100644
index 000000000000..8ed52a34fb1e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/btcoexGpio.h
@@ -0,0 +1,68 @@
+#ifndef BTCOEX_GPIO_H_
+#define BTCOEX_GPIO_H_
+
+
+
+#ifdef FPGA
+#define GPIO_A (15)
+#define GPIO_B (16)
+#define GPIO_C (17)
+#define GPIO_D (18)
+#define GPIO_E (19)
+#define GPIO_F (21)
+#define GPIO_G (21)
+#else
+#define GPIO_A (0)
+#define GPIO_B (5)
+#define GPIO_C (6)
+#define GPIO_D (7)
+#define GPIO_E (7)
+#define GPIO_F (7)
+#define GPIO_G (7)
+#endif
+
+
+
+
+
+#define GPIO_DEBUG_WORD_1 (1<<GPIO_A)
+#define GPIO_DEBUG_WORD_2 (1<<GPIO_B)
+#define GPIO_DEBUG_WORD_3 ((1<<GPIO_B) | (1<<GPIO_A))
+#define GPIO_DEBUG_WORD_4 (1<<GPIO_C)
+#define GPIO_DEBUG_WORD_5 ((1<<GPIO_C) | (1<<GPIO_A))
+#define GPIO_DEBUG_WORD_6 ((1<<GPIO_C) | (1<<GPIO_B))
+#define GPIO_DEBUG_WORD_7 ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A))
+
+#define GPIO_DEBUG_WORD_8 (1<<GPIO_D)
+#define GPIO_DEBUG_WORD_9 ((1<<GPIO_D) | GPIO_DEBUG_WORD_1)
+#define GPIO_DEBUG_WORD_10 ((1<<GPIO_D) | GPIO_DEBUG_WORD_2)
+#define GPIO_DEBUG_WORD_11 ((1<<GPIO_D) | GPIO_DEBUG_WORD_3)
+#define GPIO_DEBUG_WORD_12 ((1<<GPIO_D) | GPIO_DEBUG_WORD_4)
+#define GPIO_DEBUG_WORD_13 ((1<<GPIO_D) | GPIO_DEBUG_WORD_5)
+#define GPIO_DEBUG_WORD_14 ((1<<GPIO_D) | GPIO_DEBUG_WORD_6)
+#define GPIO_DEBUG_WORD_15 ((1<<GPIO_D) | GPIO_DEBUG_WORD_7)
+
+#define GPIO_DEBUG_WORD_16 (1<<GPIO_E)
+#define GPIO_DEBUG_WORD_17 ((1<<GPIO_E) | GPIO_DEBUG_WORD_1)
+#define GPIO_DEBUG_WORD_18 ((1<<GPIO_E) | GPIO_DEBUG_WORD_2)
+#define GPIO_DEBUG_WORD_19 ((1<<GPIO_E) | GPIO_DEBUG_WORD_3)
+#define GPIO_DEBUG_WORD_20 ((1<<GPIO_E) | GPIO_DEBUG_WORD_4)
+#define GPIO_DEBUG_WORD_21 ((1<<GPIO_E) | GPIO_DEBUG_WORD_5)
+#define GPIO_DEBUG_WORD_22 ((1<<GPIO_E) | GPIO_DEBUG_WORD_6)
+#define GPIO_DEBUG_WORD_23 ((1<<GPIO_E) | GPIO_DEBUG_WORD_7)
+
+
+
+extern void btcoexDbgPulseWord(A_UINT32 gpioPinMask);
+extern void btcoexDbgPulse(A_UINT32 pin);
+
+#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
+#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) (btcoexDbgPulseWord(gpioPinMask))
+#define BTCOEX_DBG_PULSE(pin) (btcoexDbgPulse(pin))
+#else
+#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)
+#define BTCOEX_DBG_PULSE(pin)
+
+#endif
+#endif
+
diff --git a/drivers/net/wireless/ath6kl/include/cnxmgmt.h b/drivers/net/wireless/ath6kl/include/cnxmgmt.h
new file mode 100644
index 000000000000..0c956fb6b9d5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/cnxmgmt.h
@@ -0,0 +1,32 @@
+//------------------------------------------------------------------------------
+// <copyright file="cnxmgmt.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _CNXMGMT_H_
+#define _CNXMGMT_H_
+
+typedef enum {
+ CM_CONNECT_WITHOUT_SCAN = 0x0001,
+ CM_CONNECT_ASSOC_POLICY_USER = 0x0002,
+ CM_CONNECT_SEND_REASSOC = 0x0004,
+ CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008,
+ CM_CONNECT_DO_WPA_OFFLOAD = 0x0010,
+ CM_CONNECT_DO_NOT_DEAUTH = 0x0020,
+} CM_CONNECT_TYPE;
+
+#endif /* _CNXMGMT_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/common_drv.h b/drivers/net/wireless/ath6kl/include/common_drv.h
new file mode 100644
index 000000000000..286490188605
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/common_drv.h
@@ -0,0 +1,90 @@
+//------------------------------------------------------------------------------
+// <copyright file="common_drv.h" company="Atheros">
+// Copyright (c) 2010 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef COMMON_DRV_H_
+#define COMMON_DRV_H_
+
+#include "hif.h"
+#include "htc_packet.h"
+#include "htc_api.h"
+
+/* structure that is the state information for the default credit distribution callback
+ * drivers should instantiate (zero-init as well) this structure in their driver instance
+ * and pass it as a context to the HTC credit distribution functions */
+typedef struct _COMMON_CREDIT_STATE_INFO {
+ int TotalAvailableCredits; /* total credits in the system at startup */
+ int CurrentFreeCredits; /* credits available in the pool that have not been
+ given out to endpoints */
+ HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */
+} COMMON_CREDIT_STATE_INFO;
+
+typedef struct {
+ A_INT32 (*setupTransport)(void *ar);
+ void (*cleanupTransport)(void *ar);
+} HCI_TRANSPORT_CALLBACKS;
+
+typedef struct {
+ void *netDevice;
+ void *hifDevice;
+ void *htcHandle;
+} HCI_TRANSPORT_MISC_HANDLES;
+
+/* HTC TX packet tagging definitions */
+#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
+#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1)
+
+#define AR6002_VERSION_REV1 0x20000086
+#define AR6002_VERSION_REV2 0x20000188
+#define AR6003_VERSION_REV1 0x300002ba
+#define AR6003_VERSION_REV2 0x30000384
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* OS-independent APIs */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length);
+
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset);
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
+
+A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
+ A_UINT32 TargetType,
+ A_UINT32 MboxIsrYieldValue,
+ A_UINT8 HtcControlBuffers);
+
+A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice,
+ A_UINT32 TargetType,
+ A_UINT32 TargetVersion);
+
+A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
+ A_UINT32 TargetType,
+ A_UINT32 Flags);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*COMMON_DRV_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/dbglog.h b/drivers/net/wireless/ath6kl/include/dbglog.h
new file mode 100644
index 000000000000..ae05eb66c21a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dbglog.h
@@ -0,0 +1,122 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DBGLOG_H_
+#define _DBGLOG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DBGLOG_TIMESTAMP_OFFSET 0
+#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit
+ 8-23 of the LF0 timer */
+#define DBGLOG_DBGID_OFFSET 16
+#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */
+#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULEID_OFFSET 26
+#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */
+#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */
+
+/*
+ * Please ensure that the definition of any new module intrduced is captured
+ * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
+ * structure is required for the parser to correctly pick up the values for
+ * different modules.
+ */
+#define DBGLOG_MODULEID_START
+#define DBGLOG_MODULEID_INF 0
+#define DBGLOG_MODULEID_WMI 1
+#define DBGLOG_MODULEID_MISC 2
+#define DBGLOG_MODULEID_PM 3
+#define DBGLOG_MODULEID_TXRX_MGMTBUF 4
+#define DBGLOG_MODULEID_TXRX_TXBUF 5
+#define DBGLOG_MODULEID_TXRX_RXBUF 6
+#define DBGLOG_MODULEID_WOW 7
+#define DBGLOG_MODULEID_WHAL 8
+#define DBGLOG_MODULEID_DC 9
+#define DBGLOG_MODULEID_CO 10
+#define DBGLOG_MODULEID_RO 11
+#define DBGLOG_MODULEID_CM 12
+#define DBGLOG_MODULEID_MGMT 13
+#define DBGLOG_MODULEID_TMR 14
+#define DBGLOG_MODULEID_BTCOEX 15
+#define DBGLOG_MODULEID_END
+
+#define DBGLOG_NUM_ARGS_OFFSET 30
+#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */
+#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0
+#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF
+
+#define DBGLOG_REPORTING_ENABLED_OFFSET 16
+#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000
+
+#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
+#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000
+
+#define DBGLOG_REPORT_SIZE_OFFSET 20
+#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000
+
+#define DBGLOG_LOG_BUFFER_SIZE 1500
+#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
+
+struct dbglog_buf_s {
+ struct dbglog_buf_s *next;
+ A_UINT8 *buffer;
+ A_UINT32 bufsize;
+ A_UINT32 length;
+ A_UINT32 count;
+ A_UINT32 free;
+};
+
+struct dbglog_hdr_s {
+ struct dbglog_buf_s *dbuf;
+ A_UINT32 dropped;
+};
+
+struct dbglog_config_s {
+ A_UINT32 cfgvalid; /* Mask with valid config bits */
+ union {
+ /* TODO: Take care of endianness */
+ struct {
+ A_UINT32 mmask:16; /* Mask of modules with logging on */
+ A_UINT32 rep:1; /* Reporting enabled or not */
+ A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */
+ A_UINT32 size:10; /* Report size in number of messages */
+ A_UINT32 reserved:2;
+ } dbglog_config;
+
+ A_UINT32 value;
+ } u;
+};
+
+#define cfgmmask u.dbglog_config.mmask
+#define cfgrep u.dbglog_config.rep
+#define cfgtsr u.dbglog_config.tsr
+#define cfgsize u.dbglog_config.size
+#define cfgvalue u.value
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dbglog_api.h b/drivers/net/wireless/ath6kl/include/dbglog_api.h
new file mode 100644
index 000000000000..4710b4c140fc
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dbglog_api.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog_api.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains host side debug primitives.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _DBGLOG_API_H_
+#define _DBGLOG_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dbglog.h"
+
+#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
+
+#define DBGLOG_GET_DBGID(arg) \
+ ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
+
+#define DBGLOG_GET_MODULEID(arg) \
+ ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
+
+#define DBGLOG_GET_NUMARGS(arg) \
+ ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
+
+#define DBGLOG_GET_TIMESTAMP(arg) \
+ ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dbglog_id.h b/drivers/net/wireless/ath6kl/include/dbglog_id.h
new file mode 100644
index 000000000000..b5cd521a260f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dbglog_id.h
@@ -0,0 +1,530 @@
+//------------------------------------------------------------------------------
+// <copyright file="dbglog_id.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DBGLOG_ID_H_
+#define _DBGLOG_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
+ * Please ensure that the definition of any new debugid introduced is captured
+ * between the <MODULE>_DBGID_DEFINITION_START and
+ * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
+ * parser to correctly pick up the values for different debug identifiers.
+ */
+
+/* INF debug identifier definitions */
+#define INF_DBGID_DEFINITION_START
+#define INF_ASSERTION_FAILED 1
+#define INF_TARGET_ID 2
+#define INF_DBGID_DEFINITION_END
+
+/* WMI debug identifier definitions */
+#define WMI_DBGID_DEFINITION_START
+#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1
+#define WMI_EXTENDED_CMD_NOT_HANDLED 2
+#define WMI_CMD_RX_PKT_TOO_SHORT 3
+#define WMI_CALLING_WMI_EXTENSION_FN 4
+#define WMI_CMD_NOT_HANDLED 5
+#define WMI_IN_SYNC 6
+#define WMI_TARGET_WMI_SYNC_CMD 7
+#define WMI_SET_SNR_THRESHOLD_PARAMS 8
+#define WMI_SET_RSSI_THRESHOLD_PARAMS 9
+#define WMI_SET_LQ_TRESHOLD_PARAMS 10
+#define WMI_TARGET_CREATE_PSTREAM_CMD 11
+#define WMI_WI_DTM_INUSE 12
+#define WMI_TARGET_DELETE_PSTREAM_CMD 13
+#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14
+#define WMI_TARGET_GET_BIT_RATE_CMD 15
+#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16
+#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17
+#define WMI_TARGET_GET_TX_PWR_CMD 18
+#define WMI_FREE_EVBUF_WMIBUF 19
+#define WMI_FREE_EVBUF_DATABUF 20
+#define WMI_FREE_EVBUF_BADFLAG 21
+#define WMI_HTC_RX_ERROR_DATA_PACKET 22
+#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23
+#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24
+#define WMI_SENDING_READY_EVENT 25
+#define WMI_SETPOWER_MDOE_TO_MAXPERF 26
+#define WMI_SETPOWER_MDOE_TO_REC 27
+#define WMI_BSSINFO_EVENT_FROM 28
+#define WMI_TARGET_GET_STATS_CMD 29
+#define WMI_SENDING_SCAN_COMPLETE_EVENT 30
+#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31
+#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32
+#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33
+#define WMI_SENDING_ERROR_REPORT_EVENT 34
+#define WMI_SENDING_CAC_EVENT 35
+#define WMI_TARGET_GET_ROAM_TABLE_CMD 36
+#define WMI_TARGET_GET_ROAM_DATA_CMD 37
+#define WMI_SENDING_GPIO_INTR_EVENT 38
+#define WMI_SENDING_GPIO_ACK_EVENT 39
+#define WMI_SENDING_GPIO_DATA_EVENT 40
+#define WMI_CMD_RX 41
+#define WMI_CMD_RX_XTND 42
+#define WMI_EVENT_SEND 43
+#define WMI_EVENT_SEND_XTND 44
+#define WMI_CMD_PARAMS_DUMP_START 45
+#define WMI_CMD_PARAMS_DUMP_END 46
+#define WMI_CMD_PARAMS 47
+#define WMI_DBGID_DEFINITION_END
+
+/* MISC debug identifier definitions */
+#define MISC_DBGID_DEFINITION_START
+#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1
+#define MISC_DBGID_DEFINITION_END
+
+/* TXRX debug identifier definitions */
+#define TXRX_TXBUF_DBGID_DEFINITION_START
+#define TXRX_TXBUF_ALLOCATE_BUF 1
+#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2
+#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3
+#define TXRX_TXBUF_TXQ_DEPTH 4
+#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5
+#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6
+#define TXRX_TXBUF_INITIALIZE_TIMER 7
+#define TXRX_TXBUF_ARM_TIMER 8
+#define TXRX_TXBUF_DISARM_TIMER 9
+#define TXRX_TXBUF_UNINITIALIZE_TIMER 10
+#define TXRX_TXBUF_DBGID_DEFINITION_END
+
+#define TXRX_RXBUF_DBGID_DEFINITION_START
+#define TXRX_RXBUF_ALLOCATE_BUF 1
+#define TXRX_RXBUF_QUEUE_TO_HOST 2
+#define TXRX_RXBUF_QUEUE_TO_WLAN 3
+#define TXRX_RXBUF_ZERO_LEN_BUF 4
+#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5
+#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6
+#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7
+#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8
+#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9
+#define TXRX_RXBUF_REQUEUE_ERROR 10
+#define TXRX_RXBUF_DBGID_DEFINITION_END
+
+#define TXRX_MGMTBUF_DBGID_DEFINITION_START
+#define TXRX_MGMTBUF_ALLOCATE_BUF 1
+#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2
+#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3
+#define TXRX_MGMTBUF_GET_BUF 4
+#define TXRX_MGMTBUF_GET_SM_BUF 5
+#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6
+#define TXRX_MGMTBUF_REAPED_BUF 7
+#define TXRX_MGMTBUF_REAPED_SM_BUF 8
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10
+#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11
+#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12
+#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13
+#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14
+#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15
+#define TXRX_MGMTBUF_DRAINQ 16
+#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17
+#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18
+#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19
+#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20
+#define TXRX_MGMTBUF_RESUME_HW_TXQ 21
+#define TXRX_MGMTBUF_TEAR_DOWN_BA 22
+#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23
+#define TXRX_MGMTBUF_PROCESS_DELBA 24
+#define TXRX_MGMTBUF_PERFORM_BA 25
+#define TXRX_MGMTBUF_DBGID_DEFINITION_END
+
+/* PM (Power Module) debug identifier definitions */
+#define PM_DBGID_DEFINITION_START
+#define PM_INIT 1
+#define PM_ENABLE 2
+#define PM_SET_STATE 3
+#define PM_SET_POWERMODE 4
+#define PM_CONN_NOTIFY 5
+#define PM_REF_COUNT_NEGATIVE 6
+#define PM_INFRA_STA_APSD_ENABLE 7
+#define PM_INFRA_STA_UPDATE_APSD_STATE 8
+#define PM_CHAN_OP_REQ 9
+#define PM_SET_MY_BEACON_POLICY 10
+#define PM_SET_ALL_BEACON_POLICY 11
+#define PM_INFRA_STA_SET_PM_PARAMS1 12
+#define PM_INFRA_STA_SET_PM_PARAMS2 13
+#define PM_ADHOC_SET_PM_CAPS_FAIL 14
+#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15
+#define PM_ADHOC_SET_PM_PARAMS 16
+#define PM_ADHOC_STATE1 18
+#define PM_ADHOC_STATE2 19
+#define PM_ADHOC_CONN_MAP 20
+#define PM_FAKE_SLEEP 21
+#define PM_AP_STATE1 22
+#define PM_AP_SET_PM_PARAMS 23
+#define PM_DBGID_DEFINITION_END
+
+/* Wake on Wireless debug identifier definitions */
+#define WOW_DBGID_DEFINITION_START
+#define WOW_INIT 1
+#define WOW_GET_CONFIG_DSET 2
+#define WOW_NO_CONFIG_DSET 3
+#define WOW_INVALID_CONFIG_DSET 4
+#define WOW_USE_DEFAULT_CONFIG 5
+#define WOW_SETUP_GPIO 6
+#define WOW_INIT_DONE 7
+#define WOW_SET_GPIO_PIN 8
+#define WOW_CLEAR_GPIO_PIN 9
+#define WOW_SET_WOW_MODE_CMD 10
+#define WOW_SET_HOST_MODE_CMD 11
+#define WOW_ADD_WOW_PATTERN_CMD 12
+#define WOW_NEW_WOW_PATTERN_AT_INDEX 13
+#define WOW_DEL_WOW_PATTERN_CMD 14
+#define WOW_LIST_CONTAINS_PATTERNS 15
+#define WOW_GET_WOW_LIST_CMD 16
+#define WOW_INVALID_FILTER_ID 17
+#define WOW_INVALID_FILTER_LISTID 18
+#define WOW_NO_VALID_FILTER_AT_ID 19
+#define WOW_NO_VALID_LIST_AT_ID 20
+#define WOW_NUM_PATTERNS_EXCEEDED 21
+#define WOW_NUM_LISTS_EXCEEDED 22
+#define WOW_GET_WOW_STATS 23
+#define WOW_CLEAR_WOW_STATS 24
+#define WOW_WAKEUP_HOST 25
+#define WOW_EVENT_WAKEUP_HOST 26
+#define WOW_EVENT_DISCARD 27
+#define WOW_PATTERN_MATCH 28
+#define WOW_PATTERN_NOT_MATCH 29
+#define WOW_PATTERN_NOT_MATCH_OFFSET 30
+#define WOW_DISABLED_HOST_ASLEEP 31
+#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32
+#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33
+#define WOW_DBGID_DEFINITION_END
+
+/* WHAL debug identifier definitions */
+#define WHAL_DBGID_DEFINITION_START
+#define WHAL_ERROR_ANI_CONTROL 1
+#define WHAL_ERROR_CHIP_TEST1 2
+#define WHAL_ERROR_CHIP_TEST2 3
+#define WHAL_ERROR_EEPROM_CHECKSUM 4
+#define WHAL_ERROR_EEPROM_MACADDR 5
+#define WHAL_ERROR_INTERRUPT_HIU 6
+#define WHAL_ERROR_KEYCACHE_RESET 7
+#define WHAL_ERROR_KEYCACHE_SET 8
+#define WHAL_ERROR_KEYCACHE_TYPE 9
+#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10
+#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11
+#define WHAL_ERROR_PHY_INVALID_CHANNEL 12
+#define WHAL_ERROR_POWER_AWAKE 13
+#define WHAL_ERROR_POWER_SET 14
+#define WHAL_ERROR_RECV_STOPDMA 15
+#define WHAL_ERROR_RECV_STOPPCU 16
+#define WHAL_ERROR_RESET_CHANNF1 17
+#define WHAL_ERROR_RESET_CHANNF2 18
+#define WHAL_ERROR_RESET_PM 19
+#define WHAL_ERROR_RESET_OFFSETCAL 20
+#define WHAL_ERROR_RESET_RFGRANT 21
+#define WHAL_ERROR_RESET_RXFRAME 22
+#define WHAL_ERROR_RESET_STOPDMA 23
+#define WHAL_ERROR_RESET_RECOVER 24
+#define WHAL_ERROR_XMIT_COMPUTE 25
+#define WHAL_ERROR_XMIT_NOQUEUE 26
+#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27
+#define WHAL_ERROR_XMIT_BADTYPE 28
+#define WHAL_ERROR_XMIT_STOPDMA 29
+#define WHAL_ERROR_INTERRUPT_BB_PANIC 30
+#define WHAL_ERROR_RESET_TXIQCAL 31
+#define WHAL_DBGID_DEFINITION_END
+
+/* DC debug identifier definitions */
+#define DC_DBGID_DEFINITION_START
+#define DC_SCAN_CHAN_START 1
+#define DC_SCAN_CHAN_FINISH 2
+#define DC_BEACON_RECEIVE7 3
+#define DC_SSID_PROBE_CB 4
+#define DC_SEND_NEXT_SSID_PROBE 5
+#define DC_START_SEARCH 6
+#define DC_CANCEL_SEARCH_CB 7
+#define DC_STOP_SEARCH 8
+#define DC_END_SEARCH 9
+#define DC_MIN_CHDWELL_TIMEOUT 10
+#define DC_START_SEARCH_CANCELED 11
+#define DC_SET_POWER_MODE 12
+#define DC_INIT 13
+#define DC_SEARCH_OPPORTUNITY 14
+#define DC_RECEIVED_ANY_BEACON 15
+#define DC_RECEIVED_MY_BEACON 16
+#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17
+#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18
+#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19
+#define DC_SET_BEACON_UPDATE 20
+#define DC_BEACON_UPDATE_COMPLETE 21
+#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22
+#define DC_BSSINFO_EVENT_DROPPED 23
+#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24
+#define DC_DBGID_DEFINITION_END
+
+/* CO debug identifier definitions */
+#define CO_DBGID_DEFINITION_START
+#define CO_INIT 1
+#define CO_ACQUIRE_LOCK 2
+#define CO_START_OP1 3
+#define CO_START_OP2 4
+#define CO_DRAIN_TX_COMPLETE_CB 5
+#define CO_CHANGE_CHANNEL_CB 6
+#define CO_RETURN_TO_HOME_CHANNEL 7
+#define CO_FINISH_OP_TIMEOUT 8
+#define CO_OP_END 9
+#define CO_CANCEL_OP 10
+#define CO_CHANGE_CHANNEL 11
+#define CO_RELEASE_LOCK 12
+#define CO_CHANGE_STATE 13
+#define CO_DBGID_DEFINITION_END
+
+/* RO debug identifier definitions */
+#define RO_DBGID_DEFINITION_START
+#define RO_REFRESH_ROAM_TABLE 1
+#define RO_UPDATE_ROAM_CANDIDATE 2
+#define RO_UPDATE_ROAM_CANDIDATE_CB 3
+#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4
+#define RO_REFRESH_ROAM_TABLE_DONE 5
+#define RO_PERIODIC_SEARCH_CB 6
+#define RO_PERIODIC_SEARCH_TIMEOUT 7
+#define RO_INIT 8
+#define RO_BMISS_STATE1 9
+#define RO_BMISS_STATE2 10
+#define RO_SET_PERIODIC_SEARCH_ENABLE 11
+#define RO_SET_PERIODIC_SEARCH_DISABLE 12
+#define RO_ENABLE_SQ_THRESHOLD 13
+#define RO_DISABLE_SQ_THRESHOLD 14
+#define RO_ADD_BSS_TO_ROAM_TABLE 15
+#define RO_SET_PERIODIC_SEARCH_MODE 16
+#define RO_CONFIGURE_SQ_THRESHOLD1 17
+#define RO_CONFIGURE_SQ_THRESHOLD2 18
+#define RO_CONFIGURE_SQ_PARAMS 19
+#define RO_LOW_SIGNAL_QUALITY_EVENT 20
+#define RO_HIGH_SIGNAL_QUALITY_EVENT 21
+#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22
+#define RO_UPDATE_CONNECTION_STATE_METRIC 23
+#define RO_DBGID_DEFINITION_END
+
+/* CM debug identifier definitions */
+#define CM_DBGID_DEFINITION_START
+#define CM_INITIATE_HANDOFF 1
+#define CM_INITIATE_HANDOFF_CB 2
+#define CM_CONNECT_EVENT 3
+#define CM_DISCONNECT_EVENT 4
+#define CM_INIT 5
+#define CM_HANDOFF_SOURCE 6
+#define CM_SET_HANDOFF_TRIGGERS 7
+#define CM_CONNECT_REQUEST 8
+#define CM_CONNECT_REQUEST_CB 9
+#define CM_CONTINUE_SCAN_CB 10
+#define CM_DBGID_DEFINITION_END
+
+
+/* mgmt debug identifier definitions */
+#define MGMT_DBGID_DEFINITION_START
+#define KEYMGMT_CONNECTION_INIT 1
+#define KEYMGMT_CONNECTION_COMPLETE 2
+#define KEYMGMT_CONNECTION_CLOSE 3
+#define KEYMGMT_ADD_KEY 4
+#define MLME_NEW_STATE 5
+#define MLME_CONN_INIT 6
+#define MLME_CONN_COMPLETE 7
+#define MLME_CONN_CLOSE 8
+#define MGMT_DBGID_DEFINITION_END
+
+/* TMR debug identifier definitions */
+#define TMR_DBGID_DEFINITION_START
+#define TMR_HANG_DETECTED 1
+#define TMR_WDT_TRIGGERED 2
+#define TMR_WDT_RESET 3
+#define TMR_HANDLER_ENTRY 4
+#define TMR_HANDLER_EXIT 5
+#define TMR_SAVED_START 6
+#define TMR_SAVED_END 7
+#define TMR_DBGID_DEFINITION_END
+
+/* BTCOEX debug identifier definitions */
+#define BTCOEX_DBGID_DEFINITION_START
+#define BTCOEX_STATUS_CMD 1
+#define BTCOEX_PARAMS_CMD 2
+#define BTCOEX_ANT_CONFIG 3
+#define BTCOEX_COLOCATED_BT_DEVICE 4
+#define BTCOEX_CLOSE_RANGE_SCO_ON 5
+#define BTCOEX_CLOSE_RANGE_SCO_OFF 6
+#define BTCOEX_CLOSE_RANGE_A2DP_ON 7
+#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8
+#define BTCOEX_A2DP_PROTECT_ON 9
+#define BTCOEX_A2DP_PROTECT_OFF 10
+#define BTCOEX_SCO_PROTECT_ON 11
+#define BTCOEX_SCO_PROTECT_OFF 12
+#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13
+#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14
+#define BTCOEX_CLOSE_RANGE_TOGGLE 15
+#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16
+#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17
+#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18
+#define BTCOEX_PTA_PRI_INTR_HANDLER 19
+#define BTCOEX_PSPOLL_QUEUED 20
+#define BTCOEX_PSPOLL_COMPLETE 21
+#define BTCOEX_DBG_PM_AWAKE 22
+#define BTCOEX_DBG_PM_SLEEP 23
+#define BTCOEX_DBG_SCO_COEX_ON 24
+#define BTCOEX_SCO_DATARECEIVE 25
+#define BTCOEX_INTR_INIT 26
+#define BTCOEX_PTA_PRI_DIFF 27
+#define BTCOEX_TIM_NOTIFICATION 28
+#define BTCOEX_SCO_WAKEUP_ON_DATA 29
+#define BTCOEX_SCO_SLEEP 30
+#define BTCOEX_SET_WEIGHTS 31
+#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32
+#define BTCOEX_SCO_MEASURE_TIME_DIFF 33
+#define BTCOEX_SET_EOL_VAL 34
+#define BTCOEX_OPT_DETECT_HANDLER 35
+#define BTCOEX_SCO_TOGGLE_STATE 36
+#define BTCOEX_SCO_STOMP 37
+#define BTCOEX_NULL_COMP_CALLBACK 38
+#define BTCOEX_RX_INCOMING 39
+#define BTCOEX_RX_INCOMING_CTL 40
+#define BTCOEX_RX_INCOMING_MGMT 41
+#define BTCOEX_RX_INCOMING_DATA 42
+#define BTCOEX_RTS_RECEPTION 43
+#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44
+#define BTCOEX_PM_FAKE_SLEEP 45
+#define BTCOEX_ACL_COEX_STATUS 46
+#define BTCOEX_ACL_COEX_DETECTECTION 47
+#define BTCOEX_A2DP_COEX_STATUS 48
+#define BTCOEX_SCO_STATUS 49
+#define BTCOEX_WAKEUP_ON_DATA 50
+#define BTCOEX_DATARECEIVE 51
+#define BTCOEX_GET_MAX_AGGR_SIZE 53
+#define BTCOEX_MAX_AGGR_AVAIL_TIME 54
+#define BTCOEX_DBG_WBTIMER_INTR 55
+#define BTCOEX_DBG_SCO_SYNC 57
+#define BTCOEX_UPLINK_QUEUED_RATE 59
+#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60
+#define BTCOEX_UPLINK_FRAME_DURATION 61
+#define BTCOEX_UPLINK_SET_EOL 62
+#define BTCOEX_DBG_EOL_EXPIRED 63
+#define BTCOEX_DBG_DATA_COMPLETE 64
+#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65
+#define BTCOEX_DBG_DATA_COMPLETE_TIME 66
+#define BTCOEX_DBG_TX_COMP_TXQ 67
+#define BTCOEX_DBG_SCO_FL_EDGE 68
+#define BTCOEX_DBG_UPLINK_SEQ_NUM 69
+#define BTCOEX_UPLINK_AGGR_SEQ 70
+#define BTCOEX_DBG_TX_COMP_SEQ_NO 71
+#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72
+#define BTCOEX_DBG_ACL_TRAFFIC 73
+#define BTCOEX_CURR_AGGR_PROP 74
+#define BTCOEX_CREAT_AGGR 75
+#define BTCOEX_PSPOLL_PROCESS 76
+#define BTCOEX_RETURN_FROM_MAC 77
+#define BTCOEX_FREED_REQUEUED_CNT 78
+#define BTCOEX_DBG_TOGGLE_LOW_RATES 79
+#define BTCOEX_MAC_GOES_TO_SLEEP 80
+#define BTCOEX_DBG_A2DP_NO_SYNC 81
+#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82
+#define BTCOEX_RETURN_FROM_MAC_AC 83
+#define BTCOEX_CREAT_AGGR_AC 84
+#define BTCOEX_IS_PRE_UPDATE 86
+#define BTCOEX_ENQUEUED_BIT_MAP 87
+#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88
+#define BTCOEX_UPLINK_DESC 89
+#define BTCOEX_DBG_TXQ_DETAILS 90
+#define BTCOEX_DBG_RECV_ACK 94
+#define BTCOEX_DBG_ADDBA_INDICATION 95
+#define BTCOEX_TX_COMPLETE_EOL_FAILED 96
+#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97
+#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98
+#define BTCOEX_DBG_A2DP_SYNC_INTR 99
+#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100
+#define BTCOEX_FORM_AGGR_CURR_AGGR 101
+#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102
+#define BTCOEX_DBG_BT_TRAFFIC 103
+#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104
+#define BTCOEX_RECV_NULL 105
+#define BTCOEX_DBG_A2DP_MASTER_BT_END 106
+#define BTCOEX_DBG_A2DP_BT_START 107
+#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108
+#define BTCOEX_DBG_A2DP_STOMP_BT 109
+#define BTCOEX_DBG_GO_TO_SLEEP 110
+#define BTCOEX_DBG_A2DP_PKT 111
+#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112
+#define BTCOEX_DBG_A2DP_NULL 113
+#define BTCOEX_DBG_UPLINK_DATA 114
+#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115
+#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116
+#define BTCOEX_DBG_TXQ_STATE 117
+#define BTCOEX_DBG_ALLOW_SCAN 118
+#define BTCOEX_DBG_SCAN_REQUEST 119
+#define BTCOEX_A2DP_SLEEP 127
+#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128
+#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129
+#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130
+#define BTCOEX_DATARECEIVE_AGGR 131
+#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132
+#define BTCOEX_DBG_DATARESP_TIMEOUT 133
+#define BTCOEX_BDG_BMISS 134
+#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135
+#define BTCOEX_DBG_SECOND_BMISS 136
+#define BTCOEX_DBG_SET_WLAN_STATE 138
+#define BTCOEX_BDG_FIRST_BMISS 139
+#define BTCOEX_DBG_A2DP_CHAN_OP 140
+#define BTCOEX_DBG_A2DP_INTR 141
+#define BTCOEX_DBG_BT_INQUIRY 142
+#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143
+#define BTCOEX_DBG_POST_INQUIRY_FINISH 144
+#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145
+#define BTCOEX_DBG_NULL_FRAME_SLEEP 146
+#define BTCOEX_DBG_NULL_FRAME_AWAKE 147
+#define BTCOEX_DBG_SET_AGGR_SIZE 152
+#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153
+#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154
+#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155
+#define BTCOEX_DBG_COLOCATED_BT_DEV 156
+#define BTCOEX_DBG_FE_ANT_TYPE 157
+#define BTCOEX_DBG_BT_INQUIRY_CMD 158
+#define BTCOEX_DBG_SCO_CONFIG 159
+#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160
+#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161
+#define BTCOEX_DBG_A2DP_CONFIG 162
+#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163
+#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164
+#define BTCOEX_DBG_ACLCOEX_CONFIG 165
+#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166
+#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167
+#define BTCOEX_DBG_DEBUG_CMD 168
+#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169
+#define BTCOEX_DBG_GET_CONFIG 170
+#define BTCOEX_DBG_GET_STATS 171
+#define BTCOEX_DBG_BT_OPERATING_STATUS 172
+#define BTCOEX_DBG_PERFORM_RECONNECT 173
+#define BTCOEX_DBG_ACL_WLAN_MED 175
+#define BTCOEX_DBG_ACL_BT_MED 176
+#define BTCOEX_DBG_WLAN_CONNECT 177
+#define BTCOEX_DBG_A2DP_DUAL_START 178
+#define BTCOEX_DBG_PMAWAKE_NOTIFY 179
+#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180
+#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181
+#define BTCOEX_DBG_RX_NOTIFY 182
+#define BTCOEX_DBGID_DEFINITION_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_ID_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/discovery.h b/drivers/net/wireless/ath6kl/include/discovery.h
new file mode 100644
index 000000000000..53791df70ab9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/discovery.h
@@ -0,0 +1,71 @@
+//------------------------------------------------------------------------------
+// <copyright file="discovery.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _DISCOVERY_H_
+#define _DISCOVERY_H_
+
+/*
+ * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel
+ */
+typedef enum {
+ DEFAULT_SCPRI = 0x01,
+ POPULAR_SCPRI = 0x02,
+ SSIDS_SCPRI = 0x04,
+ PROF_SCPRI = 0x08,
+} DC_SCAN_PRIORITY;
+
+/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */
+typedef enum {
+ SCAN_RESET = 0,
+ SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \
+ SSIDS_SCPRI | PROF_SCPRI),
+
+ SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI),
+ SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI),
+ SCAN_PROF_MASK = (PROF_SCPRI),
+ SCAN_MULTI_CHANNEL = 0x000100,
+ SCAN_DETERMINISTIC = 0x000200,
+ SCAN_PROFILE_MATCH_TERMINATED = 0x000400,
+ SCAN_HOME_CHANNEL_SKIP = 0x000800,
+ SCAN_CHANNEL_LIST_CONTINUE = 0x001000,
+ SCAN_CURRENT_SSID_SKIP = 0x002000,
+ SCAN_ACTIVE_PROBE_DISABLE = 0x004000,
+ SCAN_CHANNEL_HINT_ONLY = 0x008000,
+ SCAN_ACTIVE_CHANNELS_ONLY = 0x010000,
+ SCAN_UNUSED1 = 0x020000, /* unused */
+ SCAN_PERIODIC = 0x040000,
+ SCAN_FIXED_DURATION = 0x080000,
+ SCAN_AP_ASSISTED = 0x100000,
+} DC_SCAN_TYPE;
+
+typedef enum {
+ BSS_REPORTING_DEFAULT = 0x0,
+ EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */
+} DC_BSS_REPORTING_POLICY;
+
+typedef enum {
+ DC_IGNORE_WPAx_GROUP_CIPHER = 0x01,
+ DC_PROFILE_MATCH_DONE = 0x02,
+ DC_IGNORE_AAC_BEACON = 0x04,
+ DC_CSA_FOLLOW_BSS = 0x08,
+} DC_PROFILE_FILTER;
+
+#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS)
+
+#endif /* _DISCOVERY_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dl_list.h b/drivers/net/wireless/ath6kl/include/dl_list.h
new file mode 100644
index 000000000000..f07b41d7638a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dl_list.h
@@ -0,0 +1,149 @@
+//------------------------------------------------------------------------------
+// <copyright file="dl_list.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Double-link list definitions (adapted from Atheros SDIO stack)
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __DL_LIST_H___
+#define __DL_LIST_H___
+
+#include "a_osapi.h"
+
+#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
+ ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name)))
+
+/* list functions */
+/* pointers for the list */
+typedef struct _DL_LIST {
+ struct _DL_LIST *pPrev;
+ struct _DL_LIST *pNext;
+}DL_LIST, *PDL_LIST;
+/*
+ * DL_LIST_INIT , initialize doubly linked list
+*/
+#define DL_LIST_INIT(pList)\
+ {(pList)->pPrev = pList; (pList)->pNext = pList;}
+
+/* faster macro to init list and add a single item */
+#define DL_LIST_INIT_AND_ADD(pList,pItem) \
+{ (pList)->pPrev = (pItem); \
+ (pList)->pNext = (pItem); \
+ (pItem)->pNext = (pList); \
+ (pItem)->pPrev = (pList); \
+}
+
+#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
+#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
+#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
+/*
+ * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
+ * NOT: do not use this function if the items in the list are deleted inside the
+ * iteration loop
+*/
+#define ITERATE_OVER_LIST(pStart, pTemp) \
+ for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
+
+
+/* safe iterate macro that allows the item to be removed from the list
+ * the iteration continues to the next item in the list
+ */
+#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \
+{ \
+ PDL_LIST pTemp; \
+ pTemp = (pStart)->pNext; \
+ while (pTemp != (pStart)) { \
+ (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \
+ pTemp = pTemp->pNext; \
+
+#define ITERATE_END }}
+
+/*
+ * DL_ListInsertTail - insert pAdd to the end of the list
+*/
+static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) {
+ /* insert at tail */
+ pAdd->pPrev = pList->pPrev;
+ pAdd->pNext = pList;
+ pList->pPrev->pNext = pAdd;
+ pList->pPrev = pAdd;
+ return pAdd;
+}
+
+/*
+ * DL_ListInsertHead - insert pAdd into the head of the list
+*/
+static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) {
+ /* insert at head */
+ pAdd->pPrev = pList;
+ pAdd->pNext = pList->pNext;
+ pList->pNext->pPrev = pAdd;
+ pList->pNext = pAdd;
+ return pAdd;
+}
+
+#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
+/*
+ * DL_ListRemove - remove pDel from list
+*/
+static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) {
+ pDel->pNext->pPrev = pDel->pPrev;
+ pDel->pPrev->pNext = pDel->pNext;
+ /* point back to itself just to be safe, incase remove is called again */
+ pDel->pNext = pDel;
+ pDel->pPrev = pDel;
+ return pDel;
+}
+
+/*
+ * DL_ListRemoveItemFromHead - get a list item from the head
+*/
+static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) {
+ PDL_LIST pItem = NULL;
+ if (pList->pNext != pList) {
+ pItem = pList->pNext;
+ /* remove the first item from head */
+ DL_ListRemove(pItem);
+ }
+ return pItem;
+}
+
+static INLINE PDL_LIST DL_ListRemoveItemFromTail(PDL_LIST pList) {
+ PDL_LIST pItem = NULL;
+ if (pList->pPrev != pList) {
+ pItem = pList->pPrev;
+ /* remove the item from tail */
+ DL_ListRemove(pItem);
+ }
+ return pItem;
+}
+
+/* transfer src list items to the tail of the destination list */
+static INLINE void DL_ListTransferItemsToTail(PDL_LIST pDest, PDL_LIST pSrc) {
+ /* only concatenate if src is not empty */
+ if (!DL_LIST_IS_EMPTY(pSrc)) {
+ /* cut out circular list in src and re-attach to end of dest */
+ pSrc->pPrev->pNext = pDest;
+ pSrc->pNext->pPrev = pDest->pPrev;
+ pDest->pPrev->pNext = pSrc->pNext;
+ pDest->pPrev = pSrc->pPrev;
+ /* terminate src list, it is now empty */
+ pSrc->pPrev = pSrc;
+ pSrc->pNext = pSrc;
+ }
+}
+
+#endif /* __DL_LIST_H___ */
diff --git a/drivers/net/wireless/ath6kl/include/dset_api.h b/drivers/net/wireless/ath6kl/include/dset_api.h
new file mode 100644
index 000000000000..9456df988073
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dset_api.h
@@ -0,0 +1,61 @@
+//------------------------------------------------------------------------------
+// <copyright file="dset_api.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Host-side DataSet API.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _DSET_API_H_
+#define _DSET_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Host-side DataSet support is optional, and is not
+ * currently required for correct operation. To disable
+ * Host-side DataSet support, set this to 0.
+ */
+#ifndef CONFIG_HOST_DSET_SUPPORT
+#define CONFIG_HOST_DSET_SUPPORT 1
+#endif
+
+/* Called to send a DataSet Open Reply back to the Target. */
+A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT32 access_cookie,
+ A_UINT32 size,
+ A_UINT32 version,
+ A_UINT32 targ_handle,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+
+/* Called to send a DataSet Data Reply back to the Target. */
+A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT8 *host_buf,
+ A_UINT32 length,
+ A_UINT32 targ_buf,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _DSET_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/dset_internal.h b/drivers/net/wireless/ath6kl/include/dset_internal.h
new file mode 100644
index 000000000000..474f3c273574
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dset_internal.h
@@ -0,0 +1,51 @@
+//------------------------------------------------------------------------------
+// <copyright file="dset_internal.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __DSET_INTERNAL_H__
+#define __DSET_INTERNAL_H__
+
+/*
+ * Internal dset definitions, common for DataSet layer.
+ */
+
+#define DSET_TYPE_STANDARD 0
+#define DSET_TYPE_BPATCHED 1
+#define DSET_TYPE_COMPRESSED 2
+
+/* Dataset descriptor */
+
+typedef struct dset_descriptor_s {
+ struct dset_descriptor_s *next; /* List link. NULL only at the last
+ descriptor */
+ A_UINT16 id; /* Dset ID */
+ A_UINT16 size; /* Dset size. */
+ void *DataPtr; /* Pointer to raw data for standard
+ DataSet or pointer to original
+ dset_descriptor for patched
+ DataSet */
+ A_UINT32 data_type; /* DSET_TYPE_*, above */
+
+ void *AuxPtr; /* Additional data that might
+ needed for data_type. For
+ example, pointer to patch
+ Dataset descriptor for BPatch. */
+} dset_descriptor_t;
+
+#endif /* __DSET_INTERNAL_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/dsetid.h b/drivers/net/wireless/ath6kl/include/dsetid.h
new file mode 100644
index 000000000000..fc42fd20ba83
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/dsetid.h
@@ -0,0 +1,122 @@
+//------------------------------------------------------------------------------
+// <copyright file="dsetid.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+
+#ifndef __DSETID_H__
+#define __DSETID_H__
+
+/* Well-known DataSet IDs */
+#define DSETID_UNUSED 0x00000000
+#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */
+#define DSETID_REGDB 0x00000002 /* Regulatory Database */
+#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */
+#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */
+
+#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005
+#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025
+/*
+ * Get DSETID for various reference clock speeds.
+ * For each speed there are three DataSets that correspond
+ * to the three columns of bank6 data (addr, 11a, 11b/g).
+ * This macro returns the dsetid of the first of those
+ * three DataSets.
+ */
+#define ANALOG_CONTROL_DATA_DSETID(refclk) \
+ (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
+
+/*
+ * There are TWO STARTUP_PATCH DataSets.
+ * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
+ * earlier systems. On AR6002, it is applied after BMI, just like
+ * DSETID_STARTUP_PATCH2.
+ */
+#define DSETID_STARTUP_PATCH 0x00000026
+#define DSETID_GPIO_CONFIG_PATCH 0x00000027
+#define DSETID_WLANREGS 0x00000028 /* override wlan regs */
+#define DSETID_STARTUP_PATCH2 0x00000029
+
+#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */
+
+/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
+#define DSETID_INI_DATA 0x00000100
+/* Reserved for WHAL INI Tables: 0x100..0x11f */
+#define DSETID_INI_DATA_END 0x0000011f
+
+#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */
+
+#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the
+ end of a memory-based
+ DataSet Index */
+#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */
+
+/*
+ * PATCH DataSet format:
+ * A list of patches, terminated by a patch with
+ * address=PATCH_END.
+ *
+ * This allows for patches to be stored in flash.
+ */
+struct patch_s {
+ A_UINT32 *address;
+ A_UINT32 data;
+};
+
+/*
+ * Skip some patches. Can be used to erase a single patch in a
+ * patch DataSet without having to re-write the DataSet. May
+ * also be used to embed information for use by subsequent
+ * patch code. The "data" in a PATCH_SKIP tells how many
+ * bytes of length "patch_s" to skip.
+ */
+#define PATCH_SKIP ((A_UINT32 *)0x00000000)
+
+/*
+ * Execute code at the address specified by "data".
+ * The address of the patch structure is passed as
+ * the one parameter.
+ */
+#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001)
+
+/*
+ * Same as PATCH_CODE_ABS, but treat "data" as an
+ * offset from the start of the patch word.
+ */
+#define PATCH_CODE_REL ((A_UINT32 *)0x00000002)
+
+/* Mark the end of this patch DataSet. */
+#define PATCH_END ((A_UINT32 *)0xffffffff)
+
+/*
+ * A DataSet which contains a Binary Patch to some other DataSet
+ * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
+ * Such a BPatch DataSet consists of BPatch metadata followed by
+ * the bdiff bytes. BPatch metadata consists of a single 32-bit
+ * word that contains the size of the BPatched final image.
+ *
+ * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
+ * to create "diffs":
+ * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
+ * Then add BPatch metadata to the start of "diffs".
+ *
+ * NB: There are some implementation-induced restrictions
+ * on which DataSets can be BPatched.
+ */
+#define DSETID_BPATCH_FLAG 0x80000000
+
+#endif /* __DSETID_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/epping_test.h b/drivers/net/wireless/ath6kl/include/epping_test.h
new file mode 100644
index 000000000000..e76b6420758d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/epping_test.h
@@ -0,0 +1,115 @@
+//------------------------------------------------------------------------------
+// <copyright file="epping_test.h" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//
+
+/* This file contains shared definitions for the host/target endpoint ping test */
+
+#ifndef EPPING_TEST_H_
+#define EPPING_TEST_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+ /* alignment to 4-bytes */
+#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
+
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+
+#define EPPING_RSVD_FILL 0xCC
+
+#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
+
+typedef PREPACK struct {
+ A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
+ A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
+ A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
+ When echoed: StreamEchoSent_t == StreamEcho_h */
+ A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
+ A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
+ A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/
+ A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
+ since this packet maps to a 14-byte ethernet frame we want
+ to make sure ethertype field is set to something unknown */
+
+ A_UINT8 _pad[2]; /* padding for alignment */
+ A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
+ A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
+ A_UINT32 SeqNo; /* sequence number (set by host or target) */
+ A_UINT16 Cmd_h; /* ping command (filled by host) */
+ A_UINT16 CmdFlags_h; /* optional flags */
+ A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
+ A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
+ A_UINT16 DataLength; /* length of data */
+ A_UINT16 DataCRC; /* 16 bit CRC of data */
+ A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
+} POSTPACK EPPING_HEADER;
+
+#define EPPING_PING_MAGIC_0 0xAA
+#define EPPING_PING_MAGIC_1 0x55
+#define EPPING_PING_MAGIC_2 0xCE
+#define EPPING_PING_MAGIC_3 0xEC
+
+
+
+#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
+ ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
+ ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
+ ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
+
+#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
+ (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
+ (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
+ (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
+
+#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
+#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
+#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
+
+#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
+
+#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
+#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
+#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
+#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
+#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
+#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
+
+ /* test command parameters may be no more than 8 bytes */
+typedef PREPACK struct {
+ A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
+ A_UINT16 PacketLength; /* length of packet to generate including header */
+ A_UINT16 Flags; /* flags */
+
+#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
+#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
+#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
+} POSTPACK EPPING_CONT_RX_PARAMS;
+
+#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
+#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
+
+#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
+ can use this to distinguish packets */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+
+#endif /*EPPING_TEST_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/gmboxif.h b/drivers/net/wireless/ath6kl/include/gmboxif.h
new file mode 100644
index 000000000000..0d4120e34978
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/gmboxif.h
@@ -0,0 +1,73 @@
+//------------------------------------------------------------------------------
+// <copyright file="gmboxif.h" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __GMBOXIF_H__
+#define __GMBOXIF_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/* GMBOX interface definitions */
+
+#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */
+#define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */
+
+
+ /* HCI UART transport definitions when used over GMBOX interface */
+#define HCI_UART_COMMAND_PKT 0x01
+#define HCI_UART_ACL_PKT 0x02
+#define HCI_UART_SCO_PKT 0x03
+#define HCI_UART_EVENT_PKT 0x04
+
+ /* definitions for BT HCI packets */
+typedef PREPACK struct {
+ A_UINT16 Flags_ConnHandle;
+ A_UINT16 Length;
+} POSTPACK BT_HCI_ACL_HEADER;
+
+typedef PREPACK struct {
+ A_UINT16 Flags_ConnHandle;
+ A_UINT8 Length;
+} POSTPACK BT_HCI_SCO_HEADER;
+
+typedef PREPACK struct {
+ A_UINT16 OpCode;
+ A_UINT8 ParamLength;
+} POSTPACK BT_HCI_COMMAND_HEADER;
+
+typedef PREPACK struct {
+ A_UINT8 EventCode;
+ A_UINT8 ParamLength;
+} POSTPACK BT_HCI_EVENT_HEADER;
+
+/* MBOX host interrupt signal assignments */
+
+#define MBOX_SIG_HCI_BRIDGE_MAX 8
+#define MBOX_SIG_HCI_BRIDGE_BT_ON 0
+#define MBOX_SIG_HCI_BRIDGE_BT_OFF 1
+#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2
+
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __GMBOXIF_H__ */
+
diff --git a/drivers/net/wireless/ath6kl/include/gpio.h b/drivers/net/wireless/ath6kl/include/gpio.h
new file mode 100644
index 000000000000..9865af05ebd9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/gpio.h
@@ -0,0 +1,43 @@
+//------------------------------------------------------------------------------
+// <copyright file="gpio.h" company="Atheros">
+// Copyright (c) 2005 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#define AR6001_GPIO_PIN_COUNT 18
+#define AR6002_GPIO_PIN_COUNT 18
+#define AR6003_GPIO_PIN_COUNT 28
+
+/*
+ * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
+ * NB: These match hardware order, so that addresses can
+ * easily be computed.
+ */
+#define GPIO_ID_OUT 0x00000000
+#define GPIO_ID_OUT_W1TS 0x00000001
+#define GPIO_ID_OUT_W1TC 0x00000002
+#define GPIO_ID_ENABLE 0x00000003
+#define GPIO_ID_ENABLE_W1TS 0x00000004
+#define GPIO_ID_ENABLE_W1TC 0x00000005
+#define GPIO_ID_IN 0x00000006
+#define GPIO_ID_STATUS 0x00000007
+#define GPIO_ID_STATUS_W1TS 0x00000008
+#define GPIO_ID_STATUS_W1TC 0x00000009
+#define GPIO_ID_PIN0 0x0000000a
+#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
+
+#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17)
+#define GPIO_ID_NONE 0xffffffff
diff --git a/drivers/net/wireless/ath6kl/include/gpio_api.h b/drivers/net/wireless/ath6kl/include/gpio_api.h
new file mode 100644
index 000000000000..82edcdd418bb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/gpio_api.h
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+// <copyright file="gpio_api.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Host-side General Purpose I/O API.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _GPIO_API_H_
+#define _GPIO_API_H_
+
+/*
+ * Send a command to the Target in order to change output on GPIO pins.
+ */
+A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
+ A_UINT32 set_mask,
+ A_UINT32 clear_mask,
+ A_UINT32 enable_mask,
+ A_UINT32 disable_mask);
+
+/*
+ * Send a command to the Target requesting input state of GPIO pins.
+ */
+A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
+
+/*
+ * Send a command to the Target to change the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
+ A_UINT32 gpioreg_id,
+ A_UINT32 value);
+
+/*
+ * Send a command to the Target to fetch the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
+
+/*
+ * Send a command to the Target, acknowledging some GPIO interrupts.
+ */
+A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
+
+#endif /* _GPIO_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/hci_transport_api.h b/drivers/net/wireless/ath6kl/include/hci_transport_api.h
new file mode 100644
index 000000000000..a6cc16fc325a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/hci_transport_api.h
@@ -0,0 +1,243 @@
+//------------------------------------------------------------------------------
+// <copyright file="HCI_TRANSPORT_api.h" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HCI_TRANSPORT_API_H_
+#define _HCI_TRANSPORT_API_H_
+
+ /* Bluetooth HCI packets are stored in HTC packet containers */
+#include "htc_packet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void *HCI_TRANSPORT_HANDLE;
+
+typedef HTC_ENDPOINT_ID HCI_TRANSPORT_PACKET_TYPE;
+
+ /* we map each HCI packet class to a static Endpoint ID */
+#define HCI_COMMAND_TYPE ENDPOINT_1
+#define HCI_EVENT_TYPE ENDPOINT_2
+#define HCI_ACL_TYPE ENDPOINT_3
+#define HCI_PACKET_INVALID ENDPOINT_MAX
+
+#define HCI_GET_PACKET_TYPE(pP) (pP)->Endpoint
+#define HCI_SET_PACKET_TYPE(pP,s) (pP)->Endpoint = (s)
+
+/* callback when an HCI packet was completely sent */
+typedef void (*HCI_TRANSPORT_SEND_PKT_COMPLETE)(void *, HTC_PACKET *);
+/* callback when an HCI packet is received */
+typedef void (*HCI_TRANSPORT_RECV_PKT)(void *, HTC_PACKET *);
+/* Optional receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack. The driver never gets the packets back from the OS. For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ * A refill callback is used for the reception of ACL and EVENT packets. The caller must
+ * set the watermark trigger point to cause a refill.
+ */
+typedef void (*HCI_TRANSPORT_RECV_REFILL)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable);
+/* Optional receive packet refill
+ * On some systems packet buffers are an extremely limited resource. Rather than
+ * queue largest-possible-sized buffers to the HCI bridge, some systems would rather
+ * allocate a specific size as the packet is received. The trade off is
+ * slightly more processing (callback invoked for each RX packet)
+ * for the benefit of committing fewer buffer resources into the bridge.
+ *
+ * The callback is provided the length of the pending packet to fetch. This includes the
+ * full transport header, HCI header, plus the length of payload. The callback can return a pointer to
+ * the allocated HTC packet for immediate use.
+ *
+ * NOTE*** This callback is mutually exclusive with the the refill callback above.
+ *
+ * */
+typedef HTC_PACKET *(*HCI_TRANSPORT_RECV_ALLOC)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int Length);
+
+typedef enum _HCI_SEND_FULL_ACTION {
+ HCI_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */
+ HCI_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */
+} HCI_SEND_FULL_ACTION;
+
+/* callback when an HCI send queue exceeds the caller's MaxSendQueueDepth threshold,
+ * the callback must return the send full action to take (either DROP or KEEP) */
+typedef HCI_SEND_FULL_ACTION (*HCI_TRANSPORT_SEND_FULL)(void *, HTC_PACKET *);
+
+typedef struct {
+ int HeadRoom; /* number of bytes in front of HCI packet for header space */
+ int TailRoom; /* number of bytes at the end of the HCI packet for tail space */
+ int IOBlockPad; /* I/O block padding required (always a power of 2) */
+} HCI_TRANSPORT_PROPERTIES;
+
+typedef struct _HCI_TRANSPORT_CONFIG_INFO {
+ int ACLRecvBufferWaterMark; /* low watermark to trigger recv refill */
+ int EventRecvBufferWaterMark; /* low watermark to trigger recv refill */
+ int MaxSendQueueDepth; /* max number of packets in the single send queue */
+ void *pContext; /* context for all callbacks */
+ void (*TransportFailure)(void *pContext, A_STATUS Status); /* transport failure callback */
+ A_STATUS (*TransportReady)(HCI_TRANSPORT_HANDLE, HCI_TRANSPORT_PROPERTIES *,void *pContext); /* transport is ready */
+ void (*TransportRemoved)(void *pContext); /* transport was removed */
+ /* packet processing callbacks */
+ HCI_TRANSPORT_SEND_PKT_COMPLETE pHCISendComplete;
+ HCI_TRANSPORT_RECV_PKT pHCIPktRecv;
+ HCI_TRANSPORT_RECV_REFILL pHCIPktRecvRefill;
+ HCI_TRANSPORT_RECV_ALLOC pHCIPktRecvAlloc;
+ HCI_TRANSPORT_SEND_FULL pHCISendFull;
+} HCI_TRANSPORT_CONFIG_INFO;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Attach to the HCI transport module
+ @function name: HCI_TransportAttach
+ @input: HTCHandle - HTC handle (see HTC apis)
+ pInfo - initialization information
+ @output:
+ @return: HCI_TRANSPORT_HANDLE on success, NULL on failure
+ @notes: The HTC module provides HCI transport services.
+ @example:
+ @see also: HCI_TransportDetach
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Detach from the HCI transport module
+ @function name: HCI_TransportDetach
+ @input: HciTrans - HCI transport handle
+ pInfo - initialization information
+ @output:
+ @return:
+ @notes:
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Add receive packets to the HCI transport
+ @function name: HCI_TransportAddReceivePkts
+ @input: HciTrans - HCI transport handle
+ pQueue - a queue holding one or more packets
+ @output:
+ @return: A_OK on success
+ @notes: user must supply HTC packets for capturing incomming HCI packets. The caller
+ must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+ macro. Each packet in the queue must be of the same type and length
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Send an HCI packet packet
+ @function name: HCI_TransportSendPkt
+ @input: HciTrans - HCI transport handle
+ pPacket - packet to send
+ Synchronous - send the packet synchronously (blocking)
+ @output:
+ @return: A_OK
+ @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() and
+ HCI_SET_PACKET_TYPE() macros to prepare the packet.
+ If Synchronous is set to FALSE the call is fully asynchronous. On error or completion,
+ the registered send complete callback will be called.
+ If Synchronous is set to TRUE, the call will block until the packet is sent, if the
+ interface cannot send the packet within a 2 second timeout, the function will return
+ the failure code : A_EBUSY.
+
+ Synchronous Mode should only be used at start-up to initialize the HCI device using
+ custom HCI commands. It should NOT be mixed with Asynchronous operations. Mixed synchronous
+ and asynchronous operation behavior is undefined.
+
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Stop HCI transport
+ @function name: HCI_TransportStop
+ @input: HciTrans - hci transport handle
+ @output:
+ @return:
+ @notes: HCI transport communication will be halted. All receive and pending TX packets will
+ be flushed.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Start the HCI transport
+ @function name: HCI_TransportStart
+ @input: HciTrans - hci transport handle
+ @output:
+ @return: A_OK on success
+ @notes: HCI transport communication will begin, the caller can expect the arrival
+ of HCI recv packets as soon as this call returns.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Enable or Disable Asynchronous Recv
+ @function name: HCI_TransportEnableDisableAsyncRecv
+ @input: HciTrans - hci transport handle
+ Enable - enable or disable asynchronous recv
+ @output:
+ @return: A_OK on success
+ @notes: This API must be called when HCI recv is handled synchronously
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Receive an event packet from the HCI transport synchronously using polling
+ @function name: HCI_TransportRecvHCIEventSync
+ @input: HciTrans - hci transport handle
+ pPacket - HTC packet to hold the recv data
+ MaxPollMS - maximum polling duration in Milliseconds;
+ @output:
+ @return: A_OK on success
+ @notes: This API should be used only during HCI device initialization, the caller must call
+ HCI_TransportEnableDisableAsyncRecv with Enable=FALSE prior to using this API.
+ This API will only capture HCI Event packets.
+ @example:
+ @see also: HCI_TransportEnableDisableAsyncRecv
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans,
+ HTC_PACKET *pPacket,
+ int MaxPollMS);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Set the desired baud rate for the underlying transport layer
+ @function name: HCI_TransportSetBaudRate
+ @input: HciTrans - hci transport handle
+ Baud - baud rate in bps
+ @output:
+ @return: A_OK on success
+ @notes: This API should be used only after HCI device initialization
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HCI_TRANSPORT_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/hif.h b/drivers/net/wireless/ath6kl/include/hif.h
new file mode 100644
index 000000000000..bc6e6a5b3448
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/hif.h
@@ -0,0 +1,421 @@
+//------------------------------------------------------------------------------
+// <copyright file="hif.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HIF specific declarations and prototypes
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HIF_H_
+#define _HIF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "dl_list.h"
+
+
+typedef struct htc_callbacks HTC_CALLBACKS;
+typedef struct hif_device HIF_DEVICE;
+
+/*
+ * direction - Direction of transfer (HIF_READ/HIF_WRITE).
+ */
+#define HIF_READ 0x00000001
+#define HIF_WRITE 0x00000002
+#define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
+
+/*
+ * type - An interface may support different kind of read/write commands.
+ * For example: SDIO supports CMD52/CMD53s. In case of MSIO it
+ * translates to using different kinds of TPCs. The command type
+ * is thus divided into a basic and an extended command and can
+ * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
+ */
+#define HIF_BASIC_IO 0x00000004
+#define HIF_EXTENDED_IO 0x00000008
+#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO)
+
+/*
+ * emode - This indicates the whether the command is to be executed in a
+ * blocking or non-blocking fashion (HIF_SYNCHRONOUS/
+ * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
+ * implemented using the asynchronous mode allowing the the bus
+ * driver to indicate the completion of operation through the
+ * registered callback routine. The requirement primarily comes
+ * from the contexts these operations get called from (a driver's
+ * transmit context or the ISR context in case of receive).
+ * Support for both of these modes is essential.
+ */
+#define HIF_SYNCHRONOUS 0x00000010
+#define HIF_ASYNCHRONOUS 0x00000020
+#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
+
+/*
+ * dmode - An interface may support different kinds of commands based on
+ * the tradeoff between the amount of data it can carry and the
+ * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
+ * HIF_BLOCK_BASIS). In case of latter, the data is rounded off
+ * to the nearest block size by padding. The size of the block is
+ * configurable at compile time using the HIF_BLOCK_SIZE and is
+ * negotiated with the target during initialization after the
+ * AR6000 interrupts are enabled.
+ */
+#define HIF_BYTE_BASIS 0x00000040
+#define HIF_BLOCK_BASIS 0x00000080
+#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
+
+/*
+ * amode - This indicates if the address has to be incremented on AR6000
+ * after every read/write operation (HIF?FIXED_ADDRESS/
+ * HIF_INCREMENTAL_ADDRESS).
+ */
+#define HIF_FIXED_ADDRESS 0x00000100
+#define HIF_INCREMENTAL_ADDRESS 0x00000200
+#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
+
+#define HIF_WR_ASYNC_BYTE_FIX \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_ASYNC_BYTE_INC \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_INC \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BYTE_FIX \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BYTE_INC \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_INC \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_FIX \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_FIX \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_SYNC_BYTE_INC \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BYTE_FIX \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_FIX \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_FIX \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_INC \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_INC \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_INC \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_FIX \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+
+typedef enum {
+ HIF_DEVICE_POWER_STATE = 0,
+ HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ HIF_DEVICE_GET_MBOX_ADDR,
+ HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+ HIF_DEVICE_GET_IRQ_PROC_MODE,
+ HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+ HIF_DEVICE_POWER_STATE_CHANGE,
+ HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
+ HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
+ HIF_DEVICE_GET_OS_DEVICE,
+ HIF_DEVICE_DEBUG_BUS_STATE,
+} HIF_DEVICE_CONFIG_OPCODE;
+
+/*
+ * HIF CONFIGURE definitions:
+ *
+ * HIF_DEVICE_GET_MBOX_BLOCK_SIZE
+ * input : none
+ * output : array of 4 A_UINT32s
+ * notes: block size is returned for each mailbox (4)
+ *
+ * HIF_DEVICE_GET_MBOX_ADDR
+ * input : none
+ * output : HIF_DEVICE_MBOX_INFO
+ * notes:
+ *
+ * HIF_DEVICE_GET_PENDING_EVENTS_FUNC
+ * input : none
+ * output: HIF_PENDING_EVENTS_FUNC function pointer
+ * notes: this is optional for the HIF layer, if the request is
+ * not handled then it indicates that the upper layer can use
+ * the standard device methods to get pending events (IRQs, mailbox messages etc..)
+ * otherwise it can call the function pointer to check pending events.
+ *
+ * HIF_DEVICE_GET_IRQ_PROC_MODE
+ * input : none
+ * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
+ * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
+ * layer can report whether IRQ processing is requires synchronous behavior or
+ * can be processed using asynchronous bus requests (typically faster).
+ *
+ * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
+ * input :
+ * output : HIF_MASK_UNMASK_RECV_EVENT function pointer
+ * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism
+ * to mask receive message events. The upper layer can call this pointer when it needs
+ * to mask/unmask receive events (in case it runs out of buffers).
+ *
+ * HIF_DEVICE_POWER_STATE_CHANGE
+ *
+ * input : HIF_DEVICE_POWER_CHANGE_TYPE
+ * output : none
+ * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change
+ * requests in an interconnect specific way. This is highly OS and bus driver dependent.
+ * The caller must guarantee that no HIF read/write requests will be made after the device
+ * is powered down.
+ *
+ * HIF_DEVICE_GET_IRQ_YIELD_PARAMS
+ *
+ * input : none
+ * output : HIF_DEVICE_IRQ_YIELD_PARAMS
+ * note: This query checks if the HIF layer wishes to impose a processing yield count for the DSR handler.
+ * The DSR callback handler will exit after a fixed number of RX packets or events are processed.
+ * This query is only made if the device reports an IRQ processing mode of HIF_DEVICE_IRQ_SYNC_ONLY.
+ * The HIF implementation can ignore this command if it does not desire the DSR callback to yield.
+ * The HIF layer can indicate the maximum number of IRQ processing units (RX packets) before the
+ * DSR handler callback must yield and return control back to the HIF layer. When a yield limit is
+ * used the DSR callback will not call HIFAckInterrupts() as it would normally do before returning.
+ * The HIF implementation that requires a yield count must call HIFAckInterrupt() when it is prepared
+ * to process interrupts again.
+ *
+ * HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT
+ * input : none
+ * output : HIF_DEVICE_SCATTER_SUPPORT_INFO
+ * note: This query checks if the HIF layer implements the SCATTER request interface. Scatter requests
+ * allows upper layers to submit mailbox I/O operations using a list of buffers. This is useful for
+ * multi-message transfers that can better utilize the bus interconnect.
+ *
+ *
+ * HIF_DEVICE_GET_OS_DEVICE
+ * intput : none
+ * output : HIF_DEVICE_OS_DEVICE_INFO;
+ * note: On some operating systems, the HIF layer has a parent device object for the bus. This object
+ * may be required to register certain types of logical devices.
+ *
+ * HIF_DEVICE_DEBUG_BUS_STATE
+ * input : none
+ * output : none
+ * note: This configure option triggers the HIF interface to dump as much bus interface state. This
+ * configuration request is optional (No-OP on some HIF implementations)
+ *
+ */
+
+typedef struct {
+ A_UINT32 ExtendedAddress; /* extended address for larger writes */
+ A_UINT32 ExtendedSize;
+} HIF_MBOX_PROPERTIES;
+
+#define HIF_MBOX_FLAG_NO_BUNDLING (1 << 0) /* do not allow bundling over the mailbox */
+
+typedef struct {
+ A_UINT32 MboxAddresses[4]; /* must be first element for legacy HIFs that return the address in
+ and ARRAY of 32-bit words */
+
+ /* the following describe extended mailbox properties */
+ HIF_MBOX_PROPERTIES MboxProp[4];
+ /* if the HIF supports the GMbox extended address region it can report it
+ * here, some interfaces cannot support the GMBOX address range and not set this */
+ A_UINT32 GMboxAddress;
+ A_UINT32 GMboxSize;
+ A_UINT32 Flags; /* flags to describe mbox behavior or usage */
+} HIF_DEVICE_MBOX_INFO;
+
+typedef enum {
+ HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all
+ interrupts before returning */
+ HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts
+ using ASYNC I/O (that is HIFAckInterrupt can be called at a
+ later time */
+} HIF_DEVICE_IRQ_PROCESSING_MODE;
+
+typedef enum {
+ HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */
+ HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */
+ HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures
+ to completely power-off the module and associated hardware (i.e. cut power supplies)
+ */
+} HIF_DEVICE_POWER_CHANGE_TYPE;
+
+typedef struct {
+ int RecvPacketYieldCount; /* max number of packets to force DSR to return */
+} HIF_DEVICE_IRQ_YIELD_PARAMS;
+
+
+typedef struct _HIF_SCATTER_ITEM {
+ A_UINT8 *pBuffer; /* CPU accessible address of buffer */
+ int Length; /* length of transfer to/from this buffer */
+ void *pCallerContexts[2]; /* space for caller to insert a context associated with this item */
+} HIF_SCATTER_ITEM;
+
+struct _HIF_SCATTER_REQ;
+
+typedef void ( *HIF_SCATTER_COMP_CB)(struct _HIF_SCATTER_REQ *);
+
+typedef enum _HIF_SCATTER_METHOD {
+ HIF_SCATTER_NONE = 0,
+ HIF_SCATTER_DMA_REAL, /* Real SG support no restrictions */
+ HIF_SCATTER_DMA_BOUNCE, /* Uses SG DMA but HIF layer uses an internal bounce buffer */
+} HIF_SCATTER_METHOD;
+
+typedef struct _HIF_SCATTER_REQ {
+ DL_LIST ListLink; /* link management */
+ A_UINT32 Address; /* address for the read/write operation */
+ A_UINT32 Request; /* request flags */
+ A_UINT32 TotalLength; /* total length of entire transfer */
+ A_UINT32 CallerFlags; /* caller specific flags can be stored here */
+ HIF_SCATTER_COMP_CB CompletionRoutine; /* completion routine set by caller */
+ A_STATUS CompletionStatus; /* status of completion */
+ void *Context; /* caller context for this request */
+ int ValidScatterEntries; /* number of valid entries set by caller */
+ HIF_SCATTER_METHOD ScatterMethod; /* scatter method handled by HIF */
+ void *HIFPrivate[4]; /* HIF private area */
+ A_UINT8 *pScatterBounceBuffer; /* bounce buffer for upper layers to copy to/from */
+ HIF_SCATTER_ITEM ScatterList[1]; /* start of scatter list */
+} HIF_SCATTER_REQ;
+
+typedef HIF_SCATTER_REQ * ( *HIF_ALLOCATE_SCATTER_REQUEST)(HIF_DEVICE *device);
+typedef void ( *HIF_FREE_SCATTER_REQUEST)(HIF_DEVICE *device, HIF_SCATTER_REQ *request);
+typedef A_STATUS ( *HIF_READWRITE_SCATTER)(HIF_DEVICE *device, HIF_SCATTER_REQ *request);
+
+typedef struct _HIF_DEVICE_SCATTER_SUPPORT_INFO {
+ /* information returned from HIF layer */
+ HIF_ALLOCATE_SCATTER_REQUEST pAllocateReqFunc;
+ HIF_FREE_SCATTER_REQUEST pFreeReqFunc;
+ HIF_READWRITE_SCATTER pReadWriteScatterFunc;
+ int MaxScatterEntries;
+ int MaxTransferSizePerScatterReq;
+} HIF_DEVICE_SCATTER_SUPPORT_INFO;
+
+typedef struct {
+ void *pOSDevice;
+} HIF_DEVICE_OS_DEVICE_INFO;
+
+#define HIF_MAX_DEVICES 1
+
+struct htc_callbacks {
+ void *context; /* context to pass to the dsrhandler
+ note : rwCompletionHandler is provided the context passed to HIFReadWrite */
+ A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status);
+ A_STATUS (* dsrHandler)(void *context);
+};
+
+typedef struct osdrv_callbacks {
+ void *context; /* context to pass for all callbacks except deviceRemovedHandler
+ the deviceRemovedHandler is only called if the device is claimed */
+ A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle);
+ A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle);
+ A_STATUS (* deviceSuspendHandler)(void *context);
+ A_STATUS (* deviceResumeHandler)(void *context);
+ A_STATUS (* deviceWakeupHandler)(void *context);
+} OSDRV_CALLBACKS;
+
+#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host
+ needs to read the register table to figure out what */
+#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */
+
+typedef struct _HIF_PENDING_EVENTS_INFO {
+ A_UINT32 Events;
+ A_UINT32 LookAhead;
+ A_UINT32 AvailableRecvBytes;
+} HIF_PENDING_EVENTS_INFO;
+
+ /* function to get pending events , some HIF modules use special mechanisms
+ * to detect packet available and other interrupts */
+typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device,
+ HIF_PENDING_EVENTS_INFO *pEvents,
+ void *AsyncContext);
+
+#define HIF_MASK_RECV TRUE
+#define HIF_UNMASK_RECV FALSE
+ /* function to mask recv events */
+typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device,
+ A_BOOL Mask,
+ void *AsyncContext);
+
+
+/*
+ * This API is used to perform any global initialization of the HIF layer
+ * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
+ *
+ */
+A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks);
+
+/* This API claims the HIF device and provides a context for handling removal.
+ * The device removal callback is only called when the OSDRV layer claims
+ * a device. The claimed context must be non-NULL */
+void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext);
+/* release the claimed device */
+void HIFReleaseDevice(HIF_DEVICE *device);
+
+/* This API allows the HTC layer to attach to the HIF device */
+A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks);
+/* This API detaches the HTC layer from the HIF device */
+void HIFDetachHTC(HIF_DEVICE *device);
+
+/*
+ * This API is used to provide the read/write interface over the specific bus
+ * interface.
+ * address - Starting address in the AR6000's address space. For mailbox
+ * writes, it refers to the start of the mbox boundary. It should
+ * be ensured that the last byte falls on the mailbox's EOM. For
+ * mailbox reads, it refers to the end of the mbox boundary.
+ * buffer - Pointer to the buffer containg the data to be transmitted or
+ * received.
+ * length - Amount of data to be transmitted or received.
+ * request - Characterizes the attributes of the command.
+ */
+A_STATUS
+HIFReadWrite(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_UINT32 request,
+ void *context);
+
+/*
+ * This can be initiated from the unload driver context when the OSDRV layer has no more use for
+ * the device.
+ */
+void HIFShutDownDevice(HIF_DEVICE *device);
+
+/*
+ * This should translate to an acknowledgment to the bus driver indicating that
+ * the previous interrupt request has been serviced and the all the relevant
+ * sources have been cleared. HTC is ready to process more interrupts.
+ * This should prevent the bus driver from raising an interrupt unless the
+ * previous one has been serviced and acknowledged using the previous API.
+ */
+void HIFAckInterrupt(HIF_DEVICE *device);
+
+void HIFMaskInterrupt(HIF_DEVICE *device);
+
+void HIFUnMaskInterrupt(HIF_DEVICE *device);
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+ void *config, A_UINT32 configLen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HIF_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/host_version.h b/drivers/net/wireless/ath6kl/include/host_version.h
new file mode 100644
index 000000000000..8e464997ecf5
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/host_version.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="host_version.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains version information for the sample host driver for the
+// AR6000 chip
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_VERSION_H_
+#define _HOST_VERSION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <AR6002/AR6K_version.h>
+
+/*
+ * The version number is made up of major, minor, patch and build
+ * numbers. These are 16 bit numbers. The build and release script will
+ * set the build number using a Perforce counter. Here the build number is
+ * set to 9999 so that builds done without the build-release script are easily
+ * identifiable.
+ */
+
+#define ATH_SW_VER_MAJOR __VER_MAJOR_
+#define ATH_SW_VER_MINOR __VER_MINOR_
+#define ATH_SW_VER_PATCH __VER_PATCH_
+#define ATH_SW_VER_BUILD __BUILD_NUMBER_
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_VERSION_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/htc.h b/drivers/net/wireless/ath6kl/include/htc.h
new file mode 100644
index 000000000000..515c8ec62bdf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc.h
@@ -0,0 +1,232 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __HTC_H__
+#define __HTC_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+
+#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
+ (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
+
+/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
+ * structure using only the type and field name.
+ * Use these macros if there is the potential for unaligned buffer accesses. */
+#define A_GET_UINT16_FIELD(p,type,field) \
+ ASSEMBLE_UNALIGNED_UINT16(p,\
+ A_OFFSETOF(type,field) + 1, \
+ A_OFFSETOF(type,field))
+
+#define A_SET_UINT16_FIELD(p,type,field,value) \
+{ \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
+}
+
+#define A_GET_UINT8_FIELD(p,type,field) \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
+
+#define A_SET_UINT8_FIELD(p,type,field,value) \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
+
+/****** DANGER DANGER ***************
+ *
+ * The frame header length and message formats defined herein were
+ * selected to accommodate optimal alignment for target processing. This reduces code
+ * size and improves performance.
+ *
+ * Any changes to the header length may alter the alignment and cause exceptions
+ * on the target. When adding to the message structures insure that fields are
+ * properly aligned.
+ *
+ */
+
+/* HTC frame header */
+typedef PREPACK struct _HTC_FRAME_HDR{
+ /* do not remove or re-arrange these fields, these are minimally required
+ * to take advantage of 4-byte lookaheads in some hardware implementations */
+ A_UINT8 EndpointID;
+ A_UINT8 Flags;
+ A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */
+
+ /***** end of 4-byte lookahead ****/
+
+ A_UINT8 ControlBytes[2];
+
+ /* message payload starts after the header */
+
+} POSTPACK HTC_FRAME_HDR;
+
+/* frame header flags */
+
+ /* send direction */
+#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
+#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
+ /* receive direction */
+#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */
+#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
+#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */
+#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4
+
+#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
+#define HTC_MAX_TRAILER_LENGTH 255
+#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
+
+/* HTC control message IDs */
+
+#define HTC_MSG_READY_ID 1
+#define HTC_MSG_CONNECT_SERVICE_ID 2
+#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
+#define HTC_MSG_SETUP_COMPLETE_ID 4
+#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
+
+#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
+
+/* base message ID header */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+} POSTPACK HTC_UNKNOWN_MSG;
+
+/* HTC ready message
+ * direction : target-to-host */
+typedef PREPACK struct {
+ A_UINT16 MessageID; /* ID */
+ A_UINT16 CreditCount; /* number of credits the target can offer */
+ A_UINT16 CreditSize; /* size of each credit */
+ A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */
+ A_UINT8 _Pad1;
+} POSTPACK HTC_READY_MSG;
+
+ /* extended HTC ready message */
+typedef PREPACK struct {
+ HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
+ /* extended information */
+ A_UINT8 HTCVersion;
+ A_UINT8 MaxMsgsPerHTCBundle;
+} POSTPACK HTC_READY_EX_MSG;
+
+#define HTC_VERSION_2P0 0x00
+#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
+
+#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
+
+/* connect service
+ * direction : host-to-target */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ A_UINT16 ServiceID; /* service ID of the service to connect to */
+ A_UINT16 ConnectionFlags; /* connection flags */
+
+#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
+ the host needs credits */
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
+
+ A_UINT8 ServiceMetaLength; /* length of meta data that follows */
+ A_UINT8 _Pad1;
+
+ /* service-specific meta data starts after the header */
+
+} POSTPACK HTC_CONNECT_SERVICE_MSG;
+
+/* connect response
+ * direction : target-to-host */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ A_UINT16 ServiceID; /* service ID that the connection request was made */
+ A_UINT8 Status; /* service connection status */
+ A_UINT8 EndpointID; /* assigned endpoint ID */
+ A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */
+ A_UINT8 ServiceMetaLength; /* length of meta data that follows */
+ A_UINT8 _Pad1;
+
+ /* service-specific meta data starts after the header */
+
+} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
+
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ /* currently, no other fields */
+} POSTPACK HTC_SETUP_COMPLETE_MSG;
+
+ /* extended setup completion message */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ A_UINT32 SetupFlags;
+ A_UINT8 MaxMsgsPerBundledRecv;
+ A_UINT8 Rsvd[3];
+} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
+
+#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0)
+
+/* connect response status codes */
+#define HTC_SERVICE_SUCCESS 0 /* success */
+#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
+#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
+#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
+#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
+ endpoints */
+
+/* report record IDs */
+
+#define HTC_RECORD_NULL 0
+#define HTC_RECORD_CREDITS 1
+#define HTC_RECORD_LOOKAHEAD 2
+#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
+
+typedef PREPACK struct {
+ A_UINT8 RecordID; /* Record ID */
+ A_UINT8 Length; /* Length of record */
+} POSTPACK HTC_RECORD_HDR;
+
+typedef PREPACK struct {
+ A_UINT8 EndpointID; /* Endpoint that owns these credits */
+ A_UINT8 Credits; /* credits to report since last report */
+} POSTPACK HTC_CREDIT_REPORT;
+
+typedef PREPACK struct {
+ A_UINT8 PreValid; /* pre valid guard */
+ A_UINT8 LookAhead[4]; /* 4 byte lookahead */
+ A_UINT8 PostValid; /* post valid guard */
+
+ /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
+ * The PreValid bytes must equal the inverse of the PostValid byte */
+
+} POSTPACK HTC_LOOKAHEAD_REPORT;
+
+typedef PREPACK struct {
+ A_UINT8 LookAhead[4]; /* 4 byte lookahead */
+} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+
+#endif /* __HTC_H__ */
+
diff --git a/drivers/net/wireless/ath6kl/include/htc_api.h b/drivers/net/wireless/ath6kl/include/htc_api.h
new file mode 100644
index 000000000000..12f81f53ee90
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc_api.h
@@ -0,0 +1,568 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_api.h" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HTC_API_H_
+#define _HTC_API_H_
+
+#include <htc.h>
+#include <htc_services.h>
+#include "htc_packet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* TODO.. for BMI */
+#define ENDPOINT1 0
+// TODO -remove me, but we have to fix BMI first
+#define HTC_MAILBOX_NUM_MAX 4
+
+/* this is the amount of header room required by users of HTC */
+#define HTC_HEADER_LEN HTC_HDR_LENGTH
+
+typedef void *HTC_HANDLE;
+
+typedef A_UINT16 HTC_SERVICE_ID;
+
+typedef struct _HTC_INIT_INFO {
+ void *pContext; /* context for target failure notification */
+ void (*TargetFailure)(void *Instance, A_STATUS Status);
+} HTC_INIT_INFO;
+
+/* per service connection send completion */
+typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *);
+/* per service connection callback when a plurality of packets have been sent
+ * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
+ * to hold a list of completed send packets.
+ * If the handler cannot fully traverse the packet queue before returning, it should
+ * transfer the items of the queue into the caller's private queue using:
+ * HTC_PACKET_ENQUEUE() */
+typedef void (*HTC_EP_SEND_PKT_COMP_MULTIPLE)(void *,HTC_PACKET_QUEUE *);
+/* per service connection pkt received */
+typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *);
+/* per service connection callback when a plurality of packets are received
+ * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
+ * to hold a list of recv packets.
+ * If the handler cannot fully traverse the packet queue before returning, it should
+ * transfer the items of the queue into the caller's private queue using:
+ * HTC_PACKET_ENQUEUE() */
+typedef void (*HTC_EP_RECV_PKT_MULTIPLE)(void *,HTC_PACKET_QUEUE *);
+
+/* Optional per service connection receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack. The driver never gets the packets back from the OS. For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ *
+ * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
+ * the driver can re-queue these buffers into HTC. In this regard a refill callback is
+ * unnecessary */
+typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
+
+/* Optional per service connection receive buffer allocation callback.
+ * On some systems packet buffers are an extremely limited resource. Rather than
+ * queue largest-possible-sized buffers to HTC, some systems would rather
+ * allocate a specific size as the packet is received. The trade off is
+ * slightly more processing (callback invoked for each RX packet)
+ * for the benefit of committing fewer buffer resources into HTC.
+ *
+ * The callback is provided the length of the pending packet to fetch. This includes the
+ * HTC header length plus the length of payload. The callback can return a pointer to
+ * the allocated HTC packet for immediate use.
+ *
+ * Alternatively a variant of this handler can be used to allocate large receive packets as needed.
+ * For example an application can use the refill mechanism for normal packets and the recv-alloc mechanism to
+ * handle the case where a large packet buffer is required. This can significantly reduce the
+ * amount of "committed" memory used to receive packets.
+ *
+ * */
+typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length);
+
+typedef enum _HTC_SEND_FULL_ACTION {
+ HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */
+ HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */
+} HTC_SEND_FULL_ACTION;
+
+/* Optional per service connection callback when a send queue is full. This can occur if the
+ * host continues queueing up TX packets faster than credits can arrive
+ * To prevent the host (on some Oses like Linux) from continuously queueing packets
+ * and consuming resources, this callback is provided so that that the host
+ * can disable TX in the subsystem (i.e. network stack).
+ * This callback is invoked for each packet that "overflows" the HTC queue. The callback can
+ * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or
+ * dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called
+ * and the packet's status field will be set to A_NO_RESOURCE.
+ * Other OSes require a "per-packet" indication for each completed TX packet, this
+ * closed loop mechanism will prevent the network stack from overunning the NIC
+ * The packet to keep or drop is passed for inspection to the registered handler the handler
+ * must ONLY inspect the packet, it may not free or reclaim the packet. */
+typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket);
+
+typedef struct _HTC_EP_CALLBACKS {
+ void *pContext; /* context for each callback */
+ HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */
+ HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */
+ HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */
+ HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */
+ HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */
+ HTC_EP_RECV_ALLOC EpRecvAllocThresh; /* OPTIONAL recv allocation callback based on a threshold */
+ HTC_EP_SEND_PKT_COMP_MULTIPLE EpTxCompleteMultiple; /* OPTIONAL completion handler for multiple complete
+ indications (EpTxComplete must be NULL) */
+ HTC_EP_RECV_PKT_MULTIPLE EpRecvPktMultiple; /* OPTIONAL completion handler for multiple
+ recv packet indications (EpRecv must be NULL) */
+ int RecvAllocThreshold; /* if EpRecvAllocThresh is non-NULL, HTC will compare the
+ threshold value to the current recv packet length and invoke
+ the EpRecvAllocThresh callback to acquire a packet buffer */
+ int RecvRefillWaterMark; /* if a EpRecvRefill handler is provided, this value
+ can be used to set a trigger refill callback
+ when the recv queue drops below this value
+ if set to 0, the refill is only called when packets
+ are empty */
+} HTC_EP_CALLBACKS;
+
+/* service connection information */
+typedef struct _HTC_SERVICE_CONNECT_REQ {
+ HTC_SERVICE_ID ServiceID; /* service ID to connect to */
+ A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */
+ A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */
+ A_UINT8 MetaDataLength; /* optional meta data length */
+ HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */
+ int MaxSendQueueDepth; /* maximum depth of any send queue */
+ A_UINT32 LocalConnectionFlags; /* HTC flags for the host-side (local) connection */
+ unsigned int MaxSendMsgSize; /* override max message size in send direction */
+} HTC_SERVICE_CONNECT_REQ;
+
+#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0) /* enable send bundle padding for this endpoint */
+
+/* service connection response information */
+typedef struct _HTC_SERVICE_CONNECT_RESP {
+ A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */
+ A_UINT8 BufferLength; /* length of caller supplied buffer */
+ A_UINT8 ActualLength; /* actual length of meta data */
+ HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */
+ unsigned int MaxMsgLength; /* max length of all messages over this endpoint */
+ A_UINT8 ConnectRespCode; /* connect response code from target */
+} HTC_SERVICE_CONNECT_RESP;
+
+/* endpoint distribution structure */
+typedef struct _HTC_ENDPOINT_CREDIT_DIST {
+ struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
+ struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
+ HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */
+ HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */
+ A_UINT32 DistFlags; /* distribution flags, distribution function can
+ set default activity using SET_EP_ACTIVE() macro */
+ int TxCreditsNorm; /* credits for normal operation, anything above this
+ indicates the endpoint is over-subscribed, this field
+ is only relevant to the credit distribution function */
+ int TxCreditsMin; /* floor for credit distribution, this field is
+ only relevant to the credit distribution function */
+ int TxCreditsAssigned; /* number of credits assigned to this EP, this field
+ is only relevant to the credit dist function */
+ int TxCredits; /* current credits available, this field is used by
+ HTC to determine whether a message can be sent or
+ must be queued */
+ int TxCreditsToDist; /* pending credits to distribute on this endpoint, this
+ is set by HTC when credit reports arrive.
+ The credit distribution functions sets this to zero
+ when it distributes the credits */
+ int TxCreditsSeek; /* this is the number of credits that the current pending TX
+ packet needs to transmit. This is set by HTC when
+ and endpoint needs credits in order to transmit */
+ int TxCreditSize; /* size in bytes of each credit (set by HTC) */
+ int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
+ void *pHTCReserved; /* reserved for HTC use */
+ int TxQueueDepth; /* current depth of TX queue , i.e. messages waiting for credits
+ This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE
+ or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint
+ that has non-zero credits to recover
+ */
+} HTC_ENDPOINT_CREDIT_DIST;
+
+#define HTC_EP_ACTIVE ((A_UINT32) (1u << 31))
+
+/* macro to check if an endpoint has gone active, useful for credit
+ * distributions */
+#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE)
+#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
+
+ /* credit distibution code that is passed into the distrbution function,
+ * there are mandatory and optional codes that must be handled */
+typedef enum _HTC_CREDIT_DIST_REASON {
+ HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed
+ send operations (MANDATORY) resulting in credit reports */
+ HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */
+ HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */
+ HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by
+ the distribution function */
+} HTC_CREDIT_DIST_REASON;
+
+typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ HTC_CREDIT_DIST_REASON Reason);
+
+typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ int TotalCredits);
+
+ /* endpoint statistics action */
+typedef enum _HTC_ENDPOINT_STAT_ACTION {
+ HTC_EP_STAT_SAMPLE = 0, /* only read statistics */
+ HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */
+ HTC_EP_STAT_CLEAR /* clear only */
+} HTC_ENDPOINT_STAT_ACTION;
+
+ /* endpoint statistics */
+typedef struct _HTC_ENDPOINT_STATS {
+ A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on
+ this endpoint */
+ A_UINT32 TxIssued; /* running count of total TX packets issued */
+ A_UINT32 TxPacketsBundled; /* running count of TX packets that were issued in bundles */
+ A_UINT32 TxBundles; /* running count of TX bundles that were issued */
+ A_UINT32 TxDropped; /* tx packets that were dropped */
+ A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */
+ A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */
+ A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */
+ A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */
+ A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */
+ A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */
+ A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */
+ A_UINT32 TxCreditsConsummed; /* count of consummed credits */
+ A_UINT32 TxCreditsReturned; /* count of credits returned */
+ A_UINT32 RxReceived; /* count of RX packets received */
+ A_UINT32 RxLookAheads; /* count of lookahead records
+ found in messages received on this endpoint */
+ A_UINT32 RxPacketsBundled; /* count of recv packets received in a bundle */
+ A_UINT32 RxBundleLookAheads; /* count of number of bundled lookaheads */
+ A_UINT32 RxBundleIndFromHdr; /* count of the number of bundle indications from the HTC header */
+ A_UINT32 RxAllocThreshHit; /* count of the number of times the recv allocation threshhold was hit */
+ A_UINT32 RxAllocThreshBytes; /* total number of bytes */
+} HTC_ENDPOINT_STATS;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Create an instance of HTC over the underlying HIF device
+ @function name: HTCCreate
+ @input: HifDevice - hif device handle,
+ pInfo - initialization information
+ @output:
+ @return: HTC_HANDLE on success, NULL on failure
+ @notes:
+ @example:
+ @see also: HTCDestroy
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Get the underlying HIF device handle
+ @function name: HTCGetHifDevice
+ @input: HTCHandle - handle passed into the AddInstance callback
+ @output:
+ @return: opaque HIF device handle usable in HIF API calls.
+ @notes:
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void *HTCGetHifDevice(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Set credit distribution parameters
+ @function name: HTCSetCreditDistribution
+ @input: HTCHandle - HTC handle
+ pCreditDistCont - caller supplied context to pass into distribution functions
+ CreditDistFunc - Distribution function callback
+ CreditDistInit - Credit Distribution initialization callback
+ ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
+ priority
+ ListLength - number of elements in ServicePriorityOrder
+ @output:
+ @return:
+ @notes: The user can set a custom credit distribution function to handle special requirements
+ for each endpoint. A default credit distribution routine can be used by setting
+ CreditInitFunc to NULL. The default credit distribution is only provided for simple
+ "fair" credit distribution without regard to any prioritization.
+
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
+ void *pCreditDistContext,
+ HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+ HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+ HTC_SERVICE_ID ServicePriorityOrder[],
+ int ListLength);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Wait for the target to indicate the HTC layer is ready
+ @function name: HTCWaitTarget
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: This API blocks until the target responds with an HTC ready message.
+ The caller should not connect services until the target has indicated it is
+ ready.
+ @example:
+ @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Start target service communications
+ @function name: HTCStart
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: This API indicates to the target that the service connection phase is complete
+ and the target can freely start all connected services. This API should only be
+ called AFTER all service connections have been made. TCStart will issue a
+ SETUP_COMPLETE message to the target to indicate that all service connections
+ have been made and the target can start communicating over the endpoints.
+ @example:
+ @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCStart(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Add receive packet to HTC
+ @function name: HTCAddReceivePkt
+ @input: HTCHandle - HTC handle
+ pPacket - HTC receive packet to add
+ @output:
+ @return: A_OK on success
+ @notes: user must supply HTC packets for capturing incomming HTC frames. The caller
+ must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+ macro.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Connect to an HTC service
+ @function name: HTCConnectService
+ @input: HTCHandle - HTC handle
+ pReq - connection details
+ @output: pResp - connection response
+ @return:
+ @notes: Service connections must be performed before HTCStart. User provides callback handlers
+ for various endpoint events.
+ @example:
+ @see also: HTCStart
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCConnectService(HTC_HANDLE HTCHandle,
+ HTC_SERVICE_CONNECT_REQ *pReq,
+ HTC_SERVICE_CONNECT_RESP *pResp);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Send an HTC packet
+ @function name: HTCSendPkt
+ @input: HTCHandle - HTC handle
+ pPacket - packet to send
+ @output:
+ @return: A_OK
+ @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
+ This interface is fully asynchronous. On error, HTC SendPkt will
+ call the registered Endpoint callback to cleanup the packet.
+ @example:
+ @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Stop HTC service communications
+ @function name: HTCStop
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: HTC communications is halted. All receive and pending TX packets will
+ be flushed.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCStop(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Destory HTC service
+ @function name: HTCDestroy
+ @input: HTCHandle
+ @output:
+ @return:
+ @notes: This cleans up all resources allocated by HTCCreate().
+ @example:
+ @see also: HTCCreate
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCDestroy(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Flush pending TX packets
+ @function name: HTCFlushEndpoint
+ @input: HTCHandle - HTC handle
+ Endpoint - Endpoint to flush
+ Tag - flush tag
+ @output:
+ @return:
+ @notes: The Tag parameter is used to selectively flush packets with matching tags.
+ The value of 0 forces all packets to be flush regardless of tag.
+ @example:
+ @see also: HTCSendPkt
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Dump credit distribution state
+ @function name: HTCDumpCreditStates
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: This dumps all credit distribution information to the debugger
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCDumpCreditStates(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Indicate a traffic activity change on an endpoint
+ @function name: HTCIndicateActivityChange
+ @input: HTCHandle - HTC handle
+ Endpoint - endpoint in which activity has changed
+ Active - TRUE if active, FALSE if it has become inactive
+ @output:
+ @return:
+ @notes: This triggers the registered credit distribution function to
+ re-adjust credits for active/inactive endpoints.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCIndicateActivityChange(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ A_BOOL Active);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Get endpoint statistics
+ @function name: HTCGetEndpointStatistics
+ @input: HTCHandle - HTC handle
+ Endpoint - Endpoint identifier
+ Action - action to take with statistics
+ @output:
+ pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
+
+ @return: TRUE if statistics profiling is enabled, otherwise FALSE.
+
+ @notes: Statistics is a compile-time option and this function may return FALSE
+ if HTC is not compiled with profiling.
+
+ The caller can specify the statistic "action" to take when sampling
+ the statistics. This includes:
+
+ HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
+ HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
+ are cleared.
+ HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
+ pStats
+
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ HTC_ENDPOINT_STAT_ACTION Action,
+ HTC_ENDPOINT_STATS *pStats);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Unblock HTC message reception
+ @function name: HTCUnblockRecv
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes:
+ HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet.
+ The caller can use this API to indicate to HTC when resources (buffers) are available
+ such that the receiver can be unblocked and HTC may re-attempt fetching the pending message.
+
+ This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket()
+ API to recycle or provide receive packets to HTC.
+
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCUnblockRecv(HTC_HANDLE HTCHandle);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: send a series of HTC packets
+ @function name: HTCSendPktsMultiple
+ @input: HTCHandle - HTC handle
+ pPktQueue - local queue holding packets to send
+ @output:
+ @return: A_OK
+ @notes: Caller must initialize each packet using SET_HTC_PACKET_INFO_TX() macro.
+ The queue must only contain packets directed at the same endpoint.
+ Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the TX packets in FIFO order.
+ This API will remove the packets from the pkt queue and place them into the HTC Tx Queue
+ and bundle messages where possible.
+ The caller may allocate the pkt queue on the stack to hold the packets.
+ This interface is fully asynchronous. On error, HTCSendPkts will
+ call the registered Endpoint callback to cleanup the packet.
+ @example:
+ @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Add multiple receive packets to HTC
+ @function name: HTCAddReceivePktMultiple
+ @input: HTCHandle - HTC handle
+ pPktQueue - HTC receive packet queue holding packets to add
+ @output:
+ @return: A_OK on success
+ @notes: user must supply HTC packets for capturing incomming HTC frames. The caller
+ must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+ macro. The queue must only contain recv packets for the same endpoint.
+ Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the recv packet.
+ This API will remove the packets from the pkt queue and place them into internal
+ recv packet list.
+ The caller may allocate the pkt queue on the stack to hold the packets.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Check if an endpoint is marked active
+ @function name: HTCIsEndpointActive
+ @input: HTCHandle - HTC handle
+ Endpoint - endpoint to check for active state
+ @output:
+ @return: returns TRUE if Endpoint is Active
+ @notes:
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL HTCIsEndpointActive(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint);
+
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Get the number of recv buffers currently queued into an HTC endpoint
+ @function name: HTCGetNumRecvBuffers
+ @input: HTCHandle - HTC handle
+ Endpoint - endpoint to check
+ @output:
+ @return: returns number of buffers in queue
+ @notes:
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint);
+
+/* internally used functions for testing... */
+void HTCEnableRecv(HTC_HANDLE HTCHandle);
+void HTCDisableRecv(HTC_HANDLE HTCHandle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/htc_packet.h b/drivers/net/wireless/ath6kl/include/htc_packet.h
new file mode 100644
index 000000000000..26b20f2183f3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc_packet.h
@@ -0,0 +1,223 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_packet.h" company="Atheros">
+// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef HTC_PACKET_H_
+#define HTC_PACKET_H_
+
+
+#include "dl_list.h"
+
+/* ------ Endpoint IDS ------ */
+typedef enum
+{
+ ENDPOINT_UNUSED = -1,
+ ENDPOINT_0 = 0,
+ ENDPOINT_1 = 1,
+ ENDPOINT_2 = 2,
+ ENDPOINT_3,
+ ENDPOINT_4,
+ ENDPOINT_5,
+ ENDPOINT_6,
+ ENDPOINT_7,
+ ENDPOINT_8,
+ ENDPOINT_MAX,
+} HTC_ENDPOINT_ID;
+
+struct _HTC_PACKET;
+
+typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *);
+
+typedef A_UINT16 HTC_TX_TAG;
+
+typedef struct _HTC_TX_PACKET_INFO {
+ HTC_TX_TAG Tag; /* tag used to selective flush packets */
+ int CreditsUsed; /* number of credits used for this TX packet (HTC internal) */
+ A_UINT8 SendFlags; /* send flags (HTC internal) */
+ int SeqNo; /* internal seq no for debugging (HTC internal) */
+} HTC_TX_PACKET_INFO;
+
+#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */
+#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */
+#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
+
+typedef struct _HTC_RX_PACKET_INFO {
+ A_UINT32 ExpectedHdr; /* HTC internal use */
+ A_UINT32 HTCRxFlags; /* HTC internal use */
+ A_UINT32 IndicationFlags; /* indication flags set on each RX packet indication */
+} HTC_RX_PACKET_INFO;
+
+#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) /* more packets on this endpoint are being fetched */
+
+/* wrapper around endpoint-specific packets */
+typedef struct _HTC_PACKET {
+ DL_LIST ListLink; /* double link */
+ void *pPktContext; /* caller's per packet specific context */
+
+ A_UINT8 *pBufferStart; /* the true buffer start , the caller can
+ store the real buffer start here. In
+ receive callbacks, the HTC layer sets pBuffer
+ to the start of the payload past the header. This
+ field allows the caller to reset pBuffer when it
+ recycles receive packets back to HTC */
+ /*
+ * Pointer to the start of the buffer. In the transmit
+ * direction this points to the start of the payload. In the
+ * receive direction, however, the buffer when queued up
+ * points to the start of the HTC header but when returned
+ * to the caller points to the start of the payload
+ */
+ A_UINT8 *pBuffer; /* payload start (RX/TX) */
+ A_UINT32 BufferLength; /* length of buffer */
+ A_UINT32 ActualLength; /* actual length of payload */
+ HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */
+ A_STATUS Status; /* completion status */
+ union {
+ HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */
+ HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */
+ } PktInfo;
+
+ /* the following fields are for internal HTC use */
+ HTC_PACKET_COMPLETION Completion; /* completion */
+ void *pContext; /* HTC private completion context */
+} HTC_PACKET;
+
+
+
+#define COMPLETE_HTC_PACKET(p,status) \
+{ \
+ (p)->Status = (status); \
+ (p)->Completion((p)->pContext,(p)); \
+}
+
+#define INIT_HTC_PACKET_INFO(p,b,len) \
+{ \
+ (p)->pBufferStart = (b); \
+ (p)->BufferLength = (len); \
+}
+
+/* macro to set an initial RX packet for refilling HTC */
+#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
+{ \
+ (p)->pPktContext = (c); \
+ (p)->pBuffer = (b); \
+ (p)->pBufferStart = (b); \
+ (p)->BufferLength = (len); \
+ (p)->Endpoint = (ep); \
+}
+
+/* fast macro to recycle an RX packet that will be re-queued to HTC */
+#define HTC_PACKET_RESET_RX(p) \
+ { (p)->pBuffer = (p)->pBufferStart; (p)->ActualLength = 0; }
+
+/* macro to set packet parameters for TX */
+#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \
+{ \
+ (p)->pPktContext = (c); \
+ (p)->pBuffer = (b); \
+ (p)->ActualLength = (len); \
+ (p)->Endpoint = (ep); \
+ (p)->PktInfo.AsTx.Tag = (tag); \
+}
+
+/* HTC Packet Queueing Macros */
+typedef struct _HTC_PACKET_QUEUE {
+ DL_LIST QueueHead;
+ int Depth;
+} HTC_PACKET_QUEUE;
+
+/* initialize queue */
+#define INIT_HTC_PACKET_QUEUE(pQ) \
+{ \
+ DL_LIST_INIT(&(pQ)->QueueHead); \
+ (pQ)->Depth = 0; \
+}
+
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE(pQ,p) \
+{ DL_ListInsertTail(&(pQ)->QueueHead,&(p)->ListLink); \
+ (pQ)->Depth++; \
+}
+
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE_TO_HEAD(pQ,p) \
+{ DL_ListInsertHead(&(pQ)->QueueHead,&(p)->ListLink); \
+ (pQ)->Depth++; \
+}
+/* test if a queue is empty */
+#define HTC_QUEUE_EMPTY(pQ) ((pQ)->Depth == 0)
+/* get packet at head without removing it */
+static INLINE HTC_PACKET *HTC_GET_PKT_AT_HEAD(HTC_PACKET_QUEUE *queue) {
+ if (queue->Depth == 0) {
+ return NULL;
+ }
+ return A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(&queue->QueueHead)),HTC_PACKET,ListLink);
+}
+/* remove a packet from a queue, where-ever it is in the queue */
+#define HTC_PACKET_REMOVE(pQ,p) \
+{ \
+ DL_ListRemove(&(p)->ListLink); \
+ (pQ)->Depth--; \
+}
+
+/* dequeue an HTC packet from the head of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) {
+ DL_LIST *pItem = DL_ListRemoveItemFromHead(&queue->QueueHead);
+ if (pItem != NULL) {
+ queue->Depth--;
+ return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+ }
+ return NULL;
+}
+
+/* dequeue an HTC packet from the tail of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE_TAIL(HTC_PACKET_QUEUE *queue) {
+ DL_LIST *pItem = DL_ListRemoveItemFromTail(&queue->QueueHead);
+ if (pItem != NULL) {
+ queue->Depth--;
+ return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+ }
+ return NULL;
+}
+
+#define HTC_PACKET_QUEUE_DEPTH(pQ) (pQ)->Depth
+
+
+#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint
+#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag
+
+ /* transfer the packets from one queue to the tail of another queue */
+#define HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(pQDest,pQSrc) \
+{ \
+ DL_ListTransferItemsToTail(&(pQDest)->QueueHead,&(pQSrc)->QueueHead); \
+ (pQDest)->Depth += (pQSrc)->Depth; \
+ (pQSrc)->Depth = 0; \
+}
+
+ /* fast version to init and add a single packet to a queue */
+#define INIT_HTC_PACKET_QUEUE_AND_ADD(pQ,pP) \
+{ \
+ DL_LIST_INIT_AND_ADD(&(pQ)->QueueHead,&(pP)->ListLink) \
+ (pQ)->Depth = 1; \
+}
+
+#define HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQ, pPTemp) \
+ ITERATE_OVER_LIST_ALLOW_REMOVE(&(pQ)->QueueHead,(pPTemp), HTC_PACKET, ListLink)
+
+#define HTC_PACKET_QUEUE_ITERATE_END ITERATE_END
+
+#endif /*HTC_PACKET_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/htc_services.h b/drivers/net/wireless/ath6kl/include/htc_services.h
new file mode 100644
index 000000000000..4457d6634f26
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/htc_services.h
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+// <copyright file="htc_services.h" company="Atheros">
+// Copyright (c) 2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __HTC_SERVICES_H__
+#define __HTC_SERVICES_H__
+
+/* Current service IDs */
+
+typedef enum {
+ RSVD_SERVICE_GROUP = 0,
+ WMI_SERVICE_GROUP = 1,
+
+ HTC_TEST_GROUP = 254,
+ HTC_SERVICE_GROUP_LAST = 255
+}HTC_SERVICE_GROUP_IDS;
+
+#define MAKE_SERVICE_ID(group,index) \
+ (int)(((int)group << 8) | (int)(index))
+
+/* NOTE: service ID of 0x0000 is reserved and should never be used */
+#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
+#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
+#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
+#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
+#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
+#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
+#define WMI_MAX_SERVICES 5
+
+/* raw stream service (i.e. flash, tcmd, calibration apps) */
+#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
+
+#endif /*HTC_SERVICES_H_*/
diff --git a/drivers/net/wireless/ath6kl/include/ini_dset.h b/drivers/net/wireless/ath6kl/include/ini_dset.h
new file mode 100644
index 000000000000..fcd5a68fdac3
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/ini_dset.h
@@ -0,0 +1,80 @@
+//------------------------------------------------------------------------------
+// <copyright file="ini_dset.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _INI_DSET_H_
+#define _INI_DSET_H_
+
+/*
+ * Each of these represents a WHAL INI table, which consists
+ * of an "address column" followed by 1 or more "value columns".
+ *
+ * Software uses the base WHAL_INI_DATA_ID+column to access a
+ * DataSet that holds a particular column of data.
+ */
+typedef enum {
+#if defined(AR6002_REV4) || defined(AR6003)
+/* Add these definitions for compatability */
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
+ WHAL_INI_DATA_ID_NULL =0,
+ WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */
+ WHAL_INI_DATA_ID_COMMON =6, /* 7 */
+ WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */
+#ifdef FPGA
+ WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */
+ WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */
+ WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */
+ WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */
+ WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */
+ WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */
+ WHAL_INI_DATA_ID_ADDAC =25, /* 26 */
+#else
+ WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */
+ WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */
+ WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */
+ WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */
+ WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
+ WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
+#endif /* FPGA */
+#else
+ WHAL_INI_DATA_ID_NULL =0,
+ WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */
+ WHAL_INI_DATA_ID_COMMON =4, /* 5 */
+ WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */
+#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
+ WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */
+ WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */
+ WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */
+ WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */
+ WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */
+ WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */
+ WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
+ WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
+ WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */
+#endif
+ WHAL_INI_DATA_ID_MAX =31
+} WHAL_INI_DATA_ID;
+
+typedef PREPACK struct {
+ A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
+ A_UINT16 offset;
+ A_UINT32 newValue;
+} POSTPACK INI_DSET_REG_OVERRIDE;
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/pkt_log.h b/drivers/net/wireless/ath6kl/include/pkt_log.h
new file mode 100644
index 000000000000..1fcc1cb2750a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/pkt_log.h
@@ -0,0 +1,41 @@
+//------------------------------------------------------------------------------
+// Copyright (c) 2005 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __PKT_LOG_H__
+#define __PKT_LOG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Pkt log info */
+typedef PREPACK struct pkt_log_t {
+ struct info_t {
+ A_UINT16 st;
+ A_UINT16 end;
+ A_UINT16 cur;
+ }info[4096];
+ A_UINT16 last_idx;
+}POSTPACK PACKET_LOG;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __PKT_LOG_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/regdump.h b/drivers/net/wireless/ath6kl/include/regdump.h
new file mode 100644
index 000000000000..09755cd2874d
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/regdump.h
@@ -0,0 +1,45 @@
+//------------------------------------------------------------------------------
+// <copyright file="regdump.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __REGDUMP_H__
+#define __REGDUMP_H__
+#if defined(AR6001)
+#include "AR6001/AR6001_regdump.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/AR6002_regdump.h"
+#endif
+
+#if !defined(__ASSEMBLER__)
+/*
+ * Target CPU state at the time of failure is reflected
+ * in a register dump, which the Host can fetch through
+ * the diagnostic window.
+ */
+struct register_dump_s {
+ A_UINT32 target_id; /* Target ID */
+ A_UINT32 assline; /* Line number (if assertion failure) */
+ A_UINT32 pc; /* Program Counter at time of exception */
+ A_UINT32 badvaddr; /* Virtual address causing exception */
+ CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
+
+ /* Could copy top of stack here, too.... */
+};
+#endif /* __ASSEMBLER__ */
+#endif /* __REGDUMP_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/roaming.h b/drivers/net/wireless/ath6kl/include/roaming.h
new file mode 100644
index 000000000000..88c1bd278490
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/roaming.h
@@ -0,0 +1,37 @@
+//------------------------------------------------------------------------------
+// <copyright file="roaming.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef _ROAMING_H_
+#define _ROAMING_H_
+
+/*
+ * The signal quality could be in terms of either snr or rssi. We should
+ * have an enum for both of them. For the time being, we are going to move
+ * it to wmi.h that is shared by both host and the target, since we are
+ * repartitioning the code to the host
+ */
+#define SIGNAL_QUALITY_NOISE_FLOOR -96
+#define SIGNAL_QUALITY_METRICS_NUM_MAX 2
+typedef enum {
+ SIGNAL_QUALITY_METRICS_SNR = 0,
+ SIGNAL_QUALITY_METRICS_RSSI,
+ SIGNAL_QUALITY_METRICS_ALL,
+} SIGNAL_QUALITY_METRICS_TYPE;
+
+#endif /* _ROAMING_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/targaddrs.h b/drivers/net/wireless/ath6kl/include/targaddrs.h
new file mode 100644
index 000000000000..7b27ca2a78fe
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/targaddrs.h
@@ -0,0 +1,232 @@
+//------------------------------------------------------------------------------
+// <copyright file="targaddrs.h" company="Atheros">
+// Copyright (c) 2010 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __TARGADDRS_H__
+#define __TARGADDRS_H__
+#if defined(AR6001)
+#include "AR6001/addrs.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/addrs.h"
+#endif
+
+/*
+ * AR6K option bits, to enable/disable various features.
+ * By default, all option bits are 0.
+ * These bits can be set in LOCAL_SCRATCH register 0.
+ */
+#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
+#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
+#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
+#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
+#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
+#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
+#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
+#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
+
+/*
+ * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
+ * host_interest structure. It must match the address of the _host_interest
+ * symbol (see linker script).
+ *
+ * Host Interest is shared between Host and Target in order to coordinate
+ * between the two, and is intended to remain constant (with additions only
+ * at the end) across software releases.
+ *
+ * All addresses are available here so that it's possible to
+ * write a single binary that works with all Target Types.
+ * May be used in assembler code as well as C.
+ */
+#define AR6001_HOST_INTEREST_ADDRESS 0x80000600
+#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
+#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
+
+
+#define HOST_INTEREST_MAX_SIZE 0x100
+
+#if !defined(__ASSEMBLER__)
+struct register_dump_s;
+struct dbglog_hdr_s;
+
+/*
+ * These are items that the Host may need to access
+ * via BMI or via the Diagnostic Window. The position
+ * of items in this structure must remain constant
+ * across firmware revisions!
+ *
+ * Types for each item must be fixed size across
+ * target and host platforms.
+ *
+ * More items may be added at the end.
+ */
+struct host_interest_s {
+ /*
+ * Pointer to application-defined area, if any.
+ * Set by Target application during startup.
+ */
+ A_UINT32 hi_app_host_interest; /* 0x00 */
+
+ /* Pointer to register dump area, valid after Target crash. */
+ A_UINT32 hi_failure_state; /* 0x04 */
+
+ /* Pointer to debug logging header */
+ A_UINT32 hi_dbglog_hdr; /* 0x08 */
+
+ /* Indicates whether or not flash is present on Target.
+ * NB: flash_is_present indicator is here not just
+ * because it might be of interest to the Host; but
+ * also because it's set early on by Target's startup
+ * asm code and we need it to have a special RAM address
+ * so that it doesn't get reinitialized with the rest
+ * of data.
+ */
+ A_UINT32 hi_flash_is_present; /* 0x0c */
+
+ /*
+ * General-purpose flag bits, similar to AR6000_OPTION_* flags.
+ * Can be used by application rather than by OS.
+ */
+ A_UINT32 hi_option_flag; /* 0x10 */
+
+ /*
+ * Boolean that determines whether or not to
+ * display messages on the serial port.
+ */
+ A_UINT32 hi_serial_enable; /* 0x14 */
+
+ /* Start address of Flash DataSet index, if any */
+ A_UINT32 hi_dset_list_head; /* 0x18 */
+
+ /* Override Target application start address */
+ A_UINT32 hi_app_start; /* 0x1c */
+
+ /* Clock and voltage tuning */
+ A_UINT32 hi_skip_clock_init; /* 0x20 */
+ A_UINT32 hi_core_clock_setting; /* 0x24 */
+ A_UINT32 hi_cpu_clock_setting; /* 0x28 */
+ A_UINT32 hi_system_sleep_setting; /* 0x2c */
+ A_UINT32 hi_xtal_control_setting; /* 0x30 */
+ A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
+ A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
+ A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
+ A_UINT32 hi_clock_info; /* 0x40 */
+
+ /*
+ * Flash configuration overrides, used only
+ * when firmware is not executing from flash.
+ * (When using flash, modify the global variables
+ * with equivalent names.)
+ */
+ A_UINT32 hi_bank0_addr_value; /* 0x44 */
+ A_UINT32 hi_bank0_read_value; /* 0x48 */
+ A_UINT32 hi_bank0_write_value; /* 0x4c */
+ A_UINT32 hi_bank0_config_value; /* 0x50 */
+
+ /* Pointer to Board Data */
+ A_UINT32 hi_board_data; /* 0x54 */
+ A_UINT32 hi_board_data_initialized; /* 0x58 */
+
+ A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
+
+ A_UINT32 hi_desired_baud_rate; /* 0x60 */
+ A_UINT32 hi_dbglog_config; /* 0x64 */
+ A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
+ A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
+
+ A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
+ A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
+
+ A_UINT32 hi_refclk_hz; /* 0x78 */
+ A_UINT32 hi_ext_clk_detected; /* 0x7c */
+ A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
+ A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
+ A_UINT32 hi_hci_uart_baud; /* 0x88 */
+ A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
+ /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
+ A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
+ A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
+
+ A_UINT32 hi_allocram_start; /* 0x98 */
+ A_UINT32 hi_allocram_sz; /* 0x9c */
+ A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
+ A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
+ /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
+};
+
+/* Bits defined in hi_option_flag */
+#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
+#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
+#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
+#define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */
+#define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */
+#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
+#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
+#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
+
+/* 2 bits of hi_option_flag are used to represent 3 modes */
+#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
+#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
+#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
+
+/* Fw Mode Mask */
+#define HI_OPTION_FW_MODE_MASK 0x3
+#define HI_OPTION_FW_MODE_SHIFT 0x3
+
+/*
+ * Intended for use by Host software, this macro returns the Target RAM
+ * address of any item in the host_interest structure.
+ * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
+ */
+#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \
+ ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item)))
+
+#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
+ ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
+
+#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
+ ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
+
+#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
+ (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
+
+#define HOST_INTEREST_PROFILE_IS_ENABLED() \
+ (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
+
+/* Convert a Target virtual address into a Target physical address */
+#define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff)
+#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
+#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
+#define TARG_VTOP(TargetType, vaddr) \
+ (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \
+ (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr)))
+
+/* override REV2 ROM's app start address */
+#define AR6002_REV2_APP_START_OVERRIDE 0x911A00
+#define AR6003_REV1_APP_START_OVERRIDE 0x944c00
+#define AR6003_REV1_OTP_DATA_ADDRESS 0x542800
+#define AR6003_REV2_APP_START_OVERRIDE 0x945000
+#define AR6003_REV2_OTP_DATA_ADDRESS 0x543800
+
+
+/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
+#define AR6003_FETCH_TARG_REGS_COUNT 64
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __TARGADDRS_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/target_reg_table.h b/drivers/net/wireless/ath6kl/include/target_reg_table.h
new file mode 100644
index 000000000000..4105b9c418cf
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/target_reg_table.h
@@ -0,0 +1,236 @@
+//------------------------------------------------------------------------------
+// <copyright file="target_reg_table.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Target register table macros and structure definitions
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef TARGET_REG_TABLE_H_
+#define TARGET_REG_TABLE_H_
+
+#include "targaddrs.h"
+
+/*** WARNING : Add to the end of the TABLE! do not change the order ****/
+typedef struct targetdef_s {
+ A_UINT32 d_RTC_BASE_ADDRESS;
+ A_UINT32 d_SYSTEM_SLEEP_OFFSET;
+ A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB;
+ A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK;
+ A_UINT32 d_CLOCK_CONTROL_OFFSET;
+ A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK;
+ A_UINT32 d_RESET_CONTROL_OFFSET;
+ A_UINT32 d_RESET_CONTROL_SI0_RST_MASK;
+ A_UINT32 d_GPIO_BASE_ADDRESS;
+ A_UINT32 d_GPIO_PIN0_OFFSET;
+ A_UINT32 d_GPIO_PIN1_OFFSET;
+ A_UINT32 d_GPIO_PIN0_CONFIG_MASK;
+ A_UINT32 d_GPIO_PIN1_CONFIG_MASK;
+ A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
+ A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
+ A_UINT32 d_SI_CONFIG_I2C_LSB;
+ A_UINT32 d_SI_CONFIG_I2C_MASK;
+ A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB;
+ A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK;
+ A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB;
+ A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK;
+ A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB;
+ A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK;
+ A_UINT32 d_SI_CONFIG_DIVIDER_LSB;
+ A_UINT32 d_SI_CONFIG_DIVIDER_MASK;
+ A_UINT32 d_SI_BASE_ADDRESS;
+ A_UINT32 d_SI_CONFIG_OFFSET;
+ A_UINT32 d_SI_TX_DATA0_OFFSET;
+ A_UINT32 d_SI_TX_DATA1_OFFSET;
+ A_UINT32 d_SI_RX_DATA0_OFFSET;
+ A_UINT32 d_SI_RX_DATA1_OFFSET;
+ A_UINT32 d_SI_CS_OFFSET;
+ A_UINT32 d_SI_CS_DONE_ERR_MASK;
+ A_UINT32 d_SI_CS_DONE_INT_MASK;
+ A_UINT32 d_SI_CS_START_LSB;
+ A_UINT32 d_SI_CS_START_MASK;
+ A_UINT32 d_SI_CS_RX_CNT_LSB;
+ A_UINT32 d_SI_CS_RX_CNT_MASK;
+ A_UINT32 d_SI_CS_TX_CNT_LSB;
+ A_UINT32 d_SI_CS_TX_CNT_MASK;
+ A_UINT32 d_BOARD_DATA_SZ;
+} TARGET_REGISTER_TABLE;
+
+#define BOARD_DATA_SZ_MAX 2048
+
+#if defined(MY_TARGET_DEF) /* { */
+
+#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
+
+static struct targetdef_s my_target_def = {
+ RTC_BASE_ADDRESS,
+ SYSTEM_SLEEP_OFFSET,
+ SYSTEM_SLEEP_DISABLE_LSB,
+ SYSTEM_SLEEP_DISABLE_MASK,
+ CLOCK_CONTROL_OFFSET,
+ CLOCK_CONTROL_SI0_CLK_MASK,
+ RESET_CONTROL_OFFSET,
+ RESET_CONTROL_SI0_RST_MASK,
+ GPIO_BASE_ADDRESS,
+ GPIO_PIN0_OFFSET,
+ GPIO_PIN0_CONFIG_MASK,
+ GPIO_PIN1_OFFSET,
+ GPIO_PIN1_CONFIG_MASK,
+ SI_CONFIG_BIDIR_OD_DATA_LSB,
+ SI_CONFIG_BIDIR_OD_DATA_MASK,
+ SI_CONFIG_I2C_LSB,
+ SI_CONFIG_I2C_MASK,
+ SI_CONFIG_POS_SAMPLE_LSB,
+ SI_CONFIG_POS_SAMPLE_MASK,
+ SI_CONFIG_INACTIVE_CLK_LSB,
+ SI_CONFIG_INACTIVE_CLK_MASK,
+ SI_CONFIG_INACTIVE_DATA_LSB,
+ SI_CONFIG_INACTIVE_DATA_MASK,
+ SI_CONFIG_DIVIDER_LSB,
+ SI_CONFIG_DIVIDER_MASK,
+ SI_BASE_ADDRESS,
+ SI_CONFIG_OFFSET,
+ SI_TX_DATA0_OFFSET,
+ SI_TX_DATA1_OFFSET,
+ SI_RX_DATA0_OFFSET,
+ SI_RX_DATA1_OFFSET,
+ SI_CS_OFFSET,
+ SI_CS_DONE_ERR_MASK,
+ SI_CS_DONE_INT_MASK,
+ SI_CS_START_LSB,
+ SI_CS_START_MASK,
+ SI_CS_RX_CNT_LSB,
+ SI_CS_RX_CNT_MASK,
+ SI_CS_TX_CNT_LSB,
+ SI_CS_TX_CNT_MASK,
+ MY_TARGET_BOARD_DATA_SZ,
+};
+
+#else
+
+static struct targetdef_s my_target_def = {
+ .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
+ .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
+ .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
+ .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
+ .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
+ .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
+ .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
+ .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
+ .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
+ .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
+ .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
+ .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
+ .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
+ .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
+ .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
+ .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
+ .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
+ .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
+ .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
+ .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
+ .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
+ .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
+ .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
+ .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
+ .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
+ .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
+ .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
+ .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
+ .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
+ .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
+ .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
+ .d_SI_CS_OFFSET = SI_CS_OFFSET,
+ .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
+ .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
+ .d_SI_CS_START_LSB = SI_CS_START_LSB,
+ .d_SI_CS_START_MASK = SI_CS_START_MASK,
+ .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
+ .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
+ .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
+ .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
+ .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
+};
+
+#endif
+
+#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
+#error "BOARD_DATA_SZ_MAX is too small"
+#endif
+
+struct targetdef_s *MY_TARGET_DEF = &my_target_def;
+
+#else /* } { */
+
+#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
+#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
+#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
+#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
+#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
+#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
+#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
+#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
+#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
+#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
+#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
+#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
+#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
+#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
+#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
+#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
+#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
+#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
+#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
+#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
+#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
+#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
+#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
+#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
+
+/* SET macros */
+#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+
+#endif /* } */
+
+#endif /*TARGET_REG_TABLE_H_*/
+
+
diff --git a/drivers/net/wireless/ath6kl/include/testcmd.h b/drivers/net/wireless/ath6kl/include/testcmd.h
new file mode 100644
index 000000000000..49f2cf380296
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/testcmd.h
@@ -0,0 +1,179 @@
+//------------------------------------------------------------------------------
+// <copyright file="testcmd.h" company="Atheros">
+// Copyright (c) 2004-2005 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef TESTCMD_H_
+#define TESTCMD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef AR6002_REV2
+#define TCMD_MAX_RATES 12
+#else
+#define TCMD_MAX_RATES 28
+#endif
+
+typedef enum {
+ ZEROES_PATTERN = 0,
+ ONES_PATTERN,
+ REPEATING_10,
+ PN7_PATTERN,
+ PN9_PATTERN,
+ PN15_PATTERN
+}TX_DATA_PATTERN;
+
+/* Continous tx
+ mode : TCMD_CONT_TX_OFF - Disabling continous tx
+ TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
+ TCMD_CONT_TX_FRAME- Enable continuous modulated tx
+ freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
+dataRate: 0 - 1 Mbps
+ 1 - 2 Mbps
+ 2 - 5.5 Mbps
+ 3 - 11 Mbps
+ 4 - 6 Mbps
+ 5 - 9 Mbps
+ 6 - 12 Mbps
+ 7 - 18 Mbps
+ 8 - 24 Mbps
+ 9 - 36 Mbps
+ 10 - 28 Mbps
+ 11 - 54 Mbps
+ txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
+antenna: 1 - one antenna
+ 2 - two antenna
+Note : Enable/disable continuous tx test cmd works only when target is awake.
+*/
+
+typedef enum {
+ TCMD_CONT_TX_OFF = 0,
+ TCMD_CONT_TX_SINE,
+ TCMD_CONT_TX_FRAME,
+ TCMD_CONT_TX_TX99,
+ TCMD_CONT_TX_TX100
+} TCMD_CONT_TX_MODE;
+
+typedef enum {
+ TCMD_WLAN_MODE_HT20 = 0,
+ TCMD_WLAN_MODE_HT40PLUS = 1,
+ TCMD_WLAN_MODE_HT40MINUS = 2,
+} TCMD_WLAN_MODE;
+
+typedef PREPACK struct {
+ A_UINT32 testCmdId;
+ A_UINT32 mode;
+ A_UINT32 freq;
+ A_UINT32 dataRate;
+ A_INT32 txPwr;
+ A_UINT32 antenna;
+ A_UINT32 enANI;
+ A_UINT32 scramblerOff;
+ A_UINT32 aifsn;
+ A_UINT16 pktSz;
+ A_UINT16 txPattern;
+ A_UINT32 shortGuard;
+ A_UINT32 numPackets;
+ A_UINT32 wlanMode;
+} POSTPACK TCMD_CONT_TX;
+
+#define TCMD_TXPATTERN_ZERONE 0x1
+#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2
+
+/* Continuous Rx
+ act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
+ TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
+ address equal specified
+ mac address (set via act =3)
+ TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the
+ report from the last cont
+ Rx test)
+
+ TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
+ target. This Overrides
+ the default MAC address.)
+
+*/
+typedef enum {
+ TCMD_CONT_RX_PROMIS =0,
+ TCMD_CONT_RX_FILTER,
+ TCMD_CONT_RX_REPORT,
+ TCMD_CONT_RX_SETMAC,
+ TCMD_CONT_RX_SET_ANT_SWITCH_TABLE
+} TCMD_CONT_RX_ACT;
+
+typedef PREPACK struct {
+ A_UINT32 testCmdId;
+ A_UINT32 act;
+ A_UINT32 enANI;
+ PREPACK union {
+ struct PREPACK TCMD_CONT_RX_PARA {
+ A_UINT32 freq;
+ A_UINT32 antenna;
+ A_UINT32 wlanMode;
+ } POSTPACK para;
+ struct PREPACK TCMD_CONT_RX_REPORT {
+ A_UINT32 totalPkt;
+ A_INT32 rssiInDBm;
+ A_UINT32 crcErrPkt;
+ A_UINT32 secErrPkt;
+ A_UINT16 rateCnt[TCMD_MAX_RATES];
+ A_UINT16 rateCntShortGuard[TCMD_MAX_RATES];
+ } POSTPACK report;
+ struct PREPACK TCMD_CONT_RX_MAC {
+ A_UCHAR addr[ATH_MAC_LEN];
+ } POSTPACK mac;
+ struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
+ A_UINT32 antswitch1;
+ A_UINT32 antswitch2;
+ }POSTPACK antswitchtable;
+ } POSTPACK u;
+} POSTPACK TCMD_CONT_RX;
+
+/* Force sleep/wake test cmd
+ mode: TCMD_PM_WAKEUP - Wakeup the target
+ TCMD_PM_SLEEP - Force the target to sleep.
+ */
+typedef enum {
+ TCMD_PM_WAKEUP = 1, /* be consistent with target */
+ TCMD_PM_SLEEP
+} TCMD_PM_MODE;
+
+typedef PREPACK struct {
+ A_UINT32 testCmdId;
+ A_UINT32 mode;
+} POSTPACK TCMD_PM;
+
+typedef enum {
+ TCMD_CONT_TX_ID,
+ TCMD_CONT_RX_ID,
+ TCMD_PM_ID
+} TCMD_ID;
+
+typedef PREPACK union {
+ TCMD_CONT_TX contTx;
+ TCMD_CONT_RX contRx;
+ TCMD_PM pm;
+} POSTPACK TEST_CMD;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TESTCMD_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wlan_api.h b/drivers/net/wireless/ath6kl/include/wlan_api.h
new file mode 100644
index 000000000000..aa17b3e1de12
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wlan_api.h
@@ -0,0 +1,122 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_api.h" company="Atheros">
+// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the API for the host wlan module
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_WLAN_API_H_
+#define _HOST_WLAN_API_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <a_osapi.h>
+
+struct ieee80211_node_table;
+struct ieee80211_frame;
+
+struct ieee80211_common_ie {
+ A_UINT16 ie_chan;
+ A_UINT8 *ie_tstamp;
+ A_UINT8 *ie_ssid;
+ A_UINT8 *ie_rates;
+ A_UINT8 *ie_xrates;
+ A_UINT8 *ie_country;
+ A_UINT8 *ie_wpa;
+ A_UINT8 *ie_rsn;
+ A_UINT8 *ie_wmm;
+ A_UINT8 *ie_ath;
+ A_UINT16 ie_capInfo;
+ A_UINT16 ie_beaconInt;
+ A_UINT8 *ie_tim;
+ A_UINT8 *ie_chswitch;
+ A_UINT8 ie_erp;
+ A_UINT8 *ie_wsc;
+ A_UINT8 *ie_htcap;
+ A_UINT8 *ie_htop;
+#ifdef WAPI_ENABLE
+ A_UINT8 *ie_wapi;
+#endif
+};
+
+typedef struct bss {
+ A_UINT8 ni_macaddr[6];
+ A_UINT8 ni_snr;
+ A_INT16 ni_rssi;
+ struct bss *ni_list_next;
+ struct bss *ni_list_prev;
+ struct bss *ni_hash_next;
+ struct bss *ni_hash_prev;
+ struct ieee80211_common_ie ni_cie;
+ A_UINT8 *ni_buf;
+ A_UINT16 ni_framelen;
+ struct ieee80211_node_table *ni_table;
+ A_UINT32 ni_refcnt;
+ int ni_scangen;
+
+ A_UINT32 ni_tstamp;
+#ifdef OS_ROAM_MANAGEMENT
+ A_UINT32 ni_si_gen;
+#endif
+} bss_t;
+
+typedef void wlan_node_iter_func(void *arg, bss_t *);
+
+bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
+void wlan_node_free(bss_t *ni);
+void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+ const A_UINT8 *macaddr);
+bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
+void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
+void wlan_free_allnodes(struct ieee80211_node_table *nt);
+void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+ void *arg);
+
+void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
+void wlan_node_table_reset(struct ieee80211_node_table *nt);
+void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
+
+A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
+ struct ieee80211_common_ie *cie);
+
+A_UINT16 wlan_ieee2freq(int chan);
+A_UINT32 wlan_freq2ieee(A_UINT16 freq);
+
+void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge);
+
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID);
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
+
+bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid);
+
+bss_t *
+wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
+ A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_WLAN_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wlan_defs.h b/drivers/net/wireless/ath6kl/include/wlan_defs.h
new file mode 100644
index 000000000000..1fe4b113a427
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wlan_defs.h
@@ -0,0 +1,75 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_defs.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef __WLAN_DEFS_H__
+#define __WLAN_DEFS_H__
+
+/*
+ * This file contains WLAN definitions that may be used across both
+ * Host and Target software.
+ */
+
+typedef enum {
+ MODE_11A = 0, /* 11a Mode */
+ MODE_11G = 1, /* 11b/g Mode */
+ MODE_11B = 2, /* 11b Mode */
+ MODE_11GONLY = 3, /* 11g only Mode */
+#ifdef SUPPORT_11N
+ MODE_11NA_HT20 = 4, /* 11a HT20 mode */
+ MODE_11NG_HT20 = 5, /* 11g HT20 mode */
+ MODE_11NA_HT40 = 6, /* 11a HT40 mode */
+ MODE_11NG_HT40 = 7, /* 11g HT40 mode */
+ MODE_UNKNOWN = 8,
+ MODE_MAX = 8
+#else
+ MODE_UNKNOWN = 4,
+ MODE_MAX = 4
+#endif
+} WLAN_PHY_MODE;
+
+typedef enum {
+ WLAN_11A_CAPABILITY = 1,
+ WLAN_11G_CAPABILITY = 2,
+ WLAN_11AG_CAPABILITY = 3,
+}WLAN_CAPABILITY;
+
+#ifdef SUPPORT_11N
+typedef unsigned long A_RATEMASK;
+#else
+typedef unsigned short A_RATEMASK;
+#endif
+
+#ifdef SUPPORT_11N
+#define IS_MODE_11A(mode) (((mode) == MODE_11A) || \
+ ((mode) == MODE_11NA_HT20) || \
+ ((mode) == MODE_11NA_HT40))
+#define IS_MODE_11B(mode) ((mode) == MODE_11B)
+#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
+ ((mode) == MODE_11GONLY) || \
+ ((mode) == MODE_11NG_HT20) || \
+ ((mode) == MODE_11NG_HT40))
+#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
+#else
+#define IS_MODE_11A(mode) ((mode) == MODE_11A)
+#define IS_MODE_11B(mode) ((mode) == MODE_11B)
+#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
+ ((mode) == MODE_11GONLY))
+#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
+#endif /* SUPPORT_11N */
+
+#endif /* __WLANDEFS_H__ */
diff --git a/drivers/net/wireless/ath6kl/include/wlan_dset.h b/drivers/net/wireless/ath6kl/include/wlan_dset.h
new file mode 100644
index 000000000000..e5f9b2480c15
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wlan_dset.h
@@ -0,0 +1,30 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_dset.h" company="Atheros">
+// Copyright (c) 2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifndef __WLAN_DSET_H__
+#define __WLAN_DSET_H__
+
+typedef PREPACK struct wow_config_dset {
+
+ A_UINT8 valid_dset;
+ A_UINT8 gpio_enable;
+ A_UINT16 gpio_pin;
+} POSTPACK WOW_CONFIG_DSET;
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/include/wmi.h b/drivers/net/wireless/ath6kl/include/wmi.h
new file mode 100644
index 000000000000..7b140d8118b4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmi.h
@@ -0,0 +1,3053 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI). It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to commands
+ * belongs to the host driver and the WMI is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_H_
+#define _WMI_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "wmix.h"
+#include "wlan_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HTC_PROTOCOL_VERSION 0x0002
+#define HTC_PROTOCOL_REVISION 0x0000
+
+#define WMI_PROTOCOL_VERSION 0x0002
+#define WMI_PROTOCOL_REVISION 0x0000
+
+#define ATH_MAC_LEN 6 /* length of mac in bytes */
+#define WMI_CMD_MAX_LEN 100
+#define WMI_CONTROL_MSG_MAX_LEN 256
+#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
+#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
+#define RFC1042OUI {0x00, 0x00, 0x00}
+
+#define IP_ETHERTYPE 0x0800
+
+#define WMI_IMPLICIT_PSTREAM 0xFF
+#define WMI_MAX_THINSTREAM 15
+
+#ifdef AR6002_REV2
+#define IBSS_MAX_NUM_STA 4
+#else
+#define IBSS_MAX_NUM_STA 8
+#endif
+
+struct host_app_area_s {
+ A_UINT32 wmi_protocol_ver;
+};
+
+/*
+ * Data Path
+ */
+typedef PREPACK struct {
+ A_UINT8 dstMac[ATH_MAC_LEN];
+ A_UINT8 srcMac[ATH_MAC_LEN];
+ A_UINT16 typeOrLen;
+} POSTPACK ATH_MAC_HDR;
+
+typedef PREPACK struct {
+ A_UINT8 dsap;
+ A_UINT8 ssap;
+ A_UINT8 cntl;
+ A_UINT8 orgCode[3];
+ A_UINT16 etherType;
+} POSTPACK ATH_LLC_SNAP_HDR;
+
+typedef enum {
+ DATA_MSGTYPE = 0x0,
+ CNTL_MSGTYPE,
+ SYNC_MSGTYPE,
+ OPT_MSGTYPE,
+} WMI_MSG_TYPE;
+
+
+/*
+ * Macros for operating on WMI_DATA_HDR (info) field
+ */
+
+#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03
+#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
+#define WMI_DATA_HDR_UP_MASK 0x07
+#define WMI_DATA_HDR_UP_SHIFT 2
+/* In AP mode, the same bit (b5) is used to indicate Power save state in
+ * the Rx dir and More data bit state in the tx direction.
+ */
+#define WMI_DATA_HDR_PS_MASK 0x1
+#define WMI_DATA_HDR_PS_SHIFT 5
+
+#define WMI_DATA_HDR_MORE_MASK 0x1
+#define WMI_DATA_HDR_MORE_SHIFT 5
+
+typedef enum {
+ WMI_DATA_HDR_DATA_TYPE_802_3 = 0,
+ WMI_DATA_HDR_DATA_TYPE_802_11,
+ WMI_DATA_HDR_DATA_TYPE_ACL,
+} WMI_DATA_HDR_DATA_TYPE;
+
+#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3
+#define WMI_DATA_HDR_DATA_TYPE_SHIFT 6
+
+#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT))
+
+#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
+#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT))
+#define WMI_DATA_HDR_GET_UP(h) (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK)
+#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT))
+
+#define WMI_DATA_HDR_GET_DATA_TYPE(h) (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK)
+#define WMI_DATA_HDR_SET_DATA_TYPE(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT))
+
+#define WMI_DATA_HDR_GET_DOT11(h) (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11)
+#define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p))
+
+/* Macros for operating on WMI_DATA_HDR (info2) field */
+#define WMI_DATA_HDR_SEQNO_MASK 0xFFF
+#define WMI_DATA_HDR_SEQNO_SHIFT 0
+
+#define WMI_DATA_HDR_AMSDU_MASK 0x1
+#define WMI_DATA_HDR_AMSDU_SHIFT 12
+
+#define WMI_DATA_HDR_META_MASK 0x7
+#define WMI_DATA_HDR_META_SHIFT 13
+
+#define GET_SEQ_NO(_v) ((_v) & WMI_DATA_HDR_SEQNO_MASK)
+#define GET_ISMSDU(_v) ((_v) & WMI_DATA_HDR_AMSDU_MASK)
+
+#define WMI_DATA_HDR_GET_SEQNO(h) GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT)
+#define WMI_DATA_HDR_SET_SEQNO(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT))
+
+#define WMI_DATA_HDR_IS_AMSDU(h) GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT)
+#define WMI_DATA_HDR_SET_AMSDU(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT))
+
+#define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK)
+#define WMI_DATA_HDR_SET_META(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT))
+
+typedef PREPACK struct {
+ A_INT8 rssi;
+ A_UINT8 info; /* usage of 'info' field(8-bit):
+ * b1:b0 - WMI_MSG_TYPE
+ * b4:b3:b2 - UP(tid)
+ * b5 - Used in AP mode. More-data in tx dir, PS in rx.
+ * b7:b6 - Dot3 header(0),
+ * Dot11 Header(1),
+ * ACL data(2)
+ */
+
+ A_UINT16 info2; /* usage of 'info2' field(16-bit):
+ * b11:b0 - seq_no
+ * b12 - A-MSDU?
+ * b15:b13 - META_DATA_VERSION 0 - 7
+ */
+ A_UINT16 reserved;
+} POSTPACK WMI_DATA_HDR;
+
+/*
+ * TX META VERSION DEFINITIONS
+ */
+#define WMI_MAX_TX_META_SZ (12)
+#define WMI_MAX_TX_META_VERSION (7)
+#define WMI_META_VERSION_1 (0x01)
+#define WMI_META_VERSION_2 (0X02)
+
+#define WMI_ACL_TO_DOT11_HEADROOM 36
+
+#if 0 /* removed to prevent compile errors for WM.. */
+typedef PREPACK struct {
+/* intentionally empty. Default version is no meta data. */
+} POSTPACK WMI_TX_META_V0;
+#endif
+
+typedef PREPACK struct {
+ A_UINT8 pktID; /* The packet ID to identify the tx request */
+ A_UINT8 ratePolicyID; /* The rate policy to be used for the tx of this frame */
+} POSTPACK WMI_TX_META_V1;
+
+
+#define WMI_CSUM_DIR_TX (0x1)
+#define TX_CSUM_CALC_FILL (0x1)
+typedef PREPACK struct {
+ A_UINT8 csumStart; /*Offset from start of the WMI header for csum calculation to begin */
+ A_UINT8 csumDest; /*Offset from start of WMI header where final csum goes*/
+ A_UINT8 csumFlags; /*number of bytes over which csum is calculated*/
+} POSTPACK WMI_TX_META_V2;
+
+
+/*
+ * RX META VERSION DEFINITIONS
+ */
+/* if RX meta data is present at all then the meta data field
+ * will consume WMI_MAX_RX_META_SZ bytes of space between the
+ * WMI_DATA_HDR and the payload. How much of the available
+ * Meta data is actually used depends on which meta data
+ * version is active. */
+#define WMI_MAX_RX_META_SZ (12)
+#define WMI_MAX_RX_META_VERSION (7)
+
+#define WMI_RX_STATUS_OK 0 /* success */
+#define WMI_RX_STATUS_DECRYPT_ERR 1 /* decrypt error */
+#define WMI_RX_STATUS_MIC_ERR 2 /* tkip MIC error */
+#define WMI_RX_STATUS_ERR 3 /* undefined error */
+
+#define WMI_RX_FLAGS_AGGR 0x0001 /* part of AGGR */
+#define WMI_RX_FlAGS_STBC 0x0002 /* used STBC */
+#define WMI_RX_FLAGS_SGI 0x0004 /* used SGI */
+#define WMI_RX_FLAGS_HT 0x0008 /* is HT packet */
+/* the flags field is also used to store the CRYPTO_TYPE of the frame
+ * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */
+#define WMI_RX_FLAGS_CRYPTO_SHIFT 4
+#define WMI_RX_FLAGS_CRYPTO_MASK 0x1f
+#define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK)
+
+#if 0 /* removed to prevent compile errors for WM.. */
+typedef PREPACK struct {
+/* intentionally empty. Default version is no meta data. */
+} POSTPACK WMI_RX_META_VERSION_0;
+#endif
+
+typedef PREPACK struct {
+ A_UINT8 status; /* one of WMI_RX_STATUS_... */
+ A_UINT8 rix; /* rate index mapped to rate at which this packet was received. */
+ A_UINT8 rssi; /* rssi of packet */
+ A_UINT8 channel;/* rf channel during packet reception */
+ A_UINT16 flags; /* a combination of WMI_RX_FLAGS_... */
+} POSTPACK WMI_RX_META_V1;
+
+#define RX_CSUM_VALID_FLAG (0x1)
+typedef PREPACK struct {
+ A_UINT16 csum;
+ A_UINT8 csumFlags;/* bit 0 set -partial csum valid
+ bit 1 set -test mode */
+} POSTPACK WMI_RX_META_V2;
+
+
+
+#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF)
+
+/*
+ * Control Path
+ */
+typedef PREPACK struct {
+ A_UINT16 commandId;
+/*
+ * info1 - 16 bits
+ * b03:b00 - id
+ * b15:b04 - unused
+ */
+ A_UINT16 info1;
+
+ A_UINT16 reserved; /* For alignment */
+} POSTPACK WMI_CMD_HDR; /* used for commands and events */
+
+/*
+ * List of Commnands
+ */
+typedef enum {
+ WMI_CONNECT_CMDID = 0x0001,
+ WMI_RECONNECT_CMDID,
+ WMI_DISCONNECT_CMDID,
+ WMI_SYNCHRONIZE_CMDID,
+ WMI_CREATE_PSTREAM_CMDID,
+ WMI_DELETE_PSTREAM_CMDID,
+ WMI_START_SCAN_CMDID,
+ WMI_SET_SCAN_PARAMS_CMDID,
+ WMI_SET_BSS_FILTER_CMDID,
+ WMI_SET_PROBED_SSID_CMDID, /* 10 */
+ WMI_SET_LISTEN_INT_CMDID,
+ WMI_SET_BMISS_TIME_CMDID,
+ WMI_SET_DISC_TIMEOUT_CMDID,
+ WMI_GET_CHANNEL_LIST_CMDID,
+ WMI_SET_BEACON_INT_CMDID,
+ WMI_GET_STATISTICS_CMDID,
+ WMI_SET_CHANNEL_PARAMS_CMDID,
+ WMI_SET_POWER_MODE_CMDID,
+ WMI_SET_IBSS_PM_CAPS_CMDID,
+ WMI_SET_POWER_PARAMS_CMDID, /* 20 */
+ WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+ WMI_ADD_CIPHER_KEY_CMDID,
+ WMI_DELETE_CIPHER_KEY_CMDID,
+ WMI_ADD_KRK_CMDID,
+ WMI_DELETE_KRK_CMDID,
+ WMI_SET_PMKID_CMDID,
+ WMI_SET_TX_PWR_CMDID,
+ WMI_GET_TX_PWR_CMDID,
+ WMI_SET_ASSOC_INFO_CMDID,
+ WMI_ADD_BAD_AP_CMDID, /* 30 */
+ WMI_DELETE_BAD_AP_CMDID,
+ WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+ WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+ WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+ WMI_SET_ACCESS_PARAMS_CMDID,
+ WMI_SET_RETRY_LIMITS_CMDID,
+ WMI_SET_OPT_MODE_CMDID,
+ WMI_OPT_TX_FRAME_CMDID,
+ WMI_SET_VOICE_PKT_SIZE_CMDID,
+ WMI_SET_MAX_SP_LEN_CMDID, /* 40 */
+ WMI_SET_ROAM_CTRL_CMDID,
+ WMI_GET_ROAM_TBL_CMDID,
+ WMI_GET_ROAM_DATA_CMDID,
+ WMI_ENABLE_RM_CMDID,
+ WMI_SET_MAX_OFFHOME_DURATION_CMDID,
+ WMI_EXTENSION_CMDID, /* Non-wireless extensions */
+ WMI_SNR_THRESHOLD_PARAMS_CMDID,
+ WMI_LQ_THRESHOLD_PARAMS_CMDID,
+ WMI_SET_LPREAMBLE_CMDID,
+ WMI_SET_RTS_CMDID, /* 50 */
+ WMI_CLR_RSSI_SNR_CMDID,
+ WMI_SET_FIXRATES_CMDID,
+ WMI_GET_FIXRATES_CMDID,
+ WMI_SET_AUTH_MODE_CMDID,
+ WMI_SET_REASSOC_MODE_CMDID,
+ WMI_SET_WMM_CMDID,
+ WMI_SET_WMM_TXOP_CMDID,
+ WMI_TEST_CMDID,
+ /* COEX AR6002 only*/
+ WMI_SET_BT_STATUS_CMDID,
+ WMI_SET_BT_PARAMS_CMDID, /* 60 */
+
+ WMI_SET_KEEPALIVE_CMDID,
+ WMI_GET_KEEPALIVE_CMDID,
+ WMI_SET_APPIE_CMDID,
+ WMI_GET_APPIE_CMDID,
+ WMI_SET_WSC_STATUS_CMDID,
+
+ /* Wake on Wireless */
+ WMI_SET_HOST_SLEEP_MODE_CMDID,
+ WMI_SET_WOW_MODE_CMDID,
+ WMI_GET_WOW_LIST_CMDID,
+ WMI_ADD_WOW_PATTERN_CMDID,
+ WMI_DEL_WOW_PATTERN_CMDID, /* 70 */
+
+ WMI_SET_FRAMERATES_CMDID,
+ WMI_SET_AP_PS_CMDID,
+ WMI_SET_QOS_SUPP_CMDID,
+ /* WMI_THIN_RESERVED_... mark the start and end
+ * values for WMI_THIN_RESERVED command IDs. These
+ * command IDs can be found in wmi_thin.h */
+ WMI_THIN_RESERVED_START = 0x8000,
+ WMI_THIN_RESERVED_END = 0x8fff,
+ /*
+ * Developer commands starts at 0xF000
+ */
+ WMI_SET_BITRATE_CMDID = 0xF000,
+ WMI_GET_BITRATE_CMDID,
+ WMI_SET_WHALPARAM_CMDID,
+
+
+ /*Should add the new command to the tail for compatible with
+ * etna.
+ */
+ WMI_SET_MAC_ADDRESS_CMDID,
+ WMI_SET_AKMP_PARAMS_CMDID,
+ WMI_SET_PMKID_LIST_CMDID,
+ WMI_GET_PMKID_LIST_CMDID,
+ WMI_ABORT_SCAN_CMDID,
+ WMI_SET_TARGET_EVENT_REPORT_CMDID,
+
+ // Unused
+ WMI_UNUSED1,
+ WMI_UNUSED2,
+
+ /*
+ * AP mode commands
+ */
+ WMI_AP_HIDDEN_SSID_CMDID,
+ WMI_AP_SET_NUM_STA_CMDID,
+ WMI_AP_ACL_POLICY_CMDID,
+ WMI_AP_ACL_MAC_LIST_CMDID,
+ WMI_AP_CONFIG_COMMIT_CMDID,
+ WMI_AP_SET_MLME_CMDID,
+ WMI_AP_SET_PVB_CMDID,
+ WMI_AP_CONN_INACT_CMDID,
+ WMI_AP_PROT_SCAN_TIME_CMDID,
+ WMI_AP_SET_COUNTRY_CMDID,
+ WMI_AP_SET_DTIM_CMDID,
+ WMI_AP_MODE_STAT_CMDID,
+
+ WMI_SET_IP_CMDID,
+ WMI_SET_PARAMS_CMDID,
+ WMI_SET_MCAST_FILTER_CMDID,
+ WMI_DEL_MCAST_FILTER_CMDID,
+
+ WMI_ALLOW_AGGR_CMDID,
+ WMI_ADDBA_REQ_CMDID,
+ WMI_DELBA_REQ_CMDID,
+ WMI_SET_HT_CAP_CMDID,
+ WMI_SET_HT_OP_CMDID,
+ WMI_SET_TX_SELECT_RATES_CMDID,
+ WMI_SET_TX_SGI_PARAM_CMDID,
+ WMI_SET_RATE_POLICY_CMDID,
+
+ WMI_HCI_CMD_CMDID,
+ WMI_RX_FRAME_FORMAT_CMDID,
+ WMI_SET_THIN_MODE_CMDID,
+ WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID,
+
+ WMI_AP_SET_11BG_RATESET_CMDID,
+ WMI_SET_PMK_CMDID,
+ WMI_MCAST_FILTER_CMDID,
+ /* COEX CMDID AR6003*/
+ WMI_SET_BTCOEX_FE_ANT_CMDID,
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID,
+ WMI_SET_BTCOEX_SCO_CONFIG_CMDID,
+ WMI_SET_BTCOEX_A2DP_CONFIG_CMDID,
+ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID,
+ WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID,
+ WMI_SET_BTCOEX_DEBUG_CMDID,
+ WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID,
+ WMI_GET_BTCOEX_STATS_CMDID,
+ WMI_GET_BTCOEX_CONFIG_CMDID
+} WMI_COMMAND_ID;
+
+/*
+ * Frame Types
+ */
+typedef enum {
+ WMI_FRAME_BEACON = 0,
+ WMI_FRAME_PROBE_REQ,
+ WMI_FRAME_PROBE_RESP,
+ WMI_FRAME_ASSOC_REQ,
+ WMI_FRAME_ASSOC_RESP,
+ WMI_NUM_MGMT_FRAME
+} WMI_MGMT_FRAME_TYPE;
+
+/*
+ * Connect Command
+ */
+typedef enum {
+ INFRA_NETWORK = 0x01,
+ ADHOC_NETWORK = 0x02,
+ ADHOC_CREATOR = 0x04,
+ AP_NETWORK = 0x10,
+} NETWORK_TYPE;
+
+typedef enum {
+ OPEN_AUTH = 0x01,
+ SHARED_AUTH = 0x02,
+ LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */
+} DOT11_AUTH_MODE;
+
+typedef enum {
+ NONE_AUTH = 0x01,
+ WPA_AUTH = 0x02,
+ WPA2_AUTH = 0x04,
+ WPA_PSK_AUTH = 0x08,
+ WPA2_PSK_AUTH = 0x10,
+ WPA_AUTH_CCKM = 0x20,
+ WPA2_AUTH_CCKM = 0x40,
+} AUTH_MODE;
+
+typedef enum {
+ NONE_CRYPT = 0x01,
+ WEP_CRYPT = 0x02,
+ TKIP_CRYPT = 0x04,
+ AES_CRYPT = 0x08,
+#ifdef WAPI_ENABLE
+ WAPI_CRYPT = 0x10,
+#endif /*WAPI_ENABLE*/
+} CRYPTO_TYPE;
+
+#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
+#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
+
+#ifdef WAPI_ENABLE
+#undef WMI_MAX_CRYPTO_TYPE
+#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1)
+#endif /* WAPI_ENABLE */
+
+#ifdef WAPI_ENABLE
+#define IW_ENCODE_ALG_SM4 0x20
+#define IW_AUTH_WAPI_ENABLED 0x20
+#endif
+
+#define WMI_MIN_KEY_INDEX 0
+#define WMI_MAX_KEY_INDEX 3
+
+#ifdef WAPI_ENABLE
+#undef WMI_MAX_KEY_INDEX
+#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */
+#endif /* WAPI_ENABLE */
+
+#define WMI_MAX_KEY_LEN 32
+
+#define WMI_MAX_SSID_LEN 32
+
+typedef enum {
+ CONNECT_ASSOC_POLICY_USER = 0x0001,
+ CONNECT_SEND_REASSOC = 0x0002,
+ CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
+ CONNECT_PROFILE_MATCH_DONE = 0x0008,
+ CONNECT_IGNORE_AAC_BEACON = 0x0010,
+ CONNECT_CSA_FOLLOW_BSS = 0x0020,
+ CONNECT_DO_WPA_OFFLOAD = 0x0040,
+ CONNECT_DO_NOT_DEAUTH = 0x0080,
+} WMI_CONNECT_CTRL_FLAGS_BITS;
+
+#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS)
+
+typedef PREPACK struct {
+ A_UINT8 networkType;
+ A_UINT8 dot11AuthMode;
+ A_UINT8 authMode;
+ A_UINT8 pairwiseCryptoType;
+ A_UINT8 pairwiseCryptoLen;
+ A_UINT8 groupCryptoType;
+ A_UINT8 groupCryptoLen;
+ A_UINT8 ssidLength;
+ A_UCHAR ssid[WMI_MAX_SSID_LEN];
+ A_UINT16 channel;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT32 ctrl_flags;
+} POSTPACK WMI_CONNECT_CMD;
+
+/*
+ * WMI_RECONNECT_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT16 channel; /* hint */
+ A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */
+} POSTPACK WMI_RECONNECT_CMD;
+
+#define WMI_PMK_LEN 32
+typedef PREPACK struct {
+ A_UINT8 pmk[WMI_PMK_LEN];
+} POSTPACK WMI_SET_PMK_CMD;
+
+/*
+ * WMI_ADD_CIPHER_KEY_CMDID
+ */
+typedef enum {
+ PAIRWISE_USAGE = 0x00,
+ GROUP_USAGE = 0x01,
+ TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
+} KEY_USAGE;
+
+/*
+ * Bit Flag
+ * Bit 0 - Initialise TSC - default is Initialize
+ */
+#define KEY_OP_INIT_TSC 0x01
+#define KEY_OP_INIT_RSC 0x02
+#ifdef WAPI_ENABLE
+#define KEY_OP_INIT_WAPIPN 0x10
+#endif /* WAPI_ENABLE */
+
+#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */
+#define KEY_OP_VALID_MASK 0x03
+
+typedef PREPACK struct {
+ A_UINT8 keyIndex;
+ A_UINT8 keyType;
+ A_UINT8 keyUsage; /* KEY_USAGE */
+ A_UINT8 keyLength;
+ A_UINT8 keyRSC[8]; /* key replay sequence counter */
+ A_UINT8 key[WMI_MAX_KEY_LEN];
+ A_UINT8 key_op_ctrl; /* Additional Key Control information */
+ A_UINT8 key_macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_CIPHER_KEY_CMD;
+
+/*
+ * WMI_DELETE_CIPHER_KEY_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 keyIndex;
+} POSTPACK WMI_DELETE_CIPHER_KEY_CMD;
+
+#define WMI_KRK_LEN 16
+/*
+ * WMI_ADD_KRK_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 krk[WMI_KRK_LEN];
+} POSTPACK WMI_ADD_KRK_CMD;
+
+/*
+ * WMI_SET_TKIP_COUNTERMEASURES_CMDID
+ */
+typedef enum {
+ WMI_TKIP_CM_DISABLE = 0x0,
+ WMI_TKIP_CM_ENABLE = 0x1,
+} WMI_TKIP_CM_CONTROL;
+
+typedef PREPACK struct {
+ A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */
+} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
+
+/*
+ * WMI_SET_PMKID_CMDID
+ */
+
+#define WMI_PMKID_LEN 16
+
+typedef enum {
+ PMKID_DISABLE = 0,
+ PMKID_ENABLE = 1,
+} PMKID_ENABLE_FLG;
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 enable; /* PMKID_ENABLE_FLG */
+ A_UINT8 pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_SET_PMKID_CMD;
+
+/*
+ * WMI_START_SCAN_CMD
+ */
+typedef enum {
+ WMI_LONG_SCAN = 0,
+ WMI_SHORT_SCAN = 1,
+} WMI_SCAN_TYPE;
+
+typedef PREPACK struct {
+ A_BOOL forceFgScan;
+ A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */
+ A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */
+ A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/
+ A_UINT8 scanType; /* WMI_SCAN_TYPE */
+ A_UINT8 numChannels; /* how many channels follow */
+ A_UINT16 channelList[1]; /* channels in Mhz */
+} POSTPACK WMI_START_SCAN_CMD;
+
+/*
+ * WMI_SET_SCAN_PARAMS_CMDID
+ */
+#define WMI_SHORTSCANRATIO_DEFAULT 3
+/*
+ * Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD
+ * Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS
+ */
+typedef enum {
+ CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */
+ SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */
+ /* already connected to */
+ ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */
+ ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */
+ REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */
+ ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't
+ scan after a disconnect event */
+ ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */
+} WMI_SCAN_CTRL_FLAGS_BITS;
+
+#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS)
+#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS)
+#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS)
+#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS)
+#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS)
+#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS)
+#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT)
+
+#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS)
+
+
+typedef PREPACK struct {
+ A_UINT16 fg_start_period; /* seconds */
+ A_UINT16 fg_end_period; /* seconds */
+ A_UINT16 bg_period; /* seconds */
+ A_UINT16 maxact_chdwell_time; /* msec */
+ A_UINT16 pas_chdwell_time; /* msec */
+ A_UINT8 shortScanRatio; /* how many shorts scan for one long */
+ A_UINT8 scanCtrlFlags;
+ A_UINT16 minact_chdwell_time; /* msec */
+ A_UINT16 maxact_scan_per_ssid; /* max active scans per ssid */
+ A_UINT32 max_dfsch_act_time; /* msecs */
+} POSTPACK WMI_SCAN_PARAMS_CMD;
+
+/*
+ * WMI_SET_BSS_FILTER_CMDID
+ */
+typedef enum {
+ NONE_BSS_FILTER = 0x0, /* no beacons forwarded */
+ ALL_BSS_FILTER, /* all beacons forwarded */
+ PROFILE_FILTER, /* only beacons matching profile */
+ ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */
+ CURRENT_BSS_FILTER, /* only beacons matching current BSS */
+ ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */
+ PROBED_SSID_FILTER, /* beacons matching probed ssid */
+ LAST_BSS_FILTER, /* marker only */
+} WMI_BSS_FILTER;
+
+typedef PREPACK struct {
+ A_UINT8 bssFilter; /* see WMI_BSS_FILTER */
+ A_UINT8 reserved1; /* For alignment */
+ A_UINT16 reserved2; /* For alignment */
+ A_UINT32 ieMask;
+} POSTPACK WMI_BSS_FILTER_CMD;
+
+/*
+ * WMI_SET_PROBED_SSID_CMDID
+ */
+#define MAX_PROBED_SSID_INDEX 9
+
+typedef enum {
+ DISABLE_SSID_FLAG = 0, /* disables entry */
+ SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */
+ ANY_SSID_FLAG = 0x02, /* probes for any ssid */
+} WMI_SSID_FLAG;
+
+typedef PREPACK struct {
+ A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */
+ A_UINT8 flag; /* WMI_SSID_FLG */
+ A_UINT8 ssidLength;
+ A_UINT8 ssid[32];
+} POSTPACK WMI_PROBED_SSID_CMD;
+
+/*
+ * WMI_SET_LISTEN_INT_CMDID
+ * The Listen interval is between 15 and 3000 TUs
+ */
+#define MIN_LISTEN_INTERVAL 15
+#define MAX_LISTEN_INTERVAL 5000
+#define MIN_LISTEN_BEACONS 1
+#define MAX_LISTEN_BEACONS 50
+
+typedef PREPACK struct {
+ A_UINT16 listenInterval;
+ A_UINT16 numBeacons;
+} POSTPACK WMI_LISTEN_INT_CMD;
+
+/*
+ * WMI_SET_BEACON_INT_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT16 beaconInterval;
+} POSTPACK WMI_BEACON_INT_CMD;
+
+/*
+ * WMI_SET_BMISS_TIME_CMDID
+ * valid values are between 1000 and 5000 TUs
+ */
+
+#define MIN_BMISS_TIME 1000
+#define MAX_BMISS_TIME 5000
+#define MIN_BMISS_BEACONS 1
+#define MAX_BMISS_BEACONS 50
+
+typedef PREPACK struct {
+ A_UINT16 bmissTime;
+ A_UINT16 numBeacons;
+} POSTPACK WMI_BMISS_TIME_CMD;
+
+/*
+ * WMI_SET_POWER_MODE_CMDID
+ */
+typedef enum {
+ REC_POWER = 0x01,
+ MAX_PERF_POWER,
+} WMI_POWER_MODE;
+
+typedef PREPACK struct {
+ A_UINT8 powerMode; /* WMI_POWER_MODE */
+} POSTPACK WMI_POWER_MODE_CMD;
+
+typedef PREPACK struct {
+ A_INT8 status; /* WMI_SET_PARAMS_REPLY */
+} POSTPACK WMI_SET_PARAMS_REPLY;
+
+typedef PREPACK struct {
+ A_UINT32 opcode;
+ A_UINT32 length;
+ A_CHAR buffer[1]; /* WMI_SET_PARAMS */
+} POSTPACK WMI_SET_PARAMS_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */
+} POSTPACK WMI_SET_MCAST_FILTER_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 enable; /* WMI_MCAST_FILTER */
+} POSTPACK WMI_MCAST_FILTER_CMD;
+
+/*
+ * WMI_SET_POWER_PARAMS_CMDID
+ */
+typedef enum {
+ IGNORE_DTIM = 0x01,
+ NORMAL_DTIM = 0x02,
+ STICK_DTIM = 0x03,
+ AUTO_DTIM = 0x04,
+} WMI_DTIM_POLICY;
+
+/* Policy to determnine whether TX should wakeup WLAN if sleeping */
+typedef enum {
+ TX_WAKEUP_UPON_SLEEP = 1,
+ TX_DONT_WAKEUP_UPON_SLEEP = 2
+} WMI_TX_WAKEUP_POLICY_UPON_SLEEP;
+
+/*
+ * Policy to determnine whether power save failure event should be sent to
+ * host during scanning
+ */
+typedef enum {
+ SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1,
+ IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2,
+} POWER_SAVE_FAIL_EVENT_POLICY;
+
+typedef PREPACK struct {
+ A_UINT16 idle_period; /* msec */
+ A_UINT16 pspoll_number;
+ A_UINT16 dtim_policy;
+ A_UINT16 tx_wakeup_policy;
+ A_UINT16 num_tx_to_wakeup;
+ A_UINT16 ps_fail_event_policy;
+} POSTPACK WMI_POWER_PARAMS_CMD;
+
+/* Adhoc power save types */
+typedef enum {
+ ADHOC_PS_DISABLE=1,
+ ADHOC_PS_ATH=2,
+ ADHOC_PS_IEEE=3,
+ ADHOC_PS_OTHER=4,
+} WMI_ADHOC_PS_TYPE;
+
+typedef PREPACK struct {
+ A_UINT8 power_saving;
+ A_UINT8 ttl; /* number of beacon periods */
+ A_UINT16 atim_windows; /* msec */
+ A_UINT16 timeout_value; /* msec */
+} POSTPACK WMI_IBSS_PM_CAPS_CMD;
+
+/* AP power save types */
+typedef enum {
+ AP_PS_DISABLE=1,
+ AP_PS_ATH=2,
+} WMI_AP_PS_TYPE;
+
+typedef PREPACK struct {
+ A_UINT32 idle_time; /* in msec */
+ A_UINT32 ps_period; /* in usec */
+ A_UINT8 sleep_period; /* in ps periods */
+ A_UINT8 psType;
+} POSTPACK WMI_AP_PS_CMD;
+
+/*
+ * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID
+ */
+typedef enum {
+ IGNORE_TIM_ALL_QUEUES_APSD = 0,
+ PROCESS_TIM_ALL_QUEUES_APSD = 1,
+ IGNORE_TIM_SIMULATED_APSD = 2,
+ PROCESS_TIM_SIMULATED_APSD = 3,
+} APSD_TIM_POLICY;
+
+typedef PREPACK struct {
+ A_UINT16 psPollTimeout; /* msec */
+ A_UINT16 triggerTimeout; /* msec */
+ A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */
+ A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */
+} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD;
+
+/*
+ * WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT16 voicePktSize;
+} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD;
+
+/*
+ * WMI_SET_MAX_SP_LEN_CMDID
+ */
+typedef enum {
+ DELIVER_ALL_PKT = 0x0,
+ DELIVER_2_PKT = 0x1,
+ DELIVER_4_PKT = 0x2,
+ DELIVER_6_PKT = 0x3,
+} APSD_SP_LEN_TYPE;
+
+typedef PREPACK struct {
+ A_UINT8 maxSPLen;
+} POSTPACK WMI_SET_MAX_SP_LEN_CMD;
+
+/*
+ * WMI_SET_DISC_TIMEOUT_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 disconnectTimeout; /* seconds */
+} POSTPACK WMI_DISC_TIMEOUT_CMD;
+
+typedef enum {
+ UPLINK_TRAFFIC = 0,
+ DNLINK_TRAFFIC = 1,
+ BIDIR_TRAFFIC = 2,
+} DIR_TYPE;
+
+typedef enum {
+ DISABLE_FOR_THIS_AC = 0,
+ ENABLE_FOR_THIS_AC = 1,
+ ENABLE_FOR_ALL_AC = 2,
+} VOICEPS_CAP_TYPE;
+
+typedef enum {
+ TRAFFIC_TYPE_APERIODIC = 0,
+ TRAFFIC_TYPE_PERIODIC = 1,
+}TRAFFIC_TYPE;
+
+/*
+ * WMI_SYNCHRONIZE_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 dataSyncMap;
+} POSTPACK WMI_SYNC_CMD;
+
+/*
+ * WMI_CREATE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT32 minServiceInt; /* in milli-sec */
+ A_UINT32 maxServiceInt; /* in milli-sec */
+ A_UINT32 inactivityInt; /* in milli-sec */
+ A_UINT32 suspensionInt; /* in milli-sec */
+ A_UINT32 serviceStartTime;
+ A_UINT32 minDataRate; /* in bps */
+ A_UINT32 meanDataRate; /* in bps */
+ A_UINT32 peakDataRate; /* in bps */
+ A_UINT32 maxBurstSize;
+ A_UINT32 delayBound;
+ A_UINT32 minPhyRate; /* in bps */
+ A_UINT32 sba;
+ A_UINT32 mediumTime;
+ A_UINT16 nominalMSDU; /* in octects */
+ A_UINT16 maxMSDU; /* in octects */
+ A_UINT8 trafficClass;
+ A_UINT8 trafficDirection; /* DIR_TYPE */
+ A_UINT8 rxQueueNum;
+ A_UINT8 trafficType; /* TRAFFIC_TYPE */
+ A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */
+ A_UINT8 tsid;
+ A_UINT8 userPriority; /* 802.1D user priority */
+ A_UINT8 nominalPHY; /* nominal phy rate */
+} POSTPACK WMI_CREATE_PSTREAM_CMD;
+
+/*
+ * WMI_DELETE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 txQueueNumber;
+ A_UINT8 rxQueueNumber;
+ A_UINT8 trafficDirection;
+ A_UINT8 trafficClass;
+ A_UINT8 tsid;
+} POSTPACK WMI_DELETE_PSTREAM_CMD;
+
+/*
+ * WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+typedef enum {
+ WMI_11A_MODE = 0x1,
+ WMI_11G_MODE = 0x2,
+ WMI_11AG_MODE = 0x3,
+ WMI_11B_MODE = 0x4,
+ WMI_11GONLY_MODE = 0x5,
+} WMI_PHY_MODE;
+
+#define WMI_MAX_CHANNELS 32
+
+typedef PREPACK struct {
+ A_UINT8 reserved1;
+ A_UINT8 scanParam; /* set if enable scan */
+ A_UINT8 phyMode; /* see WMI_PHY_MODE */
+ A_UINT8 numChannels; /* how many channels follow */
+ A_UINT16 channelList[1]; /* channels in Mhz */
+} POSTPACK WMI_CHANNEL_PARAMS_CMD;
+
+
+/*
+ * WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ * Setting the polltime to 0 would disable polling.
+ * Threshold values are in the ascending order, and should agree to:
+ * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
+ * < highThreshold_upperVal)
+ */
+
+typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{
+ A_UINT32 pollTime; /* Polling time as a factor of LI */
+ A_INT16 thresholdAbove1_Val; /* lowest of upper */
+ A_INT16 thresholdAbove2_Val;
+ A_INT16 thresholdAbove3_Val;
+ A_INT16 thresholdAbove4_Val;
+ A_INT16 thresholdAbove5_Val;
+ A_INT16 thresholdAbove6_Val; /* highest of upper */
+ A_INT16 thresholdBelow1_Val; /* lowest of bellow */
+ A_INT16 thresholdBelow2_Val;
+ A_INT16 thresholdBelow3_Val;
+ A_INT16 thresholdBelow4_Val;
+ A_INT16 thresholdBelow5_Val;
+ A_INT16 thresholdBelow6_Val; /* highest of bellow */
+ A_UINT8 weight; /* "alpha" */
+ A_UINT8 reserved[3];
+} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD;
+
+/*
+ * WMI_SNR_THRESHOLD_PARAMS_CMDID
+ * Setting the polltime to 0 would disable polling.
+ */
+
+typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{
+ A_UINT32 pollTime; /* Polling time as a factor of LI */
+ A_UINT8 weight; /* "alpha" */
+ A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/
+ A_UINT8 thresholdAbove2_Val;
+ A_UINT8 thresholdAbove3_Val;
+ A_UINT8 thresholdAbove4_Val; /* highest of upper */
+ A_UINT8 thresholdBelow1_Val; /* lowest of bellow */
+ A_UINT8 thresholdBelow2_Val;
+ A_UINT8 thresholdBelow3_Val;
+ A_UINT8 thresholdBelow4_Val; /* highest of bellow */
+ A_UINT8 reserved[3];
+} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD;
+
+/*
+ * WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS {
+ A_UINT8 enable;
+ A_UINT8 thresholdAbove1_Val;
+ A_UINT8 thresholdAbove2_Val;
+ A_UINT8 thresholdAbove3_Val;
+ A_UINT8 thresholdAbove4_Val;
+ A_UINT8 thresholdBelow1_Val;
+ A_UINT8 thresholdBelow2_Val;
+ A_UINT8 thresholdBelow3_Val;
+ A_UINT8 thresholdBelow4_Val;
+ A_UINT8 reserved[3];
+} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD;
+
+typedef enum {
+ WMI_LPREAMBLE_DISABLED = 0,
+ WMI_LPREAMBLE_ENABLED
+} WMI_LPREAMBLE_STATUS;
+
+typedef enum {
+ WMI_IGNORE_BARKER_IN_ERP = 0,
+ WMI_DONOT_IGNORE_BARKER_IN_ERP
+} WMI_PREAMBLE_POLICY;
+
+typedef PREPACK struct {
+ A_UINT8 status;
+ A_UINT8 preamblePolicy;
+}POSTPACK WMI_SET_LPREAMBLE_CMD;
+
+typedef PREPACK struct {
+ A_UINT16 threshold;
+}POSTPACK WMI_SET_RTS_CMD;
+
+/*
+ * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ * Sets the error reporting event bitmask in target. Target clears it
+ * upon an error. Subsequent errors are counted, but not reported
+ * via event, unless the bitmask is set again.
+ */
+typedef PREPACK struct {
+ A_UINT32 bitmask;
+} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK;
+
+/*
+ * WMI_SET_TX_PWR_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 dbM; /* in dbM units */
+} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
+
+/*
+ * WMI_SET_ASSOC_INFO_CMDID
+ *
+ * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
+ * A 3rd one, the CCX version IE can also be set from the host.
+ */
+#define WMI_MAX_ASSOC_INFO_TYPE 2
+#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */
+
+#define WMI_MAX_ASSOC_INFO_LEN 240
+
+typedef PREPACK struct {
+ A_UINT8 ieType;
+ A_UINT8 bufferSize;
+ A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */
+} POSTPACK WMI_SET_ASSOC_INFO_CMD;
+
+
+/*
+ * WMI_GET_TX_PWR_CMDID does not take any parameters
+ */
+
+/*
+ * WMI_ADD_BAD_AP_CMDID
+ */
+#define WMI_MAX_BAD_AP_INDEX 1
+
+typedef PREPACK struct {
+ A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_BAD_AP_CMD;
+
+/*
+ * WMI_DELETE_BAD_AP_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */
+} POSTPACK WMI_DELETE_BAD_AP_CMD;
+
+/*
+ * WMI_SET_ACCESS_PARAMS_CMDID
+ */
+#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */
+#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */
+#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */
+#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */
+#define WMI_DEFAULT_AIFSN_ACPARAM 2
+#define WMI_MAX_AIFSN_ACPARAM 15
+typedef PREPACK struct {
+ A_UINT16 txop; /* in units of 32 usec */
+ A_UINT8 eCWmin;
+ A_UINT8 eCWmax;
+ A_UINT8 aifsn;
+ A_UINT8 ac;
+} POSTPACK WMI_SET_ACCESS_PARAMS_CMD;
+
+
+/*
+ * WMI_SET_RETRY_LIMITS_CMDID
+ *
+ * This command is used to customize the number of retries the
+ * wlan device will perform on a given frame.
+ */
+#define WMI_MIN_RETRIES 2
+#define WMI_MAX_RETRIES 13
+typedef enum {
+ MGMT_FRAMETYPE = 0,
+ CONTROL_FRAMETYPE = 1,
+ DATA_FRAMETYPE = 2
+} WMI_FRAMETYPE;
+
+typedef PREPACK struct {
+ A_UINT8 frameType; /* WMI_FRAMETYPE */
+ A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */
+ A_UINT8 maxRetries;
+ A_UINT8 enableNotify;
+} POSTPACK WMI_SET_RETRY_LIMITS_CMD;
+
+/*
+ * WMI_SET_ROAM_CTRL_CMDID
+ *
+ * This command is used to influence the Roaming behaviour
+ * Set the host biases of the BSSs before setting the roam mode as bias
+ * based.
+ */
+
+/*
+ * Different types of Roam Control
+ */
+
+typedef enum {
+ WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */
+ WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */
+ WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */
+ WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */
+} WMI_ROAM_CTRL_TYPE;
+
+#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
+#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS
+
+/*
+ * ROAM MODES
+ */
+
+typedef enum {
+ WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */
+ WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
+ WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */
+} WMI_ROAM_MODE;
+
+/*
+ * BSS HOST BIAS INFO
+ */
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_INT8 bias;
+} POSTPACK WMI_BSS_BIAS;
+
+typedef PREPACK struct {
+ A_UINT8 numBss;
+ WMI_BSS_BIAS bssBias[1];
+} POSTPACK WMI_BSS_BIAS_INFO;
+
+typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS {
+ A_UINT16 lowrssi_scan_period;
+ A_INT16 lowrssi_scan_threshold;
+ A_INT16 lowrssi_roam_threshold;
+ A_UINT8 roam_rssi_floor;
+ A_UINT8 reserved[1]; /* For alignment */
+} POSTPACK WMI_LOWRSSI_SCAN_PARAMS;
+
+typedef PREPACK struct {
+ PREPACK union {
+ A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
+ A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */
+ WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
+ WMI_LOWRSSI_SCAN_PARAMS lrScanParams;
+ } POSTPACK info;
+ A_UINT8 roamCtrlType ;
+} POSTPACK WMI_SET_ROAM_CTRL_CMD;
+
+/*
+ * WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID
+ */
+typedef enum {
+ BT_WLAN_CONN_PRECDENCE_WLAN=0, /* Default */
+ BT_WLAN_CONN_PRECDENCE_PAL,
+} BT_WLAN_CONN_PRECEDENCE;
+
+typedef PREPACK struct {
+ A_UINT8 precedence;
+} POSTPACK WMI_SET_BT_WLAN_CONN_PRECEDENCE;
+
+/*
+ * WMI_ENABLE_RM_CMDID
+ */
+typedef PREPACK struct {
+ A_BOOL enable_radio_measurements;
+} POSTPACK WMI_ENABLE_RM_CMD;
+
+/*
+ * WMI_SET_MAX_OFFHOME_DURATION_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 max_offhome_duration;
+} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 frequency;
+ A_UINT8 threshold;
+} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD;
+/*---------------------- BTCOEX RELATED -------------------------------------*/
+/*----------------------COMMON to AR6002 and AR6003 -------------------------*/
+typedef enum {
+ BT_STREAM_UNDEF = 0,
+ BT_STREAM_SCO, /* SCO stream */
+ BT_STREAM_A2DP, /* A2DP stream */
+ BT_STREAM_SCAN, /* BT Discovery or Page */
+ BT_STREAM_ESCO,
+ BT_STREAM_MAX
+} BT_STREAM_TYPE;
+
+typedef enum {
+ BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1,
+ BT_PARAM_SCO_PSPOLL_LATENCY_HALF,
+ BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH,
+} BT_PARAMS_SCO_PSPOLL_LATENCY;
+
+typedef enum {
+ BT_PARAMS_SCO_STOMP_SCO_NEVER =1,
+ BT_PARAMS_SCO_STOMP_SCO_ALWAYS,
+ BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI,
+} BT_PARAMS_SCO_STOMP_RULES;
+
+typedef enum {
+ BT_STATUS_UNDEF = 0,
+ BT_STATUS_ON,
+ BT_STATUS_OFF,
+ BT_STATUS_MAX
+} BT_STREAM_STATUS;
+
+typedef PREPACK struct {
+ A_UINT8 streamType;
+ A_UINT8 status;
+} POSTPACK WMI_SET_BT_STATUS_CMD;
+
+typedef enum {
+ BT_ANT_TYPE_UNDEF=0,
+ BT_ANT_TYPE_DUAL,
+ BT_ANT_TYPE_SPLITTER,
+ BT_ANT_TYPE_SWITCH,
+ BT_ANT_TYPE_HIGH_ISO_DUAL
+} BT_ANT_FRONTEND_CONFIG;
+
+typedef enum {
+ BT_COLOCATED_DEV_BTS4020=0,
+ BT_COLCATED_DEV_CSR ,
+ BT_COLOCATED_DEV_VALKYRIE
+} BT_COLOCATED_DEV_TYPE;
+
+/*********************** Applicable to AR6002 ONLY ******************************/
+
+typedef enum {
+ BT_PARAM_SCO = 1, /* SCO stream parameters */
+ BT_PARAM_A2DP ,
+ BT_PARAM_ANTENNA_CONFIG,
+ BT_PARAM_COLOCATED_BT_DEVICE,
+ BT_PARAM_ACLCOEX,
+ BT_PARAM_11A_SEPARATE_ANT,
+ BT_PARAM_MAX
+} BT_PARAM_TYPE;
+
+
+#define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0)
+#define BT_SCO_FORCE_AWAKE_OPT (1 << 1)
+#define BT_SCO_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2))
+#define BT_SCO_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1)
+#define BT_SCO_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3))
+#define BT_SCO_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1)
+#define BT_SCO_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF)
+#define BT_SCO_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF)
+#define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8)
+#define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16)
+
+typedef PREPACK struct {
+ A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which
+ force a pspoll. default = 10 */
+ A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt
+ in response for ps-poll,
+ default = 10 msecs */
+ A_UINT32 stompScoRules;
+ A_UINT32 scoOptFlags; /* SCO Options Flags :
+ bits: meaning:
+ 0 Allow Close Range Optimization
+ 1 Force awake during close range
+ 2 If set use host supplied RSSI for OPT
+ 3 If set use host supplied RTS COUNT for OPT
+ 4..7 Unused
+ 8..15 Low Data Rate Min Cnt
+ 16..23 Low Data Rate Max Cnt
+ */
+
+ A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing
+ if stomped */
+ A_UINT8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle
+ gradually uptill this value on need basis*/
+ A_UINT8 psPollLatencyFraction; /* Fraction of idle
+ period, within which
+ additional ps-polls
+ can be queued */
+ A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots.
+ HVx, EV3, 2EV3 = 2 */
+ A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between
+ consecutive SCO Tx/Rx slots
+ HVx, EV3 = 4
+ 2EV3 = 10 */
+ A_UINT8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/
+ A_UINT8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/
+ A_UINT8 scoOptRtsCount;
+} POSTPACK BT_PARAMS_SCO;
+
+#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0)
+#define BT_A2DP_FORCE_AWAKE_OPT (1 << 1)
+#define BT_A2DP_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2))
+#define BT_A2DP_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1)
+#define BT_A2DP_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3))
+#define BT_A2DP_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1)
+#define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF)
+#define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF)
+#define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8)
+#define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16)
+
+typedef PREPACK struct {
+ A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for
+ wlan, after it identifies the idle time
+ default (30 msecs) */
+ A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames
+ to replenish Wlan Usage limit (default 3) */
+ A_UINT32 a2dpDataRespTimeout;
+ A_UINT32 a2dpOptFlags; /* A2DP Option flags:
+ bits: meaning:
+ 0 Allow Close Range Optimization
+ 1 Force awake during close range
+ 2 If set use host supplied RSSI for OPT
+ 3 If set use host supplied RTS COUNT for OPT
+ 4..7 Unused
+ 8..15 Low Data Rate Min Cnt
+ 16..23 Low Data Rate Max Cnt
+ */
+ A_UINT8 isCoLocatedBtRoleMaster;
+ A_UINT8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/
+ A_UINT8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/
+ A_UINT8 a2dpOptRtsCount;
+}POSTPACK BT_PARAMS_A2DP;
+
+/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth
+ (non a2dp).*/
+typedef PREPACK struct {
+ A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp)
+ coexistence (default 30 msecs) */
+ A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence
+ (default 30 msecs)*/
+ A_UINT32 aclDataRespTimeout;
+ A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get
+ 10 Pkts in X msec(default 100 msecs) */
+ A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before
+ enabling ACL coex */
+
+}POSTPACK BT_PARAMS_ACLCOEX;
+
+typedef PREPACK struct {
+ PREPACK union {
+ BT_PARAMS_SCO scoParams;
+ BT_PARAMS_A2DP a2dpParams;
+ BT_PARAMS_ACLCOEX aclCoexParams;
+ A_UINT8 antType; /* 0 -Disabled (default)
+ 1 - BT_ANT_TYPE_DUAL
+ 2 - BT_ANT_TYPE_SPLITTER
+ 3 - BT_ANT_TYPE_SWITCH */
+ A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default)
+ 1 - BT_COLCATED_DEV_CSR
+ 2 - BT_COLOCATED_DEV_VALKYRIe
+ */
+ } POSTPACK info;
+ A_UINT8 paramType ;
+} POSTPACK WMI_SET_BT_PARAMS_CMD;
+
+/************************ END AR6002 BTCOEX *******************************/
+/*-----------------------AR6003 BTCOEX -----------------------------------*/
+
+/* ---------------WMI_SET_BTCOEX_FE_ANT_CMDID --------------------------*/
+/* Indicates front end antenna configuration. This command needs to be issued
+ * right after initialization and after WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID.
+ * AR6003 enables coexistence and antenna switching based on the configuration.
+ */
+typedef enum {
+ WMI_BTCOEX_NOT_ENABLED = 0,
+ WMI_BTCOEX_FE_ANT_SINGLE =1,
+ WMI_BTCOEX_FE_ANT_DUAL=2,
+ WMI_BTCOEX_FE_ANT_DUAL_HIGH_ISO=3,
+ WMI_BTCOEX_FE_ANT_TYPE_MAX
+}WMI_BTCOEX_FE_ANT_TYPE;
+
+typedef PREPACK struct {
+ A_UINT8 btcoexFeAntType; /* 1 - WMI_BTCOEX_FE_ANT_SINGLE for single antenna front end
+ 2 - WMI_BTCOEX_FE_ANT_DUAL for dual antenna front end
+ (for isolations less 35dB, for higher isolation there
+ is not need to pass this command).
+ (not implemented)
+ */
+}POSTPACK WMI_SET_BTCOEX_FE_ANT_CMD;
+
+/* -------------WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID ----------------*/
+/* Indicate the bluetooth chip to the firmware. Firmware can have different algorithm based
+ * bluetooth chip type.Based on bluetooth device, different coexistence protocol would be used.
+ */
+typedef PREPACK struct {
+ A_UINT8 btcoexCoLocatedBTdev; /*1 - Qcom BT (3 -wire PTA)
+ 2 - CSR BT (3 wire PTA)
+ 3 - Atheros 3001 BT (3 wire PTA)
+ 4 - STE bluetooth (4-wire ePTA)
+ 5 - Atheros 3002 BT (4-wire MCI)
+ defaults= 3 (Atheros 3001 BT )
+ */
+}POSTPACK WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD;
+
+/* -------------WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID ------------*/
+/* Configuration parameters during bluetooth inquiry and page. Page configuration
+ * is applicable only on interfaces which can distinguish page (applicable only for ePTA -
+ * STE bluetooth).
+ * Bluetooth inquiry start and end is indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID.
+ * During this the station will be power-save mode.
+ */
+typedef PREPACK struct {
+ A_UINT32 btInquiryDataFetchFrequency;/* The frequency of querying the AP for data
+ (via pspoll) is configured by this parameter.
+ "default = 10 ms" */
+
+ A_UINT32 protectBmissDurPostBtInquiry;/* The firmware will continue to be in inquiry state
+ for configured duration, after inquiry completion
+ . This is to ensure other bluetooth transactions
+ (RDP, SDP profiles, link key exchange ...etc)
+ goes through smoothly without wifi stomping.
+ default = 10 secs*/
+
+ A_UINT32 maxpageStomp; /*Applicable only for STE-BT interface. Currently not
+ used */
+ A_UINT32 btInquiryPageFlag; /* Not used */
+}POSTPACK WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD;
+
+/*---------------------WMI_SET_BTCOEX_SCO_CONFIG_CMDID ---------------*/
+/* Configure SCO parameters. These parameters would be used whenever firmware is indicated
+ * of (e)SCO profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID).
+ * Configration of BTCOEX_SCO_CONFIG data structure are common configuration and applies
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data between sco gaps.
+ * Opt Mode - station is in awake state and access point can send data to station any time.
+ * BTCOEX_PSPOLLMODE_SCO_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_SCO_CONFIG - Configuration applied only during opt mode.
+ */
+typedef PREPACK struct {
+ A_UINT32 scoSlots; /* Number of SCO Tx/Rx slots.
+ HVx, EV3, 2EV3 = 2 */
+ A_UINT32 scoIdleSlots; /* Number of Bluetooth idle slots between
+ consecutive SCO Tx/Rx slots
+ HVx, EV3 = 4
+ 2EV3 = 10
+ */
+ A_UINT32 scoFlags; /* SCO Options Flags :
+ bits: meaning:
+ 0 Allow Close Range Optimization
+ 1 Is EDR capable or Not
+ 2 IS Co-located Bt role Master
+ */
+
+ A_UINT32 linkId; /* applicable to STE-BT - not used */
+}POSTPACK BTCOEX_SCO_CONFIG;
+
+typedef PREPACK struct {
+ A_UINT32 scoCyclesForceTrigger; /* Number SCO cycles after which
+ force a pspoll. default = 10 */
+ A_UINT32 scoDataResponseTimeout; /* Timeout Waiting for Downlink pkt
+ in response for ps-poll,
+ default = 20 msecs */
+
+ A_UINT32 scoStompDutyCyleVal; /* not implemented */
+
+ A_UINT32 scoStompDutyCyleMaxVal; /*Not implemented */
+
+ A_UINT32 scoPsPollLatencyFraction; /* Fraction of idle
+ period, within which
+ additional ps-polls can be queued
+ 1 - 1/4 of idle duration
+ 2 - 1/2 of idle duration
+ 3 - 3/4 of idle duration
+ default =2 (1/2)
+ */
+}POSTPACK BTCOEX_PSPOLLMODE_SCO_CONFIG;
+
+typedef PREPACK struct {
+ A_UINT32 scoStompCntIn100ms;/*max number of SCO stomp in 100ms allowed in
+ opt mode. If exceeds the configured value,
+ switch to ps-poll mode
+ default = 3 */
+
+ A_UINT32 scoContStompMax; /* max number of continous stomp allowed in opt mode.
+ if excedded switch to pspoll mode
+ default = 3 */
+
+ A_UINT32 scoMinlowRateMbps; /* Low rate threshold */
+
+ A_UINT32 scoLowRateCnt; /* number of low rate pkts (< scoMinlowRateMbps) allowed in 100 ms.
+ If exceeded switch/stay to ps-poll mode, lower stay in opt mode.
+ default = 36
+ */
+
+ A_UINT32 scoHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/
+ ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms,
+ if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode.
+ default = 5 (80% of high rates)
+ */
+
+ A_UINT32 scoMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates
+ max number of aggregates if it was negogiated to higher value
+ default = 1
+ Recommended value Basic rate headsets = 1, EDR (2-EV3) =4.
+ */
+}POSTPACK BTCOEX_OPTMODE_SCO_CONFIG;
+
+typedef PREPACK struct {
+ BTCOEX_SCO_CONFIG scoConfig;
+ BTCOEX_PSPOLLMODE_SCO_CONFIG scoPspollConfig;
+ BTCOEX_OPTMODE_SCO_CONFIG scoOptModeConfig;
+}POSTPACK WMI_SET_BTCOEX_SCO_CONFIG_CMD;
+
+/* ------------------WMI_SET_BTCOEX_A2DP_CONFIG_CMDID -------------------*/
+/* Configure A2DP profile parameters. These parameters would be used whenver firmware is indicated
+ * of A2DP profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID).
+ * Configuration of BTCOEX_A2DP_CONFIG data structure are common configuration and applies to
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data between a2dp data bursts.
+ * Opt Mode - station is in power save during a2dp bursts and awake in the gaps.
+ * BTCOEX_PSPOLLMODE_A2DP_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_A2DP_CONFIG - Configuration applied only during opt mode.
+ */
+
+typedef PREPACK struct {
+ A_UINT32 a2dpFlags; /* A2DP Option flags:
+ bits: meaning:
+ 0 Allow Close Range Optimization
+ 1 IS EDR capable
+ 2 IS Co-located Bt role Master
+ 3 a2dp traffic is high priority
+ */
+ A_UINT32 linkId; /* Applicable only to STE-BT - not used */
+
+}POSTPACK BTCOEX_A2DP_CONFIG;
+
+typedef PREPACK struct {
+ A_UINT32 a2dpWlanMaxDur; /* MAX time firmware uses the medium for
+ wlan, after it identifies the idle time
+ default (30 msecs) */
+
+ A_UINT32 a2dpMinBurstCnt; /* Minimum number of bluetooth data frames
+ to replenish Wlan Usage limit (default 3) */
+
+ A_UINT32 a2dpDataRespTimeout; /* Max duration firmware waits for downlink
+ by stomping on bluetooth
+ after ps-poll is acknowledged.
+ default = 20 ms
+ */
+}POSTPACK BTCOEX_PSPOLLMODE_A2DP_CONFIG;
+
+typedef PREPACK struct {
+ A_UINT32 a2dpMinlowRateMbps; /* Low rate threshold */
+
+ A_UINT32 a2dpLowRateCnt; /* number of low rate pkts (< a2dpMinlowRateMbps) allowed in 100 ms.
+ If exceeded switch/stay to ps-poll mode, lower stay in opt mode.
+ default = 36
+ */
+
+ A_UINT32 a2dpHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/
+ ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms,
+ if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode.
+ default = 5 (80% of high rates)
+ */
+
+ A_UINT32 a2dpMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates
+ max number of aggregates if it was negogiated to higher value
+ default = 1
+ Recommended value Basic rate headsets = 1, EDR (2-EV3) =8.
+ */
+ A_UINT32 a2dpPktStompCnt; /*number of a2dp pkts that can be stomped per burst.
+ default = 6*/
+
+}POSTPACK BTCOEX_OPTMODE_A2DP_CONFIG;
+
+typedef PREPACK struct {
+ BTCOEX_A2DP_CONFIG a2dpConfig;
+ BTCOEX_PSPOLLMODE_A2DP_CONFIG a2dppspollConfig;
+ BTCOEX_OPTMODE_A2DP_CONFIG a2dpOptConfig;
+}POSTPACK WMI_SET_BTCOEX_A2DP_CONFIG_CMD;
+
+/*------------ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID---------------------*/
+/* Configure non-A2dp ACL profile parameters.The starts of ACL profile can either be
+ * indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID orenabled via firmware detection
+ * which is configured via "aclCoexFlags".
+ * Configration of BTCOEX_ACLCOEX_CONFIG data structure are common configuration and applies
+ * ps-poll mode and opt mode.
+ * Ps-poll Mode - Station is in power-save and retrieves downlink data during wlan medium.
+ * Opt Mode - station is in power save during bluetooth medium time and awake during wlan duration.
+ * (Not implemented yet)
+ *
+ * BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG - Configuration applied only during ps-poll mode.
+ * BTCOEX_OPTMODE_ACLCOEX_CONFIG - Configuration applied only during opt mode.
+ */
+
+typedef PREPACK struct {
+ A_UINT32 aclWlanMediumDur; /* Wlan usage time during Acl (non-a2dp)
+ coexistence (default 30 msecs)
+ */
+
+ A_UINT32 aclBtMediumDur; /* Bt usage time during acl coexistence
+ (default 30 msecs)
+ */
+
+ A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get
+ 10 Pkts in X msec(default 100 msecs)
+ */
+
+ A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before
+ enabling ACL coex
+ default = 9
+ */
+
+ A_UINT32 aclCoexFlags; /* A2DP Option flags:
+ bits: meaning:
+ 0 Allow Close Range Optimization
+ 1 disable Firmware detection
+ (Currently supported configuration is aclCoexFlags =0)
+ */
+ A_UINT32 linkId; /* Applicable only for STE-BT - not used */
+
+}POSTPACK BTCOEX_ACLCOEX_CONFIG;
+
+typedef PREPACK struct {
+ A_UINT32 aclDataRespTimeout; /* Max duration firmware waits for downlink
+ by stomping on bluetooth
+ after ps-poll is acknowledged.
+ default = 20 ms */
+
+}POSTPACK BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG;
+
+
+/* Not implemented yet*/
+typedef PREPACK struct {
+ A_UINT32 aclCoexMinlowRateMbps;
+ A_UINT32 aclCoexLowRateCnt;
+ A_UINT32 aclCoexHighPktRatio;
+ A_UINT32 aclCoexMaxAggrSize;
+ A_UINT32 aclPktStompCnt;
+}POSTPACK BTCOEX_OPTMODE_ACLCOEX_CONFIG;
+
+typedef PREPACK struct {
+ BTCOEX_ACLCOEX_CONFIG aclCoexConfig;
+ BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG aclCoexPspollConfig;
+ BTCOEX_OPTMODE_ACLCOEX_CONFIG aclCoexOptConfig;
+}POSTPACK WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD;
+
+/* -----------WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ------------------*/
+typedef enum {
+ WMI_BTCOEX_BT_PROFILE_SCO =1,
+ WMI_BTCOEX_BT_PROFILE_A2DP,
+ WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE,
+ WMI_BTCOEX_BT_PROFILE_ACLCOEX,
+}WMI_BTCOEX_BT_PROFILE;
+
+typedef PREPACK struct {
+ A_UINT32 btProfileType;
+ A_UINT32 btOperatingStatus;
+ A_UINT32 btLinkId;
+}WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD;
+
+/*--------------------- WMI_SET_BTCOEX_DEBUG_CMDID ---------------------*/
+/* Used for firmware development and debugging */
+typedef PREPACK struct {
+ A_UINT32 btcoexDbgParam1;
+ A_UINT32 btcoexDbgParam2;
+ A_UINT32 btcoexDbgParam3;
+ A_UINT32 btcoexDbgParam4;
+ A_UINT32 btcoexDbgParam5;
+}WMI_SET_BTCOEX_DEBUG_CMD;
+
+/*---------------------WMI_GET_BTCOEX_CONFIG_CMDID --------------------- */
+/* Command to firmware to get configuration parameters of the bt profile
+ * reported via WMI_BTCOEX_CONFIG_EVENTID */
+typedef PREPACK struct {
+ A_UINT32 btProfileType; /* 1 - SCO
+ 2 - A2DP
+ 3 - INQUIRY_PAGE
+ 4 - ACLCOEX
+ */
+ A_UINT32 linkId; /* not used */
+}WMI_GET_BTCOEX_CONFIG_CMD;
+
+/*------------------WMI_REPORT_BTCOEX_CONFIG_EVENTID------------------- */
+/* Event from firmware to host, sent in response to WMI_GET_BTCOEX_CONFIG_CMDID
+ * */
+typedef PREPACK struct {
+ A_UINT32 btProfileType;
+ A_UINT32 linkId; /* not used */
+ PREPACK union {
+ WMI_SET_BTCOEX_SCO_CONFIG_CMD scoConfigCmd;
+ WMI_SET_BTCOEX_A2DP_CONFIG_CMD a2dpConfigCmd;
+ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD aclcoexConfig;
+ WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD btinquiryPageConfigCmd;
+ } POSTPACK info;
+} POSTPACK WMI_BTCOEX_CONFIG_EVENT;
+
+/*------------- WMI_REPORT_BTCOEX_BTCOEX_STATS_EVENTID--------------------*/
+/* Used for firmware development and debugging*/
+typedef PREPACK struct {
+ A_UINT32 highRatePktCnt;
+ A_UINT32 firstBmissCnt;
+ A_UINT32 psPollFailureCnt;
+ A_UINT32 nullFrameFailureCnt;
+ A_UINT32 optModeTransitionCnt;
+}BTCOEX_GENERAL_STATS;
+
+typedef PREPACK struct {
+ A_UINT32 scoStompCntAvg;
+ A_UINT32 scoStompIn100ms;
+ A_UINT32 scoMaxContStomp;
+ A_UINT32 scoAvgNoRetries;
+ A_UINT32 scoMaxNoRetriesIn100ms;
+}BTCOEX_SCO_STATS;
+
+typedef PREPACK struct {
+ A_UINT32 a2dpBurstCnt;
+ A_UINT32 a2dpMaxBurstCnt;
+ A_UINT32 a2dpAvgIdletimeIn100ms;
+ A_UINT32 a2dpAvgStompCnt;
+}BTCOEX_A2DP_STATS;
+
+typedef PREPACK struct {
+ A_UINT32 aclPktCntInBtTime;
+ A_UINT32 aclStompCntInWlanTime;
+ A_UINT32 aclPktCntIn100ms;
+}BTCOEX_ACLCOEX_STATS;
+
+typedef PREPACK struct {
+ BTCOEX_GENERAL_STATS coexStats;
+ BTCOEX_SCO_STATS scoStats;
+ BTCOEX_A2DP_STATS a2dpStats;
+ BTCOEX_ACLCOEX_STATS aclCoexStats;
+}WMI_BTCOEX_STATS_EVENT;
+
+
+
+/*--------------------------END OF BTCOEX -------------------------------------*/
+typedef enum {
+ DISCONN_EVT_IN_RECONN = 0, /* default */
+ NO_DISCONN_EVT_IN_RECONN
+} TARGET_EVENT_REPORT_CONFIG;
+
+typedef PREPACK struct {
+ A_UINT32 evtConfig;
+} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD;
+
+
+typedef PREPACK struct {
+ A_UINT16 cmd_buf_sz; /* HCI cmd buffer size */
+ A_UINT8 buf[1]; /* Absolute HCI cmd */
+} POSTPACK WMI_HCI_CMD;
+
+/*
+ * Command Replies
+ */
+
+/*
+ * WMI_GET_CHANNEL_LIST_CMDID reply
+ */
+typedef PREPACK struct {
+ A_UINT8 reserved1;
+ A_UINT8 numChannels; /* number of channels in reply */
+ A_UINT16 channelList[1]; /* channel in Mhz */
+} POSTPACK WMI_CHANNEL_LIST_REPLY;
+
+typedef enum {
+ A_SUCCEEDED = A_OK,
+ A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250,
+ A_SUCCEEDED_MODIFY_STREAM=251,
+ A_FAILED_INVALID_STREAM = 252,
+ A_FAILED_MAX_THINSTREAMS = 253,
+ A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
+} PSTREAM_REPLY_STATUS;
+
+typedef PREPACK struct {
+ A_UINT8 status; /* PSTREAM_REPLY_STATUS */
+ A_UINT8 txQueueNumber;
+ A_UINT8 rxQueueNumber;
+ A_UINT8 trafficClass;
+ A_UINT8 trafficDirection; /* DIR_TYPE */
+} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY;
+
+typedef PREPACK struct {
+ A_UINT8 status; /* PSTREAM_REPLY_STATUS */
+ A_UINT8 txQueueNumber;
+ A_UINT8 rxQueueNumber;
+ A_UINT8 trafficDirection; /* DIR_TYPE */
+ A_UINT8 trafficClass;
+} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY;
+
+/*
+ * List of Events (target to host)
+ */
+typedef enum {
+ WMI_READY_EVENTID = 0x1001,
+ WMI_CONNECT_EVENTID,
+ WMI_DISCONNECT_EVENTID,
+ WMI_BSSINFO_EVENTID,
+ WMI_CMDERROR_EVENTID,
+ WMI_REGDOMAIN_EVENTID,
+ WMI_PSTREAM_TIMEOUT_EVENTID,
+ WMI_NEIGHBOR_REPORT_EVENTID,
+ WMI_TKIP_MICERR_EVENTID,
+ WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */
+ WMI_REPORT_STATISTICS_EVENTID,
+ WMI_RSSI_THRESHOLD_EVENTID,
+ WMI_ERROR_REPORT_EVENTID,
+ WMI_OPT_RX_FRAME_EVENTID,
+ WMI_REPORT_ROAM_TBL_EVENTID,
+ WMI_EXTENSION_EVENTID,
+ WMI_CAC_EVENTID,
+ WMI_SNR_THRESHOLD_EVENTID,
+ WMI_LQ_THRESHOLD_EVENTID,
+ WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */
+ WMI_REPORT_ROAM_DATA_EVENTID,
+ WMI_TEST_EVENTID,
+ WMI_APLIST_EVENTID,
+ WMI_GET_WOW_LIST_EVENTID,
+ WMI_GET_PMKID_LIST_EVENTID,
+ WMI_CHANNEL_CHANGE_EVENTID,
+ WMI_PEER_NODE_EVENTID,
+ WMI_PSPOLL_EVENTID,
+ WMI_DTIMEXPIRY_EVENTID,
+ WMI_WLAN_VERSION_EVENTID,
+ WMI_SET_PARAMS_REPLY_EVENTID,
+ WMI_ADDBA_REQ_EVENTID, /*0x1020 */
+ WMI_ADDBA_RESP_EVENTID,
+ WMI_DELBA_REQ_EVENTID,
+ WMI_TX_COMPLETE_EVENTID,
+ WMI_HCI_EVENT_EVENTID,
+ WMI_ACL_DATA_EVENTID,
+#ifdef WAPI_ENABLE
+ WMI_WAPI_REKEY_EVENTID,
+#endif
+ WMI_REPORT_BTCOEX_STATS_EVENTID,
+ WMI_REPORT_BTCOEX_CONFIG_EVENTID,
+
+ WMI_THIN_RESERVED_START_EVENTID = 0x8000,
+ /* Events in this range are reserved for thinmode
+ * See wmi_thin.h for actual definitions */
+ WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
+
+} WMI_EVENT_ID;
+
+
+typedef enum {
+ WMI_11A_CAPABILITY = 1,
+ WMI_11G_CAPABILITY = 2,
+ WMI_11AG_CAPABILITY = 3,
+ WMI_11NA_CAPABILITY = 4,
+ WMI_11NG_CAPABILITY = 5,
+ WMI_11NAG_CAPABILITY = 6,
+ // END CAPABILITY
+ WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
+} WMI_PHY_CAPABILITY;
+
+typedef PREPACK struct {
+ A_UINT8 macaddr[ATH_MAC_LEN];
+ A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT_1;
+
+typedef PREPACK struct {
+ A_UINT32 version;
+ A_UINT8 macaddr[ATH_MAC_LEN];
+ A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT_2;
+
+#if defined(ATH_TARGET)
+#ifdef AR6002_REV2
+#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */
+#else
+#define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6002_REV4 and AR6001 */
+#endif
+#else
+#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */
+#endif
+
+
+/*
+ * Connect Event
+ */
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT16 listenInterval;
+ A_UINT16 beaconInterval;
+ A_UINT32 networkType;
+ A_UINT8 beaconIeLen;
+ A_UINT8 assocReqLen;
+ A_UINT8 assocRespLen;
+ A_UINT8 assocInfo[1];
+} POSTPACK WMI_CONNECT_EVENT;
+
+/*
+ * Disconnect Event
+ */
+typedef enum {
+ NO_NETWORK_AVAIL = 0x01,
+ LOST_LINK = 0x02, /* bmiss */
+ DISCONNECT_CMD = 0x03,
+ BSS_DISCONNECTED = 0x04,
+ AUTH_FAILED = 0x05,
+ ASSOC_FAILED = 0x06,
+ NO_RESOURCES_AVAIL = 0x07,
+ CSERV_DISCONNECT = 0x08,
+ INVALID_PROFILE = 0x0a,
+ DOT11H_CHANNEL_SWITCH = 0x0b,
+ PROFILE_MISMATCH = 0x0c,
+ CONNECTION_EVICTED = 0x0d,
+} WMI_DISCONNECT_REASON;
+
+typedef PREPACK struct {
+ A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */
+ A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */
+ A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */
+ A_UINT8 assocRespLen;
+ A_UINT8 assocInfo[1];
+} POSTPACK WMI_DISCONNECT_EVENT;
+
+/*
+ * BSS Info Event.
+ * Mechanism used to inform host of the presence and characteristic of
+ * wireless networks present. Consists of bss info header followed by
+ * the beacon or probe-response frame body. The 802.11 header is not included.
+ */
+typedef enum {
+ BEACON_FTYPE = 0x1,
+ PROBERESP_FTYPE,
+ ACTION_MGMT_FTYPE,
+ PROBEREQ_FTYPE,
+} WMI_BI_FTYPE;
+
+enum {
+ BSS_ELEMID_CHANSWITCH = 0x01,
+ BSS_ELEMID_ATHEROS = 0x02,
+};
+
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 frameType; /* see WMI_BI_FTYPE */
+ A_UINT8 snr;
+ A_INT16 rssi;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT32 ieMask;
+} POSTPACK WMI_BSS_INFO_HDR;
+
+/*
+ * BSS INFO HDR version 2.0
+ * With 6 bytes HTC header and 6 bytes of WMI header
+ * WMI_BSS_INFO_HDR cannot be accomodated in the removed 802.11 management
+ * header space.
+ * - Reduce the ieMask to 2 bytes as only two bit flags are used
+ * - Remove rssi and compute it on the host. rssi = snr - 95
+ */
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 frameType; /* see WMI_BI_FTYPE */
+ A_UINT8 snr;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT16 ieMask;
+} POSTPACK WMI_BSS_INFO_HDR2;
+
+/*
+ * Command Error Event
+ */
+typedef enum {
+ INVALID_PARAM = 0x01,
+ ILLEGAL_STATE = 0x02,
+ INTERNAL_ERROR = 0x03,
+} WMI_ERROR_CODE;
+
+typedef PREPACK struct {
+ A_UINT16 commandId;
+ A_UINT8 errorCode;
+} POSTPACK WMI_CMD_ERROR_EVENT;
+
+/*
+ * New Regulatory Domain Event
+ */
+typedef PREPACK struct {
+ A_UINT32 regDomain;
+} POSTPACK WMI_REG_DOMAIN_EVENT;
+
+typedef PREPACK struct {
+ A_UINT8 txQueueNumber;
+ A_UINT8 rxQueueNumber;
+ A_UINT8 trafficDirection;
+ A_UINT8 trafficClass;
+} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT;
+
+/*
+ * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
+ * the host of BSS's it has found that matches the current profile.
+ * It can be used by the host to cache PMKs and/to initiate pre-authentication
+ * if the BSS supports it. The first bssid is always the current associated
+ * BSS.
+ * The bssid and bssFlags information repeats according to the number
+ * or APs reported.
+ */
+typedef enum {
+ WMI_DEFAULT_BSS_FLAGS = 0x00,
+ WMI_PREAUTH_CAPABLE_BSS = 0x01,
+ WMI_PMKID_VALID_BSS = 0x02,
+} WMI_BSS_FLAGS;
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */
+} POSTPACK WMI_NEIGHBOR_INFO;
+
+typedef PREPACK struct {
+ A_INT8 numberOfAps;
+ WMI_NEIGHBOR_INFO neighbor[1];
+} POSTPACK WMI_NEIGHBOR_REPORT_EVENT;
+
+/*
+ * TKIP MIC Error Event
+ */
+typedef PREPACK struct {
+ A_UINT8 keyid;
+ A_UINT8 ismcast;
+} POSTPACK WMI_TKIP_MICERR_EVENT;
+
+/*
+ * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new)
+ */
+typedef PREPACK struct {
+ A_INT32 status;
+} POSTPACK WMI_SCAN_COMPLETE_EVENT;
+
+#define MAX_OPT_DATA_LEN 1400
+
+/*
+ * WMI_SET_ADHOC_BSSID_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_SET_ADHOC_BSSID_CMD;
+
+/*
+ * WMI_SET_OPT_MODE_CMDID
+ */
+typedef enum {
+ SPECIAL_OFF,
+ SPECIAL_ON,
+} OPT_MODE_TYPE;
+
+typedef PREPACK struct {
+ A_UINT8 optMode;
+} POSTPACK WMI_SET_OPT_MODE_CMD;
+
+/*
+ * WMI_TX_OPT_FRAME_CMDID
+ */
+typedef enum {
+ OPT_PROBE_REQ = 0x01,
+ OPT_PROBE_RESP = 0x02,
+ OPT_CPPP_START = 0x03,
+ OPT_CPPP_STOP = 0x04,
+} WMI_OPT_FTYPE;
+
+typedef PREPACK struct {
+ A_UINT16 optIEDataLen;
+ A_UINT8 frmType;
+ A_UINT8 dstAddr[ATH_MAC_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 reserved; /* For alignment */
+ A_UINT8 optIEData[1];
+} POSTPACK WMI_OPT_TX_FRAME_CMD;
+
+/*
+ * Special frame receive Event.
+ * Mechanism used to inform host of the receiption of the special frames.
+ * Consists of special frame info header followed by special frame body.
+ * The 802.11 header is not included.
+ */
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 frameType; /* see WMI_OPT_FTYPE */
+ A_INT8 snr;
+ A_UINT8 srcAddr[ATH_MAC_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_OPT_RX_INFO_HDR;
+
+/*
+ * Reporting statistics.
+ */
+typedef PREPACK struct {
+ A_UINT32 tx_packets;
+ A_UINT32 tx_bytes;
+ A_UINT32 tx_unicast_pkts;
+ A_UINT32 tx_unicast_bytes;
+ A_UINT32 tx_multicast_pkts;
+ A_UINT32 tx_multicast_bytes;
+ A_UINT32 tx_broadcast_pkts;
+ A_UINT32 tx_broadcast_bytes;
+ A_UINT32 tx_rts_success_cnt;
+ A_UINT32 tx_packet_per_ac[4];
+ A_UINT32 tx_errors_per_ac[4];
+
+ A_UINT32 tx_errors;
+ A_UINT32 tx_failed_cnt;
+ A_UINT32 tx_retry_cnt;
+ A_UINT32 tx_mult_retry_cnt;
+ A_UINT32 tx_rts_fail_cnt;
+ A_INT32 tx_unicast_rate;
+}POSTPACK tx_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 rx_packets;
+ A_UINT32 rx_bytes;
+ A_UINT32 rx_unicast_pkts;
+ A_UINT32 rx_unicast_bytes;
+ A_UINT32 rx_multicast_pkts;
+ A_UINT32 rx_multicast_bytes;
+ A_UINT32 rx_broadcast_pkts;
+ A_UINT32 rx_broadcast_bytes;
+ A_UINT32 rx_fragment_pkt;
+
+ A_UINT32 rx_errors;
+ A_UINT32 rx_crcerr;
+ A_UINT32 rx_key_cache_miss;
+ A_UINT32 rx_decrypt_err;
+ A_UINT32 rx_duplicate_frames;
+ A_INT32 rx_unicast_rate;
+}POSTPACK rx_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 tkip_local_mic_failure;
+ A_UINT32 tkip_counter_measures_invoked;
+ A_UINT32 tkip_replays;
+ A_UINT32 tkip_format_errors;
+ A_UINT32 ccmp_format_errors;
+ A_UINT32 ccmp_replays;
+}POSTPACK tkip_ccmp_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 power_save_failure_cnt;
+ A_UINT16 stop_tx_failure_cnt;
+ A_UINT16 atim_tx_failure_cnt;
+ A_UINT16 atim_rx_failure_cnt;
+ A_UINT16 bcn_rx_failure_cnt;
+}POSTPACK pm_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 cs_bmiss_cnt;
+ A_UINT32 cs_lowRssi_cnt;
+ A_UINT16 cs_connect_cnt;
+ A_UINT16 cs_disconnect_cnt;
+ A_INT16 cs_aveBeacon_rssi;
+ A_UINT16 cs_roam_count;
+ A_INT16 cs_rssi;
+ A_UINT8 cs_snr;
+ A_UINT8 cs_aveBeacon_snr;
+ A_UINT8 cs_lastRoam_msec;
+} POSTPACK cserv_stats_t;
+
+typedef PREPACK struct {
+ tx_stats_t tx_stats;
+ rx_stats_t rx_stats;
+ tkip_ccmp_stats_t tkipCcmpStats;
+}POSTPACK wlan_net_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 arp_received;
+ A_UINT32 arp_matched;
+ A_UINT32 arp_replied;
+} POSTPACK arp_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 wow_num_pkts_dropped;
+ A_UINT16 wow_num_events_discarded;
+ A_UINT8 wow_num_host_pkt_wakeups;
+ A_UINT8 wow_num_host_event_wakeups;
+} POSTPACK wlan_wow_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 lqVal;
+ A_INT32 noise_floor_calibation;
+ pm_stats_t pmStats;
+ wlan_net_stats_t txrxStats;
+ wlan_wow_stats_t wowStats;
+ arp_stats_t arpStats;
+ cserv_stats_t cservStats;
+} POSTPACK WMI_TARGET_STATS;
+
+/*
+ * WMI_RSSI_THRESHOLD_EVENTID.
+ * Indicate the RSSI events to host. Events are indicated when we breach a
+ * thresold value.
+ */
+typedef enum{
+ WMI_RSSI_THRESHOLD1_ABOVE = 0,
+ WMI_RSSI_THRESHOLD2_ABOVE,
+ WMI_RSSI_THRESHOLD3_ABOVE,
+ WMI_RSSI_THRESHOLD4_ABOVE,
+ WMI_RSSI_THRESHOLD5_ABOVE,
+ WMI_RSSI_THRESHOLD6_ABOVE,
+ WMI_RSSI_THRESHOLD1_BELOW,
+ WMI_RSSI_THRESHOLD2_BELOW,
+ WMI_RSSI_THRESHOLD3_BELOW,
+ WMI_RSSI_THRESHOLD4_BELOW,
+ WMI_RSSI_THRESHOLD5_BELOW,
+ WMI_RSSI_THRESHOLD6_BELOW
+}WMI_RSSI_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+ A_INT16 rssi;
+ A_UINT8 range;
+}POSTPACK WMI_RSSI_THRESHOLD_EVENT;
+
+/*
+ * WMI_ERROR_REPORT_EVENTID
+ */
+typedef enum{
+ WMI_TARGET_PM_ERR_FAIL = 0x00000001,
+ WMI_TARGET_KEY_NOT_FOUND = 0x00000002,
+ WMI_TARGET_DECRYPTION_ERR = 0x00000004,
+ WMI_TARGET_BMISS = 0x00000008,
+ WMI_PSDISABLE_NODE_JOIN = 0x00000010,
+ WMI_TARGET_COM_ERR = 0x00000020,
+ WMI_TARGET_FATAL_ERR = 0x00000040
+} WMI_TARGET_ERROR_VAL;
+
+typedef PREPACK struct {
+ A_UINT32 errorVal;
+}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT;
+
+typedef PREPACK struct {
+ A_UINT8 retrys;
+}POSTPACK WMI_TX_RETRY_ERR_EVENT;
+
+typedef enum{
+ WMI_SNR_THRESHOLD1_ABOVE = 1,
+ WMI_SNR_THRESHOLD1_BELOW,
+ WMI_SNR_THRESHOLD2_ABOVE,
+ WMI_SNR_THRESHOLD2_BELOW,
+ WMI_SNR_THRESHOLD3_ABOVE,
+ WMI_SNR_THRESHOLD3_BELOW,
+ WMI_SNR_THRESHOLD4_ABOVE,
+ WMI_SNR_THRESHOLD4_BELOW
+} WMI_SNR_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+ A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */
+ A_UINT8 snr;
+}POSTPACK WMI_SNR_THRESHOLD_EVENT;
+
+typedef enum{
+ WMI_LQ_THRESHOLD1_ABOVE = 1,
+ WMI_LQ_THRESHOLD1_BELOW,
+ WMI_LQ_THRESHOLD2_ABOVE,
+ WMI_LQ_THRESHOLD2_BELOW,
+ WMI_LQ_THRESHOLD3_ABOVE,
+ WMI_LQ_THRESHOLD3_BELOW,
+ WMI_LQ_THRESHOLD4_ABOVE,
+ WMI_LQ_THRESHOLD4_BELOW
+} WMI_LQ_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+ A_INT32 lq;
+ A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */
+}POSTPACK WMI_LQ_THRESHOLD_EVENT;
+/*
+ * WMI_REPORT_ROAM_TBL_EVENTID
+ */
+#define MAX_ROAM_TBL_CAND 5
+
+typedef PREPACK struct {
+ A_INT32 roam_util;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_INT8 rssi;
+ A_INT8 rssidt;
+ A_INT8 last_rssi;
+ A_INT8 util;
+ A_INT8 bias;
+ A_UINT8 reserved; /* For alignment */
+} POSTPACK WMI_BSS_ROAM_INFO;
+
+
+typedef PREPACK struct {
+ A_UINT16 roamMode;
+ A_UINT16 numEntries;
+ WMI_BSS_ROAM_INFO bssRoamInfo[1];
+} POSTPACK WMI_TARGET_ROAM_TBL;
+
+/*
+ * WMI_HCI_EVENT_EVENTID
+ */
+typedef PREPACK struct {
+ A_UINT16 evt_buf_sz; /* HCI event buffer size */
+ A_UINT8 buf[1]; /* HCI event */
+} POSTPACK WMI_HCI_EVENT;
+
+/*
+ * WMI_CAC_EVENTID
+ */
+typedef enum {
+ CAC_INDICATION_ADMISSION = 0x00,
+ CAC_INDICATION_ADMISSION_RESP = 0x01,
+ CAC_INDICATION_DELETE = 0x02,
+ CAC_INDICATION_NO_RESP = 0x03,
+}CAC_INDICATION;
+
+#define WMM_TSPEC_IE_LEN 63
+
+typedef PREPACK struct {
+ A_UINT8 ac;
+ A_UINT8 cac_indication;
+ A_UINT8 statusCode;
+ A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
+}POSTPACK WMI_CAC_EVENT;
+
+/*
+ * WMI_APLIST_EVENTID
+ */
+
+typedef enum {
+ APLIST_VER1 = 1,
+} APLIST_VER;
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT16 channel;
+} POSTPACK WMI_AP_INFO_V1;
+
+typedef PREPACK union {
+ WMI_AP_INFO_V1 apInfoV1;
+} POSTPACK WMI_AP_INFO;
+
+typedef PREPACK struct {
+ A_UINT8 apListVer;
+ A_UINT8 numAP;
+ WMI_AP_INFO apList[1];
+} POSTPACK WMI_APLIST_EVENT;
+
+/*
+ * developer commands
+ */
+
+/*
+ * WMI_SET_BITRATE_CMDID
+ *
+ * Get bit rate cmd uses same definition as set bit rate cmd
+ */
+typedef enum {
+ RATE_AUTO = -1,
+ RATE_1Mb = 0,
+ RATE_2Mb = 1,
+ RATE_5_5Mb = 2,
+ RATE_11Mb = 3,
+ RATE_6Mb = 4,
+ RATE_9Mb = 5,
+ RATE_12Mb = 6,
+ RATE_18Mb = 7,
+ RATE_24Mb = 8,
+ RATE_36Mb = 9,
+ RATE_48Mb = 10,
+ RATE_54Mb = 11,
+ RATE_MCS_0_20 = 12,
+ RATE_MCS_1_20 = 13,
+ RATE_MCS_2_20 = 14,
+ RATE_MCS_3_20 = 15,
+ RATE_MCS_4_20 = 16,
+ RATE_MCS_5_20 = 17,
+ RATE_MCS_6_20 = 18,
+ RATE_MCS_7_20 = 19,
+ RATE_MCS_0_40 = 20,
+ RATE_MCS_1_40 = 21,
+ RATE_MCS_2_40 = 22,
+ RATE_MCS_3_40 = 23,
+ RATE_MCS_4_40 = 24,
+ RATE_MCS_5_40 = 25,
+ RATE_MCS_6_40 = 26,
+ RATE_MCS_7_40 = 27,
+} WMI_BIT_RATE;
+
+typedef PREPACK struct {
+ A_INT8 rateIndex; /* see WMI_BIT_RATE */
+ A_INT8 mgmtRateIndex;
+ A_INT8 ctlRateIndex;
+} POSTPACK WMI_BIT_RATE_CMD;
+
+
+typedef PREPACK struct {
+ A_INT8 rateIndex; /* see WMI_BIT_RATE */
+} POSTPACK WMI_BIT_RATE_REPLY;
+
+
+/*
+ * WMI_SET_FIXRATES_CMDID
+ *
+ * Get fix rates cmd uses same definition as set fix rates cmd
+ */
+#define FIX_RATE_1Mb ((A_UINT32)0x1)
+#define FIX_RATE_2Mb ((A_UINT32)0x2)
+#define FIX_RATE_5_5Mb ((A_UINT32)0x4)
+#define FIX_RATE_11Mb ((A_UINT32)0x8)
+#define FIX_RATE_6Mb ((A_UINT32)0x10)
+#define FIX_RATE_9Mb ((A_UINT32)0x20)
+#define FIX_RATE_12Mb ((A_UINT32)0x40)
+#define FIX_RATE_18Mb ((A_UINT32)0x80)
+#define FIX_RATE_24Mb ((A_UINT32)0x100)
+#define FIX_RATE_36Mb ((A_UINT32)0x200)
+#define FIX_RATE_48Mb ((A_UINT32)0x400)
+#define FIX_RATE_54Mb ((A_UINT32)0x800)
+#define FIX_RATE_MCS_0_20 ((A_UINT32)0x1000)
+#define FIX_RATE_MCS_1_20 ((A_UINT32)0x2000)
+#define FIX_RATE_MCS_2_20 ((A_UINT32)0x4000)
+#define FIX_RATE_MCS_3_20 ((A_UINT32)0x8000)
+#define FIX_RATE_MCS_4_20 ((A_UINT32)0x10000)
+#define FIX_RATE_MCS_5_20 ((A_UINT32)0x20000)
+#define FIX_RATE_MCS_6_20 ((A_UINT32)0x40000)
+#define FIX_RATE_MCS_7_20 ((A_UINT32)0x80000)
+#define FIX_RATE_MCS_0_40 ((A_UINT32)0x100000)
+#define FIX_RATE_MCS_1_40 ((A_UINT32)0x200000)
+#define FIX_RATE_MCS_2_40 ((A_UINT32)0x400000)
+#define FIX_RATE_MCS_3_40 ((A_UINT32)0x800000)
+#define FIX_RATE_MCS_4_40 ((A_UINT32)0x1000000)
+#define FIX_RATE_MCS_5_40 ((A_UINT32)0x2000000)
+#define FIX_RATE_MCS_6_40 ((A_UINT32)0x4000000)
+#define FIX_RATE_MCS_7_40 ((A_UINT32)0x8000000)
+
+typedef PREPACK struct {
+ A_UINT32 fixRateMask; /* see WMI_BIT_RATE */
+} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY;
+
+typedef PREPACK struct {
+ A_UINT8 bEnableMask;
+ A_UINT8 frameType; /*type and subtype*/
+ A_UINT32 frameRateMask; /* see WMI_BIT_RATE */
+} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY;
+
+/*
+ * WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+ RECONN_DO_AUTH = 0x00,
+ RECONN_NOT_AUTH = 0x01
+} WMI_AUTH_MODE;
+
+typedef PREPACK struct {
+ A_UINT8 mode;
+} POSTPACK WMI_SET_AUTH_MODE_CMD;
+
+/*
+ * WMI_SET_REASSOC_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+ REASSOC_DO_DISASSOC = 0x00,
+ REASSOC_DONOT_DISASSOC = 0x01
+} WMI_REASSOC_MODE;
+
+typedef PREPACK struct {
+ A_UINT8 mode;
+}POSTPACK WMI_SET_REASSOC_MODE_CMD;
+
+typedef enum {
+ ROAM_DATA_TIME = 1, /* Get The Roam Time Data */
+} ROAM_DATA_TYPE;
+
+typedef PREPACK struct {
+ A_UINT32 disassoc_time;
+ A_UINT32 no_txrx_time;
+ A_UINT32 assoc_time;
+ A_UINT32 allow_txrx_time;
+ A_UINT8 disassoc_bssid[ATH_MAC_LEN];
+ A_INT8 disassoc_bss_rssi;
+ A_UINT8 assoc_bssid[ATH_MAC_LEN];
+ A_INT8 assoc_bss_rssi;
+} POSTPACK WMI_TARGET_ROAM_TIME;
+
+typedef PREPACK struct {
+ PREPACK union {
+ WMI_TARGET_ROAM_TIME roamTime;
+ } POSTPACK u;
+ A_UINT8 roamDataType ;
+} POSTPACK WMI_TARGET_ROAM_DATA;
+
+typedef enum {
+ WMI_WMM_DISABLED = 0,
+ WMI_WMM_ENABLED
+} WMI_WMM_STATUS;
+
+typedef PREPACK struct {
+ A_UINT8 status;
+}POSTPACK WMI_SET_WMM_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 status;
+}POSTPACK WMI_SET_QOS_SUPP_CMD;
+
+typedef enum {
+ WMI_TXOP_DISABLED = 0,
+ WMI_TXOP_ENABLED
+} WMI_TXOP_CFG;
+
+typedef PREPACK struct {
+ A_UINT8 txopEnable;
+}POSTPACK WMI_SET_WMM_TXOP_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 keepaliveInterval;
+} POSTPACK WMI_SET_KEEPALIVE_CMD;
+
+typedef PREPACK struct {
+ A_BOOL configured;
+ A_UINT8 keepaliveInterval;
+} POSTPACK WMI_GET_KEEPALIVE_CMD;
+
+/*
+ * Add Application specified IE to a management frame
+ */
+#define WMI_MAX_IE_LEN 255
+
+typedef PREPACK struct {
+ A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */
+ A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */
+ A_UINT8 ieInfo[1];
+} POSTPACK WMI_SET_APPIE_CMD;
+
+/*
+ * Notify the WSC registration status to the target
+ */
+#define WSC_REG_ACTIVE 1
+#define WSC_REG_INACTIVE 0
+/* Generic Hal Interface for setting hal paramters. */
+/* Add new Set HAL Param cmdIds here for newer params */
+typedef enum {
+ WHAL_SETCABTO_CMDID = 1,
+}WHAL_CMDID;
+
+typedef PREPACK struct {
+ A_UINT8 cabTimeOut;
+} POSTPACK WHAL_SETCABTO_PARAM;
+
+typedef PREPACK struct {
+ A_UINT8 whalCmdId;
+ A_UINT8 data[1];
+} POSTPACK WHAL_PARAMCMD;
+
+
+#define WOW_MAX_FILTER_LISTS 1 /*4*/
+#define WOW_MAX_FILTERS_PER_LIST 4
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+#define MAC_MAX_FILTERS_PER_LIST 4
+
+typedef PREPACK struct {
+ A_UINT8 wow_valid_filter;
+ A_UINT8 wow_filter_id;
+ A_UINT8 wow_filter_size;
+ A_UINT8 wow_filter_offset;
+ A_UINT8 wow_filter_mask[WOW_MASK_SIZE];
+ A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE];
+} POSTPACK WOW_FILTER;
+
+
+typedef PREPACK struct {
+ A_UINT8 wow_valid_list;
+ A_UINT8 wow_list_id;
+ A_UINT8 wow_num_filters;
+ A_UINT8 wow_total_list_size;
+ WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST];
+} POSTPACK WOW_FILTER_LIST;
+
+typedef PREPACK struct {
+ A_UINT8 valid_filter;
+ A_UINT8 mac_addr[ATH_MAC_LEN];
+} POSTPACK MAC_FILTER;
+
+
+typedef PREPACK struct {
+ A_UINT8 total_list_size;
+ A_UINT8 enable;
+ MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST];
+} POSTPACK MAC_FILTER_LIST;
+
+#define MAX_IP_ADDRS 2
+typedef PREPACK struct {
+ A_UINT32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */
+} POSTPACK WMI_SET_IP_CMD;
+
+typedef PREPACK struct {
+ A_BOOL awake;
+ A_BOOL asleep;
+} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD;
+
+typedef enum {
+ WOW_FILTER_SSID = 0x1
+} WMI_WOW_FILTER;
+
+typedef PREPACK struct {
+ A_BOOL enable_wow;
+ WMI_WOW_FILTER filter;
+} POSTPACK WMI_SET_WOW_MODE_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 filter_list_id;
+} POSTPACK WMI_GET_WOW_LIST_CMD;
+
+/*
+ * WMI_GET_WOW_LIST_CMD reply
+ */
+typedef PREPACK struct {
+ A_UINT8 num_filters; /* number of patterns in reply */
+ A_UINT8 this_filter_num; /* this is filter # x of total num_filters */
+ A_UINT8 wow_mode;
+ A_UINT8 host_mode;
+ WOW_FILTER wow_filters[1];
+} POSTPACK WMI_GET_WOW_LIST_REPLY;
+
+typedef PREPACK struct {
+ A_UINT8 filter_list_id;
+ A_UINT8 filter_size;
+ A_UINT8 filter_offset;
+ A_UINT8 filter[1];
+} POSTPACK WMI_ADD_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+ A_UINT16 filter_list_id;
+ A_UINT16 filter_id;
+} POSTPACK WMI_DEL_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_SET_MAC_ADDRESS_CMD;
+
+/*
+ * WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define WMI_AKMP_MULTI_PMKID_EN 0x000001
+
+typedef PREPACK struct {
+ A_UINT32 akmpInfo;
+} POSTPACK WMI_SET_AKMP_PARAMS_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_PMKID;
+
+/*
+ * WMI_SET_PMKID_LIST_CMD
+ */
+#define WMI_MAX_PMKID_CACHE 8
+
+typedef PREPACK struct {
+ A_UINT32 numPMKID;
+ WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
+} POSTPACK WMI_SET_PMKID_LIST_CMD;
+
+/*
+ * WMI_GET_PMKID_LIST_CMD Reply
+ * Following the Number of PMKIDs is the list of PMKIDs
+ */
+typedef PREPACK struct {
+ A_UINT32 numPMKID;
+ A_UINT8 bssidList[ATH_MAC_LEN][1];
+ WMI_PMKID pmkidList[1];
+} POSTPACK WMI_PMKID_LIST_REPLY;
+
+typedef PREPACK struct {
+ A_UINT16 oldChannel;
+ A_UINT32 newChannel;
+} POSTPACK WMI_CHANNEL_CHANGE_EVENT;
+
+typedef PREPACK struct {
+ A_UINT32 version;
+} POSTPACK WMI_WLAN_VERSION_EVENT;
+
+
+/* WMI_ADDBA_REQ_EVENTID */
+typedef PREPACK struct {
+ A_UINT8 tid;
+ A_UINT8 win_sz;
+ A_UINT16 st_seq_no;
+ A_UINT8 status; /* f/w response for ADDBA Req; OK(0) or failure(!=0) */
+} POSTPACK WMI_ADDBA_REQ_EVENT;
+
+/* WMI_ADDBA_RESP_EVENTID */
+typedef PREPACK struct {
+ A_UINT8 tid;
+ A_UINT8 status; /* OK(0), failure (!=0) */
+ A_UINT16 amsdu_sz; /* Three values: Not supported(0), 3839, 8k */
+} POSTPACK WMI_ADDBA_RESP_EVENT;
+
+/* WMI_DELBA_EVENTID
+ * f/w received a DELBA for peer and processed it.
+ * Host is notified of this
+ */
+typedef PREPACK struct {
+ A_UINT8 tid;
+ A_UINT8 is_peer_initiator;
+ A_UINT16 reason_code;
+} POSTPACK WMI_DELBA_EVENT;
+
+
+#ifdef WAPI_ENABLE
+#define WAPI_REKEY_UCAST 1
+#define WAPI_REKEY_MCAST 2
+typedef PREPACK struct {
+ A_UINT8 type;
+ A_UINT8 macAddr[ATH_MAC_LEN];
+} POSTPACK WMI_WAPIREKEY_EVENT;
+#endif
+
+
+/* WMI_ALLOW_AGGR_CMDID
+ * Configures tid's to allow ADDBA negotiations
+ * on each tid, in each direction
+ */
+typedef PREPACK struct {
+ A_UINT16 tx_allow_aggr; /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/
+ A_UINT16 rx_allow_aggr; /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/
+} POSTPACK WMI_ALLOW_AGGR_CMD;
+
+/* WMI_ADDBA_REQ_CMDID
+ * f/w starts performing ADDBA negotiations with peer
+ * on the given tid
+ */
+typedef PREPACK struct {
+ A_UINT8 tid;
+} POSTPACK WMI_ADDBA_REQ_CMD;
+
+/* WMI_DELBA_REQ_CMDID
+ * f/w would teardown BA with peer.
+ * is_send_initiator indicates if it's or tx or rx side
+ */
+typedef PREPACK struct {
+ A_UINT8 tid;
+ A_UINT8 is_sender_initiator;
+
+} POSTPACK WMI_DELBA_REQ_CMD;
+
+#define PEER_NODE_JOIN_EVENT 0x00
+#define PEER_NODE_LEAVE_EVENT 0x01
+#define PEER_FIRST_NODE_JOIN_EVENT 0x10
+#define PEER_LAST_NODE_LEAVE_EVENT 0x11
+typedef PREPACK struct {
+ A_UINT8 eventCode;
+ A_UINT8 peerMacAddr[ATH_MAC_LEN];
+} POSTPACK WMI_PEER_NODE_EVENT;
+
+#define IEEE80211_FRAME_TYPE_MGT 0x00
+#define IEEE80211_FRAME_TYPE_CTL 0x04
+
+/*
+ * Transmit complete event data structure(s)
+ */
+
+
+typedef PREPACK struct {
+#define TX_COMPLETE_STATUS_SUCCESS 0
+#define TX_COMPLETE_STATUS_RETRIES 1
+#define TX_COMPLETE_STATUS_NOLINK 2
+#define TX_COMPLETE_STATUS_TIMEOUT 3
+#define TX_COMPLETE_STATUS_OTHER 4
+
+ A_UINT8 status; /* one of TX_COMPLETE_STATUS_... */
+ A_UINT8 pktID; /* packet ID to identify parent packet */
+ A_UINT8 rateIdx; /* rate index on successful transmission */
+ A_UINT8 ackFailures; /* number of ACK failures in tx attempt */
+#if 0 /* optional params currently ommitted. */
+ A_UINT32 queueDelay; // usec delay measured Tx Start time - host delivery time
+ A_UINT32 mediaDelay; // usec delay measured ACK rx time - host delivery time
+#endif
+} POSTPACK TX_COMPLETE_MSG_V1; /* version 1 of tx complete msg */
+
+typedef PREPACK struct {
+ A_UINT8 numMessages; /* number of tx comp msgs following this struct */
+ A_UINT8 msgLen; /* length in bytes for each individual msg following this struct */
+ A_UINT8 msgType; /* version of tx complete msg data following this struct */
+ A_UINT8 reserved; /* individual messages follow this header */
+} POSTPACK WMI_TX_COMPLETE_EVENT;
+
+#define WMI_TXCOMPLETE_VERSION_1 (0x01)
+
+
+/*
+ * ------- AP Mode definitions --------------
+ */
+
+/*
+ * !!! Warning !!!
+ * -Changing the following values needs compilation of both driver and firmware
+ */
+#ifdef AR6002_REV2
+#define AP_MAX_NUM_STA 4
+#else
+#define AP_MAX_NUM_STA 8
+#endif
+#define AP_ACL_SIZE 10
+#define IEEE80211_MAX_IE 256
+#define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */
+#define DEF_AP_COUNTRY_CODE "US "
+#define DEF_AP_WMODE_G WMI_11G_MODE
+#define DEF_AP_WMODE_AG WMI_11AG_MODE
+#define DEF_AP_DTIM 5
+#define DEF_BEACON_INTERVAL 100
+
+/* AP mode disconnect reasons */
+#define AP_DISCONNECT_STA_LEFT 101
+#define AP_DISCONNECT_FROM_HOST 102
+#define AP_DISCONNECT_COMM_TIMEOUT 103
+
+/*
+ * Used with WMI_AP_HIDDEN_SSID_CMDID
+ */
+#define HIDDEN_SSID_FALSE 0
+#define HIDDEN_SSID_TRUE 1
+typedef PREPACK struct {
+ A_UINT8 hidden_ssid;
+} POSTPACK WMI_AP_HIDDEN_SSID_CMD;
+
+/*
+ * Used with WMI_AP_ACL_POLICY_CMDID
+ */
+#define AP_ACL_DISABLE 0x00
+#define AP_ACL_ALLOW_MAC 0x01
+#define AP_ACL_DENY_MAC 0x02
+#define AP_ACL_RETAIN_LIST_MASK 0x80
+typedef PREPACK struct {
+ A_UINT8 policy;
+} POSTPACK WMI_AP_ACL_POLICY_CMD;
+
+/*
+ * Used with WMI_AP_ACL_MAC_LIST_CMDID
+ */
+#define ADD_MAC_ADDR 1
+#define DEL_MAC_ADDR 2
+typedef PREPACK struct {
+ A_UINT8 action;
+ A_UINT8 index;
+ A_UINT8 mac[ATH_MAC_LEN];
+ A_UINT8 wildcard;
+} POSTPACK WMI_AP_ACL_MAC_CMD;
+
+typedef PREPACK struct {
+ A_UINT16 index;
+ A_UINT8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN];
+ A_UINT8 wildcard[AP_ACL_SIZE];
+ A_UINT8 policy;
+} POSTPACK WMI_AP_ACL;
+
+/*
+ * Used with WMI_AP_SET_NUM_STA_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 num_sta;
+} POSTPACK WMI_AP_SET_NUM_STA_CMD;
+
+/*
+ * Used with WMI_AP_SET_MLME_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 mac[ATH_MAC_LEN];
+ A_UINT16 reason; /* 802.11 reason code */
+ A_UINT8 cmd; /* operation to perform */
+#define WMI_AP_MLME_ASSOC 1 /* associate station */
+#define WMI_AP_DISASSOC 2 /* disassociate station */
+#define WMI_AP_DEAUTH 3 /* deauthenticate station */
+#define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */
+#define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */
+} POSTPACK WMI_AP_SET_MLME_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 period;
+} POSTPACK WMI_AP_CONN_INACT_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 period_min;
+ A_UINT32 dwell_ms;
+} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD;
+
+typedef PREPACK struct {
+ A_BOOL flag;
+ A_UINT16 aid;
+} POSTPACK WMI_AP_SET_PVB_CMD;
+
+#define WMI_DISABLE_REGULATORY_CODE "FF"
+
+typedef PREPACK struct {
+ A_UCHAR countryCode[3];
+} POSTPACK WMI_AP_SET_COUNTRY_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 dtim;
+} POSTPACK WMI_AP_SET_DTIM_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 band; /* specifies which band to apply these values */
+ A_UINT8 enable; /* allows 11n to be disabled on a per band basis */
+ A_UINT8 chan_width_40M_supported;
+ A_UINT8 short_GI_20MHz;
+ A_UINT8 short_GI_40MHz;
+ A_UINT8 intolerance_40MHz;
+ A_UINT8 max_ampdu_len_exp;
+} POSTPACK WMI_SET_HT_CAP_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 sta_chan_width;
+} POSTPACK WMI_SET_HT_OP_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 rateMasks[8];
+} POSTPACK WMI_SET_TX_SELECT_RATES_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 sgiMask;
+ A_UINT8 sgiPERThreshold;
+} POSTPACK WMI_SET_TX_SGI_PARAM_CMD;
+
+
+typedef PREPACK struct {
+ A_UINT32 rateField; /* 1 bit per rate corresponding to index */
+ A_UINT8 id;
+ A_UINT8 shortTrys;
+ A_UINT8 longTrys;
+ A_UINT8 reserved; /* padding */
+} POSTPACK WMI_SET_RATE_POLICY_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 metaVersion; /* version of meta data for rx packets <0 = default> (0-7 = valid) */
+ A_UINT8 dot11Hdr; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 <default> */
+ A_UINT8 defragOnHost; /* 1 == defragmentation is performed by host, 0 == performed by target <default> */
+ A_UINT8 reserved[1]; /* alignment */
+} POSTPACK WMI_RX_FRAME_FORMAT_CMD;
+
+
+typedef PREPACK struct {
+ A_UINT8 enable; // 1 == device operates in thin mode , 0 == normal mode <default> */
+ A_UINT8 reserved[3];
+} POSTPACK WMI_SET_THIN_MODE_CMD;
+
+/* AP mode events */
+/* WMI_PS_POLL_EVENT */
+typedef PREPACK struct {
+ A_UINT16 aid;
+} POSTPACK WMI_PSPOLL_EVENT;
+
+typedef PREPACK struct {
+ A_UINT32 tx_bytes;
+ A_UINT32 tx_pkts;
+ A_UINT32 tx_error;
+ A_UINT32 tx_discard;
+ A_UINT32 rx_bytes;
+ A_UINT32 rx_pkts;
+ A_UINT32 rx_error;
+ A_UINT32 rx_discard;
+ A_UINT32 aid;
+} POSTPACK WMI_PER_STA_STAT;
+
+#define AP_GET_STATS 0
+#define AP_CLEAR_STATS 1
+
+typedef PREPACK struct {
+ A_UINT32 action;
+ WMI_PER_STA_STAT sta[AP_MAX_NUM_STA+1];
+} POSTPACK WMI_AP_MODE_STAT;
+#define WMI_AP_MODE_STAT_SIZE(numSta) (sizeof(A_UINT32) + ((numSta + 1) * sizeof(WMI_PER_STA_STAT)))
+
+#define AP_11BG_RATESET1 1
+#define AP_11BG_RATESET2 2
+#define DEF_AP_11BG_RATESET AP_11BG_RATESET1
+typedef PREPACK struct {
+ A_UINT8 rateset;
+} POSTPACK WMI_AP_SET_11BG_RATESET_CMD;
+/*
+ * End of AP mode definitions
+ */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wmi_api.h b/drivers/net/wireless/ath6kl/include/wmi_api.h
new file mode 100644
index 000000000000..446c56eab0ed
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmi_api.h
@@ -0,0 +1,435 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_api.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the definitions for the Wireless Module Interface (WMI).
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _WMI_API_H_
+#define _WMI_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /* WMI converts a dix frame with an ethernet payload (up to 1500 bytes)
+ * to an 802.3 frame (adds SNAP header) and adds on a WMI data header */
+#define WMI_MAX_TX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+ /* A normal WMI data frame */
+#define WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+ /* An AMSDU frame */
+#define WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH (4096 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR))
+
+/*
+ * IP QoS Field definitions according to 802.1p
+ */
+#define BEST_EFFORT_PRI 0
+#define BACKGROUND_PRI 1
+#define EXCELLENT_EFFORT_PRI 3
+#define CONTROLLED_LOAD_PRI 4
+#define VIDEO_PRI 5
+#define VOICE_PRI 6
+#define NETWORK_CONTROL_PRI 7
+#define MAX_NUM_PRI 8
+
+#define UNDEFINED_PRI (0xff)
+
+#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
+
+#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+
+typedef enum {
+ ATHEROS_COMPLIANCE = 0x1,
+}TSPEC_PARAM_COMPLIANCE;
+
+struct wmi_t;
+
+void *wmi_init(void *devt);
+
+void wmi_qos_state_init(struct wmi_t *wmip);
+void wmi_shutdown(struct wmi_t *wmip);
+HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip);
+void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid);
+A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8);
+A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData, WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS);
+A_STATUS wmi_dot3_2_dix(void *osbuf);
+
+A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode);
+
+A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_syncpoint(struct wmi_t *wmip);
+A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled);
+
+A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri);
+
+A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
+void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
+void wmi_free_allnodes(struct wmi_t *wmip);
+bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+
+
+typedef enum {
+ NO_SYNC_WMIFLAG = 0,
+ SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */
+ SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */
+ SYNC_BOTH_WMIFLAG,
+ END_WMIFLAG /* end marker */
+} WMI_SYNC_FLAG;
+
+A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG flag);
+
+A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
+ NETWORK_TYPE netType,
+ DOT11_AUTH_MODE dot11AuthMode,
+ AUTH_MODE authMode,
+ CRYPTO_TYPE pairwiseCrypto,
+ A_UINT8 pairwiseCryptoLen,
+ CRYPTO_TYPE groupCrypto,
+ A_UINT8 groupCryptoLen,
+ int ssidLength,
+ A_UCHAR *ssid,
+ A_UINT8 *bssid,
+ A_UINT16 channel,
+ A_UINT32 ctrl_flags);
+
+A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
+ A_UINT8 *bssid,
+ A_UINT16 channel);
+A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
+A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
+A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+ A_BOOL forceFgScan, A_BOOL isLegacy,
+ A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
+ A_INT8 numChan, A_UINT16 *channelList);
+A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+ A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+ A_UINT16 minact_chdw_msec,
+ A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec,
+ A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+ A_UINT32 max_dfsch_act_time,
+ A_UINT16 maxact_scan_per_ssid);
+A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask);
+A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+ A_UINT8 ssidLength, A_UCHAR *ssid);
+A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
+A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
+A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+ A_UINT8 ieLen, A_UINT8 *ieInfo);
+A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
+A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+ A_UINT16 atim_windows, A_UINT16 timeout_value);
+A_STATUS wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time,
+ A_UINT32 ps_period, A_UINT8 sleep_period);
+A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+ A_UINT16 psPollNum, A_UINT16 dtimPolicy,
+ A_UINT16 wakup_tx_policy, A_UINT16 num_tx_to_wakeup,
+ A_UINT16 ps_fail_event_policy);
+A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
+A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
+A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
+A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID);
+A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask);
+A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate);
+A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
+A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate);
+A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+ WMI_PHY_MODE mode, A_INT8 numChan,
+ A_UINT16 *channelList);
+
+A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip,
+ WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip);
+A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip,
+ WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
+A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold);
+A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy);
+
+A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
+
+A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
+ A_UINT32 source);
+
+A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+ A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+ A_UINT32 valid);
+
+A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
+ CRYPTO_TYPE keyType, A_UINT8 keyUsage,
+ A_UINT8 keyLength,A_UINT8 *keyRSC,
+ A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac,
+ WMI_SYNC_FLAG sync_flag);
+A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
+A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
+A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
+A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+ WMI_SET_AKMP_PARAMS_CMD *akmpParams);
+A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+ WMI_SET_PMKID_LIST_CMD *pmkInfo);
+A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
+A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
+A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
+A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
+A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
+A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+ A_BOOL set);
+A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac, A_UINT16 txop,
+ A_UINT8 eCWmin, A_UINT8 eCWmax,
+ A_UINT8 aifsn);
+A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+ A_UINT8 trafficClass, A_UINT8 maxRetries,
+ A_UINT8 enableNotify);
+
+void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
+
+A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
+A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+ A_UINT8 size);
+A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+ WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+ A_UINT8 size);
+
+A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
+A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+ A_UINT8 frmType,
+ A_UINT8 *dstMacAddr,
+ A_UINT8 *bssid,
+ A_UINT16 optIEDataLen,
+ A_UINT8 *optIEData);
+
+A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
+A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
+A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
+A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority);
+A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
+A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len);
+#endif
+
+A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status);
+A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
+
+A_STATUS wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *cmd);
+
+A_STATUS wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_A2DP_CONFIG_CMD* cmd);
+
+
+A_STATUS wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD* cmd);
+
+A_STATUS wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd);
+
+A_STATUS wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
+ WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd);
+
+A_STATUS wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd);
+
+A_STATUS wmi_get_btcoex_stats_cmd(struct wmi_t * wmip);
+
+/*
+ * This function is used to configure the fix rates mask to the target.
+ */
+A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask);
+A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_qos_supp_cmd(struct wmi_t *wmip,A_UINT8 status);
+A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
+A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
+A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode);
+
+A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip);
+A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval);
+
+A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType,
+ A_UINT8 ieLen,A_UINT8 *ieInfo);
+
+A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen);
+
+A_INT32 wmi_get_rate(A_INT8 rateindex);
+
+A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd);
+
+/*Wake on Wireless WMI commands*/
+A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
+A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
+A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size);
+A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_DEL_WOW_PATTERN_CMD *cmd);
+A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
+
+A_STATUS
+wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer);
+
+A_STATUS
+wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4);
+
+A_STATUS
+wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4);
+
+A_STATUS
+wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable);
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID);
+
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss);
+
+void
+wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge);
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins);
+A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr);
+A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip);
+A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip);
+A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip);
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+#ifdef OS_ROAM_MANAGEMENT
+void wmi_scan_indication (struct wmi_t *wmip);
+#endif
+
+A_STATUS
+wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd);
+
+bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id);
+A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss);
+
+
+/*
+ * AP mode
+ */
+A_STATUS
+wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p);
+
+A_STATUS
+wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid);
+
+A_STATUS
+wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta);
+
+A_STATUS
+wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy);
+
+A_STATUS
+wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a);
+
+A_UINT8
+acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl);
+
+A_STATUS
+wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason);
+
+A_STATUS
+wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag);
+
+A_STATUS
+wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period);
+
+A_STATUS
+wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell);
+
+A_STATUS
+wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim);
+
+A_STATUS
+wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset);
+
+A_STATUS
+wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd);
+
+A_STATUS
+wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width);
+
+A_STATUS
+wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz);
+
+A_STATUS
+wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray);
+
+A_STATUS
+wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid);
+
+A_STATUS
+wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink);
+
+A_STATUS
+wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask);
+
+A_STATUS
+wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion, A_BOOL rxDot11Hdr, A_BOOL defragOnHost);
+
+A_STATUS
+wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode);
+
+A_STATUS
+wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence);
+
+A_STATUS
+wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk);
+
+A_UINT16
+wmi_ieee2freq (int chan);
+
+A_UINT32
+wmi_freq2ieee (A_UINT16 freq);
+
+bss_t *
+wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+ A_UINT32 ssidLength,
+ A_UINT32 dot11AuthMode, A_UINT32 authMode,
+ A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_API_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wmi_thin.h b/drivers/net/wireless/ath6kl/include/wmi_thin.h
new file mode 100644
index 000000000000..1e300d1c6563
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmi_thin.h
@@ -0,0 +1,343 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_thin.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI). It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to WMI commands
+ * belongs to the host driver and the WM is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_THIN_H_
+#define _WMI_THIN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+ WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START
+ WMI_THIN_SET_MIB_CMDID,
+ WMI_THIN_GET_MIB_CMDID,
+ WMI_THIN_JOIN_CMDID,
+ /* add new CMDID's here */
+ WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END
+} WMI_THIN_COMMAND_ID;
+
+typedef enum{
+ TEMPLATE_FRM_FIRST = 0,
+ TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST,
+ TEMPLATE_FRM_BEACON,
+ TEMPLATE_FRM_PROBE_RESP,
+ TEMPLATE_FRM_NULL,
+ TEMPLATE_FRM_QOS_NULL,
+ TEMPLATE_FRM_PSPOLL,
+ TEMPLATE_FRM_MAX
+}WMI_TEMPLATE_FRM_TYPE;
+
+/* TEMPLATE_FRM_LEN... represent the maximum allowable
+ * data lengths (bytes) for each frame type */
+#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */
+#define TEMPLATE_FRM_LEN_BEACON (256)
+#define TEMPLATE_FRM_LEN_PROBE_RESP (256)
+#define TEMPLATE_FRM_LEN_NULL (32)
+#define TEMPLATE_FRM_LEN_QOS_NULL (32)
+#define TEMPLATE_FRM_LEN_PSPOLL (32)
+#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \
+ TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL)
+
+
+/* MAC Header Build Rules */
+/* These values allow the host to configure the
+ * target code that is responsible for constructing
+ * the MAC header. In cases where the MAC header
+ * is provided by the host framework, the target
+ * has a diminished responsibility over what fields
+ * it must write. This will vary from framework to framework.
+ * Symbian requires different behavior from MAC80211 which
+ * requires different behavior from MS Native Wifi. */
+#define WMI_WRT_VER_TYPE 0x00000001
+#define WMI_WRT_DURATION 0x00000002
+#define WMI_WRT_DIRECTION 0x00000004
+#define WMI_WRT_POWER 0x00000008
+#define WMI_WRT_WEP 0x00000010
+#define WMI_WRT_MORE 0x00000020
+#define WMI_WRT_BSSID 0x00000040
+#define WMI_WRT_QOS 0x00000080
+#define WMI_WRT_SEQNO 0x00000100
+#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */
+#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \
+ WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \
+ WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX)
+
+/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for
+ * TX Complete messages the will come from the Target. these messages are
+ * disabled by default but can be enabled using this structure and the
+ * WMI_THIN_CONFIG_CMDID. */
+typedef PREPACK struct {
+ A_UINT8 version; /* the versioned type of messages to use or 0 to disable */
+ A_UINT8 countThreshold; /* msg count threshold triggering a tx complete message */
+ A_UINT16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */
+} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE;
+
+/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames
+ * that have decryption errors. The default behavior is to discard the frame
+ * without notification. Alternately, the MAC Header is forwarded to the host
+ * with the failed status. */
+typedef PREPACK struct {
+ A_UINT8 enable; /* 1 == send decrypt errors to the host, 0 == don't */
+ A_UINT8 reserved[3]; /* align padding */
+} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR;
+
+/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted
+ * frames that require partial MAC header construction. These rules
+ * are used by the target to indicate which fields need to be written. */
+typedef PREPACK struct {
+ A_UINT32 rules; /* combination of WMI_WRT_... values */
+} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
+
+/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
+ * frames as to which frames should get forwarded to the host and which
+ * should get processed internally. */
+typedef PREPACK struct {
+ A_UINT32 rules; /* combination of WMI_FILT_... values */
+} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
+
+/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
+ * WMI_THIN_CONFIG_... structures. The actual combination is indicated
+ * by the value of cfgField. Each bit in this field corresponds to
+ * one of the above structures. */
+typedef PREPACK struct {
+#define WMI_THIN_CFG_TXCOMP 0x00000001
+#define WMI_THIN_CFG_DECRYPT 0x00000002
+#define WMI_THIN_CFG_MAC_RULES 0x00000004
+#define WMI_THIN_CFG_FILTER_RULES 0x00000008
+ A_UINT32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */
+ A_UINT16 length; /* length in bytes of appended sub-commands */
+ A_UINT8 reserved[2]; /* align padding */
+} POSTPACK WMI_THIN_CONFIG_CMD;
+
+/* MIB Access Identifiers tailored for Symbian. */
+enum {
+ MIB_ID_STA_MAC = 1, // [READONLY]
+ MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED]
+ MIB_ID_SLOT_TIME, // [READ/WRITE]
+ MIB_ID_RTS_THRESHOLD, // [READ/WRITE]
+ MIB_ID_CTS_TO_SELF, // [READ/WRITE]
+ MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY]
+ MIB_ID_RXFRAME_FILTER, // [READ/WRITE]
+ MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY]
+ MIB_ID_BEACON_FILTER, // [READ/WRITE]
+ MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY]
+ MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY]
+ MIB_ID_HT_CAP, // [NOT IMPLEMENTED]
+ MIB_ID_HT_OP, // [NOT IMPLEMENTED]
+ MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED]
+ MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED]
+ MIB_ID_PREAMBLE, // [READ/WRITE]
+ /*MIB_ID_GROUP_ADDR_TABLE,*/
+ /*MIB_ID_WEP_DEFAULT_KEY_ID */
+ /*MIB_ID_TX_POWER */
+ /*MIB_ID_ARP_IP_TABLE */
+ /*MIB_ID_SLEEP_MODE */
+ /*MIB_ID_WAKE_INTERVAL*/
+ /*MIB_ID_STAT_TABLE*/
+ /*MIB_ID_IBSS_PWR_SAVE*/
+ /*MIB_ID_COUNTERS_TABLE*/
+ /*MIB_ID_ETHERTYPE_FILTER*/
+ /*MIB_ID_BC_UDP_FILTER*/
+
+};
+
+typedef PREPACK struct {
+ A_UINT8 addr[ATH_MAC_LEN];
+} POSTPACK WMI_THIN_MIB_STA_MAC;
+
+typedef PREPACK struct {
+ A_UINT32 time; // units == msec
+} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
+
+typedef PREPACK struct {
+ A_UINT8 enable; //1 = on, 0 = off
+} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
+
+typedef PREPACK struct {
+ A_UINT32 time; // units == usec
+} POSTPACK WMI_THIN_MIB_SLOT_TIME;
+
+typedef PREPACK struct {
+ A_UINT16 length; //units == bytes
+} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD;
+
+typedef PREPACK struct {
+ A_UINT8 type; // type of frame
+ A_UINT8 rate; // tx rate to be used (one of WMI_BIT_RATE)
+ A_UINT16 length; // num bytes following this structure as the template data
+} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME;
+
+typedef PREPACK struct {
+#define FRAME_FILTER_PROMISCUOUS 0x00000001
+#define FRAME_FILTER_BSSID 0x00000002
+ A_UINT32 filterMask;
+} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
+
+
+#define IE_FILTER_TREATMENT_CHANGE 1
+#define IE_FILTER_TREATMENT_APPEAR 2
+
+typedef PREPACK struct {
+ A_UINT8 ie;
+ A_UINT8 treatment;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE;
+
+typedef PREPACK struct {
+ A_UINT8 ie;
+ A_UINT8 treatment;
+ A_UINT8 oui[3];
+ A_UINT8 type;
+ A_UINT16 version;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI;
+
+typedef PREPACK struct {
+ A_UINT16 numElements;
+ A_UINT8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4
+ A_UINT8 reserved;
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER;
+
+typedef PREPACK struct {
+ A_UINT32 count; /* num beacons between deliveries */
+ A_UINT8 enable;
+ A_UINT8 reserved[3];
+} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
+
+typedef PREPACK struct {
+ A_UINT32 count; /* num consec lost beacons after which send event */
+} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
+
+typedef PREPACK struct {
+ A_UINT8 rssi; /* the low threshold which can trigger an event warning */
+ A_UINT8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */
+ A_UINT8 count; /* the sample count of consecutive frames necessary to trigger an event. */
+ A_UINT8 reserved[1]; /* padding */
+} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD;
+
+
+typedef PREPACK struct {
+ A_UINT32 cap;
+ A_UINT32 rxRateField;
+ A_UINT32 beamForming;
+ A_UINT8 addr[ATH_MAC_LEN];
+ A_UINT8 enable;
+ A_UINT8 stbc;
+ A_UINT8 maxAMPDU;
+ A_UINT8 msduSpacing;
+ A_UINT8 mcsFeedback;
+ A_UINT8 antennaSelCap;
+} POSTPACK WMI_THIN_MIB_HT_CAP;
+
+typedef PREPACK struct {
+ A_UINT32 infoField;
+ A_UINT32 basicRateField;
+ A_UINT8 protection;
+ A_UINT8 secondChanneloffset;
+ A_UINT8 channelWidth;
+ A_UINT8 reserved;
+} POSTPACK WMI_THIN_MIB_HT_OP;
+
+typedef PREPACK struct {
+#define SECOND_BEACON_PRIMARY 1
+#define SECOND_BEACON_EITHER 2
+#define SECOND_BEACON_SECONDARY 3
+ A_UINT8 cfg;
+ A_UINT8 reserved[3]; /* padding */
+} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON;
+
+typedef PREPACK struct {
+ A_UINT8 txTIDField;
+ A_UINT8 rxTIDField;
+ A_UINT8 reserved[2]; /* padding */
+} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK;
+
+typedef PREPACK struct {
+ A_UINT8 enableLong; // 1 == long preamble, 0 == short preamble
+ A_UINT8 reserved[3];
+} POSTPACK WMI_THIN_MIB_PREAMBLE;
+
+typedef PREPACK struct {
+ A_UINT16 length; /* the length in bytes of the appended MIB data */
+ A_UINT8 mibID; /* the ID of the MIB element being set */
+ A_UINT8 reserved; /* align padding */
+} POSTPACK WMI_THIN_SET_MIB_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 mibID; /* the ID of the MIB element being set */
+ A_UINT8 reserved[3]; /* align padding */
+} POSTPACK WMI_THIN_GET_MIB_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 basicRateMask; /* bit mask of basic rates */
+ A_UINT32 beaconIntval; /* TUs */
+ A_UINT16 atimWindow; /* TUs */
+ A_UINT16 channel; /* frequency in Mhz */
+ A_UINT8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
+ A_UINT8 ssidLength; /* 0 - 32 */
+ A_UINT8 probe; /* != 0 : issue probe req at start */
+ A_UINT8 reserved; /* alignment */
+ A_UCHAR ssid[WMI_MAX_SSID_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_THIN_JOIN_CMD;
+
+typedef PREPACK struct {
+ A_UINT16 dtim; /* dtim interval in num beacons */
+ A_UINT16 aid; /* 80211 AID from Assoc resp */
+} POSTPACK WMI_THIN_POST_ASSOC_CMD;
+
+typedef enum {
+ WMI_THIN_EVENTID_RESERVED_START = 0x8000,
+ WMI_THIN_GET_MIB_EVENTID,
+ WMI_THIN_JOIN_EVENTID,
+
+ /* Add new THIN EVENTID's here */
+ WMI_THIN_EVENTID_RESERVED_END = 0x8fff
+} WMI_THIN_EVENT_ID;
+
+/* Possible values for WMI_THIN_JOIN_EVENT.result */
+typedef enum {
+ WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network
+ WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason
+ WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit
+ WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param.
+}WMI_THIN_JOIN_RESULT;
+
+typedef PREPACK struct {
+ A_UINT8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */
+ A_UINT8 reserved[3]; /* alignment */
+} POSTPACK WMI_THIN_JOIN_EVENT;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_THIN_H_ */
diff --git a/drivers/net/wireless/ath6kl/include/wmix.h b/drivers/net/wireless/ath6kl/include/wmix.h
new file mode 100644
index 000000000000..7db5560f41f0
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/include/wmix.h
@@ -0,0 +1,275 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmix.h" company="Atheros">
+// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+/*
+ * This file contains extensions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI). It includes definitions of all
+ * extended commands and events. Extensions include useful commands
+ * that are not directly related to wireless activities. They may
+ * be hardware-specific, and they might not be supported on all
+ * implementations.
+ *
+ * Extended WMIX commands are encapsulated in a WMI message with
+ * cmd=WMI_EXTENSION_CMD.
+ */
+
+#ifndef _WMIX_H_
+#define _WMIX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "dbglog.h"
+
+/*
+ * Extended WMI commands are those that are needed during wireless
+ * operation, but which are not really wireless commands. This allows,
+ * for instance, platform-specific commands. Extended WMI commands are
+ * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
+ * Extended WMI events are similarly embedded in a WMI event message with
+ * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
+ */
+typedef PREPACK struct {
+ A_UINT32 commandId;
+} POSTPACK WMIX_CMD_HDR;
+
+typedef enum {
+ WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
+ WMIX_DSETDATA_REPLY_CMDID,
+ WMIX_GPIO_OUTPUT_SET_CMDID,
+ WMIX_GPIO_INPUT_GET_CMDID,
+ WMIX_GPIO_REGISTER_SET_CMDID,
+ WMIX_GPIO_REGISTER_GET_CMDID,
+ WMIX_GPIO_INTR_ACK_CMDID,
+ WMIX_HB_CHALLENGE_RESP_CMDID,
+ WMIX_DBGLOG_CFG_MODULE_CMDID,
+ WMIX_PROF_CFG_CMDID, /* 0x200a */
+ WMIX_PROF_ADDR_SET_CMDID,
+ WMIX_PROF_START_CMDID,
+ WMIX_PROF_STOP_CMDID,
+ WMIX_PROF_COUNT_GET_CMDID,
+} WMIX_COMMAND_ID;
+
+typedef enum {
+ WMIX_DSETOPENREQ_EVENTID = 0x3001,
+ WMIX_DSETCLOSE_EVENTID,
+ WMIX_DSETDATAREQ_EVENTID,
+ WMIX_GPIO_INTR_EVENTID,
+ WMIX_GPIO_DATA_EVENTID,
+ WMIX_GPIO_ACK_EVENTID,
+ WMIX_HB_CHALLENGE_RESP_EVENTID,
+ WMIX_DBGLOG_EVENTID,
+ WMIX_PROF_COUNT_EVENTID,
+} WMIX_EVENT_ID;
+
+/*
+ * =============DataSet support=================
+ */
+
+/*
+ * WMIX_DSETOPENREQ_EVENTID
+ * DataSet Open Request Event
+ */
+typedef PREPACK struct {
+ A_UINT32 dset_id;
+ A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETOPENREQ_EVENT;
+
+/*
+ * WMIX_DSETCLOSE_EVENTID
+ * DataSet Close Event
+ */
+typedef PREPACK struct {
+ A_UINT32 access_cookie;
+} POSTPACK WMIX_DSETCLOSE_EVENT;
+
+/*
+ * WMIX_DSETDATAREQ_EVENTID
+ * DataSet Data Request Event
+ */
+typedef PREPACK struct {
+ A_UINT32 access_cookie;
+ A_UINT32 offset;
+ A_UINT32 length;
+ A_UINT32 targ_buf; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETDATAREQ_EVENT;
+
+typedef PREPACK struct {
+ A_UINT32 status;
+ A_UINT32 targ_dset_handle;
+ A_UINT32 targ_reply_fn;
+ A_UINT32 targ_reply_arg;
+ A_UINT32 access_cookie;
+ A_UINT32 size;
+ A_UINT32 version;
+} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 status;
+ A_UINT32 targ_buf;
+ A_UINT32 targ_reply_fn;
+ A_UINT32 targ_reply_arg;
+ A_UINT32 length;
+ A_UINT8 buf[1];
+} POSTPACK WMIX_DSETDATA_REPLY_CMD;
+
+
+/*
+ * =============GPIO support=================
+ * All masks are 18-bit masks with bit N operating on GPIO pin N.
+ */
+
+#include "gpio.h"
+
+/*
+ * Set GPIO pin output state.
+ * In order for output to be driven, a pin must be enabled for output.
+ * This can be done during initialization through the GPIO Configuration
+ * DataSet, or during operation with the enable_mask.
+ *
+ * If a request is made to simultaneously set/clear or set/disable or
+ * clear/disable or disable/enable, results are undefined.
+ */
+typedef PREPACK struct {
+ A_UINT32 set_mask; /* pins to set */
+ A_UINT32 clear_mask; /* pins to clear */
+ A_UINT32 enable_mask; /* pins to enable for output */
+ A_UINT32 disable_mask; /* pins to disable/tristate */
+} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
+
+/*
+ * Set a GPIO register. For debug/exceptional cases.
+ * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
+ * platform-dependent header.
+ */
+typedef PREPACK struct {
+ A_UINT32 gpioreg_id; /* GPIO register ID */
+ A_UINT32 value; /* value to write */
+} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
+
+/* Get a GPIO register. For debug/exceptional cases. */
+typedef PREPACK struct {
+ A_UINT32 gpioreg_id; /* GPIO register to read */
+} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
+
+/*
+ * Host acknowledges and re-arms GPIO interrupts. A single
+ * message should be used to acknowledge all interrupts that
+ * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
+ */
+typedef PREPACK struct {
+ A_UINT32 ack_mask; /* interrupts to acknowledge */
+} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
+
+/*
+ * Target informs Host of GPIO interrupts that have ocurred since the
+ * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information --
+ * the current GPIO input values is provided -- in order to support
+ * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
+ */
+typedef PREPACK struct {
+ A_UINT32 intr_mask; /* pending GPIO interrupts */
+ A_UINT32 input_values; /* recent GPIO input values */
+} POSTPACK WMIX_GPIO_INTR_EVENT;
+
+/*
+ * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ * value set to the mask of GPIO pin inputs and
+ * reg_id set to GPIO_ID_NONE
+ *
+ *
+ * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ * value set to the value of the requested register and
+ * reg_id identifying the register (reflects the original request)
+ * NB: reg_id supports the future possibility of unsolicited
+ * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
+ * simplify Host GPIO support.
+ */
+typedef PREPACK struct {
+ A_UINT32 value;
+ A_UINT32 reg_id;
+} POSTPACK WMIX_GPIO_DATA_EVENT;
+
+/*
+ * =============Error Detection support=================
+ */
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_CMDID
+ * Heartbeat Challenge Response command
+ */
+typedef PREPACK struct {
+ A_UINT32 cookie;
+ A_UINT32 source;
+} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_EVENTID
+ * Heartbeat Challenge Response Event
+ */
+#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
+
+typedef PREPACK struct {
+ struct dbglog_config_s config;
+} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
+
+/*
+ * =============Target Profiling support=================
+ */
+
+typedef PREPACK struct {
+ A_UINT32 period; /* Time (in 30.5us ticks) between samples */
+ A_UINT32 nbins;
+} POSTPACK WMIX_PROF_CFG_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 addr;
+} POSTPACK WMIX_PROF_ADDR_SET_CMD;
+
+/*
+ * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
+ * using a WMIX_PROF_COUNT_EVENT with
+ * addr set to the next address
+ * count set to the corresponding count
+ */
+typedef PREPACK struct {
+ A_UINT32 addr;
+ A_UINT32 count;
+} POSTPACK WMIX_PROF_COUNT_EVENT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMIX_H_ */
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c
new file mode 100644
index 000000000000..44ae924ef134
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c
@@ -0,0 +1,432 @@
+//------------------------------------------------------------------------------
+// <copyright file="ar3kconfig.c" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// AR3K configuration implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "common_drv.h"
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include "export_hci_transport.h"
+#else
+#include "hci_transport_api.h"
+#endif
+#include "ar3kconfig.h"
+
+#define BAUD_CHANGE_COMMAND_STATUS_OFFSET 5
+#define HCI_EVENT_RESP_TIMEOUTMS 3000
+#define HCI_CMD_OPCODE_BYTE_LOW_OFFSET 0
+#define HCI_CMD_OPCODE_BYTE_HI_OFFSET 1
+#define HCI_EVENT_OPCODE_BYTE_LOW 3
+#define HCI_EVENT_OPCODE_BYTE_HI 4
+#define HCI_CMD_COMPLETE_EVENT_CODE 0xE
+#define HCI_MAX_EVT_RECV_LENGTH 257
+#define EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET 5
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev);
+
+static A_STATUS SendHCICommand(AR3K_CONFIG_INFO *pConfig,
+ A_UINT8 *pBuffer,
+ int Length)
+{
+ HTC_PACKET *pPacket = NULL;
+ A_STATUS status = A_OK;
+
+ do {
+
+ pPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET));
+ if (NULL == pPacket) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ A_MEMZERO(pPacket,sizeof(HTC_PACKET));
+ SET_HTC_PACKET_INFO_TX(pPacket,
+ NULL,
+ pBuffer,
+ Length,
+ HCI_COMMAND_TYPE,
+ AR6K_CONTROL_PKT_TAG);
+
+ /* issue synchronously */
+ status = HCI_TransportSendPkt(pConfig->pHCIDev,pPacket,TRUE);
+
+ } while (FALSE);
+
+ if (pPacket != NULL) {
+ A_FREE(pPacket);
+ }
+
+ return status;
+}
+
+static A_STATUS RecvHCIEvent(AR3K_CONFIG_INFO *pConfig,
+ A_UINT8 *pBuffer,
+ int *pLength)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pRecvPacket = NULL;
+
+ do {
+
+ pRecvPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET));
+ if (NULL == pRecvPacket) {
+ status = A_NO_MEMORY;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
+ break;
+ }
+
+ A_MEMZERO(pRecvPacket,sizeof(HTC_PACKET));
+
+ SET_HTC_PACKET_INFO_RX_REFILL(pRecvPacket,NULL,pBuffer,*pLength,HCI_EVENT_TYPE);
+
+ status = HCI_TransportRecvHCIEventSync(pConfig->pHCIDev,
+ pRecvPacket,
+ HCI_EVENT_RESP_TIMEOUTMS);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ *pLength = pRecvPacket->ActualLength;
+
+ } while (FALSE);
+
+ if (pRecvPacket != NULL) {
+ A_FREE(pRecvPacket);
+ }
+
+ return status;
+}
+
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+ A_UINT8 *pHCICommand,
+ int CmdLength,
+ A_UINT8 **ppEventBuffer,
+ A_UINT8 **ppBufferToFree)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 *pBuffer = NULL;
+ A_UINT8 *pTemp;
+ int length;
+ A_BOOL commandComplete = FALSE;
+ A_UINT8 opCodeBytes[2];
+
+ do {
+
+ length = max(HCI_MAX_EVT_RECV_LENGTH,CmdLength);
+ length += pConfig->pHCIProps->HeadRoom + pConfig->pHCIProps->TailRoom;
+ length += pConfig->pHCIProps->IOBlockPad;
+
+ pBuffer = (A_UINT8 *)A_MALLOC(length);
+ if (NULL == pBuffer) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to allocate bt buffer \n"));
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ /* get the opcodes to check the command complete event */
+ opCodeBytes[0] = pHCICommand[HCI_CMD_OPCODE_BYTE_LOW_OFFSET];
+ opCodeBytes[1] = pHCICommand[HCI_CMD_OPCODE_BYTE_HI_OFFSET];
+
+ /* copy HCI command */
+ A_MEMCPY(pBuffer + pConfig->pHCIProps->HeadRoom,pHCICommand,CmdLength);
+ /* send command */
+ status = SendHCICommand(pConfig,
+ pBuffer + pConfig->pHCIProps->HeadRoom,
+ CmdLength);
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to send HCI Command (%d) \n", status));
+ AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
+ break;
+ }
+
+ /* reuse buffer to capture command complete event */
+ A_MEMZERO(pBuffer,length);
+ status = RecvHCIEvent(pConfig,pBuffer,&length);
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI event recv failed \n"));
+ AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command");
+ break;
+ }
+
+ pTemp = pBuffer + pConfig->pHCIProps->HeadRoom;
+ if (pTemp[0] == HCI_CMD_COMPLETE_EVENT_CODE) {
+ if ((pTemp[HCI_EVENT_OPCODE_BYTE_LOW] == opCodeBytes[0]) &&
+ (pTemp[HCI_EVENT_OPCODE_BYTE_HI] == opCodeBytes[1])) {
+ commandComplete = TRUE;
+ }
+ }
+
+ if (!commandComplete) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Unexpected HCI event : %d \n",pTemp[0]));
+ AR_DEBUG_PRINTBUF(pTemp,pTemp[1],"Unexpected HCI event");
+ status = A_ECOMM;
+ break;
+ }
+
+ if (ppEventBuffer != NULL) {
+ /* caller wants to look at the event */
+ *ppEventBuffer = pTemp;
+ if (ppBufferToFree == NULL) {
+ status = A_EINVAL;
+ break;
+ }
+ /* caller must free the buffer */
+ *ppBufferToFree = pBuffer;
+ pBuffer = NULL;
+ }
+
+ } while (FALSE);
+
+ if (pBuffer != NULL) {
+ A_FREE(pBuffer);
+ }
+
+ return status;
+}
+
+static A_STATUS AR3KConfigureHCIBaud(AR3K_CONFIG_INFO *pConfig)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 hciBaudChangeCommand[] = {0x0c,0xfc,0x2,0,0};
+ A_UINT16 baudVal;
+ A_UINT8 *pEvent = NULL;
+ A_UINT8 *pBufferToFree = NULL;
+
+ do {
+
+ if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR3K_BAUD) {
+ baudVal = (A_UINT16)(pConfig->AR3KBaudRate / 100);
+ hciBaudChangeCommand[3] = (A_UINT8)baudVal;
+ hciBaudChangeCommand[4] = (A_UINT8)(baudVal >> 8);
+
+ status = SendHCICommandWaitCommandComplete(pConfig,
+ hciBaudChangeCommand,
+ sizeof(hciBaudChangeCommand),
+ &pEvent,
+ &pBufferToFree);
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Baud rate change failed! \n"));
+ break;
+ }
+
+ if (pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET] != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("AR3K Config: Baud change command event status failed: %d \n",
+ pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET]));
+ status = A_ECOMM;
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("AR3K Config: Baud Changed to %d \n",pConfig->AR3KBaudRate));
+ }
+
+ if (pConfig->Flags & AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY) {
+ /* some versions of AR3K do not switch baud immediately, up to 300MS */
+ A_MDELAY(325);
+ }
+
+ if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP) {
+ /* Tell target to change UART baud rate for AR6K */
+ status = HCI_TransportSetBaudRate(pConfig->pHCIDev, pConfig->AR3KBaudRate);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("AR3K Config: failed to set scale and step values: %d \n", status));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
+ ("AR3K Config: Baud changed to %d for AR6K\n", pConfig->AR3KBaudRate));
+ }
+
+ } while (FALSE);
+
+ if (pBufferToFree != NULL) {
+ A_FREE(pBufferToFree);
+ }
+
+ return status;
+}
+
+static A_STATUS AR3KExitMinBoot(AR3K_CONFIG_INFO *pConfig)
+{
+ A_STATUS status;
+ A_CHAR exitMinBootCmd[] = {0x25,0xFC,0x0c,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00};
+ A_UINT8 *pEvent = NULL;
+ A_UINT8 *pBufferToFree = NULL;
+
+ status = SendHCICommandWaitCommandComplete(pConfig,
+ exitMinBootCmd,
+ sizeof(exitMinBootCmd),
+ &pEvent,
+ &pBufferToFree);
+
+ if (A_SUCCESS(status)) {
+ if (pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET] != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("AR3K Config: MinBoot exit command event status failed: %d \n",
+ pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET]));
+ status = A_ECOMM;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("AR3K Config: MinBoot Exit Command Complete (Success) \n"));
+ A_MDELAY(1);
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: MinBoot Exit Failed! \n"));
+ }
+
+ if (pBufferToFree != NULL) {
+ A_FREE(pBufferToFree);
+ }
+
+ return status;
+}
+
+static A_STATUS AR3KConfigureSendHCIReset(AR3K_CONFIG_INFO *pConfig)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 hciResetCommand[] = {0x03,0x0c,0x0};
+ A_UINT8 *pEvent = NULL;
+ A_UINT8 *pBufferToFree = NULL;
+
+ status = SendHCICommandWaitCommandComplete( pConfig,
+ hciResetCommand,
+ sizeof(hciResetCommand),
+ &pEvent,
+ &pBufferToFree );
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI reset failed! \n"));
+ }
+
+ if (pBufferToFree != NULL) {
+ A_FREE(pBufferToFree);
+ }
+
+ return status;
+}
+
+A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfig)
+{
+ A_STATUS status = A_OK;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuring AR3K ...\n"));
+
+ do {
+
+ if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
+ status = A_EINVAL;
+ break;
+ }
+
+ /* disable asynchronous recv while we issue commands and receive events synchronously */
+ status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (pConfig->Flags & AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT) {
+ status = AR3KExitMinBoot(pConfig);
+ if (A_FAILED(status)) {
+ break;
+ }
+ }
+
+ if (pConfig->Flags &
+ (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
+ status = AR3KConfigureHCIBaud(pConfig);
+ if (A_FAILED(status)) {
+ break;
+ }
+ }
+
+ /* Load patching and PST file if available*/
+ if (A_OK != AthPSInitialize(pConfig)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch Download Failed!\n"));
+ }
+
+ /* Send HCI reset to make PS tags take effect*/
+ AR3KConfigureSendHCIReset(pConfig);
+
+ /* re-enable asynchronous recv */
+ status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+
+ } while (FALSE);
+
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuration Complete (status = %d) \n",status));
+
+ return status;
+}
+
+A_STATUS AR3KConfigureExit(void *config)
+{
+ A_STATUS status = A_OK;
+ AR3K_CONFIG_INFO *pConfig = (AR3K_CONFIG_INFO *)config;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleaning up AR3K ...\n"));
+
+ do {
+
+ if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) {
+ status = A_EINVAL;
+ break;
+ }
+
+ /* disable asynchronous recv while we issue commands and receive events synchronously */
+ status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (pConfig->Flags &
+ (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) {
+ status = AR3KConfigureHCIBaud(pConfig);
+ if (A_FAILED(status)) {
+ break;
+ }
+ }
+
+ /* re-enable asynchronous recv */
+ status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+
+ } while (FALSE);
+
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleanup Complete (status = %d) \n",status));
+
+ return status;
+}
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
new file mode 100644
index 000000000000..d4048c8efd0c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file implements the Atheros PS and patch downloaded for HCI UART Transport driver.
+ * This file can be used for HCI SDIO transport implementation for AR6002 with HCI_TRANSPORT_SDIO
+ * defined.
+ *
+ *
+ * ar3kcpsconfig.c
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices.. Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+
+#include "ar3kpsconfig.h"
+#ifndef HCI_TRANSPORT_SDIO
+#include "hci_ath.h"
+#include "hci_uart.h"
+#endif /* #ifndef HCI_TRANSPORT_SDIO */
+
+/*
+ * Structure used to send HCI packet, hci packet length and device info
+ * together as parameter to PSThread.
+ */
+typedef struct {
+
+ PSCmdPacket *HciCmdList;
+ A_UINT32 num_packets;
+ AR3K_CONFIG_INFO *dev;
+}HciCommandListParam;
+
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+ A_UINT8 *pHCICommand,
+ int CmdLength,
+ A_UINT8 **ppEventBuffer,
+ A_UINT8 **ppBufferToFree);
+
+A_UINT32 Rom_Version;
+A_UINT32 Build_Version;
+
+A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code);
+A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig);
+#ifndef HCI_TRANSPORT_SDIO
+
+DECLARE_WAIT_QUEUE_HEAD(PsCompleteEvent);
+DECLARE_WAIT_QUEUE_HEAD(HciEvent);
+A_UCHAR *HciEventpacket;
+rwlock_t syncLock;
+wait_queue_t Eventwait;
+
+int PSHciWritepacket(struct hci_dev*,A_UCHAR* Data, A_UINT32 len);
+extern char *bdaddr;
+#endif /* HCI_TRANSPORT_SDIO */
+
+A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr);
+
+int PSSendOps(void *arg);
+
+#ifdef BT_PS_DEBUG
+void Hci_log(A_UCHAR * log_string,A_UCHAR *data,A_UINT32 len)
+{
+ int i;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s : ",log_string));
+ for (i = 0; i < len; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("0x%02x ", data[i]));
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n...................................\n"));
+}
+#else
+#define Hci_log(string,data,len)
+#endif /* BT_PS_DEBUG */
+
+
+
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev)
+{
+ A_STATUS status = A_OK;
+ if(hdev == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Device handle received\n"));
+ return A_ERROR;
+ }
+
+#ifndef HCI_TRANSPORT_SDIO
+ DECLARE_WAITQUEUE(wait, current);
+#endif /* HCI_TRANSPORT_SDIO */
+
+
+#ifdef HCI_TRANSPORT_SDIO
+ status = PSSendOps((void*)hdev);
+#else
+ if(InitPSState(hdev) == -1) {
+ return A_ERROR;
+ }
+ allow_signal(SIGKILL);
+ add_wait_queue(&PsCompleteEvent,&wait);
+ set_current_state(TASK_INTERRUPTIBLE);
+ if(!kernel_thread(PSSendOps,(void*)hdev,CLONE_FS|CLONE_FILES|CLONE_SIGHAND|SIGCHLD)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Kthread Failed\n"));
+ remove_wait_queue(&PsCompleteEvent,&wait);
+ return A_ERROR;
+ }
+ wait_event_interruptible(PsCompleteEvent,(PSTagMode == FALSE));
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&PsCompleteEvent,&wait);
+
+#endif /* HCI_TRANSPORT_SDIO */
+
+
+ return status;
+
+}
+
+int PSSendOps(void *arg)
+{
+ int i;
+ int status = 0;
+ PSCmdPacket *HciCmdList; /* List storing the commands */
+ const struct firmware* firmware;
+ A_UINT32 numCmds;
+ A_UINT8 *event;
+ A_UINT8 *bufferToFree;
+ struct hci_dev *device;
+ A_UCHAR *buffer;
+ A_UINT32 len;
+ A_UINT32 DevType;
+ A_UCHAR *PsFileName;
+ A_UCHAR *patchFileName;
+ AR3K_CONFIG_INFO *hdev = (AR3K_CONFIG_INFO*)arg;
+ struct device *firmwareDev = NULL;
+ status = 0;
+ HciCmdList = NULL;
+#ifdef HCI_TRANSPORT_SDIO
+ device = hdev->pBtStackHCIDev;
+ firmwareDev = device->parent;
+#else
+ device = hdev;
+ firmwareDev = &device->dev;
+ AthEnableSyncCommandOp(TRUE);
+#endif /* HCI_TRANSPORT_SDIO */
+ /* First verify if the controller is an FPGA or ASIC, so depending on the device type the PS file to be written will be different.
+ */
+ if(A_ERROR == getDeviceType(hdev,&DevType)) {
+ status = 1;
+ goto complete;
+ }
+ if(A_ERROR == ReadVersionInfo(hdev)) {
+ status = 1;
+ goto complete;
+ }
+ patchFileName = PATCH_FILE;
+ if(DevType){
+ if(DevType == 0xdeadc0de){
+ PsFileName = PS_ASIC_FILE;
+ } else{
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" FPGA Test Image : %x %x \n",Rom_Version,Build_Version));
+ if((Rom_Version == 0x99999999) && (Build_Version == 1)){
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("FPGA Test Image : Skipping Patch File load\n"));
+ patchFileName = NULL;
+ }
+ PsFileName = PS_FPGA_FILE;
+ }
+ }
+ else{
+ PsFileName = PS_ASIC_FILE;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%x: FPGA/ASIC PS File Name %s\n", DevType,PsFileName));
+ /* Read the PS file to a dynamically allocated buffer */
+ if(request_firmware(&firmware,PsFileName,firmwareDev) < 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+ status = 1;
+ goto complete;
+
+ }
+ if(NULL == firmware || firmware->size == 0) {
+ status = 1;
+ goto complete;
+ }
+ buffer = (A_UCHAR *)A_MALLOC(firmware->size);
+ if(buffer != NULL) {
+ /* Copy the read file to a local Dynamic buffer */
+ memcpy(buffer,firmware->data,firmware->size);
+ len = firmware->size;
+ release_firmware(firmware);
+ /* Parse the PS buffer to a global variable */
+ status = AthDoParsePS(buffer,len);
+ A_FREE(buffer);
+ } else {
+ release_firmware(firmware);
+ }
+
+
+ /* Read the patch file to a dynamically allocated buffer */
+ if((patchFileName == NULL) || (request_firmware(&firmware,patchFileName,firmwareDev) < 0)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+ /*
+ * It is not necessary that Patch file be available, continue with PS Operations if.
+ * failed.
+ */
+ status = 0;
+
+ } else {
+ if(NULL == firmware || firmware->size == 0) {
+ status = 0;
+ } else {
+ buffer = (A_UCHAR *)A_MALLOC(firmware->size);
+ if(buffer != NULL) {
+ /* Copy the read file to a local Dynamic buffer */
+ memcpy(buffer,firmware->data,firmware->size);
+ len = firmware->size;
+ release_firmware(firmware);
+ /* parse and store the Patch file contents to a global variables */
+ status = AthDoParsePatch(buffer,len);
+ A_FREE(buffer);
+ } else {
+ release_firmware(firmware);
+ }
+ }
+ }
+
+ /* Create an HCI command list from the parsed PS and patch information */
+ AthCreateCommandList(&HciCmdList,&numCmds);
+
+ /* Form the parameter for PSSendOps() API */
+
+
+ /*
+ * First Send the CRC packet,
+ * We have to continue with the PS operations only if the CRC packet has been replied with
+ * a Command complete event with status Error.
+ */
+
+ if(SendHCICommandWaitCommandComplete
+ (hdev,
+ HciCmdList[0].Hcipacket,
+ HciCmdList[0].packetLen,
+ &event,
+ &bufferToFree) == A_OK) {
+ if(ReadPSEvent(event) == A_OK) { /* Exit if the status is success */
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+#ifndef HCI_TRANSPORT_SDIO
+ if(bdaddr[0] !='\0') {
+ write_bdaddr(hdev,bdaddr);
+ }
+#endif
+ status = 1;
+ goto complete;
+ }
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+ } else {
+ status = 0;
+ goto complete;
+ }
+
+ for(i = 1; i <numCmds; i++) {
+
+ if(SendHCICommandWaitCommandComplete
+ (hdev,
+ HciCmdList[i].Hcipacket,
+ HciCmdList[i].packetLen,
+ &event,
+ &bufferToFree) == A_OK) {
+ if(ReadPSEvent(event) != A_OK) { /* Exit if the status is success */
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+ status = 1;
+ goto complete;
+ }
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+ } else {
+ status = 0;
+ goto complete;
+ }
+ }
+#ifndef HCI_TRANSPORT_SDIO
+ if(bdaddr[0] != '\0') {
+ write_bdaddr(hdev,bdaddr);
+ } else
+#endif /* HCI_TRANSPORT_SDIO */
+ {
+ /* Read Contents of BDADDR file if user has not provided any option */
+ if(request_firmware(&firmware,BDADDR_FILE,firmwareDev) < 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ ));
+ status = 1;
+ goto complete;
+ }
+ if(NULL == firmware || firmware->size == 0) {
+ status = 1;
+ goto complete;
+ }
+ write_bdaddr(hdev,(A_UCHAR *)firmware->data);
+ release_firmware(firmware);
+ }
+complete:
+#ifndef HCI_TRANSPORT_SDIO
+ AthEnableSyncCommandOp(FALSE);
+ PSTagMode = FALSE;
+ wake_up_interruptible(&PsCompleteEvent);
+#endif /* HCI_TRANSPORT_SDIO */
+ if(NULL != HciCmdList) {
+ AthFreeCommandList(&HciCmdList,numCmds);
+ }
+ return status;
+}
+#ifndef HCI_TRANSPORT_SDIO
+/*
+ * This API is used to send the HCI command to controller and return
+ * with a HCI Command Complete event.
+ * For HCI SDIO transport, this will be internally defined.
+ */
+A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig,
+ A_UINT8 *pHCICommand,
+ int CmdLength,
+ A_UINT8 **ppEventBuffer,
+ A_UINT8 **ppBufferToFree)
+{
+ if(CmdLength == 0) {
+ return A_ERROR;
+ }
+ Hci_log("COM Write -->",pHCICommand,CmdLength);
+ PSAcked = FALSE;
+ if(PSHciWritepacket(pConfig,pHCICommand,CmdLength) == 0) {
+ /* If the controller is not available, return Error */
+ return A_ERROR;
+ }
+ //add_timer(&psCmdTimer);
+ wait_event_interruptible(HciEvent,(PSAcked == TRUE));
+ if(NULL != HciEventpacket) {
+ *ppEventBuffer = HciEventpacket;
+ *ppBufferToFree = HciEventpacket;
+ } else {
+ /* Did not get an event from controller. return error */
+ *ppBufferToFree = NULL;
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+#endif /* HCI_TRANSPORT_SDIO */
+
+A_STATUS ReadPSEvent(A_UCHAR* Data){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" PS Event %x %x %x\n",Data[4],Data[5],Data[3]));
+
+ if(Data[4] == 0xFC && Data[5] == 0x00)
+ {
+ switch(Data[3]){
+ case 0x0B:
+ return A_OK;
+ break;
+ case 0x0C:
+ /* Change Baudrate */
+ return A_OK;
+ break;
+ case 0x04:
+ return A_OK;
+ break;
+ case 0x1E:
+ Rom_Version = Data[9];
+ Rom_Version = ((Rom_Version << 8) |Data[8]);
+ Rom_Version = ((Rom_Version << 8) |Data[7]);
+ Rom_Version = ((Rom_Version << 8) |Data[6]);
+
+ Build_Version = Data[13];
+ Build_Version = ((Build_Version << 8) |Data[12]);
+ Build_Version = ((Build_Version << 8) |Data[11]);
+ Build_Version = ((Build_Version << 8) |Data[10]);
+ return A_OK;
+ break;
+
+
+ }
+ }
+
+ return A_ERROR;
+}
+int str2ba(unsigned char *str_bdaddr,unsigned char *bdaddr)
+{
+ unsigned char bdbyte[3];
+ unsigned char *str_byte = str_bdaddr;
+ int i,j;
+ unsigned char colon_present = 0;
+
+ if(NULL != strstr(str_bdaddr,":")) {
+ colon_present = 1;
+ }
+
+
+ bdbyte[2] = '\0';
+
+ for( i = 0,j = 5; i < 6; i++, j--) {
+ bdbyte[0] = str_byte[0];
+ bdbyte[1] = str_byte[1];
+ bdaddr[j] = A_STRTOL(bdbyte,NULL,16);
+ if(colon_present == 1) {
+ str_byte+=3;
+ } else {
+ str_byte+=2;
+ }
+ }
+ return 0;
+}
+
+A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr)
+{
+ A_UCHAR bdaddr_cmd[] = { 0x0B, 0xFC, 0x0A, 0x01, 0x01,
+ 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+ A_UINT8 *event;
+ A_UINT8 *bufferToFree = NULL;
+ A_STATUS result = A_ERROR;
+
+ str2ba(bdaddr,&bdaddr_cmd[7]);
+
+ if(A_OK == SendHCICommandWaitCommandComplete(pConfig,bdaddr_cmd,
+ sizeof(bdaddr_cmd),
+ &event,&bufferToFree)) {
+
+ if(event[4] == 0xFC && event[5] == 0x00){
+ if(event[3] == 0x0B){
+ result = A_OK;
+ }
+ }
+
+ }
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+ return result;
+
+}
+A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig)
+{
+ A_UINT8 hciCommand[] = {0x1E,0xfc,0x00};
+ A_UINT8 *event;
+ A_UINT8 *bufferToFree = NULL;
+ A_STATUS result = A_ERROR;
+ if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
+ result = ReadPSEvent(event);
+
+ }
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+ return result;
+}
+A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code)
+{
+ A_UINT8 hciCommand[] = {0x05,0xfc,0x05,0x00,0x00,0x00,0x00,0x04};
+ A_UINT8 *event;
+ A_UINT8 *bufferToFree = NULL;
+ A_UINT32 reg;
+ A_STATUS result = A_ERROR;
+ *code = 0;
+ hciCommand[3] = (A_UINT8)(FPGA_REGISTER & 0xFF);
+ hciCommand[4] = (A_UINT8)((FPGA_REGISTER >> 8) & 0xFF);
+ hciCommand[5] = (A_UINT8)((FPGA_REGISTER >> 16) & 0xFF);
+ hciCommand[6] = (A_UINT8)((FPGA_REGISTER >> 24) & 0xFF);
+ if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) {
+
+ if(event[4] == 0xFC && event[5] == 0x00){
+ switch(event[3]){
+ case 0x05:
+ reg = event[9];
+ reg = ((reg << 8) |event[8]);
+ reg = ((reg << 8) |event[7]);
+ reg = ((reg << 8) |event[6]);
+ *code = reg;
+ result = A_OK;
+
+ break;
+ case 0x06:
+ //Sleep(500);
+ break;
+ }
+ }
+
+ }
+ if(bufferToFree != NULL) {
+ A_FREE(bufferToFree);
+ }
+ return result;
+}
+
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h
new file mode 100644
index 000000000000..2dd664e47798
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file defines the symbols exported by Atheros PS and patch download module.
+ * define the constant HCI_TRANSPORT_SDIO if the module is being used for HCI SDIO transport.
+ * defined.
+ *
+ *
+ * ar3kcpsconfig.h
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices.. Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+
+#ifndef __AR3KPSCONFIG_H
+#define __AR3KPSCONFIG_H
+
+/*
+ * Define the flag HCI_TRANSPORT_SDIO and undefine HCI_TRANSPORT_UART if the transport being used is SDIO.
+ */
+#undef HCI_TRANSPORT_UART
+
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/signal.h>
+#include <linux/timer.h>
+
+
+#include <linux/ioctl.h>
+#include <linux/skbuff.h>
+#include <linux/firmware.h>
+#include <linux/wait.h>
+
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#include "ar3kpsparser.h"
+
+#define FPGA_REGISTER 0x4FFC
+
+
+#define PS_ASIC_FILE "PS_ASIC.pst"
+#define PS_FPGA_FILE "PS_FPGA.pst"
+
+#define PATCH_FILE "RamPatch.txt"
+#define BDADDR_FILE "ar3kbdaddr.pst"
+
+
+#ifndef HCI_TRANSPORT_SDIO
+#define AR3K_CONFIG_INFO struct hci_dev
+extern wait_queue_head_t HciEvent;
+extern wait_queue_t Eventwait;
+extern A_UCHAR *HciEventpacket;
+#endif /* #ifndef HCI_TRANSPORT_SDIO */
+
+A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev);
+A_STATUS ReadPSEvent(A_UCHAR* Data);
+#endif /* __AR3KPSCONFIG_H */
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
new file mode 100644
index 000000000000..8392777512ec
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
@@ -0,0 +1,972 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file implements the Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ * ar3kpsparser.c
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices.. Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+
+#include "ar3kpsparser.h"
+
+#define BD_ADDR_SIZE 6
+#define WRITE_PATCH 8
+#define ENABLE_PATCH 11
+#define PS_RESET 2
+#define PS_WRITE 1
+#define PS_VERIFY_CRC 9
+#define CHANGE_BDADDR 15
+
+#define HCI_COMMAND_HEADER 7
+
+#define HCI_EVENT_SIZE 7
+
+#define WRITE_PATCH_COMMAND_STATUS_OFFSET 5
+
+#define RAM_PS_REGION (1<<0)
+#define RAM_PATCH_REGION (1<<1)
+#define RAMPS_MAX_PS_DATA_PER_TAG 20000
+#define MAX_RADIO_CFG_TABLE_SIZE 244
+#define RAMPS_MAX_PS_TAGS_PER_FILE 50
+
+#define PS_MAX_LEN 500
+#define LINE_SIZE_MAX (PS_MAX_LEN *2)
+
+/* Constant values used by parser */
+#define BYTES_OF_PS_DATA_PER_LINE 16
+#define RAMPS_MAX_PS_DATA_PER_TAG 20000
+
+
+/* Number pf PS/Patch entries in an HCI packet */
+#define MAX_BYTE_LENGTH 244
+
+#define SKIP_BLANKS(str) while (*str == ' ') str++
+#define MIN(x, y) (((x) <= (y))? (x):(y))
+#define MAX(x, y) (((x) >= (y))? (x):(y))
+
+#define UNUSED(x) (x=x)
+
+#define IS_BETWEEN(x, lower, upper) (((lower) <= (x)) && ((x) <= (upper)))
+#define IS_DIGIT(c) (IS_BETWEEN((c), '0', '9'))
+#define IS_HEX(c) (IS_BETWEEN((c), '0', '9') || IS_BETWEEN((c), 'a', 'f') || IS_BETWEEN((c), 'A', 'F'))
+#define TO_LOWER(c) (IS_BETWEEN((c), 'A', 'Z') ? ((c) - 'A' + 'a') : (c))
+#define IS_BLANK(c) ((c) == ' ')
+#define CONV_DEC_DIGIT_TO_VALUE(c) ((c) - '0')
+#define CONV_HEX_DIGIT_TO_VALUE(c) (IS_DIGIT(c) ? ((c) - '0') : (IS_BETWEEN((c), 'A', 'Z') ? ((c) - 'A' + 10) : ((c) - 'a' + 10)))
+#define CONV_VALUE_TO_HEX(v) ((A_UINT8)( ((v & 0x0F) <= 9) ? ((v & 0x0F) + '0') : ((v & 0x0F) - 10 + 'A') ) )
+
+
+enum MinBootFileFormatE
+{
+ MB_FILEFORMAT_RADIOTBL,
+ MB_FILEFORMAT_PATCH,
+ MB_FILEFORMAT_COEXCONFIG
+};
+
+enum RamPsSection
+{
+ RAM_PS_SECTION,
+ RAM_PATCH_SECTION,
+ RAM_DYN_MEM_SECTION
+};
+
+enum eType {
+ eHex,
+ edecimal
+};
+
+
+typedef struct tPsTagEntry
+{
+ A_UINT32 TagId;
+ A_UINT32 TagLen;
+ A_UINT8 *TagData;
+} tPsTagEntry, *tpPsTagEntry;
+
+typedef struct tRamPatch
+{
+ A_UINT16 Len;
+ A_UINT8 * Data;
+} tRamPatch, *ptRamPatch;
+
+
+
+typedef struct ST_PS_DATA_FORMAT {
+ enum eType eDataType;
+ A_BOOL bIsArray;
+}ST_PS_DATA_FORMAT;
+
+typedef struct ST_READ_STATUS {
+ unsigned uTagID;
+ unsigned uSection;
+ unsigned uLineCount;
+ unsigned uCharCount;
+ unsigned uByteCount;
+}ST_READ_STATUS;
+
+
+/* Stores the number of PS Tags */
+static A_UINT32 Tag_Count = 0;
+
+/* Stores the number of patch commands */
+static A_UINT32 Patch_Count = 0;
+static A_UINT32 Total_tag_lenght = 0;
+static A_BOOL BDADDR = FALSE;
+A_UINT32 StartTagId;
+
+tPsTagEntry PsTagEntry[RAMPS_MAX_PS_TAGS_PER_FILE];
+tRamPatch RamPatch[MAX_NUM_PATCH_ENTRY];
+
+
+A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat);
+char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos);
+char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos);
+static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index);
+
+/* Function to reads the next character from the input buffer */
+char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos)
+{
+ char Ch;
+ if(buffer == NULL || *pos >=len )
+ {
+ return '\0';
+ } else {
+ Ch = buffer[*pos];
+ (*pos)++;
+ return Ch;
+ }
+}
+/* PS parser helper function */
+unsigned int uGetInputDataFormat(char* pCharLine, ST_PS_DATA_FORMAT *pstFormat)
+{
+ if(pCharLine[0] != '[') {
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ return 0;
+ }
+ switch(pCharLine[1]) {
+ case 'H':
+ case 'h':
+ if(pCharLine[2]==':') {
+ if((pCharLine[3]== 'a') || (pCharLine[3]== 'A')) {
+ if(pCharLine[4] == ']') {
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 5;
+ return 0;
+ }
+ else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
+ return 1;
+ }
+ }
+ if((pCharLine[3]== 'S') || (pCharLine[3]== 's')) {
+ if(pCharLine[4] == ']') {
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = false;
+ pCharLine += 5;
+ return 0;
+ }
+ else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A
+ return 1;
+ }
+ }
+ else if(pCharLine[3] == ']') { //[H:]
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 4;
+ return 0;
+ }
+ else { //[H:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
+ return 1;
+ }
+ }
+ else if(pCharLine[2]==']') { //[H]
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 3;
+ return 0;
+ }
+ else { //[H
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n"));
+ return 1;
+ }
+ break;
+
+ case 'A':
+ case 'a':
+ if(pCharLine[2]==':') {
+ if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
+ if(pCharLine[4] == ']') {
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 5;
+ return 0;
+ }
+ else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 1\n")); //[A:H
+ return 1;
+ }
+ }
+ else if(pCharLine[3]== ']') { //[A:]
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 4;
+ return 0;
+ }
+ else { //[A:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 2\n"));
+ return 1;
+ }
+ }
+ else if(pCharLine[2]==']') { //[H]
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 3;
+ return 0;
+ }
+ else { //[H
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 3\n"));
+ return 1;
+ }
+ break;
+
+ case 'S':
+ case 's':
+ if(pCharLine[2]==':') {
+ if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) {
+ if(pCharLine[4] == ']') {
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 5;
+ return 0;
+ }
+ else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 5\n")); //[A:H
+ return 1;
+ }
+ }
+ else if(pCharLine[3]== ']') { //[A:]
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 4;
+ return 0;
+ }
+ else { //[A:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 6\n"));
+ return 1;
+ }
+ }
+ else if(pCharLine[2]==']') { //[H]
+ pstFormat->eDataType = eHex;
+ pstFormat->bIsArray = true;
+ pCharLine += 3;
+ return 0;
+ }
+ else { //[H
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 7\n"));
+ return 1;
+ }
+ break;
+
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 8\n"));
+ return 1;
+ }
+}
+
+unsigned int uReadDataInSection(char *pCharLine, ST_PS_DATA_FORMAT stPS_DataFormat)
+{
+ char *pTokenPtr = pCharLine;
+
+ if(pTokenPtr[0] == '[') {
+ while(pTokenPtr[0] != ']' && pTokenPtr[0] != '\0') {
+ pTokenPtr++;
+ }
+ if(pTokenPtr[0] == '\0') {
+ return (0x0FFF);
+ }
+ pTokenPtr++;
+
+
+ }
+ if(stPS_DataFormat.eDataType == eHex) {
+ if(stPS_DataFormat.bIsArray == true) {
+ //Not implemented
+ return (0x0FFF);
+ }
+ else {
+ return (A_STRTOL(pTokenPtr, NULL, 16));
+ }
+ }
+ else {
+ //Not implemented
+ return (0x0FFF);
+ }
+}
+A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat)
+{
+ char *Buffer;
+ char *pCharLine;
+ A_UINT8 TagCount;
+ A_UINT16 ByteCount;
+ A_UINT8 ParseSection=RAM_PS_SECTION;
+ A_UINT32 pos;
+
+
+
+ int uReadCount;
+ ST_PS_DATA_FORMAT stPS_DataFormat;
+ ST_READ_STATUS stReadStatus = {0, 0, 0,0};
+ pos = 0;
+ Buffer = NULL;
+
+ if (srcbuffer == NULL || srclen == 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Could not open .\n"));
+ return A_ERROR;
+ }
+ TagCount = 0;
+ ByteCount = 0;
+ Buffer = A_MALLOC(LINE_SIZE_MAX + 1);
+ if(NULL == Buffer) {
+ return A_ERROR;
+ }
+ if (FileFormat == MB_FILEFORMAT_PATCH)
+ {
+ int LineRead = 0;
+ while((pCharLine = AthGetLine(Buffer, LINE_SIZE_MAX, srcbuffer,srclen,&pos)) != NULL)
+ {
+
+ SKIP_BLANKS(pCharLine);
+
+ // Comment line or empty line
+ if ((pCharLine[0] == '/') && (pCharLine[1] == '/'))
+ {
+ continue;
+ }
+
+ if ((pCharLine[0] == '#')) {
+ if (stReadStatus.uSection != 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n"));
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+ else {
+ stReadStatus.uSection = 1;
+ continue;
+ }
+ }
+ if ((pCharLine[0] == '/') && (pCharLine[1] == '*'))
+ {
+ pCharLine+=2;
+ SKIP_BLANKS(pCharLine);
+
+ if(!strncmp(pCharLine,"PA",2)||!strncmp(pCharLine,"Pa",2)||!strncmp(pCharLine,"pa",2))
+ ParseSection=RAM_PATCH_SECTION;
+
+ if(!strncmp(pCharLine,"DY",2)||!strncmp(pCharLine,"Dy",2)||!strncmp(pCharLine,"dy",2))
+ ParseSection=RAM_DYN_MEM_SECTION;
+
+ if(!strncmp(pCharLine,"PS",2)||!strncmp(pCharLine,"Ps",2)||!strncmp(pCharLine,"ps",2))
+ ParseSection=RAM_PS_SECTION;
+
+ LineRead = 0;
+ stReadStatus.uSection = 0;
+
+ continue;
+ }
+
+ switch(ParseSection)
+ {
+ case RAM_PS_SECTION:
+ {
+ if (stReadStatus.uSection == 1) //TagID
+ {
+ SKIP_BLANKS(pCharLine);
+ if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n"));
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+ //pCharLine +=5;
+ PsTagEntry[TagCount].TagId = uReadDataInSection(pCharLine, stPS_DataFormat);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG ID %d \n",PsTagEntry[TagCount].TagId));
+
+ //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag # %x\n", PsTagEntry[TagCount].TagId);
+ if (TagCount == 0)
+ {
+ StartTagId = PsTagEntry[TagCount].TagId;
+ }
+ stReadStatus.uSection = 2;
+ }
+ else if (stReadStatus.uSection == 2) //TagLength
+ {
+
+ if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n"));
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+ //pCharLine +=5;
+ ByteCount = uReadDataInSection(pCharLine, stPS_DataFormat);
+
+ //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag length %x\n", ByteCount));
+ if (ByteCount > LINE_SIZE_MAX/2)
+ {
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+ PsTagEntry[TagCount].TagLen = ByteCount;
+ PsTagEntry[TagCount].TagData = (A_UINT8*)A_MALLOC(ByteCount);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG Length %d Tag Index %d \n",PsTagEntry[TagCount].TagLen,TagCount));
+ stReadStatus.uSection = 3;
+ stReadStatus.uLineCount = 0;
+ }
+ else if( stReadStatus.uSection == 3) { //Data
+
+ if(stReadStatus.uLineCount == 0) {
+ if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n"));
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+ //pCharLine +=5;
+ }
+ SKIP_BLANKS(pCharLine);
+ stReadStatus.uCharCount = 0;
+ if(pCharLine[stReadStatus.uCharCount] == '[') {
+ while(pCharLine[stReadStatus.uCharCount] != ']' && pCharLine[stReadStatus.uCharCount] != '\0' ) {
+ stReadStatus.uCharCount++;
+ }
+ if(pCharLine[stReadStatus.uCharCount] == ']' ) {
+ stReadStatus.uCharCount++;
+ } else {
+ stReadStatus.uCharCount = 0;
+ }
+ }
+ uReadCount = (ByteCount > BYTES_OF_PS_DATA_PER_LINE)? BYTES_OF_PS_DATA_PER_LINE: ByteCount;
+ //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" "));
+ if((stPS_DataFormat.eDataType == eHex) && stPS_DataFormat.bIsArray == true) {
+ while(uReadCount > 0) {
+ PsTagEntry[TagCount].TagData[stReadStatus.uByteCount] =
+ (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount]) << 4)
+ | (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 1]));
+
+ PsTagEntry[TagCount].TagData[stReadStatus.uByteCount+1] =
+ (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 3]) << 4)
+ | (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 4]));
+
+ stReadStatus.uCharCount += 6; // read two bytes, plus a space;
+ stReadStatus.uByteCount += 2;
+ uReadCount -= 2;
+ }
+ if(ByteCount > BYTES_OF_PS_DATA_PER_LINE) {
+ ByteCount -= BYTES_OF_PS_DATA_PER_LINE;
+ }
+ else {
+ ByteCount = 0;
+ }
+ }
+ else {
+ //to be implemented
+ }
+
+ stReadStatus.uLineCount++;
+
+ if(ByteCount == 0) {
+ stReadStatus.uSection = 0;
+ stReadStatus.uCharCount = 0;
+ stReadStatus.uLineCount = 0;
+ stReadStatus.uByteCount = 0;
+ }
+ else {
+ stReadStatus.uCharCount = 0;
+ }
+
+ if((stReadStatus.uSection == 0)&&(++TagCount == RAMPS_MAX_PS_TAGS_PER_FILE))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!"));
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ //Sleep (3000);
+ //exit(1);
+ }
+
+ }
+ }
+
+ break;
+ default:
+ {
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+ break;
+ }
+ LineRead++;
+ }
+ Tag_Count = TagCount;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Number of Tags %d\n", Tag_Count));
+ }
+
+
+ if (TagCount > RAMPS_MAX_PS_TAGS_PER_FILE)
+ {
+
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_ERROR;
+ }
+
+ if(Buffer != NULL) {
+ A_FREE(Buffer);
+ }
+ return A_OK;
+
+}
+
+
+
+/********************/
+
+
+A_STATUS GetNextTwoChar(A_UCHAR *srcbuffer,A_UINT32 len, A_UINT32 *pos, char * buffer)
+{
+ unsigned char ch;
+
+ ch = AthReadChar(srcbuffer,len,pos);
+ if(ch != '\0' && IS_HEX(ch)) {
+ buffer[0] = ch;
+ } else
+ {
+ return A_ERROR;
+ }
+ ch = AthReadChar(srcbuffer,len,pos);
+ if(ch != '\0' && IS_HEX(ch)) {
+ buffer[1] = ch;
+ } else
+ {
+ return A_ERROR;
+ }
+ return A_OK;
+}
+
+A_STATUS AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen)
+{
+
+ char Byte[3];
+ char Line[MAX_BYTE_LENGTH + 1];
+ int ByteCount,ByteCount_Org;
+ int count;
+ int i,j,k;
+ int data;
+ A_UINT32 filepos;
+ Byte[2] = '\0';
+ j = 0;
+ filepos = 0;
+
+ while(NULL != AthGetLine(Line,MAX_BYTE_LENGTH,patchbuffer,patchlen,&filepos)) {
+ if(strlen(Line) <= 1 || !IS_HEX(Line[0])) {
+ continue;
+ } else {
+ break;
+ }
+ }
+ ByteCount = A_STRTOL(Line, NULL, 16);
+ ByteCount_Org = ByteCount;
+
+ while(ByteCount > MAX_BYTE_LENGTH){
+
+ /* Handle case when the number of patch buffer is more than the 20K */
+ if(MAX_NUM_PATCH_ENTRY == Patch_Count) {
+ for(i = 0; i < Patch_Count; i++) {
+ A_FREE(RamPatch[i].Data);
+ }
+ return A_ERROR;
+ }
+ RamPatch[Patch_Count].Len= MAX_BYTE_LENGTH;
+ RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(MAX_BYTE_LENGTH);
+ Patch_Count ++;
+
+
+ ByteCount= ByteCount - MAX_BYTE_LENGTH;
+ }
+
+ RamPatch[Patch_Count].Len= (ByteCount & 0xFF);
+ if(ByteCount != 0) {
+ RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(ByteCount);
+ Patch_Count ++;
+ }
+ count = 0;
+ while(ByteCount_Org > MAX_BYTE_LENGTH){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
+ for (i = 0,k=0; i < MAX_BYTE_LENGTH*2; i += 2,k++,count +=2) {
+ if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
+ return A_ERROR;
+ }
+ data = A_STRTOUL(&Byte[0], NULL, 16);
+ RamPatch[j].Data[k] = (data & 0xFF);
+
+
+ }
+ j++;
+ ByteCount_Org = ByteCount_Org - MAX_BYTE_LENGTH;
+ }
+ if(j == 0){
+ j++;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j));
+ for (k=0; k < ByteCount_Org; i += 2,k++,count+=2) {
+ if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) {
+ return A_ERROR;
+ }
+ data = A_STRTOUL(Byte, NULL, 16);
+ RamPatch[j].Data[k] = (data & 0xFF);
+
+
+ }
+ return A_OK;
+}
+
+
+/********************/
+A_STATUS AthDoParsePS(A_UCHAR *srcbuffer, A_UINT32 srclen)
+{
+ A_STATUS status;
+ int i;
+ A_BOOL BDADDR_Present = A_ERROR;
+
+
+
+ status = A_ERROR;
+
+ if(NULL != srcbuffer && srclen != 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("File Open Operation Successful\n"));
+
+ status = AthParseFilesUnified(srcbuffer,srclen,MB_FILEFORMAT_PATCH);
+ }
+
+
+
+ if(Tag_Count == 0){
+ Total_tag_lenght = 10;
+
+ }
+ else{
+ for(i=0; i<Tag_Count; i++){
+ if(PsTagEntry[i].TagId == 1){
+ BDADDR_Present = A_OK;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is present in Patch File \r\n"));
+
+ }
+ if(PsTagEntry[i].TagLen % 2 == 1){
+ Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen + 1;
+ }
+ else{
+ Total_tag_lenght = Total_tag_lenght + PsTagEntry[i].TagLen;
+ }
+
+ }
+ }
+
+ if(Tag_Count > 0 && !BDADDR_Present){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is not present adding 10 extra bytes \r\n"));
+ Total_tag_lenght=Total_tag_lenght + 10;
+ }
+ Total_tag_lenght = Total_tag_lenght+ 10 + (Tag_Count*4);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Total Length %d\n",Total_tag_lenght));
+
+
+ return status;
+}
+char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos)
+{
+
+ int count;
+ static short flag;
+ char CharRead;
+ count = 0;
+ flag = A_ERROR;
+
+ do
+ {
+ CharRead = AthReadChar(srcbuffer,len,pos);
+ if( CharRead == '\0' ) {
+ buffer[count+1] = '\0';
+ if(count == 0) {
+ return NULL;
+ }
+ else {
+ return buffer;
+ }
+ }
+
+ if(CharRead == 13) {
+ } else if(CharRead == 10) {
+ buffer[count] ='\0';
+ flag = A_ERROR;
+ return buffer;
+ }else {
+ buffer[count++] = CharRead;
+ }
+
+ }
+ while(count < maxlen-1 && CharRead != '\0');
+ buffer[count] = '\0';
+
+ return buffer;
+}
+
+static void LoadHeader(A_UCHAR *HCI_PS_Command,A_UCHAR opcode,int length,int index){
+
+ HCI_PS_Command[0]= 0x0B;
+ HCI_PS_Command[1]= 0xFC;
+ HCI_PS_Command[2]= length + 4;
+ HCI_PS_Command[3]= opcode;
+ HCI_PS_Command[4]= (index & 0xFF);
+ HCI_PS_Command[5]= ((index>>8) & 0xFF);
+ HCI_PS_Command[6]= length;
+}
+
+/////////////////////////
+//
+int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets)
+{
+
+ A_UINT8 count;
+ A_UINT32 NumcmdEntry = 0;
+
+ A_UINT32 Crc = 0;
+ *numPackets = 0;
+
+
+ if(Patch_Count > 0)
+ Crc |= RAM_PATCH_REGION;
+ if(Tag_Count > 0)
+ Crc |= RAM_PS_REGION;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("PS Thread Started CRC %x Patch Count %d Tag Count %d \n",Crc,Patch_Count,Tag_Count));
+
+ if(Patch_Count || Tag_Count ){
+ NumcmdEntry+=(2 + Patch_Count + Tag_Count); /* CRC Packet + PS Reset Packet + Patch List + PS List*/
+ if(Patch_Count > 0) {
+ NumcmdEntry++; /* Patch Enable Command */
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size %d \r\n",NumcmdEntry,sizeof(PSCmdPacket) * NumcmdEntry));
+ (*HciPacketList) = A_MALLOC(sizeof(PSCmdPacket) * NumcmdEntry);
+ if(NULL == *HciPacketList) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("memory allocation failed \r\n"));
+ }
+ AthPSCreateHCICommand(PS_VERIFY_CRC,Crc,*HciPacketList,numPackets);
+ if(Patch_Count > 0){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Write Patch**** \r\n"));
+ AthPSCreateHCICommand(WRITE_PATCH,Patch_Count,*HciPacketList,numPackets);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Enable Patch**** \r\n"));
+ AthPSCreateHCICommand(ENABLE_PATCH,0,*HciPacketList,numPackets);
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Reset**** \r\n"));
+ AthPSCreateHCICommand(PS_RESET,Total_tag_lenght,*HciPacketList,numPackets);
+ if(Tag_Count > 0){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Write**** \r\n"));
+ AthPSCreateHCICommand(PS_WRITE,Tag_Count,*HciPacketList,numPackets);
+ }
+ }
+ if(!BDADDR){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR not present \r\n"));
+
+ }
+ for(count = 0; count < Patch_Count; count++) {
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count));
+ A_FREE(RamPatch[Patch_Count].Data);
+ }
+
+ for(count = 0; count < Tag_Count; count++) {
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count));
+ A_FREE(PsTagEntry[count].TagData);
+ }
+
+/*
+ * SDIO Transport uses synchronous mode of data transfer
+ * So, AthPSOperations() call returns only after receiving the
+ * command complete event.
+ */
+ return *numPackets;
+}
+
+
+////////////////////////
+
+/////////////
+static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index)
+{
+ A_UCHAR *HCI_PS_Command;
+ A_UINT32 Length;
+ int i,j;
+
+ switch(Opcode)
+ {
+ case WRITE_PATCH:
+
+
+ for(i=0;i< Param1;i++){
+
+ HCI_PS_Command = (A_UCHAR *) A_MALLOC(RamPatch[i].Len+HCI_COMMAND_HEADER);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Allocated Buffer Size %d\n",RamPatch[i].Len+HCI_COMMAND_HEADER));
+ if(HCI_PS_Command == NULL){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+ return A_ERROR;
+ }
+ memset (HCI_PS_Command, 0, RamPatch[i].Len+HCI_COMMAND_HEADER);
+ LoadHeader(HCI_PS_Command,Opcode,RamPatch[i].Len,i);
+ for(j=0;j<RamPatch[i].Len;j++){
+ HCI_PS_Command[HCI_COMMAND_HEADER+j]=RamPatch[i].Data[j];
+ }
+ PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+ PSPatchPacket[*index].packetLen = RamPatch[i].Len+HCI_COMMAND_HEADER;
+ (*index)++;
+
+
+ }
+
+ break;
+
+ case ENABLE_PATCH:
+
+
+ Length = 0;
+ i= 0;
+ HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+ if(HCI_PS_Command == NULL){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+ return A_ERROR;
+ }
+
+ memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+ LoadHeader(HCI_PS_Command,Opcode,Length,i);
+ PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+ PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+ (*index)++;
+
+ break;
+
+ case PS_RESET:
+ Length = 0x06;
+ i=0;
+ HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+ if(HCI_PS_Command == NULL){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+ return A_ERROR;
+ }
+ memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+ LoadHeader(HCI_PS_Command,Opcode,Length,i);
+ HCI_PS_Command[7]= 0x00;
+ HCI_PS_Command[Length+HCI_COMMAND_HEADER -2]= (Param1 & 0xFF);
+ HCI_PS_Command[Length+HCI_COMMAND_HEADER -1]= ((Param1 >> 8) & 0xFF);
+ PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+ PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+ (*index)++;
+
+ break;
+
+ case PS_WRITE:
+ for(i=0;i< Param1;i++){
+ if(PsTagEntry[i].TagId ==1)
+ BDADDR = TRUE;
+
+ HCI_PS_Command = (A_UCHAR *) A_MALLOC(PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
+ if(HCI_PS_Command == NULL){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+ return A_ERROR;
+ }
+
+ memset (HCI_PS_Command, 0, PsTagEntry[i].TagLen+HCI_COMMAND_HEADER);
+ LoadHeader(HCI_PS_Command,Opcode,PsTagEntry[i].TagLen,PsTagEntry[i].TagId);
+
+ for(j=0;j<PsTagEntry[i].TagLen;j++){
+ HCI_PS_Command[HCI_COMMAND_HEADER+j]=PsTagEntry[i].TagData[j];
+ }
+
+ PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+ PSPatchPacket[*index].packetLen = PsTagEntry[i].TagLen+HCI_COMMAND_HEADER;
+ (*index)++;
+
+ }
+
+ break;
+
+
+ case PS_VERIFY_CRC:
+ Length = 0x0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("VALUE of CRC:%d At index %d\r\n",Param1,*index));
+
+ HCI_PS_Command = (A_UCHAR *) A_MALLOC(Length+HCI_COMMAND_HEADER);
+ if(HCI_PS_Command == NULL){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n"));
+ return A_ERROR;
+ }
+ memset (HCI_PS_Command, 0, Length+HCI_COMMAND_HEADER);
+ LoadHeader(HCI_PS_Command,Opcode,Length,Param1);
+
+ PSPatchPacket[*index].Hcipacket = HCI_PS_Command;
+ PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER;
+ (*index)++;
+
+ break;
+
+ case CHANGE_BDADDR:
+ break;
+ }
+ return A_OK;
+}
+A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets)
+{
+ int i;
+ if(*HciPacketList == NULL) {
+ return A_ERROR;
+ }
+ for(i = 0; i < numPackets;i++) {
+ A_FREE((*HciPacketList)[i].Hcipacket);
+ }
+ A_FREE(*HciPacketList);
+ return A_OK;
+}
diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
new file mode 100644
index 000000000000..2aaadbb50469
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2004-2008 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file is the include file for Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ * ar3kpsparser.h
+ *
+ *
+ *
+ * The software source and binaries included in this development package are
+ * licensed, not sold. You, or your company, received the package under one
+ * or more license agreements. The rights granted to you are specifically
+ * listed in these license agreement(s). All other rights remain with Atheros
+ * Communications, Inc., its subsidiaries, or the respective owner including
+ * those listed on the included copyright notices.. Distribution of any
+ * portion of this package must be in strict compliance with the license
+ * agreement(s) terms.
+ *
+ *
+ *
+ */
+
+/*------------------------------------------------------------------------------
+ *
+ * <copyright file="File name" company="Atheros">
+ * Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * This file is the include file for Atheros PS and patch parser.
+ * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands.
+ *
+ *
+ *
+ *
+ *
+ */
+#ifndef __AR3KPSPARSER_H
+#define __AR3KPSPARSER_H
+
+
+
+
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include "athdefs.h"
+#ifdef HCI_TRANSPORT_SDIO
+#include "a_config.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "common_drv.h"
+#include "hci_transport_api.h"
+#include "ar3kconfig.h"
+#else
+#ifndef A_PRINTF
+#define A_PRINTF(args...) printk(KERN_ALERT args)
+#endif /* A_PRINTF */
+#include "debug_linux.h"
+
+/* Helper data type declaration */
+
+#ifndef A_UINT32
+#define A_UCHAR unsigned char
+#define A_UINT32 unsigned long
+#define A_UINT16 unsigned short
+#define A_UINT8 unsigned char
+#define A_BOOL unsigned char
+#endif /* A_UINT32 */
+
+#define ATH_DEBUG_ERR (1 << 0)
+#define ATH_DEBUG_WARN (1 << 1)
+#define ATH_DEBUG_INFO (1 << 2)
+
+
+
+#define FALSE 0
+#define TRUE 1
+
+#ifndef A_MALLOC
+#define A_MALLOC(size) kmalloc((size),GFP_KERNEL)
+#endif /* A_MALLOC */
+
+
+#ifndef A_FREE
+#define A_FREE(addr) kfree((addr))
+#endif /* A_MALLOC */
+#endif /* HCI_TRANSPORT_UART */
+
+/* String manipulation APIs */
+#ifndef A_STRTOUL
+#define A_STRTOUL simple_strtoul
+#endif /* A_STRTOL */
+
+#ifndef A_STRTOL
+#define A_STRTOL simple_strtol
+#endif /* A_STRTOL */
+
+
+/* The maximum number of bytes possible in a patch entry */
+#define MAX_PATCH_SIZE 20000
+
+/* Maximum HCI packets that will be formed from the Patch file */
+#define MAX_NUM_PATCH_ENTRY (MAX_PATCH_SIZE/MAX_BYTE_LENGTH) + 1
+
+
+
+
+
+
+
+typedef struct PSCmdPacket
+{
+ A_UCHAR *Hcipacket;
+ int packetLen;
+} PSCmdPacket;
+
+/* Parses a Patch information buffer and store it in global structure */
+A_STATUS AthDoParsePatch(A_UCHAR *, A_UINT32);
+
+/* parses a PS information buffer and stores it in a global structure */
+A_STATUS AthDoParsePS(A_UCHAR *, A_UINT32);
+
+/*
+ * Uses the output of Both AthDoParsePS and AthDoParsePatch APIs to form HCI command array with
+ * all the PS and patch commands.
+ * The list will have the below mentioned commands in order.
+ * CRC command packet
+ * Download patch command(s)
+ * Enable patch Command
+ * PS Reset Command
+ * PS Tag Command(s)
+ *
+ */
+int AthCreateCommandList(PSCmdPacket **, A_UINT32 *);
+
+/* Cleanup the dynamically allicated HCI command list */
+A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets);
+#endif /* __AR3KPSPARSER_H */
diff --git a/drivers/net/wireless/ath6kl/miscdrv/common_drv.c b/drivers/net/wireless/ath6kl/miscdrv/common_drv.c
new file mode 100644
index 000000000000..0a318c3c8de4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/common_drv.c
@@ -0,0 +1,973 @@
+//------------------------------------------------------------------------------
+// <copyright file="common_drv.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+
+#include "AR6002/hw/mbox_host_reg.h"
+#include "AR6002/hw/apb_map.h"
+#include "AR6002/hw/si_reg.h"
+#include "AR6002/hw/gpio_reg.h"
+#include "AR6002/hw/rtc_reg.h"
+#include "AR6002/hw/vmc_reg.h"
+#include "AR6002/hw/mbox_reg.h"
+
+#include "targaddrs.h"
+#include "a_osapi.h"
+#include "hif.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "bmi.h"
+#include "bmi_msg.h"
+#include "common_drv.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "ar6000_diag.h"
+
+static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL;
+static A_MUTEX_T g_ModuleListLock;
+static A_BOOL g_ModuleDebugInit = FALSE;
+
+#ifdef DEBUG
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc,
+ "misc",
+ "Common and misc APIs",
+ ATH_DEBUG_MASK_DEFAULTS,
+ 0,
+ NULL);
+
+#endif
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
+ (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
+
+
+#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080
+#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080
+#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080
+#define CPU_DBG_SEL_ADDRESS 0x00000483
+#define CPU_DBG_ADDRESS 0x00000484
+
+/* Compile the 4BYTE version of the window register setup routine,
+ * This mitigates host interconnect issues with non-4byte aligned bus requests, some
+ * interconnects use bus adapters that impose strict limitations.
+ * Since diag window access is not intended for performance critical operations, the 4byte mode should
+ * be satisfactory even though it generates 4X the bus activity. */
+
+#ifdef USE_4BYTE_REGISTER_ACCESS
+
+ /* set the window address register (using 4-byte register access ). */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+ A_STATUS status;
+ A_UINT8 addrValue[4];
+ A_INT32 i;
+
+ /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+ * last to initiate the access cycle */
+
+ for (i = 1; i <= 3; i++) {
+ /* fill the buffer with the address byte value we want to hit 4 times*/
+ addrValue[0] = ((A_UINT8 *)&Address)[i];
+ addrValue[1] = addrValue[0];
+ addrValue[2] = addrValue[0];
+ addrValue[3] = addrValue[0];
+
+ /* hit each byte of the register address with a 4-byte write operation to the same address,
+ * this is a harmless operation */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr+i,
+ addrValue,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+ if (status != A_OK) {
+ break;
+ }
+ }
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+ Address, RegisterAddr));
+ return status;
+ }
+
+ /* write the address register again, this time write the whole 4-byte value.
+ * The effect here is that the LSB write causes the cycle to start, the extra
+ * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr,
+ (A_UCHAR *)(&Address),
+ 4,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+ Address, RegisterAddr));
+ return status;
+ }
+
+ return A_OK;
+
+
+
+}
+
+
+#else
+
+ /* set the window address register */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+ A_STATUS status;
+
+ /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+ * last to initiate the access cycle */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr+1, /* write upper 3 bytes */
+ ((A_UCHAR *)(&Address))+1,
+ sizeof(A_UINT32)-1,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+ RegisterAddr, Address));
+ return status;
+ }
+
+ /* write the LSB of the register, this initiates the operation */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr,
+ (A_UCHAR *)(&Address),
+ sizeof(A_UINT8),
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+ RegisterAddr, Address));
+ return status;
+ }
+
+ return A_OK;
+}
+
+#endif
+
+/*
+ * Read from the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+ A_STATUS status;
+
+ /* set window register to start read cycle */
+ status = ar6000_SetAddressWindowRegister(hifDevice,
+ WINDOW_READ_ADDR_ADDRESS,
+ *address);
+
+ if (status != A_OK) {
+ return status;
+ }
+
+ /* read the data */
+ status = HIFReadWrite(hifDevice,
+ WINDOW_DATA_ADDRESS,
+ (A_UCHAR *)data,
+ sizeof(A_UINT32),
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
+ return status;
+ }
+
+ return status;
+}
+
+
+/*
+ * Write to the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+ A_STATUS status;
+
+ /* set write data */
+ status = HIFReadWrite(hifDevice,
+ WINDOW_DATA_ADDRESS,
+ (A_UCHAR *)data,
+ sizeof(A_UINT32),
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
+ return status;
+ }
+
+ /* set window register, which starts the write cycle */
+ return ar6000_SetAddressWindowRegister(hifDevice,
+ WINDOW_WRITE_ADDR_ADDRESS,
+ *address);
+ }
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length)
+{
+ A_UINT32 count;
+ A_STATUS status = A_OK;
+
+ for (count = 0; count < length; count += 4, address += 4) {
+ if ((status = ar6000_ReadRegDiag(hifDevice, &address,
+ (A_UINT32 *)&data[count])) != A_OK)
+ {
+ break;
+ }
+ }
+
+ return status;
+}
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length)
+{
+ A_UINT32 count;
+ A_STATUS status = A_OK;
+
+ for (count = 0; count < length; count += 4, address += 4) {
+ if ((status = ar6000_WriteRegDiag(hifDevice, &address,
+ (A_UINT32 *)&data[count])) != A_OK)
+ {
+ break;
+ }
+ }
+
+ return status;
+}
+
+A_STATUS
+ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval)
+{
+ A_STATUS status;
+ A_UCHAR vals[4];
+ A_UCHAR register_selection[4];
+
+ register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
+ status = HIFReadWrite(hifDevice,
+ CPU_DBG_SEL_ADDRESS,
+ register_selection,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
+ return status;
+ }
+
+ status = HIFReadWrite(hifDevice,
+ CPU_DBG_ADDRESS,
+ (A_UCHAR *)vals,
+ sizeof(vals),
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
+ return status;
+ }
+
+ *regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
+
+ return status;
+}
+
+void
+ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs)
+{
+ int i;
+ A_UINT32 val;
+
+ for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
+ val=0xffffffff;
+ (void)ar6k_ReadTargetRegister(hifDevice, i, &val);
+ targregs[i] = val;
+ }
+}
+
+#if 0
+static A_STATUS
+_do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value)
+{
+ A_STATUS status;
+
+ status = ar6000_WriteRegDiag(hifDevice, &addr, &value);
+ if (status != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
+ }
+
+ return status;
+}
+#endif
+
+
+/*
+ * Delay up to wait_msecs millisecs to allow Target to enter BMI phase,
+ * which is a good sign that it's alive and well. This is used after
+ * explicitly forcing the Target to reset.
+ *
+ * The wait_msecs time should be sufficiently long to cover any reasonable
+ * boot-time delay. For instance, AR6001 firmware allow one second for a
+ * low frequency crystal to settle before it calibrates the refclk frequency.
+ *
+ * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE.
+ */
+#if 0
+static A_STATUS
+_delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType)
+{
+ A_INT32 actual_wait;
+ A_INT32 i;
+ A_UINT32 address;
+
+ actual_wait = 0;
+
+ /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */
+ if (TargetType == TARGET_TYPE_AR6001) {
+ address = AR6001_LOCAL_COUNT_ADDRESS;
+ } else if (TargetType == TARGET_TYPE_AR6002) {
+ address = AR6002_LOCAL_COUNT_ADDRESS;
+ } else if (TargetType == TARGET_TYPE_AR6003) {
+ address = AR6003_LOCAL_COUNT_ADDRESS;
+ } else {
+ A_ASSERT(0);
+ }
+ address += 0x10;
+ for (i=0; actual_wait < wait_msecs; i++) {
+ A_UINT32 data;
+
+ A_MDELAY(100);
+ actual_wait += 100;
+
+ data = 0;
+ if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) {
+ return A_ERROR;
+ }
+
+ if (data != 0) {
+ /* No need to wait longer -- we have a BMI credit */
+ return A_OK;
+ }
+ }
+ return A_ERROR; /* timed out */
+}
+#endif
+
+#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000
+#define AR6002_RESET_CONTROL_ADDRESS 0x00004000
+#define AR6003_RESET_CONTROL_ADDRESS 0x00004000
+/* reset device */
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset)
+{
+ A_STATUS status = A_OK;
+ A_UINT32 address;
+ A_UINT32 data;
+
+ do {
+// Workaround BEGIN
+ // address = RESET_CONTROL_ADDRESS;
+
+ if (coldReset) {
+ data = RESET_CONTROL_COLD_RST_MASK;
+ }
+ else {
+ data = RESET_CONTROL_MBOX_RST_MASK;
+ }
+
+ /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
+ if (TargetType == TARGET_TYPE_AR6001) {
+ address = AR6001_RESET_CONTROL_ADDRESS;
+ } else if (TargetType == TARGET_TYPE_AR6002) {
+ address = AR6002_RESET_CONTROL_ADDRESS;
+ } else if (TargetType == TARGET_TYPE_AR6003) {
+ address = AR6003_RESET_CONTROL_ADDRESS;
+ } else {
+ A_ASSERT(0);
+ }
+
+
+ status = ar6000_WriteRegDiag(hifDevice, &address, &data);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (!waitForCompletion) {
+ break;
+ }
+
+#if 0
+ /* Up to 2 second delay to allow things to settle down */
+ (void)_delay_until_target_alive(hifDevice, 2000, TargetType);
+
+ /*
+ * Read back the RESET CAUSE register to ensure that the cold reset
+ * went through.
+ */
+
+ // address = RESET_CAUSE_ADDRESS;
+ /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
+ if (TargetType == TARGET_TYPE_AR6001) {
+ address = 0x0C0000CC;
+ } else if (TargetType == TARGET_TYPE_AR6002) {
+ address = 0x000040C0;
+ } else if (TargetType == TARGET_TYPE_AR6003) {
+ address = 0x000040C0;
+ } else {
+ A_ASSERT(0);
+ }
+
+ data = 0;
+ status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
+ data &= RESET_CAUSE_LAST_MASK;
+ if (data != 2) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
+ }
+#endif
+// Workaroud END
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
+ }
+
+ return A_OK;
+}
+
+#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */
+#define REG_DUMP_COUNT_AR6002 60
+#define REG_DUMP_COUNT_AR6003 60
+#define REGISTER_DUMP_LEN_MAX 60
+#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6001 too large"
+#endif
+#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6002 too large"
+#endif
+#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX
+#error "REG_DUMP_COUNT_AR6003 too large"
+#endif
+
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
+{
+ A_UINT32 address;
+ A_UINT32 regDumpArea = 0;
+ A_STATUS status;
+ A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
+ A_UINT32 regDumpCount = 0;
+ A_UINT32 i;
+
+ do {
+
+ /* the reg dump pointer is copied to the host interest area */
+ address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
+ address = TARG_VTOP(TargetType, address);
+
+ if (TargetType == TARGET_TYPE_AR6001) {
+ /* for AR6001, this is a fixed location because the ptr is actually stuck in cache,
+ * this may be fixed in later firmware versions */
+ address = 0x18a0;
+ regDumpCount = REG_DUMP_COUNT_AR6001;
+ } else if (TargetType == TARGET_TYPE_AR6002) {
+ regDumpCount = REG_DUMP_COUNT_AR6002;
+ } else if (TargetType == TARGET_TYPE_AR6003) {
+ regDumpCount = REG_DUMP_COUNT_AR6003;
+ } else {
+ A_ASSERT(0);
+ }
+
+ /* read RAM location through diagnostic window */
+ status = ar6000_ReadRegDiag(hifDevice, &address, &regDumpArea);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
+
+ if (regDumpArea == 0) {
+ /* no reg dump */
+ break;
+ }
+
+ regDumpArea = TARG_VTOP(TargetType, regDumpArea);
+
+ /* fetch register dump data */
+ status = ar6000_ReadDataDiag(hifDevice,
+ regDumpArea,
+ (A_UCHAR *)&regDumpValues[0],
+ regDumpCount * (sizeof(A_UINT32)));
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
+ break;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
+
+ for (i = 0; i < regDumpCount; i++) {
+ //ATHR_DISPLAY_MSG (_T(" %d : 0x%8.8X \n"), i, regDumpValues[i]);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i]));
+
+#ifdef UNDER_CE
+ /*
+ * For Every logPrintf() Open the File so that in case of Crashes
+ * We will have until the Last Message Flushed on to the File
+ * So use logPrintf Sparingly..!!
+ */
+ tgtassertPrintf (ATH_DEBUG_TRC," %d: 0x%8.8X \n",i, regDumpValues[i]);
+#endif
+ }
+
+ } while (FALSE);
+
+}
+
+/* set HTC/Mbox operational parameters, this can only be called when the target is in the
+ * BMI phase */
+A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
+ A_UINT32 TargetType,
+ A_UINT32 MboxIsrYieldValue,
+ A_UINT8 HtcControlBuffers)
+{
+ A_STATUS status;
+ A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+ do {
+ /* get the block sizes */
+ status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ blocksizes, sizeof(blocksizes));
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
+ break;
+ }
+ /* note: we actually get the block size for mailbox 1, for SDIO the block
+ * size on mailbox 0 is artificially set to 1 */
+ /* must be a power of 2 */
+ A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
+
+ if (HtcControlBuffers != 0) {
+ /* set override for number of control buffers to use */
+ blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16;
+ }
+
+ /* set the host interest area for the block size */
+ status = BMIWriteMemory(hifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
+ (A_UCHAR *)&blocksizes[1],
+ 4);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
+ blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
+
+ if (MboxIsrYieldValue != 0) {
+ /* set the host interest area for the mbox ISR yield limit */
+ status = BMIWriteMemory(hifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
+ (A_UCHAR *)&MboxIsrYieldValue,
+ 4);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
+ break;
+ }
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+
+static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
+{
+ A_STATUS status = A_OK;
+
+ /* placeholder */
+
+ return status;
+}
+
+static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
+{
+ A_STATUS status = A_OK;
+
+ /* placeholder */
+
+ return status;
+}
+
+/* this function assumes the caller has already initialized the BMI APIs */
+A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice,
+ A_UINT32 TargetType,
+ A_UINT32 TargetVersion)
+{
+ if (TargetType == TARGET_TYPE_AR6002) {
+ /* do any preparations for AR6002 devices */
+ return prepare_ar6002(hifDevice,TargetVersion);
+ } else if (TargetType == TARGET_TYPE_AR6003) {
+ return prepare_ar6003(hifDevice,TargetVersion);
+ }
+
+ return A_OK;
+}
+
+#if defined(CONFIG_AR6002_REV1_FORCE_HOST)
+/*
+ * Call this function just before the call to BMIInit
+ * in order to force* AR6002 rev 1.x firmware to detect a Host.
+ * THIS IS FOR USE ONLY WITH AR6002 REV 1.x.
+ * TBDXXX: Remove this function when REV 1.x is desupported.
+ */
+A_STATUS
+ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice)
+{
+ A_INT32 i;
+ struct forceROM_s {
+ A_UINT32 addr;
+ A_UINT32 data;
+ };
+ struct forceROM_s *ForceROM;
+ A_INT32 szForceROM;
+ A_STATUS status = A_OK;
+ A_UINT32 address;
+ A_UINT32 data;
+
+ /* Force AR6002 REV1.x to recognize Host presence.
+ *
+ * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0
+ * so that this workaround functions with AR6002.war1.sh. We
+ * could fold that entire workaround into this one, but it's not
+ * worth the effort at this point. This workaround cannot be
+ * merged into the other workaround because this must be done
+ * before BMI.
+ */
+
+ static struct forceROM_s ForceROM_NEW[] = {
+ {0x52df80, 0x20f31c07},
+ {0x52df84, 0x92374420},
+ {0x52df88, 0x1d120c03},
+ {0x52df8c, 0xff8216f0},
+ {0x52df90, 0xf01d120c},
+ {0x52df94, 0x81004136},
+ {0x52df98, 0xbc9100bd},
+ {0x52df9c, 0x00bba100},
+
+ {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */
+ {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380},
+ {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000},
+ {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001},
+
+ {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */
+
+ {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
+ };
+
+ address = 0x004ed4b0; /* REV1 target software ID is stored here */
+ status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+ if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) {
+ return A_ERROR; /* Not AR6002 REV1 */
+ }
+
+ ForceROM = ForceROM_NEW;
+ szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
+
+ ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n"));
+ for (i = 0; i < szForceROM; i++)
+ {
+ if (ar6000_WriteRegDiag(hifDevice,
+ &ForceROM[i].addr,
+ &ForceROM[i].data) != A_OK)
+ {
+ ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n"));
+ return A_ERROR;
+ }
+ }
+
+ A_MDELAY(1000);
+
+ return A_OK;
+}
+
+#endif /* CONFIG_AR6002_REV1_FORCE_HOST */
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
+{
+ A_CHAR stream[60];
+ A_CHAR byteOffsetStr[10];
+ A_UINT32 i;
+ A_UINT16 offset, count, byteOffset;
+
+ A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription);
+
+ count = 0;
+ offset = 0;
+ byteOffset = 0;
+ for(i = 0; i < length; i++) {
+ A_SPRINTF(stream + offset, "%2.2X ", buffer[i]);
+ count ++;
+ offset += 3;
+
+ if(count == 16) {
+ count = 0;
+ offset = 0;
+ A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
+ A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
+ A_MEMZERO(stream, 60);
+ byteOffset += 16;
+ }
+ }
+
+ if(offset != 0) {
+ A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
+ A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
+ }
+
+ A_PRINTF("<------------------------------------------------->\n");
+}
+
+void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
+{
+ int i;
+ ATH_DEBUG_MASK_DESCRIPTION *pDesc;
+
+ if (pInfo == NULL) {
+ return;
+ }
+
+ pDesc = pInfo->pMaskDescriptions;
+
+ A_PRINTF("========================================================\n\n");
+ A_PRINTF("Module Debug Info => Name : %s \n", pInfo->ModuleName);
+ A_PRINTF(" => Descr. : %s \n", pInfo->ModuleDescription);
+ A_PRINTF("\n Current mask => 0x%8.8X \n", pInfo->CurrentMask);
+ A_PRINTF("\n Avail. Debug Masks :\n\n");
+
+ for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) {
+ A_PRINTF(" => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description);
+ }
+
+ if (0 == i) {
+ A_PRINTF(" => * none defined * \n");
+ }
+
+ A_PRINTF("\n Standard Debug Masks :\n\n");
+ /* print standard masks */
+ A_PRINTF(" => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR);
+ A_PRINTF(" => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN);
+ A_PRINTF(" => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO);
+ A_PRINTF(" => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC);
+ A_PRINTF("\n========================================================\n");
+
+}
+
+
+static ATH_DEBUG_MODULE_DBG_INFO *FindModule(A_CHAR *module_name)
+{
+ ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+
+ if (!g_ModuleDebugInit) {
+ return NULL;
+ }
+
+ while (pInfo != NULL) {
+ /* TODO: need to use something other than strlen */
+ if (A_MEMCMP(pInfo->ModuleName,module_name,strlen(module_name)) == 0) {
+ break;
+ }
+ pInfo = pInfo->pNext;
+ }
+
+ return pInfo;
+}
+
+
+void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
+{
+ if (!g_ModuleDebugInit) {
+ return;
+ }
+
+ A_MUTEX_LOCK(&g_ModuleListLock);
+
+ if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) {
+ if (g_pModuleInfoHead == NULL) {
+ g_pModuleInfoHead = pInfo;
+ } else {
+ pInfo->pNext = g_pModuleInfoHead;
+ g_pModuleInfoHead = pInfo;
+ }
+ pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED;
+ }
+
+ A_MUTEX_UNLOCK(&g_ModuleListLock);
+}
+
+void a_dump_module_debug_info_by_name(A_CHAR *module_name)
+{
+ ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+
+ if (!g_ModuleDebugInit) {
+ return;
+ }
+
+ if (A_MEMCMP(module_name,"all",3) == 0) {
+ /* dump all */
+ while (pInfo != NULL) {
+ a_dump_module_debug_info(pInfo);
+ pInfo = pInfo->pNext;
+ }
+ return;
+ }
+
+ pInfo = FindModule(module_name);
+
+ if (pInfo != NULL) {
+ a_dump_module_debug_info(pInfo);
+ }
+
+}
+
+A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask)
+{
+ ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
+
+ if (NULL == pInfo) {
+ return A_ERROR;
+ }
+
+ *pMask = pInfo->CurrentMask;
+ return A_OK;
+}
+
+A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask)
+{
+ ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
+
+ if (NULL == pInfo) {
+ return A_ERROR;
+ }
+
+ pInfo->CurrentMask = Mask;
+ A_PRINTF("Module %s, new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask);
+ return A_OK;
+}
+
+
+void a_module_debug_support_init(void)
+{
+ if (g_ModuleDebugInit) {
+ return;
+ }
+ A_MUTEX_INIT(&g_ModuleListLock);
+ g_pModuleInfoHead = NULL;
+ g_ModuleDebugInit = TRUE;
+ A_REGISTER_MODULE_DEBUG_INFO(misc);
+}
+
+void a_module_debug_support_cleanup(void)
+{
+ ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
+ ATH_DEBUG_MODULE_DBG_INFO *pCur;
+
+ if (!g_ModuleDebugInit) {
+ return;
+ }
+
+ g_ModuleDebugInit = FALSE;
+
+ A_MUTEX_LOCK(&g_ModuleListLock);
+
+ while (pInfo != NULL) {
+ pCur = pInfo;
+ pInfo = pInfo->pNext;
+ pCur->pNext = NULL;
+ /* clear registered flag */
+ pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED;
+ }
+
+ A_MUTEX_UNLOCK(&g_ModuleListLock);
+
+ A_MUTEX_DELETE(&g_ModuleListLock);
+ g_pModuleInfoHead = NULL;
+}
+
+ /* can only be called during bmi init stage */
+A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
+ A_UINT32 TargetType,
+ A_UINT32 Flags)
+{
+ A_STATUS status = A_OK;
+
+ do {
+
+ if (TargetType != TARGET_TYPE_AR6003) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n",
+ TargetType));
+ break;
+ }
+
+ /* set hci bridge flags */
+ status = BMIWriteMemory(hifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags),
+ (A_UCHAR *)&Flags,
+ 4);
+
+
+ } while (FALSE);
+
+ return status;
+}
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c b/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c
new file mode 100644
index 000000000000..74426b8f710a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c
@@ -0,0 +1,375 @@
+//------------------------------------------------------------------------------
+// <copyright file="credit_dist.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#define ATH_MODULE_NAME misc
+#include "a_debug.h"
+#include "htc_api.h"
+#include "common_drv.h"
+
+/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
+
+#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
+
+#ifdef NO_VO_SERVICE
+#define DATA_SVCS_USED 3
+#else
+#define DATA_SVCS_USED 4
+#endif
+
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+/* reduce an ep's credits back to a set limit */
+static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEpDist,
+ int Limit)
+{
+ int credits;
+
+ /* set the new limit */
+ pEpDist->TxCreditsAssigned = Limit;
+
+ if (pEpDist->TxCredits <= Limit) {
+ return;
+ }
+
+ /* figure out how much to take away */
+ credits = pEpDist->TxCredits - Limit;
+ /* take them away */
+ pEpDist->TxCredits -= credits;
+ pCredInfo->CurrentFreeCredits += credits;
+}
+
+/* give an endpoint some credits from the free credit pool */
+#define GiveCredits(pCredInfo,pEpDist,credits) \
+{ \
+ (pEpDist)->TxCredits += (credits); \
+ (pEpDist)->TxCreditsAssigned += (credits); \
+ (pCredInfo)->CurrentFreeCredits -= (credits); \
+}
+
+
+/* default credit init callback.
+ * This function is called in the context of HTCStart() to setup initial (application-specific)
+ * credit distributions */
+static void ar6000_credit_init(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ int TotalCredits)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ int count;
+ COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+ pCredInfo->CurrentFreeCredits = TotalCredits;
+ pCredInfo->TotalAvailableCredits = TotalCredits;
+
+ pCurEpDist = pEPList;
+
+ /* run through the list and initialize */
+ while (pCurEpDist != NULL) {
+
+ /* set minimums for each endpoint */
+ pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+
+ if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+ /* give control service some credits */
+ GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
+ /* control service is always marked active, it never goes inactive EVER */
+ SET_EP_ACTIVE(pCurEpDist);
+ } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
+ /* this is the lowest priority data endpoint, save this off for easy access */
+ pCredInfo->pLowestPriEpDist = pCurEpDist;
+ }
+
+ /* Streams have to be created (explicit | implicit)for all kinds
+ * of traffic. BE endpoints are also inactive in the beginning.
+ * When BE traffic starts it creates implicit streams that
+ * redistributes credits.
+ */
+
+ /* note, all other endpoints have minimums set but are initially given NO credits.
+ * Credits will be distributed as traffic activity demands */
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+ if (pCredInfo->CurrentFreeCredits <= 0) {
+ AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
+ A_ASSERT(FALSE);
+ return;
+ }
+
+ /* reset list */
+ pCurEpDist = pEPList;
+ /* now run through the list and set max operating credit limits for everyone */
+ while (pCurEpDist != NULL) {
+ if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+ /* control service max is just 1 max message */
+ pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
+ } else {
+ /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
+ * the same.
+ * We use a simple calculation here, we take the remaining credits and
+ * determine how many max messages this can cover and then set each endpoint's
+ * normal value equal to 3/4 this amount.
+ * */
+ count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
+ count = (count * 3) >> 2;
+ count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
+ /* set normal */
+ pCurEpDist->TxCreditsNorm = count;
+
+ }
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+}
+
+
+/* default credit distribution callback
+ * This callback is invoked whenever endpoints require credit distributions.
+ * A lock is held while this function is invoked, this function shall NOT block.
+ * The pEPDistList is a list of distribution structures in prioritized order as
+ * defined by the call to the HTCSetCreditDistribution() api.
+ *
+ */
+static void ar6000_credit_distribute(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+ HTC_CREDIT_DIST_REASON Reason)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+ switch (Reason) {
+ case HTC_CREDIT_DIST_SEND_COMPLETE :
+ pCurEpDist = pEPDistList;
+ /* we are given the start of the endpoint distribution list.
+ * There may be one or more endpoints to service.
+ * Run through the list and distribute credits */
+ while (pCurEpDist != NULL) {
+
+ if (pCurEpDist->TxCreditsToDist > 0) {
+ /* return the credits back to the endpoint */
+ pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+ /* always zero out when we are done */
+ pCurEpDist->TxCreditsToDist = 0;
+
+ if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
+ /* reduce to the assigned limit, previous credit reductions
+ * could have caused the limit to change */
+ ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
+ }
+
+ if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
+ /* oversubscribed endpoints need to reduce back to normal */
+ ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
+ }
+
+ if (!IS_EP_ACTIVE(pCurEpDist)) {
+ /* endpoint is inactive, now check for messages waiting for credits */
+ if (pCurEpDist->TxQueueDepth == 0) {
+ /* EP is inactive and there are no pending messages,
+ * reduce credits back to zero to recover credits */
+ ReduceCredits(pCredInfo, pCurEpDist, 0);
+ }
+ }
+ }
+
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+ break;
+
+ case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
+ RedistributeCredits(pCredInfo,pEPDistList);
+ break;
+ case HTC_CREDIT_DIST_SEEK_CREDITS :
+ SeekCredits(pCredInfo,pEPDistList);
+ break;
+ case HTC_DUMP_CREDIT_STATE :
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n",
+ pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
+ break;
+ default:
+ break;
+
+ }
+
+ /* sanity checks done after each distribution action */
+ A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
+ A_ASSERT(pCredInfo->CurrentFreeCredits >= 0);
+
+}
+
+/* redistribute credits based on activity change */
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList;
+
+ /* walk through the list and remove credits from inactive endpoints */
+ while (pCurEpDist != NULL) {
+
+ if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
+ if (!IS_EP_ACTIVE(pCurEpDist)) {
+ if (pCurEpDist->TxQueueDepth == 0) {
+ /* EP is inactive and there are no pending messages, reduce credits back to zero */
+ ReduceCredits(pCredInfo, pCurEpDist, 0);
+ } else {
+ /* we cannot zero the credits assigned to this EP, but to keep
+ * the credits available for these leftover packets, reduce to
+ * a minimum */
+ ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin);
+ }
+ }
+ }
+
+ /* NOTE in the active case, we do not need to do anything further,
+ * when an EP goes active and needs credits, HTC will call into
+ * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */
+
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+}
+
+/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ int credits = 0;
+ int need;
+
+ do {
+
+ if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
+ /* we never oversubscribe on the control service, this is not
+ * a high performance path and the target never holds onto control
+ * credits for too long */
+ break;
+ }
+
+ if (pEPDist->ServiceID == WMI_DATA_VI_SVC) {
+ if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
+ (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
+ /* limit VI service from oversubscribing */
+ /* at least one free credit will not be used by VI */
+ break;
+ }
+ }
+
+ if (pEPDist->ServiceID == WMI_DATA_VO_SVC) {
+ if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) ||
+ (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) {
+ /* limit VO service from oversubscribing */
+ /* at least one free credit will not be used by VO */
+ break;
+ }
+ }
+
+ /* for all other services, we follow a simple algorithm of
+ * 1. checking the free pool for credits
+ * 2. checking lower priority endpoints for credits to take */
+
+ /* give what we can */
+ credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+ if (credits >= pEPDist->TxCreditsSeek) {
+ /* we found some to fullfill the seek request */
+ break;
+ }
+
+ /* we don't have enough in the free pool, try taking away from lower priority services
+ *
+ * The rule for taking away credits:
+ * 1. Only take from lower priority endpoints
+ * 2. Only take what is allocated above the minimum (never starve an endpoint completely)
+ * 3. Only take what you need.
+ *
+ * */
+
+ /* starting at the lowest priority */
+ pCurEpDist = pCredInfo->pLowestPriEpDist;
+
+ /* work backwards until we hit the endpoint again */
+ while (pCurEpDist != pEPDist) {
+ /* calculate how many we need so far */
+ need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
+
+ if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) {
+ /* the current one has been allocated more than it's minimum and it
+ * has enough credits assigned above it's minimum to fullfill our need
+ * try to take away just enough to fullfill our need */
+ ReduceCredits(pCredInfo,
+ pCurEpDist,
+ pCurEpDist->TxCreditsAssigned - need);
+
+ if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
+ /* we have enough */
+ break;
+ }
+ }
+
+ pCurEpDist = pCurEpDist->pPrev;
+ }
+
+ /* return what we can get */
+ credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+ } while (FALSE);
+
+ /* did we find some credits? */
+ if (credits) {
+ /* give what we can */
+ GiveCredits(pCredInfo, pEPDist, credits);
+ }
+
+}
+
+/* initialize and setup credit distribution */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo)
+{
+ HTC_SERVICE_ID servicepriority[5];
+
+ A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO));
+
+ servicepriority[0] = WMI_CONTROL_SVC; /* highest */
+ servicepriority[1] = WMI_DATA_VO_SVC;
+ servicepriority[2] = WMI_DATA_VI_SVC;
+ servicepriority[3] = WMI_DATA_BE_SVC;
+ servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
+
+ /* set callbacks and priority list */
+ HTCSetCreditDistribution(HTCHandle,
+ pCredInfo,
+ ar6000_credit_distribute,
+ ar6000_credit_init,
+ servicepriority,
+ 5);
+
+ return A_OK;
+}
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/makefile b/drivers/net/wireless/ath6kl/miscdrv/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h b/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h
new file mode 100644
index 000000000000..c72f116dbe04
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+// <copyright file="miscdrv.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _MISCDRV_H
+#define _MISCDRV_H
+
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
+(((target) == TARGET_TYPE_AR6001) ? \
+ AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+A_UINT32 ar6kRev2Array[][128] = {
+ {0xFFFF, 0xFFFF}, // No Patches
+ };
+
+#define CFG_REV2_ITEMS 0 // no patches so far
+#define AR6K_RESET_ADDR 0x4000
+#define AR6K_RESET_VAL 0x100
+
+#define EEPROM_SZ 768
+#define EEPROM_WAIT_LIMIT 4
+
+#endif
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
new file mode 100644
index 000000000000..1ca77e513493
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c
@@ -0,0 +1,621 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+#include "ar6000_drv.h"
+#include "htc.h"
+#include <linux/vmalloc.h>
+
+#include <linux/fs.h>
+#ifdef CONFIG_PM
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+#include <linux/wakelock.h>
+#endif
+enum {
+ WLAN_PWR_CTRL_UP = 0,
+ WLAN_PWR_CTRL_CUT_PWR,
+ WLAN_PWR_CTRL_DEEP_SLEEP,
+ WLAN_PWR_CTRL_WOW
+};
+#include <linux/platform_device.h>
+#include <linux/inetdevice.h>
+
+#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0)
+#define MAX_BUF (8*1024)
+
+#ifdef DEBUG
+
+#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+static ATH_DEBUG_MASK_DESCRIPTION android_debug_desc[] = {
+ { ATH_DEBUG_DBG_LOG , "Android Debug Logs"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(android,
+ "android",
+ "Android Driver Interface",
+ ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_DBG_LOG,
+ ATH_DEBUG_DESCRIPTION_COUNT(android_debug_desc),
+ android_debug_desc);
+
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+char fwpath[256] = "/system/wifi";
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
+int buspm = WLAN_PWR_CTRL_CUT_PWR;
+int wow2mode = WLAN_PWR_CTRL_CUT_PWR;
+#define HAVE_WLAN_PWR_IMPL 0
+#if HAVE_WLAN_PWR_IMPL
+/** @brief Disable SDIO clock source and mask all interrupt */
+extern void plat_disable_wlan_slot(void);
+/** @brief Enable SDIO clock source and unmask all interrupt */
+extern void plat_enable_wlan_slot(void);
+#else
+#define plat_disable_wlan_slot()
+#define plat_enable_wlan_slot()
+#endif
+
+#endif /* CONFIG_PM */
+extern int bmienable;
+extern int wlaninitmode;
+extern unsigned int wmitimeout;
+extern wait_queue_head_t arEvent;
+extern struct net_device *ar6000_devices[];
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+extern unsigned int testmode;
+#endif
+extern char ifname[];
+
+const char def_ifname[] = "wlan0";
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
+module_param(buspm, int, 0644);
+#else
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(buspm,"i");
+#endif
+
+struct wake_lock ar6k_init_wake_lock;
+struct wake_lock ar6k_wow_wake_lock;
+static A_STATUS (*ar6000_avail_ev_p)(void *, void *);
+
+extern int ar6000_init(struct net_device *dev);
+extern A_STATUS ar6000_configure_target(AR_SOFTC_T *ar);
+extern void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile);
+extern A_STATUS ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode);
+extern void ar6000_destroy(struct net_device *dev, unsigned int unregister);
+
+static void ar6000_enable_mmchost_detect_change(int enable);
+static void ar6000_restart_endpoint(struct net_device *dev);
+
+#if defined(CONFIG_PM)
+static A_STATUS ar6000_suspend_ev(void *context);
+
+static A_STATUS ar6000_resume_ev(void *context);
+#endif
+
+int android_request_firmware(const struct firmware **firmware_p, const char *name,
+ struct device *device)
+{
+ struct file *filp = (struct file *)-ENOENT;
+ int ret = 0;
+ mm_segment_t oldfs;
+ struct firmware *firmware;
+ char filename[2048];
+#if 0
+ const char *raw_filename = strrchr(name, '/');
+#else
+ const char *raw_filename = NULL;
+#endif
+ *firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
+ if (!firmware)
+ return -ENOMEM;
+ if (raw_filename)
+ ++raw_filename;
+ else
+ raw_filename = name;
+ sprintf(filename, "%s/%s", fwpath, raw_filename);
+ // Open file
+ oldfs = get_fs();
+ set_fs(KERNEL_DS);
+ do {
+ size_t length, bufsize, bmisize;
+ struct inode *inode;
+ filp = filp_open(filename, O_RDONLY, S_IRUSR);
+ if (IS_ERR(filp) || !filp->f_op) {
+ printk("%s: file %s filp_open error\n", __FUNCTION__, filename);
+ ret = -1;
+ break;
+ }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ inode = filp->f_path.dentry->d_inode;
+#else
+ inode = filp->f_dentry->d_inode;
+#endif
+ if (!inode) {
+ printk("%s: Get inode from filp failed\n", __FUNCTION__);
+ ret = -1;
+ break;
+ }
+ length = i_size_read(inode->i_mapping->host);
+ bufsize = ALIGN(length, PAGE_SIZE);
+ bmisize = A_ROUND_UP(length, 4);
+ bufsize = max(bmisize, bufsize);
+ firmware->data = vmalloc(bufsize);
+ firmware->size = bmisize;
+ if (!firmware->data) {
+ printk("Cannot allocate buffer for firmware\n");
+ ret = -ENOMEM;
+ break;
+ }
+ if (filp->f_op->read(filp, (char*)firmware->data, length, &filp->f_pos) != length) {
+ printk("%s: file read error, remaining=%d\n", __FUNCTION__, length);
+ ret = -1;
+ break;
+ }
+ } while (0);
+
+ if (!IS_ERR(filp)) {
+ filp_close(filp, NULL);
+ }
+ set_fs(oldfs);
+
+ if (ret!=0) {
+ if (firmware) {
+ if (firmware->data)
+ vfree(firmware->data);
+ kfree(firmware);
+ }
+ *firmware_p = NULL;
+ }
+ return ret;
+}
+
+void android_release_firmware(const struct firmware *firmware)
+{
+ if (firmware) {
+ if (firmware->data)
+ vfree(firmware->data);
+ kfree(firmware);
+ }
+}
+
+#if defined(CONFIG_PM)
+static void ar6k_send_asleep_event_to_app(AR_SOFTC_T *ar, A_BOOL asleep)
+{
+ char buf[128];
+ union iwreq_data wrqu;
+
+ snprintf(buf, sizeof(buf), "HOST_ASLEEP=%s", asleep ? "asleep" : "awake");
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+static void ar6000_wow_resume(AR_SOFTC_T *ar)
+{
+ if (ar->arWowState) {
+ WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {TRUE, FALSE};
+ ar->arWowState = 0;
+ wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode);
+ wmi_scanparams_cmd(ar->arWmi, 0,0,60,0,0,0,0,0,0,0);
+ //wmi_set_keepalive_cmd(ar->arWmi, 0);
+
+#if 1 /* we don't do it if the power consumption is already good enough. */
+ if (wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0) == A_OK) {
+ }
+#endif
+ ar6k_send_asleep_event_to_app(ar, FALSE);
+ if (ar->arTxPending[ar->arControlEp]) {
+ long timeleft = wait_event_interruptible_timeout(arEvent,
+ ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
+ if (!timeleft || signal_pending(current)) {
+ printk("Failed to Resume Wow!!!!!!!!!!!!!!!!!!!!\n");
+ } else {
+ printk("Resume WoW successfully\n");
+ }
+ }
+ } else {
+ printk("WoW does not invoked. skip resume");
+ }
+}
+
+static void ar6000_wow_suspend(AR_SOFTC_T *ar)
+{
+#define ANDROID_WOW_LIST_ID 1
+ if (ar->arNetworkType != AP_NETWORK) {
+ /* Setup WoW for unicast & Aarp request for our own IP
+ disable background scan. Set listen interval into 1000 TUs
+ Enable keepliave for 110 seconds
+ */
+ struct in_ifaddr **ifap = NULL;
+ struct in_ifaddr *ifa = NULL;
+ struct in_device *in_dev;
+ A_UINT8 macMask[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+ A_STATUS status;
+ WMI_ADD_WOW_PATTERN_CMD addWowCmd = { .filter = { 0 } };
+ WMI_DEL_WOW_PATTERN_CMD delWowCmd;
+ WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {FALSE, TRUE};
+ WMI_SET_WOW_MODE_CMD wowMode = { .enable_wow = TRUE };
+
+ ar6000_TxDataCleanup(ar); /* IMPORTANT, otherwise there will be 11mA after listen interval as 1000*/
+
+#if 1 /* we don't do it if the power consumption is already good enough. */
+ if (wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0) == A_OK) {
+ }
+#endif
+
+// wmi_set_keepalive_cmd(ar->arWmi, 110); /* keepalive otherwise, we will be disconnected*/
+ status = wmi_scanparams_cmd(ar->arWmi, 0,0,0xffff,0,0,0,0,0,0,0);
+ wmi_set_wow_mode_cmd(ar->arWmi, &wowMode);
+
+ /* clear up our WoW pattern first */
+ delWowCmd.filter_list_id = ANDROID_WOW_LIST_ID;
+ delWowCmd.filter_id = 0;
+ wmi_del_wow_pattern_cmd(ar->arWmi, &delWowCmd);
+
+ /* setup unicast packet pattern for WoW */
+ if (ar->arNetDev->dev_addr[1]) {
+ addWowCmd.filter_list_id = ANDROID_WOW_LIST_ID;
+ addWowCmd.filter_size = 6; /* MAC address */
+ addWowCmd.filter_offset = 2;
+ status = wmi_add_wow_pattern_cmd(ar->arWmi, &addWowCmd, ar->arNetDev->dev_addr, macMask, addWowCmd.filter_size);
+ }
+ /* setup ARP request for our own IP */
+ if ((in_dev = __in_dev_get_rtnl(ar->arNetDev)) != NULL) {
+ for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL; ifap = &ifa->ifa_next) {
+ if (!strcmp(ar->arNetDev->name, ifa->ifa_label)) {
+ break; /* found */
+ }
+ }
+ }
+ if (ifa && ifa->ifa_local) {
+ WMI_SET_IP_CMD ipCmd;
+ memset(&ipCmd, 0, sizeof(ipCmd));
+ ipCmd.ips[0] = ifa->ifa_local;
+ status = wmi_set_ip_cmd(ar->arWmi, &ipCmd);
+ }
+ ar6k_send_asleep_event_to_app(ar, TRUE);
+ wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode);
+ if (ar->arTxPending[ar->arControlEp]) {
+ long timeleft = wait_event_interruptible_timeout(arEvent,
+ ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ);
+ if (!timeleft || signal_pending(current)) {
+ /* what can I do? wow resume at once */
+ printk("Fail to setup WoW\n");
+ } else {
+ ar->arWowState = 1;
+ printk("Setup WoW successfully\n");
+ }
+ }
+ mdelay(10);
+ } else {
+ printk("Not allowed to go to WOW at this moment.\n");
+ }
+}
+
+static void ar6000_pwr_on(AR_SOFTC_T *ar)
+{
+ if (ar == NULL) {
+ /* turn on for all cards */
+ }
+ printk("%s --enter\n", __func__);
+
+}
+
+static void ar6000_pwr_down(AR_SOFTC_T *ar)
+{
+ if (ar == NULL) {
+ /* shutdown for all cards */
+ }
+ printk("%s --enter\n", __func__);
+
+}
+
+static A_STATUS ar6000_suspend_ev(void *context)
+{
+ int pmmode = buspm;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+ printk("%s: enter ar %p devices %p\n", __func__, ar, ar6000_devices[0]? netdev_priv(ar6000_devices[0]) : NULL);
+
+wow_not_connected:
+
+ switch (pmmode) {
+ case WLAN_PWR_CTRL_DEEP_SLEEP:
+ ar6000_set_wlan_state(ar, WLAN_DISABLED);
+ ar->arOsPowerCtrl = WLAN_PWR_CTRL_DEEP_SLEEP;
+ return A_EBUSY;
+ case WLAN_PWR_CTRL_WOW:
+ if (ar->arWmiReady && ar->arWlanState==WLAN_ENABLED && ar->arConnected) {
+ ar->arOsPowerCtrl = WLAN_PWR_CTRL_WOW;
+ /* leave for pm_device to setup wow */
+ return A_EBUSY;
+ } else {
+ pmmode = wow2mode;
+ goto wow_not_connected;
+ }
+ break;
+ case WLAN_PWR_CTRL_CUT_PWR:
+ /* fall through */
+ default:
+ ar->arOsPowerCtrl = WLAN_PWR_CTRL_CUT_PWR;
+ ar6000_stop_endpoint(ar->arNetDev, TRUE);
+ ar->arWlanState = WLAN_DISABLED;
+ break;
+ }
+ return A_OK;
+}
+
+static A_STATUS ar6000_resume_ev(void *context)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+ A_UINT16 powerCtrl = ar->arOsPowerCtrl;
+ wake_lock(&ar6k_init_wake_lock);
+ printk("%s: enter\n", __func__);
+ ar->arOsPowerCtrl = WLAN_PWR_CTRL_UP;
+ switch (powerCtrl) {
+ case WLAN_PWR_CTRL_WOW:
+ printk("Warning! resume but osPowerCtl is not clear\n");
+ break;
+ case WLAN_PWR_CTRL_CUT_PWR:
+ ar6000_restart_endpoint(ar->arNetDev);
+ break;
+ case WLAN_PWR_CTRL_DEEP_SLEEP:
+ ar6000_set_wlan_state(ar, WLAN_ENABLED);
+ break;
+ default:
+ printk("Strange SDIO bus power mode!!\n");
+ break;
+ }
+ wake_unlock(&ar6k_init_wake_lock);
+ return A_OK;
+}
+
+static A_STATUS ar6000_android_avail_ev(void *context, void *hif_handle)
+{
+ A_STATUS ret;
+ wake_lock(&ar6k_init_wake_lock);
+ ret = ar6000_avail_ev_p(context, hif_handle);
+ wake_unlock(&ar6k_init_wake_lock);
+ return ret;
+}
+
+
+static int ar6000_pm_suspend(struct platform_device *dev, pm_message_t state)
+{
+ int i;
+ for (i = 0; i < MAX_AR6000; i++) {
+ AR_SOFTC_T *ar;
+
+ if (ar6000_devices[i] == NULL)
+ continue;
+ ar = (AR_SOFTC_T*)netdev_priv(ar6000_devices[i]);
+ printk("%s: enter\n", __func__);
+ switch (ar->arOsPowerCtrl) {
+ case WLAN_PWR_CTRL_CUT_PWR:
+ ar6000_pwr_down(ar);
+ break;
+ case WLAN_PWR_CTRL_WOW:
+ ar6000_wow_suspend(ar);
+ plat_disable_wlan_slot();
+ break;
+ case WLAN_PWR_CTRL_DEEP_SLEEP:
+ /* nothing to do. keep the power on */
+ break;
+ default:
+ printk("Something is strange for ar6000_pm_suspend %d\n", ar->arOsPowerCtrl);
+ break;
+ }
+ }
+ return 0;
+}
+
+static int ar6000_pm_resume(struct platform_device *dev)
+{
+ int i;
+ for (i = 0; i < MAX_AR6000; i++) {
+ AR_SOFTC_T *ar;
+
+ if (ar6000_devices[i] == NULL)
+ continue;
+ printk("%s: enter\n", __func__);
+ ar = (AR_SOFTC_T*)netdev_priv(ar6000_devices[i]);
+ switch (ar->arOsPowerCtrl) {
+ case WLAN_PWR_CTRL_CUT_PWR:
+ ar6000_pwr_on(ar);
+ break;
+ case WLAN_PWR_CTRL_WOW:
+ wake_lock_timeout(&ar6k_wow_wake_lock, 3*HZ);
+ plat_enable_wlan_slot();
+ ar6000_wow_resume(ar);
+ ar->arOsPowerCtrl = WLAN_PWR_CTRL_UP;
+ break;
+ case WLAN_PWR_CTRL_DEEP_SLEEP:
+ /* nothing to do. keep the power on */
+ break;
+ default:
+ printk("Something is strange for ar6000_pm_resume %d\n", ar->arOsPowerCtrl);
+ break;
+ }
+ }
+ return 0;
+}
+
+static int ar6000_pm_probe(struct platform_device *pdev)
+{
+ ar6000_pwr_on(NULL);
+ return 0;
+}
+
+static int ar6000_pm_remove(struct platform_device *pdev)
+{
+ ar6000_pwr_down(NULL);
+ return 0;
+}
+
+static struct platform_driver ar6000_pm_device = {
+ .probe = ar6000_pm_probe,
+ .remove = ar6000_pm_remove,
+ .suspend = ar6000_pm_suspend,
+ .resume = ar6000_pm_resume,
+ .driver = {
+ .name = "wlan_ar6000_pm_dev",
+ },
+};
+#endif /* CONFIG_PM */
+
+/* Useful for qualcom platform to detect our wlan card for mmc stack */
+static void ar6000_enable_mmchost_detect_change(int enable)
+{
+#ifdef CONFIG_MMC_MSM
+ mm_segment_t oldfs;
+ struct file *filp = (struct file*)-ENOENT;
+ int length;
+ oldfs = get_fs();
+ set_fs(KERNEL_DS);
+ do {
+ char buf[3];
+ filp = filp_open("/sys/devices/platform/msm_sdcc.2/detect_change", O_RDWR, S_IRUSR);
+ if (IS_ERR(filp) || !filp->f_op)
+ break;
+ length = snprintf(buf, sizeof(buf), "%d\n", enable ? 1 : 0);
+ if (filp->f_op->write(filp, buf, length, &filp->f_pos) != length) {
+ break;
+ }
+ } while (0);
+ if (!IS_ERR(filp)) {
+ filp_close(filp, NULL);
+ }
+ set_fs(oldfs);
+#endif
+}
+
+static void
+ar6000_restart_endpoint(struct net_device *dev)
+{
+ A_STATUS status = A_OK;
+ AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev);
+ if (down_interruptible(&ar->arSem)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s(): down_interruptible failed \n", __func__));
+ return ;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return;
+ }
+ BMIInit();
+ do {
+ A_BOOL rtnl_lock_held_on_entry;
+ if ( (status=ar6000_configure_target(ar))!=A_OK)
+ break;
+ if ( (status=ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
+ break;
+ }
+ rtnl_lock_held_on_entry = rtnl_trylock();
+ status = (ar6000_init(dev)==0) ? A_OK : A_ERROR;
+ if (rtnl_lock_held_on_entry) {
+ rtnl_unlock();
+ }
+ if (status!=A_OK) {
+ break;
+ }
+ ar->arWlanState = WLAN_ENABLED;
+ if (ar->arSsidLen) {
+ ar6000_connect_to_ap(ar);
+ }
+ } while (0);
+
+ up(&ar->arSem);
+ if (status==A_OK) {
+ return;
+ }
+
+ ar6000_devices[ar->arDeviceIndex] = NULL;
+ ar6000_destroy(ar->arNetDev, 1);
+}
+
+void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks)
+{
+ ar6000_enable_mmchost_detect_change(1);
+ bmienable = 1;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ if (ifname[0] == '\0')
+ strcpy(ifname, def_ifname);
+#endif
+ if (wow2mode!=WLAN_PWR_CTRL_CUT_PWR && wow2mode!=WLAN_PWR_CTRL_DEEP_SLEEP) {
+ wow2mode=WLAN_PWR_CTRL_CUT_PWR;
+ }
+
+ wake_lock_init(&ar6k_init_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_init");
+ wake_lock_init(&ar6k_wow_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_wow");
+
+#if defined(CONFIG_PM)
+ osdrvCallbacks->deviceSuspendHandler = ar6000_suspend_ev;
+ osdrvCallbacks->deviceResumeHandler = ar6000_resume_ev;
+#endif
+ ar6000_avail_ev_p = osdrvCallbacks->deviceInsertedHandler;
+ osdrvCallbacks->deviceInsertedHandler = ar6000_android_avail_ev;
+
+#if defined(CONFIG_PM)
+ /* Register ar6000_pm_device into system.
+ * We should also add platform_device into the first item of array devices[] in
+ * file arch/xxx/mach-xxx/board-xxxx.c
+ * Otherwise, WoW may not work properly since we may trigger WoW GPIO before system suspend
+ */
+ if (platform_driver_register(&ar6000_pm_device))
+ printk("ar6000: fail to register the power control driver.\n");
+#endif
+}
+
+void android_module_exit(void)
+{
+ wake_lock_destroy(&ar6k_wow_wake_lock);
+ wake_lock_destroy(&ar6k_init_wake_lock);
+
+#ifdef CONFIG_PM
+ platform_driver_unregister(&ar6000_pm_device);
+#endif
+ ar6000_enable_mmchost_detect_change(1);
+}
+
+A_BOOL android_ar6k_endpoint_is_stop(AR_SOFTC_T *ar)
+{
+#ifdef CONFIG_PM
+ return ar->arOsPowerCtrl == WLAN_PWR_CTRL_CUT_PWR;
+#else
+ return FALSE;
+#endif
+}
+
+void android_ar6k_check_wow_status(AR_SOFTC_T *ar)
+{
+#ifdef CONFIG_PM
+ if (ar->arWowState) {
+ ar6000_wow_resume(ar);
+ }
+#endif /* CONFIG_PM */
+}
+
+A_STATUS android_ar6k_start(AR_SOFTC_T *ar)
+{
+ return A_OK;
+}
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c
new file mode 100644
index 000000000000..68b2ebf655ee
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c
@@ -0,0 +1,6311 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+/*
+ * This driver is a pseudo ethernet driver to access the Atheros AR6000
+ * WLAN Device
+ */
+
+#include "ar6000_drv.h"
+#ifdef ATH6K_CONFIG_CFG80211
+#include "cfg80211.h"
+#endif /* ATH6K_CONFIG_CFG80211 */
+#include "htc.h"
+#include "wmi_filter_linux.h"
+#include "epping_test.h"
+#include "wlan_config.h"
+#include "ar3kconfig.h"
+
+
+/* LINUX_HACK_FUDGE_FACTOR -- this is used to provide a workaround for linux behavior. When
+ * the meta data was added to the header it was found that linux did not correctly provide
+ * enough headroom. However when more headroom was requested beyond what was truly needed
+ * Linux gave the requested headroom. Therefore to get the necessary headroom from Linux
+ * the driver requests more than is needed by the amount = LINUX_HACK_FUDGE_FACTOR */
+#define LINUX_HACK_FUDGE_FACTOR 16
+
+A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+
+#ifdef DEBUG
+
+#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define ATH_DEBUG_WLAN_CONNECT ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define ATH_DEBUG_WLAN_SCAN ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define ATH_DEBUG_WLAN_TX ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define ATH_DEBUG_WLAN_RX ATH_DEBUG_MAKE_MODULE_MASK(4)
+#define ATH_DEBUG_HTC_RAW ATH_DEBUG_MAKE_MODULE_MASK(5)
+#define ATH_DEBUG_HCI_BRIDGE ATH_DEBUG_MAKE_MODULE_MASK(6)
+
+static ATH_DEBUG_MASK_DESCRIPTION driver_debug_desc[] = {
+ { ATH_DEBUG_DBG_LOG , "Target Debug Logs"},
+ { ATH_DEBUG_WLAN_CONNECT , "WLAN connect"},
+ { ATH_DEBUG_WLAN_SCAN , "WLAN scan"},
+ { ATH_DEBUG_WLAN_TX , "WLAN Tx"},
+ { ATH_DEBUG_WLAN_RX , "WLAN Rx"},
+ { ATH_DEBUG_HTC_RAW , "HTC Raw IF tracing"},
+ { ATH_DEBUG_HCI_BRIDGE , "HCI Bridge Setup"},
+ { ATH_DEBUG_HCI_RECV , "HCI Recv tracing"},
+ { ATH_DEBUG_HCI_SEND , "HCI Send tracing"},
+ { ATH_DEBUG_HCI_DUMP , "HCI Packet dumps"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(driver,
+ "driver",
+ "Linux Driver Interface",
+ ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_WLAN_SCAN |
+ ATH_DEBUG_HCI_BRIDGE,
+ ATH_DEBUG_DESCRIPTION_COUNT(driver_debug_desc),
+ driver_debug_desc);
+
+#endif
+
+
+#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0)
+#define IS_MAC_BCAST(mac) (*mac==0xff)
+
+MODULE_LICENSE("GPL and additional rights");
+
+#ifndef REORG_APTC_HEURISTICS
+#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#endif /* REORG_APTC_HEURISTICS */
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */
+#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */
+#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */
+
+typedef struct aptc_traffic_record {
+ A_BOOL timerScheduled;
+ struct timeval samplingTS;
+ unsigned long bytesReceived;
+ unsigned long bytesTransmitted;
+} APTC_TRAFFIC_RECORD;
+
+A_TIMER aptcTimer;
+APTC_TRAFFIC_RECORD aptcTR;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+// callbacks registered by HCI transport driver
+HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks = { NULL };
+#endif
+
+unsigned int processDot11Hdr = 0;
+int bmienable = BMIENABLE_DEFAULT;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+char ifname[IFNAMSIZ] = {0,};
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
+
+int wlaninitmode = WLAN_INIT_MODE_DEFAULT;
+unsigned int bypasswmi = 0;
+unsigned int debuglevel = 0;
+int tspecCompliance = ATHEROS_COMPLIANCE;
+unsigned int busspeedlow = 0;
+unsigned int onebitmode = 0;
+unsigned int skipflash = 0;
+unsigned int wmitimeout = 2;
+unsigned int wlanNodeCaching = 1;
+unsigned int enableuartprint = ENABLEUARTPRINT_DEFAULT;
+unsigned int logWmiRawMsgs = 0;
+unsigned int enabletimerwar = 0;
+unsigned int fwmode = 1;
+unsigned int mbox_yield_limit = 99;
+unsigned int enablerssicompensation = 0;
+int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF;
+int allow_trace_signal = 0;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+unsigned int testmode =0;
+#endif
+
+unsigned int irqprocmode = HIF_DEVICE_IRQ_SYNC_ONLY;//HIF_DEVICE_IRQ_ASYNC_SYNC;
+unsigned int panic_on_assert = 1;
+unsigned int nohifscattersupport = NOHIFSCATTERSUPPORT_DEFAULT;
+
+unsigned int setuphci = SETUPHCI_DEFAULT;
+unsigned int loghci = 0;
+unsigned int setupbtdev = SETUPBTDEV_DEFAULT;
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+unsigned int ar3khcibaud = AR3KHCIBAUD_DEFAULT;
+unsigned int hciuartscale = HCIUARTSCALE_DEFAULT;
+unsigned int hciuartstep = HCIUARTSTEP_DEFAULT;
+#endif
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+unsigned int csumOffload=0;
+unsigned int csumOffloadTest=0;
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_string(ifname, ifname, sizeof(ifname), 0644);
+module_param(wlaninitmode, int, 0644);
+module_param(bmienable, int, 0644);
+module_param(bypasswmi, uint, 0644);
+module_param(debuglevel, uint, 0644);
+module_param(tspecCompliance, int, 0644);
+module_param(onebitmode, uint, 0644);
+module_param(busspeedlow, uint, 0644);
+module_param(skipflash, uint, 0644);
+module_param(wmitimeout, uint, 0644);
+module_param(wlanNodeCaching, uint, 0644);
+module_param(logWmiRawMsgs, uint, 0644);
+module_param(enableuartprint, uint, 0644);
+module_param(enabletimerwar, uint, 0644);
+module_param(fwmode, uint, 0644);
+module_param(mbox_yield_limit, uint, 0644);
+module_param(reduce_credit_dribble, int, 0644);
+module_param(allow_trace_signal, int, 0644);
+module_param(enablerssicompensation, uint, 0644);
+module_param(processDot11Hdr, uint, 0644);
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+module_param(csumOffload, uint, 0644);
+#endif
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+module_param(testmode, uint, 0644);
+#endif
+module_param(irqprocmode, uint, 0644);
+module_param(nohifscattersupport, uint, 0644);
+module_param(panic_on_assert, uint, 0644);
+module_param(setuphci, uint, 0644);
+module_param(loghci, uint, 0644);
+module_param(setupbtdev, uint, 0644);
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+module_param(ar3khcibaud, uint, 0644);
+module_param(hciuartscale, uint, 0644);
+module_param(hciuartstep, uint, 0644);
+#endif
+#else
+
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(bmienable,"i");
+MODULE_PARM(wlaninitmode,"i");
+MODULE_PARM(bypasswmi,"i");
+MODULE_PARM(debuglevel, "i");
+MODULE_PARM(onebitmode,"i");
+MODULE_PARM(busspeedlow, "i");
+MODULE_PARM(skipflash, "i");
+MODULE_PARM(wmitimeout, "i");
+MODULE_PARM(wlanNodeCaching, "i");
+MODULE_PARM(enableuartprint,"i");
+MODULE_PARM(logWmiRawMsgs, "i");
+MODULE_PARM(enabletimerwar,"i");
+MODULE_PARM(fwmode,"i");
+MODULE_PARM(mbox_yield_limit,"i");
+MODULE_PARM(reduce_credit_dribble,"i");
+MODULE_PARM(allow_trace_signal,"i");
+MODULE_PARM(enablerssicompensation,"i");
+MODULE_PARM(processDot11Hdr,"i");
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+MODULE_PARM(csumOffload,"i");
+#endif
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+MODULE_PARM(testmode, "i");
+#endif
+MODULE_PARM(irqprocmode, "i");
+MODULE_PARM(nohifscattersupport, "i");
+MODULE_PARM(panic_on_assert, "i");
+MODULE_PARM(setuphci, "i");
+MODULE_PARM(loghci, "i");
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)
+/* in 2.6.10 and later this is now a pointer to a uint */
+unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
+#define mboxnum &_mboxnum
+#else
+unsigned int mboxnum = HTC_MAILBOX_NUM_MAX;
+#endif
+
+#ifdef DEBUG
+A_UINT32 g_dbg_flags = DBG_DEFAULTS;
+unsigned int debugflags = 0;
+int debugdriver = 0;
+unsigned int debughtc = 0;
+unsigned int debugbmi = 0;
+unsigned int debughif = 0;
+unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(debugflags, uint, 0644);
+module_param(debugdriver, int, 0644);
+module_param(debughtc, uint, 0644);
+module_param(debugbmi, uint, 0644);
+module_param(debughif, uint, 0644);
+module_param_array(txcreditsavailable, uint, mboxnum, 0644);
+module_param_array(txcreditsconsumed, uint, mboxnum, 0644);
+module_param_array(txcreditintrenable, uint, mboxnum, 0644);
+module_param_array(txcreditintrenableaggregate, uint, mboxnum, 0644);
+#else
+/* linux 2.4 and lower */
+MODULE_PARM(debugflags,"i");
+MODULE_PARM(debugdriver, "i");
+MODULE_PARM(debughtc, "i");
+MODULE_PARM(debugbmi, "i");
+MODULE_PARM(debughif, "i");
+MODULE_PARM(txcreditsavailable, "0-3i");
+MODULE_PARM(txcreditsconsumed, "0-3i");
+MODULE_PARM(txcreditintrenable, "0-3i");
+MODULE_PARM(txcreditintrenableaggregate, "0-3i");
+#endif
+
+#endif /* DEBUG */
+
+unsigned int resetok = 1;
+unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int hifBusRequestNumMax = 40;
+unsigned int war23838_disabled = 0;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+unsigned int enableAPTCHeuristics = 1;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_array(tx_attempt, uint, mboxnum, 0644);
+module_param_array(tx_post, uint, mboxnum, 0644);
+module_param_array(tx_complete, uint, mboxnum, 0644);
+module_param(hifBusRequestNumMax, uint, 0644);
+module_param(war23838_disabled, uint, 0644);
+module_param(resetok, uint, 0644);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+module_param(enableAPTCHeuristics, uint, 0644);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#else
+MODULE_PARM(tx_attempt, "0-3i");
+MODULE_PARM(tx_post, "0-3i");
+MODULE_PARM(tx_complete, "0-3i");
+MODULE_PARM(hifBusRequestNumMax, "i");
+MODULE_PARM(war23838_disabled, "i");
+MODULE_PARM(resetok, "i");
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+MODULE_PARM(enableAPTCHeuristics, "i");
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#endif
+
+#ifdef BLOCK_TX_PATH_FLAG
+int blocktx = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(blocktx, int, 0644);
+#else
+MODULE_PARM(blocktx, "i");
+#endif
+#endif /* BLOCK_TX_PATH_FLAG */
+
+typedef struct user_rssi_compensation_t {
+ A_UINT16 a_enable;
+ A_INT16 a_param_a;
+ A_INT16 a_param_b;
+ A_UINT16 bg_enable;
+ A_INT16 bg_param_a;
+ A_INT16 bg_param_b;
+} USER_RSSI_CPENSATION;
+
+static USER_RSSI_CPENSATION rssi_compensation_param;
+
+static A_INT16 rssi_compensation_table[96];
+
+int reconnect_flag = 0;
+
+/* Function declarations */
+static int ar6000_init_module(void);
+static void ar6000_cleanup_module(void);
+
+int ar6000_init(struct net_device *dev);
+static int ar6000_open(struct net_device *dev);
+static int ar6000_close(struct net_device *dev);
+static void ar6000_init_control_info(AR_SOFTC_T *ar);
+static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
+
+void ar6000_destroy(struct net_device *dev, unsigned int unregister);
+static void ar6000_detect_error(unsigned long ptr);
+static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
+static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
+
+static void disconnect_timer_handler(unsigned long ptr);
+
+void read_rssi_compensation_param(AR_SOFTC_T *ar);
+
+ /* for android builds we call external APIs that handle firmware download and configuration */
+#ifdef ANDROID_ENV
+/* !!!! Interim android support to make it easier to patch the default driver for
+ * android use. You must define an external source file ar6000_android.c that handles the following
+ * APIs */
+extern A_STATUS android_ar6k_start(AR_SOFTC_T *ar);
+extern void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks);
+extern void android_module_exit(void);
+extern A_BOOL android_ar6k_endpoint_is_stop(AR_SOFTC_T *ar);
+extern void android_ar6k_check_wow_status(AR_SOFTC_T *ar);
+#endif
+/*
+ * HTC service connection handlers
+ */
+static A_STATUS ar6000_avail_ev(void *context, void *hif_handle);
+
+static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle);
+
+A_STATUS ar6000_configure_target(AR_SOFTC_T *ar);
+
+void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile);
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status);
+
+static void ar6000_rx(void *Context, HTC_PACKET *pPacket);
+
+static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint);
+
+static void ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPackets);
+
+static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket);
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static void ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num);
+#endif
+static void ar6000_deliver_frames_to_nw_stack(void * dev, void *osbuf);
+//static void ar6000_deliver_frames_to_bt_stack(void * dev, void *osbuf);
+
+static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length);
+
+static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count);
+
+static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar);
+
+static ssize_t
+ar6000_sysfs_bmi_read(struct kobject *kobj, struct bin_attribute *bin_attr,
+ char *buf, loff_t pos, size_t count);
+
+static ssize_t
+ar6000_sysfs_bmi_write(struct kobject *kobj, struct bin_attribute *bin_attr,
+ char *buf, loff_t pos, size_t count);
+
+static A_STATUS
+ar6000_sysfs_bmi_init(AR_SOFTC_T *ar);
+
+static void
+ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar);
+
+A_STATUS
+ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode);
+
+/*
+ * Static variables
+ */
+
+struct net_device *ar6000_devices[MAX_AR6000];
+extern struct iw_handler_def ath_iw_handler_def;
+DECLARE_WAIT_QUEUE_HEAD(arEvent);
+static void ar6000_cookie_init(AR_SOFTC_T *ar);
+static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
+static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
+static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
+
+#ifdef USER_KEYS
+static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl);
+#endif
+
+
+static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
+
+#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \
+ (((ar)->arTargetType == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
+static struct net_device_ops ar6000_netdev_ops = {
+ .ndo_init = NULL,
+ .ndo_open = ar6000_open,
+ .ndo_stop = ar6000_close,
+ .ndo_get_stats = ar6000_get_stats,
+ .ndo_do_ioctl = ar6000_ioctl,
+ .ndo_start_xmit = ar6000_data_tx,
+};
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) */
+
+/* Debug log support */
+
+/*
+ * Flag to govern whether the debug logs should be parsed in the kernel
+ * or reported to the application.
+ */
+#define REPORT_DEBUG_LOGS_TO_APP
+
+A_STATUS
+ar6000_set_host_app_area(AR_SOFTC_T *ar)
+{
+ A_UINT32 address, data;
+ struct host_app_area_s host_app_area;
+
+ /* Fetch the address of the host_app_area_s instance in the host interest area */
+ address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest));
+ if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) {
+ return A_ERROR;
+ }
+ address = TARG_VTOP(ar->arTargetType, data);
+ host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
+ if (ar6000_WriteDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&host_app_area,
+ sizeof(struct host_app_area_s)) != A_OK)
+ {
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+
+A_UINT32
+dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar)
+{
+ A_UINT32 param;
+ A_UINT32 address;
+ A_STATUS status;
+
+ address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr));
+ if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&param, 4)) != A_OK)
+ {
+ param = 0;
+ }
+
+ return param;
+}
+
+/*
+ * The dbglog module has been initialized. Its ok to access the relevant
+ * data stuctures over the diagnostic window.
+ */
+void
+ar6000_dbglog_init_done(AR_SOFTC_T *ar)
+{
+ ar->dbglog_init_done = TRUE;
+}
+
+A_UINT32
+dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit)
+{
+ A_INT32 *buffer;
+ A_UINT32 count;
+ A_UINT32 numargs;
+ A_UINT32 length;
+ A_UINT32 fraglen;
+
+ count = fraglen = 0;
+ buffer = (A_INT32 *)datap;
+ length = (limit >> 2);
+
+ if (len <= limit) {
+ fraglen = len;
+ } else {
+ while (count < length) {
+ numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+ fraglen = (count << 2);
+ count += numargs + 1;
+ }
+ }
+
+ return fraglen;
+}
+
+void
+dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len)
+{
+ A_INT32 *buffer;
+ A_UINT32 count;
+ A_UINT32 timestamp;
+ A_UINT32 debugid;
+ A_UINT32 moduleid;
+ A_UINT32 numargs;
+ A_UINT32 length;
+
+ count = 0;
+ buffer = (A_INT32 *)datap;
+ length = (len >> 2);
+ while (count < length) {
+ debugid = DBGLOG_GET_DBGID(buffer[count]);
+ moduleid = DBGLOG_GET_MODULEID(buffer[count]);
+ numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+ timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]);
+ switch (numargs) {
+ case 0:
+ AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d)\n", moduleid, debugid, timestamp));
+ break;
+
+ case 1:
+ AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x\n", moduleid, debugid,
+ timestamp, buffer[count+1]));
+ break;
+
+ case 2:
+ AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid,
+ timestamp, buffer[count+1], buffer[count+2]));
+ break;
+
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid args: %d\n", numargs));
+ }
+ count += numargs + 1;
+ }
+}
+
+int
+ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar)
+{
+ struct dbglog_hdr_s debug_hdr;
+ struct dbglog_buf_s debug_buf;
+ A_UINT32 address;
+ A_UINT32 length;
+ A_UINT32 dropped;
+ A_UINT32 firstbuf;
+ A_UINT32 debug_hdr_ptr;
+
+ if (!ar->dbglog_init_done) return A_ERROR;
+
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if (ar->dbgLogFetchInProgress) {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ return A_EBUSY;
+ }
+
+ /* block out others */
+ ar->dbgLogFetchInProgress = TRUE;
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar);
+ printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr);
+
+ /* Get the contents of the ring buffer */
+ if (debug_hdr_ptr) {
+ address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr);
+ length = sizeof(struct dbglog_hdr_s);
+ ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&debug_hdr, length);
+ address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_hdr.dbuf);
+ firstbuf = address;
+ dropped = debug_hdr.dropped;
+ length = sizeof(struct dbglog_buf_s);
+ ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&debug_buf, length);
+
+ do {
+ address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.buffer);
+ length = debug_buf.length;
+ if ((length) && (debug_buf.length <= debug_buf.bufsize)) {
+ /* Rewind the index if it is about to overrun the buffer */
+ if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) {
+ ar->log_cnt = 0;
+ }
+ if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length))
+ {
+ break;
+ }
+ ar6000_dbglog_event(ar, dropped, (A_INT8*)&ar->log_buffer[ar->log_cnt], length);
+ ar->log_cnt += length;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("Length: %d (Total size: %d)\n",
+ debug_buf.length, debug_buf.bufsize));
+ }
+
+ address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.next);
+ length = sizeof(struct dbglog_buf_s);
+ if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&debug_buf, length))
+ {
+ break;
+ }
+
+ } while (address != firstbuf);
+ }
+
+ ar->dbgLogFetchInProgress = FALSE;
+
+ return A_OK;
+}
+
+void
+ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped,
+ A_INT8 *buffer, A_UINT32 length)
+{
+#ifdef REPORT_DEBUG_LOGS_TO_APP
+ #define MAX_WIRELESS_EVENT_SIZE 252
+ /*
+ * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages.
+ * There seems to be a limitation on the length of message that could be
+ * transmitted to the user app via this mechanism.
+ */
+ A_UINT32 send, sent;
+
+ sent = 0;
+ send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+ MAX_WIRELESS_EVENT_SIZE);
+ while (send) {
+ ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, (A_UINT8*)&buffer[sent], send);
+ sent += send;
+ send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+ MAX_WIRELESS_EVENT_SIZE);
+ }
+#else
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Dropped logs: 0x%x\nDebug info length: %d\n",
+ dropped, length));
+
+ /* Interpret the debug logs */
+ dbglog_parse_debug_logs((A_INT8*)buffer, length);
+#endif /* REPORT_DEBUG_LOGS_TO_APP */
+}
+
+
+static int __init
+ar6000_init_module(void)
+{
+ static int probed = 0;
+ A_STATUS status;
+ OSDRV_CALLBACKS osdrvCallbacks;
+
+ a_module_debug_support_init();
+
+#ifdef DEBUG
+ /* check for debug mask overrides */
+ if (debughtc != 0) {
+ ATH_DEBUG_SET_DEBUG_MASK(htc,debughtc);
+ }
+ if (debugbmi != 0) {
+ ATH_DEBUG_SET_DEBUG_MASK(bmi,debugbmi);
+ }
+ if (debughif != 0) {
+ ATH_DEBUG_SET_DEBUG_MASK(hif,debughif);
+ }
+ if (debugdriver != 0) {
+ ATH_DEBUG_SET_DEBUG_MASK(driver,debugdriver);
+ }
+
+#endif
+
+ A_REGISTER_MODULE_DEBUG_INFO(driver);
+
+ A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks));
+ osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev;
+ osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev;
+
+#ifdef ANDROID_ENV
+ android_module_init(&osdrvCallbacks);
+#endif
+
+#ifdef DEBUG
+ /* Set the debug flags if specified at load time */
+ if(debugflags != 0)
+ {
+ g_dbg_flags = debugflags;
+ }
+#endif
+
+ if (probed) {
+ return -ENODEV;
+ }
+ probed++;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+ ar6000_gpio_init();
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+ status = HIFInit(&osdrvCallbacks);
+ if(status != A_OK)
+ return -ENODEV;
+
+ return 0;
+}
+
+static void __exit
+ar6000_cleanup_module(void)
+{
+ int i = 0;
+ struct net_device *ar6000_netdev;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ /* Delete the Adaptive Power Control timer */
+ if (timer_pending(&aptcTimer)) {
+ del_timer_sync(&aptcTimer);
+ }
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+ for (i=0; i < MAX_AR6000; i++) {
+ if (ar6000_devices[i] != NULL) {
+ ar6000_netdev = ar6000_devices[i];
+ ar6000_devices[i] = NULL;
+ ar6000_destroy(ar6000_netdev, 1);
+ }
+ }
+
+ HIFShutDownDevice(NULL);
+
+ a_module_debug_support_cleanup();
+
+#ifdef ANDROID_ENV
+ android_module_exit();
+#endif
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_cleanup: success\n"));
+}
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+void
+aptcTimerHandler(unsigned long arg)
+{
+ A_UINT32 numbytes;
+ A_UINT32 throughput;
+ AR_SOFTC_T *ar;
+ A_STATUS status;
+
+ ar = (AR_SOFTC_T *)arg;
+ A_ASSERT(ar != NULL);
+ A_ASSERT(!timer_pending(&aptcTimer));
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ /* Get the number of bytes transferred */
+ numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+ aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+
+ /* Calculate and decide based on throughput thresholds */
+ throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */
+ if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) {
+ /* Enable Sleep and delete the timer */
+ A_ASSERT(ar->arWmiReady == TRUE);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ status = wmi_powermode_cmd(ar->arWmi, REC_POWER);
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ A_ASSERT(status == A_OK);
+ aptcTR.timerScheduled = FALSE;
+ } else {
+ A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static void
+ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num)
+{
+ void * osbuf;
+
+ while(num) {
+ if((osbuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE))) {
+ A_NETBUF_ENQUEUE(q, osbuf);
+ } else {
+ break;
+ }
+ num--;
+ }
+
+ if(num) {
+ A_PRINTF("%s(), allocation of netbuf failed", __func__);
+ }
+}
+#endif
+
+static struct bin_attribute bmi_attr = {
+ .attr = {.name = "bmi", .mode = 0600},
+ .read = ar6000_sysfs_bmi_read,
+ .write = ar6000_sysfs_bmi_write,
+};
+
+static ssize_t
+ar6000_sysfs_bmi_read(struct kobject *kobj, struct bin_attribute *bin_attr,
+ char *buf, loff_t pos, size_t count)
+{
+ int index;
+ AR_SOFTC_T *ar;
+ HIF_DEVICE_OS_DEVICE_INFO *osDevInfo;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Read %d bytes\n", count));
+ for (index=0; index < MAX_AR6000; index++) {
+ ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]);
+ osDevInfo = &ar->osDevInfo;
+ if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) {
+ break;
+ }
+ }
+
+ if (index == MAX_AR6000) return 0;
+
+ if ((BMIRawRead(ar->arHifDevice, (A_UCHAR*)buf, count, TRUE)) != A_OK) {
+ return 0;
+ }
+
+ return count;
+}
+
+static ssize_t
+ar6000_sysfs_bmi_write(struct kobject *kobj, struct bin_attribute *bin_attr,
+ char *buf, loff_t pos, size_t count)
+{
+ int index;
+ AR_SOFTC_T *ar;
+ HIF_DEVICE_OS_DEVICE_INFO *osDevInfo;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Write %d bytes\n", count));
+ for (index=0; index < MAX_AR6000; index++) {
+ ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]);
+ osDevInfo = &ar->osDevInfo;
+ if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) {
+ break;
+ }
+ }
+
+ if (index == MAX_AR6000) return 0;
+
+ if ((BMIRawWrite(ar->arHifDevice, (A_UCHAR*)buf, count)) != A_OK) {
+ return 0;
+ }
+
+ return count;
+}
+
+static A_STATUS
+ar6000_sysfs_bmi_init(AR_SOFTC_T *ar)
+{
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Creating sysfs entry\n"));
+ A_MEMZERO(&ar->osDevInfo, sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+
+ /* Get the underlying OS device */
+ status = HIFConfigureDevice(ar->arHifDevice,
+ HIF_DEVICE_GET_OS_DEVICE,
+ &ar->osDevInfo,
+ sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failed to get OS device info from HIF\n"));
+ return A_ERROR;
+ }
+
+ /* Create a bmi entry in the sysfs filesystem */
+ if ((sysfs_create_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr)) < 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to create entry for bmi in sysfs filesystem\n"));
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+
+static void
+ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Deleting sysfs entry\n"));
+
+ sysfs_remove_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr);
+}
+
+#define bmifn(fn) do { \
+ if ((fn) < A_OK) { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__)); \
+ return A_ERROR; \
+ } \
+} while(0)
+
+#ifdef INIT_MODE_DRV_ENABLED
+
+#ifdef SOFTMAC_FILE_USED
+#define AR6001_MAC_ADDRESS_OFFSET 0x06
+#define AR6002_MAC_ADDRESS_OFFSET 0x0A
+#define AR6003_MAC_ADDRESS_OFFSET 0x16
+static
+void calculate_crc(A_UINT32 TargetType, A_UCHAR *eeprom_data)
+{
+ A_UINT16 *ptr_crc;
+ A_UINT16 *ptr16_eeprom;
+ A_UINT16 checksum;
+ A_UINT32 i;
+ A_UINT32 eeprom_size;
+
+ if (TargetType == TARGET_TYPE_AR6001)
+ {
+ eeprom_size = 512;
+ ptr_crc = (A_UINT16 *)eeprom_data;
+ }
+ else if (TargetType == TARGET_TYPE_AR6003)
+ {
+ eeprom_size = 1024;
+ ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04);
+ }
+ else
+ {
+ eeprom_size = 768;
+ ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04);
+ }
+
+
+ // Clear the crc
+ *ptr_crc = 0;
+
+ // Recalculate new CRC
+ checksum = 0;
+ ptr16_eeprom = (A_UINT16 *)eeprom_data;
+ for (i = 0;i < eeprom_size; i += 2)
+ {
+ checksum = checksum ^ (*ptr16_eeprom);
+ ptr16_eeprom++;
+ }
+ checksum = 0xFFFF ^ checksum;
+ *ptr_crc = checksum;
+}
+
+static void
+ar6000_softmac_update(AR_SOFTC_T *ar, A_UCHAR *eeprom_data, size_t size)
+{
+ const char *source = "random generated";
+ const struct firmware *softmac_entry;
+ A_UCHAR *ptr_mac;
+ switch (ar->arTargetType) {
+ case TARGET_TYPE_AR6001:
+ ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6001_MAC_ADDRESS_OFFSET);
+ break;
+ case TARGET_TYPE_AR6002:
+ ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6002_MAC_ADDRESS_OFFSET);
+ break;
+ case TARGET_TYPE_AR6003:
+ ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6003_MAC_ADDRESS_OFFSET);
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Target Type \n"));
+ return;
+ }
+ printk("MAC from EEPROM %02X:%02X:%02X:%02X:%02X:%02X\n",
+ ptr_mac[0], ptr_mac[1], ptr_mac[2],
+ ptr_mac[3], ptr_mac[4], ptr_mac[5]);
+
+ /* create a random MAC in case we cannot read file from system */
+ ptr_mac[0] = 0;
+ ptr_mac[1] = 0x03;
+ ptr_mac[2] = 0x7F;
+ ptr_mac[3] = random32() & 0xff;
+ ptr_mac[4] = random32() & 0xff;
+ ptr_mac[5] = random32() & 0xff;
+ if ((A_REQUEST_FIRMWARE(&softmac_entry, "softmac", ((struct device *)ar->osDevInfo.pOSDevice))) == 0)
+ {
+ A_CHAR *macbuf = A_MALLOC_NOWAIT(softmac_entry->size+1);
+ if (macbuf) {
+ unsigned int softmac[6];
+ memcpy(macbuf, softmac_entry->data, softmac_entry->size);
+ macbuf[softmac_entry->size] = '\0';
+ if (sscanf(macbuf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ &softmac[0], &softmac[1], &softmac[2],
+ &softmac[3], &softmac[4], &softmac[5])==6) {
+ int i;
+ for (i=0; i<6; ++i) {
+ ptr_mac[i] = softmac[i] & 0xff;
+ }
+ source = "softmac file";
+ }
+ A_FREE(macbuf);
+ }
+ A_RELEASE_FIRMWARE(softmac_entry);
+ }
+ printk("MAC from %s %02X:%02X:%02X:%02X:%02X:%02X\n", source,
+ ptr_mac[0], ptr_mac[1], ptr_mac[2],
+ ptr_mac[3], ptr_mac[4], ptr_mac[5]);
+ calculate_crc(ar->arTargetType, eeprom_data);
+}
+#endif /* SOFTMAC_FILE_USED */
+
+static A_STATUS
+ar6000_transfer_bin_file(AR_SOFTC_T *ar, AR6K_BIN_FILE file, A_UINT32 address, A_BOOL compressed)
+{
+ A_STATUS status;
+ const char *filename;
+ const struct firmware *fw_entry;
+
+ switch (file) {
+ case AR6K_OTP_FILE:
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ filename = AR6003_REV1_OTP_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ filename = AR6003_REV2_OTP_FILE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+ return A_ERROR;
+ }
+ break;
+
+ case AR6K_FIRMWARE_FILE:
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ filename = AR6003_REV1_FIRMWARE_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ filename = AR6003_REV2_FIRMWARE_FILE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+ return A_ERROR;
+ }
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ if(testmode) {
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ filename = AR6003_REV1_TCMD_FIRMWARE_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ filename = AR6003_REV2_TCMD_FIRMWARE_FILE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+ return A_ERROR;
+ }
+ compressed = 0;
+ }
+#endif
+#ifdef HTC_RAW_INTERFACE
+ if (bypasswmi) {
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ filename = AR6003_REV1_ART_FIRMWARE_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ filename = AR6003_REV2_ART_FIRMWARE_FILE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+ return A_ERROR;
+ }
+ compressed = 0;
+ }
+#endif
+ break;
+
+ case AR6K_PATCH_FILE:
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ filename = AR6003_REV1_PATCH_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ filename = AR6003_REV2_PATCH_FILE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+ return A_ERROR;
+ }
+ break;
+
+ case AR6K_BOARD_DATA_FILE:
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ filename = AR6003_REV1_BOARD_DATA_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ filename = AR6003_REV2_BOARD_DATA_FILE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
+ return A_ERROR;
+ }
+ break;
+
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown file type: %d\n", file));
+ return A_ERROR;
+ }
+ if ((A_REQUEST_FIRMWARE(&fw_entry, filename, ((struct device *)ar->osDevInfo.pOSDevice))) != 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to get %s\n", filename));
+ return A_ENOENT;
+ }
+
+#ifdef SOFTMAC_FILE_USED
+ if (file==AR6K_BOARD_DATA_FILE && fw_entry->data) {
+ ar6000_softmac_update(ar, (A_UCHAR *)fw_entry->data, fw_entry->size);
+ }
+#endif
+
+ if (compressed) {
+ status = BMIFastDownload(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry->size);
+ } else {
+ status = BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry->size);
+ }
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__));
+ A_RELEASE_FIRMWARE(fw_entry);
+ return A_ERROR;
+ }
+ A_RELEASE_FIRMWARE(fw_entry);
+ return A_OK;
+}
+#endif /* INIT_MODE_DRV_ENABLED */
+
+A_STATUS
+ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Requesting device specific configuration\n"));
+
+ if (mode == WLAN_INIT_MODE_UDEV) {
+ A_CHAR version[16];
+ const struct firmware *fw_entry;
+
+ /* Get config using udev through a script in user space */
+ sprintf(version, "%2.2x", ar->arVersion.target_ver);
+ if ((A_REQUEST_FIRMWARE(&fw_entry, version, ((struct device *)ar->osDevInfo.pOSDevice))) != 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failure to get configuration for target version: %s\n", version));
+ return A_ERROR;
+ }
+
+ A_RELEASE_FIRMWARE(fw_entry);
+#ifdef INIT_MODE_DRV_ENABLED
+ } else {
+ /* The config is contained within the driver itself */
+ A_STATUS status;
+ A_UINT32 param, options, sleep, address;
+
+ /* Temporarily disable system sleep */
+ address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
+ bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+ options = param;
+ param |= AR6K_OPTION_SLEEP_DISABLE;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+ address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
+ bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+ sleep = param;
+ param |= WLAN_SYSTEM_SLEEP_DISABLE_SET(1);
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("old options: %d, old sleep: %d\n", options, sleep));
+
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ /* Run at 80/88MHz by default */
+ param = CPU_CLOCK_STANDARD_SET(1);
+ } else {
+ /* Run at 40/44MHz by default */
+ param = CPU_CLOCK_STANDARD_SET(0);
+ }
+ address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+ param = 0;
+ if (ar->arTargetType == TARGET_TYPE_AR6002) {
+ bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)&param, 4));
+ }
+
+ /* LPO_CAL.ENABLE = 1 if no external clk is detected */
+ if (param != 1) {
+ address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
+ param = LPO_CAL_ENABLE_SET(1);
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+ }
+
+ /* Venus2.0: Lower SDIO pad drive strength,
+ * temporary WAR to avoid SDIO CRC error */
+ if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6K: Temporary WAR to avoid SDIO CRC error\n"));
+ param = 0x20;
+ address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+ address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+ address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+ address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+ }
+
+#ifdef FORCE_INTERNAL_CLOCK
+ /* Ignore external clock, if any, and force use of internal clock */
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ /* hi_ext_clk_detected = 0 */
+ param = 0;
+ bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)&param, 4));
+
+ /* CLOCK_CONTROL &= ~LF_CLK32 */
+ address = RTC_BASE_ADDRESS + CLOCK_CONTROL_ADDRESS;
+ bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+ param &= (~CLOCK_CONTROL_LF_CLK32_SET(1));
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+ }
+#endif /* FORCE_INTERNAL_CLOCK */
+
+ /* Transfer Board Data from Target EEPROM to Target RAM */
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ /* Determine where in Target RAM to write Board Data */
+ bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data), (A_UCHAR *)&address, 4));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("Board Data download address: 0x%x\n", address));
+
+ /* Write EEPROM data to Target RAM */
+ if ((ar6000_transfer_bin_file(ar, AR6K_BOARD_DATA_FILE, address, FALSE)) != A_OK) {
+ return A_ERROR;
+ }
+
+ /* Record the fact that Board Data IS initialized */
+ param = 1;
+ bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), (A_UCHAR *)&param, 4));
+
+ /* Transfer One time Programmable data */
+ AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+ status = ar6000_transfer_bin_file(ar, AR6K_OTP_FILE, address, TRUE);
+ if (status == A_OK) {
+ /* Execute the OTP code */
+ param = 0;
+ AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
+ bmifn(BMIExecute(ar->arHifDevice, address, &param));
+ } else if (status != A_ENOENT) {
+ return A_ERROR;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Programming of board data for chip %d not supported\n", ar->arTargetType));
+ return A_ERROR;
+ }
+
+ /* Download Target firmware */
+ AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+ if ((ar6000_transfer_bin_file(ar, AR6K_FIRMWARE_FILE, address, TRUE)) != A_OK) {
+ return A_ERROR;
+ }
+
+ /* Set starting address for firmware */
+ AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
+ bmifn(BMISetAppStart(ar->arHifDevice, address));
+
+ /* Apply the patches */
+ AR6K_PATCH_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+ if ((ar6000_transfer_bin_file(ar, AR6K_PATCH_FILE, address, FALSE)) != A_OK) {
+ return A_ERROR;
+ }
+
+ param = address;
+ bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dset_list_head), (A_UCHAR *)&param, 4));
+
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
+ /* Reserve 5.5K of RAM */
+ param = 5632;
+ } else { /* AR6003_REV2_VERSION */
+ /* Reserve 6K of RAM */
+ param = 6144;
+ }
+ bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), (A_UCHAR *)&param, 4));
+ }
+
+ /* Restore system sleep */
+ address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, sleep));
+
+ address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
+ param = options | 0x20;
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ /* Configure GPIO AR6003 UART */
+#ifndef CONFIG_AR600x_DEBUG_UART_TX_PIN
+#define CONFIG_AR600x_DEBUG_UART_TX_PIN 8
+#endif
+ param = CONFIG_AR600x_DEBUG_UART_TX_PIN;
+ bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbg_uart_txpin), (A_UCHAR *)&param, 4));
+
+#if (CONFIG_AR600x_DEBUG_UART_TX_PIN == 23)
+ {
+ address = GPIO_BASE_ADDRESS + CLOCK_GPIO_ADDRESS;
+ bmifn(BMIReadSOCRegister(ar->arHifDevice, address, &param));
+ param |= CLOCK_GPIO_BT_CLK_OUT_EN_SET(1);
+ bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param));
+ }
+#endif
+
+ /* Configure GPIO for BT Reset */
+#ifdef ATH6KL_CONFIG_GPIO_BT_RESET
+ param = CONFIG_AR600x_BT_RESET_PIN;
+ bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_hci_uart_support_pins), (A_UCHAR *)&param, 4));
+#endif /* ATH6KL_CONFIG_GPIO_BT_RESET */
+ }
+#ifdef HTC_RAW_INTERFACE
+ if (bypasswmi) {
+ /* Don't run BMIDone for ART mode and force resetok=0 */
+ resetok = 0;
+ msleep(1000);
+ return A_OK;
+ }
+#endif /* HTC_RAW_INTERFACE */
+ /* Tell Target to execute loaded firmware */
+ bmifn(BMIDone(ar->arHifDevice));
+#endif /* INIT_MODE_DRV_ENABLED */
+ }
+
+ return A_OK;
+}
+
+A_STATUS
+ar6000_configure_target(AR_SOFTC_T *ar)
+{
+ A_UINT32 param;
+ if (enableuartprint) {
+ param = 1;
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enableuartprint failed \n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Serial console prints enabled\n"));
+ }
+
+ /* Tell target which HTC version it is used*/
+ param = HTC_PROTOCOL_VERSION;
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for htc version failed \n"));
+ return A_ERROR;
+ }
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ if(testmode) {
+ ar->arTargetMode = AR6000_TCMD_MODE;
+ }else {
+ ar->arTargetMode = AR6000_WLAN_MODE;
+ }
+#endif
+ if (enabletimerwar) {
+ A_UINT32 param;
+
+ if (BMIReadMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for enabletimerwar failed \n"));
+ return A_ERROR;
+ }
+
+ param |= HI_OPTION_TIMER_WAR;
+
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enabletimerwar failed \n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Timer WAR enabled\n"));
+ }
+
+ /* set the firmware mode to STA/IBSS/AP */
+ {
+ A_UINT32 param;
+
+ if (BMIReadMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for setting fwmode failed \n"));
+ return A_ERROR;
+ }
+
+ param |= (fwmode << HI_OPTION_FW_MODE_SHIFT);
+
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for setting fwmode failed \n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n"));
+ }
+#if 0 /* HOST_INTEREST is no longer used to configure dot11 processing rule */
+ if (processDot11Hdr) {
+ A_UINT32 param;
+
+ if (BMIReadMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for processDot11Hdr failed \n"));
+ return A_ERROR;
+ }
+
+ param |= HI_OPTION_RELAY_DOT11_HDR;
+
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for processDot11Hdr failed \n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("processDot11Hdr enabled\n"));
+ }
+#endif
+
+#ifdef ATH6KL_DISABLE_TARGET_DBGLOGS
+ {
+ A_UINT32 param;
+
+ if (BMIReadMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for disabling debug logs failed\n"));
+ return A_ERROR;
+ }
+
+ param |= HI_OPTION_DISABLE_DBGLOG;
+
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for HI_OPTION_DISABLE_DBGLOG\n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n"));
+ }
+#endif /* ATH6KL_DISABLE_TARGET_DBGLOGS */
+
+ // No need to reserve RAM space for patch as AR6001 is flash based
+ if (ar->arTargetType == TARGET_TYPE_AR6001) {
+ param = 0;
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz),
+ (A_UCHAR *)&param,
+ 4) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n"));
+ return A_ERROR;
+ }
+ }
+
+
+ /* since BMIInit is called in the driver layer, we have to set the block
+ * size here for the target */
+
+ if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice,
+ ar->arTargetType,
+ mbox_yield_limit,
+ 0 /* use default number of control buffers */
+ ))) {
+ return A_ERROR;
+ }
+
+ if (setupbtdev != 0) {
+ if (A_FAILED(ar6000_set_hci_bridge_flags(ar->arHifDevice,
+ ar->arTargetType,
+ setupbtdev))) {
+ return A_ERROR;
+ }
+ }
+ return A_OK;
+}
+
+/*
+ * HTC Event handlers
+ */
+static A_STATUS
+ar6000_avail_ev(void *context, void *hif_handle)
+{
+ int i;
+ struct net_device *dev;
+ void *ar_netif;
+ AR_SOFTC_T *ar;
+ int device_index = 0;
+ HTC_INIT_INFO htcInfo;
+#ifdef ATH6K_CONFIG_CFG80211
+ struct wireless_dev *wdev;
+#endif /* ATH6K_CONFIG_CFG80211 */
+ A_STATUS init_status = A_OK;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_available\n"));
+
+ for (i=0; i < MAX_AR6000; i++) {
+ if (ar6000_devices[i] == NULL) {
+ break;
+ }
+ }
+
+ if (i == MAX_AR6000) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: max devices reached\n"));
+ return A_ERROR;
+ }
+
+ /* Save this. It gives a bit better readability especially since */
+ /* we use another local "i" variable below. */
+ device_index = i;
+
+#ifdef ATH6K_CONFIG_CFG80211
+ wdev = ar6k_cfg80211_init(NULL);
+ if (IS_ERR(wdev)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ar6k_cfg80211_init failed\n", __func__));
+ return A_ERROR;
+ }
+ ar_netif = wdev_priv(wdev);
+#else
+ dev = alloc_etherdev(sizeof(AR_SOFTC_T));
+ if (dev == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: can't alloc etherdev\n"));
+ return A_ERROR;
+ }
+ ether_setup(dev);
+ ar_netif = ar6k_priv(dev);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+ if (ar_netif == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Can't allocate ar6k priv memory\n", __func__));
+ return A_ERROR;
+ }
+
+ A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T));
+ ar = (AR_SOFTC_T *)ar_netif;
+
+#ifdef ATH6K_CONFIG_CFG80211
+ ar->wdev = wdev;
+ wdev->iftype = NL80211_IFTYPE_STATION;
+
+ dev = alloc_netdev_mq(0, "wlan%d", ether_setup, 1);
+ if (!dev) {
+ printk(KERN_CRIT "AR6K: no memory for network device instance\n");
+ ar6k_cfg80211_deinit(ar);
+ return A_ERROR;
+ }
+
+ dev->ieee80211_ptr = wdev;
+ SET_NETDEV_DEV(dev, wiphy_dev(wdev->wiphy));
+ wdev->netdev = dev;
+ ar->arNetworkType = INFRA_NETWORK;
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ if (ifname[0])
+ {
+ strcpy(dev->name, ifname);
+ }
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */
+
+#ifdef SET_MODULE_OWNER
+ SET_MODULE_OWNER(dev);
+#endif
+
+#ifdef SET_NETDEV_DEV
+ if (ar_netif) {
+ HIF_DEVICE_OS_DEVICE_INFO osDevInfo;
+ A_MEMZERO(&osDevInfo, sizeof(osDevInfo));
+ if ( A_SUCCESS( HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_OS_DEVICE,
+ &osDevInfo, sizeof(osDevInfo))) ) {
+ SET_NETDEV_DEV(dev, osDevInfo.pOSDevice);
+ }
+ }
+#endif
+
+ ar->arNetDev = dev;
+ ar->arHifDevice = hif_handle;
+ ar->arWlanState = WLAN_ENABLED;
+ ar->arDeviceIndex = device_index;
+
+ A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev);
+ ar->arHBChallengeResp.seqNum = 0;
+ ar->arHBChallengeResp.outstanding = FALSE;
+ ar->arHBChallengeResp.missCnt = 0;
+ ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT;
+ ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT;
+
+ ar6000_init_control_info(ar);
+ init_waitqueue_head(&arEvent);
+ sema_init(&ar->arSem, 1);
+ ar->bIsDestroyProgress = FALSE;
+
+ INIT_HTC_PACKET_QUEUE(&ar->amsdu_rx_buffer_queue);
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+ A_INIT_TIMER(&ar->disconnect_timer, disconnect_timer_handler, dev);
+
+ /*
+ * If requested, perform some magic which requires no cooperation from
+ * the Target. It causes the Target to ignore flash and execute to the
+ * OS from ROM.
+ *
+ * This is intended to support recovery from a corrupted flash on Targets
+ * that support flash.
+ */
+ if (skipflash)
+ {
+ //ar6000_reset_device_skipflash(ar->arHifDevice);
+ }
+
+ BMIInit();
+
+ if (bmienable) {
+ ar6000_sysfs_bmi_init(ar);
+ }
+
+ {
+ struct bmi_target_info targ_info;
+
+ if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) {
+ init_status = A_ERROR;
+ goto avail_ev_failed;
+ }
+
+ ar->arVersion.target_ver = targ_info.target_ver;
+ ar->arTargetType = targ_info.target_type;
+
+ /* do any target-specific preparation that can be done through BMI */
+ if (ar6000_prepare_target(ar->arHifDevice,
+ targ_info.target_type,
+ targ_info.target_ver) != A_OK) {
+ init_status = A_ERROR;
+ goto avail_ev_failed;
+ }
+
+ }
+
+ if (ar6000_configure_target(ar) != A_OK) {
+ init_status = A_ERROR;
+ goto avail_ev_failed;
+ }
+
+ A_MEMZERO(&htcInfo,sizeof(htcInfo));
+ htcInfo.pContext = ar;
+ htcInfo.TargetFailure = ar6000_target_failure;
+
+ ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo);
+
+ if (ar->arHtcTarget == NULL) {
+ init_status = A_ERROR;
+ goto avail_ev_failed;
+ }
+
+ spin_lock_init(&ar->arLock);
+
+#ifdef WAPI_ENABLE
+ ar->arWapiEnable = 0;
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+ dev->open = &ar6000_open;
+ dev->stop = &ar6000_close;
+ dev->hard_start_xmit = &ar6000_data_tx;
+ dev->get_stats = &ar6000_get_stats;
+
+ /* dev->tx_timeout = ar6000_tx_timeout; */
+ dev->do_ioctl = &ar6000_ioctl;
+#else
+ dev->netdev_ops = &ar6000_netdev_ops;
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) */
+ dev->watchdog_timeo = AR6000_TX_TIMEOUT;
+ dev->wireless_handlers = &ath_iw_handler_def;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
+ dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
+#else
+ ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
+#endif
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+ if(csumOffload){
+
+ dev->features |= NETIF_F_IP_CSUM;/*advertise kernel capability
+ to do TCP/UDP CSUM offload for IPV4*/
+ ar->rxMetaVersion=WMI_META_VERSION_2;/*if external frame work is also needed, change and use an extended rxMetaVerion*/
+ }
+#endif
+ if (processDot11Hdr) {
+ dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR;
+ } else {
+ /*
+ * We need the OS to provide us with more headroom in order to
+ * perform dix to 802.3, WMI header encap, and the HTC header
+ */
+ dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
+ sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR;
+ }
+
+#ifdef ATH_AR6K_11N_SUPPORT
+ if((ar->aggr_cntxt = aggr_init(ar6000_alloc_netbufs)) == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize aggr.\n", __func__));
+ init_status = A_ERROR;
+ goto avail_ev_failed;
+ }
+
+ aggr_register_rx_dispatcher(ar->aggr_cntxt, (void *)dev, ar6000_deliver_frames_to_nw_stack);
+#endif
+
+ HIFClaimDevice(ar->arHifDevice, ar);
+
+ /* We only register the device in the global list if we succeed. */
+ /* If the device is in the global list, it will be destroyed */
+ /* when the module is unloaded. */
+ ar6000_devices[device_index] = dev;
+
+ /* Don't install the init function if BMI is requested */
+ if (!bmienable) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
+ dev->init = ar6000_init;
+#else
+ ar6000_netdev_ops.ndo_init = ar6000_init;
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) */
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("BMI enabled: %d\n", wlaninitmode));
+ if ((wlaninitmode == WLAN_INIT_MODE_UDEV) ||
+ (wlaninitmode == WLAN_INIT_MODE_DRV))
+ {
+ A_STATUS status = A_OK;
+ do {
+ A_BOOL rtnl_lock_grabbed;
+ if ((status = ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
+ break;
+ }
+#ifdef HTC_RAW_INTERFACE
+ if (bypasswmi) {
+ A_UINT32 param = 1;
+ status = BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized),
+ (A_UCHAR *)&param, 4);
+ break;
+ }
+#endif
+ rtnl_lock_grabbed = rtnl_trylock();
+ status = (ar6000_init(dev)==0) ? A_OK : A_ERROR;
+ if (rtnl_lock_grabbed) {
+ rtnl_unlock(); /* we locked it above, so unlock it here */
+ }
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_init\n"));
+ }
+ } while (FALSE);
+
+ if (status != A_OK) {
+ init_status = status;
+ goto avail_ev_failed;
+ }
+ }
+ }
+
+ /* This runs the init function if registered */
+ if (register_netdev(dev)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: register_netdev failed\n"));
+ ar6000_destroy(dev, 0);
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_avail: name=%s hifdevice=0x%x, dev=0x%x (%d), ar=0x%x\n",
+ dev->name, (A_UINT32)ar->arHifDevice, (A_UINT32)dev, device_index,
+ (A_UINT32)ar));
+
+avail_ev_failed :
+ if (A_FAILED(init_status)) {
+ if (bmienable) {
+ ar6000_sysfs_bmi_deinit(ar);
+ }
+ }
+
+ return init_status;
+}
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
+ WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+ static A_BOOL sip = FALSE;
+
+ if (Status != A_OK) {
+
+ printk(KERN_ERR "ar6000_target_failure: target asserted \n");
+
+ if (timer_pending(&ar->arHBChallengeResp.timer)) {
+ A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+ }
+
+ /* try dumping target assertion information (if any) */
+ ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType);
+
+ /*
+ * Fetch the logs from the target via the diagnostic
+ * window.
+ */
+ ar6000_dbglog_get_debug_logs(ar);
+
+ /* Report the error only once */
+ if (!sip) {
+ sip = TRUE;
+ errEvent.errorVal = WMI_TARGET_COM_ERR |
+ WMI_TARGET_FATAL_ERR;
+ ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+ (A_UINT8 *)&errEvent,
+ sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+ }
+ }
+}
+
+static A_STATUS
+ar6000_unavail_ev(void *context, void *hif_handle)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)context;
+ /* NULL out it's entry in the global list */
+ ar6000_devices[ar->arDeviceIndex] = NULL;
+ ar6000_destroy(ar->arNetDev, 1);
+
+ return A_OK;
+}
+
+void
+ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev);
+ /* Stop the transmit queues */
+ netif_stop_queue(dev);
+
+ /* Disable the target and the interrupts associated with it */
+ if (ar->arWmiReady == TRUE)
+ {
+ if (!bypasswmi)
+ {
+ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Disconnect\n", __func__));
+#ifdef ANDROID_ENV
+ if (keepprofile) {
+ wmi_disconnect_cmd(ar->arWmi);
+ } else
+#endif /* ANDROID_ENV */
+ {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar6000_init_profile_info(ar);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ wmi_disconnect_cmd(ar->arWmi);
+ }
+ }
+ A_UNTIMEOUT(&ar->disconnect_timer);
+ ar->arWmiReady = FALSE;
+ ar->arConnected = FALSE;
+ ar->arConnectPending = FALSE;
+ wmi_shutdown(ar->arWmi);
+ ar->arWmiEnabled = FALSE;
+ ar->arWmi = NULL;
+ ar->arWlanState = WLAN_ENABLED;
+#ifdef USER_KEYS
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+ ar->user_key_ctrl = 0;
+#endif
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI stopped\n", __func__));
+ }
+ else
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI not ready 0x%08x 0x%08x\n",
+ __func__, (unsigned int) ar, (unsigned int) ar->arWmi));
+
+ /* Shut down WMI if we have started it */
+ if(ar->arWmiEnabled == TRUE)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Shut down WMI\n", __func__));
+ wmi_shutdown(ar->arWmi);
+ ar->arWmiEnabled = FALSE;
+ ar->arWmi = NULL;
+ }
+ }
+
+ if (ar->arHtcTarget != NULL) {
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ if (NULL != ar6kHciTransCallbacks.cleanupTransport) {
+ ar6kHciTransCallbacks.cleanupTransport(NULL);
+ }
+#else
+ // FIXME: workaround to reset BT's UART baud rate to default
+ if (NULL != ar->exitCallback) {
+ AR3K_CONFIG_INFO ar3kconfig;
+ A_STATUS status;
+
+ A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig));
+ ar6000_set_default_ar3kconfig(ar, (void *)&ar3kconfig);
+ status = ar->exitCallback(&ar3kconfig);
+ if (A_OK != status) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to reset AR3K baud rate! \n"));
+ }
+ }
+ // END workaround
+ ar6000_cleanup_hci(ar);
+#endif
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Shutting down HTC .... \n"));
+ /* stop HTC */
+ HTCStop(ar->arHtcTarget);
+ }
+
+ if (resetok) {
+ /* try to reset the device if we can
+ * The driver may have been configure NOT to reset the target during
+ * a debug session */
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Attempting to reset target on instance destroy.... \n"));
+ if (ar->arHifDevice != NULL) {
+ /* WAR for AR6003 cannot do without cold reset */
+ A_BOOL coldReset = (ar->arTargetType==TARGET_TYPE_AR6003) ? TRUE : FALSE;
+ ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, coldReset);
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Host does not want target reset. \n"));
+ }
+ /* Done with cookies */
+ ar6000_cookie_cleanup(ar);
+}
+/*
+ * We need to differentiate between the surprise and planned removal of the
+ * device because of the following consideration:
+ * - In case of surprise removal, the hcd already frees up the pending
+ * for the device and hence there is no need to unregister the function
+ * driver inorder to get these requests. For planned removal, the function
+ * driver has to explictly unregister itself to have the hcd return all the
+ * pending requests before the data structures for the devices are freed up.
+ * Note that as per the current implementation, the function driver will
+ * end up releasing all the devices since there is no API to selectively
+ * release a particular device.
+ * - Certain commands issued to the target can be skipped for surprise
+ * removal since they will anyway not go through.
+ */
+void
+ar6000_destroy(struct net_device *dev, unsigned int unregister)
+{
+ AR_SOFTC_T *ar;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("+ar6000_destroy \n"));
+
+ if((dev == NULL) || ((ar = ar6k_priv(dev)) == NULL))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): Failed to get device structure.\n", __func__));
+ return;
+ }
+
+ ar->bIsDestroyProgress = TRUE;
+
+ if (down_interruptible(&ar->arSem)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): down_interruptible failed \n", __func__));
+ return;
+ }
+ if (ar->arWmiReady && !bypasswmi) {
+ ar6000_dbglog_get_debug_logs(ar);
+ }
+#ifdef ANDROID_ENV
+ if (!android_ar6k_endpoint_is_stop(ar)) {
+#else
+ if (1) {
+#endif
+ /* only stop endpoint if we are not stop it in suspend_ev */
+ ar6000_stop_endpoint(dev, FALSE);
+ }
+ if (ar->arHtcTarget != NULL) {
+ /* destroy HTC */
+ HTCDestroy(ar->arHtcTarget);
+ }
+ if (ar->arHifDevice != NULL) {
+ /*release the device so we do not get called back on remove incase we
+ * we're explicity destroyed by module unload */
+ HIFReleaseDevice(ar->arHifDevice);
+ HIFShutDownDevice(ar->arHifDevice);
+ }
+#ifdef ATH_AR6K_11N_SUPPORT
+ aggr_module_destroy(ar->aggr_cntxt);
+#endif
+
+ /* Done with cookies */
+ ar6000_cookie_cleanup(ar);
+
+ /* cleanup any allocated AMSDU buffers */
+ ar6000_cleanup_amsdu_rxbufs(ar);
+
+ if (bmienable) {
+ ar6000_sysfs_bmi_deinit(ar);
+ }
+
+ /* Cleanup BMI */
+ BMIInit();
+
+ /* Clear the tx counters */
+ memset(tx_attempt, 0, sizeof(tx_attempt));
+ memset(tx_post, 0, sizeof(tx_post));
+ memset(tx_complete, 0, sizeof(tx_complete));
+
+#ifdef HTC_RAW_INTERFACE
+ if (ar->arRawHtc) {
+ A_FREE(ar->arRawHtc);
+ ar->arRawHtc = NULL;
+ }
+#endif
+ /* Free up the device data structure */
+ if( unregister )
+ unregister_netdev(dev);
+#ifndef free_netdev
+ kfree(dev);
+#else
+ free_netdev(dev);
+#endif
+
+#ifdef ATH6K_CONFIG_CFG80211
+ ar6k_cfg80211_deinit(ar);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("-ar6000_destroy \n"));
+}
+
+static void disconnect_timer_handler(unsigned long ptr)
+{
+ struct net_device *dev = (struct net_device *)ptr;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ A_UNTIMEOUT(&ar->disconnect_timer);
+
+ ar6000_init_profile_info(ar);
+ wmi_disconnect_cmd(ar->arWmi);
+}
+
+static void ar6000_detect_error(unsigned long ptr)
+{
+ struct net_device *dev = (struct net_device *)ptr;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if (ar->arHBChallengeResp.outstanding) {
+ ar->arHBChallengeResp.missCnt++;
+ } else {
+ ar->arHBChallengeResp.missCnt = 0;
+ }
+
+ if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) {
+ /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */
+ ar->arHBChallengeResp.missCnt = 0;
+ ar->arHBChallengeResp.seqNum = 0;
+ errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+ (A_UINT8 *)&errEvent,
+ sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+ return;
+ }
+
+ /* Generate the sequence number for the next challenge */
+ ar->arHBChallengeResp.seqNum++;
+ ar->arHBChallengeResp.outstanding = TRUE;
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ /* Send the challenge on the control channel */
+ if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to send heart beat challenge\n"));
+ }
+
+
+ /* Reschedule the timer for the next challenge */
+ A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+}
+
+void ar6000_init_profile_info(AR_SOFTC_T *ar)
+{
+ ar->arSsidLen = 0;
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+
+ switch(fwmode) {
+ case HI_OPTION_FW_MODE_IBSS:
+ ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK;
+ break;
+ case HI_OPTION_FW_MODE_BSS_STA:
+ ar->arNetworkType = ar->arNextMode = INFRA_NETWORK;
+ break;
+ case HI_OPTION_FW_MODE_AP:
+ ar->arNetworkType = ar->arNextMode = AP_NETWORK;
+ break;
+ }
+
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arAuthMode = NONE_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+ ar->arBssChannel = 0;
+ ar->arConnected = FALSE;
+}
+
+static void
+ar6000_init_control_info(AR_SOFTC_T *ar)
+{
+ ar->arWmiEnabled = FALSE;
+ ar6000_init_profile_info(ar);
+ ar->arDefTxKeyIndex = 0;
+ A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+ ar->arChannelHint = 0;
+ ar->arListenInterval = A_DEFAULT_LISTEN_INTERVAL;
+ ar->arVersion.host_ver = AR6K_SW_VERSION;
+ ar->arRssi = 0;
+ ar->arTxPwr = 0;
+ ar->arTxPwrSet = FALSE;
+ ar->arSkipScan = 0;
+ ar->arBeaconInterval = 0;
+ ar->arBitRate = 0;
+ ar->arMaxRetries = 0;
+ ar->arWmmEnabled = TRUE;
+ ar->intra_bss = 1;
+ ar->scan_complete = 1;
+ A_MEMZERO(&ar->scParams, sizeof(ar->scParams));
+ ar->scParams.shortScanRatio = WMI_SHORTSCANRATIO_DEFAULT;
+ ar->scParams.scanCtrlFlags = DEFAULT_SCAN_CTRL_FLAGS;
+
+ /* Initialize the AP mode state info */
+ {
+ A_UINT8 ctr;
+ A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t));
+
+ /* init the Mutexes */
+ A_MUTEX_INIT(&ar->mcastpsqLock);
+
+ /* Init the PS queues */
+ for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) {
+ A_MUTEX_INIT(&ar->sta_list[ctr].psqLock);
+ A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq);
+ }
+
+ ar->ap_profile_flag = 0;
+ A_NETBUF_QUEUE_INIT(&ar->mcastpsq);
+
+ A_MEMCPY(ar->ap_country_code, DEF_AP_COUNTRY_CODE, 3);
+ ar->ap_wmode = DEF_AP_WMODE_G;
+ ar->ap_dtim_period = DEF_AP_DTIM;
+ ar->ap_beacon_interval = DEF_BEACON_INTERVAL;
+ }
+}
+
+static int
+ar6000_open(struct net_device *dev)
+{
+ unsigned long flags;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ spin_lock_irqsave(&ar->arLock, flags);
+
+#ifndef ANDROID_ENV
+ if(ar->arWlanState == WLAN_DISABLED) {
+ ar->arWlanState = WLAN_ENABLED;
+ }
+#endif
+
+ if( ar->arConnected || bypasswmi) {
+ netif_carrier_on(dev);
+ /* Wake up the queues */
+ netif_wake_queue(dev);
+ }
+ else
+ netif_carrier_off(dev);
+
+ spin_unlock_irqrestore(&ar->arLock, flags);
+ return 0;
+}
+
+static int
+ar6000_close(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ netif_stop_queue(dev);
+
+#ifdef ANDROID_ENV
+ (void)ar; /* do nothing. Android SDK will handle it */
+#else
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ wmi_disconnect_cmd(ar->arWmi);
+ } else {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+
+ if(ar->arWmiReady == TRUE) {
+ if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0) != A_OK) {
+ return -EIO;
+ }
+ ar->arWlanState = WLAN_DISABLED;
+ }
+#endif
+ return 0;
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar,
+ HTC_SERVICE_CONNECT_REQ *pConnect,
+ char *pDesc)
+{
+ A_STATUS status;
+ HTC_SERVICE_CONNECT_RESP response;
+
+ do {
+
+ A_MEMZERO(&response,sizeof(response));
+
+ status = HTCConnectService(ar->arHtcTarget,
+ pConnect,
+ &response);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Failed to connect to %s service status:%d \n",
+ pDesc, status));
+ break;
+ }
+ switch (pConnect->ServiceID) {
+ case WMI_CONTROL_SVC :
+ if (ar->arWmiEnabled) {
+ /* set control endpoint for WMI use */
+ wmi_set_control_ep(ar->arWmi, response.Endpoint);
+ }
+ /* save EP for fast lookup */
+ ar->arControlEp = response.Endpoint;
+ break;
+ case WMI_DATA_BE_SVC :
+ arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint);
+ break;
+ case WMI_DATA_BK_SVC :
+ arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint);
+ break;
+ case WMI_DATA_VI_SVC :
+ arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint);
+ break;
+ case WMI_DATA_VO_SVC :
+ arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint);
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ServiceID not mapped %d\n", pConnect->ServiceID));
+ status = A_EINVAL;
+ break;
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+void ar6000_TxDataCleanup(AR_SOFTC_T *ar)
+{
+ /* flush all the data (non-control) streams
+ * we only flush packets that are tagged as data, we leave any control packets that
+ * were in the TX queues alone */
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arAc2EndpointID(ar, WMM_AC_BE),
+ AR6K_DATA_PKT_TAG);
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arAc2EndpointID(ar, WMM_AC_BK),
+ AR6K_DATA_PKT_TAG);
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arAc2EndpointID(ar, WMM_AC_VI),
+ AR6K_DATA_PKT_TAG);
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arAc2EndpointID(ar, WMM_AC_VO),
+ AR6K_DATA_PKT_TAG);
+}
+
+HTC_ENDPOINT_ID
+ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
+ return(arAc2EndpointID(ar, ac));
+}
+
+A_UINT8
+ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep )
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *) devt;
+ return(arEndpoint2Ac(ar, ep ));
+}
+
+/* This function does one time initialization for the lifetime of the device */
+int ar6000_init(struct net_device *dev)
+{
+ AR_SOFTC_T *ar;
+ A_STATUS status;
+ A_INT32 timeleft;
+ A_INT16 i;
+ int ret = 0;
+#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD sbcb_cmd;
+ WMI_SET_BTCOEX_FE_ANT_CMD sbfa_cmd;
+#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+
+ dev_hold(dev);
+ rtnl_unlock();
+
+ if((ar = ar6k_priv(dev)) == NULL)
+ {
+ ret = -EIO;
+ goto ar6000_init_done;
+ }
+
+ if (enablerssicompensation) {
+ read_rssi_compensation_param(ar);
+ for (i=-95; i<=0; i++) {
+ rssi_compensation_table[0-i] = rssi_compensation_calc(ar,i);
+ }
+ }
+
+ /* Do we need to finish the BMI phase */
+ if ((wlaninitmode == WLAN_INIT_MODE_USR) && (BMIDone(ar->arHifDevice) != A_OK))
+ {
+ ret = -EIO;
+ goto ar6000_init_done;
+ }
+
+ if (!bypasswmi)
+ {
+#if 0 /* TBDXXX */
+ if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
+ A_PRINTF("WARNING: Host version 0x%x does not match Target "
+ " version 0x%x!\n",
+ ar->arVersion.host_ver, ar->arVersion.target_ver);
+ }
+#endif
+
+ /* Indicate that WMI is enabled (although not ready yet) */
+ ar->arWmiEnabled = TRUE;
+ if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize WMI.\n", __func__));
+ ret = -EIO;
+ goto ar6000_init_done;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Got WMI @ 0x%08x.\n", __func__,
+ (unsigned int) ar->arWmi));
+ }
+
+ do {
+ HTC_SERVICE_CONNECT_REQ connect;
+
+ /* the reason we have to wait for the target here is that the driver layer
+ * has to init BMI in order to set the host block size,
+ */
+ status = HTCWaitTarget(ar->arHtcTarget);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ A_MEMZERO(&connect,sizeof(connect));
+ /* meta data is unused for now */
+ connect.pMetaData = NULL;
+ connect.MetaDataLength = 0;
+ /* these fields are the same for all service endpoints */
+ connect.EpCallbacks.pContext = ar;
+ connect.EpCallbacks.EpTxCompleteMultiple = ar6000_tx_complete;
+ connect.EpCallbacks.EpRecv = ar6000_rx;
+ connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill;
+ connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full;
+ /* set the max queue depth so that our ar6000_tx_queue_full handler gets called.
+ * Linux has the peculiarity of not providing flow control between the
+ * NIC and the network stack. There is no API to indicate that a TX packet
+ * was sent which could provide some back pressure to the network stack.
+ * Under linux you would have to wait till the network stack consumed all sk_buffs
+ * before any back-flow kicked in. Which isn't very friendly.
+ * So we have to manage this ourselves */
+ connect.MaxSendQueueDepth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
+ connect.EpCallbacks.RecvRefillWaterMark = AR6000_MAX_RX_BUFFERS / 4; /* set to 25 % */
+ if (0 == connect.EpCallbacks.RecvRefillWaterMark) {
+ connect.EpCallbacks.RecvRefillWaterMark++;
+ }
+ /* connect to control service */
+ connect.ServiceID = WMI_CONTROL_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ "WMI CONTROL");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ connect.LocalConnectionFlags |= HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING;
+ /* limit the HTC message size on the send path, although we can receive A-MSDU frames of
+ * 4K, we will only send ethernet-sized (802.3) frames on the send path. */
+ connect.MaxSendMsgSize = WMI_MAX_TX_DATA_FRAME_LENGTH;
+
+ /* to reduce the amount of committed memory for larger A_MSDU frames, use the recv-alloc threshold
+ * mechanism for larger packets */
+ connect.EpCallbacks.RecvAllocThreshold = AR6000_BUFFER_SIZE;
+ connect.EpCallbacks.EpRecvAllocThresh = ar6000_alloc_amsdu_rxbuf;
+
+ /* for the remaining data services set the connection flag to reduce dribbling,
+ * if configured to do so */
+ if (reduce_credit_dribble) {
+ connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE;
+ /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value
+ * of 0-3 */
+ connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+ connect.ConnectionFlags |=
+ ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+ }
+ /* connect to best-effort service */
+ connect.ServiceID = WMI_DATA_BE_SVC;
+
+ status = ar6000_connectservice(ar,
+ &connect,
+ "WMI DATA BE");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* connect to back-ground
+ * map this to WMI LOW_PRI */
+ connect.ServiceID = WMI_DATA_BK_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ "WMI DATA BK");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* connect to Video service, map this to
+ * to HI PRI */
+ connect.ServiceID = WMI_DATA_VI_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ "WMI DATA VI");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* connect to VO service, this is currently not
+ * mapped to a WMI priority stream due to historical reasons.
+ * WMI originally defined 3 priorities over 3 mailboxes
+ * We can change this when WMI is reworked so that priorities are not
+ * dependent on mailboxes */
+ connect.ServiceID = WMI_DATA_VO_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ "WMI DATA VO");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0);
+ A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0);
+ A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0);
+ A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0);
+
+ /* setup access class priority mappings */
+ ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest */
+ ar->arAcStreamPriMap[WMM_AC_BE] = 1; /* */
+ ar->arAcStreamPriMap[WMM_AC_VI] = 2; /* */
+ ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ if (setuphci && (NULL != ar6kHciTransCallbacks.setupTransport)) {
+ HCI_TRANSPORT_MISC_HANDLES hciHandles;
+
+ hciHandles.netDevice = ar->arNetDev;
+ hciHandles.hifDevice = ar->arHifDevice;
+ hciHandles.htcHandle = ar->arHtcTarget;
+ status = (A_STATUS)(ar6kHciTransCallbacks.setupTransport(&hciHandles));
+ }
+#else
+ if (setuphci) {
+ /* setup HCI */
+ status = ar6000_setup_hci(ar);
+ }
+#endif
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ ret = -EIO;
+ goto ar6000_init_done;
+ }
+
+ /*
+ * give our connected endpoints some buffers
+ */
+
+ ar6000_rx_refill(ar, ar->arControlEp);
+ ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE));
+
+ /*
+ * We will post the receive buffers only for SPE or endpoint ping testing so we are
+ * making it conditional on the 'bypasswmi' flag.
+ */
+ if (bypasswmi) {
+ ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK));
+ ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI));
+ ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO));
+ }
+
+ /* allocate some buffers that handle larger AMSDU frames */
+ ar6000_refill_amsdu_rxbufs(ar,AR6000_MAX_AMSDU_RX_BUFFERS);
+
+ /* setup credit distribution */
+ ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo);
+
+ /* Since cookies are used for HTC transports, they should be */
+ /* initialized prior to enabling HTC. */
+ ar6000_cookie_init(ar);
+
+ /* start HTC */
+ status = HTCStart(ar->arHtcTarget);
+
+ if (status != A_OK) {
+ if (ar->arWmiEnabled == TRUE) {
+ wmi_shutdown(ar->arWmi);
+ ar->arWmiEnabled = FALSE;
+ ar->arWmi = NULL;
+ }
+ ar6000_cookie_cleanup(ar);
+ ret = -EIO;
+ goto ar6000_init_done;
+ }
+
+ if (!bypasswmi) {
+ /* Wait for Wmi event to be ready */
+ timeleft = wait_event_interruptible_timeout(arEvent,
+ (ar->arWmiReady == TRUE), wmitimeout * HZ);
+
+ if(!timeleft || signal_pending(current))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI is not ready or wait was interrupted\n"));
+ ret = -EIO;
+ goto ar6000_init_done;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() WMI is ready\n", __func__));
+
+ /* Communicate the wmi protocol verision to the target */
+ if ((ar6000_set_host_app_area(ar)) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the host app area\n"));
+ }
+
+ /* configure the device for rx dot11 header rules 0,0 are the default values
+ * therefore this command can be skipped if the inputs are 0,FALSE,FALSE.Required
+ if checksum offload is needed. Set RxMetaVersion to 2*/
+ if ((wmi_set_rx_frame_format_cmd(ar->arWmi,ar->rxMetaVersion, processDot11Hdr, processDot11Hdr)) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the rx frame format.\n"));
+ }
+
+#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
+ /* Configure the type of BT collocated with WLAN */
+ A_MEMZERO(&sbcb_cmd, sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+#ifdef CONFIG_AR600x_BT_QCOM
+ sbcb_cmd.btcoexCoLocatedBTdev = 1;
+#elif defined(CONFIG_AR600x_BT_CSR)
+ sbcb_cmd.btcoexCoLocatedBTdev = 2;
+#elif defined(CONFIG_AR600x_BT_AR3001)
+ sbcb_cmd.btcoexCoLocatedBTdev = 3;
+#else
+#error Unsupported Bluetooth Type
+#endif /* Collocated Bluetooth Type */
+
+ if ((wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &sbcb_cmd)) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set collocated BT type\n"));
+ }
+
+ /* Configure the type of BT collocated with WLAN */
+ A_MEMZERO(&sbfa_cmd, sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+#ifdef CONFIG_AR600x_DUAL_ANTENNA
+ sbfa_cmd.btcoexFeAntType = 2;
+#elif defined(CONFIG_AR600x_SINGLE_ANTENNA)
+ sbfa_cmd.btcoexFeAntType = 1;
+#else
+#error Unsupported Front-End Antenna Configuration
+#endif /* AR600x Front-End Antenna Configuration */
+
+ if ((wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &sbfa_cmd)) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set fornt end antenna configuration\n"));
+ }
+#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+ }
+
+ ar->arNumDataEndPts = 1;
+
+ if (bypasswmi) {
+ /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise
+ * the data path through a raw socket is disabled */
+ dev->dev_addr[0] = 0x00;
+ dev->dev_addr[1] = 0x01;
+ dev->dev_addr[2] = 0x02;
+ dev->dev_addr[3] = 0xAA;
+ dev->dev_addr[4] = 0xBB;
+ dev->dev_addr[5] = 0xCC;
+ }
+
+#ifdef ANDROID_ENV
+ android_ar6k_start(ar);
+#endif
+
+ar6000_init_done:
+ rtnl_lock();
+ dev_put(dev);
+
+ return ret;
+}
+
+
+void
+ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arBitRate = rateKbps;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_ratemask_rx(void *devt, A_UINT32 ratemask)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arRateMask = ratemask;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arTxPwr = txPwr;
+ wake_up(&arEvent);
+}
+
+
+void
+ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
+ ar->arNumChannels = numChan;
+
+ wake_up(&arEvent);
+}
+
+A_UINT8
+ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT8 *datap;
+ ATH_MAC_HDR *macHdr;
+ A_UINT32 i, eptMap;
+
+ (*mapNo) = 0;
+ datap = A_NETBUF_DATA(skb);
+ macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
+ if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
+ return ENDPOINT_2;
+ }
+
+ eptMap = -1;
+ for (i = 0; i < ar->arNodeNum; i ++) {
+ if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
+ (*mapNo) = i + 1;
+ ar->arNodeMap[i].txPending ++;
+ return ar->arNodeMap[i].epId;
+ }
+
+ if ((eptMap == -1) && !ar->arNodeMap[i].txPending) {
+ eptMap = i;
+ }
+ }
+
+ if (eptMap == -1) {
+ eptMap = ar->arNodeNum;
+ ar->arNodeNum ++;
+ A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
+ }
+
+ A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
+
+ for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) {
+ if (!ar->arTxPending[i]) {
+ ar->arNodeMap[eptMap].epId = i;
+ break;
+ }
+ // No free endpoint is available, start redistribution on the inuse endpoints.
+ if (i == ENDPOINT_5) {
+ ar->arNodeMap[eptMap].epId = ar->arNexEpId;
+ ar->arNexEpId ++;
+ if (ar->arNexEpId > ENDPOINT_5) {
+ ar->arNexEpId = ENDPOINT_2;
+ }
+ }
+ }
+
+ (*mapNo) = eptMap + 1;
+ ar->arNodeMap[eptMap].txPending ++;
+
+ return ar->arNodeMap[eptMap].epId;
+}
+
+#ifdef DEBUG
+static void ar6000_dump_skb(struct sk_buff *skb)
+{
+ u_char *ch;
+ for (ch = A_NETBUF_DATA(skb);
+ (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) +
+ A_NETBUF_LEN(skb)); ch++)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("%2.2x ", *ch));
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("\n"));
+}
+#endif
+
+#ifdef HTC_TEST_SEND_PKTS
+static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *skb);
+#endif
+
+static int
+ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+#define AC_NOT_MAPPED 99
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT8 ac = AC_NOT_MAPPED;
+ HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED;
+ A_UINT32 mapNo = 0;
+ int len;
+ struct ar_cookie *cookie;
+ A_BOOL checkAdHocPsMapping = FALSE,bMoreData = FALSE;
+ HTC_TX_TAG htc_tag = AR6K_DATA_PKT_TAG;
+ A_UINT8 dot11Hdr = processDot11Hdr;
+#ifdef CONFIG_PM
+ if (ar->arWowState) {
+ A_NETBUF_FREE(skb);
+ return 0;
+ }
+#endif /* CONFIG_PM */
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)
+ skb->list = NULL;
+#endif
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
+ (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb),
+ A_NETBUF_LEN(skb)));
+
+ /* If target is not associated */
+ if( (!ar->arConnected && !bypasswmi)
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ /* TCMD doesnt support any data, free the buf and return */
+ || (ar->arTargetMode == AR6000_TCMD_MODE)
+#endif
+ ) {
+ A_NETBUF_FREE(skb);
+ return 0;
+ }
+
+ do {
+
+ if (ar->arWmiReady == FALSE && bypasswmi == 0) {
+ break;
+ }
+
+#ifdef BLOCK_TX_PATH_FLAG
+ if (blocktx) {
+ break;
+ }
+#endif /* BLOCK_TX_PATH_FLAG */
+
+ /* AP mode Power save processing */
+ /* If the dst STA is in sleep state, queue the pkt in its PS queue */
+
+ if (ar->arNetworkType == AP_NETWORK) {
+ ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+ sta_t *conn = NULL;
+
+ /* If the dstMac is a Multicast address & atleast one of the
+ * associated STA is in PS mode, then queue the pkt to the
+ * mcastq
+ */
+ if (IEEE80211_IS_MULTICAST(datap->dstMac)) {
+ A_UINT8 ctr=0;
+ A_BOOL qMcast=FALSE;
+
+
+ for (ctr=0; ctr<AP_MAX_NUM_STA; ctr++) {
+ if (STA_IS_PWR_SLEEP((&ar->sta_list[ctr]))) {
+ qMcast = TRUE;
+ }
+ }
+ if(qMcast) {
+
+ /* If this transmit is not because of a Dtim Expiry q it */
+ if (ar->DTIMExpired == FALSE) {
+ A_BOOL isMcastqEmpty = FALSE;
+
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq);
+ A_NETBUF_ENQUEUE(&ar->mcastpsq, skb);
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+ /* If this is the first Mcast pkt getting queued
+ * indicate to the target to set the BitmapControl LSB
+ * of the TIM IE.
+ */
+ if (isMcastqEmpty) {
+ wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1);
+ }
+ return 0;
+ } else {
+ /* This transmit is because of Dtim expiry. Determine if
+ * MoreData bit has to be set.
+ */
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+ bMoreData = TRUE;
+ }
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+ }
+ }
+ } else {
+ conn = ieee80211_find_conn(ar, datap->dstMac);
+ if (conn) {
+ if (STA_IS_PWR_SLEEP(conn)) {
+ /* If this transmit is not because of a PsPoll q it*/
+ if (!STA_IS_PS_POLLED(conn)) {
+ A_BOOL isPsqEmpty = FALSE;
+ /* Queue the frames if the STA is sleeping */
+ A_MUTEX_LOCK(&conn->psqLock);
+ isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+ A_NETBUF_ENQUEUE(&conn->psq, skb);
+ A_MUTEX_UNLOCK(&conn->psqLock);
+
+ /* If this is the first pkt getting queued
+ * for this STA, update the PVB for this STA
+ */
+ if (isPsqEmpty) {
+ wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1);
+ }
+
+ return 0;
+ } else {
+ /* This tx is because of a PsPoll. Determine if
+ * MoreData bit has to be set
+ */
+ A_MUTEX_LOCK(&conn->psqLock);
+ if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) {
+ bMoreData = TRUE;
+ }
+ A_MUTEX_UNLOCK(&conn->psqLock);
+ }
+ }
+ } else {
+
+ /* non existent STA. drop the frame */
+ A_NETBUF_FREE(skb);
+ return 0;
+ }
+ }
+ }
+
+ if (ar->arWmiEnabled) {
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+ A_UINT8 csumStart=0;
+ A_UINT8 csumDest=0;
+ A_UINT8 csum=skb->ip_summed;
+ if(csumOffload && (csum==CHECKSUM_PARTIAL)){
+ csumStart=skb->csum_start-(skb->network_header-skb->head)+sizeof(ATH_LLC_SNAP_HDR);
+ csumDest=skb->csum_offset+csumStart;
+ }
+#endif
+ if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len - LINUX_HACK_FUDGE_FACTOR) {
+ struct sk_buff *newbuf;
+
+ /*
+ * We really should have gotten enough headroom but sometimes
+ * we still get packets with not enough headroom. Copy the packet.
+ */
+ len = A_NETBUF_LEN(skb);
+ newbuf = A_NETBUF_ALLOC(len);
+ if (newbuf == NULL) {
+ break;
+ }
+ A_NETBUF_PUT(newbuf, len);
+ A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len);
+ A_NETBUF_FREE(skb);
+ skb = newbuf;
+ /* fall through and assemble header */
+ }
+
+ if (dot11Hdr) {
+ if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx-wmi_dot11_hdr_add failed\n"));
+ break;
+ }
+ } else {
+ if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_dix_2_dot3 failed\n"));
+ break;
+ }
+ }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+ if(csumOffload && (csum ==CHECKSUM_PARTIAL)){
+ WMI_TX_META_V2 metaV2;
+ metaV2.csumStart =csumStart;
+ metaV2.csumDest = csumDest;
+ metaV2.csumFlags = 0x1;/*instruct target to calculate checksum*/
+ if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,
+ WMI_META_VERSION_2,&metaV2) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
+ break;
+ }
+
+ }
+ else
+#endif
+ {
+ if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,0,NULL) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
+ break;
+ }
+ }
+
+
+ if ((ar->arNetworkType == ADHOC_NETWORK) &&
+ ar->arIbssPsEnable && ar->arConnected) {
+ /* flag to check adhoc mapping once we take the lock below: */
+ checkAdHocPsMapping = TRUE;
+
+ } else {
+ /* get the stream mapping */
+ ac = wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled);
+ }
+
+ } else {
+ EPPING_HEADER *eppingHdr;
+
+ eppingHdr = A_NETBUF_DATA(skb);
+
+ if (IS_EPPING_PACKET(eppingHdr)) {
+ /* the stream ID is mapped to an access class */
+ ac = eppingHdr->StreamNo_h;
+ /* some EPPING packets cannot be dropped no matter what access class it was
+ * sent on. We can change the packet tag to guarantee it will not get dropped */
+ if (IS_EPING_PACKET_NO_DROP(eppingHdr)) {
+ htc_tag = AR6K_CONTROL_PKT_TAG;
+ }
+
+ if (ac == HCI_TRANSPORT_STREAM_NUM) {
+ /* pass this to HCI */
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+ if (A_SUCCESS(hci_test_send(ar,skb))) {
+ return 0;
+ }
+#endif
+ /* set AC to discard this skb */
+ ac = AC_NOT_MAPPED;
+ } else {
+ /* a quirk of linux, the payload of the frame is 32-bit aligned and thus the addition
+ * of the HTC header will mis-align the start of the HTC frame, so we add some
+ * padding which will be stripped off in the target */
+ if (EPPING_ALIGNMENT_PAD > 0) {
+ A_NETBUF_PUSH(skb, EPPING_ALIGNMENT_PAD);
+ }
+ }
+
+ } else {
+ /* not a ping packet, drop it */
+ ac = AC_NOT_MAPPED;
+ }
+ }
+
+ } while (FALSE);
+
+ /* did we succeed ? */
+ if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) {
+ /* cleanup and exit */
+ A_NETBUF_FREE(skb);
+ AR6000_STAT_INC(ar, tx_dropped);
+ AR6000_STAT_INC(ar, tx_aborted_errors);
+ return 0;
+ }
+
+ cookie = NULL;
+
+ /* take the lock to protect driver data */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ do {
+
+ if (checkAdHocPsMapping) {
+ eid = ar6000_ibss_map_epid(skb, dev, &mapNo);
+ }else {
+ eid = arAc2EndpointID (ar, ac);
+ }
+ /* validate that the endpoint is connected */
+ if (eid == 0 || eid == ENDPOINT_UNUSED ) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" eid %d is NOT mapped!\n", eid));
+ break;
+ }
+ /* allocate resource for this packet */
+ cookie = ar6000_alloc_cookie(ar);
+
+ if (cookie != NULL) {
+ /* update counts while the lock is held */
+ ar->arTxPending[eid]++;
+ ar->arTotalTxDataPending++;
+ }
+
+ } while (FALSE);
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (cookie != NULL) {
+ cookie->arc_bp[0] = (A_UINT32)skb;
+ cookie->arc_bp[1] = mapNo;
+ SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+ cookie,
+ A_NETBUF_DATA(skb),
+ A_NETBUF_LEN(skb),
+ eid,
+ htc_tag);
+
+#ifdef DEBUG
+ if (debugdriver >= 3) {
+ ar6000_dump_skb(skb);
+ }
+#endif
+#ifdef HTC_TEST_SEND_PKTS
+ DoHTCSendPktsTest(ar,mapNo,eid,skb);
+#endif
+ /* HTC interface is asynchronous, if this fails, cleanup will happen in
+ * the ar6000_tx_complete callback */
+ HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+ } else {
+ /* no packet to send, cleanup */
+ A_NETBUF_FREE(skb);
+ AR6000_STAT_INC(ar, tx_dropped);
+ AR6000_STAT_INC(ar, tx_aborted_errors);
+ }
+
+ return 0;
+}
+
+int
+ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ struct ar_cookie *cookie;
+ HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED;
+
+ cookie = NULL;
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ /* For now we send ACL on BE endpoint: We can also have a dedicated EP */
+ eid = arAc2EndpointID (ar, 0);
+ /* allocate resource for this packet */
+ cookie = ar6000_alloc_cookie(ar);
+
+ if (cookie != NULL) {
+ /* update counts while the lock is held */
+ ar->arTxPending[eid]++;
+ ar->arTotalTxDataPending++;
+ }
+
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (cookie != NULL) {
+ cookie->arc_bp[0] = (A_UINT32)skb;
+ cookie->arc_bp[1] = 0;
+ SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+ cookie,
+ A_NETBUF_DATA(skb),
+ A_NETBUF_LEN(skb),
+ eid,
+ AR6K_DATA_PKT_TAG);
+
+ /* HTC interface is asynchronous, if this fails, cleanup will happen in
+ * the ar6000_tx_complete callback */
+ HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+ } else {
+ /* no packet to send, cleanup */
+ A_NETBUF_FREE(skb);
+ AR6000_STAT_INC(ar, tx_dropped);
+ AR6000_STAT_INC(ar, tx_aborted_errors);
+ }
+ return 0;
+}
+
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+static void
+tvsub(register struct timeval *out, register struct timeval *in)
+{
+ if((out->tv_usec -= in->tv_usec) < 0) {
+ out->tv_sec--;
+ out->tv_usec += 1000000;
+ }
+ out->tv_sec -= in->tv_sec;
+}
+
+void
+applyAPTCHeuristics(AR_SOFTC_T *ar)
+{
+ A_UINT32 duration;
+ A_UINT32 numbytes;
+ A_UINT32 throughput;
+ struct timeval ts;
+ A_STATUS status;
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) {
+ do_gettimeofday(&ts);
+ tvsub(&ts, &aptcTR.samplingTS);
+ duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */
+ numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+
+ if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) {
+ /* Initialize the time stamp and byte count */
+ aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+ do_gettimeofday(&aptcTR.samplingTS);
+
+ /* Calculate and decide based on throughput thresholds */
+ throughput = ((numbytes * 8) / duration);
+ if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) {
+ /* Disable Sleep and schedule a timer */
+ A_ASSERT(ar->arWmiReady == TRUE);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+ aptcTR.timerScheduled = TRUE;
+ }
+ }
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ HTC_SEND_FULL_ACTION action = HTC_SEND_FULL_KEEP;
+ A_BOOL stopNet = FALSE;
+ HTC_ENDPOINT_ID Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket);
+
+ do {
+
+ if (bypasswmi) {
+ int accessClass;
+
+ if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) {
+ /* don't drop special control packets */
+ break;
+ }
+
+ accessClass = arEndpoint2Ac(ar,Endpoint);
+ /* for endpoint ping testing drop Best Effort and Background */
+ if ((accessClass == WMM_AC_BE) || (accessClass == WMM_AC_BK)) {
+ action = HTC_SEND_FULL_DROP;
+ stopNet = FALSE;
+ } else {
+ /* keep but stop the netqueues */
+ stopNet = TRUE;
+ }
+ break;
+ }
+
+ if (Endpoint == ar->arControlEp) {
+ /* under normal WMI if this is getting full, then something is running rampant
+ * the host should not be exhausting the WMI queue with too many commands
+ * the only exception to this is during testing using endpointping */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ /* set flag to handle subsequent messages */
+ ar->arWMIControlEpFull = TRUE;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI Control Endpoint is FULL!!! \n"));
+ /* no need to stop the network */
+ stopNet = FALSE;
+ break;
+ }
+
+ /* if we get here, we are dealing with data endpoints getting full */
+
+ if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) {
+ /* don't drop control packets issued on ANY data endpoint */
+ break;
+ }
+
+ if (ar->arNetworkType == ADHOC_NETWORK) {
+ /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to
+ * continue, however we should stop the network */
+ stopNet = TRUE;
+ break;
+ }
+ /* the last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for the highest
+ * active stream */
+ if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri &&
+ ar->arCookieCount <= MAX_HI_COOKIE_NUM) {
+ /* this stream's priority is less than the highest active priority, we
+ * give preference to the highest priority stream by directing
+ * HTC to drop the packet that overflowed */
+ action = HTC_SEND_FULL_DROP;
+ /* since we are dropping packets, no need to stop the network */
+ stopNet = FALSE;
+ break;
+ }
+
+ } while (FALSE);
+
+ if (stopNet) {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arNetQueueStopped = TRUE;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ /* one of the data endpoints queues is getting full..need to stop network stack
+ * the queue will resume in ar6000_tx_complete() */
+ netif_stop_queue(ar->arNetDev);
+ }
+
+ return action;
+}
+
+
+static void
+ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPacketQueue)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ A_UINT32 mapNo = 0;
+ A_STATUS status;
+ struct ar_cookie * ar_cookie;
+ HTC_ENDPOINT_ID eid;
+ A_BOOL wakeEvent = FALSE;
+ struct sk_buff_head skb_queue;
+ HTC_PACKET *pPacket;
+ struct sk_buff *pktSkb;
+ A_BOOL flushing = FALSE;
+
+ skb_queue_head_init(&skb_queue);
+
+ /* lock the driver as we update internal state */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ /* reap completed packets */
+ while (!HTC_QUEUE_EMPTY(pPacketQueue)) {
+
+ pPacket = HTC_PACKET_DEQUEUE(pPacketQueue);
+
+ ar_cookie = (struct ar_cookie *)pPacket->pPktContext;
+ A_ASSERT(ar_cookie);
+
+ status = pPacket->Status;
+ pktSkb = (struct sk_buff *)ar_cookie->arc_bp[0];
+ eid = pPacket->Endpoint;
+ mapNo = ar_cookie->arc_bp[1];
+
+ A_ASSERT(pktSkb);
+ A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(pktSkb));
+
+ /* add this to the list, use faster non-lock API */
+ __skb_queue_tail(&skb_queue,pktSkb);
+
+ if (A_SUCCESS(status)) {
+ A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(pktSkb));
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ",
+ (A_UINT32)pktSkb, (A_UINT32)pPacket->pBuffer,
+ pPacket->ActualLength,
+ eid));
+
+ ar->arTxPending[eid]--;
+
+ if ((eid != ar->arControlEp) || bypasswmi) {
+ ar->arTotalTxDataPending--;
+ }
+
+ if (eid == ar->arControlEp)
+ {
+ if (ar->arWMIControlEpFull) {
+ /* since this packet completed, the WMI EP is no longer full */
+ ar->arWMIControlEpFull = FALSE;
+ }
+
+ if (ar->arTxPending[eid] == 0) {
+ wakeEvent = TRUE;
+ }
+ }
+
+ if (A_FAILED(status)) {
+ if (status == A_ECANCELED) {
+ /* a packet was flushed */
+ flushing = TRUE;
+ }
+ AR6000_STAT_INC(ar, tx_errors);
+ if (status != A_NO_RESOURCE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() -TX ERROR, status: 0x%x\n", __func__,
+ status));
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("OK\n"));
+ flushing = FALSE;
+ AR6000_STAT_INC(ar, tx_packets);
+ ar->arNetStats.tx_bytes += A_NETBUF_LEN(pktSkb);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ aptcTR.bytesTransmitted += a_netbuf_to_len(pktSkb);
+ applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+ }
+
+ // TODO this needs to be looked at
+ if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
+ && (eid != ar->arControlEp) && mapNo)
+ {
+ mapNo --;
+ ar->arNodeMap[mapNo].txPending --;
+
+ if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
+ A_UINT32 i;
+ for (i = ar->arNodeNum; i > 0; i --) {
+ if (!ar->arNodeMap[i - 1].txPending) {
+ A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
+ ar->arNodeNum --;
+ } else {
+ break;
+ }
+ }
+ }
+ }
+
+ ar6000_free_cookie(ar, ar_cookie);
+
+ if (ar->arNetQueueStopped) {
+ ar->arNetQueueStopped = FALSE;
+ }
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ /* lock is released, we can freely call other kernel APIs */
+
+ /* free all skbs in our local list */
+ while (!skb_queue_empty(&skb_queue)) {
+ /* use non-lock version */
+ pktSkb = __skb_dequeue(&skb_queue);
+ A_NETBUF_FREE(pktSkb);
+ }
+
+ if ((ar->arConnected == TRUE) || (bypasswmi)) {
+ if (!flushing) {
+ /* don't wake the queue if we are flushing, other wise it will just
+ * keep queueing packets, which will keep failing */
+ netif_wake_queue(ar->arNetDev);
+ }
+ }
+
+ if (wakeEvent) {
+ wake_up(&arEvent);
+ }
+
+}
+
+sta_t *
+ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr)
+{
+ sta_t *conn = NULL;
+ A_UINT8 i, max_conn;
+
+ switch(ar->arNetworkType) {
+ case AP_NETWORK:
+ max_conn = AP_MAX_NUM_STA;
+ break;
+ default:
+ max_conn=0;
+ break;
+ }
+
+ for (i = 0; i < max_conn; i++) {
+ if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) {
+ conn = &ar->sta_list[i];
+ break;
+ }
+ }
+
+ return conn;
+}
+
+sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid)
+{
+ sta_t *conn = NULL;
+ A_UINT8 ctr;
+
+ for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) {
+ if (ar->sta_list[ctr].aid == aid) {
+ conn = &ar->sta_list[ctr];
+ break;
+ }
+ }
+ return conn;
+}
+
+/*
+ * Receive event handler. This is called by HTC when a packet is received
+ */
+int pktcount;
+static void
+ar6000_rx(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext;
+ int minHdrLen;
+ A_UINT8 containsDot11Hdr = 0;
+ A_STATUS status = pPacket->Status;
+ HTC_ENDPOINT_ID ept = pPacket->Endpoint;
+
+ A_ASSERT((status != A_OK) ||
+ (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN)));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x status:%d",
+ (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
+ pPacket->ActualLength, status));
+ if (status != A_OK) {
+ if (status != A_ECANCELED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("RX ERR (%d) \n",status));
+ }
+ }
+
+ /* take lock to protect buffer counts
+ * and adaptive power throughput state */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if (A_SUCCESS(status)) {
+ AR6000_STAT_INC(ar, rx_packets);
+ ar->arNetStats.rx_bytes += pPacket->ActualLength;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ aptcTR.bytesReceived += a_netbuf_to_len(skb);
+ applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+ A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN);
+ A_NETBUF_PULL(skb, HTC_HEADER_LEN);
+
+#ifdef DEBUG
+ if (debugdriver >= 2) {
+ ar6000_dump_skb(skb);
+ }
+#endif /* DEBUG */
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ skb->dev = ar->arNetDev;
+ if (status != A_OK) {
+ AR6000_STAT_INC(ar, rx_errors);
+ A_NETBUF_FREE(skb);
+ } else if (ar->arWmiEnabled == TRUE) {
+ if (ept == ar->arControlEp) {
+ /*
+ * this is a wmi control msg
+ */
+#ifdef ANDROID_ENV
+ android_ar6k_check_wow_status(ar);
+#endif /* ANDROID_ENV */
+ wmi_control_rx(ar->arWmi, skb);
+ } else {
+ WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
+ A_UINT8 is_amsdu, tid, is_acl_data_frame;
+ is_acl_data_frame = WMI_DATA_HDR_GET_DATA_TYPE(dhdr) == WMI_DATA_HDR_DATA_TYPE_ACL;
+
+ /*
+ * this is a wmi data packet
+ */
+ // NWF
+
+ if (processDot11Hdr) {
+ minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR);
+ } else {
+ minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR);
+ }
+
+ /* In the case of AP mode we may receive NULL data frames
+ * that do not have LLC hdr. They are 16 bytes in size.
+ * Allow these frames in the AP mode.
+ * ACL data frames don't follow ethernet frame bounds for
+ * min length
+ */
+ if (ar->arNetworkType != AP_NETWORK && !is_acl_data_frame &&
+ ((pPacket->ActualLength < minHdrLen) ||
+ (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)))
+ {
+ /*
+ * packet is too short or too long
+ */
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("TOO SHORT or TOO LONG\n"));
+ AR6000_STAT_INC(ar, rx_errors);
+ AR6000_STAT_INC(ar, rx_length_errors);
+ A_NETBUF_FREE(skb);
+ } else {
+ A_UINT16 seq_no;
+ A_UINT8 meta_type;
+
+#if 0
+ /* Access RSSI values here */
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("RSSI %d\n",
+ ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi));
+#endif
+ /* Get the Power save state of the STA */
+ if (ar->arNetworkType == AP_NETWORK) {
+ sta_t *conn = NULL;
+ A_UINT8 psState=0,prevPsState;
+ ATH_MAC_HDR *datap=NULL;
+ A_UINT16 offset;
+
+ meta_type = WMI_DATA_HDR_GET_META(dhdr);
+
+ psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info
+ >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK;
+
+ offset = sizeof(WMI_DATA_HDR);
+
+ switch (meta_type) {
+ case 0:
+ break;
+ case WMI_META_VERSION_1:
+ offset += sizeof(WMI_RX_META_V1);
+ break;
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+ case WMI_META_VERSION_2:
+ offset += sizeof(WMI_RX_META_V2);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+offset);
+ conn = ieee80211_find_conn(ar, datap->srcMac);
+
+ if (conn) {
+ /* if there is a change in PS state of the STA,
+ * take appropriate steps.
+ * 1. If Sleep-->Awake, flush the psq for the STA
+ * Clear the PVB for the STA.
+ * 2. If Awake-->Sleep, Starting queueing frames
+ * the STA.
+ */
+ prevPsState = STA_IS_PWR_SLEEP(conn);
+ if (psState) {
+ STA_SET_PWR_SLEEP(conn);
+ } else {
+ STA_CLR_PWR_SLEEP(conn);
+ }
+
+ if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) {
+
+ if (!STA_IS_PWR_SLEEP(conn)) {
+
+ A_MUTEX_LOCK(&conn->psqLock);
+ while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) {
+ struct sk_buff *skb=NULL;
+
+ skb = A_NETBUF_DEQUEUE(&conn->psq);
+ A_MUTEX_UNLOCK(&conn->psqLock);
+ ar6000_data_tx(skb,ar->arNetDev);
+ A_MUTEX_LOCK(&conn->psqLock);
+ }
+ A_MUTEX_UNLOCK(&conn->psqLock);
+ /* Clear the PVB for this STA */
+ wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0);
+ }
+ }
+ } else {
+ /* This frame is from a STA that is not associated*/
+ A_ASSERT(FALSE);
+ }
+
+ /* Drop NULL data frames here */
+ if((pPacket->ActualLength < minHdrLen) ||
+ (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)) {
+ A_NETBUF_FREE(skb);
+ goto rx_done;
+ }
+ }
+
+ is_amsdu = WMI_DATA_HDR_IS_AMSDU(dhdr);
+ tid = WMI_DATA_HDR_GET_UP(dhdr);
+ seq_no = WMI_DATA_HDR_GET_SEQNO(dhdr);
+ meta_type = WMI_DATA_HDR_GET_META(dhdr);
+ containsDot11Hdr = WMI_DATA_HDR_GET_DOT11(dhdr);
+
+ wmi_data_hdr_remove(ar->arWmi, skb);
+
+ switch (meta_type) {
+ case WMI_META_VERSION_1:
+ {
+ WMI_RX_META_V1 *pMeta = (WMI_RX_META_V1 *)A_NETBUF_DATA(skb);
+ A_PRINTF("META %d %d %d %d %x\n", pMeta->status, pMeta->rix, pMeta->rssi, pMeta->channel, pMeta->flags);
+ A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V1));
+ break;
+ }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+ case WMI_META_VERSION_2:
+ {
+ WMI_RX_META_V2 *pMeta = (WMI_RX_META_V2 *)A_NETBUF_DATA(skb);
+ if(pMeta->csumFlags & 0x1){
+ skb->ip_summed=CHECKSUM_COMPLETE;
+ skb->csum=(pMeta->csum);
+ }
+ A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V2));
+ break;
+ }
+#endif
+ default:
+ break;
+ }
+
+ A_ASSERT(status == A_OK);
+
+ /* NWF: print the 802.11 hdr bytes */
+ if(containsDot11Hdr) {
+ status = wmi_dot11_hdr_remove(ar->arWmi,skb);
+ } else if(!is_amsdu && !is_acl_data_frame) {
+ status = wmi_dot3_2_dix(skb);
+ }
+
+ if (status != A_OK) {
+ /* Drop frames that could not be processed (lack of memory, etc.) */
+ A_NETBUF_FREE(skb);
+ goto rx_done;
+ }
+
+ if (is_acl_data_frame) {
+ A_NETBUF_PUSH(skb, sizeof(int));
+ *((short *)A_NETBUF_DATA(skb)) = WMI_ACL_DATA_EVENTID;
+ }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+ /*
+ * extra push and memcpy, for eth_type_trans() of 2.4 kernel
+ * will pull out hard_header_len bytes of the skb.
+ */
+ A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN);
+ A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR));
+#endif
+ if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) {
+ if (ar->arNetworkType == AP_NETWORK) {
+ struct sk_buff *skb1 = NULL;
+ ATH_MAC_HDR *datap;
+
+ datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
+ if (IEEE80211_IS_MULTICAST(datap->dstMac)) {
+ /* Bcast/Mcast frames should be sent to the OS
+ * stack as well as on the air.
+ */
+ skb1 = skb_copy(skb,GFP_ATOMIC);
+ } else {
+ /* Search for a connected STA with dstMac as
+ * the Mac address. If found send the frame to
+ * it on the air else send the frame up the
+ * stack
+ */
+ sta_t *conn = NULL;
+ conn = ieee80211_find_conn(ar, datap->dstMac);
+
+ if (conn && ar->intra_bss) {
+ skb1 = skb;
+ skb = NULL;
+ } else if(conn && !ar->intra_bss) {
+ A_NETBUF_FREE(skb);
+ skb = NULL;
+ }
+ }
+ if (skb1) {
+ ar6000_data_tx(skb1, ar->arNetDev);
+ }
+ }
+ }
+#ifdef ATH_AR6K_11N_SUPPORT
+ aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no, is_amsdu, (void **)&skb);
+#endif
+ ar6000_deliver_frames_to_nw_stack((void *) ar->arNetDev, (void *)skb);
+ }
+ }
+ } else {
+ if (EPPING_ALIGNMENT_PAD > 0) {
+ A_NETBUF_PULL(skb, EPPING_ALIGNMENT_PAD);
+ }
+ ar6000_deliver_frames_to_nw_stack((void *)ar->arNetDev, (void *)skb);
+ }
+
+rx_done:
+
+ return;
+}
+
+static void
+ar6000_deliver_frames_to_nw_stack(void *dev, void *osbuf)
+{
+ struct sk_buff *skb = (struct sk_buff *)osbuf;
+
+ if(skb) {
+ skb->dev = dev;
+ if ((skb->dev->flags & IFF_UP) == IFF_UP) {
+ skb->protocol = eth_type_trans(skb, skb->dev);
+ /*
+ * If this routine is called on a ISR (Hard IRQ) or DSR (Soft IRQ)
+ * or tasklet use the netif_rx to deliver the packet to the stack
+ * netif_rx will queue the packet onto the receive queue and mark
+ * the softirq thread has a pending action to complete. Kernel will
+ * schedule the softIrq kernel thread after processing the DSR.
+ *
+ * If this routine is called on a process context, use netif_rx_ni
+ * which will schedle the softIrq kernel thread after queuing the packet.
+ */
+ if (in_interrupt()) {
+ netif_rx(skb);
+ } else {
+ netif_rx_ni(skb);
+ }
+ } else {
+ A_NETBUF_FREE(skb);
+ }
+ }
+}
+
+#if 0
+static void
+ar6000_deliver_frames_to_bt_stack(void *dev, void *osbuf)
+{
+ struct sk_buff *skb = (struct sk_buff *)osbuf;
+
+ if(skb) {
+ skb->dev = dev;
+ if ((skb->dev->flags & IFF_UP) == IFF_UP) {
+ skb->protocol = htons(ETH_P_CONTROL);
+ netif_rx(skb);
+ } else {
+ A_NETBUF_FREE(skb);
+ }
+ }
+}
+#endif
+
+static void
+ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ void *osBuf;
+ int RxBuffers;
+ int buffersToRefill;
+ HTC_PACKET *pPacket;
+ HTC_PACKET_QUEUE queue;
+
+ buffersToRefill = (int)AR6000_MAX_RX_BUFFERS -
+ HTCGetNumRecvBuffers(ar->arHtcTarget, Endpoint);
+
+ if (buffersToRefill <= 0) {
+ /* fast return, nothing to fill */
+ return;
+ }
+
+ INIT_HTC_PACKET_QUEUE(&queue);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
+ buffersToRefill, Endpoint));
+
+ for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) {
+ osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE);
+ if (NULL == osBuf) {
+ break;
+ }
+ /* the HTC packet wrapper is at the head of the reserved area
+ * in the skb */
+ pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+ /* set re-fill info */
+ SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint);
+ /* add to queue */
+ HTC_PACKET_ENQUEUE(&queue,pPacket);
+ }
+
+ if (!HTC_QUEUE_EMPTY(&queue)) {
+ /* add packets */
+ HTCAddReceivePktMultiple(ar->arHtcTarget, &queue);
+ }
+
+}
+
+ /* clean up our amsdu buffer list */
+static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar)
+{
+ HTC_PACKET *pPacket;
+ void *osBuf;
+
+ /* empty AMSDU buffer queue and free OS bufs */
+ while (TRUE) {
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (NULL == pPacket) {
+ break;
+ }
+
+ osBuf = pPacket->pPktContext;
+ if (NULL == osBuf) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ A_NETBUF_FREE(osBuf);
+ }
+
+}
+
+
+ /* refill the amsdu buffer list */
+static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count)
+{
+ HTC_PACKET *pPacket;
+ void *osBuf;
+
+ while (Count > 0) {
+ osBuf = A_NETBUF_ALLOC(AR6000_AMSDU_BUFFER_SIZE);
+ if (NULL == osBuf) {
+ break;
+ }
+ /* the HTC packet wrapper is at the head of the reserved area
+ * in the skb */
+ pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+ /* set re-fill info */
+ SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_AMSDU_BUFFER_SIZE,0);
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ /* put it in the list */
+ HTC_PACKET_ENQUEUE(&ar->amsdu_rx_buffer_queue,pPacket);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ Count--;
+ }
+
+}
+
+ /* callback to allocate a large receive buffer for a pending packet. This function is called when
+ * an HTC packet arrives whose length exceeds a threshold value
+ *
+ * We use a pre-allocated list of buffers of maximum AMSDU size (4K). Under linux it is more optimal to
+ * keep the allocation size the same to optimize cached-slab allocations.
+ *
+ * */
+static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length)
+{
+ HTC_PACKET *pPacket = NULL;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ int refillCount = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_alloc_amsdu_rxbuf: eid=%d, Length:%d\n",Endpoint,Length));
+
+ do {
+
+ if (Length <= AR6000_BUFFER_SIZE) {
+ /* shouldn't be getting called on normal sized packets */
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ if (Length > AR6000_AMSDU_BUFFER_SIZE) {
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ /* allocate a packet from the list */
+ pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue);
+ /* see if we need to refill again */
+ refillCount = AR6000_MAX_AMSDU_RX_BUFFERS - HTC_PACKET_QUEUE_DEPTH(&ar->amsdu_rx_buffer_queue);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (NULL == pPacket) {
+ break;
+ }
+ /* set actual endpoint ID */
+ pPacket->Endpoint = Endpoint;
+
+ } while (FALSE);
+
+ if (refillCount >= AR6000_AMSDU_REFILL_THRESHOLD) {
+ ar6000_refill_amsdu_rxbufs(ar,refillCount);
+ }
+
+ return pPacket;
+}
+
+
+static struct net_device_stats *
+ar6000_get_stats(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ return &ar->arNetStats;
+}
+
+static struct iw_statistics *
+ar6000_get_iwstats(struct net_device * dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ struct iw_statistics * pIwStats = &ar->arIwStats;
+ int rtnllocked;
+
+ if (ar->bIsDestroyProgress || ar->arWmiReady == FALSE)
+ {
+ pIwStats->status = 0;
+ pIwStats->qual.qual = 0;
+ pIwStats->qual.level =0;
+ pIwStats->qual.noise = 0;
+ pIwStats->discard.code =0;
+ pIwStats->discard.retries=0;
+ pIwStats->miss.beacon =0;
+ return pIwStats;
+ }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ /*
+ * The in_atomic function is used to determine if the scheduling is
+ * allowed in the current context or not. This was introduced in 2.6
+ * From what I have read on the differences between 2.4 and 2.6, the
+ * 2.4 kernel did not support preemption and so this check might not
+ * be required for 2.4 kernels.
+ */
+ if (in_atomic())
+ {
+ wmi_get_stats_cmd(ar->arWmi);
+
+ pIwStats->status = 1 ;
+ pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
+ pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */
+ pIwStats->qual.noise = pStats->noise_floor_calibation;
+ pIwStats->discard.code = pStats->rx_decrypt_err;
+ pIwStats->discard.retries = pStats->tx_retry_cnt;
+ pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+ return pIwStats;
+ }
+#endif /* LINUX_VERSION_CODE */
+
+ if (down_interruptible(&ar->arSem)) {
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+
+ ar->statsUpdatePending = TRUE;
+
+ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+
+ dev_hold(dev);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ rtnllocked = rtnl_is_locked();
+#else
+ rtnllocked = TRUE;
+#endif
+ if (rtnllocked) {
+ rtnl_unlock();
+ }
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+ if (rtnllocked) {
+ rtnl_lock();
+ }
+ dev_put(dev);
+
+ if (signal_pending(current)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : WMI get stats timeout \n"));
+ up(&ar->arSem);
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+ pIwStats->status = 1 ;
+ pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
+ pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */
+ pIwStats->qual.noise = pStats->noise_floor_calibation;
+ pIwStats->discard.code = pStats->rx_decrypt_err;
+ pIwStats->discard.retries = pStats->tx_retry_cnt;
+ pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+ up(&ar->arSem);
+ return pIwStats;
+}
+
+void
+ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ struct net_device *dev = ar->arNetDev;
+
+ ar->arWmiReady = TRUE;
+ wake_up(&arEvent);
+ A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+ dev->dev_addr[0], dev->dev_addr[1],
+ dev->dev_addr[2], dev->dev_addr[3],
+ dev->dev_addr[4], dev->dev_addr[5]));
+
+ ar->arPhyCapability = phyCap;
+ ar->arVersion.wlan_ver = vers;
+
+#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+ wmi_pmparams_cmd(ar->arWmi, 0, 1, 0, 0, 1, IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN);
+#endif
+#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP
+ wmi_set_lpreamble_cmd(ar->arWmi, 0, WMI_DONOT_IGNORE_BARKER_IN_ERP);
+#endif
+ wmi_set_keepalive_cmd(ar->arWmi, WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
+}
+
+A_UINT8
+add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie,
+ A_UINT8 ielen, A_UINT8 keymgmt, A_UINT8 ucipher, A_UINT8 auth)
+{
+ A_INT8 free_slot=-1, i;
+
+ for(i=0; i < AP_MAX_NUM_STA; i++) {
+ if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) {
+ /* it is already available */
+ return 0;
+ }
+
+ if(!((1 << i) & ar->sta_list_index)) {
+ free_slot = i;
+ break;
+ }
+ }
+
+ if(free_slot >= 0) {
+ A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN);
+ A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen);
+ ar->sta_list[free_slot].aid = aid;
+ ar->sta_list[free_slot].keymgmt = keymgmt;
+ ar->sta_list[free_slot].ucipher = ucipher;
+ ar->sta_list[free_slot].auth = auth;
+ ar->sta_list_index = ar->sta_list_index | (1 << free_slot);
+ ar->arAPStats.sta[aid-1].aid = aid;
+ return 1;
+ }
+ return 0; /* not added */
+}
+
+void
+ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
+ A_UINT16 listenInterval, A_UINT16 beaconInterval,
+ NETWORK_TYPE networkType, A_UINT8 beaconIeLen,
+ A_UINT8 assocReqLen, A_UINT8 assocRespLen,
+ A_UINT8 *assocInfo)
+{
+ union iwreq_data wrqu;
+ int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
+ static const char *tag1 = "ASSOCINFO(ReqIEs=";
+ static const char *tag2 = "ASSOCRESPIE=";
+ static const char *beaconIetag = "BEACONIE=";
+ char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1];
+ char *pos;
+ A_UINT8 key_op_ctrl;
+ unsigned long flags;
+ struct ieee80211req_key *ik;
+ CRYPTO_TYPE keyType = NONE_CRYPT;
+
+ if(ar->arNetworkType & AP_NETWORK) {
+ struct net_device *dev = ar->arNetDev;
+ if(A_MEMCMP(dev->dev_addr, bssid, ATH_MAC_LEN)==0) {
+ ar->arACS = channel;
+ ik = &ar->ap_mode_bkey;
+
+ switch(ar->arAuthMode) {
+ case NONE_AUTH:
+ if(ar->arPairwiseCrypto == WEP_CRYPT) {
+ ar6000_install_static_wep_keys(ar);
+ }
+#ifdef WAPI_ENABLE
+ else if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+ ap_set_wapi_key(ar, ik);
+ }
+#endif
+ break;
+ case WPA_PSK_AUTH:
+ case WPA2_PSK_AUTH:
+ case (WPA_PSK_AUTH|WPA2_PSK_AUTH):
+ switch (ik->ik_type) {
+ case IEEE80211_CIPHER_TKIP:
+ keyType = TKIP_CRYPT;
+ break;
+ case IEEE80211_CIPHER_AES_CCM:
+ keyType = AES_CRYPT;
+ break;
+ default:
+ goto skip_key;
+ }
+ wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE,
+ ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+ ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+ SYNC_BOTH_WMIFLAG);
+
+ break;
+ }
+skip_key:
+ ar->arConnected = TRUE;
+ return;
+ }
+
+ A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x \n "
+ " AID=%d \n", bssid[0], bssid[1], bssid[2],
+ bssid[3], bssid[4], bssid[5], channel);
+ switch ((listenInterval>>8)&0xFF) {
+ case OPEN_AUTH:
+ A_PRINTF("AUTH: OPEN\n");
+ break;
+ case SHARED_AUTH:
+ A_PRINTF("AUTH: SHARED\n");
+ break;
+ default:
+ A_PRINTF("AUTH: Unknown\n");
+ break;
+ };
+ switch (listenInterval&0xFF) {
+ case WPA_PSK_AUTH:
+ A_PRINTF("KeyMgmt: WPA-PSK\n");
+ break;
+ case WPA2_PSK_AUTH:
+ A_PRINTF("KeyMgmt: WPA2-PSK\n");
+ break;
+ default:
+ A_PRINTF("KeyMgmt: NONE\n");
+ break;
+ };
+ switch (beaconInterval) {
+ case AES_CRYPT:
+ A_PRINTF("Cipher: AES\n");
+ break;
+ case TKIP_CRYPT:
+ A_PRINTF("Cipher: TKIP\n");
+ break;
+ case WEP_CRYPT:
+ A_PRINTF("Cipher: WEP\n");
+ break;
+#ifdef WAPI_ENABLE
+ case WAPI_CRYPT:
+ A_PRINTF("Cipher: WAPI\n");
+ break;
+#endif
+ default:
+ A_PRINTF("Cipher: NONE\n");
+ break;
+ };
+
+ add_new_sta(ar, bssid, channel /*aid*/,
+ assocInfo /* WPA IE */, assocRespLen /* IE len */,
+ listenInterval&0xFF /* Keymgmt */, beaconInterval /* cipher */,
+ (listenInterval>>8)&0xFF /* auth alg */);
+
+ /* Send event to application */
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN);
+ wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL);
+ /* In case the queue is stopped when we switch modes, this will
+ * wake it up
+ */
+ netif_wake_queue(ar->arNetDev);
+ return;
+ }
+
+#ifdef ATH6K_CONFIG_CFG80211
+ ar6k_cfg80211_connect_event(ar, channel, bssid,
+ listenInterval, beaconInterval,
+ networkType, beaconIeLen,
+ assocReqLen, assocRespLen,
+ assocInfo);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+ A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
+ ar->arBssChannel = channel;
+
+ A_PRINTF("AR6000 connected event on freq %d ", channel);
+ A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+ " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d"
+ " assocRespLen =%d\n",
+ bssid[0], bssid[1], bssid[2],
+ bssid[3], bssid[4], bssid[5],
+ listenInterval, beaconInterval,
+ beaconIeLen, assocReqLen, assocRespLen);
+ if (networkType & ADHOC_NETWORK) {
+ if (networkType & ADHOC_CREATOR) {
+ A_PRINTF("Network: Adhoc (Creator)\n");
+ } else {
+ A_PRINTF("Network: Adhoc (Joiner)\n");
+ }
+ } else {
+ A_PRINTF("Network: Infrastructure\n");
+ }
+
+ if ((ar->arNetworkType == INFRA_NETWORK)) {
+ wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0);
+ }
+
+ if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nBeaconIEs= "));
+
+ beacon_ie_pos = 0;
+ A_MEMZERO(buf, sizeof(buf));
+ sprintf(buf, "%s", beaconIetag);
+ pos = buf + 9;
+ for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+ sprintf(pos, "%2.2x", assocInfo[i]);
+ pos += 2;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+
+ if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
+ {
+ assoc_resp_ie_pos = beaconIeLen + assocReqLen +
+ sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16) + /* status Code */
+ sizeof(A_UINT16) ; /* associd */
+ A_MEMZERO(buf, sizeof(buf));
+ sprintf(buf, "%s", tag2);
+ pos = buf + 12;
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocRespIEs= "));
+ /*
+ * The Association Response Frame w.o. the WLAN header is delivered to
+ * the host, so skip over to the IEs
+ */
+ for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+ sprintf(pos, "%2.2x", assocInfo[i]);
+ pos += 2;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+
+ if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
+ /*
+ * assoc Request includes capability and listen interval. Skip these.
+ */
+ assoc_req_ie_pos = beaconIeLen +
+ sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16); /* listen interval */
+
+ A_MEMZERO(buf, sizeof(buf));
+ sprintf(buf, "%s", tag1);
+ pos = buf + 17;
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AssocReqIEs= "));
+ for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+ sprintf(pos, "%2.2x", assocInfo[i]);
+ pos += 2;;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+
+#ifdef USER_KEYS
+ if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
+ ar->user_saved_keys.keyOk == TRUE)
+ {
+ key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC;
+
+ if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) {
+ key_op_ctrl &= ~KEY_OP_INIT_RSC;
+ } else {
+ key_op_ctrl |= KEY_OP_INIT_RSC;
+ }
+ ar6000_reinstall_keys(ar, key_op_ctrl);
+ }
+#endif /* USER_KEYS */
+
+ netif_wake_queue(ar->arNetDev);
+
+ if ((networkType & ADHOC_NETWORK) &&
+ (OPEN_AUTH == ar->arDot11AuthMode) &&
+ (NONE_AUTH == ar->arAuthMode) &&
+ (WEP_CRYPT == ar->arPairwiseCrypto))
+ {
+ if (!ar->arConnected) {
+ wmi_addKey_cmd(ar->arWmi,
+ ar->arDefTxKeyIndex,
+ WEP_CRYPT,
+ GROUP_USAGE | TX_USAGE,
+ ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen,
+ NULL,
+ ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL,
+ NO_SYNC_WMIFLAG);
+ }
+ }
+
+ /* Update connect & link status atomically */
+ spin_lock_irqsave(&ar->arLock, flags);
+ ar->arConnected = TRUE;
+ ar->arConnectPending = FALSE;
+ netif_carrier_on(ar->arNetDev);
+ spin_unlock_irqrestore(&ar->arLock, flags);
+ /* reset the rx aggr state */
+ aggr_reset_state(ar->aggr_cntxt);
+ reconnect_flag = 0;
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
+ wrqu.addr.sa_family = ARPHRD_ETHER;
+ wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+ if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
+ A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
+ ar->arNodeNum = 0;
+ ar->arNexEpId = ENDPOINT_2;
+ }
+ if (!ar->arUserBssFilter) {
+ wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+ }
+
+}
+
+void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
+{
+ A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
+ ar->arNumDataEndPts = num;
+}
+
+void
+sta_cleanup(AR_SOFTC_T *ar, A_UINT8 i)
+{
+ struct sk_buff *skb;
+
+ /* empty the queued pkts in the PS queue if any */
+ A_MUTEX_LOCK(&ar->sta_list[i].psqLock);
+ while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) {
+ skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq);
+ A_NETBUF_FREE(skb);
+ }
+ A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock);
+
+ /* Zero out the state fields */
+ A_MEMZERO(&ar->arAPStats.sta[ar->sta_list[i].aid-1], sizeof(WMI_PER_STA_STAT));
+ A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN);
+ A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE);
+ ar->sta_list[i].aid = 0;
+ ar->sta_list[i].flags = 0;
+
+ ar->sta_list_index = ar->sta_list_index & ~(1 << i);
+
+}
+
+A_UINT8
+remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason)
+{
+ A_UINT8 i, removed=0;
+
+ if(IS_MAC_NULL(mac)) {
+ return removed;
+ }
+
+ if(IS_MAC_BCAST(mac)) {
+ A_PRINTF("DEL ALL STA\n");
+ for(i=0; i < AP_MAX_NUM_STA; i++) {
+ if(!IS_MAC_NULL(ar->sta_list[i].mac)) {
+ sta_cleanup(ar, i);
+ removed = 1;
+ }
+ }
+ } else {
+ for(i=0; i < AP_MAX_NUM_STA; i++) {
+ if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) {
+ A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+ " aid=%d REASON=%d\n", mac[0], mac[1], mac[2],
+ mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason);
+
+ sta_cleanup(ar, i);
+ removed = 1;
+ break;
+ }
+ }
+ }
+ return removed;
+}
+
+void
+ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
+ A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+ A_UINT8 i;
+ unsigned long flags;
+
+ if(ar->arNetworkType & AP_NETWORK) {
+ union iwreq_data wrqu;
+ struct sk_buff *skb;
+
+ if(!remove_sta(ar, bssid, protocolReasonStatus)) {
+ return;
+ }
+
+ /* If there are no more associated STAs, empty the mcast PS q */
+ if (ar->sta_list_index == 0) {
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+ skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+ A_NETBUF_FREE(skb);
+ }
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+ /* Clear the LSB of the BitMapCtl field of the TIM IE */
+ wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0);
+ }
+
+ if(!IS_MAC_BCAST(bssid)) {
+ /* Send event to application */
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN);
+ wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL);
+ }
+ return;
+ }
+
+#ifdef ATH6K_CONFIG_CFG80211
+ ar6k_cfg80211_disconnect_event(ar, reason, bssid,
+ assocRespLen, assocInfo,
+ protocolReasonStatus);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+ if (NO_NETWORK_AVAIL != reason)
+ {
+ union iwreq_data wrqu;
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.addr.sa_family = ARPHRD_ETHER;
+
+ /* Send disconnect event to supplicant */
+ wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+ }
+ /* it is necessary to clear the host-side rx aggregation state */
+
+ aggr_reset_state(ar->aggr_cntxt);
+
+ A_UNTIMEOUT(&ar->disconnect_timer);
+
+ A_PRINTF("AR6000 disconnected");
+ if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
+ A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+ bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nDisconnect Reason is %d", reason));
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nProtocol Reason/Status Code is %d", protocolReasonStatus));
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocResp Frame = %s",
+ assocRespLen ? " " : "NULL"));
+ for (i = 0; i < assocRespLen; i++) {
+ if (!(i % 0x10)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i]));
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n"));
+ /*
+ * If the event is due to disconnect cmd from the host, only they the target
+ * would stop trying to connect. Under any other condition, target would
+ * keep trying to connect.
+ *
+ */
+ if( reason == DISCONNECT_CMD)
+ {
+ ar->arConnectPending = FALSE;
+ if (!ar->arUserBssFilter) {
+ wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+ }
+ } else {
+ ar->arConnectPending = TRUE;
+ if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) ||
+ ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) {
+ ar->arConnected = TRUE;
+ return;
+ }
+ }
+
+ if (reason == NO_NETWORK_AVAIL)
+ {
+ bss_t *pWmiSsidnode = NULL;
+
+ /* remove the current associated bssid node */
+ wmi_free_node (ar->arWmi, bssid);
+
+ /*
+ * In case any other same SSID nodes are present
+ * remove it, since those nodes also not available now
+ */
+ do
+ {
+ /*
+ * Find the nodes based on SSID and remove it
+ * NOTE :: This case will not work out for Hidden-SSID
+ */
+ pWmiSsidnode = wmi_find_Ssidnode (ar->arWmi, ar->arSsid, ar->arSsidLen, FALSE, TRUE);
+
+ if (pWmiSsidnode)
+ {
+ wmi_free_node (ar->arWmi, pWmiSsidnode->ni_macaddr);
+ }
+
+ }while (pWmiSsidnode);
+
+#if 0
+ /*
+ * Issuing a disconnect cmd prevent the firmware from
+ * continuing the scan and connect to the AP, if the AP
+ * cannot be found in 10 seconds. The user has to issue
+ * the iwconfig command again to connect to the AP.
+ * This change came in CL#575412 (EV# 59469) has to
+ * be fixed in a different way
+ */
+ ar6000_init_profile_info(ar);
+ wmi_disconnect_cmd(ar->arWmi);
+#endif
+ }
+
+ /* Update connect & link status atomically */
+ spin_lock_irqsave(&ar->arLock, flags);
+ ar->arConnected = FALSE;
+ netif_carrier_off(ar->arNetDev);
+ spin_unlock_irqrestore(&ar->arLock, flags);
+
+ if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) {
+ reconnect_flag = 0;
+ }
+
+#ifdef USER_KEYS
+ if (reason != CSERV_DISCONNECT)
+ {
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+ ar->user_key_ctrl = 0;
+ }
+#endif /* USER_KEYS */
+
+ netif_stop_queue(ar->arNetDev);
+ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+ ar->arBssChannel = 0;
+ ar->arBeaconInterval = 0;
+
+ ar6000_TxDataCleanup(ar);
+}
+
+void
+ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
+{
+ A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
+ ar->arRegCode = regCode;
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+void
+ar6000_aggr_rcv_addba_req_evt(AR_SOFTC_T *ar, WMI_ADDBA_REQ_EVENT *evt)
+{
+ if(evt->status == 0) {
+ aggr_recv_addba_req_evt(ar->aggr_cntxt, evt->tid, evt->st_seq_no, evt->win_sz);
+ }
+}
+
+void
+ar6000_aggr_rcv_addba_resp_evt(AR_SOFTC_T *ar, WMI_ADDBA_RESP_EVENT *evt)
+{
+ A_PRINTF("ADDBA RESP. tid %d status %d, sz %d\n", evt->tid, evt->status, evt->amsdu_sz);
+ if(evt->status == 0) {
+ }
+}
+
+void
+ar6000_aggr_rcv_delba_req_evt(AR_SOFTC_T *ar, WMI_DELBA_EVENT *evt)
+{
+ aggr_recv_delba_req_evt(ar->aggr_cntxt, evt->tid);
+}
+#endif
+
+void
+ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd)
+{
+ void *osbuf = NULL;
+ A_INT8 i;
+ A_UINT8 size, *buf;
+ A_STATUS ret = A_OK;
+
+ size = cmd->evt_buf_sz + 4;
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ ret = A_NO_MEMORY;
+ A_PRINTF("Error in allocating netbuf \n");
+ return;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+ buf = (A_UINT8 *)A_NETBUF_DATA(osbuf);
+ /* First 2-bytes carry HCI event/ACL data type
+ * the next 2 are free
+ */
+ *((short *)buf) = WMI_HCI_EVENT_EVENTID;
+ buf += sizeof(int);
+ A_MEMCPY(buf, cmd->buf, cmd->evt_buf_sz);
+
+ ar6000_deliver_frames_to_nw_stack(ar->arNetDev, osbuf);
+ if(loghci) {
+ A_PRINTF_LOG("HCI Event From PAL <-- \n");
+ for(i = 0; i < cmd->evt_buf_sz; i++) {
+ A_PRINTF_LOG("0x%02x ", cmd->buf[i]);
+ if((i % 10) == 0) {
+ A_PRINTF_LOG("\n");
+ }
+ }
+ A_PRINTF_LOG("\n");
+ A_PRINTF_LOG("==================================\n");
+ }
+}
+
+void
+ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
+{
+#if WIRELESS_EXT >= 18
+ struct iw_pmkid_cand *pmkcand;
+#else /* WIRELESS_EXT >= 18 */
+ static const char *tag = "PRE-AUTH";
+ char buf[128];
+#endif /* WIRELESS_EXT >= 18 */
+
+ union iwreq_data wrqu;
+ int i;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("AR6000 Neighbor Report Event\n"));
+ for (i=0; i < numAps; info++, i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+ info->bssid[0], info->bssid[1], info->bssid[2],
+ info->bssid[3], info->bssid[4], info->bssid[5]));
+ if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("preauth-cap"));
+ }
+ if (info->bssFlags & WMI_PMKID_VALID_BSS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,(" pmkid-valid\n"));
+ continue; /* we skip bss if the pmkid is already valid */
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("\n"));
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+#if WIRELESS_EXT >= 18
+ pmkcand = A_MALLOC_NOWAIT(sizeof(struct iw_pmkid_cand));
+ A_MEMZERO(pmkcand, sizeof(struct iw_pmkid_cand));
+ pmkcand->index = i;
+ pmkcand->flags = info->bssFlags;
+ A_MEMCPY(pmkcand->bssid.sa_data, info->bssid, ATH_MAC_LEN);
+ wrqu.data.length = sizeof(struct iw_pmkid_cand);
+ wireless_send_event(ar->arNetDev, IWEVPMKIDCAND, &wrqu, (char *)pmkcand);
+ A_FREE(pmkcand);
+#else /* WIRELESS_EXT >= 18 */
+ snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
+ tag,
+ info->bssid[0], info->bssid[1], info->bssid[2],
+ info->bssid[3], info->bssid[4], info->bssid[5],
+ i, info->bssFlags);
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+#endif /* WIRELESS_EXT >= 18 */
+ }
+}
+
+void
+ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+ static const char *tag = "MLME-MICHAELMICFAILURE.indication";
+ char buf[128];
+ union iwreq_data wrqu;
+
+ /*
+ * For AP case, keyid will have aid of STA which sent pkt with
+ * MIC error. Use this aid to get MAC & send it to hostapd.
+ */
+ if (ar->arNetworkType == AP_NETWORK) {
+ sta_t *s = ieee80211_find_conn_for_aid(ar, (keyid >> 2));
+ if(!s){
+ A_PRINTF("AP TKIP MIC error received from Invalid aid / STA not found =%d\n", keyid);
+ return;
+ }
+ A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid);
+ snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
+ tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]);
+ } else {
+
+#ifdef ATH6K_CONFIG_CFG80211
+ ar6k_cfg80211_tkip_micerr_event(ar, keyid, ismcast);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+ A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
+ keyid & 0x3, ismcast ? "multi": "uni");
+ snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid & 0x3,
+ ismcast ? "mult" : "un");
+ }
+
+ memset(&wrqu, 0, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+void
+ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+
+#ifdef ATH6K_CONFIG_CFG80211
+ ar6k_cfg80211_scanComplete_event(ar, status);
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+ if (!ar->arUserBssFilter) {
+ wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+ }
+ if (!ar->scan_complete) {
+ if (status==A_OK) {
+ union iwreq_data wrqu;
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wireless_send_event(ar->arNetDev, SIOCGIWSCAN, &wrqu, NULL);
+ ar->scan_complete = 1;
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,( "AR6000 scan complete: %d\n", status));
+}
+
+void
+ar6000_targetStats_event(AR_SOFTC_T *ar, A_UINT8 *ptr, A_UINT32 len)
+{
+ A_UINT8 ac;
+
+ if(ar->arNetworkType == AP_NETWORK) {
+ WMI_AP_MODE_STAT *p = (WMI_AP_MODE_STAT *)ptr;
+ WMI_AP_MODE_STAT *ap = &ar->arAPStats;
+
+ if (len < sizeof(*p)) {
+ return;
+ }
+
+ for(ac=0;ac<AP_MAX_NUM_STA;ac++) {
+ ap->sta[ac].tx_bytes += p->sta[ac].tx_bytes;
+ ap->sta[ac].tx_pkts += p->sta[ac].tx_pkts;
+ ap->sta[ac].tx_error += p->sta[ac].tx_error;
+ ap->sta[ac].tx_discard += p->sta[ac].tx_discard;
+ ap->sta[ac].rx_bytes += p->sta[ac].rx_bytes;
+ ap->sta[ac].rx_pkts += p->sta[ac].rx_pkts;
+ ap->sta[ac].rx_error += p->sta[ac].rx_error;
+ ap->sta[ac].rx_discard += p->sta[ac].rx_discard;
+ }
+
+ } else {
+ WMI_TARGET_STATS *pTarget = (WMI_TARGET_STATS *)ptr;
+ TARGET_STATS *pStats = &ar->arTargetStats;
+
+ if (len < sizeof(*pTarget)) {
+ return;
+ }
+
+ // Update the RSSI of the connected bss.
+ if (ar->arConnected) {
+ bss_t *pConnBss = NULL;
+
+ pConnBss = wmi_find_node(ar->arWmi,ar->arBssid);
+ if (pConnBss)
+ {
+ pConnBss->ni_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
+ pConnBss->ni_snr = pTarget->cservStats.cs_aveBeacon_snr;
+ wmi_node_return(ar->arWmi, pConnBss);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 updating target stats\n"));
+ pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets;
+ pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes;
+ pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
+ pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
+ pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
+ pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
+ pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
+ pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
+ pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
+ for(ac = 0; ac < WMM_NUM_AC; ac++)
+ pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
+ pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors;
+ pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt;
+ pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt;
+ pStats->tx_mult_retry_cnt += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt;
+ pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
+ pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate);
+
+ pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets;
+ pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes;
+ pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
+ pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
+ pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
+ pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
+ pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
+ pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
+ pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
+ pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors;
+ pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr;
+ pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
+ pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err;
+ pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
+ pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate);
+
+
+ pStats->tkip_local_mic_failure
+ += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
+ pStats->tkip_counter_measures_invoked
+ += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
+ pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
+ pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
+ pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
+ pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
+
+ pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
+ pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
+
+ pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt;
+ pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt;
+ pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt;
+ pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt;
+ pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr;
+ pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
+
+ if (enablerssicompensation) {
+ pStats->cs_aveBeacon_rssi =
+ rssi_compensation_calc(ar, pStats->cs_aveBeacon_rssi);
+ }
+ pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec;
+ pStats->cs_snr = pTarget->cservStats.cs_snr;
+ pStats->cs_rssi = pTarget->cservStats.cs_rssi;
+
+ pStats->lq_val = pTarget->lqVal;
+
+ pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped;
+ pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups;
+ pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups;
+ pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded;
+ pStats->arp_received += pTarget->arpStats.arp_received;
+ pStats->arp_matched += pTarget->arpStats.arp_matched;
+ pStats->arp_replied += pTarget->arpStats.arp_replied;
+
+ if (ar->statsUpdatePending) {
+ ar->statsUpdatePending = FALSE;
+ wake_up(&arEvent);
+ }
+ }
+}
+
+void
+ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi)
+{
+ USER_RSSI_THOLD userRssiThold;
+
+ rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR;
+
+ if (enablerssicompensation) {
+ rssi = rssi_compensation_calc(ar, rssi);
+ }
+
+ /* Send an event to the app */
+ userRssiThold.tag = ar->rssi_map[newThreshold].tag;
+ userRssiThold.rssi = rssi;
+ A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold,
+ userRssiThold.tag, userRssiThold.rssi);
+
+ ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
+}
+
+
+void
+ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source)
+{
+ if (source == APP_HB_CHALLENGE) {
+ /* Report it to the app in case it wants a positive acknowledgement */
+ ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
+ (A_UINT8 *)&cookie, sizeof(cookie));
+ } else {
+ /* This would ignore the replys that come in after their due time */
+ if (cookie == ar->arHBChallengeResp.seqNum) {
+ ar->arHBChallengeResp.outstanding = FALSE;
+ }
+ }
+}
+
+
+void
+ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
+{
+ char *errString[] = {
+ [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL",
+ [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND",
+ [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
+ [WMI_TARGET_BMISS] "WMI_TARGET_BMISS",
+ [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN"
+ };
+
+ A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
+
+ /* One error is reported at a time, and errorval is a bitmask */
+ if(errorVal & (errorVal - 1))
+ return;
+
+ A_PRINTF("AR6000 Error type = ");
+ switch(errorVal)
+ {
+ case WMI_TARGET_PM_ERR_FAIL:
+ case WMI_TARGET_KEY_NOT_FOUND:
+ case WMI_TARGET_DECRYPTION_ERR:
+ case WMI_TARGET_BMISS:
+ case WMI_PSDISABLE_NODE_JOIN:
+ A_PRINTF("%s\n", errString[errorVal]);
+ break;
+ default:
+ A_PRINTF("INVALID\n");
+ break;
+ }
+
+}
+
+
+void
+ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
+ A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
+{
+ WMM_TSPEC_IE *tspecIe;
+
+ /*
+ * This is the TSPEC IE suggestion from AP.
+ * Suggestion provided by AP under some error
+ * cases, could be helpful for the host app.
+ * Check documentation.
+ */
+ tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
+
+ /*
+ * What do we do, if we get TSPEC rejection? One thought
+ * that comes to mind is implictly delete the pstream...
+ */
+ A_PRINTF("AR6000 CAC notification. "
+ "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
+ ac, cacIndication, statusCode);
+}
+
+void
+ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel,
+ A_UINT16 newChannel)
+{
+ A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n",
+ oldChannel, newChannel);
+}
+
+#define AR6000_PRINT_BSSID(_pBss) do { \
+ A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
+ (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
+ (_pBss)[4],(_pBss)[5]); \
+} while(0)
+
+void
+ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
+{
+ A_UINT8 i;
+
+ A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
+ pTbl->numEntries, pTbl->roamMode);
+ for (i= 0; i < pTbl->numEntries; i++) {
+ A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
+ pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
+ pTbl->bssRoamInfo[i].bssid[2],
+ pTbl->bssRoamInfo[i].bssid[3],
+ pTbl->bssRoamInfo[i].bssid[4],
+ pTbl->bssRoamInfo[i].bssid[5]);
+ A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
+ " BIAS %d\n",
+ pTbl->bssRoamInfo[i].rssi,
+ pTbl->bssRoamInfo[i].rssidt,
+ pTbl->bssRoamInfo[i].last_rssi,
+ pTbl->bssRoamInfo[i].util,
+ pTbl->bssRoamInfo[i].roam_util,
+ pTbl->bssRoamInfo[i].bias);
+ }
+}
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply)
+{
+ A_UINT8 i,j;
+
+ /*Each event now contains exactly one filter, see bug 26613*/
+ A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters);
+ A_PRINTF("wow mode = %s host mode = %s\n",
+ (wow_reply->wow_mode == 0? "disabled":"enabled"),
+ (wow_reply->host_mode == 1 ? "awake":"asleep"));
+
+
+ /*If there are no patterns, the reply will only contain generic
+ WoW information. Pattern information will exist only if there are
+ patterns present. Bug 26716*/
+
+ /* If this event contains pattern information, display it*/
+ if (wow_reply->this_filter_num) {
+ i=0;
+ A_PRINTF("id=%d size=%d offset=%d\n",
+ wow_reply->wow_filters[i].wow_filter_id,
+ wow_reply->wow_filters[i].wow_filter_size,
+ wow_reply->wow_filters[i].wow_filter_offset);
+ A_PRINTF("wow pattern = ");
+ for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+ A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]);
+ }
+
+ A_PRINTF("\nwow mask = ");
+ for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+ A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]);
+ }
+ A_PRINTF("\n");
+ }
+}
+
+/*
+ * Report the Roaming related data collected on the target
+ */
+void
+ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
+{
+ A_PRINTF("Disconnect Data : BSSID: ");
+ AR6000_PRINT_BSSID(p->disassoc_bssid);
+ A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
+ p->disassoc_bss_rssi,p->disassoc_time,
+ p->no_txrx_time);
+ A_PRINTF("Connect Data: BSSID: ");
+ AR6000_PRINT_BSSID(p->assoc_bssid);
+ A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
+ p->assoc_bss_rssi,p->assoc_time,
+ p->allow_txrx_time);
+}
+
+void
+ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
+{
+ switch (p->roamDataType) {
+ case ROAM_DATA_TIME:
+ ar6000_display_roam_time(&p->u.roamTime);
+ break;
+ default:
+ break;
+ }
+}
+
+void
+ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len)
+{
+ struct sk_buff *skb;
+ WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap;
+
+
+ if (!ar->arMgmtFilter) {
+ return;
+ }
+ if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) &&
+ (bih->frameType != BEACON_FTYPE)) ||
+ ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) &&
+ (bih->frameType != PROBERESP_FTYPE)))
+ {
+ return;
+ }
+
+ if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) {
+
+ A_NETBUF_PUT(skb, len);
+ A_MEMCPY(A_NETBUF_DATA(skb), datap, len);
+ skb->dev = ar->arNetDev;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6);
+#else
+ skb->mac.raw = A_NETBUF_DATA(skb);
+#endif
+ skb->ip_summed = CHECKSUM_NONE;
+ skb->pkt_type = PACKET_OTHERHOST;
+ skb->protocol = __constant_htons(0x0019);
+ netif_rx(skb);
+ }
+}
+
+A_UINT32 wmiSendCmdNum;
+
+A_STATUS
+ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ A_STATUS status = A_OK;
+ struct ar_cookie *cookie = NULL;
+ int i;
+#ifdef CONFIG_PM
+ if (ar->arWowState) {
+ A_NETBUF_FREE(osbuf);
+ return A_EACCES;
+ }
+#endif /* CONFIG_PM */
+ /* take lock to protect ar6000_alloc_cookie() */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ do {
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n",
+ (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid));
+
+ if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) {
+ /* control endpoint is full, don't allocate resources, we
+ * are just going to drop this packet */
+ cookie = NULL;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" WMI Control EP full, dropping packet : 0x%X, len:%d \n",
+ (A_UINT32)osbuf, A_NETBUF_LEN(osbuf)));
+ } else {
+ cookie = ar6000_alloc_cookie(ar);
+ }
+
+ if (cookie == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ if(logWmiRawMsgs) {
+ A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum);
+ for(i = 0; i < a_netbuf_to_len(osbuf); i++)
+ A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]);
+ A_PRINTF("\n");
+ }
+
+ wmiSendCmdNum++;
+
+ } while (FALSE);
+
+ if (cookie != NULL) {
+ /* got a structure to send it out on */
+ ar->arTxPending[eid]++;
+
+ if (eid != ar->arControlEp) {
+ ar->arTotalTxDataPending++;
+ }
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (cookie != NULL) {
+ cookie->arc_bp[0] = (A_UINT32)osbuf;
+ cookie->arc_bp[1] = 0;
+ SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+ cookie,
+ A_NETBUF_DATA(osbuf),
+ A_NETBUF_LEN(osbuf),
+ eid,
+ AR6K_CONTROL_PKT_TAG);
+ /* this interface is asynchronous, if there is an error, cleanup will happen in the
+ * TX completion callback */
+ HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+ status = A_OK;
+ }
+
+ if (status != A_OK) {
+ A_NETBUF_FREE(osbuf);
+ }
+ return status;
+}
+
+/* indicate tx activity or inactivity on a WMI stream */
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ HTC_ENDPOINT_ID eid ;
+ int i;
+
+ if (ar->arWmiEnabled) {
+ eid = arAc2EndpointID(ar, TrafficClass);
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ ar->arAcStreamActive[TrafficClass] = Active;
+
+ if (Active) {
+ /* when a stream goes active, keep track of the active stream with the highest priority */
+
+ if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) {
+ /* set the new highest active priority */
+ ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass];
+ }
+
+ } else {
+ /* when a stream goes inactive, we may have to search for the next active stream
+ * that is the highest priority */
+
+ if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) {
+
+ /* the highest priority stream just went inactive */
+
+ /* reset and search for the "next" highest "active" priority stream */
+ ar->arHiAcStreamActivePri = 0;
+ for (i = 0; i < WMM_NUM_AC; i++) {
+ if (ar->arAcStreamActive[i]) {
+ if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) {
+ /* set the new highest active priority */
+ ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i];
+ }
+ }
+ }
+ }
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ } else {
+ /* for mbox ping testing, the traffic class is mapped directly as a stream ID,
+ * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */
+ eid = (HTC_ENDPOINT_ID)TrafficClass;
+ }
+
+ /* notify HTC, this may cause credit distribution changes */
+
+ HTCIndicateActivityChange(ar->arHtcTarget,
+ eid,
+ Active);
+
+}
+
+void
+ar6000_btcoex_config_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len)
+{
+
+ WMI_BTCOEX_CONFIG_EVENT *pBtcoexConfig = (WMI_BTCOEX_CONFIG_EVENT *)ptr;
+ WMI_BTCOEX_CONFIG_EVENT *pArbtcoexConfig =&ar->arBtcoexConfig;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n"));
+
+ A_PRINTF("received config event\n");
+ pArbtcoexConfig->btProfileType = pBtcoexConfig->btProfileType;
+ pArbtcoexConfig->linkId = pBtcoexConfig->linkId;
+
+ switch (pBtcoexConfig->btProfileType) {
+ case WMI_BTCOEX_BT_PROFILE_SCO:
+ A_MEMCPY(&pArbtcoexConfig->info.scoConfigCmd, &pBtcoexConfig->info.scoConfigCmd,
+ sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD));
+ break;
+ case WMI_BTCOEX_BT_PROFILE_A2DP:
+ A_MEMCPY(&pArbtcoexConfig->info.a2dpConfigCmd, &pBtcoexConfig->info.a2dpConfigCmd,
+ sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD));
+ break;
+ case WMI_BTCOEX_BT_PROFILE_ACLCOEX:
+ A_MEMCPY(&pArbtcoexConfig->info.aclcoexConfig, &pBtcoexConfig->info.aclcoexConfig,
+ sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+ break;
+ case WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE:
+ A_MEMCPY(&pArbtcoexConfig->info.btinquiryPageConfigCmd, &pBtcoexConfig->info.btinquiryPageConfigCmd,
+ sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+ break;
+ }
+ if (ar->statsUpdatePending) {
+ ar->statsUpdatePending = FALSE;
+ wake_up(&arEvent);
+ }
+}
+
+void
+ar6000_btcoex_stats_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len)
+{
+ WMI_BTCOEX_STATS_EVENT *pBtcoexStats = (WMI_BTCOEX_STATS_EVENT *)ptr;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n"));
+
+ A_MEMCPY(&ar->arBtcoexStats, pBtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT));
+
+ if (ar->statsUpdatePending) {
+ ar->statsUpdatePending = FALSE;
+ wake_up(&arEvent);
+ }
+
+}
+module_init(ar6000_init_module);
+module_exit(ar6000_cleanup_module);
+
+/* Init cookie queue */
+static void
+ar6000_cookie_init(AR_SOFTC_T *ar)
+{
+ A_UINT32 i;
+
+ ar->arCookieList = NULL;
+ ar->arCookieCount = 0;
+
+ A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
+
+ for (i = 0; i < MAX_COOKIE_NUM; i++) {
+ ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
+ }
+}
+
+/* cleanup cookie queue */
+static void
+ar6000_cookie_cleanup(AR_SOFTC_T *ar)
+{
+ /* It is gone .... */
+ ar->arCookieList = NULL;
+ ar->arCookieCount = 0;
+}
+
+/* Init cookie queue */
+static void
+ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
+{
+ /* Insert first */
+ A_ASSERT(ar != NULL);
+ A_ASSERT(cookie != NULL);
+
+ cookie->arc_list_next = ar->arCookieList;
+ ar->arCookieList = cookie;
+ ar->arCookieCount++;
+}
+
+/* cleanup cookie queue */
+static struct ar_cookie *
+ar6000_alloc_cookie(AR_SOFTC_T *ar)
+{
+ struct ar_cookie *cookie;
+
+ cookie = ar->arCookieList;
+ if(cookie != NULL)
+ {
+ ar->arCookieList = cookie->arc_list_next;
+ ar->arCookieCount--;
+ }
+
+ return cookie;
+}
+
+#ifdef SEND_EVENT_TO_APP
+/*
+ * This function is used to send event which come from taget to
+ * the application. The buf which send to application is include
+ * the event ID and event content.
+ */
+#define EVENT_ID_LEN 2
+void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+ A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 15)
+
+/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
+
+ char *buf;
+ A_UINT16 size;
+ union iwreq_data wrqu;
+
+ size = len + EVENT_ID_LEN;
+
+ if (size > IW_CUSTOM_MAX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
+ eventId, size, IW_CUSTOM_MAX));
+ return;
+ }
+
+ buf = A_MALLOC_NOWAIT(size);
+ if (NULL == buf){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
+ return;
+ }
+
+ A_MEMZERO(buf, size);
+ A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+ A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+ //AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("event ID = %d,len = %d\n",*(A_UINT16*)buf, size));
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = size;
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+
+ A_FREE(buf);
+#endif
+
+
+}
+
+/*
+ * This function is used to send events larger than 256 bytes
+ * to the application. The buf which is sent to application
+ * includes the event ID and event content.
+ */
+void ar6000_send_generic_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+ A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 18)
+
+/* IWEVGENIE exists in wireless extensions version 18 onwards */
+
+ char *buf;
+ A_UINT16 size;
+ union iwreq_data wrqu;
+
+ size = len + EVENT_ID_LEN;
+
+ if (size > IW_GENERIC_IE_MAX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n",
+ eventId, size, IW_GENERIC_IE_MAX));
+ return;
+ }
+
+ buf = A_MALLOC_NOWAIT(size);
+ if (NULL == buf){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
+ return;
+ }
+
+ A_MEMZERO(buf, size);
+ A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+ A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = size;
+ wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf);
+
+ A_FREE(buf);
+
+#endif /* (WIRELESS_EXT >= 18) */
+
+}
+#endif /* SEND_EVENT_TO_APP */
+
+
+void
+ar6000_tx_retry_err_event(void *devt)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Tx retries reach maximum!\n"));
+}
+
+void
+ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr)
+{
+ WMI_SNR_THRESHOLD_EVENT event;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ event.range = newThreshold;
+ event.snr = snr;
+
+ ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event,
+ sizeof(WMI_SNR_THRESHOLD_EVENT));
+}
+
+void
+ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("lq threshold range %d, lq %d\n", newThreshold, lq));
+}
+
+
+
+A_UINT32
+a_copy_to_user(void *to, const void *from, A_UINT32 n)
+{
+ return(copy_to_user(to, from, n));
+}
+
+A_UINT32
+a_copy_from_user(void *to, const void *from, A_UINT32 n)
+{
+ return(copy_from_user(to, from, n));
+}
+
+
+A_STATUS
+ar6000_get_driver_cfg(struct net_device *dev,
+ A_UINT16 cfgParam,
+ void *result)
+{
+
+ A_STATUS ret = 0;
+
+ switch(cfgParam)
+ {
+ case AR6000_DRIVER_CFG_GET_WLANNODECACHING:
+ *((A_UINT32 *)result) = wlanNodeCaching;
+ break;
+ case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS:
+ *((A_UINT32 *)result) = logWmiRawMsgs;
+ break;
+ default:
+ ret = EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+void
+ar6000_keepalive_rx(void *devt, A_UINT8 configured)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arKeepaliveConfigured = configured;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList,
+ A_UINT8 *bssidList)
+{
+ A_UINT8 i, j;
+
+ A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID);
+
+ for (i = 0; i < numPMKID; i++) {
+ A_PRINTF("\nBSSID %d ", i);
+ for (j = 0; j < ATH_MAC_LEN; j++) {
+ A_PRINTF("%2.2x", bssidList[j]);
+ }
+ bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN);
+ A_PRINTF("\nPMKID %d ", i);
+ for (j = 0; j < WMI_PMKID_LEN; j++) {
+ A_PRINTF("%2.2x", pmkidList->pmkid[j]);
+ }
+ pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN +
+ WMI_PMKID_LEN);
+ }
+}
+
+void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid)
+{
+ sta_t *conn=NULL;
+ A_BOOL isPsqEmpty = FALSE;
+
+ conn = ieee80211_find_conn_for_aid(ar, aid);
+
+ /* If the PS q for this STA is not empty, dequeue and send a pkt from
+ * the head of the q. Also update the More data bit in the WMI_DATA_HDR
+ * if there are more pkts for this STA in the PS q. If there are no more
+ * pkts for this STA, update the PVB for this STA.
+ */
+ A_MUTEX_LOCK(&conn->psqLock);
+ isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+ A_MUTEX_UNLOCK(&conn->psqLock);
+
+ if (isPsqEmpty) {
+ /* TODO:No buffered pkts for this STA. Send out a NULL data frame */
+ } else {
+ struct sk_buff *skb = NULL;
+
+ A_MUTEX_LOCK(&conn->psqLock);
+ skb = A_NETBUF_DEQUEUE(&conn->psq);
+ A_MUTEX_UNLOCK(&conn->psqLock);
+ /* Set the STA flag to PSPolled, so that the frame will go out */
+ STA_SET_PS_POLLED(conn);
+ ar6000_data_tx(skb, ar->arNetDev);
+ STA_CLR_PS_POLLED(conn);
+
+ /* Clear the PVB for this STA if the queue has become empty */
+ A_MUTEX_LOCK(&conn->psqLock);
+ isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq);
+ A_MUTEX_UNLOCK(&conn->psqLock);
+
+ if (isPsqEmpty) {
+ wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0);
+ }
+ }
+}
+
+void ar6000_dtimexpiry_event(AR_SOFTC_T *ar)
+{
+ A_BOOL isMcastQueued = FALSE;
+ struct sk_buff *skb = NULL;
+
+ /* If there are no associated STAs, ignore the DTIM expiry event.
+ * There can be potential race conditions where the last associated
+ * STA may disconnect & before the host could clear the 'Indicate DTIM'
+ * request to the firmware, the firmware would have just indicated a DTIM
+ * expiry event. The race is between 'clear DTIM expiry cmd' going
+ * from the host to the firmware & the DTIM expiry event happening from
+ * the firmware to the host.
+ */
+ if (ar->sta_list_index == 0) {
+ return;
+ }
+
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq);
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+ A_ASSERT(isMcastQueued == FALSE);
+
+ /* Flush the mcast psq to the target */
+ /* Set the STA flag to DTIMExpired, so that the frame will go out */
+ ar->DTIMExpired = TRUE;
+
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+ skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+ ar6000_data_tx(skb, ar->arNetDev);
+
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ }
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+
+ /* Reset the DTIMExpired flag back to 0 */
+ ar->DTIMExpired = FALSE;
+
+ /* Clear the LSB of the BitMapCtl field of the TIM IE */
+ wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0);
+}
+
+void
+read_rssi_compensation_param(AR_SOFTC_T *ar)
+{
+ HIF_DEVICE *device= ar->arHifDevice;
+ A_UINT32 rssicomp;
+ A_UINT32 param;
+
+ if (BMIReadMemory(device,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data),
+ (A_UCHAR *)&rssicomp,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n"));
+ return;
+ }
+
+ rssicomp += 0x40;
+ if (BMIReadSOCRegister(device, rssicomp, &param)!= A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+ return ;
+ }
+ rssi_compensation_param.a_enable = (A_INT16) (param & 0xffff);
+ rssi_compensation_param.a_param_a = (A_INT16) (param >> 16);
+
+ rssicomp += 4;
+ if (BMIReadSOCRegister(device, rssicomp, &param)!= A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+ return ;
+ }
+ rssi_compensation_param.a_param_b = (A_INT16) (param & 0xffff);
+ rssi_compensation_param.bg_enable = (A_INT16) (param >> 16);
+
+ rssicomp += 4;
+ if (BMIReadSOCRegister(device, rssicomp, &param)!= A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
+ return ;
+ }
+ rssi_compensation_param.bg_param_a = (A_INT16) (param & 0xffff);
+ rssi_compensation_param.bg_param_b = (A_INT16) (param >> 16);
+
+ if (rssi_compensation_param.bg_enable != 0x1)
+ rssi_compensation_param.bg_enable = 0;
+
+ if (rssi_compensation_param.a_enable != 0x1)
+ rssi_compensation_param.a_enable = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("compensation flag = %d a = %d b = %d\n",\
+ rssi_compensation_param.bg_enable,
+ rssi_compensation_param.bg_param_a,
+ rssi_compensation_param.bg_param_b));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("compensation flag = %d a = %d b = %d\n",\
+ rssi_compensation_param.a_enable,
+ rssi_compensation_param.a_param_a,
+ rssi_compensation_param.a_param_b));
+
+ return ;
+}
+
+A_INT32
+rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt)
+{
+
+ if (freq > 5000)
+ {
+ if (rssi_compensation_param.a_enable)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d, totalPkt = %d\n", rssi,totalPkt));
+ rssi = rssi * rssi_compensation_param.a_param_a + totalPkt * rssi_compensation_param.a_param_b;
+ rssi = (rssi-50) /100;
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+ }
+ }
+ else
+ {
+ if (rssi_compensation_param.bg_enable)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d, totalPkt = %d\n", rssi,totalPkt));
+ rssi = rssi * rssi_compensation_param.bg_param_a + totalPkt * rssi_compensation_param.bg_param_b;
+ rssi = (rssi-50) /100;
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+ }
+ }
+
+ return rssi;
+}
+
+A_INT16
+rssi_compensation_calc(AR_SOFTC_T *ar, A_INT16 rssi)
+{
+ if (ar->arBssChannel > 5000)
+ {
+ if (rssi_compensation_param.a_enable)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d\n", rssi));
+ rssi = rssi * rssi_compensation_param.a_param_a + rssi_compensation_param.a_param_b;
+ rssi = (rssi-50) /100;
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+ }
+ }
+ else
+ {
+ if (rssi_compensation_param.bg_enable)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d\n", rssi));
+ rssi = rssi * rssi_compensation_param.bg_param_a + rssi_compensation_param.bg_param_b;
+ rssi = (rssi-50) /100;
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi));
+ }
+ }
+
+ return rssi;
+}
+
+A_INT16
+rssi_compensation_reverse_calc(AR_SOFTC_T *ar, A_INT16 rssi, A_BOOL Above)
+{
+ A_INT16 i;
+
+ if (ar->arBssChannel > 5000)
+ {
+ if (rssi_compensation_param.a_enable)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation = %d\n", rssi));
+ rssi = rssi * 100;
+ rssi = (rssi - rssi_compensation_param.a_param_b) / rssi_compensation_param.a_param_a;
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi));
+ }
+ }
+ else
+ {
+ if (rssi_compensation_param.bg_enable)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n"));
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation = %d\n", rssi));
+
+ if (Above) {
+ for (i=95; i>=0; i--) {
+ if (rssi <= rssi_compensation_table[i]) {
+ rssi = 0 - i;
+ break;
+ }
+ }
+ } else {
+ for (i=0; i<=95; i++) {
+ if (rssi >= rssi_compensation_table[i]) {
+ rssi = 0 - i;
+ break;
+ }
+ }
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi));
+ }
+ }
+
+ return rssi;
+}
+
+#ifdef WAPI_ENABLE
+void ap_wapi_rekey_event(AR_SOFTC_T *ar, A_UINT8 type, A_UINT8 *mac)
+{
+ union iwreq_data wrqu;
+ A_CHAR buf[20];
+
+ A_MEMZERO(buf, sizeof(buf));
+
+ strcpy(buf, "WAPI_REKEY");
+ buf[10] = type;
+ A_MEMCPY(&buf[11], mac, ATH_MAC_LEN);
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = 10+1+ATH_MAC_LEN;
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+
+ A_PRINTF("WAPI REKEY - %d - %02x:%02x\n", type, mac[4], mac[5]);
+}
+#endif
+
+#ifdef USER_KEYS
+static A_STATUS
+
+ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl)
+{
+ A_STATUS status = A_OK;
+ struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik;
+ struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik;
+ CRYPTO_TYPE keyType = ar->user_saved_keys.keyType;
+
+ if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) {
+ if (NONE_CRYPT == keyType) {
+ goto _reinstall_keys_out;
+ }
+
+ if (uik->ik_keylen) {
+ status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix,
+ ar->user_saved_keys.keyType, PAIRWISE_USAGE,
+ uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc,
+ uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG);
+ }
+
+ } else {
+ status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata);
+ }
+
+ if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) {
+ if (NONE_CRYPT == keyType) {
+ goto _reinstall_keys_out;
+ }
+
+ if (bik->ik_keylen) {
+ status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix,
+ ar->user_saved_keys.keyType, GROUP_USAGE,
+ bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc,
+ bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG);
+ }
+ } else {
+ status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata);
+ }
+
+_reinstall_keys_out:
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+ ar->user_key_ctrl = 0;
+
+ return status;
+}
+#endif /* USER_KEYS */
+
+
+void
+ar6000_dset_open_req(
+ void *context,
+ A_UINT32 id,
+ A_UINT32 targHandle,
+ A_UINT32 targReplyFn,
+ A_UINT32 targReplyArg)
+{
+}
+
+void
+ar6000_dset_close(
+ void *context,
+ A_UINT32 access_cookie)
+{
+ return;
+}
+
+void
+ar6000_dset_data_req(
+ void *context,
+ A_UINT32 accessCookie,
+ A_UINT32 offset,
+ A_UINT32 length,
+ A_UINT32 targBuf,
+ A_UINT32 targReplyFn,
+ A_UINT32 targReplyArg)
+{
+}
+
+int
+ar6000_ap_mode_profile_commit(struct ar6_softc *ar)
+{
+ WMI_CONNECT_CMD p;
+ unsigned long flags;
+
+ /* No change in AP's profile configuration */
+ if(ar->ap_profile_flag==0) {
+ A_PRINTF("COMMIT: No change in profile!!!\n");
+ return -ENODATA;
+ }
+
+ if(!ar->arSsidLen) {
+ A_PRINTF("SSID not set!!!\n");
+ return -ECHRNG;
+ }
+
+ switch(ar->arAuthMode) {
+ case NONE_AUTH:
+ if((ar->arPairwiseCrypto != NONE_CRYPT) &&
+#ifdef WAPI_ENABLE
+ (ar->arPairwiseCrypto != WAPI_CRYPT) &&
+#endif
+ (ar->arPairwiseCrypto != WEP_CRYPT)) {
+ A_PRINTF("Cipher not supported in AP mode Open auth\n");
+ return -EOPNOTSUPP;
+ }
+ break;
+ case WPA_PSK_AUTH:
+ case WPA2_PSK_AUTH:
+ case (WPA_PSK_AUTH|WPA2_PSK_AUTH):
+ break;
+ default:
+ A_PRINTF("This key mgmt type not supported in AP mode\n");
+ return -EOPNOTSUPP;
+ }
+
+ /* Update the arNetworkType */
+ ar->arNetworkType = ar->arNextMode;
+
+ A_MEMZERO(&p,sizeof(p));
+ p.ssidLength = ar->arSsidLen;
+ A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength);
+ p.channel = ar->arChannelHint;
+ p.networkType = ar->arNetworkType;
+
+ p.dot11AuthMode = ar->arDot11AuthMode;
+ p.authMode = ar->arAuthMode;
+ p.pairwiseCryptoType = ar->arPairwiseCrypto;
+ p.pairwiseCryptoLen = ar->arPairwiseCryptoLen;
+ p.groupCryptoType = ar->arGroupCrypto;
+ p.groupCryptoLen = ar->arGroupCryptoLen;
+ p.ctrl_flags = ar->arConnectCtrlFlags;
+
+ ar->arConnected = FALSE;
+
+ wmi_ap_profile_commit(ar->arWmi, &p);
+ spin_lock_irqsave(&ar->arLock, flags);
+ ar->arConnected = TRUE;
+ netif_carrier_on(ar->arNetDev);
+ spin_unlock_irqrestore(&ar->arLock, flags);
+ ar->ap_profile_flag = 0;
+ return 0;
+}
+
+
+A_STATUS
+ar6000_connect_to_ap(struct ar6_softc *ar)
+{
+ /* The ssid length check prevents second "essid off" from the user,
+ to be treated as a connect cmd. The second "essid off" is ignored.
+ */
+ if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) && ar->arNetworkType!=AP_NETWORK)
+ {
+ A_STATUS status;
+ if((ADHOC_NETWORK != ar->arNetworkType) &&
+ (NONE_AUTH==ar->arAuthMode) &&
+ (WEP_CRYPT==ar->arPairwiseCrypto)) {
+ ar6000_install_static_wep_keys(ar);
+ }
+
+ if (!ar->arUserBssFilter) {
+ if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+ return -EIO;
+ }
+ }
+#ifdef WAPI_ENABLE
+ if (ar->arWapiEnable) {
+ ar->arPairwiseCrypto = WAPI_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = WAPI_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ ar->arAuthMode = NONE_AUTH;
+ ar->arConnectCtrlFlags |= CONNECT_IGNORE_WPAx_GROUP_CIPHER;
+ }
+#endif
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Connect called with authmode %d dot11 auth %d"\
+ " PW crypto %d PW crypto Len %d GRP crypto %d"\
+ " GRP crypto Len %d\n",
+ ar->arAuthMode, ar->arDot11AuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto, ar->arGroupCryptoLen));
+ reconnect_flag = 0;
+ /* Set the listen interval into 1000TUs. This value will be indicated to Ap in the conn.
+ later set it back locally at the STA to 100/1000 TUs depending on the power mode */
+ if ((ar->arNetworkType == INFRA_NETWORK)) {
+ wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0);
+ }
+ status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+ ar->arDot11AuthMode, ar->arAuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto,ar->arGroupCryptoLen,
+ ar->arSsidLen, ar->arSsid,
+ ar->arReqBssid, ar->arChannelHint,
+ ar->arConnectCtrlFlags);
+ if (status != A_OK) {
+ wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0);
+ if (!ar->arUserBssFilter) {
+ wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
+ }
+ return status;
+ }
+
+ if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) &&
+ ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)))
+ {
+ A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0);
+ }
+
+ ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD;
+
+ ar->arConnectPending = TRUE;
+ return status;
+ }
+ return A_ERROR;
+}
+
+A_STATUS
+ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state)
+{
+ A_STATUS status = A_OK;
+ AR6000_WLAN_STATE oldstate = ar->arWlanState;
+ if (ar->arWmiReady == FALSE ||
+ (state!=WLAN_DISABLED && state!=WLAN_ENABLED)) {
+ return A_ERROR;
+ }
+ if (state == ar->arWlanState) {
+ return A_OK;
+ }
+ ar->arWlanState = state;
+ do {
+ if (ar->arWlanState == WLAN_ENABLED) {
+ /* Enable foreground scanning */
+ if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period,
+ ar->scParams.fg_end_period,
+ ar->scParams.bg_period,
+ ar->scParams.minact_chdwell_time,
+ ar->scParams.maxact_chdwell_time,
+ ar->scParams.pas_chdwell_time,
+ ar->scParams.shortScanRatio,
+ ar->scParams.scanCtrlFlags,
+ ar->scParams.max_dfsch_act_time,
+ ar->scParams.maxact_scan_per_ssid) != A_OK) {
+ status = A_ERROR;
+ break;
+ }
+ if (ar->arSsidLen) {
+ if (ar6000_connect_to_ap(ar) != A_OK) {
+ status = A_ERROR;
+ break;
+ }
+ }
+ } else {
+ /* Disconnect from the AP and disable foreground scanning */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ wmi_disconnect_cmd(ar->arWmi);
+ } else {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+
+ if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0) != A_OK) {
+ status = A_ERROR;
+ break;
+ }
+ }
+ } while (0);
+ if (status!=A_OK) {
+ ar->arWlanState = oldstate;
+ }
+ return status;
+}
+
+A_STATUS
+ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie)
+{
+ sta_t *conn = NULL;
+ conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr);
+
+ A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE);
+ A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE);
+
+ if(conn) {
+ A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE);
+ }
+
+ return 0;
+}
+
+A_STATUS
+is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd)
+{
+ if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) {
+ cmd -= SIOCSIWCOMMIT;
+ if(sioctl_filter[cmd] == 0xFF) return A_OK;
+ if(sioctl_filter[cmd] & mode) return A_OK;
+ } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) {
+ cmd -= SIOCIWFIRSTPRIV;
+ if(pioctl_filter[cmd] == 0xFF) return A_OK;
+ if(pioctl_filter[cmd] & mode) return A_OK;
+ } else {
+ return A_ERROR;
+ }
+ return A_ENOTSUP;
+}
+
+A_STATUS
+is_xioctl_allowed(A_UINT8 mode, int cmd)
+{
+ if(sizeof(xioctl_filter)-1 < cmd) {
+ A_PRINTF("Filter for this cmd=%d not defined\n",cmd);
+ return 0;
+ }
+ if(xioctl_filter[cmd] == 0xFF) return A_OK;
+ if(xioctl_filter[cmd] & mode) return A_OK;
+ return A_ERROR;
+}
+
+#ifdef WAPI_ENABLE
+int
+ap_set_wapi_key(struct ar6_softc *ar, void *ikey)
+{
+ struct ieee80211req_key *ik = (struct ieee80211req_key *)ikey;
+ KEY_USAGE keyUsage = 0;
+ A_STATUS status;
+
+ if (A_MEMCMP(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN) == 0) {
+ keyUsage = GROUP_USAGE;
+ } else {
+ keyUsage = PAIRWISE_USAGE;
+ }
+ A_PRINTF("WAPI_KEY: Type:%d ix:%d mac:%02x:%02x len:%d\n",
+ keyUsage, ik->ik_keyix, ik->ik_macaddr[4], ik->ik_macaddr[5],
+ ik->ik_keylen);
+
+ status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, WAPI_CRYPT, keyUsage,
+ ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+ ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+ SYNC_BOTH_WMIFLAG);
+
+ if (A_OK != status) {
+ return -EIO;
+ }
+ return 0;
+}
+#endif
+
+void ar6000_peer_event(
+ void *context,
+ A_UINT8 eventCode,
+ A_UINT8 *macAddr)
+{
+ A_UINT8 pos;
+
+ for (pos=0;pos<6;pos++)
+ printk("%02x: ",*(macAddr+pos));
+ printk("\n");
+}
+
+#ifdef HTC_TEST_SEND_PKTS
+#define HTC_TEST_DUPLICATE 8
+static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *dupskb)
+{
+ struct ar_cookie *cookie;
+ struct ar_cookie *cookieArray[HTC_TEST_DUPLICATE];
+ struct sk_buff *new_skb;
+ int i;
+ int pkts = 0;
+ HTC_PACKET_QUEUE pktQueue;
+ EPPING_HEADER *eppingHdr;
+
+ eppingHdr = A_NETBUF_DATA(dupskb);
+
+ if (eppingHdr->Cmd_h == EPPING_CMD_NO_ECHO) {
+ /* skip test if this is already a tx perf test */
+ return;
+ }
+
+ for (i = 0; i < HTC_TEST_DUPLICATE; i++,pkts++) {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ cookie = ar6000_alloc_cookie(ar);
+ if (cookie != NULL) {
+ ar->arTxPending[eid]++;
+ ar->arTotalTxDataPending++;
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (NULL == cookie) {
+ break;
+ }
+
+ new_skb = A_NETBUF_ALLOC(A_NETBUF_LEN(dupskb));
+
+ if (new_skb == NULL) {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar6000_free_cookie(ar,cookie);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ break;
+ }
+
+ A_NETBUF_PUT_DATA(new_skb, A_NETBUF_DATA(dupskb), A_NETBUF_LEN(dupskb));
+ cookie->arc_bp[0] = (A_UINT32)new_skb;
+ cookie->arc_bp[1] = MapNo;
+ SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+ cookie,
+ A_NETBUF_DATA(new_skb),
+ A_NETBUF_LEN(new_skb),
+ eid,
+ AR6K_DATA_PKT_TAG);
+
+ cookieArray[i] = cookie;
+
+ {
+ EPPING_HEADER *pHdr = (EPPING_HEADER *)A_NETBUF_DATA(new_skb);
+ pHdr->Cmd_h = EPPING_CMD_NO_ECHO; /* do not echo the packet */
+ }
+ }
+
+ if (pkts == 0) {
+ return;
+ }
+
+ INIT_HTC_PACKET_QUEUE(&pktQueue);
+
+ for (i = 0; i < pkts; i++) {
+ HTC_PACKET_ENQUEUE(&pktQueue,&cookieArray[i]->HtcPkt);
+ }
+
+ HTCSendPktsMultiple(ar->arHtcTarget, &pktQueue);
+
+}
+
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+EXPORT_SYMBOL(setupbtdev);
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c
new file mode 100644
index 000000000000..62f5f2158c18
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c
@@ -0,0 +1,455 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#include "ar6000_drv.h"
+
+#ifdef HTC_RAW_INTERFACE
+
+static void
+ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ raw_htc_buffer *busy;
+ HTC_RAW_STREAM_ID streamID;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+ busy = (raw_htc_buffer *)pPacket->pPktContext;
+ A_ASSERT(busy != NULL);
+
+ if (pPacket->Status == A_ECANCELED) {
+ /*
+ * HTC provides A_ECANCELED status when it doesn't want to be refilled
+ * (probably due to a shutdown)
+ */
+ return;
+ }
+
+ streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+ A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+
+#ifdef CF
+ if (down_trylock(&arRaw->raw_htc_read_sem[streamID])) {
+#else
+ if (down_interruptible(&arRaw->raw_htc_read_sem[streamID])) {
+#endif /* CF */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n"));
+ }
+
+ A_ASSERT((pPacket->Status != A_OK) ||
+ (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN)));
+
+ busy->length = pPacket->ActualLength + HTC_HEADER_LEN;
+ busy->currPtr = HTC_HEADER_LEN;
+ arRaw->read_buffer_available[streamID] = TRUE;
+ //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("raw read cb: 0x%X 0x%X \n", busy->currPtr,busy->length);
+ up(&arRaw->raw_htc_read_sem[streamID]);
+
+ /* Signal the waiting process */
+ AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) read process\n", streamID));
+ wake_up_interruptible(&arRaw->raw_htc_read_queue[streamID]);
+}
+
+static void
+ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ raw_htc_buffer *free;
+ HTC_RAW_STREAM_ID streamID;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+ free = (raw_htc_buffer *)pPacket->pPktContext;
+ A_ASSERT(free != NULL);
+
+ if (pPacket->Status == A_ECANCELED) {
+ /*
+ * HTC provides A_ECANCELED status when it doesn't want to be refilled
+ * (probably due to a shutdown)
+ */
+ return;
+ }
+
+ streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+ A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+
+#ifdef CF
+ if (down_trylock(&arRaw->raw_htc_write_sem[streamID])) {
+#else
+ if (down_interruptible(&arRaw->raw_htc_write_sem[streamID])) {
+#endif
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n"));
+ }
+
+ A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN));
+
+ free->length = 0;
+ arRaw->write_buffer_available[streamID] = TRUE;
+ up(&arRaw->raw_htc_write_sem[streamID]);
+
+ /* Signal the waiting process */
+ AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) write process\n", streamID));
+ wake_up_interruptible(&arRaw->raw_htc_write_queue[streamID]);
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar,
+ HTC_RAW_STREAM_ID StreamID)
+{
+ A_STATUS status;
+ HTC_SERVICE_CONNECT_RESP response;
+ A_UINT8 streamNo;
+ HTC_SERVICE_CONNECT_REQ connect;
+
+ do {
+
+ A_MEMZERO(&connect,sizeof(connect));
+ /* pass the stream ID as meta data to the RAW streams service */
+ streamNo = (A_UINT8)StreamID;
+ connect.pMetaData = &streamNo;
+ connect.MetaDataLength = sizeof(A_UINT8);
+ /* these fields are the same for all endpoints */
+ connect.EpCallbacks.pContext = ar;
+ connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb;
+ connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb;
+ /* simple interface, we don't need these optional callbacks */
+ connect.EpCallbacks.EpRecvRefill = NULL;
+ connect.EpCallbacks.EpSendFull = NULL;
+ connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM;
+
+ /* connect to the raw streams service, we may be able to get 1 or more
+ * connections, depending on WHAT is running on the target */
+ connect.ServiceID = HTC_RAW_STREAMS_SVC;
+
+ A_MEMZERO(&response,sizeof(response));
+
+ /* try to connect to the raw stream, it is okay if this fails with
+ * status HTC_SERVICE_NO_MORE_EP */
+ status = HTCConnectService(ar->arHtcTarget,
+ &connect,
+ &response);
+
+ if (A_FAILED(status)) {
+ if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTC RAW , No more streams allowed \n"));
+ status = A_OK;
+ }
+ break;
+ }
+
+ /* set endpoint mapping for the RAW HTC streams */
+ arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("HTC RAW : stream ID: %d, endpoint: %d\n",
+ StreamID, arRawStream2EndpointID(ar,StreamID)));
+
+ } while (FALSE);
+
+ return status;
+}
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar)
+{
+ A_STATUS status;
+ int streamID, endPt, count2;
+ raw_htc_buffer *buffer;
+ HTC_SERVICE_ID servicepriority;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+ if (!arRaw) {
+ arRaw = ar->arRawHtc = A_MALLOC(sizeof(AR_RAW_HTC_T));
+ if (arRaw) {
+ A_MEMZERO(arRaw, sizeof(AR_RAW_HTC_T));
+ }
+ }
+ A_ASSERT(ar->arHtcTarget != NULL);
+ if (!arRaw) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Faile to allocate memory for HTC RAW interface\n"));
+ return -ENOMEM;
+ }
+ /* wait for target */
+ status = HTCWaitTarget(ar->arHtcTarget);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTCWaitTarget failed (%d)\n", status));
+ return -ENODEV;
+ }
+
+ for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) {
+ arRaw->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED;
+ }
+
+ for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) {
+ /* Initialize the data structures */
+ init_MUTEX(&arRaw->raw_htc_read_sem[streamID]);
+ init_MUTEX(&arRaw->raw_htc_write_sem[streamID]);
+ init_waitqueue_head(&arRaw->raw_htc_read_queue[streamID]);
+ init_waitqueue_head(&arRaw->raw_htc_write_queue[streamID]);
+
+ /* try to connect to the raw service */
+ status = ar6000_connect_raw_service(ar,streamID);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (arRawStream2EndpointID(ar,streamID) == 0) {
+ break;
+ }
+
+ for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
+ /* Initialize the receive buffers */
+ buffer = &arRaw->raw_htc_write_buffer[streamID][count2];
+ memset(buffer, 0, sizeof(raw_htc_buffer));
+ buffer = &arRaw->raw_htc_read_buffer[streamID][count2];
+ memset(buffer, 0, sizeof(raw_htc_buffer));
+
+ SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket,
+ buffer,
+ buffer->data,
+ HTC_RAW_BUFFER_SIZE,
+ arRawStream2EndpointID(ar,streamID));
+
+ /* Queue buffers to HTC for receive */
+ if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK)
+ {
+ BMIInit();
+ return -EIO;
+ }
+ }
+
+ for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
+ /* Initialize the receive buffers */
+ buffer = &arRaw->raw_htc_write_buffer[streamID][count2];
+ memset(buffer, 0, sizeof(raw_htc_buffer));
+ }
+
+ arRaw->read_buffer_available[streamID] = FALSE;
+ arRaw->write_buffer_available[streamID] = TRUE;
+ }
+
+ if (A_FAILED(status)) {
+ return -EIO;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("HTC RAW, number of streams the target supports: %d \n", streamID));
+
+ servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */
+
+ /* set callbacks and priority list */
+ HTCSetCreditDistribution(ar->arHtcTarget,
+ ar,
+ NULL, /* use default */
+ NULL, /* use default */
+ &servicepriority,
+ 1);
+
+ /* Start the HTC component */
+ if ((status = HTCStart(ar->arHtcTarget)) != A_OK) {
+ BMIInit();
+ return -EIO;
+ }
+
+ (ar)->arRawIfInit = TRUE;
+
+ return 0;
+}
+
+int ar6000_htc_raw_close(AR_SOFTC_T *ar)
+{
+ A_PRINTF("ar6000_htc_raw_close called \n");
+ HTCStop(ar->arHtcTarget);
+
+ /* reset the device */
+ ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, FALSE);
+ /* Initialize the BMI component */
+ BMIInit();
+
+ if (ar->arRawHtc) {
+ A_FREE(ar->arRawHtc);
+ ar->arRawHtc = NULL;
+ }
+ return 0;
+}
+
+raw_htc_buffer *
+get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID)
+{
+ int count;
+ raw_htc_buffer *busy;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+ /* Check for data */
+ for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
+ busy = &arRaw->raw_htc_read_buffer[StreamID][count];
+ if (busy->length) {
+ break;
+ }
+ }
+ if (busy->length) {
+ arRaw->read_buffer_available[StreamID] = TRUE;
+ } else {
+ arRaw->read_buffer_available[StreamID] = FALSE;
+ }
+
+ return busy;
+}
+
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t length)
+{
+ int readPtr;
+ raw_htc_buffer *busy;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+ if (arRawStream2EndpointID(ar,StreamID) == 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID));
+ return -EFAULT;
+ }
+
+ if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+
+ busy = get_filled_buffer(ar,StreamID);
+ while (!arRaw->read_buffer_available[StreamID]) {
+ up(&arRaw->raw_htc_read_sem[StreamID]);
+
+ /* Wait for the data */
+ AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) read process\n", StreamID));
+ if (wait_event_interruptible(arRaw->raw_htc_read_queue[StreamID],
+ arRaw->read_buffer_available[StreamID]))
+ {
+ return -EINTR;
+ }
+ if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+ busy = get_filled_buffer(ar,StreamID);
+ }
+
+ /* Read the data */
+ readPtr = busy->currPtr;
+ if (length > busy->length - HTC_HEADER_LEN) {
+ length = busy->length - HTC_HEADER_LEN;
+ }
+ if (copy_to_user(buffer, &busy->data[readPtr], length)) {
+ up(&arRaw->raw_htc_read_sem[StreamID]);
+ return -EFAULT;
+ }
+
+ busy->currPtr += length;
+
+ if (busy->currPtr == busy->length)
+ {
+ busy->currPtr = 0;
+ busy->length = 0;
+ HTC_PACKET_RESET_RX(&busy->HTCPacket);
+ //AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint));
+ HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket);
+ }
+ arRaw->read_buffer_available[StreamID] = FALSE;
+ up(&arRaw->raw_htc_read_sem[StreamID]);
+
+ return length;
+}
+
+static raw_htc_buffer *
+get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID)
+{
+ int count;
+ raw_htc_buffer *free;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+
+ free = NULL;
+ for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
+ free = &arRaw->raw_htc_write_buffer[StreamID][count];
+ if (free->length == 0) {
+ break;
+ }
+ }
+ if (!free->length) {
+ arRaw->write_buffer_available[StreamID] = TRUE;
+ } else {
+ arRaw->write_buffer_available[StreamID] = FALSE;
+ }
+
+ return free;
+}
+
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t length)
+{
+ int writePtr;
+ raw_htc_buffer *free;
+ AR_RAW_HTC_T *arRaw = ar->arRawHtc;
+ if (arRawStream2EndpointID(ar,StreamID) == 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID));
+ return -EFAULT;
+ }
+
+ if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+
+ /* Search for a free buffer */
+ free = get_free_buffer(ar,StreamID);
+
+ /* Check if there is space to write else wait */
+ while (!arRaw->write_buffer_available[StreamID]) {
+ up(&arRaw->raw_htc_write_sem[StreamID]);
+
+ /* Wait for buffer to become free */
+ AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) write process\n", StreamID));
+ if (wait_event_interruptible(arRaw->raw_htc_write_queue[StreamID],
+ arRaw->write_buffer_available[StreamID]))
+ {
+ return -EINTR;
+ }
+ if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+ free = get_free_buffer(ar,StreamID);
+ }
+
+ /* Send the data */
+ writePtr = HTC_HEADER_LEN;
+ if (length > (HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN)) {
+ length = HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN;
+ }
+
+ if (copy_from_user(&free->data[writePtr], buffer, length)) {
+ up(&arRaw->raw_htc_read_sem[StreamID]);
+ return -EFAULT;
+ }
+
+ free->length = length;
+
+ SET_HTC_PACKET_INFO_TX(&free->HTCPacket,
+ free,
+ &free->data[writePtr],
+ length,
+ arRawStream2EndpointID(ar,StreamID),
+ AR6K_DATA_PKT_TAG);
+
+ HTCSendPkt(ar->arHtcTarget,&free->HTCPacket);
+
+ arRaw->write_buffer_available[StreamID] = FALSE;
+ up(&arRaw->raw_htc_write_sem[StreamID]);
+
+ return length;
+}
+#endif /* HTC_RAW_INTERFACE */
diff --git a/drivers/net/wireless/ath6kl/os/linux/cfg80211.c b/drivers/net/wireless/ath6kl/os/linux/cfg80211.c
new file mode 100644
index 000000000000..402f98931b46
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/cfg80211.c
@@ -0,0 +1,1467 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <net/cfg80211.h>
+
+#include "ar6000_drv.h"
+
+
+extern A_WAITQUEUE_HEAD arEvent;
+extern unsigned int wmitimeout;
+extern int reconnect_flag;
+
+
+#define RATETAB_ENT(_rate, _rateid, _flags) { \
+ .bitrate = (_rate), \
+ .flags = (_flags), \
+ .hw_value = (_rateid), \
+}
+
+#define CHAN2G(_channel, _freq, _flags) { \
+ .band = IEEE80211_BAND_2GHZ, \
+ .hw_value = (_channel), \
+ .center_freq = (_freq), \
+ .flags = (_flags), \
+ .max_antenna_gain = 0, \
+ .max_power = 30, \
+}
+
+#define CHAN5G(_channel, _flags) { \
+ .band = IEEE80211_BAND_5GHZ, \
+ .hw_value = (_channel), \
+ .center_freq = 5000 + (5 * (_channel)), \
+ .flags = (_flags), \
+ .max_antenna_gain = 0, \
+ .max_power = 30, \
+}
+
+static struct
+ieee80211_rate ar6k_rates[] = {
+ RATETAB_ENT(10, 0x1, 0),
+ RATETAB_ENT(20, 0x2, 0),
+ RATETAB_ENT(55, 0x4, 0),
+ RATETAB_ENT(110, 0x8, 0),
+ RATETAB_ENT(60, 0x10, 0),
+ RATETAB_ENT(90, 0x20, 0),
+ RATETAB_ENT(120, 0x40, 0),
+ RATETAB_ENT(180, 0x80, 0),
+ RATETAB_ENT(240, 0x100, 0),
+ RATETAB_ENT(360, 0x200, 0),
+ RATETAB_ENT(480, 0x400, 0),
+ RATETAB_ENT(540, 0x800, 0),
+};
+
+#define ar6k_a_rates (ar6k_rates + 4)
+#define ar6k_a_rates_size 8
+#define ar6k_g_rates (ar6k_rates + 0)
+#define ar6k_g_rates_size 12
+
+static struct
+ieee80211_channel ar6k_2ghz_channels[] = {
+ CHAN2G(1, 2412, 0),
+ CHAN2G(2, 2417, 0),
+ CHAN2G(3, 2422, 0),
+ CHAN2G(4, 2427, 0),
+ CHAN2G(5, 2432, 0),
+ CHAN2G(6, 2437, 0),
+ CHAN2G(7, 2442, 0),
+ CHAN2G(8, 2447, 0),
+ CHAN2G(9, 2452, 0),
+ CHAN2G(10, 2457, 0),
+ CHAN2G(11, 2462, 0),
+ CHAN2G(12, 2467, 0),
+ CHAN2G(13, 2472, 0),
+ CHAN2G(14, 2484, 0),
+};
+
+static struct
+ieee80211_channel ar6k_5ghz_a_channels[] = {
+ CHAN5G(34, 0), CHAN5G(36, 0),
+ CHAN5G(38, 0), CHAN5G(40, 0),
+ CHAN5G(42, 0), CHAN5G(44, 0),
+ CHAN5G(46, 0), CHAN5G(48, 0),
+ CHAN5G(52, 0), CHAN5G(56, 0),
+ CHAN5G(60, 0), CHAN5G(64, 0),
+ CHAN5G(100, 0), CHAN5G(104, 0),
+ CHAN5G(108, 0), CHAN5G(112, 0),
+ CHAN5G(116, 0), CHAN5G(120, 0),
+ CHAN5G(124, 0), CHAN5G(128, 0),
+ CHAN5G(132, 0), CHAN5G(136, 0),
+ CHAN5G(140, 0), CHAN5G(149, 0),
+ CHAN5G(153, 0), CHAN5G(157, 0),
+ CHAN5G(161, 0), CHAN5G(165, 0),
+ CHAN5G(184, 0), CHAN5G(188, 0),
+ CHAN5G(192, 0), CHAN5G(196, 0),
+ CHAN5G(200, 0), CHAN5G(204, 0),
+ CHAN5G(208, 0), CHAN5G(212, 0),
+ CHAN5G(216, 0),
+};
+
+static struct
+ieee80211_supported_band ar6k_band_2ghz = {
+ .n_channels = ARRAY_SIZE(ar6k_2ghz_channels),
+ .channels = ar6k_2ghz_channels,
+ .n_bitrates = ar6k_g_rates_size,
+ .bitrates = ar6k_g_rates,
+};
+
+static struct
+ieee80211_supported_band ar6k_band_5ghz = {
+ .n_channels = ARRAY_SIZE(ar6k_5ghz_a_channels),
+ .channels = ar6k_5ghz_a_channels,
+ .n_bitrates = ar6k_a_rates_size,
+ .bitrates = ar6k_a_rates,
+};
+
+static int
+ar6k_set_wpa_version(AR_SOFTC_T *ar, enum nl80211_wpa_versions wpa_version)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: %u\n", __func__, wpa_version));
+
+ if (!wpa_version) {
+ ar->arAuthMode = NONE_AUTH;
+ } else if (wpa_version & NL80211_WPA_VERSION_1) {
+ ar->arAuthMode = WPA_AUTH;
+ } else if (wpa_version & NL80211_WPA_VERSION_2) {
+ ar->arAuthMode = WPA2_AUTH;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: %u not spported\n", __func__, wpa_version));
+ return -ENOTSUPP;
+ }
+
+ return A_OK;
+}
+
+static int
+ar6k_set_auth_type(AR_SOFTC_T *ar, enum nl80211_auth_type auth_type)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, auth_type));
+
+ switch (auth_type) {
+ case NL80211_AUTHTYPE_OPEN_SYSTEM:
+ ar->arDot11AuthMode = OPEN_AUTH;
+ break;
+ case NL80211_AUTHTYPE_SHARED_KEY:
+ ar->arDot11AuthMode = SHARED_AUTH;
+ break;
+ case NL80211_AUTHTYPE_NETWORK_EAP:
+ ar->arDot11AuthMode = LEAP_AUTH;
+ break;
+ default:
+ ar->arDot11AuthMode = OPEN_AUTH;
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: 0x%x not spported\n", __func__, auth_type));
+ return -ENOTSUPP;
+ }
+
+ return A_OK;
+}
+
+static int
+ar6k_set_cipher(AR_SOFTC_T *ar, A_UINT32 cipher, A_BOOL ucast)
+{
+ A_UINT8 *ar_cipher = ucast ? &ar->arPairwiseCrypto :
+ &ar->arGroupCrypto;
+ A_UINT8 *ar_cipher_len = ucast ? &ar->arPairwiseCryptoLen :
+ &ar->arGroupCryptoLen;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: cipher 0x%x, ucast %u\n", __func__, cipher, ucast));
+
+ switch (cipher) {
+ case 0:
+ case IW_AUTH_CIPHER_NONE:
+ *ar_cipher = NONE_CRYPT;
+ *ar_cipher_len = 0;
+ break;
+ case WLAN_CIPHER_SUITE_WEP40:
+ *ar_cipher = WEP_CRYPT;
+ *ar_cipher_len = 5;
+ break;
+ case WLAN_CIPHER_SUITE_WEP104:
+ *ar_cipher = WEP_CRYPT;
+ *ar_cipher_len = 13;
+ break;
+ case WLAN_CIPHER_SUITE_TKIP:
+ *ar_cipher = TKIP_CRYPT;
+ *ar_cipher_len = 0;
+ break;
+ case WLAN_CIPHER_SUITE_CCMP:
+ *ar_cipher = AES_CRYPT;
+ *ar_cipher_len = 0;
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: cipher 0x%x not supported\n", __func__, cipher));
+ return -ENOTSUPP;
+ }
+
+ return A_OK;
+}
+
+static void
+ar6k_set_key_mgmt(AR_SOFTC_T *ar, A_UINT32 key_mgmt)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, key_mgmt));
+
+ if (WLAN_AKM_SUITE_PSK == key_mgmt) {
+ if (WPA_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA_PSK_AUTH;
+ } else if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_PSK_AUTH;
+ }
+ } else if (WLAN_AKM_SUITE_8021X != key_mgmt) {
+ ar->arAuthMode = NONE_AUTH;
+ }
+}
+
+static int
+ar6k_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev,
+ struct cfg80211_connect_params *sme)
+{
+ AR_SOFTC_T *ar = ar6k_priv(dev);
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready yet\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->bIsDestroyProgress) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: destroy in progress\n", __func__));
+ return -EBUSY;
+ }
+
+ if(!sme->ssid_len || IEEE80211_MAX_SSID_LEN < sme->ssid_len) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__));
+ return -EINVAL;
+ }
+
+ if(ar->arSkipScan == TRUE &&
+ ((sme->channel && sme->channel->center_freq == 0) ||
+ (sme->bssid && !sme->bssid[0] && !sme->bssid[1] && !sme->bssid[2] &&
+ !sme->bssid[3] && !sme->bssid[4] && !sme->bssid[5])))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s:SkipScan: channel or bssid invalid\n", __func__));
+ return -EINVAL;
+ }
+
+ if(down_interruptible(&ar->arSem)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+ return -ERESTARTSYS;
+ }
+
+ if(ar->bIsDestroyProgress) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__));
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ if(ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
+ /*
+ * sleep until the command queue drains
+ */
+ wait_event_interruptible_timeout(arEvent,
+ ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: cmd queue drain timeout\n", __func__));
+ up(&ar->arSem);
+ return -EINTR;
+ }
+ }
+
+ if(ar->arConnected == TRUE &&
+ ar->arSsidLen == sme->ssid_len &&
+ !A_MEMCMP(ar->arSsid, sme->ssid, ar->arSsidLen)) {
+ reconnect_flag = TRUE;
+ status = wmi_reconnect_cmd(ar->arWmi,
+ ar->arReqBssid,
+ ar->arChannelHint);
+
+ up(&ar->arSem);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_reconnect_cmd failed\n", __func__));
+ return -EIO;
+ }
+ return 0;
+ }
+
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = sme->ssid_len;
+ A_MEMCPY(ar->arSsid, sme->ssid, sme->ssid_len);
+
+ if(sme->channel){
+ ar->arChannelHint = sme->channel->center_freq;
+ }
+
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ if(sme->bssid){
+ if(A_MEMCMP(&sme->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) {
+ A_MEMCPY(ar->arReqBssid, sme->bssid, sizeof(ar->arReqBssid));
+ }
+ }
+
+ ar6k_set_wpa_version(ar, sme->crypto.wpa_versions);
+ ar6k_set_auth_type(ar, sme->auth_type);
+
+ if(sme->crypto.n_ciphers_pairwise) {
+ ar6k_set_cipher(ar, sme->crypto.ciphers_pairwise[0], true);
+ }
+ ar6k_set_cipher(ar, sme->crypto.cipher_group, false);
+
+ if(sme->crypto.n_akm_suites) {
+ ar6k_set_key_mgmt(ar, sme->crypto.akm_suites[0]);
+ }
+
+ ar->arNetworkType = INFRA_NETWORK;
+
+ if((sme->key_len) &&
+ (NONE_AUTH == ar->arAuthMode) &&
+ (WEP_CRYPT == ar->arPairwiseCrypto)) {
+ struct ar_key *key = NULL;
+
+ if(sme->key_idx < WMI_MIN_KEY_INDEX || sme->key_idx > WMI_MAX_KEY_INDEX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: key index %d out of bounds\n", __func__, sme->key_idx));
+ up(&ar->arSem);
+ return -ENOENT;
+ }
+
+ key = &ar->keys[sme->key_idx];
+ key->key_len = sme->key_len;
+ A_MEMCPY(key->key, sme->key, key->key_len);
+ key->cipher = ar->arPairwiseCrypto;
+ ar->arDefTxKeyIndex = sme->key_idx;
+
+ wmi_addKey_cmd(ar->arWmi, sme->key_idx,
+ ar->arPairwiseCrypto,
+ GROUP_USAGE | TX_USAGE,
+ key->key_len,
+ NULL,
+ key->key, KEY_OP_INIT_VAL, NULL,
+ NO_SYNC_WMIFLAG);
+ }
+
+ if (!ar->arUserBssFilter) {
+ if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__));
+ up(&ar->arSem);
+ return -EIO;
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\
+ " PW crypto %d PW crypto Len %d GRP crypto %d"\
+ " GRP crypto Len %d channel hint %u\n",
+ __func__, ar->arAuthMode, ar->arDot11AuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint));
+
+ reconnect_flag = 0;
+ status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+ ar->arDot11AuthMode, ar->arAuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto,ar->arGroupCryptoLen,
+ ar->arSsidLen, ar->arSsid,
+ ar->arReqBssid, ar->arChannelHint,
+ ar->arConnectCtrlFlags);
+
+ up(&ar->arSem);
+
+ if (A_EINVAL == status) {
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Invalid request\n", __func__));
+ return -ENOENT;
+ } else if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_connect_cmd failed\n", __func__));
+ return -EIO;
+ }
+
+ if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) &&
+ ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)))
+ {
+ A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0);
+ }
+
+ ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD;
+ ar->arConnectPending = TRUE;
+
+ return 0;
+}
+
+void
+ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel,
+ A_UINT8 *bssid, A_UINT16 listenInterval,
+ A_UINT16 beaconInterval,NETWORK_TYPE networkType,
+ A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+ A_UINT8 assocRespLen, A_UINT8 *assocInfo)
+{
+ A_UINT16 size = 0;
+ A_UINT16 capability = 0;
+ struct cfg80211_bss *bss = NULL;
+ struct ieee80211_mgmt *mgmt = NULL;
+ struct ieee80211_channel *ibss_channel = NULL;
+ s32 signal = 50 * 100;
+ A_UINT8 ie_buf_len = 0;
+ unsigned char ie_buf[256];
+ unsigned char *ptr_ie_buf = ie_buf;
+ unsigned char *ieeemgmtbuf = NULL;
+ A_UINT8 source_mac[ATH_MAC_LEN];
+
+ A_UINT8 assocReqIeOffset = sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16); /* listen interval */
+ A_UINT8 assocRespIeOffset = sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16) + /* status Code */
+ sizeof(A_UINT16); /* associd */
+ A_UINT8 *assocReqIe = assocInfo + beaconIeLen + assocReqIeOffset;
+ A_UINT8 *assocRespIe = assocInfo + beaconIeLen + assocReqLen + assocRespIeOffset;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ assocReqLen -= assocReqIeOffset;
+ assocRespLen -= assocRespIeOffset;
+
+ if((ADHOC_NETWORK & networkType)) {
+ if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: ath6k not in ibss mode\n", __func__));
+ return;
+ }
+ }
+
+ /* Before informing the join/connect event, make sure that
+ * bss entry is present in scan list, if it not present
+ * construct and insert into scan list, otherwise that
+ * event will be dropped on the way by cfg80211, due to
+ * this keys will not be plumbed in case of WEP and
+ * application will not be aware of join/connect status. */
+ bss = cfg80211_get_bss(ar->wdev->wiphy, NULL, bssid,
+ ar->wdev->ssid, ar->wdev->ssid_len,
+ ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS),
+ ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS));
+
+ if(!bss) {
+ if (ADHOC_NETWORK & networkType) {
+ /* construct 802.11 mgmt beacon */
+ if(ptr_ie_buf) {
+ *ptr_ie_buf++ = WLAN_EID_SSID;
+ *ptr_ie_buf++ = ar->arSsidLen;
+ A_MEMCPY(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
+ ptr_ie_buf +=ar->arSsidLen;
+
+ *ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
+ *ptr_ie_buf++ = 2; /* length */
+ *ptr_ie_buf++ = 0; /* ATIM window */
+ *ptr_ie_buf++ = 0; /* ATIM window */
+
+ /* TODO: update ibss params and include supported rates,
+ * DS param set, extened support rates, wmm. */
+
+ ie_buf_len = ptr_ie_buf - ie_buf;
+ }
+
+ capability |= IEEE80211_CAPINFO_IBSS;
+ if(WEP_CRYPT == ar->arPairwiseCrypto) {
+ capability |= IEEE80211_CAPINFO_PRIVACY;
+ }
+ A_MEMCPY(source_mac, ar->arNetDev->dev_addr, ATH_MAC_LEN);
+ ptr_ie_buf = ie_buf;
+ } else {
+ capability = *(A_UINT16 *)(&assocInfo[beaconIeLen]);
+ A_MEMCPY(source_mac, bssid, ATH_MAC_LEN);
+ ptr_ie_buf = assocReqIe;
+ ie_buf_len = assocReqLen;
+ }
+
+ size = offsetof(struct ieee80211_mgmt, u)
+ + sizeof(mgmt->u.beacon)
+ + ie_buf_len;
+
+ ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+ if(!ieeemgmtbuf) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: ieeeMgmtbuf alloc error\n", __func__));
+ return;
+ }
+
+ A_MEMZERO(ieeemgmtbuf, size);
+ mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+ mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
+ A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN);
+ A_MEMCPY(mgmt->sa, source_mac, ATH_MAC_LEN);
+ A_MEMCPY(mgmt->bssid, bssid, ATH_MAC_LEN);
+ mgmt->u.beacon.beacon_int = beaconInterval;
+ mgmt->u.beacon.capab_info = capability;
+ A_MEMCPY(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
+
+ ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: inform bss with bssid %02x:%02x:%02x:%02x:%02x:%02x "\
+ "channel %d beaconInterval %d capability 0x%x\n",
+ __func__,
+ mgmt->bssid[0], mgmt->bssid[1], mgmt->bssid[2],
+ mgmt->bssid[3], mgmt->bssid[4], mgmt->bssid[5],
+ ibss_channel->hw_value, beaconInterval, capability));
+
+ bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
+ ibss_channel, mgmt,
+ le16_to_cpu(size),
+ signal, GFP_KERNEL);
+ A_FREE(ieeemgmtbuf);
+ cfg80211_put_bss(bss);
+ }
+
+ if((ADHOC_NETWORK & networkType)) {
+ cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
+ return;
+ }
+
+ if (FALSE == ar->arConnected) {
+ /* inform connect result to cfg80211 */
+ cfg80211_connect_result(ar->arNetDev, bssid,
+ assocReqIe, assocReqLen,
+ assocRespIe, assocRespLen,
+ WLAN_STATUS_SUCCESS, GFP_KERNEL);
+ } else {
+ /* inform roam event to cfg80211 */
+ cfg80211_roamed(ar->arNetDev, bssid,
+ assocReqIe, assocReqLen,
+ assocRespIe, assocRespLen,
+ GFP_KERNEL);
+ }
+}
+
+static int
+ar6k_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev,
+ A_UINT16 reason_code)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason_code));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->bIsDestroyProgress) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__));
+ return -EBUSY;
+ }
+
+ if(down_interruptible(&ar->arSem)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+ return -ERESTARTSYS;
+ }
+
+ reconnect_flag = 0;
+ wmi_disconnect_cmd(ar->arWmi);
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+
+ if (ar->arSkipScan == FALSE) {
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ }
+
+ up(&ar->arSem);
+
+ return 0;
+}
+
+void
+ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason,
+ A_UINT8 *bssid, A_UINT8 assocRespLen,
+ A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason));
+
+ if((ADHOC_NETWORK & ar->arNetworkType)) {
+ if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: ath6k not in ibss mode\n", __func__));
+ return;
+ }
+ A_MEMZERO(bssid, ETH_ALEN);
+ cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
+ return;
+ }
+
+ if(FALSE == ar->arConnected) {
+ if(NO_NETWORK_AVAIL == reason) {
+ /* connect cmd failed */
+ cfg80211_connect_result(ar->arNetDev, bssid,
+ NULL, 0,
+ NULL, 0,
+ WLAN_STATUS_UNSPECIFIED_FAILURE,
+ GFP_KERNEL);
+ }
+ } else {
+ /* connection loss due to disconnect cmd or low rssi */
+ cfg80211_disconnected(ar->arNetDev, reason, NULL, 0, GFP_KERNEL);
+ }
+}
+
+void
+ar6k_cfg80211_scan_node(void *arg, bss_t *ni)
+{
+ struct wiphy *wiphy = (struct wiphy *)arg;
+ A_UINT16 size;
+ unsigned char *ieeemgmtbuf = NULL;
+ struct ieee80211_mgmt *mgmt;
+ struct ieee80211_channel *channel;
+ struct ieee80211_supported_band *band;
+ struct ieee80211_common_ie *cie;
+ s32 signal;
+ int freq;
+
+ cie = &ni->ni_cie;
+
+#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484)))
+ if(CHAN_IS_11A(cie->ie_chan)) {
+ /* 11a */
+ band = wiphy->bands[IEEE80211_BAND_5GHZ];
+ } else if((cie->ie_erp) || (cie->ie_xrates)) {
+ /* 11g */
+ band = wiphy->bands[IEEE80211_BAND_2GHZ];
+ } else {
+ /* 11b */
+ band = wiphy->bands[IEEE80211_BAND_2GHZ];
+ }
+
+ size = ni->ni_framelen + offsetof(struct ieee80211_mgmt, u);
+ ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+ if(!ieeemgmtbuf)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ieeeMgmtbuf alloc error\n", __func__));
+ return;
+ }
+
+ /* Note:
+ TODO: Update target to include 802.11 mac header while sending bss info.
+ Target removes 802.11 mac header while sending the bss info to host,
+ cfg80211 needs it, for time being just filling the da, sa and bssid fields alone.
+ */
+ mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+ A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN);
+ A_MEMCPY(mgmt->sa, ni->ni_macaddr, ATH_MAC_LEN);
+ A_MEMCPY(mgmt->bssid, ni->ni_macaddr, ATH_MAC_LEN);
+ A_MEMCPY(ieeemgmtbuf + offsetof(struct ieee80211_mgmt, u),
+ ni->ni_buf, ni->ni_framelen);
+
+ freq = cie->ie_chan;
+ channel = ieee80211_get_channel(wiphy, freq);
+ signal = ni->ni_snr * 100;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: bssid %02x:%02x:%02x:%02x:%02x:%02x channel %d freq %d size %d\n",
+ __func__,
+ mgmt->bssid[0], mgmt->bssid[1], mgmt->bssid[2],
+ mgmt->bssid[3], mgmt->bssid[4], mgmt->bssid[5],
+ channel->hw_value, freq, size));
+ cfg80211_inform_bss_frame(wiphy, channel, mgmt,
+ le16_to_cpu(size),
+ signal, GFP_KERNEL);
+
+ A_FREE (ieeemgmtbuf);
+}
+
+static int
+ar6k_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
+ struct cfg80211_scan_request *request)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+ int ret = 0;
+ A_BOOL forceFgScan = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if (!ar->arUserBssFilter) {
+ if (wmi_bssfilter_cmd(ar->arWmi,
+ (ar->arConnected ? ALL_BUT_BSS_FILTER : ALL_BSS_FILTER),
+ 0) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__));
+ return -EIO;
+ }
+ }
+
+ if(request->n_ssids &&
+ request->ssids[0].ssid_len) {
+ A_UINT8 i;
+
+ if(request->n_ssids > MAX_PROBED_SSID_INDEX) {
+ request->n_ssids = MAX_PROBED_SSID_INDEX;
+ }
+
+ for (i = 0; i < request->n_ssids; i++) {
+ wmi_probedSsid_cmd(ar->arWmi, i, SPECIFIC_SSID_FLAG,
+ request->ssids[i].ssid_len,
+ request->ssids[i].ssid);
+ }
+ }
+
+ if(ar->arConnected) {
+ forceFgScan = TRUE;
+ }
+
+ if(wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, forceFgScan, FALSE, \
+ 0, 0, 0, NULL) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_startscan_cmd failed\n", __func__));
+ ret = -EIO;
+ }
+
+ ar->scan_request = request;
+
+ return ret;
+}
+
+void
+ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: status %d\n", __func__, status));
+
+ if(ar->scan_request)
+ {
+ /* Translate data to cfg80211 mgmt format */
+ wmi_iterate_nodes(ar->arWmi, ar6k_cfg80211_scan_node, ar->wdev->wiphy);
+
+ cfg80211_scan_done(ar->scan_request,
+ (status & A_ECANCELED) ? true : false);
+
+ if(ar->scan_request->n_ssids &&
+ ar->scan_request->ssids[0].ssid_len) {
+ A_UINT8 i;
+
+ for (i = 0; i < ar->scan_request->n_ssids; i++) {
+ wmi_probedSsid_cmd(ar->arWmi, i, DISABLE_SSID_FLAG,
+ 0, NULL);
+ }
+ }
+ ar->scan_request = NULL;
+ }
+}
+
+static int
+ar6k_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+ A_UINT8 key_index, const A_UINT8 *mac_addr,
+ struct key_params *params)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+ struct ar_key *key = NULL;
+ A_UINT8 key_usage;
+ A_UINT8 key_type;
+ A_STATUS status = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s:\n", __func__));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: key index %d out of bounds\n", __func__, key_index));
+ return -ENOENT;
+ }
+
+ key = &ar->keys[key_index];
+ A_MEMZERO(key, sizeof(struct ar_key));
+
+ if(!mac_addr || is_broadcast_ether_addr(mac_addr)) {
+ key_usage = GROUP_USAGE;
+ } else {
+ key_usage = PAIRWISE_USAGE;
+ }
+
+ if(params) {
+ if(params->key_len > WLAN_MAX_KEY_LEN ||
+ params->seq_len > IW_ENCODE_SEQ_MAX_SIZE)
+ return -EINVAL;
+
+ key->key_len = params->key_len;
+ A_MEMCPY(key->key, params->key, key->key_len);
+ key->seq_len = params->seq_len;
+ A_MEMCPY(key->seq, params->seq, key->seq_len);
+ key->cipher = params->cipher;
+ }
+
+ switch (key->cipher) {
+ case WLAN_CIPHER_SUITE_WEP40:
+ case WLAN_CIPHER_SUITE_WEP104:
+ key_type = WEP_CRYPT;
+ if(key_index == ar->arDefTxKeyIndex) {
+ key_usage = GROUP_USAGE | TX_USAGE;
+ }
+ break;
+
+ case WLAN_CIPHER_SUITE_TKIP:
+ key_type = TKIP_CRYPT;
+ break;
+
+ case WLAN_CIPHER_SUITE_CCMP:
+ key_type = AES_CRYPT;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+ (GROUP_USAGE & key_usage))
+ {
+ A_UNTIMEOUT(&ar->disconnect_timer);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: index %d, key_len %d, key_type 0x%x,"\
+ " key_usage 0x%x, seq_len %d\n",
+ __func__, key_index, key->key_len, key_type,
+ key_usage, key->seq_len));
+
+ status = wmi_addKey_cmd(ar->arWmi, key_index, key_type, key_usage,
+ key->key_len, key->seq, key->key, KEY_OP_INIT_VAL,
+ (A_UINT8*)mac_addr, SYNC_BOTH_WMIFLAG);
+
+
+ if(status != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
+ A_UINT8 key_index, const A_UINT8 *mac_addr)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: key index %d out of bounds\n", __func__, key_index));
+ return -ENOENT;
+ }
+
+ if(!ar->keys[key_index].key_len) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d is empty\n", __func__, key_index));
+ return 0;
+ }
+
+ ar->keys[key_index].key_len = 0;
+
+ return wmi_deleteKey_cmd(ar->arWmi, key_index);
+}
+
+
+static int
+ar6k_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev,
+ A_UINT8 key_index, const A_UINT8 *mac_addr, void *cookie,
+ void (*callback)(void *cookie, struct key_params*))
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+ struct ar_key *key = NULL;
+ struct key_params params;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: key index %d out of bounds\n", __func__, key_index));
+ return -ENOENT;
+ }
+
+ key = &ar->keys[key_index];
+ A_MEMZERO(&params, sizeof(params));
+ params.cipher = key->cipher;
+ params.key_len = key->key_len;
+ params.seq_len = key->seq_len;
+ params.seq = key->seq;
+ params.key = key->key;
+
+ callback(cookie, &params);
+
+ return key->key_len ? 0 : -ENOENT;
+}
+
+
+static int
+ar6k_cfg80211_set_default_key(struct wiphy *wiphy, struct net_device *ndev,
+ A_UINT8 key_index)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: key index %d out of bounds\n",
+ __func__, key_index));
+ return -ENOENT;
+ }
+
+ if(!ar->keys[key_index].key_len) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: invalid key index %d\n",
+ __func__, key_index));
+ return -EINVAL;
+ }
+
+ ar->arDefTxKeyIndex = key_index;
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_set_default_mgmt_key(struct wiphy *wiphy, struct net_device *ndev,
+ A_UINT8 key_index)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+ return -ENOTSUPP;
+}
+
+void
+ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: keyid %d, ismcast %d\n", __func__, keyid, ismcast));
+
+ cfg80211_michael_mic_failure(ar->arNetDev, ar->arBssid,
+ (ismcast ? NL80211_KEYTYPE_GROUP : NL80211_KEYTYPE_PAIRWISE),
+ keyid, NULL, GFP_KERNEL);
+}
+
+static int
+ar6k_cfg80211_set_wiphy_params(struct wiphy *wiphy, A_UINT32 changed)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: changed 0x%x\n", __func__, changed));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if (changed & WIPHY_PARAM_RTS_THRESHOLD) {
+ if (wmi_set_rts_cmd(ar->arWmi,wiphy->rts_threshold) != A_OK){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_rts_cmd failed\n", __func__));
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev,
+ const A_UINT8 *peer,
+ const struct cfg80211_bitrate_mask *mask)
+{
+ AR_SOFTC_T *ar = ar6k_priv(dev);
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: mask 0x%x\n", __func__, mask->fixed));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ status = wmi_set_fixrates_cmd(ar->arWmi, mask->fixed);
+
+ if(status == A_EINVAL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: invalid params\n", __func__));
+ return -EINVAL;
+ } else if(status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_fixrates_cmd failed\n", __func__));
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_set_txpower(struct wiphy *wiphy, enum tx_power_setting type, int dbm)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+ A_UINT8 ar_dbm;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x, dbm %d\n", __func__, type, dbm));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ ar->arTxPwrSet = FALSE;
+ switch(type) {
+ case TX_POWER_AUTOMATIC:
+ return 0;
+ case TX_POWER_LIMITED:
+ ar->arTxPwr = ar_dbm = dbm;
+ ar->arTxPwrSet = TRUE;
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x not supported\n", __func__, type));
+ return -EOPNOTSUPP;
+ }
+
+ wmi_set_txPwr_cmd(ar->arWmi, ar_dbm);
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_get_txpower(struct wiphy *wiphy, int *dbm)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if((ar->arConnected == TRUE)) {
+ ar->arTxPwr = 0;
+
+ if(wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_get_txPwr_cmd failed\n", __func__));
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, 5 * HZ);
+
+ if(signal_pending(current)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Target did not respond\n", __func__));
+ return -EINTR;
+ }
+ }
+
+ *dbm = ar->arTxPwr;
+ return 0;
+}
+
+static int
+ar6k_cfg80211_set_power_mgmt(struct wiphy *wiphy,
+ struct net_device *dev,
+ bool pmgmt, int timeout)
+{
+ AR_SOFTC_T *ar = ar6k_priv(dev);
+ WMI_POWER_MODE_CMD pwrMode;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: pmgmt %d, timeout %d\n", __func__, pmgmt, timeout));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(pmgmt) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Max Perf\n", __func__));
+ pwrMode.powerMode = MAX_PERF_POWER;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Rec Power\n", __func__));
+ pwrMode.powerMode = REC_POWER;
+ }
+
+ if(wmi_powermode_cmd(ar->arWmi, pwrMode.powerMode) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_powermode_cmd failed\n", __func__));
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_add_virtual_intf(struct wiphy *wiphy, char *name,
+ enum nl80211_iftype type, u32 *flags,
+ struct vif_params *params)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+
+ /* Multiple virtual interface is not supported.
+ * The default interface supports STA and IBSS type
+ */
+ return -EOPNOTSUPP;
+}
+
+static int
+ar6k_cfg80211_del_virtual_intf(struct wiphy *wiphy, struct net_device *dev)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__));
+
+ /* Multiple virtual interface is not supported.
+ * The default interface supports STA and IBSS type
+ */
+ return -EOPNOTSUPP;
+}
+
+static int
+ar6k_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
+ enum nl80211_iftype type, u32 *flags,
+ struct vif_params *params)
+{
+ AR_SOFTC_T *ar = ar6k_priv(ndev);
+ struct wireless_dev *wdev = ar->wdev;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type %u\n", __func__, type));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ switch (type) {
+ case NL80211_IFTYPE_STATION:
+ ar->arNetworkType = INFRA_NETWORK;
+ break;
+ case NL80211_IFTYPE_ADHOC:
+ ar->arNetworkType = ADHOC_NETWORK;
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: type %u\n", __func__, type));
+ return -EOPNOTSUPP;
+ }
+
+ wdev->iftype = type;
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
+ struct cfg80211_ibss_params *ibss_param)
+{
+ AR_SOFTC_T *ar = ar6k_priv(dev);
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ if(!ibss_param->ssid_len || IEEE80211_MAX_SSID_LEN < ibss_param->ssid_len) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__));
+ return -EINVAL;
+ }
+
+ ar->arSsidLen = ibss_param->ssid_len;
+ A_MEMCPY(ar->arSsid, ibss_param->ssid, ar->arSsidLen);
+
+ if(ibss_param->channel) {
+ ar->arChannelHint = ibss_param->channel->center_freq;
+ }
+
+ if(ibss_param->channel_fixed) {
+ /* TODO: channel_fixed: The channel should be fixed, do not search for
+ * IBSSs to join on other channels. Target firmware does not support this
+ * feature, needs to be updated.*/
+ }
+
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ if(ibss_param->bssid) {
+ if(A_MEMCMP(&ibss_param->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) {
+ A_MEMCPY(ar->arReqBssid, ibss_param->bssid, sizeof(ar->arReqBssid));
+ }
+ }
+
+ ar6k_set_wpa_version(ar, 0);
+ ar6k_set_auth_type(ar, NL80211_AUTHTYPE_OPEN_SYSTEM);
+
+ if(ibss_param->privacy) {
+ ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, true);
+ ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, false);
+ } else {
+ ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, true);
+ ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, false);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\
+ " PW crypto %d PW crypto Len %d GRP crypto %d"\
+ " GRP crypto Len %d channel hint %u\n",
+ __func__, ar->arAuthMode, ar->arDot11AuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint));
+
+ status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+ ar->arDot11AuthMode, ar->arAuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto,ar->arGroupCryptoLen,
+ ar->arSsidLen, ar->arSsid,
+ ar->arReqBssid, ar->arChannelHint,
+ ar->arConnectCtrlFlags);
+
+ return 0;
+}
+
+static int
+ar6k_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ if(ar->arWmiReady == FALSE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__));
+ return -EIO;
+ }
+
+ if(ar->arWlanState == WLAN_DISABLED) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__));
+ return -EIO;
+ }
+
+ wmi_disconnect_cmd(ar->arWmi);
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+
+ return 0;
+}
+
+
+static const
+A_UINT32 cipher_suites[] = {
+ WLAN_CIPHER_SUITE_WEP40,
+ WLAN_CIPHER_SUITE_WEP104,
+ WLAN_CIPHER_SUITE_TKIP,
+ WLAN_CIPHER_SUITE_CCMP,
+};
+
+static struct
+cfg80211_ops ar6k_cfg80211_ops = {
+ .change_virtual_intf = ar6k_cfg80211_change_iface,
+ .add_virtual_intf = ar6k_cfg80211_add_virtual_intf,
+ .del_virtual_intf = ar6k_cfg80211_del_virtual_intf,
+ .scan = ar6k_cfg80211_scan,
+ .connect = ar6k_cfg80211_connect,
+ .disconnect = ar6k_cfg80211_disconnect,
+ .add_key = ar6k_cfg80211_add_key,
+ .get_key = ar6k_cfg80211_get_key,
+ .del_key = ar6k_cfg80211_del_key,
+ .set_default_key = ar6k_cfg80211_set_default_key,
+ .set_default_mgmt_key = ar6k_cfg80211_set_default_mgmt_key,
+ .set_wiphy_params = ar6k_cfg80211_set_wiphy_params,
+ .set_bitrate_mask = ar6k_cfg80211_set_bitrate_mask,
+ .set_tx_power = ar6k_cfg80211_set_txpower,
+ .get_tx_power = ar6k_cfg80211_get_txpower,
+ .set_power_mgmt = ar6k_cfg80211_set_power_mgmt,
+ .join_ibss = ar6k_cfg80211_join_ibss,
+ .leave_ibss = ar6k_cfg80211_leave_ibss,
+};
+
+struct wireless_dev *
+ar6k_cfg80211_init(struct device *dev)
+{
+ int ret = 0;
+ struct wireless_dev *wdev;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ wdev = kzalloc(sizeof(struct wireless_dev), GFP_KERNEL);
+ if(!wdev) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: Couldn't allocate wireless device\n", __func__));
+ return ERR_PTR(-ENOMEM);
+ }
+
+ /* create a new wiphy for use with cfg80211 */
+ wdev->wiphy = wiphy_new(&ar6k_cfg80211_ops, sizeof(AR_SOFTC_T));
+ if(!wdev->wiphy) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: Couldn't allocate wiphy device\n", __func__));
+ kfree(wdev);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ /* set device pointer for wiphy */
+ set_wiphy_dev(wdev->wiphy, dev);
+
+ wdev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
+ BIT(NL80211_IFTYPE_ADHOC);
+ /* max num of ssids that can be probed during scanning */
+ wdev->wiphy->max_scan_ssids = MAX_PROBED_SSID_INDEX;
+ wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &ar6k_band_2ghz;
+ wdev->wiphy->bands[IEEE80211_BAND_5GHZ] = &ar6k_band_5ghz;
+ wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
+
+ wdev->wiphy->cipher_suites = cipher_suites;
+ wdev->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites);
+
+ ret = wiphy_register(wdev->wiphy);
+ if(ret < 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("%s: Couldn't register wiphy device\n", __func__));
+ wiphy_free(wdev->wiphy);
+ return ERR_PTR(ret);
+ }
+
+ return wdev;
+}
+
+void
+ar6k_cfg80211_deinit(AR_SOFTC_T *ar)
+{
+ struct wireless_dev *wdev = ar->wdev;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__));
+
+ if(ar->scan_request) {
+ cfg80211_scan_done(ar->scan_request, true);
+ ar->scan_request = NULL;
+ }
+
+ if(!wdev)
+ return;
+
+ wiphy_unregister(wdev->wiphy);
+ wiphy_free(wdev->wiphy);
+ kfree(wdev);
+}
+
+
+
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/eeprom.c b/drivers/net/wireless/ath6kl/os/linux/eeprom.c
new file mode 100644
index 000000000000..1c182751a939
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/eeprom.c
@@ -0,0 +1,581 @@
+/*
+ *
+ * Copyright (c) 2004-2009 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+
+#include "ar6000_drv.h"
+#include "htc.h"
+#include <linux/fs.h>
+
+#include "AR6002/hw2.0/hw/gpio_reg.h"
+#include "AR6002/hw2.0/hw/si_reg.h"
+
+//
+// defines
+//
+
+#define MAX_FILENAME 1023
+#define EEPROM_WAIT_LIMIT 16
+
+#define HOST_INTEREST_ITEM_ADDRESS(item) \
+ (AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+#define EEPROM_SZ 768
+
+/* soft mac */
+#define ATH_MAC_LEN 6
+#define ATH_SOFT_MAC_TMP_BUF_LEN 64
+unsigned char mac_addr[ATH_MAC_LEN];
+unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN];
+char *p_mac = NULL;
+/* soft mac */
+
+//
+// static variables
+//
+
+static A_UCHAR eeprom_data[EEPROM_SZ];
+static A_UINT32 sys_sleep_reg;
+static HIF_DEVICE *p_bmi_device;
+
+//
+// Functions
+//
+
+/* soft mac */
+static int
+wmic_ether_aton(const char *orig, A_UINT8 *eth)
+{
+ const char *bufp;
+ int i;
+
+ i = 0;
+ for(bufp = orig; *bufp != '\0'; ++bufp) {
+ unsigned int val;
+ unsigned char c = *bufp++;
+ if (c >= '0' && c <= '9') val = c - '0';
+ else if (c >= 'a' && c <= 'f') val = c - 'a' + 10;
+ else if (c >= 'A' && c <= 'F') val = c - 'A' + 10;
+ else {
+ printk("%s: MAC value is invalid\n", __FUNCTION__);
+ break;
+ }
+
+ val <<= 4;
+ c = *bufp++;
+ if (c >= '0' && c <= '9') val |= c - '0';
+ else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10;
+ else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10;
+ else {
+ printk("%s: MAC value is invalid\n", __FUNCTION__);
+ break;
+ }
+
+ eth[i] = (unsigned char) (val & 0377);
+ if(++i == ATH_MAC_LEN) {
+ /* That's it. Any trailing junk? */
+ if (*bufp != '\0') {
+ return 0;
+ }
+ return 1;
+ }
+ if (*bufp != ':')
+ break;
+ }
+ return 0;
+}
+
+static void
+update_mac(unsigned char* eeprom, int size, unsigned char* macaddr)
+{
+ int i;
+ A_UINT16* ptr = (A_UINT16*)(eeprom+4);
+ A_UINT16 checksum = 0;
+
+ memcpy(eeprom+10,macaddr,6);
+
+ *ptr = 0;
+ ptr = (A_UINT16*)eeprom;
+
+ for (i=0; i<size; i+=2) {
+ checksum ^= *ptr++;
+ }
+ checksum = ~checksum;
+
+ ptr = (A_UINT16*)(eeprom+4);
+ *ptr = checksum;
+ return;
+}
+/* soft mac */
+
+/* Read a Target register and return its value. */
+inline void
+BMI_read_reg(A_UINT32 address, A_UINT32 *pvalue)
+{
+ BMIReadSOCRegister(p_bmi_device, address, pvalue);
+}
+
+/* Write a value to a Target register. */
+inline void
+BMI_write_reg(A_UINT32 address, A_UINT32 value)
+{
+ BMIWriteSOCRegister(p_bmi_device, address, value);
+}
+
+/* Read Target memory word and return its value. */
+inline void
+BMI_read_mem(A_UINT32 address, A_UINT32 *pvalue)
+{
+ BMIReadMemory(p_bmi_device, address, (A_UCHAR*)(pvalue), 4);
+}
+
+/* Write a word to a Target memory. */
+inline void
+BMI_write_mem(A_UINT32 address, A_UINT8 *p_data, A_UINT32 sz)
+{
+ BMIWriteMemory(p_bmi_device, address, (A_UCHAR*)(p_data), sz);
+}
+
+/*
+ * Enable and configure the Target's Serial Interface
+ * so we can access the EEPROM.
+ */
+static void
+enable_SI(HIF_DEVICE *p_device)
+{
+ A_UINT32 regval;
+
+ printk("%s\n", __FUNCTION__);
+
+ p_bmi_device = p_device;
+
+ BMI_read_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, &sys_sleep_reg);
+ BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, SYSTEM_SLEEP_DISABLE_SET(1)); //disable system sleep temporarily
+
+ BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
+ regval &= ~CLOCK_CONTROL_SI0_CLK_MASK;
+ BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);
+
+ BMI_read_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, &regval);
+ regval &= ~RESET_CONTROL_SI0_RST_MASK;
+ BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, regval);
+
+
+ BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, &regval);
+ regval &= ~GPIO_PIN0_CONFIG_MASK;
+ BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, regval);
+
+ BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, &regval);
+ regval &= ~GPIO_PIN1_CONFIG_MASK;
+ BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, regval);
+
+ /* SI_CONFIG = 0x500a6; */
+ regval = SI_CONFIG_BIDIR_OD_DATA_SET(1) |
+ SI_CONFIG_I2C_SET(1) |
+ SI_CONFIG_POS_SAMPLE_SET(1) |
+ SI_CONFIG_INACTIVE_CLK_SET(1) |
+ SI_CONFIG_INACTIVE_DATA_SET(1) |
+ SI_CONFIG_DIVIDER_SET(6);
+ BMI_write_reg(SI_BASE_ADDRESS+SI_CONFIG_OFFSET, regval);
+
+}
+
+static void
+disable_SI(void)
+{
+ A_UINT32 regval;
+
+ printk("%s\n", __FUNCTION__);
+
+ BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, RESET_CONTROL_SI0_RST_MASK);
+ BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, &regval);
+ regval |= CLOCK_CONTROL_SI0_CLK_MASK;
+ BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);//Gate SI0 clock
+ BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, sys_sleep_reg); //restore system sleep setting
+}
+
+/*
+ * Tell the Target to start an 8-byte read from EEPROM,
+ * putting the results in Target RX_DATA registers.
+ */
+static void
+request_8byte_read(int offset)
+{
+ A_UINT32 regval;
+
+// printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
+
+
+ /* SI_TX_DATA0 = read from offset */
+ regval =(0xa1<<16)|
+ ((offset & 0xff)<<8) |
+ (0xa0 | ((offset & 0xff00)>>7));
+
+ BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
+
+ regval = SI_CS_START_SET(1) |
+ SI_CS_RX_CNT_SET(8) |
+ SI_CS_TX_CNT_SET(3);
+ BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
+}
+
+/*
+ * Tell the Target to start a 4-byte write to EEPROM,
+ * writing values from Target TX_DATA registers.
+ */
+static void
+request_4byte_write(int offset, A_UINT32 data)
+{
+ A_UINT32 regval;
+
+ printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
+
+ /* SI_TX_DATA0 = write data to offset */
+ regval = ((data & 0xffff) <<16) |
+ ((offset & 0xff)<<8) |
+ (0xa0 | ((offset & 0xff00)>>7));
+ BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
+
+ regval = data >> 16;
+ BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval);
+
+ regval = SI_CS_START_SET(1) |
+ SI_CS_RX_CNT_SET(0) |
+ SI_CS_TX_CNT_SET(6);
+ BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
+}
+
+/*
+ * Check whether or not an EEPROM request that was started
+ * earlier has completed yet.
+ */
+static A_BOOL
+request_in_progress(void)
+{
+ A_UINT32 regval;
+
+ /* Wait for DONE_INT in SI_CS */
+ BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
+
+// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval);
+ if (regval & SI_CS_DONE_ERR_MASK) {
+ printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval);
+ }
+
+ return (!(regval & SI_CS_DONE_INT_MASK));
+}
+
+/*
+ * try to detect the type of EEPROM,16bit address or 8bit address
+ */
+
+static void eeprom_type_detect(void)
+{
+ A_UINT32 regval;
+ A_UINT8 i = 0;
+
+ request_8byte_read(0x100);
+ /* Wait for DONE_INT in SI_CS */
+ do{
+ BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, &regval);
+ if (regval & SI_CS_DONE_ERR_MASK) {
+ printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__);
+ break;
+ }
+ if (i++ == EEPROM_WAIT_LIMIT) {
+ printk("%s: EEPROM not responding\n", __FUNCTION__);
+ }
+ } while(!(regval & SI_CS_DONE_INT_MASK));
+}
+
+/*
+ * Extract the results of a completed EEPROM Read request
+ * and return them to the caller.
+ */
+inline void
+read_8byte_results(A_UINT32 *data)
+{
+ /* Read SI_RX_DATA0 and SI_RX_DATA1 */
+ BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
+ BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]);
+}
+
+
+/*
+ * Wait for a previously started command to complete.
+ * Timeout if the command is takes "too long".
+ */
+static void
+wait_for_eeprom_completion(void)
+{
+ int i=0;
+
+ while (request_in_progress()) {
+ if (i++ == EEPROM_WAIT_LIMIT) {
+ printk("%s: EEPROM not responding\n", __FUNCTION__);
+ }
+ }
+}
+
+/*
+ * High-level function which starts an 8-byte read,
+ * waits for it to complete, and returns the result.
+ */
+static void
+fetch_8bytes(int offset, A_UINT32 *data)
+{
+ request_8byte_read(offset);
+ wait_for_eeprom_completion();
+ read_8byte_results(data);
+
+ /* Clear any pending intr */
+ BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK);
+}
+
+/*
+ * High-level function which starts a 4-byte write,
+ * and waits for it to complete.
+ */
+inline void
+commit_4bytes(int offset, A_UINT32 data)
+{
+ request_4byte_write(offset, data);
+ wait_for_eeprom_completion();
+}
+/* ATHENV */
+#ifdef ANDROID_ENV
+void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac)
+{
+ A_UINT32 first_word;
+ A_UINT32 board_data_addr;
+ int i;
+
+ printk("%s: Enter\n", __FUNCTION__);
+
+ enable_SI(device);
+ eeprom_type_detect();
+
+ if (fake_file) {
+ /*
+ * Transfer from file to Target RAM.
+ * Fetch source data from file.
+ */
+ mm_segment_t oldfs;
+ struct file *filp;
+ struct inode *inode = NULL;
+ int length;
+
+ /* open file */
+ oldfs = get_fs();
+ set_fs(KERNEL_DS);
+ filp = filp_open(fake_file, O_RDONLY, S_IRUSR);
+
+ if (IS_ERR(filp)) {
+ printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file);
+ set_fs(oldfs);
+ return;
+ }
+
+ if (!filp->f_op) {
+ printk("%s: File Operation Method Error\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ inode = filp->f_path.dentry->d_inode;
+#else
+ inode = filp->f_dentry->d_inode;
+#endif
+
+ if (!inode) {
+ printk("%s: Get inode from filp failed\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+ printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
+
+ /* file's size */
+ length = i_size_read(inode->i_mapping->host);
+ printk("%s: length=%d\n", __FUNCTION__, length);
+ if (length != EEPROM_SZ) {
+ printk("%s: The file's size is not as expected\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+ /* read data */
+ if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) {
+ printk("%s: file read error\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+ /* read data out successfully */
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ } else {
+ /*
+ * Read from EEPROM to file OR transfer from EEPROM to Target RAM.
+ * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
+ */
+
+ fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0]));
+
+ /* Check the first word of EEPROM for validity */
+ first_word = *((A_UINT32 *)eeprom_data);
+
+ if ((first_word == 0) || (first_word == 0xffffffff)) {
+ printk("Did not find EEPROM with valid Board Data.\n");
+ }
+
+ for (i=8; i<EEPROM_SZ; i+=8) {
+ fetch_8bytes(i, (A_UINT32 *)(&eeprom_data[i]));
+ }
+ }
+
+ /* soft mac */
+ if (p_mac) {
+
+ mm_segment_t oldfs;
+ struct file *filp;
+ struct inode *inode = NULL;
+ int length;
+
+ /* open file */
+ oldfs = get_fs();
+ set_fs(KERNEL_DS);
+ filp = filp_open(p_mac, O_RDONLY, S_IRUSR);
+
+ printk("%s try to open file %s\n", __FUNCTION__, p_mac);
+
+ if (IS_ERR(filp)) {
+ printk("%s: file %s filp_open error\n", __FUNCTION__, p_mac);
+ set_fs(oldfs);
+ return;
+ }
+
+ if (!filp->f_op) {
+ printk("%s: File Operation Method Error\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+ inode = filp->f_path.dentry->d_inode;
+#else
+ inode = filp->f_dentry->d_inode;
+#endif
+ if (!inode) {
+ printk("%s: Get inode from filp failed\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+ printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
+
+ /* file's size */
+ length = i_size_read(inode->i_mapping->host);
+ printk("%s: length=%d\n", __FUNCTION__, length);
+ if (length > ATH_SOFT_MAC_TMP_BUF_LEN) {
+ printk("%s: MAC file's size is not as expected\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+ /* read data */
+ if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) {
+ printk("%s: file read error\n", __FUNCTION__);
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+ return;
+ }
+
+#if 0
+ /* the data we just read */
+ printk("%s: mac address from the file:\n", __FUNCTION__);
+ for (i = 0; i < length; i++)
+ printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]);
+ printk("\n");
+#endif
+
+ /* read data out successfully */
+ filp_close(filp, NULL);
+ set_fs(oldfs);
+
+ /* convert mac address */
+ if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) {
+ printk("%s: convert mac value fail\n", __FUNCTION__);
+ return;
+ }
+
+#if 0
+ /* the converted mac address */
+ printk("%s: the converted mac value\n", __FUNCTION__);
+ for (i = 0; i < ATH_MAC_LEN; i++)
+ printk("[0x%x],", mac_addr[i]);
+ printk("\n");
+#endif
+ }
+ /* soft mac */
+
+ /* Determine where in Target RAM to write Board Data */
+ BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr);
+ if (board_data_addr == 0) {
+ printk("hi_board_data is zero\n");
+ }
+
+ /* soft mac */
+#if 1
+ /* Update MAC address in RAM */
+ if (p_mac) {
+ update_mac(eeprom_data, EEPROM_SZ, mac_addr);
+ }
+#endif
+#if 0
+ /* mac address in eeprom array */
+ printk("%s: mac values in eeprom array\n", __FUNCTION__);
+ for (i = 10; i < 10 + 6; i++)
+ printk("[0x%x],", eeprom_data[i]);
+ printk("\n");
+#endif
+ /* soft mac */
+
+ /* Write EEPROM data to Target RAM */
+ BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ);
+
+ /* Record the fact that Board Data IS initialized */
+ {
+ A_UINT32 one = 1;
+ BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
+ (A_UINT8 *)&one, sizeof(A_UINT32));
+ }
+
+ disable_SI();
+}
+#endif
+/* ATHENV */
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c b/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c
new file mode 100644
index 000000000000..29b7fac80949
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c
@@ -0,0 +1,119 @@
+//------------------------------------------------------------------------------
+// <copyright file="hci_bridge.c" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "a_drv.h"
+#include "hif.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#include "hci_transport_api.h"
+
+#include "AR6002/hw4.0/hw/apb_athr_wlan_map.h"
+#include "AR6002/hw4.0/hw/uart_reg.h"
+#include "AR6002/hw4.0/hw/rtc_wlan_reg.h"
+
+HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+A_STATUS (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+void (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans);
+A_STATUS (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+A_STATUS (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans,
+ HTC_PACKET *pPacket,
+ int MaxPollMS);
+A_STATUS (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+extern HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks;
+
+A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks)
+{
+ ar6kHciTransCallbacks = *hciTransCallbacks;
+
+ _HCI_TransportAttach = HCI_TransportAttach;
+ _HCI_TransportDetach = HCI_TransportDetach;
+ _HCI_TransportAddReceivePkts = HCI_TransportAddReceivePkts;
+ _HCI_TransportSendPkt = HCI_TransportSendPkt;
+ _HCI_TransportStop = HCI_TransportStop;
+ _HCI_TransportStart = HCI_TransportStart;
+ _HCI_TransportEnableDisableAsyncRecv = HCI_TransportEnableDisableAsyncRecv;
+ _HCI_TransportRecvHCIEventSync = HCI_TransportRecvHCIEventSync;
+ _HCI_TransportSetBaudRate = HCI_TransportSetBaudRate;
+
+ return A_OK;
+}
+
+A_STATUS
+ar6000_get_hif_dev(HIF_DEVICE *device, void *config)
+{
+ A_STATUS status;
+
+ status = HIFConfigureDevice(device,
+ HIF_DEVICE_GET_OS_DEVICE,
+ (HIF_DEVICE_OS_DEVICE_INFO *)config,
+ sizeof(HIF_DEVICE_OS_DEVICE_INFO));
+ return status;
+}
+
+A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice,
+ A_UINT32 scale,
+ A_UINT32 step)
+{
+ A_UINT32 regAddress;
+ A_UINT32 regVal;
+ A_STATUS status;
+
+ regAddress = WLAN_UART_BASE_ADDRESS | UART_CLKDIV_ADDRESS;
+ regVal = ((A_UINT32)scale << 16) | step;
+ /* change the HCI UART scale/step values through the diagnostic window */
+ status = ar6000_WriteRegDiag(hifDevice, &regAddress, &regVal);
+
+ return status;
+}
+
+A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data)
+{
+ A_UINT32 regAddress;
+ A_STATUS status;
+
+ regAddress = WLAN_RTC_BASE_ADDRESS | WLAN_CPU_CLOCK_ADDRESS;
+ /* read CPU clock settings*/
+ status = ar6000_ReadRegDiag(hifDevice, &regAddress, data);
+
+ return status;
+}
+
+EXPORT_SYMBOL(ar6000_register_hci_transport);
+EXPORT_SYMBOL(ar6000_get_hif_dev);
+EXPORT_SYMBOL(ar6000_set_uart_config);
+EXPORT_SYMBOL(ar6000_get_core_clock_config);
+EXPORT_SYMBOL(_HCI_TransportAttach);
+EXPORT_SYMBOL(_HCI_TransportDetach);
+EXPORT_SYMBOL(_HCI_TransportAddReceivePkts);
+EXPORT_SYMBOL(_HCI_TransportSendPkt);
+EXPORT_SYMBOL(_HCI_TransportStop);
+EXPORT_SYMBOL(_HCI_TransportStart);
+EXPORT_SYMBOL(_HCI_TransportEnableDisableAsyncRecv);
+EXPORT_SYMBOL(_HCI_TransportRecvHCIEventSync);
+EXPORT_SYMBOL(_HCI_TransportSetBaudRate);
diff --git a/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c b/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c
new file mode 100644
index 000000000000..3cbf5849e8fb
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c
@@ -0,0 +1,1126 @@
+//------------------------------------------------------------------------------
+// <copyright file="hci_bridge.c" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include <linux/etherdevice.h>
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "hif.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#define ATH_DEBUG_HCI_BRIDGE ATH_DEBUG_MAKE_MODULE_MASK(6)
+#define ATH_DEBUG_HCI_RECV ATH_DEBUG_MAKE_MODULE_MASK(7)
+#define ATH_DEBUG_HCI_SEND ATH_DEBUG_MAKE_MODULE_MASK(8)
+#define ATH_DEBUG_HCI_DUMP ATH_DEBUG_MAKE_MODULE_MASK(9)
+#else
+#include "ar6000_drv.h"
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+#ifdef ATH_AR6K_ENABLE_GMBOX
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+#include "export_hci_transport.h"
+#else
+#include "hci_transport_api.h"
+#endif
+#include "epping_test.h"
+#include "gmboxif.h"
+#include "ar3kconfig.h"
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
+ /* only build on newer kernels which have BT configured */
+#if defined(CONFIG_BT_MODULE) || defined(CONFIG_BT)
+#define CONFIG_BLUEZ_HCI_BRIDGE
+#endif
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+unsigned int ar3khcibaud = 0;
+unsigned int hciuartscale = 0;
+unsigned int hciuartstep = 0;
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(ar3khcibaud, int, 0644);
+module_param(hciuartscale, int, 0644);
+module_param(hciuartstep, int, 0644);
+#else
+
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(ar3khcibaud, "i");
+MODULE_PARM(hciuartscale, "i");
+MODULE_PARM(hciuartstep, "i");
+#endif
+#else
+extern unsigned int ar3khcibaud;
+extern unsigned int hciuartscale;
+extern unsigned int hciuartstep;
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+typedef struct {
+ void *pHCIDev; /* HCI bridge device */
+ HCI_TRANSPORT_PROPERTIES HCIProps; /* HCI bridge props */
+ struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */
+ A_BOOL HciNormalMode; /* Actual HCI mode enabled (non-TEST)*/
+ A_BOOL HciRegistered; /* HCI device registered with stack */
+ HTC_PACKET_QUEUE HTCPacketStructHead;
+ A_UINT8 *pHTCStructAlloc;
+ spinlock_t BridgeLock;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ HCI_TRANSPORT_MISC_HANDLES HCITransHdl;
+#else
+ AR_SOFTC_T *ar;
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+} AR6K_HCI_BRIDGE_INFO;
+
+#define MAX_ACL_RECV_BUFS 16
+#define MAX_EVT_RECV_BUFS 8
+#define MAX_HCI_WRITE_QUEUE_DEPTH 32
+#define MAX_ACL_RECV_LENGTH 1200
+#define MAX_EVT_RECV_LENGTH 257
+#define TX_PACKET_RSV_OFFSET 32
+#define NUM_HTC_PACKET_STRUCTS ((MAX_ACL_RECV_BUFS + MAX_EVT_RECV_BUFS + MAX_HCI_WRITE_QUEUE_DEPTH) * 2)
+
+#define HCI_GET_OP_CODE(p) (((A_UINT16)((p)[1])) << 8) | ((A_UINT16)((p)[0]))
+
+extern unsigned int setupbtdev;
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+AR6K_HCI_BRIDGE_INFO *g_pHcidevInfo;
+#endif
+
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo);
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO *pHcidevInfo,
+ HCI_TRANSPORT_PACKET_TYPE Type,
+ struct sk_buff *skb);
+static struct sk_buff *bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length);
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb);
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar);
+void ar6000_cleanup_hci(void *ar);
+A_STATUS hci_test_send(void *ar, struct sk_buff *skb);
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar);
+void ar6000_cleanup_hci(AR_SOFTC_T *ar);
+/* HCI bridge testing */
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb);
+#endif /* EXPORT_HCI_BRIDGE_INTERFACE */
+
+#define LOCK_BRIDGE(dev) spin_lock_bh(&(dev)->BridgeLock)
+#define UNLOCK_BRIDGE(dev) spin_unlock_bh(&(dev)->BridgeLock)
+
+static inline void FreeBtOsBuf(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, void *osbuf)
+{
+ if (pHcidevInfo->HciNormalMode) {
+ bt_free_buffer(pHcidevInfo, (struct sk_buff *)osbuf);
+ } else {
+ /* in test mode, these are just ordinary netbuf allocations */
+ A_NETBUF_FREE(osbuf);
+ }
+}
+
+static void FreeHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, HTC_PACKET *pPacket)
+{
+ LOCK_BRIDGE(pHcidevInfo);
+ HTC_PACKET_ENQUEUE(&pHcidevInfo->HTCPacketStructHead,pPacket);
+ UNLOCK_BRIDGE(pHcidevInfo);
+}
+
+static HTC_PACKET * AllocHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+ HTC_PACKET *pPacket = NULL;
+ LOCK_BRIDGE(pHcidevInfo);
+ pPacket = HTC_PACKET_DEQUEUE(&pHcidevInfo->HTCPacketStructHead);
+ UNLOCK_BRIDGE(pHcidevInfo);
+ return pPacket;
+}
+
+#define BLOCK_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1))
+
+static void RefillRecvBuffers(AR6K_HCI_BRIDGE_INFO *pHcidevInfo,
+ HCI_TRANSPORT_PACKET_TYPE Type,
+ int NumBuffers)
+{
+ int length, i;
+ void *osBuf = NULL;
+ HTC_PACKET_QUEUE queue;
+ HTC_PACKET *pPacket;
+
+ INIT_HTC_PACKET_QUEUE(&queue);
+
+ if (Type == HCI_ACL_TYPE) {
+ if (pHcidevInfo->HciNormalMode) {
+ length = HCI_MAX_FRAME_SIZE;
+ } else {
+ length = MAX_ACL_RECV_LENGTH;
+ }
+ } else {
+ length = MAX_EVT_RECV_LENGTH;
+ }
+
+ /* add on transport head and tail room */
+ length += pHcidevInfo->HCIProps.HeadRoom + pHcidevInfo->HCIProps.TailRoom;
+ /* round up to the required I/O padding */
+ length = BLOCK_ROUND_UP_PWR2(length,pHcidevInfo->HCIProps.IOBlockPad);
+
+ for (i = 0; i < NumBuffers; i++) {
+
+ if (pHcidevInfo->HciNormalMode) {
+ osBuf = bt_alloc_buffer(pHcidevInfo,length);
+ } else {
+ osBuf = A_NETBUF_ALLOC(length);
+ }
+
+ if (NULL == osBuf) {
+ break;
+ }
+
+ pPacket = AllocHTCStruct(pHcidevInfo);
+ if (NULL == pPacket) {
+ FreeBtOsBuf(pHcidevInfo,osBuf);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n"));
+ break;
+ }
+
+ SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),length,Type);
+ /* add to queue */
+ HTC_PACKET_ENQUEUE(&queue,pPacket);
+ }
+
+ if (i > 0) {
+ HCI_TransportAddReceivePkts(pHcidevInfo->pHCIDev, &queue);
+ }
+}
+
+static A_STATUS ar6000_hci_transport_ready(HCI_TRANSPORT_HANDLE HCIHandle,
+ HCI_TRANSPORT_PROPERTIES *pProps,
+ void *pContext)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+ A_STATUS status;
+ AR3K_CONFIG_INFO ar3kconfig;
+
+ pHcidevInfo->pHCIDev = HCIHandle;
+
+ A_MEMCPY(&pHcidevInfo->HCIProps,pProps,sizeof(*pProps));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE,("HCI ready (hci:0x%X, headroom:%d, tailroom:%d blockpad:%d) \n",
+ (A_UINT32)HCIHandle,
+ pHcidevInfo->HCIProps.HeadRoom,
+ pHcidevInfo->HCIProps.TailRoom,
+ pHcidevInfo->HCIProps.IOBlockPad));
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice)->hard_header_len);
+#else
+ A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= pHcidevInfo->ar->arNetDev->hard_header_len);
+#endif
+
+ /* provide buffers */
+ RefillRecvBuffers(pHcidevInfo, HCI_ACL_TYPE, MAX_ACL_RECV_BUFS);
+ RefillRecvBuffers(pHcidevInfo, HCI_EVENT_TYPE, MAX_EVT_RECV_BUFS);
+
+ do {
+ /* start transport */
+ status = HCI_TransportStart(pHcidevInfo->pHCIDev);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (!pHcidevInfo->HciNormalMode) {
+ /* in test mode, no need to go any further */
+ break;
+ }
+
+ // The delay is required when AR6K is driving the BT reset line
+ // where time is needed after the BT chip is out of reset (HCI_TransportStart)
+ // and before the first HCI command is issued (AR3KConfigure)
+ // FIXME
+ // The delay should be configurable and be only applied when AR6K driving the BT
+ // reset line. This could be done by some module parameter or based on some HW config
+ // info. For now apply 100ms delay blindly
+ A_MDELAY(100);
+
+ A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig));
+ ar3kconfig.pHCIDev = pHcidevInfo->pHCIDev;
+ ar3kconfig.pHCIProps = &pHcidevInfo->HCIProps;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ ar3kconfig.pHIFDevice = (HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice);
+#else
+ ar3kconfig.pHIFDevice = pHcidevInfo->ar->arHifDevice;
+#endif
+ ar3kconfig.pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev;
+
+ if (ar3khcibaud != 0) {
+ /* user wants ar3k baud rate change */
+ ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD;
+ ar3kconfig.Flags |= AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY;
+ ar3kconfig.AR3KBaudRate = ar3khcibaud;
+ }
+
+ if ((hciuartscale != 0) || (hciuartstep != 0)) {
+ /* user wants to tune HCI bridge UART scale/step values */
+ ar3kconfig.AR6KScale = (A_UINT16)hciuartscale;
+ ar3kconfig.AR6KStep = (A_UINT16)hciuartstep;
+ ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP;
+ }
+
+ /* configure the AR3K device */
+ status = AR3KConfigure(&ar3kconfig);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ status = bt_register_hci(pHcidevInfo);
+
+ } while (FALSE);
+
+ return status;
+}
+
+static void ar6000_hci_transport_failure(void *pContext, A_STATUS Status)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: transport failure! \n"));
+
+ if (pHcidevInfo->HciNormalMode) {
+ /* TODO .. */
+ }
+}
+
+static void ar6000_hci_transport_removed(void *pContext)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: transport removed. \n"));
+
+ A_ASSERT(pHcidevInfo->pHCIDev != NULL);
+
+ HCI_TransportDetach(pHcidevInfo->pHCIDev);
+ bt_cleanup_hci(pHcidevInfo);
+ pHcidevInfo->pHCIDev = NULL;
+}
+
+static void ar6000_hci_send_complete(void *pContext, HTC_PACKET *pPacket)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+ void *osbuf = pPacket->pPktContext;
+ A_ASSERT(osbuf != NULL);
+ A_ASSERT(pHcidevInfo != NULL);
+
+ if (A_FAILED(pPacket->Status)) {
+ if ((pPacket->Status != A_ECANCELED) && (pPacket->Status != A_NO_RESOURCE)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: Send Packet Failed: %d \n",pPacket->Status));
+ }
+ }
+
+ FreeHTCStruct(pHcidevInfo,pPacket);
+ FreeBtOsBuf(pHcidevInfo,osbuf);
+
+}
+
+static void ar6000_hci_pkt_recv(void *pContext, HTC_PACKET *pPacket)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+ struct sk_buff *skb;
+
+ A_ASSERT(pHcidevInfo != NULL);
+ skb = (struct sk_buff *)pPacket->pPktContext;
+ A_ASSERT(skb != NULL);
+
+ do {
+
+ if (A_FAILED(pPacket->Status)) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV,
+ ("HCI Bridge, packet received type : %d len:%d \n",
+ HCI_GET_PACKET_TYPE(pPacket),pPacket->ActualLength));
+
+ /* set the actual buffer position in the os buffer, HTC recv buffers posted to HCI are set
+ * to fill the front of the buffer */
+ A_NETBUF_PUT(skb,pPacket->ActualLength + pHcidevInfo->HCIProps.HeadRoom);
+ A_NETBUF_PULL(skb,pHcidevInfo->HCIProps.HeadRoom);
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("<<< Recv HCI %s packet len:%d \n",
+ (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) ? "EVENT" : "ACL",
+ skb->len));
+ AR_DEBUG_PRINTBUF(skb->data, skb->len,"BT HCI RECV Packet Dump");
+ }
+
+ if (pHcidevInfo->HciNormalMode) {
+ /* indicate the packet */
+ if (bt_indicate_recv(pHcidevInfo,HCI_GET_PACKET_TYPE(pPacket),skb)) {
+ /* bt stack accepted the packet */
+ skb = NULL;
+ }
+ break;
+ }
+
+ /* for testing, indicate packet to the network stack */
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ skb->dev = (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice);
+ if ((((struct net_device *)pHcidevInfo->HCITransHdl.netDevice)->flags & IFF_UP) == IFF_UP) {
+ skb->protocol = eth_type_trans(skb, (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice));
+#else
+ skb->dev = pHcidevInfo->ar->arNetDev;
+ if ((pHcidevInfo->ar->arNetDev->flags & IFF_UP) == IFF_UP) {
+ skb->protocol = eth_type_trans(skb, pHcidevInfo->ar->arNetDev);
+#endif
+ netif_rx(skb);
+ skb = NULL;
+ }
+
+ } while (FALSE);
+
+ FreeHTCStruct(pHcidevInfo,pPacket);
+
+ if (skb != NULL) {
+ /* packet was not accepted, free it */
+ FreeBtOsBuf(pHcidevInfo,skb);
+ }
+
+}
+
+static void ar6000_hci_pkt_refill(void *pContext, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+ int refillCount;
+
+ if (Type == HCI_ACL_TYPE) {
+ refillCount = MAX_ACL_RECV_BUFS - BuffersAvailable;
+ } else {
+ refillCount = MAX_EVT_RECV_BUFS - BuffersAvailable;
+ }
+
+ if (refillCount > 0) {
+ RefillRecvBuffers(pHcidevInfo,Type,refillCount);
+ }
+
+}
+
+static HCI_SEND_FULL_ACTION ar6000_hci_pkt_send_full(void *pContext, HTC_PACKET *pPacket)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext;
+ HCI_SEND_FULL_ACTION action = HCI_SEND_FULL_KEEP;
+
+ if (!pHcidevInfo->HciNormalMode) {
+ /* for epping testing, check packet tag, some epping packets are
+ * special and cannot be dropped */
+ if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_DATA_PKT_TAG) {
+ action = HCI_SEND_FULL_DROP;
+ }
+ }
+
+ return action;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar)
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar)
+#endif
+{
+ HCI_TRANSPORT_CONFIG_INFO config;
+ A_STATUS status = A_OK;
+ int i;
+ HTC_PACKET *pPacket;
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo;
+
+
+ do {
+
+ pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)A_MALLOC(sizeof(AR6K_HCI_BRIDGE_INFO));
+
+ if (NULL == pHcidevInfo) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ A_MEMZERO(pHcidevInfo, sizeof(AR6K_HCI_BRIDGE_INFO));
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ g_pHcidevInfo = pHcidevInfo;
+ pHcidevInfo->HCITransHdl = *(HCI_TRANSPORT_MISC_HANDLES *)ar;
+#else
+ ar->hcidev_info = pHcidevInfo;
+ pHcidevInfo->ar = ar;
+#endif
+ spin_lock_init(&pHcidevInfo->BridgeLock);
+ INIT_HTC_PACKET_QUEUE(&pHcidevInfo->HTCPacketStructHead);
+
+ ar->exitCallback = AR3KConfigureExit;
+
+ status = bt_setup_hci(pHcidevInfo);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (pHcidevInfo->HciNormalMode) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in normal mode... \n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in test mode... \n"));
+ }
+
+ pHcidevInfo->pHTCStructAlloc = (A_UINT8 *)A_MALLOC((sizeof(HTC_PACKET)) * NUM_HTC_PACKET_STRUCTS);
+
+ if (NULL == pHcidevInfo->pHTCStructAlloc) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ pPacket = (HTC_PACKET *)pHcidevInfo->pHTCStructAlloc;
+ for (i = 0; i < NUM_HTC_PACKET_STRUCTS; i++,pPacket++) {
+ FreeHTCStruct(pHcidevInfo,pPacket);
+ }
+
+ A_MEMZERO(&config,sizeof(HCI_TRANSPORT_CONFIG_INFO));
+ config.ACLRecvBufferWaterMark = MAX_ACL_RECV_BUFS / 2;
+ config.EventRecvBufferWaterMark = MAX_EVT_RECV_BUFS / 2;
+ config.MaxSendQueueDepth = MAX_HCI_WRITE_QUEUE_DEPTH;
+ config.pContext = pHcidevInfo;
+ config.TransportFailure = ar6000_hci_transport_failure;
+ config.TransportReady = ar6000_hci_transport_ready;
+ config.TransportRemoved = ar6000_hci_transport_removed;
+ config.pHCISendComplete = ar6000_hci_send_complete;
+ config.pHCIPktRecv = ar6000_hci_pkt_recv;
+ config.pHCIPktRecvRefill = ar6000_hci_pkt_refill;
+ config.pHCISendFull = ar6000_hci_pkt_send_full;
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ pHcidevInfo->pHCIDev = HCI_TransportAttach(pHcidevInfo->HCITransHdl.htcHandle, &config);
+#else
+ pHcidevInfo->pHCIDev = HCI_TransportAttach(ar->arHtcTarget, &config);
+#endif
+
+ if (NULL == pHcidevInfo->pHCIDev) {
+ status = A_ERROR;
+ }
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ if (pHcidevInfo != NULL) {
+ if (NULL == pHcidevInfo->pHCIDev) {
+ /* GMBOX may not be present in older chips */
+ /* just return success */
+ status = A_OK;
+ }
+ }
+ ar6000_cleanup_hci(ar);
+ }
+
+ return status;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_cleanup_hci(void *ar)
+#else
+void ar6000_cleanup_hci(AR_SOFTC_T *ar)
+#endif
+{
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo;
+#else
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+#endif
+
+ if (pHcidevInfo != NULL) {
+ bt_cleanup_hci(pHcidevInfo);
+
+ if (pHcidevInfo->pHCIDev != NULL) {
+ HCI_TransportStop(pHcidevInfo->pHCIDev);
+ HCI_TransportDetach(pHcidevInfo->pHCIDev);
+ pHcidevInfo->pHCIDev = NULL;
+ }
+
+ if (pHcidevInfo->pHTCStructAlloc != NULL) {
+ A_FREE(pHcidevInfo->pHTCStructAlloc);
+ pHcidevInfo->pHTCStructAlloc = NULL;
+ }
+
+ A_FREE(pHcidevInfo);
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+ ar->hcidev_info = NULL;
+#endif
+ }
+
+
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS hci_test_send(void *ar, struct sk_buff *skb)
+#else
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb)
+#endif
+{
+ int status = A_OK;
+ int length;
+ EPPING_HEADER *pHeader;
+ HTC_PACKET *pPacket;
+ HTC_TX_TAG htc_tag = AR6K_DATA_PKT_TAG;
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo;
+#else
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+#endif
+
+ do {
+
+ if (NULL == pHcidevInfo) {
+ status = A_ERROR;
+ break;
+ }
+
+ if (NULL == pHcidevInfo->pHCIDev) {
+ status = A_ERROR;
+ break;
+ }
+
+ if (pHcidevInfo->HciNormalMode) {
+ /* this interface cannot run when normal WMI is running */
+ status = A_ERROR;
+ break;
+ }
+
+ pHeader = (EPPING_HEADER *)A_NETBUF_DATA(skb);
+
+ if (!IS_EPPING_PACKET(pHeader)) {
+ status = A_EINVAL;
+ break;
+ }
+
+ if (IS_EPING_PACKET_NO_DROP(pHeader)) {
+ htc_tag = AR6K_CONTROL_PKT_TAG;
+ }
+
+ length = sizeof(EPPING_HEADER) + pHeader->DataLength;
+
+ pPacket = AllocHTCStruct(pHcidevInfo);
+ if (NULL == pPacket) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ SET_HTC_PACKET_INFO_TX(pPacket,
+ skb,
+ A_NETBUF_DATA(skb),
+ length,
+ HCI_ACL_TYPE, /* send every thing out as ACL */
+ htc_tag);
+
+ HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE);
+ pPacket = NULL;
+
+ } while (FALSE);
+
+ return status;
+}
+
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info;
+ AR3K_CONFIG_INFO *config = (AR3K_CONFIG_INFO *)ar3kconfig;
+
+ config->pHCIDev = pHcidevInfo->pHCIDev;
+ config->pHCIProps = &pHcidevInfo->HCIProps;
+ config->pHIFDevice = ar->arHifDevice;
+ config->pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev;
+ config->Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD;
+ config->AR3KBaudRate = 115200;
+}
+
+#ifdef CONFIG_BLUEZ_HCI_BRIDGE
+/*** BT Stack Entrypoints *******/
+
+/*
+ * bt_open - open a handle to the device
+*/
+static int bt_open(struct hci_dev *hdev)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_open - enter - x\n"));
+ set_bit(HCI_RUNNING, &hdev->flags);
+ set_bit(HCI_UP, &hdev->flags);
+ set_bit(HCI_INIT, &hdev->flags);
+ return 0;
+}
+
+/*
+ * bt_close - close handle to the device
+*/
+static int bt_close(struct hci_dev *hdev)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_close - enter\n"));
+ clear_bit(HCI_RUNNING, &hdev->flags);
+ return 0;
+}
+
+/*
+ * bt_send_frame - send data frames
+*/
+static int bt_send_frame(struct sk_buff *skb)
+{
+ struct hci_dev *hdev = (struct hci_dev *)skb->dev;
+ HCI_TRANSPORT_PACKET_TYPE type;
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo;
+ A_UINT8 *pTemp;
+ HTC_PACKET *pPacket;
+ A_STATUS status = A_OK;
+ struct sk_buff *txSkb = NULL;
+
+ if (!hdev) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_send_frame - no device\n"));
+ return -ENODEV;
+ }
+
+ if (!test_bit(HCI_RUNNING, &hdev->flags)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_send_frame - not open\n"));
+ return -EBUSY;
+ }
+
+ pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data;
+ A_ASSERT(pHcidevInfo != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("+bt_send_frame type: %d \n",bt_cb(skb)->pkt_type));
+ type = HCI_COMMAND_TYPE;
+
+ switch (bt_cb(skb)->pkt_type) {
+ case HCI_COMMAND_PKT:
+ type = HCI_COMMAND_TYPE;
+ hdev->stat.cmd_tx++;
+ break;
+
+ case HCI_ACLDATA_PKT:
+ type = HCI_ACL_TYPE;
+ hdev->stat.acl_tx++;
+ break;
+
+ case HCI_SCODATA_PKT:
+ /* we don't support SCO over the bridge */
+ kfree_skb(skb);
+ return 0;
+ default:
+ A_ASSERT(FALSE);
+ kfree_skb(skb);
+ return 0;
+ }
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(">>> Send HCI %s packet len: %d\n",
+ (type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL",
+ skb->len));
+ if (type == HCI_COMMAND_TYPE) {
+ A_UINT16 opcode = HCI_GET_OP_CODE(skb->data);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" HCI Command: OGF:0x%X OCF:0x%X \r\n",
+ opcode >> 10, opcode & 0x3FF));
+ }
+ AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump");
+ }
+
+ do {
+
+ txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom +
+ pHcidevInfo->HCIProps.TailRoom + skb->len,
+ GFP_ATOMIC);
+
+ if (txSkb == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type;
+ txSkb->dev = (void *)pHcidevInfo->pBtStackHCIDev;
+ skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom);
+ A_MEMCPY(txSkb->data, skb->data, skb->len);
+ skb_put(txSkb,skb->len);
+
+ /* push on header transport space */
+ pTemp = (A_UINT8 *)skb_push(txSkb, pHcidevInfo->HCIProps.HeadRoom);
+ pPacket = AllocHTCStruct(pHcidevInfo);
+ if (NULL == pPacket) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ SET_HTC_PACKET_INFO_TX(pPacket,
+ txSkb,
+ pTemp + pHcidevInfo->HCIProps.HeadRoom,
+ txSkb->len,
+ type,
+ AR6K_CONTROL_PKT_TAG); /* HCI packets cannot be dropped */
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: bt_send_frame skb:0x%X \n",(A_UINT32)txSkb));
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: type:%d, Total Length:%d Bytes \n",
+ type, txSkb->len));
+
+ status = HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE);
+ pPacket = NULL;
+ txSkb = NULL;
+
+ } while (FALSE);
+
+ if (txSkb != NULL) {
+ kfree_skb(txSkb);
+ }
+
+ kfree_skb(skb);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("-bt_send_frame \n"));
+ return 0;
+}
+
+/*
+ * bt_ioctl - ioctl processing
+*/
+static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_ioctl - enter\n"));
+ return -ENOIOCTLCMD;
+}
+
+/*
+ * bt_flush - flush outstandingbpackets
+*/
+static int bt_flush(struct hci_dev *hdev)
+{
+ AR6K_HCI_BRIDGE_INFO *pHcidevInfo;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_flush - enter\n"));
+
+ pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data;
+
+ /* TODO??? */
+
+ return 0;
+}
+
+
+/*
+ * bt_destruct -
+*/
+static void bt_destruct(struct hci_dev *hdev)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_destruct - enter\n"));
+ /* nothing to do here */
+}
+
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+ A_STATUS status = A_OK;
+ struct hci_dev *pHciDev = NULL;
+ HIF_DEVICE_OS_DEVICE_INFO osDevInfo;
+
+ if (!setupbtdev) {
+ return A_OK;
+ }
+
+ do {
+
+ A_MEMZERO(&osDevInfo,sizeof(osDevInfo));
+ /* get the underlying OS device */
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+ status = ar6000_get_hif_dev((HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice),
+ &osDevInfo);
+#else
+ status = HIFConfigureDevice(pHcidevInfo->ar->arHifDevice,
+ HIF_DEVICE_GET_OS_DEVICE,
+ &osDevInfo,
+ sizeof(osDevInfo));
+#endif
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to OS device info from HIF\n"));
+ break;
+ }
+
+ /* allocate a BT HCI struct for this device */
+ pHciDev = hci_alloc_dev();
+ if (NULL == pHciDev) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge - failed to allocate bt struct \n"));
+ status = A_NO_MEMORY;
+ break;
+ }
+ /* save the device, we'll register this later */
+ pHcidevInfo->pBtStackHCIDev = pHciDev;
+ SET_HCIDEV_DEV(pHciDev,osDevInfo.pOSDevice);
+ pHciDev->type = HCI_VIRTUAL;
+ pHciDev->driver_data = pHcidevInfo;
+ pHciDev->open = bt_open;
+ pHciDev->close = bt_close;
+ pHciDev->send = bt_send_frame;
+ pHciDev->ioctl = bt_ioctl;
+ pHciDev->flush = bt_flush;
+ pHciDev->destruct = bt_destruct;
+ pHciDev->owner = THIS_MODULE;
+ /* driver is running in normal BT mode */
+ pHcidevInfo->HciNormalMode = TRUE;
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ bt_cleanup_hci(pHcidevInfo);
+ }
+
+ return status;
+}
+
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+ int err;
+
+ if (pHcidevInfo->HciRegistered) {
+ pHcidevInfo->HciRegistered = FALSE;
+ clear_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags);
+ clear_bit(HCI_UP, &pHcidevInfo->pBtStackHCIDev->flags);
+ clear_bit(HCI_INIT, &pHcidevInfo->pBtStackHCIDev->flags);
+ A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL);
+ /* unregister */
+ if ((err = hci_unregister_dev(pHcidevInfo->pBtStackHCIDev)) < 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to unregister with bluetooth %d\n",err));
+ }
+ }
+
+ if (pHcidevInfo->pBtStackHCIDev != NULL) {
+ kfree(pHcidevInfo->pBtStackHCIDev);
+ pHcidevInfo->pBtStackHCIDev = NULL;
+ }
+}
+
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+ int err;
+ A_STATUS status = A_OK;
+
+ do {
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: registering HCI... \n"));
+ A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL);
+ /* mark that we are registered */
+ pHcidevInfo->HciRegistered = TRUE;
+ if ((err = hci_register_dev(pHcidevInfo->pBtStackHCIDev)) < 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to register with bluetooth %d\n",err));
+ pHcidevInfo->HciRegistered = FALSE;
+ status = A_ERROR;
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: HCI registered \n"));
+
+ } while (FALSE);
+
+ return status;
+}
+
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO *pHcidevInfo,
+ HCI_TRANSPORT_PACKET_TYPE Type,
+ struct sk_buff *skb)
+{
+ A_UINT8 btType;
+ int len;
+ A_BOOL success = FALSE;
+ BT_HCI_EVENT_HEADER *pEvent;
+
+ do {
+
+ if (!test_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_indicate_recv - not running\n"));
+ break;
+ }
+
+ switch (Type) {
+ case HCI_ACL_TYPE:
+ btType = HCI_ACLDATA_PKT;
+ break;
+ case HCI_EVENT_TYPE:
+ btType = HCI_EVENT_PKT;
+ break;
+ default:
+ btType = 0;
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ if (0 == btType) {
+ break;
+ }
+
+ /* set the final type */
+ bt_cb(skb)->pkt_type = btType;
+ /* set dev */
+ skb->dev = (void *)pHcidevInfo->pBtStackHCIDev;
+ len = skb->len;
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_RECV)) {
+ if (bt_cb(skb)->pkt_type == HCI_EVENT_PKT) {
+ pEvent = (BT_HCI_EVENT_HEADER *)skb->data;
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, ("BT HCI EventCode: %d, len:%d \n",
+ pEvent->EventCode, pEvent->ParamLength));
+ }
+ }
+
+ /* pass receive packet up the stack */
+ if (hci_recv_frame(skb) != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: hci_recv_frame failed \n"));
+ break;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV,
+ ("HCI Bridge: Indicated RCV of type:%d, Length:%d \n",btType,len));
+ }
+
+ success = TRUE;
+
+ } while (FALSE);
+
+ return success;
+}
+
+static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length)
+{
+ struct sk_buff *skb;
+ /* in normal HCI mode we need to alloc from the bt core APIs */
+ skb = bt_skb_alloc(Length, GFP_ATOMIC);
+ if (NULL == skb) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc bt sk_buff \n"));
+ }
+ return skb;
+}
+
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb)
+{
+ kfree_skb(skb);
+}
+
+#else // { CONFIG_BLUEZ_HCI_BRIDGE
+
+ /* stubs when we only want to test the HCI bridging Interface without the HT stack */
+static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+ return A_OK;
+}
+static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+
+}
+static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo)
+{
+ A_ASSERT(FALSE);
+ return A_ERROR;
+}
+
+static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO *pHcidevInfo,
+ HCI_TRANSPORT_PACKET_TYPE Type,
+ struct sk_buff *skb)
+{
+ A_ASSERT(FALSE);
+ return FALSE;
+}
+
+static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length)
+{
+ A_ASSERT(FALSE);
+ return NULL;
+}
+static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb)
+{
+ A_ASSERT(FALSE);
+}
+
+#endif // } CONFIG_BLUEZ_HCI_BRIDGE
+
+#else // { ATH_AR6K_ENABLE_GMBOX
+
+ /* stubs when GMBOX support is not needed */
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(void *ar)
+#else
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar)
+#endif
+{
+ return A_OK;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_cleanup_hci(void *ar)
+#else
+void ar6000_cleanup_hci(AR_SOFTC_T *ar)
+#endif
+{
+ return;
+}
+
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig)
+{
+ return;
+}
+#endif
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+int hci_test_send(void *ar, struct sk_buff *skb)
+#else
+int hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb)
+#endif
+{
+ return -EOPNOTSUPP;
+}
+
+#endif // } ATH_AR6K_ENABLE_GMBOX
+
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+static int __init
+hcibridge_init_module(void)
+{
+ A_STATUS status;
+ HCI_TRANSPORT_CALLBACKS hciTransCallbacks;
+
+ hciTransCallbacks.setupTransport = ar6000_setup_hci;
+ hciTransCallbacks.cleanupTransport = ar6000_cleanup_hci;
+
+ status = ar6000_register_hci_transport(&hciTransCallbacks);
+ if(status != A_OK)
+ return -ENODEV;
+
+ return 0;
+}
+
+static void __exit
+hcibridge_cleanup_module(void)
+{
+}
+
+module_init(hcibridge_init_module);
+module_exit(hcibridge_cleanup_module);
+MODULE_LICENSE("GPL and additional rights");
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h b/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h
new file mode 100644
index 000000000000..3df15b71133a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h
@@ -0,0 +1,694 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _AR6000_H_
+#define _AR6000_H_
+
+#include <linux/version.h>
+
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17)
+#include <linux/config.h>
+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
+#include <linux/autoconf.h>
+#else
+#include <generated/autoconf.h>
+#endif
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/skbuff.h>
+#include <linux/if_ether.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/iw_handler.h>
+#include <linux/if_arp.h>
+#include <linux/ip.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
+#include <asm/semaphore.h>
+#else
+#include <linux/semaphore.h>
+#endif
+#include <linux/wireless.h>
+#ifdef ATH6K_CONFIG_CFG80211
+#include <net/cfg80211.h>
+#endif /* ATH6K_CONFIG_CFG80211 */
+#include <linux/module.h>
+#include <asm/io.h>
+
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "bmi.h"
+#include <ieee80211.h>
+#include <ieee80211_ioctl.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include "gpio_api.h"
+#include "gpio.h"
+#include "pkt_log.h"
+#include "aggr_recv_api.h"
+#include <host_version.h>
+#include <linux/rtnetlink.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+#include <asm/uaccess.h>
+#else
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#endif
+#include "ar6000_api.h"
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#include <testcmd.h>
+#endif
+#include <linux/firmware.h>
+
+#include "targaddrs.h"
+#include "dbglog_api.h"
+#include "ar6000_diag.h"
+#include "common_drv.h"
+#include "roaming.h"
+#include "hci_transport_api.h"
+#define ATH_MODULE_NAME driver
+#include "a_debug.h"
+#include "hw/apb_map.h"
+#include "hw/rtc_reg.h"
+#include "hw/mbox_reg.h"
+#include "hw/gpio_reg.h"
+
+#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0)
+#define ATH_DEBUG_WLAN_CONNECT ATH_DEBUG_MAKE_MODULE_MASK(1)
+#define ATH_DEBUG_WLAN_SCAN ATH_DEBUG_MAKE_MODULE_MASK(2)
+#define ATH_DEBUG_WLAN_TX ATH_DEBUG_MAKE_MODULE_MASK(3)
+#define ATH_DEBUG_WLAN_RX ATH_DEBUG_MAKE_MODULE_MASK(4)
+#define ATH_DEBUG_HTC_RAW ATH_DEBUG_MAKE_MODULE_MASK(5)
+#define ATH_DEBUG_HCI_BRIDGE ATH_DEBUG_MAKE_MODULE_MASK(6)
+#define ATH_DEBUG_HCI_RECV ATH_DEBUG_MAKE_MODULE_MASK(7)
+#define ATH_DEBUG_HCI_SEND ATH_DEBUG_MAKE_MODULE_MASK(8)
+#define ATH_DEBUG_HCI_DUMP ATH_DEBUG_MAKE_MODULE_MASK(9)
+
+#ifndef __dev_put
+#define __dev_put(dev) dev_put(dev)
+#endif
+
+
+#ifdef USER_KEYS
+
+#define USER_SAVEDKEYS_STAT_INIT 0
+#define USER_SAVEDKEYS_STAT_RUN 1
+
+// TODO this needs to move into the AR_SOFTC struct
+struct USER_SAVEDKEYS {
+ struct ieee80211req_key ucast_ik;
+ struct ieee80211req_key bcast_ik;
+ CRYPTO_TYPE keyType;
+ A_BOOL keyOk;
+};
+#endif
+
+#define DBG_INFO 0x00000001
+#define DBG_ERROR 0x00000002
+#define DBG_WARNING 0x00000004
+#define DBG_SDIO 0x00000008
+#define DBG_HIF 0x00000010
+#define DBG_HTC 0x00000020
+#define DBG_WMI 0x00000040
+#define DBG_WMI2 0x00000080
+#define DBG_DRIVER 0x00000100
+
+#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING)
+
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_AR6000 1
+#define AR6000_MAX_RX_BUFFERS 16
+#define AR6000_BUFFER_SIZE 1664
+#define AR6000_MAX_AMSDU_RX_BUFFERS 4
+#define AR6000_AMSDU_REFILL_THRESHOLD 3
+#define AR6000_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
+#define AR6000_MAX_RX_MESSAGE_SIZE (max(WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH,WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))
+
+#define AR6000_TX_TIMEOUT 10
+#define AR6000_ETH_ADDR_LEN 6
+#define AR6000_MAX_ENDPOINTS 4
+#define MAX_NODE_NUM 15
+/* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
+#define MAX_DEF_COOKIE_NUM 150
+#define MAX_HI_COOKIE_NUM 15 /* 10% of MAX_COOKIE_NUM */
+#define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
+
+/* MAX_DEFAULT_SEND_QUEUE_DEPTH is used to set the default queue depth for the
+ * WMM send queues. If a queue exceeds this depth htc will query back to the
+ * OS specific layer by calling EpSendFull(). This gives the OS layer the
+ * opportunity to drop the packet if desired. Therefore changing
+ * MAX_DEFAULT_SEND_QUEUE_DEPTH does not affect resource utilization but
+ * does impact the threshold used to identify if a packet should be
+ * dropped. */
+#define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
+
+#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1
+#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1
+#define A_DISCONNECT_TIMER_INTERVAL 10 * 1000
+#define A_DEFAULT_LISTEN_INTERVAL 100
+#define A_MAX_WOW_LISTEN_INTERVAL 1000
+
+enum {
+ DRV_HB_CHALLENGE = 0,
+ APP_HB_CHALLENGE
+};
+
+enum {
+ WLAN_INIT_MODE_NONE = 0,
+ WLAN_INIT_MODE_USR,
+ WLAN_INIT_MODE_UDEV,
+ WLAN_INIT_MODE_DRV
+};
+
+typedef enum _AR6K_BIN_FILE {
+ AR6K_OTP_FILE,
+ AR6K_FIRMWARE_FILE,
+ AR6K_PATCH_FILE,
+ AR6K_BOARD_DATA_FILE,
+} AR6K_BIN_FILE;
+
+#ifdef SETUPHCI_ENABLED
+#define SETUPHCI_DEFAULT 1
+#else
+#define SETUPHCI_DEFAULT 0
+#endif /* SETUPHCI_ENABLED */
+
+#ifdef SETUPBTDEV_ENABLED
+#define SETUPBTDEV_DEFAULT 1
+#else
+#define SETUPBTDEV_DEFAULT 0
+#endif /* SETUPBTDEV_ENABLED */
+
+#ifdef BMIENABLE_SET
+#define BMIENABLE_DEFAULT 1
+#else
+#define BMIENABLE_DEFAULT 0
+#endif /* BMIENABLE_SET */
+
+#ifdef ENABLEUARTPRINT_SET
+#define ENABLEUARTPRINT_DEFAULT 1
+#else
+#define ENABLEUARTPRINT_DEFAULT 0
+#endif /* ENABLEARTPRINT_SET */
+
+#ifdef ATH6K_CONFIG_HIF_VIRTUAL_SCATTER
+#define NOHIFSCATTERSUPPORT_DEFAULT 1
+#else /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+#define NOHIFSCATTERSUPPORT_DEFAULT 0
+#endif /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+
+#ifdef AR600x_BT_AR3001
+#define AR3KHCIBAUD_DEFAULT 3000000
+#define HCIUARTSCALE_DEFAULT 1
+#define HCIUARTSTEP_DEFAULT 8937
+#else
+#define AR3KHCIBAUD_DEFAULT 0
+#define HCIUARTSCALE_DEFAULT 0
+#define HCIUARTSTEP_DEFAULT 0
+#endif /* AR600x_BT_AR3001 */
+
+#ifdef INIT_MODE_DRV_ENABLED
+#define WLAN_INIT_MODE_DEFAULT WLAN_INIT_MODE_DRV
+#else
+#define WLAN_INIT_MODE_DEFAULT WLAN_INIT_MODE_USR
+#endif /* INIT_MODE_DRV_ENABLED */
+
+#define AR6K_PATCH_DOWNLOAD_ADDRESS(_param, _ver) do { \
+ if ((_ver) == AR6003_REV1_VERSION) { \
+ (_param) = AR6003_REV1_PATCH_DOWNLOAD_ADDRESS; \
+ } else if ((_ver) == AR6003_REV2_VERSION) { \
+ (_param) = AR6003_REV2_PATCH_DOWNLOAD_ADDRESS; \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+ A_ASSERT(0); \
+ } \
+} while (0)
+
+#define AR6K_DATA_DOWNLOAD_ADDRESS(_param, _ver) do { \
+ if ((_ver) == AR6003_REV1_VERSION) { \
+ (_param) = AR6003_REV1_DATA_DOWNLOAD_ADDRESS; \
+ } else if ((_ver) == AR6003_REV2_VERSION) { \
+ (_param) = AR6003_REV2_DATA_DOWNLOAD_ADDRESS; \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+ A_ASSERT(0); \
+ } \
+} while (0)
+
+#define AR6K_APP_START_OVERRIDE_ADDRESS(_param, _ver) do { \
+ if ((_ver) == AR6003_REV1_VERSION) { \
+ (_param) = AR6003_REV1_APP_START_OVERRIDE; \
+ } else if ((_ver) == AR6003_REV2_VERSION) { \
+ (_param) = AR6003_REV2_APP_START_OVERRIDE; \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+ A_ASSERT(0); \
+ } \
+} while (0)
+
+/* AR6003 1.0 definitions */
+#define AR6003_REV1_VERSION 0x300002ba
+#define AR6003_REV1_DATA_DOWNLOAD_ADDRESS AR6003_REV1_OTP_DATA_ADDRESS
+#define AR6003_REV1_PATCH_DOWNLOAD_ADDRESS 0x57ea6c
+#define AR6003_REV1_OTP_FILE "ath6k/AR6003/hw1.0/otp.bin.z77"
+#define AR6003_REV1_FIRMWARE_FILE "ath6k/AR6003/hw1.0/athwlan.bin.z77"
+#define AR6003_REV1_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw1.0/athtcmd_ram.bin"
+#define AR6003_REV1_ART_FIRMWARE_FILE "ath6k/AR6003/hw1.0/device.bin"
+#define AR6003_REV1_PATCH_FILE "ath6k/AR6003/hw1.0/data.patch.bin"
+#ifdef AR600x_SD31_XXX
+#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.SD31.bin"
+#elif defined(AR600x_SD32_XXX)
+#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.SD32.bin"
+#elif defined(AR600x_WB31_XXX)
+#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.WB31.bin"
+#else
+#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+/* AR6003 2.0 definitions */
+#define AR6003_REV2_VERSION 0x30000384
+#define AR6003_REV2_DATA_DOWNLOAD_ADDRESS AR6003_REV2_OTP_DATA_ADDRESS
+#define AR6003_REV2_PATCH_DOWNLOAD_ADDRESS 0x57e918
+#define AR6003_REV2_OTP_FILE "ath6k/AR6003/hw2.0/otp.bin.z77"
+#define AR6003_REV2_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athwlan.bin.z77"
+#define AR6003_REV2_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athtcmd_ram.bin"
+#define AR6003_REV2_ART_FIRMWARE_FILE "ath6k/AR6003/hw2.0/device.bin"
+#define AR6003_REV2_PATCH_FILE "ath6k/AR6003/hw2.0/data.patch.bin"
+#ifdef AR600x_SD31_XXX
+#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.SD31.bin"
+#elif defined(AR600x_SD32_XXX)
+#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.SD32.bin"
+#elif defined(AR600x_WB31_XXX)
+#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.WB31.bin"
+#else
+#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+/* HTC RAW streams */
+typedef enum _HTC_RAW_STREAM_ID {
+ HTC_RAW_STREAM_NOT_MAPPED = -1,
+ HTC_RAW_STREAM_0 = 0,
+ HTC_RAW_STREAM_1 = 1,
+ HTC_RAW_STREAM_2 = 2,
+ HTC_RAW_STREAM_3 = 3,
+ HTC_RAW_STREAM_NUM_MAX
+} HTC_RAW_STREAM_ID;
+
+#define RAW_HTC_READ_BUFFERS_NUM 4
+#define RAW_HTC_WRITE_BUFFERS_NUM 4
+
+#define HTC_RAW_BUFFER_SIZE 1664
+
+typedef struct {
+ int currPtr;
+ int length;
+ unsigned char data[HTC_RAW_BUFFER_SIZE];
+ HTC_PACKET HTCPacket;
+} raw_htc_buffer;
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/*
+ * add TCMD_MODE besides wmi and bypasswmi
+ * in TCMD_MODE, only few TCMD releated wmi commands
+ * counld be hanlder
+ */
+enum {
+ AR6000_WMI_MODE = 0,
+ AR6000_BYPASS_MODE,
+ AR6000_TCMD_MODE,
+ AR6000_WLAN_MODE
+};
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+struct ar_wep_key {
+ A_UINT8 arKeyIndex;
+ A_UINT8 arKeyLen;
+ A_UINT8 arKey[64];
+} ;
+
+#ifdef ATH6K_CONFIG_CFG80211
+struct ar_key {
+ A_UINT8 key[WLAN_MAX_KEY_LEN];
+ A_UINT8 key_len;
+ A_UINT8 seq[IW_ENCODE_SEQ_MAX_SIZE];
+ A_UINT8 seq_len;
+ A_UINT32 cipher;
+};
+#endif /* ATH6K_CONFIG_CFG80211 */
+
+
+struct ar_node_mapping {
+ A_UINT8 macAddress[6];
+ A_UINT8 epId;
+ A_UINT8 txPending;
+};
+
+struct ar_cookie {
+ A_UINT32 arc_bp[2]; /* Must be first field */
+ HTC_PACKET HtcPkt; /* HTC packet wrapper */
+ struct ar_cookie *arc_list_next;
+};
+
+struct ar_hb_chlng_resp {
+ A_TIMER timer;
+ A_UINT32 frequency;
+ A_UINT32 seqNum;
+ A_BOOL outstanding;
+ A_UINT8 missCnt;
+ A_UINT8 missThres;
+};
+
+/* Per STA data, used in AP mode */
+/*TODO: All this should move to OS independent dir */
+
+#define STA_PWR_MGMT_MASK 0x1
+#define STA_PWR_MGMT_SHIFT 0x0
+#define STA_PWR_MGMT_AWAKE 0x0
+#define STA_PWR_MGMT_SLEEP 0x1
+
+#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT))
+#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT))
+#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK)
+
+#define STA_PS_POLLED_MASK 0x1
+#define STA_PS_POLLED_SHIFT 0x1
+#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT))
+
+typedef struct {
+ A_UINT16 flags;
+ A_UINT8 mac[ATH_MAC_LEN];
+ A_UINT8 aid;
+ A_UINT8 keymgmt;
+ A_UINT8 ucipher;
+ A_UINT8 auth;
+ A_UINT8 wpa_ie[IEEE80211_MAX_IE];
+ A_NETBUF_QUEUE_T psq; /* power save q */
+ A_MUTEX_T psqLock;
+} sta_t;
+
+typedef struct ar6_raw_htc {
+ HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX];
+ HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX];
+ struct semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX];
+ struct semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX];
+ wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX];
+ wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX];
+ raw_htc_buffer raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
+ raw_htc_buffer raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
+ A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+ A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+} AR_RAW_HTC_T;
+
+typedef struct ar6_softc {
+ struct net_device *arNetDev; /* net_device pointer */
+ void *arWmi;
+ int arTxPending[ENDPOINT_MAX];
+ int arTotalTxDataPending;
+ A_UINT8 arNumDataEndPts;
+ A_BOOL arWmiEnabled;
+ A_BOOL arWmiReady;
+ A_BOOL arConnected;
+ HTC_HANDLE arHtcTarget;
+ void *arHifDevice;
+ spinlock_t arLock;
+ struct semaphore arSem;
+ int arSsidLen;
+ u_char arSsid[32];
+ A_UINT8 arNextMode;
+ A_UINT8 arNetworkType;
+ A_UINT8 arDot11AuthMode;
+ A_UINT8 arAuthMode;
+ A_UINT8 arPairwiseCrypto;
+ A_UINT8 arPairwiseCryptoLen;
+ A_UINT8 arGroupCrypto;
+ A_UINT8 arGroupCryptoLen;
+ A_UINT8 arDefTxKeyIndex;
+ struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1];
+ A_UINT8 arBssid[6];
+ A_UINT8 arReqBssid[6];
+ A_UINT16 arChannelHint;
+ A_UINT16 arBssChannel;
+ A_UINT16 arListenInterval;
+ struct ar6000_version arVersion;
+ A_UINT32 arTargetType;
+ A_INT8 arRssi;
+ A_UINT8 arTxPwr;
+ A_BOOL arTxPwrSet;
+ A_INT32 arBitRate;
+ struct net_device_stats arNetStats;
+ struct iw_statistics arIwStats;
+ A_INT8 arNumChannels;
+ A_UINT16 arChannelList[32];
+ A_UINT32 arRegCode;
+ A_BOOL statsUpdatePending;
+ TARGET_STATS arTargetStats;
+ A_INT8 arMaxRetries;
+ A_UINT8 arPhyCapability;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ A_UINT8 tcmdRxReport;
+ A_UINT32 tcmdRxTotalPkt;
+ A_INT32 tcmdRxRssi;
+ A_UINT32 tcmdPm;
+ A_UINT32 arTargetMode;
+ A_UINT32 tcmdRxcrcErrPkt;
+ A_UINT32 tcmdRxsecErrPkt;
+ A_UINT16 tcmdRateCnt[TCMD_MAX_RATES];
+ A_UINT16 tcmdRateCntShortGuard[TCMD_MAX_RATES];
+#endif
+ AR6000_WLAN_STATE arWlanState;
+ struct ar_node_mapping arNodeMap[MAX_NODE_NUM];
+ A_UINT8 arIbssPsEnable;
+ A_UINT8 arNodeNum;
+ A_UINT8 arNexEpId;
+ struct ar_cookie *arCookieList;
+ A_UINT32 arCookieCount;
+ A_UINT32 arRateMask;
+ A_UINT8 arSkipScan;
+ A_UINT16 arBeaconInterval;
+ A_BOOL arConnectPending;
+ A_BOOL arWmmEnabled;
+ struct ar_hb_chlng_resp arHBChallengeResp;
+ A_UINT8 arKeepaliveConfigured;
+ A_UINT32 arMgmtFilter;
+ HTC_ENDPOINT_ID arAc2EpMapping[WMM_NUM_AC];
+ A_BOOL arAcStreamActive[WMM_NUM_AC];
+ A_UINT8 arAcStreamPriMap[WMM_NUM_AC];
+ A_UINT8 arHiAcStreamActivePri;
+ A_UINT8 arEp2AcMapping[ENDPOINT_MAX];
+ HTC_ENDPOINT_ID arControlEp;
+#ifdef HTC_RAW_INTERFACE
+ AR_RAW_HTC_T *arRawHtc;
+#endif
+ A_BOOL arNetQueueStopped;
+ A_BOOL arRawIfInit;
+ int arDeviceIndex;
+ COMMON_CREDIT_STATE_INFO arCreditStateInfo;
+ A_BOOL arWMIControlEpFull;
+ A_BOOL dbgLogFetchInProgress;
+ A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE];
+ A_UINT32 log_cnt;
+ A_UINT32 dbglog_init_done;
+ A_UINT32 arConnectCtrlFlags;
+#ifdef USER_KEYS
+ A_INT32 user_savedkeys_stat;
+ A_UINT32 user_key_ctrl;
+ struct USER_SAVEDKEYS user_saved_keys;
+#endif
+ USER_RSSI_THOLD rssi_map[12];
+ A_UINT8 arUserBssFilter;
+ A_UINT16 ap_profile_flag; /* AP mode */
+ WMI_AP_ACL g_acl; /* AP mode */
+ sta_t sta_list[AP_MAX_NUM_STA]; /* AP mode */
+ A_UINT8 sta_list_index; /* AP mode */
+ struct ieee80211req_key ap_mode_bkey; /* AP mode */
+ A_NETBUF_QUEUE_T mcastpsq; /* power save q for Mcast frames */
+ A_MUTEX_T mcastpsqLock;
+ A_BOOL DTIMExpired; /* flag to indicate DTIM expired */
+ A_UINT8 intra_bss; /* enable/disable intra bss data forward */
+ void *aggr_cntxt;
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+ void *hcidev_info;
+#endif
+ WMI_AP_MODE_STAT arAPStats;
+ A_UINT8 ap_hidden_ssid;
+ A_UINT8 ap_country_code[3];
+ A_UINT8 ap_wmode;
+ A_UINT8 ap_dtim_period;
+ A_UINT16 ap_beacon_interval;
+ A_UINT16 arRTS;
+ A_UINT16 arACS; /* AP mode - Auto Channel Selection */
+ HTC_PACKET_QUEUE amsdu_rx_buffer_queue;
+ A_BOOL bIsDestroyProgress; /* flag to indicate ar6k destroy is in progress */
+ A_TIMER disconnect_timer;
+ A_UINT8 rxMetaVersion;
+#ifdef WAPI_ENABLE
+ A_UINT8 arWapiEnable;
+#endif
+ WMI_BTCOEX_CONFIG_EVENT arBtcoexConfig;
+ WMI_BTCOEX_STATS_EVENT arBtcoexStats;
+ A_INT32 (*exitCallback)(void *config); /* generic callback at AR6K exit */
+ HIF_DEVICE_OS_DEVICE_INFO osDevInfo;
+#ifdef ATH6K_CONFIG_CFG80211
+ struct wireless_dev *wdev;
+ struct cfg80211_scan_request *scan_request;
+ struct ar_key keys[WMI_MAX_KEY_INDEX + 1];
+#endif /* ATH6K_CONFIG_CFG80211 */
+#if CONFIG_PM
+ A_UINT16 arOsPowerCtrl;
+ A_UINT16 arWowState;
+#endif
+ A_BOOL scan_complete;
+ WMI_SCAN_PARAMS_CMD scParams;
+} AR_SOFTC_T;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+/* Looks like we need this for 2.4 kernels */
+static inline void *ar6k_priv(struct net_device *dev)
+{
+ return(dev->priv);
+}
+#else
+#ifdef ATH6K_CONFIG_CFG80211
+static inline void *ar6k_priv(struct net_device *dev)
+{
+ return (wdev_priv(dev->ieee80211_ptr));
+}
+#else
+#define ar6k_priv netdev_priv
+#endif /* ATH6K_CONFIG_CFG80211 */
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) */
+
+#define arAc2EndpointID(ar,ac) (ar)->arAc2EpMapping[(ac)]
+#define arSetAc2EndpointIDMap(ar,ac,ep) \
+{ (ar)->arAc2EpMapping[(ac)] = (ep); \
+ (ar)->arEp2AcMapping[(ep)] = (ac); }
+#define arEndpoint2Ac(ar,ep) (ar)->arEp2AcMapping[(ep)]
+
+#define arRawIfEnabled(ar) (ar)->arRawIfInit
+#define arRawStream2EndpointID(ar,raw) (ar)->arRawHtc->arRaw2EpMapping[(raw)]
+#define arSetRawStream2EndpointIDMap(ar,raw,ep) \
+{ (ar)->arRawHtc->arRaw2EpMapping[(raw)] = (ep); \
+ (ar)->arRawHtc->arEp2RawMapping[(ep)] = (raw); }
+#define arEndpoint2RawStreamID(ar,ep) (ar)->arRawHtc->arEp2RawMapping[(ep)]
+
+struct ar_giwscan_param {
+ char *current_ev;
+ char *end_buf;
+ A_UINT32 bytes_needed;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ struct iw_request_info *info;
+#endif
+};
+
+#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++)
+
+#define AR6000_SPIN_LOCK(lock, param) do { \
+ if (irqs_disabled()) { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled:AR6000_LOCK\n")); \
+ } \
+ spin_lock_bh(lock); \
+} while (0)
+
+#define AR6000_SPIN_UNLOCK(lock, param) do { \
+ if (irqs_disabled()) { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled: AR6000_UNLOCK\n")); \
+ } \
+ spin_unlock_bh(lock); \
+} while (0)
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
+void ar6000_gpio_init(void);
+void ar6000_init_profile_info(AR_SOFTC_T *ar);
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
+int ar6000_init(struct net_device *dev);
+int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar);
+void ar6000_TxDataCleanup(AR_SOFTC_T *ar);
+int ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev);
+
+#ifdef HTC_RAW_INTERFACE
+
+#ifndef __user
+#define __user
+#endif
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar);
+int ar6000_htc_raw_close(AR_SOFTC_T *ar);
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar,
+ HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t count);
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar,
+ HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t count);
+
+#endif /* HTC_RAW_INTERFACE */
+
+/* AP mode */
+/*TODO: These routines should be moved to a file that is common across OS */
+sta_t *
+ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr);
+
+sta_t *
+ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid);
+
+A_UINT8
+remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason);
+
+/* HCI support */
+
+#ifndef EXPORT_HCI_BRIDGE_INTERFACE
+A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar);
+void ar6000_cleanup_hci(AR_SOFTC_T *ar);
+void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig);
+
+/* HCI bridge testing */
+A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb);
+#endif
+
+ATH_DEBUG_DECLARE_EXTERN(htc);
+ATH_DEBUG_DECLARE_EXTERN(wmi);
+ATH_DEBUG_DECLARE_EXTERN(bmi);
+ATH_DEBUG_DECLARE_EXTERN(hif);
+ATH_DEBUG_DECLARE_EXTERN(wlan);
+ATH_DEBUG_DECLARE_EXTERN(misc);
+
+extern A_UINT8 bcast_mac[];
+extern A_UINT8 null_mac[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AR6000_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h
new file mode 100644
index 000000000000..fc5c363f9936
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h
@@ -0,0 +1,175 @@
+#ifndef _AR6XAPI_LINUX_H
+#define _AR6XAPI_LINUX_H
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ar6_softc;
+
+void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap,
+ A_UINT32 ver);
+A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid);
+void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
+ A_UINT8 *bssid, A_UINT16 listenInterval,
+ A_UINT16 beaconInterval, NETWORK_TYPE networkType,
+ A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+ A_UINT8 assocRespLen,A_UINT8 *assocInfo);
+void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
+ A_UINT8 *bssid, A_UINT8 assocRespLen,
+ A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
+ A_BOOL ismcast);
+void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
+void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
+void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
+void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
+void ar6000_keepalive_rx(void *devt, A_UINT8 configured);
+void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
+ WMI_NEIGHBOR_INFO *info);
+void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
+void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status);
+void ar6000_targetStats_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len);
+void ar6000_rssiThreshold_event(struct ar6_softc *ar,
+ WMI_RSSI_THRESHOLD_VAL newThreshold,
+ A_INT16 rssi);
+void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
+void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
+ A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
+void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel);
+void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source);
+void
+ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
+
+void
+ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p);
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters,
+ WMI_GET_WOW_LIST_REPLY *wow_reply);
+
+void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID,
+ WMI_PMKID *pmkidList, A_UINT8 *bssidList);
+
+void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
+void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
+void ar6000_gpio_ack_rx(void);
+
+A_INT32 rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt);
+A_INT16 rssi_compensation_calc(struct ar6_softc *ar, A_INT16 rssi);
+A_INT16 rssi_compensation_reverse_calc(struct ar6_softc *ar, A_INT16 rssi, A_BOOL Above);
+
+void ar6000_dbglog_init_done(struct ar6_softc *ar);
+
+#ifdef SEND_EVENT_TO_APP
+void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+void ar6000_send_generic_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len);
+#endif
+
+void ar6000_tx_retry_err_event(void *devt);
+
+void ar6000_snrThresholdEvent_rx(void *devt,
+ WMI_SNR_THRESHOLD_VAL newThreshold,
+ A_UINT8 snr);
+
+void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal);
+
+
+void ar6000_ratemask_rx(void *devt, A_UINT32 ratemask);
+
+A_STATUS ar6000_get_driver_cfg(struct net_device *dev,
+ A_UINT16 cfgParam,
+ void *result);
+void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len);
+
+void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped,
+ A_INT8 *buffer, A_UINT32 length);
+
+int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar);
+
+void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid);
+
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active);
+HTC_ENDPOINT_ID ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac);
+A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep );
+
+void ar6000_btcoex_config_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len);
+
+void ar6000_btcoex_stats_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len) ;
+
+void ar6000_dset_open_req(void *devt,
+ A_UINT32 id,
+ A_UINT32 targ_handle,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
+void ar6000_dset_data_req(void *devt,
+ A_UINT32 access_cookie,
+ A_UINT32 offset,
+ A_UINT32 length,
+ A_UINT32 targ_buf,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+void prof_count_rx(unsigned int addr, unsigned int count);
+#endif
+
+A_UINT32 ar6000_getnodeAge (void);
+
+A_UINT32 ar6000_getclkfreq (void);
+
+int ar6000_ap_mode_profile_commit(struct ar6_softc *ar);
+
+struct ieee80211req_wpaie;
+A_STATUS
+ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie);
+
+A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd);
+
+A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd);
+
+void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid);
+
+void ar6000_dtimexpiry_event(struct ar6_softc *ar);
+
+void ar6000_aggr_rcv_addba_req_evt(struct ar6_softc *ar, WMI_ADDBA_REQ_EVENT *cmd);
+void ar6000_aggr_rcv_addba_resp_evt(struct ar6_softc *ar, WMI_ADDBA_RESP_EVENT *cmd);
+void ar6000_aggr_rcv_delba_req_evt(struct ar6_softc *ar, WMI_DELBA_EVENT *cmd);
+void ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd);
+
+#ifdef WAPI_ENABLE
+int ap_set_wapi_key(struct ar6_softc *ar, void *ik);
+void ap_wapi_rekey_event(struct ar6_softc *ar, A_UINT8 type, A_UINT8 *mac);
+#endif
+
+A_STATUS ar6000_connect_to_ap(struct ar6_softc *ar);
+A_STATUS ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h
new file mode 100644
index 000000000000..e661741f3b9e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h
@@ -0,0 +1,1202 @@
+/*
+ * Copyright (c) 2004-2009 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _ATHDRV_LINUX_H
+#define _ATHDRV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ * There are two types of ioctl's here: Standard ioctls and
+ * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed
+ * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The
+ * arguments for every XIOCTL starts with a 32-bit command word
+ * that is used to select which extended ioctl is in use. After
+ * the command word are command-specific arguments.
+ */
+
+/* Linux standard Wireless Extensions, private ioctl interfaces */
+#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0)
+#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1)
+#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2)
+#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3)
+#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4)
+#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5)
+//#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+6)
+//#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+7)
+//#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+8)
+//#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+9)
+//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10)
+#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10)
+
+
+
+/* ====WMI Ioctls==== */
+/*
+ *
+ * Many ioctls simply provide WMI services to application code:
+ * an application makes such an ioctl call with a set of arguments
+ * that are packaged into the corresponding WMI message, and sent
+ * to the Target.
+ */
+
+#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11)
+/*
+ * arguments:
+ * ar6000_version *revision
+ */
+
+#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12)
+/*
+ * arguments:
+ * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
+ * uses: WMI_SET_POWER_MODE_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13)
+/*
+ * arguments:
+ * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
+ * uses: WMI_SET_SCAN_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14)
+/*
+ * arguments:
+ * UINT32 listenInterval
+ * uses: WMI_SET_LISTEN_INT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15)
+/*
+ * arguments:
+ * WMI_BSS_FILTER filter (see include/wmi.h)
+ * uses: WMI_SET_BSS_FILTER_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16)
+/*
+ * arguments:
+ * WMI_CHANNEL_PARAMS_CMD chParams
+ * uses: WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17)
+/*
+ * arguments:
+ * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
+ * uses: WMI_SETPROBED_SSID_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18)
+/*
+ * arguments:
+ * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
+ * uses: WMI_SET_POWER_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19)
+/*
+ * arguments:
+ * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
+ * uses: WMI_ADD_BAD_AP_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20)
+/*
+ * arguments:
+ * ar6000_queuereq queueRequest (see below)
+ */
+
+#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21)
+/*
+ * arguments:
+ * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
+ * uses: WMI_CREATE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22)
+/*
+ * arguments:
+ * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
+ * uses: WMI_DELETE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23)
+/*
+ * arguments:
+ * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
+/*
+ * arguments:
+ * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
+ * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25)
+/*
+ * arguments:
+ * TARGET_STATS *targetStats (see below)
+ * uses: WMI_GET_STATISTICS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26)
+/*
+ * arguments:
+ * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
+ * uses: WMI_SET_ASSOC_INFO_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27)
+/*
+ * arguments:
+ * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
+ * uses: WMI_SET_ACCESS_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28)
+/*
+ * arguments:
+ * UINT32 beaconMissTime
+ * uses: WMI_SET_BMISS_TIME_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29)
+/*
+ * arguments:
+ * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
+ * uses: WMI_SET_DISC_TIMEOUT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30)
+/*
+ * arguments:
+ * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
+ * uses: WMI_SET_IBSS_PM_CAPS_CMDID
+ */
+
+/*
+ * There is a very small space available for driver-private
+ * wireless ioctls. In order to circumvent this limitation,
+ * we multiplex a bunch of ioctls (XIOCTLs) on top of a
+ * single AR6000_IOCTL_EXTENDED ioctl.
+ */
+#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31)
+
+
+/* ====BMI Extended Ioctls==== */
+
+#define AR6000_XIOCTL_BMI_DONE 1
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
+ * uses: BMI_DONE
+ */
+
+#define AR6000_XIOCTL_BMI_READ_MEMORY 2
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
+ * UINT32 address
+ * UINT32 length
+ * }
+ * char results[length]
+ * }
+ * uses: BMI_READ_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
+ * UINT32 address
+ * UINT32 length
+ * char data[length]
+ * uses: BMI_WRITE_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_EXECUTE 4
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
+ * UINT32 TargetAddress
+ * UINT32 parameter
+ * uses: BMI_EXECUTE
+ */
+
+#define AR6000_XIOCTL_BMI_SET_APP_START 5
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
+ * UINT32 TargetAddress
+ * uses: BMI_SET_APP_START
+ */
+
+#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
+ * UINT32 TargetAddress, 32-bit aligned
+ * }
+ * UINT32 result
+ * }
+ * uses: BMI_READ_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
+ * UINT32 TargetAddress, 32-bit aligned
+ * UINT32 newValue
+ * }
+ * uses: BMI_WRITE_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_TEST 8
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
+ * UINT32 address
+ * UINT32 length
+ * UINT32 count
+ */
+
+
+
+/* Historical Host-side DataSet support */
+#define AR6000_XIOCTL_UNUSED9 9
+#define AR6000_XIOCTL_UNUSED10 10
+#define AR6000_XIOCTL_UNUSED11 11
+
+/* ====Misc Extended Ioctls==== */
+
+#define AR6000_XIOCTL_FORCE_TARGET_RESET 12
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
+ */
+
+
+#ifdef HTC_RAW_INTERFACE
+/* HTC Raw Interface Ioctls */
+#define AR6000_XIOCTL_HTC_RAW_OPEN 13
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_CLOSE 14
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_READ 15
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
+ * UINT32 mailboxID
+ * UINT32 length
+ * }
+ * results[length]
+ * }
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_WRITE 16
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
+ * UINT32 mailboxID
+ * UINT32 length
+ * char buffer[length]
+ */
+#endif /* HTC_RAW_INTERFACE */
+
+#define AR6000_XIOCTL_CHECK_TARGET_READY 17
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
+ */
+
+
+
+/* ====GPIO (General Purpose I/O) Extended Ioctls==== */
+
+#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
+ * ar6000_gpio_output_set_cmd_s (see below)
+ * uses: WMIX_GPIO_OUTPUT_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INPUT_GET 19
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
+ * uses: WMIX_GPIO_INPUT_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_SET 20
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
+ * ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_GET 21
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
+ * ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_ACK 22
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
+ * ar6000_cpio_intr_ack_cmd_s (see below)
+ * uses: WMIX_GPIO_INTR_ACK_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_WAIT 23
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
+ */
+
+
+
+/* ====more wireless commands==== */
+
+#define AR6000_XIOCTL_SET_ADHOC_BSSID 24
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
+ * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
+ */
+
+#define AR6000_XIOCTL_SET_OPT_MODE 25
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
+ * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
+ * uses: WMI_SET_OPT_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_OPT_SEND_FRAME 26
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
+ * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
+ * uses: WMI_OPT_TX_FRAME_CMDID
+ */
+
+#define AR6000_XIOCTL_SET_BEACON_INTVAL 27
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL)
+ * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
+ * uses: WMI_SET_BEACON_INT_CMDID
+ */
+
+
+#define IEEE80211_IOCTL_SETAUTHALG 28
+
+
+#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
+ * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
+ * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+
+
+#define AR6000_XIOCTL_SET_MAX_SP 30
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
+ * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
+ * uses: WMI_SET_MAX_SP_LEN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31
+
+#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32
+
+#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33
+
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
+ * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
+ * WMI_SET_POWERSAVE_TIMERS_CMDID
+ */
+
+#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
+ */
+
+#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35
+typedef enum {
+ WLAN_DISABLED,
+ WLAN_ENABLED
+} AR6000_WLAN_STATE;
+/*
+ * arguments:
+ * enable/disable
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36
+
+#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37
+/*
+ * arguments:
+ * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd
+ * uses: WMI_SET_RETRY_LIMITS_CMDID
+ */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/* ====extended commands for radio test ==== */
+
+#define AR6000_XIOCTL_TCMD_CONT_TX 38
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX)
+ * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_TX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_CONT_RX 39
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX)
+ * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_RX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_PM 40
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TCMD_PM)
+ * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h)
+ * uses: WMI_TCMD_PM_CMDID
+ */
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+#define AR6000_XIOCTL_WMI_STARTSCAN 41
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN)
+ * UINT8 scanType
+ * UINT8 scanConnected
+ * A_BOOL forceFgScan
+ * uses: WMI_START_SCAN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SETFIXRATES 42
+
+#define AR6000_XIOCTL_WMI_GETFIXRATES 43
+
+
+#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44
+/*
+ * arguments:
+ * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45
+/*
+ * arguments:
+ * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_CLR_RSSISNR_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46
+/*
+ * arguments:
+ * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_RTS 47
+/*
+ * arguments:
+ * WMI_SET_RTS_MODE_CMD (see include/wmi.h)
+ * uses: WMI_SET_RTS_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48
+
+#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE)
+ * UINT8 mode
+ * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM)
+ * UINT8 mode
+ * uses: WMI_SET_WMM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_WMM 51
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS)
+ * UINT32 frequency
+ * UINT8 threshold
+ */
+#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP)
+ * UINT32 cookie
+ */
+#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD)
+ * UINT32 regDomain
+ */
+#define AR6000_XIOCTL_WMI_GET_RD 54
+
+#define AR6000_XIOCTL_DIAG_READ 55
+
+#define AR6000_XIOCTL_DIAG_WRITE 56
+
+/*
+ * arguments cmd (AR6000_XIOCTL_SET_TXOP)
+ * WMI_TXOP_CFG txopEnable
+ */
+#define AR6000_XIOCTL_WMI_SET_TXOP 57
+
+#ifdef USER_KEYS
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
+ * UINT32 keyOpCtrl
+ * uses AR6000_USER_SETKEYS_INFO
+ */
+#define AR6000_XIOCTL_USER_SETKEYS 58
+#endif /* USER_KEYS */
+
+#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59
+/*
+ * arguments:
+ * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE)
+ * UINT8 keepaliveInterval
+ * uses: WMI_SET_KEEPALIVE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60
+/*
+ * arguments:
+ * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE)
+ * UINT8 keepaliveInterval
+ * A_BOOL configured
+ * uses: WMI_GET_KEEPALIVE_CMDID
+ */
+
+/* ====ROM Patching Extended Ioctls==== */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL)
+ * UINT32 ROM Address
+ * UINT32 RAM Address
+ * UINT32 number of bytes
+ * UINT32 activate? (0 or 1)
+ * }
+ * A_UINT32 resulting rompatch ID
+ * }
+ * uses: BMI_ROMPATCH_INSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL)
+ * UINT32 rompatch ID
+ * }
+ * uses: BMI_ROMPATCH_UNINSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE)
+ * UINT32 rompatch count
+ * UINT32 rompatch IDs[rompatch count]
+ * }
+ * uses: BMI_ROMPATCH_ACTIVATE
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE)
+ * UINT32 rompatch count
+ * UINT32 rompatch IDs[rompatch count]
+ * }
+ * uses: BMI_ROMPATCH_DEACTIVATE
+ */
+
+#define AR6000_XIOCTL_WMI_SET_APPIE 65
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE)
+ * UINT32 app_frmtype;
+ * UINT32 app_buflen;
+ * UINT8 app_buf[];
+ * }
+ */
+#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66
+/*
+ * arguments:
+ * A_UINT32 filter_type;
+ */
+
+#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67
+
+#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68
+
+#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70
+/*
+ * arguments:
+ * A_UINT32 wsc_status;
+ * (WSC_REG_INACTIVE or WSC_REG_ACTIVE)
+ */
+
+/*
+ * arguments:
+ * struct {
+ * A_UINT8 streamType;
+ * A_UINT8 status;
+ * }
+ * uses: WMI_SET_BT_STATUS_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71
+
+/*
+ * arguments:
+ * struct {
+ * A_UINT8 paramType;
+ * union {
+ * A_UINT8 noSCOPkts;
+ * BT_PARAMS_A2DP a2dpParams;
+ * BT_COEX_REGS regs;
+ * };
+ * }
+ * uses: WMI_SET_BT_PARAM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72
+
+#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73
+#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74
+#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75
+#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76
+#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77
+
+
+
+#define AR6000_XIOCTL_TARGET_INFO 78
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO)
+ * A_UINT32 TargetVersion (returned)
+ * A_UINT32 TargetType (returned)
+ * (See also bmi_msg.h target_ver and target_type)
+ */
+
+#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79
+/*
+ * arguments:
+ * none
+ */
+
+#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80
+/*
+ * This ioctl is used to emulate traffic activity
+ * timeouts. Activity/inactivity will trigger the driver
+ * to re-balance credits.
+ *
+ * arguments:
+ * ar6000_traffic_activity_change
+ */
+
+#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81
+/*
+ * This ioctl is used to set the connect control flags
+ *
+ * arguments:
+ * A_UINT32 connectCtrlFlags
+ */
+
+#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82
+/*
+ * This IOCTL sets any Authentication,Key Management and Protection
+ * related parameters. This is used along with the information set in
+ * Connect Command.
+ * Currently this enables Multiple PMKIDs to an AP.
+ *
+ * arguments:
+ * struct {
+ * A_UINT32 akmpInfo;
+ * }
+ * uses: WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83
+
+#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84
+/*
+ * This IOCTL is used to set a list of PMKIDs. This list of
+ * PMKIDs is used in the [Re]AssocReq Frame. This list is used
+ * only if the MultiPMKID option is enabled via the
+ * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL.
+ *
+ * arguments:
+ * struct {
+ * A_UINT32 numPMKID;
+ * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
+ * }
+ * uses: WMI_SET_PMKIDLIST_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_SET_PARAMS 85
+#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER 86
+#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER 87
+
+
+/* Historical DSETPATCH support for INI patches */
+#define AR6000_XIOCTL_UNUSED90 90
+
+
+/* Support LZ-compressed firmware download */
+#define AR6000_XIOCTL_BMI_LZ_STREAM_START 91
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START)
+ * UINT32 address
+ * uses: BMI_LZ_STREAM_START
+ */
+
+#define AR6000_XIOCTL_BMI_LZ_DATA 92
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA)
+ * UINT32 length
+ * char data[length]
+ * uses: BMI_LZ_DATA
+ */
+
+#define AR6000_XIOCTL_PROF_CFG 93
+/*
+ * arguments:
+ * A_UINT32 period
+ * A_UINT32 nbins
+ */
+
+#define AR6000_XIOCTL_PROF_ADDR_SET 94
+/*
+ * arguments:
+ * A_UINT32 Target address
+ */
+
+#define AR6000_XIOCTL_PROF_START 95
+
+#define AR6000_XIOCTL_PROF_STOP 96
+
+#define AR6000_XIOCTL_PROF_COUNT_GET 97
+
+#define AR6000_XIOCTL_WMI_ABORT_SCAN 98
+
+/*
+ * AP mode
+ */
+#define AR6000_XIOCTL_AP_GET_STA_LIST 99
+
+#define AR6000_XIOCTL_AP_HIDDEN_SSID 100
+
+#define AR6000_XIOCTL_AP_SET_NUM_STA 101
+
+#define AR6000_XIOCTL_AP_SET_ACL_MAC 102
+
+#define AR6000_XIOCTL_AP_GET_ACL_LIST 103
+
+#define AR6000_XIOCTL_AP_COMMIT_CONFIG 104
+
+#define IEEE80211_IOCTL_GETWPAIE 105
+
+#define AR6000_XIOCTL_AP_CONN_INACT_TIME 106
+
+#define AR6000_XIOCTL_AP_PROT_SCAN_TIME 107
+
+#define AR6000_XIOCTL_AP_SET_COUNTRY 108
+
+#define AR6000_XIOCTL_AP_SET_DTIM 109
+
+
+
+
+#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110
+
+#define AR6000_XIOCTL_SET_IP 111
+
+#define AR6000_XIOCTL_AP_SET_ACL_POLICY 112
+
+#define AR6000_XIOCTL_AP_INTRA_BSS_COMM 113
+
+#define AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO 114
+
+#define AR6000_XIOCTL_MODULE_DEBUG_SET_MASK 115
+
+#define AR6000_XIOCTL_MODULE_DEBUG_GET_MASK 116
+
+#define AR6000_XIOCTL_DUMP_RCV_AGGR_STATS 117
+
+#define AR6000_XIOCTL_SET_HT_CAP 118
+
+#define AR6000_XIOCTL_SET_HT_OP 119
+
+#define AR6000_XIOCTL_AP_GET_STAT 120
+
+#define AR6000_XIOCTL_SET_TX_SELECT_RATES 121
+
+#define AR6000_XIOCTL_SETUP_AGGR 122
+
+#define AR6000_XIOCTL_ALLOW_AGGR 123
+
+#define AR6000_XIOCTL_AP_GET_HIDDEN_SSID 124
+
+#define AR6000_XIOCTL_AP_GET_COUNTRY 125
+
+#define AR6000_XIOCTL_AP_GET_WMODE 126
+
+#define AR6000_XIOCTL_AP_GET_DTIM 127
+
+#define AR6000_XIOCTL_AP_GET_BINTVL 128
+
+#define AR6000_XIOCTL_AP_GET_RTS 129
+
+#define AR6000_XIOCTL_DELE_AGGR 130
+
+#define AR6000_XIOCTL_FETCH_TARGET_REGS 131
+
+#define AR6000_XIOCTL_HCI_CMD 132
+
+#define AR6000_XIOCTL_ACL_DATA 133
+
+#define AR6000_XIOCTL_WLAN_CONN_PRECEDENCE 134
+
+#define AR6000_XIOCTL_AP_SET_11BG_RATESET 135
+
+#define AR6000_XIOCTL_WMI_SET_AP_PS 136
+
+#define AR6000_XIOCTL_WMI_MCAST_FILTER 137
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT 138
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV 139
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG 140
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG 141
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG 142
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG 143
+
+#define AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG 144
+
+#define AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS 145
+
+#define AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG 146
+
+#define AR6000_XIOCTL_WMI_GET_BTCOEX_STATS 147
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_QOS_SUPP)
+ * UINT8 mode
+ * uses: WMI_SET_QOS_SUPP_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_QOS_SUPP 148
+
+
+/*
+ * arguments:
+ * WMI_AP_PS_CMD apPsCmd
+ * uses: WMI_AP_PS_CMDID
+ */
+
+/* used by AR6000_IOCTL_WMI_GETREV */
+struct ar6000_version {
+ A_UINT32 host_ver;
+ A_UINT32 target_ver;
+ A_UINT32 wlan_ver;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
+struct ar6000_queuereq {
+ A_UINT8 trafficClass;
+ A_UINT16 activeTsids;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
+typedef struct targetStats_t {
+ A_UINT64 tx_packets;
+ A_UINT64 tx_bytes;
+ A_UINT64 tx_unicast_pkts;
+ A_UINT64 tx_unicast_bytes;
+ A_UINT64 tx_multicast_pkts;
+ A_UINT64 tx_multicast_bytes;
+ A_UINT64 tx_broadcast_pkts;
+ A_UINT64 tx_broadcast_bytes;
+ A_UINT64 tx_rts_success_cnt;
+ A_UINT64 tx_packet_per_ac[4];
+
+ A_UINT64 tx_errors;
+ A_UINT64 tx_failed_cnt;
+ A_UINT64 tx_retry_cnt;
+ A_UINT64 tx_mult_retry_cnt;
+ A_UINT64 tx_rts_fail_cnt;
+
+ A_UINT64 rx_packets;
+ A_UINT64 rx_bytes;
+ A_UINT64 rx_unicast_pkts;
+ A_UINT64 rx_unicast_bytes;
+ A_UINT64 rx_multicast_pkts;
+ A_UINT64 rx_multicast_bytes;
+ A_UINT64 rx_broadcast_pkts;
+ A_UINT64 rx_broadcast_bytes;
+ A_UINT64 rx_fragment_pkt;
+
+ A_UINT64 rx_errors;
+ A_UINT64 rx_crcerr;
+ A_UINT64 rx_key_cache_miss;
+ A_UINT64 rx_decrypt_err;
+ A_UINT64 rx_duplicate_frames;
+
+ A_UINT64 tkip_local_mic_failure;
+ A_UINT64 tkip_counter_measures_invoked;
+ A_UINT64 tkip_replays;
+ A_UINT64 tkip_format_errors;
+ A_UINT64 ccmp_format_errors;
+ A_UINT64 ccmp_replays;
+
+ A_UINT64 power_save_failure_cnt;
+
+ A_UINT64 cs_bmiss_cnt;
+ A_UINT64 cs_lowRssi_cnt;
+ A_UINT64 cs_connect_cnt;
+ A_UINT64 cs_disconnect_cnt;
+
+ A_INT32 tx_unicast_rate;
+ A_INT32 rx_unicast_rate;
+
+ A_UINT32 lq_val;
+
+ A_UINT32 wow_num_pkts_dropped;
+ A_UINT16 wow_num_events_discarded;
+
+ A_INT16 noise_floor_calibation;
+ A_INT16 cs_rssi;
+ A_INT16 cs_aveBeacon_rssi;
+ A_UINT8 cs_aveBeacon_snr;
+ A_UINT8 cs_lastRoam_msec;
+ A_UINT8 cs_snr;
+
+ A_UINT8 wow_num_host_pkt_wakeups;
+ A_UINT8 wow_num_host_event_wakeups;
+
+ A_UINT32 arp_received;
+ A_UINT32 arp_matched;
+ A_UINT32 arp_replied;
+}TARGET_STATS;
+
+typedef struct targetStats_cmd_t {
+ TARGET_STATS targetStats;
+ int clearStats;
+} TARGET_STATS_CMD;
+
+/* used by AR6000_XIOCTL_USER_SETKEYS */
+
+/*
+ * Setting this bit to 1 doesnot initialize the RSC on the firmware
+ */
+#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1
+#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002
+
+typedef struct {
+ A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */
+} AR6000_USER_SETKEYS_INFO;
+
+
+/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
+struct ar6000_gpio_output_set_cmd_s {
+ A_UINT32 set_mask;
+ A_UINT32 clear_mask;
+ A_UINT32 enable_mask;
+ A_UINT32 disable_mask;
+};
+
+/*
+ * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
+ */
+struct ar6000_gpio_register_cmd_s {
+ A_UINT32 gpioreg_id;
+ A_UINT32 value;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
+struct ar6000_gpio_intr_ack_cmd_s {
+ A_UINT32 ack_mask;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
+struct ar6000_gpio_intr_wait_cmd_s {
+ A_UINT32 intr_mask;
+ A_UINT32 input_values;
+};
+
+/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */
+typedef struct ar6000_dbglog_module_config_s {
+ A_UINT32 valid;
+ A_UINT16 mmask;
+ A_UINT16 tsr;
+ A_BOOL rep;
+ A_UINT16 size;
+} DBGLOG_MODULE_CONFIG;
+
+typedef struct user_rssi_thold_t {
+ A_INT16 tag;
+ A_INT16 rssi;
+} USER_RSSI_THOLD;
+
+typedef struct user_rssi_params_t {
+ A_UINT8 weight;
+ A_UINT32 pollTime;
+ USER_RSSI_THOLD tholds[12];
+} USER_RSSI_PARAMS;
+
+typedef struct ar6000_get_btcoex_config_cmd_t{
+ A_UINT32 btProfileType;
+ A_UINT32 linkId;
+ }AR6000_GET_BTCOEX_CONFIG_CMD;
+
+typedef struct ar6000_btcoex_config_t {
+ AR6000_GET_BTCOEX_CONFIG_CMD configCmd;
+ A_UINT32 * configEvent;
+} AR6000_BTCOEX_CONFIG;
+
+typedef struct ar6000_btcoex_stats_t {
+ A_UINT32 * statsEvent;
+ }AR6000_BTCOEX_STATS;
+/*
+ * Host driver may have some config parameters. Typically, these
+ * config params are one time config parameters. These could
+ * correspond to any of the underlying modules. Host driver exposes
+ * an api for the underlying modules to get this config.
+ */
+#define AR6000_DRIVER_CFG_BASE 0x8000
+
+/* Should driver perform wlan node caching? */
+#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001
+/*Should we log raw WMI msgs */
+#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002
+
+/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */
+struct ar6000_diag_window_cmd_s {
+ unsigned int addr;
+ unsigned int value;
+};
+
+
+struct ar6000_traffic_activity_change {
+ A_UINT32 StreamID; /* stream ID to indicate activity change */
+ A_UINT32 Active; /* active (1) or inactive (0) */
+};
+
+/* Used with AR6000_XIOCTL_PROF_COUNT_GET */
+struct prof_count_s {
+ A_UINT32 addr; /* bin start address */
+ A_UINT32 count; /* hit count */
+};
+
+
+/* used by AR6000_XIOCTL_MODULE_DEBUG_SET_MASK */
+/* AR6000_XIOCTL_MODULE_DEBUG_GET_MASK */
+/* AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO */
+struct drv_debug_module_s {
+ A_CHAR modulename[128]; /* name of module */
+ A_UINT32 mask; /* new mask to set .. or .. current mask */
+};
+
+
+/* All HCI related rx events are sent up to the host app
+ * via a wmi event id. It can contain ACL data or HCI event,
+ * based on which it will be de-multiplexed.
+ */
+typedef enum {
+ PAL_HCI_EVENT = 0,
+ PAL_HCI_RX_DATA,
+} WMI_PAL_EVENT_INFO;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athendpack_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athendpack_linux.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/athendpack_linux.h
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athstartpack_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athstartpack_linux.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/athstartpack_linux.h
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h
new file mode 100644
index 000000000000..a2bd9e953cd2
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h
@@ -0,0 +1,47 @@
+/*
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _ATHTYPES_LINUX_H_
+#define _ATHTYPES_LINUX_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <sys/types.h>
+#endif
+
+typedef int8_t A_INT8;
+typedef int16_t A_INT16;
+typedef int32_t A_INT32;
+typedef int64_t A_INT64;
+
+typedef u_int8_t A_UINT8;
+typedef u_int16_t A_UINT16;
+typedef u_int32_t A_UINT32;
+typedef u_int64_t A_UINT64;
+
+typedef int A_BOOL;
+typedef char A_CHAR;
+typedef unsigned char A_UCHAR;
+typedef unsigned long A_ATH_TIMER;
+
+
+#endif /* _ATHTYPES_LINUX_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h b/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h
new file mode 100644
index 000000000000..2fac60b8a589
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h
@@ -0,0 +1,46 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _AR6K_CFG80211_H_
+#define _AR6K_CFG80211_H_
+
+struct wireless_dev *ar6k_cfg80211_init(struct device *dev);
+void ar6k_cfg80211_deinit(AR_SOFTC_T *ar);
+
+void ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status);
+
+void ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel,
+ A_UINT8 *bssid, A_UINT16 listenInterval,
+ A_UINT16 beaconInterval,NETWORK_TYPE networkType,
+ A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+ A_UINT8 assocRespLen, A_UINT8 *assocInfo);
+
+void ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason,
+ A_UINT8 *bssid, A_UINT8 assocRespLen,
+ A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+
+void ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast);
+
+#endif /* _AR6K_CFG80211_H_ */
+
+
+
+
+
+
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h
new file mode 100644
index 000000000000..78b95bf7faa4
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _CONFIG_LINUX_H_
+#define _CONFIG_LINUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/version.h>
+
+/*
+ * Host-side GPIO support is optional.
+ * If run-time access to GPIO pins is not required, then
+ * this should be changed to #undef.
+ */
+#define CONFIG_HOST_GPIO_SUPPORT
+
+/*
+ * Host side Test Command support
+ */
+#define CONFIG_HOST_TCMD_SUPPORT
+
+#define USE_4BYTE_REGISTER_ACCESS
+
+/* Host-side support for Target-side profiling */
+#undef CONFIG_TARGET_PROFILE_SUPPORT
+
+/* IP/TCP checksum offload */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
+#define CONFIG_CHECKSUM_OFFLOAD
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h
new file mode 100644
index 000000000000..6ef4cb6953d9
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _DEBUG_LINUX_H_
+#define _DEBUG_LINUX_H_
+
+ /* macro to remove parens */
+#define ATH_PRINTX_ARG(arg...) arg
+
+#ifdef DEBUG
+ /* NOTE: the AR_DEBUG_PRINTF macro is defined here to handle special handling of variable arg macros
+ * which may be compiler dependent. */
+#define AR_DEBUG_PRINTF(mask, args) do { \
+ if (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (mask)) { \
+ A_PRINTF(ATH_PRINTX_ARG args); \
+ } \
+} while (0)
+#else
+ /* on non-debug builds, keep in error and warning messages in the driver, all other
+ * message tracing will get compiled out */
+#define AR_DEBUG_PRINTF(mask, args) \
+ if ((mask) & (ATH_DEBUG_ERR | ATH_DEBUG_WARN)) { A_PRINTF(ATH_PRINTX_ARG args); }
+
+#endif
+
+ /* compile specific macro to get the function name string */
+#define _A_FUNCNAME_ __func__
+
+
+#endif /* _DEBUG_LINUX_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h b/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h
new file mode 100644
index 000000000000..b3d51b44906a
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h
@@ -0,0 +1,70 @@
+//------------------------------------------------------------------------------
+// <copyright file="hci_bridge.c" company="Atheros">
+// Copyright (c) 2009 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// HCI bridge implementation
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "hci_transport_api.h"
+#include "common_drv.h"
+
+extern HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo);
+extern void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue);
+extern A_STATUS (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous);
+extern void (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans);
+extern A_STATUS (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable);
+extern A_STATUS (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans,
+ HTC_PACKET *pPacket,
+ int MaxPollMS);
+extern A_STATUS (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud);
+
+
+#define HCI_TransportAttach(HTCHandle, pInfo) \
+ _HCI_TransportAttach((HTCHandle), (pInfo))
+#define HCI_TransportDetach(HciTrans) \
+ _HCI_TransportDetach(HciTrans)
+#define HCI_TransportAddReceivePkts(HciTrans, pQueue) \
+ _HCI_TransportAddReceivePkts((HciTrans), (pQueue))
+#define HCI_TransportSendPkt(HciTrans, pPacket, Synchronous) \
+ _HCI_TransportSendPkt((HciTrans), (pPacket), (Synchronous))
+#define HCI_TransportStop(HciTrans) \
+ _HCI_TransportStop((HciTrans))
+#define HCI_TransportStart(HciTrans) \
+ _HCI_TransportStart((HciTrans))
+#define HCI_TransportEnableDisableAsyncRecv(HciTrans, Enable) \
+ _HCI_TransportEnableDisableAsyncRecv((HciTrans), (Enable))
+#define HCI_TransportRecvHCIEventSync(HciTrans, pPacket, MaxPollMS) \
+ _HCI_TransportRecvHCIEventSync((HciTrans), (pPacket), (MaxPollMS))
+#define HCI_TransportSetBaudRate(HciTrans, Baud) \
+ _HCI_TransportSetBaudRate((HciTrans), (Baud))
+
+
+extern A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks);
+
+extern A_STATUS ar6000_get_hif_dev(HIF_DEVICE *device, void *config);
+
+extern A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, A_UINT32 scale, A_UINT32 step);
+
+/* get core clock register settings
+ * data: 0 - 40/44MHz
+ * 1 - 80/88MHz
+ * where (5G band/2.4G band)
+ * assume 2.4G band for now
+ */
+extern A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data);
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h b/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h
new file mode 100644
index 000000000000..29c68886d92e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _IEEE80211_IOCTL_H_
+#define _IEEE80211_IOCTL_H_
+
+#include <linux/version.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
+ */
+
+/*
+ * WPA/RSN get/set key request. Specify the key/cipher
+ * type and whether the key is to be used for sending and/or
+ * receiving. The key index should be set only when working
+ * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
+ * Otherwise a unicast/pairwise key is specified by the bssid
+ * (on a station) or mac address (on an ap). They key length
+ * must include any MIC key data; otherwise it should be no
+ more than IEEE80211_KEYBUF_SIZE.
+ */
+struct ieee80211req_key {
+ u_int8_t ik_type; /* key/cipher type */
+ u_int8_t ik_pad;
+ u_int16_t ik_keyix; /* key index */
+ u_int8_t ik_keylen; /* key length in bytes */
+ u_int8_t ik_flags;
+#define IEEE80211_KEY_XMIT 0x01
+#define IEEE80211_KEY_RECV 0x02
+#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */
+ u_int8_t ik_macaddr[IEEE80211_ADDR_LEN];
+ u_int64_t ik_keyrsc; /* key receive sequence counter */
+ u_int64_t ik_keytsc; /* key transmit sequence counter */
+ u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
+};
+/*
+ * Delete a key either by index or address. Set the index
+ * to IEEE80211_KEYIX_NONE when deleting a unicast key.
+ */
+struct ieee80211req_del_key {
+ u_int8_t idk_keyix; /* key index */
+ u_int8_t idk_macaddr[IEEE80211_ADDR_LEN];
+};
+/*
+ * MLME state manipulation request. IEEE80211_MLME_ASSOC
+ * only makes sense when operating as a station. The other
+ * requests can be used when operating as a station or an
+ * ap (to effect a station).
+ */
+struct ieee80211req_mlme {
+ u_int8_t im_op; /* operation to perform */
+#define IEEE80211_MLME_ASSOC 1 /* associate station */
+#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */
+#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */
+#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */
+#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */
+ u_int16_t im_reason; /* 802.11 reason code */
+ u_int8_t im_macaddr[IEEE80211_ADDR_LEN];
+};
+
+struct ieee80211req_addpmkid {
+ u_int8_t pi_bssid[IEEE80211_ADDR_LEN];
+ u_int8_t pi_enable;
+ u_int8_t pi_pmkid[16];
+};
+
+#define AUTH_ALG_OPEN_SYSTEM 0x01
+#define AUTH_ALG_SHARED_KEY 0x02
+#define AUTH_ALG_LEAP 0x04
+
+struct ieee80211req_authalg {
+ u_int8_t auth_alg;
+};
+
+/*
+ * Request to add an IE to a Management Frame
+ */
+enum{
+ IEEE80211_APPIE_FRAME_BEACON = 0,
+ IEEE80211_APPIE_FRAME_PROBE_REQ = 1,
+ IEEE80211_APPIE_FRAME_PROBE_RESP = 2,
+ IEEE80211_APPIE_FRAME_ASSOC_REQ = 3,
+ IEEE80211_APPIE_FRAME_ASSOC_RESP = 4,
+ IEEE80211_APPIE_NUM_OF_FRAME = 5
+};
+
+/*
+ * The Maximum length of the IE that can be added to a Management frame
+ */
+#define IEEE80211_APPIE_FRAME_MAX_LEN 200
+
+struct ieee80211req_getset_appiebuf {
+ u_int32_t app_frmtype; /* management frame type for which buffer is added */
+ u_int32_t app_buflen; /*application supplied buffer length */
+ u_int8_t app_buf[];
+};
+
+/*
+ * The following definitions are used by an application to set filter
+ * for receiving management frames
+ */
+enum {
+ IEEE80211_FILTER_TYPE_BEACON = 0x1,
+ IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2,
+ IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4,
+ IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8,
+ IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10,
+ IEEE80211_FILTER_TYPE_AUTH = 0x20,
+ IEEE80211_FILTER_TYPE_DEAUTH = 0x40,
+ IEEE80211_FILTER_TYPE_DISASSOC = 0x80,
+ IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */
+};
+
+struct ieee80211req_set_filter {
+ u_int32_t app_filterype; /* management frame filter type */
+};
+
+enum {
+ IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */
+ IEEE80211_PARAM_MCASTCIPHER = 5,
+ IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */
+ IEEE80211_PARAM_UCASTCIPHER = 8,
+ IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */
+ IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */
+ IEEE80211_PARAM_ROAMING = 12, /* roaming mode */
+ IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */
+ IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */
+ IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */
+ IEEE80211_PARAM_WAPI = 16, /* WAPI policy from wapid */
+};
+
+/*
+ * Values for IEEE80211_PARAM_WPA
+ */
+#define WPA_MODE_WPA1 1
+#define WPA_MODE_WPA2 2
+#define WPA_MODE_AUTO 3
+#define WPA_MODE_NONE 4
+
+struct ieee80211req_wpaie {
+ u_int8_t wpa_macaddr[IEEE80211_ADDR_LEN];
+ u_int8_t wpa_ie[IEEE80211_MAX_IE];
+ u_int8_t rsn_ie[IEEE80211_MAX_IE];
+};
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
+#define IW_ENCODE_ALG_PMK 4
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IEEE80211_IOCTL_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h
new file mode 100644
index 000000000000..23d81c2bc3da
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h
@@ -0,0 +1,361 @@
+/*
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef _OSAPI_LINUX_H_
+#define _OSAPI_LINUX_H_
+
+#ifdef __KERNEL__
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+#include <linux/jiffies.h>
+#endif
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#ifdef KERNEL_2_4
+#include <asm/arch/irq.h>
+#include <asm/irq.h>
+#endif
+
+#include <linux/cache.h>
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK __attribute__ ((packed))
+#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK __ATTRIB_PACK
+
+/*
+ * Endianes macros
+ */
+#define A_BE2CPU8(x) ntohb(x)
+#define A_BE2CPU16(x) ntohs(x)
+#define A_BE2CPU32(x) ntohl(x)
+
+#define A_LE2CPU8(x) (x)
+#define A_LE2CPU16(x) (x)
+#define A_LE2CPU32(x) (x)
+
+#define A_CPU2BE8(x) htonb(x)
+#define A_CPU2BE16(x) htons(x)
+#define A_CPU2BE32(x) htonl(x)
+
+#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len))
+#define A_MEMZERO(addr, len) memset(addr, 0, len)
+#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size) kmalloc((size), GFP_KERNEL)
+#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC)
+#define A_FREE(addr) kfree(addr)
+#define A_PRINTF(args...) printk(KERN_ALERT args)
+#define A_PRINTF_LOG(args...) printk(args)
+#define A_SPRINTF(buf, args...) sprintf (buf, args)
+
+/* Mutual Exclusion */
+typedef spinlock_t A_MUTEX_T;
+#define A_MUTEX_INIT(mutex) spin_lock_init(mutex)
+#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex)
+#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex)
+#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */
+#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */
+
+/* Get current time in ms adding a constant offset (in ms) */
+#define A_GET_MS(offset) \
+ (jiffies + ((offset) / 1000) * HZ)
+
+/*
+ * Timer Functions
+ */
+#define A_MDELAY(msecs) mdelay(msecs)
+typedef struct timer_list A_TIMER;
+
+#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \
+ init_timer(pTimer); \
+ (pTimer)->function = (pFunction); \
+ (pTimer)->data = (unsigned long)(pArg); \
+} while (0)
+
+/*
+ * Start a Timer that elapses after 'periodMSec' milli-seconds
+ * Support is provided for a one-shot timer. The 'repeatFlag' is
+ * ignored.
+ */
+#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \
+ if (repeatFlag) { \
+ printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \
+ panic("Timer Repeat"); \
+ } \
+ mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \
+} while (0)
+
+/*
+ * Cancel the Timer.
+ */
+#define A_UNTIMEOUT(pTimer) do { \
+ del_timer((pTimer)); \
+} while (0)
+
+#define A_DELETE_TIMER(pTimer) do { \
+} while (0)
+
+/*
+ * Wait Queue related functions
+ */
+typedef wait_queue_head_t A_WAITQUEUE_HEAD;
+#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head)
+#ifndef wait_event_interruptible_timeout
+#define __wait_event_interruptible_timeout(wq, condition, ret) \
+do { \
+ wait_queue_t __wait; \
+ init_waitqueue_entry(&__wait, current); \
+ \
+ add_wait_queue(&wq, &__wait); \
+ for (;;) { \
+ set_current_state(TASK_INTERRUPTIBLE); \
+ if (condition) \
+ break; \
+ if (!signal_pending(current)) { \
+ ret = schedule_timeout(ret); \
+ if (!ret) \
+ break; \
+ continue; \
+ } \
+ ret = -ERESTARTSYS; \
+ break; \
+ } \
+ current->state = TASK_RUNNING; \
+ remove_wait_queue(&wq, &__wait); \
+} while (0)
+
+#define wait_event_interruptible_timeout(wq, condition, timeout) \
+({ \
+ long __ret = timeout; \
+ if (!(condition)) \
+ __wait_event_interruptible_timeout(wq, condition, __ret); \
+ __ret; \
+})
+#endif /* wait_event_interruptible_timeout */
+
+#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
+ wait_event_interruptible_timeout(head, condition, timeout); \
+} while (0)
+
+#define A_WAKE_UP(head) wake_up(head)
+
+#ifdef DEBUG
+extern unsigned int panic_on_assert;
+#define A_ASSERT(expr) \
+ if (!(expr)) { \
+ printk(KERN_ALERT"Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#expr); \
+ if (panic_on_assert) panic(#expr); \
+ }
+#else
+#define A_ASSERT(expr)
+#endif /* DEBUG */
+
+#ifdef ANDROID_ENV
+struct firmware;
+int android_request_firmware(const struct firmware **firmware_p, const char *filename,
+ struct device *device);
+void android_release_firmware(const struct firmware *firmware);
+#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) android_request_firmware(_ppf, _pfile, _dev)
+#define A_RELEASE_FIRMWARE(_pf) android_release_firmware(_pf)
+#else
+#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) request_firmware(_ppf, _pfile, _dev)
+#define A_RELEASE_FIRMWARE(_pf) release_firmware(_pf)
+#endif
+
+/*
+ * Initialization of the network buffer subsystem
+ */
+#define A_NETBUF_INIT()
+
+/*
+ * Network buffer queue support
+ */
+typedef struct sk_buff_head A_NETBUF_QUEUE_T;
+
+#define A_NETBUF_QUEUE_INIT(q) \
+ a_netbuf_queue_init(q)
+
+#define A_NETBUF_ENQUEUE(q, pkt) \
+ a_netbuf_enqueue((q), (pkt))
+#define A_NETBUF_PREQUEUE(q, pkt) \
+ a_netbuf_prequeue((q), (pkt))
+#define A_NETBUF_DEQUEUE(q) \
+ (a_netbuf_dequeue(q))
+#define A_NETBUF_QUEUE_SIZE(q) \
+ a_netbuf_queue_size(q)
+#define A_NETBUF_QUEUE_EMPTY(q) \
+ a_netbuf_queue_empty(q)
+
+/*
+ * Network buffer support
+ */
+#define A_NETBUF_ALLOC(size) \
+ a_netbuf_alloc(size)
+#define A_NETBUF_ALLOC_RAW(size) \
+ a_netbuf_alloc_raw(size)
+#define A_NETBUF_FREE(bufPtr) \
+ a_netbuf_free(bufPtr)
+#define A_NETBUF_DATA(bufPtr) \
+ a_netbuf_to_data(bufPtr)
+#define A_NETBUF_LEN(bufPtr) \
+ a_netbuf_to_len(bufPtr)
+#define A_NETBUF_PUSH(bufPtr, len) \
+ a_netbuf_push(bufPtr, len)
+#define A_NETBUF_PUT(bufPtr, len) \
+ a_netbuf_put(bufPtr, len)
+#define A_NETBUF_TRIM(bufPtr,len) \
+ a_netbuf_trim(bufPtr, len)
+#define A_NETBUF_PULL(bufPtr, len) \
+ a_netbuf_pull(bufPtr, len)
+#define A_NETBUF_HEADROOM(bufPtr)\
+ a_netbuf_headroom(bufPtr)
+#define A_NETBUF_SETLEN(bufPtr,len) \
+ a_netbuf_setlen(bufPtr, len)
+
+/* Add data to end of a buffer */
+#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \
+ a_netbuf_put_data(bufPtr, srcPtr, len)
+
+/* Add data to start of the buffer */
+#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \
+ a_netbuf_push_data(bufPtr, srcPtr, len)
+
+/* Remove data at start of the buffer */
+#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \
+ a_netbuf_pull_data(bufPtr, dstPtr, len)
+
+/* Remove data from the end of the buffer */
+#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \
+ a_netbuf_trim_data(bufPtr, dstPtr, len)
+
+/* View data as "size" contiguous bytes of type "t" */
+#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \
+ (t )( ((struct skbuf *)(bufPtr))->data)
+
+/* return the beginning of the headroom for the buffer */
+#define A_NETBUF_HEAD(bufPtr) \
+ ((((struct sk_buff *)(bufPtr))->head))
+
+/*
+ * OS specific network buffer access routines
+ */
+void *a_netbuf_alloc(int size);
+void *a_netbuf_alloc_raw(int size);
+void a_netbuf_free(void *bufPtr);
+void *a_netbuf_to_data(void *bufPtr);
+A_UINT32 a_netbuf_to_len(void *bufPtr);
+A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len);
+A_INT32 a_netbuf_headroom(void *bufPtr);
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt);
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt);
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q);
+
+/*
+ * Kernel v.s User space functions
+ */
+A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
+A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
+
+/* In linux, WLAN Rx and Tx run in different contexts, so no need to check
+ * for any commands/data queued for WLAN */
+#define A_CHECK_DRV_TX()
+
+#define A_GET_CACHE_LINE_BYTES() L1_CACHE_BYTES
+
+static inline void *A_ALIGN_TO_CACHE_LINE(void *ptr) {
+ return (void *)L1_CACHE_ALIGN((A_UINT32)ptr);
+}
+
+#else /* __KERNEL__ */
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK __attribute__ ((packed))
+#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK __ATTRIB_PACK
+
+#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len))
+#define A_MEMZERO(addr, len) memset((addr), 0, (len))
+#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size) malloc(size)
+#define A_FREE(addr) free(addr)
+
+#ifdef ANDROID
+#ifndef err
+#include <errno.h>
+#define err(_s, args...) do { \
+ fprintf(stderr, "%s: line %d ", __FILE__, __LINE__); \
+ fprintf(stderr, args); fprintf(stderr, ": %d\n", errno); \
+ exit(_s); } while (0)
+#endif
+#else
+#include <err.h>
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _OSAPI_LINUX_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h b/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h
new file mode 100644
index 000000000000..97e090f95481
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_config.h" company="Atheros">
+// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains the tunable configuration items for the WLAN module
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _HOST_WLAN_CONFIG_H_
+#define _HOST_WLAN_CONFIG_H_
+
+/* Include definitions here that can be used to tune the WLAN module behavior.
+ * Different customers can tune the behavior as per their needs, here.
+ */
+
+/* This configuration item when defined will consider the barker preamble
+ * mentioned in the ERP IE of the beacons from the AP to determine the short
+ * preamble support sent in the (Re)Assoc request frames.
+ */
+#define WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 0
+
+/* This config item when defined will not send the power module state transition
+ * failure events that happen during scan, to the host.
+ */
+#define WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 0
+
+/*
+ * This configuration item enable/disable keepalive support.
+ * Keepalive support: In the absence of any data traffic to AP, null
+ * frames will be sent to the AP at periodic interval, to keep the association
+ * active. This configuration item defines the periodic interval.
+ * Use value of zero to disable keepalive support
+ * Default: 60 seconds
+ */
+#define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
+
+
+#endif /* _HOST_WLAN_CONFIG_H_ */
diff --git a/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h
new file mode 100644
index 000000000000..ab9a9fc0d0fd
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ */
+
+#ifndef _WMI_FILTER_LINUX_H_
+#define _WMI_FILTER_LINUX_H_
+
+/*
+ * sioctl_filter - Standard ioctl
+ * pioctl_filter - Priv ioctl
+ * xioctl_filter - eXtended ioctl
+ *
+ * ---- Possible values for the WMI filter ---------------
+ * (0) - Block this cmd always (or) not implemented
+ * (INFRA_NETWORK) - Allow this cmd only in STA mode
+ * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode
+ * (AP_NETWORK) - Allow this cmd only in AP mode
+ * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode
+ * (ADHOC_NETWORK | AP_NETWORK) - Block this cmd in STA mode
+ * (INFRA_NETWORK | AP_NETWORK) - Block this cmd in IBSS mode
+ * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set
+ * (0xFF) - Allow this cmd always irrespective of mode
+ */
+
+A_UINT8 sioctl_filter[] = {
+(AP_NETWORK), /* SIOCSIWCOMMIT 0x8B00 */
+(0xFF), /* SIOCGIWNAME 0x8B01 */
+(0), /* SIOCSIWNWID 0x8B02 */
+(0), /* SIOCGIWNWID 0x8B03 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWFREQ 0x8B04 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWFREQ 0x8B05 */
+(0xFF), /* SIOCSIWMODE 0x8B06 */
+(0xFF), /* SIOCGIWMODE 0x8B07 */
+(0), /* SIOCSIWSENS 0x8B08 */
+(0), /* SIOCGIWSENS 0x8B09 */
+(0), /* SIOCSIWRANGE 0x8B0A */
+(0xFF), /* SIOCGIWRANGE 0x8B0B */
+(0), /* SIOCSIWPRIV 0x8B0C */
+(0), /* SIOCGIWPRIV 0x8B0D */
+(0), /* SIOCSIWSTATS 0x8B0E */
+(0), /* SIOCGIWSTATS 0x8B0F */
+(0), /* SIOCSIWSPY 0x8B10 */
+(0), /* SIOCGIWSPY 0x8B11 */
+(0), /* SIOCSIWTHRSPY 0x8B12 */
+(0), /* SIOCGIWTHRSPY 0x8B13 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWAP 0x8B14 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWAP 0x8B15 */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWMLME 0X8B16 */
+#else
+(0), /* Dummy 0 */
+#endif /* LINUX_VERSION_CODE */
+(0), /* SIOCGIWAPLIST 0x8B17 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWSCAN 0x8B18 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWSCAN 0x8B19 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWESSID 0x8B1A */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWESSID 0x8B1B */
+(0), /* SIOCSIWNICKN 0x8B1C */
+(0), /* SIOCGIWNICKN 0x8B1D */
+(0), /* Dummy 0 */
+(0), /* Dummy 0 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWRATE 0x8B20 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWRATE 0x8B21 */
+(0), /* SIOCSIWRTS 0x8B22 */
+(0), /* SIOCGIWRTS 0x8B23 */
+(0), /* SIOCSIWFRAG 0x8B24 */
+(0), /* SIOCGIWFRAG 0x8B25 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWTXPOW 0x8B26 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWTXPOW 0x8B27 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWRETRY 0x8B28 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWRETRY 0x8B29 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWENCODE 0x8B2A */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWENCODE 0x8B2B */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWPOWER 0x8B2C */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWPOWER 0x8B2D */
+};
+
+
+
+A_UINT8 pioctl_filter[] = {
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) */
+(AP_NETWORK), /* IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) */
+(INFRA_NETWORK), /* IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) */
+(0), /* IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) */
+(0), /* (SIOCIWFIRSTPRIV+6) */
+(0), /* (SIOCIWFIRSTPRIV+7) */
+(0), /* (SIOCIWFIRSTPRIV+8) */
+(0), /* (SIOCIWFIRSTPRIV+9) */
+(0), /* IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) */
+(0xFF), /* AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) */
+(INFRA_NETWORK), /* AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/
+(0xFF), /* AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) */
+(ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) */
+};
+
+
+
+A_UINT8 xioctl_filter[] = {
+(0xFF), /* Dummy 0 */
+(0xFF), /* AR6000_XIOCTL_BMI_DONE 1 */
+(0xFF), /* AR6000_XIOCTL_BMI_READ_MEMORY 2 */
+(0xFF), /* AR6000_XIOCTL_BMI_WRITE_MEMORY 3 */
+(0xFF), /* AR6000_XIOCTL_BMI_EXECUTE 4 */
+(0xFF), /* AR6000_XIOCTL_BMI_SET_APP_START 5 */
+(0xFF), /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 */
+(0xFF), /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 */
+(0xFF), /* AR6000_XIOCTL_BMI_TEST 8 */
+(0xFF), /* AR6000_XIOCTL_UNUSED9 9 */
+(0xFF), /* AR6000_XIOCTL_UNUSED10 10 */
+(0xFF), /* AR6000_XIOCTL_UNUSED11 11 */
+(0xFF), /* AR6000_XIOCTL_FORCE_TARGET_RESET 12 */
+(0xFF), /* AR6000_XIOCTL_HTC_RAW_OPEN 13 */
+(0xFF), /* AR6000_XIOCTL_HTC_RAW_CLOSE 14 */
+(0xFF), /* AR6000_XIOCTL_HTC_RAW_READ 15 */
+(0xFF), /* AR6000_XIOCTL_HTC_RAW_WRITE 16 */
+(0xFF), /* AR6000_XIOCTL_CHECK_TARGET_READY 17 */
+(0xFF), /* AR6000_XIOCTL_GPIO_OUTPUT_SET 18 */
+(0xFF), /* AR6000_XIOCTL_GPIO_INPUT_GET 19 */
+(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_SET 20 */
+(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_GET 21 */
+(0xFF), /* AR6000_XIOCTL_GPIO_INTR_ACK 22 */
+(0xFF), /* AR6000_XIOCTL_GPIO_INTR_WAIT 23 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_ADHOC_BSSID 24 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_OPT_MODE 25 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_OPT_SEND_FRAME 26 */
+(ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_SET_BEACON_INTVAL 27 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETAUTHALG 28 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_MAX_SP 30 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 */
+(0xFF), /* AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 */
+(0xFF), /* AR6000_XIOCTL_TCMD_CONT_TX 38 */
+(0xFF), /* AR6000_XIOCTL_TCMD_CONT_RX 39 */
+(0xFF), /* AR6000_XIOCTL_TCMD_PM 40 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_STARTSCAN 41 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SETFIXRATES 42 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GETFIXRATES 43 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_CLR_RSSISNR 45 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_RTS 47 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_AUTHMODE 49 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WMM 51 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 */
+(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GET_RD 54 */
+(0xFF), /* AR6000_XIOCTL_DIAG_READ 55 */
+(0xFF), /* AR6000_XIOCTL_DIAG_WRITE 56 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_TXOP 57 */
+(INFRA_NETWORK), /* AR6000_XIOCTL_USER_SETKEYS 58 */
+(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 */
+(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 */
+(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 */
+(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 */
+(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 */
+(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 */
+(0xFF), /* AR6000_XIOCTL_WMI_SET_APPIE 65 */
+(0xFF), /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 */
+(0xFF), /* AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 */
+(0xFF), /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 */
+(0xFF), /* Dummy 69 */
+(0xFF), /* AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_STATUS 71 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WOW_MODE 74 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_WOW_LIST 75 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 */
+(0xFF), /* AR6000_XIOCTL_TARGET_INFO 78 */
+(0xFF), /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 */
+(0xFF), /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 */
+(0xFF), /* Dummy 85 */
+(0xFF), /* Dummy 86 */
+(0xFF), /* Dummy 87 */
+(0xFF), /* Dummy 88 */
+(0xFF), /* Dummy 89 */
+(0xFF), /* AR6000_XIOCTL_UNUSED90 90 */
+(0xFF), /* AR6000_XIOCTL_BMI_LZ_STREAM_START 91 */
+(0xFF), /* AR6000_XIOCTL_BMI_LZ_DATA 92 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_CFG 93 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_ADDR_SET 94 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_START 95 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_STOP 96 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_COUNT_GET 97 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ABORT_SCAN 98 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STA_LIST 99 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_HIDDEN_SSID 100 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_NUM_STA 101 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_MAC 102 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_ACL_LIST 103 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_COMMIT_CONFIG 104 */
+(AP_NETWORK), /* IEEE80211_IOCTL_GETWPAIE 105 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_CONN_INACT_TIME 106 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 */
+(AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_COUNTRY 108 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_DTIM 109 */
+(0xFF), /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 */
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_IP 111 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_POLICY 112 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 */
+(0xFF), /* AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO 114 */
+(0xFF), /* AR6000_XIOCTL_MODULE_DEBUG_SET_MASK 115 */
+(0xFF), /* AR6000_XIOCTL_MODULE_DEBUG_GET_MASK 116 */
+(0xFF), /* AR6000_XIOCTL_DUMP_RCV_AGGR_STATS 117 */
+(0xFF), /* AR6000_XIOCTL_SET_HT_CAP 118 */
+(0xFF), /* AR6000_XIOCTL_SET_HT_OP 119 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STAT 120 */
+(0xFF), /* AR6000_XIOCTL_SET_TX_SELECT_RATES 121 */
+(0xFF), /* AR6000_XIOCTL_SETUP_AGGR 122 */
+(0xFF), /* AR6000_XIOCTL_ALLOW_AGGR 123 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_HIDDEN_SSID 124 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_COUNTRY 125 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_WMODE 126 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_DTIM 127 */
+(AP_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_AP_GET_BINTVL 128 */
+(0xFF), /* AR6000_XIOCTL_AP_GET_RTS 129 */
+(0xFF), /* AR6000_XIOCTL_DELE_AGGR 130 */
+(0xFF), /* AR6000_XIOCTL_FETCH_TARGET_REGS 131 */
+(0xFF), /* AR6000_XIOCTL_HCI_CMD 132 */
+(0xFF), /* AR6000_XIOCTL_ACL_DATA 133 */
+(0xFF), /* AR6000_XIOCTL_WLAN_CONN_PRECEDENCE 134 */
+(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_11BG_RATESET 135 */
+(0xFF),
+(0xFF),
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT 138*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV 139*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG 140*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG 141*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG 142*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG 143*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG 144*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS 145*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG 146*/
+(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_BTCOEX_GET_STATS 147*/
+
+};
+
+#endif /*_WMI_FILTER_LINUX_H_*/
diff --git a/drivers/net/wireless/ath6kl/os/linux/ioctl.c b/drivers/net/wireless/ath6kl/os/linux/ioctl.c
new file mode 100644
index 000000000000..902f0701dabd
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/ioctl.c
@@ -0,0 +1,4559 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#include "ar6000_drv.h"
+#include "ieee80211_ioctl.h"
+#include "ar6kap_common.h"
+#include "targaddrs.h"
+#include "a_hci.h"
+#include "wlan_config.h"
+
+extern int enablerssicompensation;
+A_UINT32 tcmdRxFreq;
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+extern int tspecCompliance;
+extern int bmienable;
+extern int bypasswmi;
+extern int loghci;
+
+static int
+ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ /* currently assume only roam times are required */
+ if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
+ return -EIO;
+ }
+
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_ROAM_CTRL_CMD cmd;
+ A_UINT8 size = sizeof(cmd);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
+ if (cmd.info.bssBiasInfo.numBss > 1) {
+ size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
+ }
+ }
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
+ A_UINT8 size = sizeof(cmd);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_set_qos_supp(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_QOS_SUPP_CMD cmd;
+ A_STATUS ret;
+
+ if ((dev->flags & IFF_UP) != IFF_UP) {
+ return -EIO;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+
+ ret = wmi_set_qos_supp_cmd(ar->arWmi, cmd.status);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_WMM_CMD cmd;
+ A_STATUS ret;
+
+ if ((dev->flags & IFF_UP) != IFF_UP) {
+ return -EIO;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+
+ if (cmd.status == WMI_WMM_ENABLED) {
+ ar->arWmmEnabled = TRUE;
+ } else {
+ ar->arWmmEnabled = FALSE;
+ }
+
+ ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_WMM_TXOP_CMD cmd;
+ A_STATUS ret;
+
+ if ((dev->flags & IFF_UP) != IFF_UP) {
+ return -EIO;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+
+ ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_STATUS ret = 0;
+
+ if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
+ &ar->arRegCode, sizeof(ar->arRegCode)))
+ ret = -EFAULT;
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_AP_SET_COUNTRY_CMD cmd;
+ A_STATUS ret;
+
+ if ((dev->flags & IFF_UP) != IFF_UP) {
+ return -EIO;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+
+ ret = wmi_set_country(ar->arWmi, cmd.countryCode);
+ A_MEMCPY(ar->ap_country_code, cmd.countryCode, 3);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+
+/* Get power mode command */
+static int
+ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_POWER_MODE_CMD power_mode;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
+ if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
+ ret = -EFAULT;
+ }
+
+ return ret;
+}
+
+
+static int
+ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) {
+ A_PRINTF("ERROR: Only wmode is allowed in AP mode\n");
+ return -EIO;
+ }
+
+ if (cmd.numChannels > 1) {
+ cmdp = A_MALLOC(130);
+ if (copy_from_user(cmdp, rq->ifr_data,
+ sizeof (*cmdp) +
+ ((cmd.numChannels - 1) * sizeof(A_UINT16))))
+ {
+ kfree(cmdp);
+ return -EFAULT;
+ }
+ } else {
+ cmdp = &cmd;
+ }
+
+ if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
+ ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
+ {
+ ret = -EINVAL;
+ }
+
+ if (!ret &&
+ (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
+ cmdp->numChannels, cmdp->channelList)
+ != A_OK))
+ {
+ ret = -EIO;
+ }
+
+ if (cmd.numChannels > 1) {
+ kfree(cmdp);
+ }
+
+ ar->ap_wmode = cmdp->phyMode;
+ /* Set the profile change flag to allow a commit cmd */
+ ar->ap_profile_flag = 1;
+
+ return ret;
+}
+
+
+static int
+ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
+{
+#define SWAP_THOLD(thold1, thold2) do { \
+ USER_RSSI_THOLD tmpThold; \
+ tmpThold.tag = thold1.tag; \
+ tmpThold.rssi = thold1.rssi; \
+ thold1.tag = thold2.tag; \
+ thold1.rssi = thold2.rssi; \
+ thold2.tag = tmpThold.tag; \
+ thold2.rssi = tmpThold.rssi; \
+} while (0)
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+ USER_RSSI_PARAMS rssiParams;
+ A_INT32 i, j;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
+ return -EFAULT;
+ }
+ cmd.weight = rssiParams.weight;
+ cmd.pollTime = rssiParams.pollTime;
+
+ A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map));
+ /*
+ * only 6 elements, so use bubble sorting, in ascending order
+ */
+ for (i = 5; i > 0; i--) {
+ for (j = 0; j < i; j++) { /* above tholds */
+ if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
+ SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
+ } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
+ return EFAULT;
+ }
+ }
+ }
+ for (i = 11; i > 6; i--) {
+ for (j = 6; j < i; j++) { /* below tholds */
+ if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
+ SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
+ } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
+ return EFAULT;
+ }
+ }
+ }
+
+#ifdef DEBUG
+ for (i = 0; i < 12; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("thold[%d].tag: %d, thold[%d].rssi: %d \n",
+ i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi));
+ }
+#endif
+
+ if (enablerssicompensation) {
+ for (i = 0; i < 6; i++)
+ ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, TRUE);
+ for (i = 6; i < 12; i++)
+ ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, FALSE);
+ }
+
+ cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi;
+ cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi;
+ cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi;
+ cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi;
+ cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi;
+ cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi;
+ cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi;
+ cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi;
+ cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi;
+ cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi;
+ cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi;
+ cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi;
+
+ if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+
+static int
+ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_PROBED_SSID_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
+ cmd.ssid) != A_OK)
+ {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_ADD_BAD_AP_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
+ return -EIO;
+ }
+
+ if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
+ /*
+ * This is a delete badAP.
+ */
+ if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
+ ret = -EIO;
+ }
+ } else {
+ if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
+ ret = -EIO;
+ }
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_CREATE_PSTREAM_CMD cmd;
+ A_STATUS ret;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
+ if (ret == A_OK)
+ ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_DELETE_PSTREAM_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ struct ar6000_queuereq qreq;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if( copy_from_user(&qreq, rq->ifr_data,
+ sizeof(struct ar6000_queuereq)))
+ return -EFAULT;
+
+ qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
+
+ if (copy_to_user(rq->ifr_data, &qreq,
+ sizeof(struct ar6000_queuereq)))
+ {
+ ret = -EFAULT;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
+ struct ifreq *rq, A_UINT8 *data, A_UINT32 len)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT32 buf[4+TCMD_MAX_RATES];
+ int ret = 0;
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ ar->tcmdRxReport = 0;
+ if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ buf[0] = ar->tcmdRxTotalPkt;
+ buf[1] = ar->tcmdRxRssi;
+ buf[2] = ar->tcmdRxcrcErrPkt;
+ buf[3] = ar->tcmdRxsecErrPkt;
+ A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32)), ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt));
+ A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32))+(TCMD_MAX_RATES *sizeof(A_UINT16)), ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+
+ if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
+ ret = -EFAULT;
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+void
+ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
+
+ if (enablerssicompensation) {
+ rx_rep->u.report.rssiInDBm = rssi_compensation_calc_tcmd(tcmdRxFreq, rx_rep->u.report.rssiInDBm,rx_rep->u.report.totalPkt);
+ }
+
+
+ ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
+ ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
+ ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt;
+ ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt;
+ ar->tcmdRxReport = 1;
+ A_MEMZERO(ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt));
+ A_MEMZERO(ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+ A_MEMCPY(ar->tcmdRateCnt, rx_rep->u.report.rateCnt, sizeof(ar->tcmdRateCnt));
+ A_MEMCPY(ar->tcmdRateCntShortGuard, rx_rep->u.report.rateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
+
+ wake_up(&arEvent);
+}
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+static int
+ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_TARGET_ERROR_REPORT_BITMASK cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
+
+ return (ret==0 ? ret : -EINVAL);
+}
+
+static int
+ar6000_clear_target_stats(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ A_MEMZERO(pStats, sizeof(TARGET_STATS));
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ return ret;
+}
+
+static int
+ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ TARGET_STATS_CMD cmd;
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ int ret = 0;
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ ar->statsUpdatePending = TRUE;
+
+ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+ ret = -EFAULT;
+ }
+
+ if (cmd.clearStats == 1) {
+ ret = ar6000_clear_target_stats(dev);
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_get_ap_stats(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_AP_MODE_STAT cmd;
+ WMI_AP_MODE_STAT *pStats = &ar->arAPStats;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+ if (cmd.action == AP_CLEAR_STATS) {
+ A_UINT8 i;
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ for(i = 0; i < AP_MAX_NUM_STA; i++) {
+ pStats->sta[i].tx_bytes = 0;
+ pStats->sta[i].tx_pkts = 0;
+ pStats->sta[i].tx_error = 0;
+ pStats->sta[i].tx_discard = 0;
+ pStats->sta[i].rx_bytes = 0;
+ pStats->sta[i].rx_pkts = 0;
+ pStats->sta[i].rx_error = 0;
+ pStats->sta[i].rx_discard = 0;
+ }
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ return ret;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ ar->statsUpdatePending = TRUE;
+
+ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+ ret = -EFAULT;
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_ACCESS_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_access_params_cmd(ar->arWmi, cmd.ac, cmd.txop, cmd.eCWmin, cmd.eCWmax,
+ cmd.aifsn) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_DISC_TIMEOUT_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_VOICE_PKT_SIZE_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_MAX_SP_LEN_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+
+static int
+ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BT_STATUS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BT_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_fe_ant_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_FE_ANT_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_btinquiry_page_config_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_sco_config_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_SCO_CONFIG_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_sco_config_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_a2dp_config_cmd(struct net_device * dev,
+ char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_A2DP_CONFIG_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_a2dp_config_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_aclcoex_config_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_aclcoex_config_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar60000_xioctl_set_btcoex_debug_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_DEBUG_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_debug_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return(ret);
+}
+
+static int
+ar6000_xioctl_set_btcoex_bt_operating_status_cmd(struct net_device * dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_btcoex_bt_operating_status_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+ return(ret);
+}
+
+static int
+ar6000_xioctl_get_btcoex_config_cmd(struct net_device * dev, char * userdata,
+ struct ifreq *rq)
+{
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ AR6000_BTCOEX_CONFIG btcoexConfig;
+ WMI_BTCOEX_CONFIG_EVENT *pbtcoexConfigEv = &ar->arBtcoexConfig;
+
+ int ret = 0;
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (copy_from_user(&btcoexConfig.configCmd, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
+ return -EFAULT;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (wmi_get_btcoex_config_cmd(ar->arWmi, (WMI_GET_BTCOEX_CONFIG_CMD *)&btcoexConfig.configCmd) != A_OK)
+ {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ ar->statsUpdatePending = TRUE;
+
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret && copy_to_user(btcoexConfig.configEvent, pbtcoexConfigEv, sizeof(WMI_BTCOEX_CONFIG_EVENT))) {
+ ret = -EFAULT;
+ }
+ up(&ar->arSem);
+ return ret;
+}
+
+static int
+ar6000_xioctl_get_btcoex_stats_cmd(struct net_device * dev, char * userdata, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ AR6000_BTCOEX_STATS btcoexStats;
+ WMI_BTCOEX_STATS_EVENT *pbtcoexStats = &ar->arBtcoexStats;
+ int ret = 0;
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (copy_from_user(&btcoexStats.statsEvent, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
+ return -EFAULT;
+ }
+
+ if (wmi_get_btcoex_stats_cmd(ar->arWmi) != A_OK)
+ {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ ar->statsUpdatePending = TRUE;
+
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret && copy_to_user(btcoexStats.statsEvent, pbtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT))) {
+ ret = -EFAULT;
+ }
+
+
+ up(&ar->arSem);
+
+ return(ret);
+}
+
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results;
+/* gpio_reg_results and gpio_data_available are protected by arSem */
+static struct ar6000_gpio_register_cmd_s gpio_reg_results;
+static A_BOOL gpio_data_available; /* Requested GPIO data available */
+static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
+static A_BOOL gpio_ack_received; /* GPIO ack was received */
+
+/* Host-side initialization for General Purpose I/O support */
+void ar6000_gpio_init(void)
+{
+ gpio_intr_available = FALSE;
+ gpio_data_available = FALSE;
+ gpio_ack_received = FALSE;
+}
+
+/*
+ * Called when a GPIO interrupt is received from the Target.
+ * intr_values shows which GPIO pins have interrupted.
+ * input_values shows a recent value of GPIO pins.
+ */
+void
+ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
+{
+ gpio_intr_results.intr_mask = intr_mask;
+ gpio_intr_results.input_values = input_values;
+ *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
+ wake_up(&arEvent);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
+ * call.
+ */
+void
+ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
+{
+ gpio_reg_results.gpioreg_id = reg_id;
+ gpio_reg_results.value = value;
+ *((volatile A_BOOL *)&gpio_data_available) = TRUE;
+ wake_up(&arEvent);
+}
+
+/*
+ * This is called when an acknowledgement is received from the Target
+ * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
+ * call.
+ */
+void
+ar6000_gpio_ack_rx(void)
+{
+ gpio_ack_received = TRUE;
+ wake_up(&arEvent);
+}
+
+A_STATUS
+ar6000_gpio_output_set(struct net_device *dev,
+ A_UINT32 set_mask,
+ A_UINT32 clear_mask,
+ A_UINT32 enable_mask,
+ A_UINT32 disable_mask)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ gpio_ack_received = FALSE;
+ return wmi_gpio_output_set(ar->arWmi,
+ set_mask, clear_mask, enable_mask, disable_mask);
+}
+
+static A_STATUS
+ar6000_gpio_input_get(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+ return wmi_gpio_input_get(ar->arWmi);
+}
+
+static A_STATUS
+ar6000_gpio_register_set(struct net_device *dev,
+ A_UINT32 gpioreg_id,
+ A_UINT32 value)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ gpio_ack_received = FALSE;
+ return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
+}
+
+static A_STATUS
+ar6000_gpio_register_get(struct net_device *dev,
+ A_UINT32 gpioreg_id)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+ return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
+}
+
+static A_STATUS
+ar6000_gpio_intr_ack(struct net_device *dev,
+ A_UINT32 ack_mask)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ gpio_intr_available = FALSE;
+ return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static struct prof_count_s prof_count_results;
+static A_BOOL prof_count_available; /* Requested GPIO data available */
+
+static A_STATUS
+prof_count_get(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ *((volatile A_BOOL *)&prof_count_available) = FALSE;
+ return wmi_prof_count_get_cmd(ar->arWmi);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous prof_count_get call.
+ */
+void
+prof_count_rx(A_UINT32 addr, A_UINT32 count)
+{
+ prof_count_results.addr = addr;
+ prof_count_results.count = count;
+ *((volatile A_BOOL *)&prof_count_available) = TRUE;
+ wake_up(&arEvent);
+}
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+
+static A_STATUS
+ar6000_create_acl_data_osbuf(struct net_device *dev, A_UINT8 *userdata, void **p_osbuf)
+{
+ void *osbuf = NULL;
+ A_UINT8 tmp_space[8];
+ HCI_ACL_DATA_PKT *acl;
+ A_UINT8 hdr_size, *datap=NULL;
+ A_STATUS ret = A_OK;
+
+ /* ACL is in data path. There is a need to create pool
+ * mechanism for allocating and freeing NETBUFs - ToDo later.
+ */
+
+ *p_osbuf = NULL;
+ acl = (HCI_ACL_DATA_PKT *)tmp_space;
+ hdr_size = sizeof(acl->hdl_and_flags) + sizeof(acl->data_len);
+
+ do {
+ if (a_copy_from_user(acl, userdata, hdr_size)) {
+ ret = A_EFAULT;
+ break;
+ }
+
+ osbuf = A_NETBUF_ALLOC(hdr_size + acl->data_len);
+ if (osbuf == NULL) {
+ ret = A_NO_MEMORY;
+ break;
+ }
+ A_NETBUF_PUT(osbuf, hdr_size + acl->data_len);
+ datap = (A_UINT8 *)A_NETBUF_DATA(osbuf);
+
+ /* Real copy to osbuf */
+ acl = (HCI_ACL_DATA_PKT *)(datap);
+ A_MEMCPY(acl, tmp_space, hdr_size);
+ if (a_copy_from_user(acl->data, userdata + hdr_size, acl->data_len)) {
+ ret = A_EFAULT;
+ break;
+ }
+ } while(FALSE);
+
+ if (ret == A_OK) {
+ *p_osbuf = osbuf;
+ } else {
+ A_NETBUF_FREE(osbuf);
+ }
+ return ret;
+}
+
+
+
+int
+ar6000_ioctl_ap_setparam(AR_SOFTC_T *ar, int param, int value)
+{
+ int ret=0;
+
+ switch(param) {
+ case IEEE80211_PARAM_WPA:
+ switch (value) {
+ case WPA_MODE_WPA1:
+ ar->arAuthMode = WPA_AUTH;
+ break;
+ case WPA_MODE_WPA2:
+ ar->arAuthMode = WPA2_AUTH;
+ break;
+ case WPA_MODE_AUTO:
+ ar->arAuthMode = WPA_AUTH | WPA2_AUTH;
+ break;
+ case WPA_MODE_NONE:
+ ar->arAuthMode = NONE_AUTH;
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_AUTHMODE:
+ if(value == IEEE80211_AUTH_WPA_PSK) {
+ if (WPA_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA_PSK_AUTH;
+ } else if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_PSK_AUTH;
+ } else if ((WPA_AUTH | WPA2_AUTH) == ar->arAuthMode) {
+ ar->arAuthMode = WPA_PSK_AUTH | WPA2_PSK_AUTH;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error - Setting PSK "\
+ "mode when WPA param was set to %d\n",
+ ar->arAuthMode));
+ ret = -EIO;
+ }
+ }
+ break;
+ case IEEE80211_PARAM_UCASTCIPHER:
+ ar->arPairwiseCrypto = 0;
+ if(value & (1<<IEEE80211_CIPHER_AES_CCM)) {
+ ar->arPairwiseCrypto |= AES_CRYPT;
+ }
+ if(value & (1<<IEEE80211_CIPHER_TKIP)) {
+ ar->arPairwiseCrypto |= TKIP_CRYPT;
+ }
+ if(!ar->arPairwiseCrypto) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Error - Invalid cipher in WPA \n"));
+ ret = -EIO;
+ }
+ break;
+ case IEEE80211_PARAM_PRIVACY:
+ if(value == 0) {
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arAuthMode = NONE_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ }
+ break;
+#ifdef WAPI_ENABLE
+ case IEEE80211_PARAM_WAPI:
+ A_PRINTF("WAPI Policy: %d\n", value);
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arAuthMode = NONE_AUTH;
+ if(value & 0x1) {
+ ar->arPairwiseCrypto = WAPI_CRYPT;
+ ar->arGroupCrypto = WAPI_CRYPT;
+ } else {
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arGroupCrypto = NONE_CRYPT;
+ }
+ break;
+#endif
+ }
+ return ret;
+}
+
+int
+ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value)
+{
+ A_BOOL profChanged = FALSE;
+ int ret=0;
+
+ if(ar->arNextMode == AP_NETWORK) {
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ switch (param) {
+ case IEEE80211_PARAM_WPA:
+ case IEEE80211_PARAM_AUTHMODE:
+ case IEEE80211_PARAM_UCASTCIPHER:
+ case IEEE80211_PARAM_PRIVACY:
+ case IEEE80211_PARAM_WAPI:
+ ret = ar6000_ioctl_ap_setparam(ar, param, value);
+ return ret;
+ }
+ }
+
+ switch (param) {
+ case IEEE80211_PARAM_WPA:
+ switch (value) {
+ case WPA_MODE_WPA1:
+ ar->arAuthMode = WPA_AUTH;
+ profChanged = TRUE;
+ break;
+ case WPA_MODE_WPA2:
+ ar->arAuthMode = WPA2_AUTH;
+ profChanged = TRUE;
+ break;
+ case WPA_MODE_NONE:
+ ar->arAuthMode = NONE_AUTH;
+ profChanged = TRUE;
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_AUTHMODE:
+ switch(value) {
+ case IEEE80211_AUTH_WPA_PSK:
+ if (WPA_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA_PSK_AUTH;
+ profChanged = TRUE;
+ } else if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_PSK_AUTH;
+ profChanged = TRUE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error - Setting PSK "\
+ "mode when WPA param was set to %d\n",
+ ar->arAuthMode));
+ ret = -EIO;
+ }
+ break;
+ case IEEE80211_AUTH_WPA_CCKM:
+ if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_AUTH_CCKM;
+ } else {
+ ar->arAuthMode = WPA_AUTH_CCKM;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_UCASTCIPHER:
+ switch (value) {
+ case IEEE80211_CIPHER_AES_CCM:
+ ar->arPairwiseCrypto = AES_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ ar->arPairwiseCrypto = TKIP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_WEP:
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_NONE:
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ profChanged = TRUE;
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_UCASTKEYLEN:
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+ ret = -EIO;
+ } else {
+ ar->arPairwiseCryptoLen = value;
+ }
+ break;
+ case IEEE80211_PARAM_MCASTCIPHER:
+ switch (value) {
+ case IEEE80211_CIPHER_AES_CCM:
+ ar->arGroupCrypto = AES_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ ar->arGroupCrypto = TKIP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_WEP:
+ ar->arGroupCrypto = WEP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_NONE:
+ ar->arGroupCrypto = NONE_CRYPT;
+ profChanged = TRUE;
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_MCASTKEYLEN:
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+ ret = -EIO;
+ } else {
+ ar->arGroupCryptoLen = value;
+ }
+ break;
+ case IEEE80211_PARAM_COUNTERMEASURES:
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+ break;
+ default:
+ break;
+ }
+ if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) {
+ /*
+ * profile has changed. Erase ssid to signal change
+ */
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ }
+
+ return ret;
+}
+
+int
+ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik)
+{
+ KEY_USAGE keyUsage;
+ A_STATUS status;
+ CRYPTO_TYPE keyType = NONE_CRYPT;
+
+#ifdef USER_KEYS
+ ar->user_saved_keys.keyOk = FALSE;
+#endif
+ if ( (0 == memcmp(ik->ik_macaddr, null_mac, IEEE80211_ADDR_LEN)) ||
+ (0 == memcmp(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN)) ) {
+ keyUsage = GROUP_USAGE;
+ if(ar->arNextMode == AP_NETWORK) {
+ A_MEMCPY(&ar->ap_mode_bkey, ik,
+ sizeof(struct ieee80211req_key));
+#ifdef WAPI_ENABLE
+ if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+ return ap_set_wapi_key(ar, ik);
+ }
+#endif
+ }
+#ifdef USER_KEYS
+ A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik,
+ sizeof(struct ieee80211req_key));
+#endif
+ } else {
+ keyUsage = PAIRWISE_USAGE;
+#ifdef USER_KEYS
+ A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik,
+ sizeof(struct ieee80211req_key));
+#endif
+#ifdef WAPI_ENABLE
+ if(ar->arNextMode == AP_NETWORK) {
+ if(ar->arPairwiseCrypto == WAPI_CRYPT) {
+ return ap_set_wapi_key(ar, ik);
+ }
+ }
+#endif
+ }
+
+ switch (ik->ik_type) {
+ case IEEE80211_CIPHER_WEP:
+ keyType = WEP_CRYPT;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ keyType = TKIP_CRYPT;
+ break;
+ case IEEE80211_CIPHER_AES_CCM:
+ keyType = AES_CRYPT;
+ break;
+ default:
+ break;
+ }
+#ifdef USER_KEYS
+ ar->user_saved_keys.keyType = keyType;
+#endif
+ if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
+ if (NONE_CRYPT == keyType) {
+ return -EIO;
+ }
+
+ if (WEP_CRYPT == keyType) {
+ int index = ik->ik_keyix;
+
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(ik->ik_keylen)) {
+ return -EIO;
+ }
+
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ A_MEMCPY(ar->arWepKeyList[index].arKey, ik->ik_keydata, ik->ik_keylen);
+ ar->arWepKeyList[index].arKeyLen = ik->ik_keylen;
+
+ if(ik->ik_flags & IEEE80211_KEY_DEFAULT){
+ ar->arDefTxKeyIndex = index;
+ }
+
+ return 0;
+ }
+
+ if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+ (GROUP_USAGE & keyUsage))
+ {
+ A_UNTIMEOUT(&ar->disconnect_timer);
+ }
+
+ status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
+ ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+ ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
+ SYNC_BOTH_WMIFLAG);
+
+ if (status != A_OK) {
+ return -EIO;
+ }
+ } else {
+ status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
+ }
+
+#ifdef USER_KEYS
+ ar->user_saved_keys.keyOk = TRUE;
+#endif
+
+ return 0;
+}
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ HIF_DEVICE *hifDevice = ar->arHifDevice;
+ int ret = 0, param;
+ unsigned int address = 0;
+ unsigned int length = 0;
+ unsigned char *buffer;
+ char *userdata;
+ A_UINT32 connectCtrlFlags;
+
+
+ WMI_SET_AKMP_PARAMS_CMD akmpParams;
+ WMI_SET_PMKID_LIST_CMD pmkidInfo;
+
+ WMI_SET_HT_CAP_CMD htCap;
+ WMI_SET_HT_OP_CMD htOp;
+
+ /*
+ * ioctl operations may have to wait for the Target, so we cannot hold rtnl.
+ * Prevent the device from disappearing under us and release the lock during
+ * the ioctl operation.
+ */
+ dev_hold(dev);
+ rtnl_unlock();
+
+ if (cmd == AR6000_IOCTL_EXTENDED) {
+ /*
+ * This allows for many more wireless ioctls than would otherwise
+ * be available. Applications embed the actual ioctl command in
+ * the first word of the parameter block, and use the command
+ * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
+ */
+ get_user(cmd, (int *)rq->ifr_data);
+ userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
+ if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) {
+ A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd);
+ ret = -EOPNOTSUPP;
+ goto ioctl_done;
+ }
+ } else {
+ A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd);
+ if(ret == A_ENOTSUP) {
+ A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd);
+ ret = -EOPNOTSUPP;
+ goto ioctl_done;
+ } else if (ret == A_ERROR) {
+ /* It is not our ioctl (out of range ioctl) */
+ ret = -EOPNOTSUPP;
+ goto ioctl_done;
+ }
+ userdata = (char *)rq->ifr_data;
+ }
+
+ if ((ar->arWlanState == WLAN_DISABLED) &&
+ ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
+ (cmd != AR6000_XIOCTL_DIAG_READ) &&
+ (cmd != AR6000_XIOCTL_DIAG_WRITE)))
+ {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+
+ ret = 0;
+ switch(cmd)
+ {
+ case IEEE80211_IOCTL_SETPARAM:
+ {
+ int param, value;
+ int *ptr = (int *)rq->ifr_ifru.ifru_newname;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ param = *ptr++;
+ value = *ptr;
+ ret = ar6000_ioctl_setparam(ar,param,value);
+ }
+ break;
+ }
+ case IEEE80211_IOCTL_SETKEY:
+ {
+ struct ieee80211req_key keydata;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&keydata, userdata,
+ sizeof(struct ieee80211req_key))) {
+ ret = -EFAULT;
+ } else {
+ ar6000_ioctl_setkey(ar, &keydata);
+ }
+ break;
+ }
+ case IEEE80211_IOCTL_DELKEY:
+ case IEEE80211_IOCTL_SETOPTIE:
+ {
+ //ret = -EIO;
+ break;
+ }
+ case IEEE80211_IOCTL_SETMLME:
+ {
+ struct ieee80211req_mlme mlme;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&mlme, userdata,
+ sizeof(struct ieee80211req_mlme))) {
+ ret = -EFAULT;
+ } else {
+ switch (mlme.im_op) {
+ case IEEE80211_MLME_AUTHORIZE:
+ A_PRINTF("setmlme AUTHORIZE %02X:%02X\n",
+ mlme.im_macaddr[4], mlme.im_macaddr[5]);
+ break;
+ case IEEE80211_MLME_UNAUTHORIZE:
+ A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n",
+ mlme.im_macaddr[4], mlme.im_macaddr[5]);
+ break;
+ case IEEE80211_MLME_DEAUTH:
+ A_PRINTF("setmlme DEAUTH %02X:%02X\n",
+ mlme.im_macaddr[4], mlme.im_macaddr[5]);
+ //remove_sta(ar, mlme.im_macaddr);
+ break;
+ case IEEE80211_MLME_DISASSOC:
+ A_PRINTF("setmlme DISASSOC %02X:%02X\n",
+ mlme.im_macaddr[4], mlme.im_macaddr[5]);
+ //remove_sta(ar, mlme.im_macaddr);
+ break;
+ default:
+ ret = 0;
+ goto ioctl_done;
+ }
+
+ wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr,
+ mlme.im_reason);
+ }
+ break;
+ }
+ case IEEE80211_IOCTL_ADDPMKID:
+ {
+ struct ieee80211req_addpmkid req;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) {
+ ret = -EFAULT;
+ } else {
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
+ req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2],
+ req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5],
+ req.pi_enable));
+
+ status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid,
+ req.pi_enable);
+
+ if (status != A_OK) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ }
+ break;
+ }
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ case AR6000_XIOCTL_TCMD_CONT_TX:
+ {
+ TCMD_CONT_TX txCmd;
+
+ if (ar->tcmdPm == TCMD_PM_SLEEP) {
+ A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+
+ if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) {
+ ret = -EFAULT;
+ goto ioctl_done;
+ } else {
+ wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX));
+ }
+ }
+ break;
+ case AR6000_XIOCTL_TCMD_CONT_RX:
+ {
+ TCMD_CONT_RX rxCmd;
+
+ if (ar->tcmdPm == TCMD_PM_SLEEP) {
+ A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+ if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+
+ switch(rxCmd.act)
+ {
+ case TCMD_CONT_RX_PROMIS:
+ case TCMD_CONT_RX_FILTER:
+ case TCMD_CONT_RX_SETMAC:
+ case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE:
+ wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd,
+ sizeof(TCMD_CONT_RX));
+ tcmdRxFreq = rxCmd.u.para.freq;
+ break;
+ case TCMD_CONT_RX_REPORT:
+ ar6000_ioctl_tcmd_get_rx_report(dev, rq,
+ (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX));
+ break;
+ default:
+ A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
+ ret = -EINVAL;
+ goto ioctl_done;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_TCMD_PM:
+ {
+ TCMD_PM pmCmd;
+
+ if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+ ar->tcmdPm = pmCmd.mode;
+ wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM));
+ }
+ break;
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+ case AR6000_XIOCTL_BMI_DONE:
+ if(bmienable)
+ {
+ rtnl_lock(); /* ar6000_init expects to be called holding rtnl lock */
+ ret = ar6000_init(dev);
+ rtnl_unlock();
+ }
+ else
+ {
+ ret = BMIDone(hifDevice);
+ }
+ break;
+
+ case AR6000_XIOCTL_BMI_READ_MEMORY:
+ get_user(address, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Read Memory (address: 0x%x, length: %d)\n",
+ address, length));
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ ret = BMIReadMemory(hifDevice, address, buffer, length);
+ if (copy_to_user(rq->ifr_data, buffer, length)) {
+ ret = -EFAULT;
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+ break;
+
+ case AR6000_XIOCTL_BMI_WRITE_MEMORY:
+ get_user(address, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Write Memory (address: 0x%x, length: %d)\n",
+ address, length));
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ if (copy_from_user(buffer, &userdata[sizeof(address) +
+ sizeof(length)], length))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = BMIWriteMemory(hifDevice, address, buffer, length);
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+ break;
+
+ case AR6000_XIOCTL_BMI_TEST:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("No longer supported\n"));
+ ret = -EOPNOTSUPP;
+ break;
+
+ case AR6000_XIOCTL_BMI_EXECUTE:
+ get_user(address, (unsigned int *)userdata);
+ get_user(param, (unsigned int *)userdata + 1);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Execute (address: 0x%x, param: %d)\n",
+ address, param));
+ ret = BMIExecute(hifDevice, address, (A_UINT32*)&param);
+ put_user(param, (unsigned int *)rq->ifr_data); /* return value */
+ break;
+
+ case AR6000_XIOCTL_BMI_SET_APP_START:
+ get_user(address, (unsigned int *)userdata);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Set App Start (address: 0x%x)\n", address));
+ ret = BMISetAppStart(hifDevice, address);
+ break;
+
+ case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
+ get_user(address, (unsigned int *)userdata);
+ ret = BMIReadSOCRegister(hifDevice, address, (A_UINT32*)&param);
+ put_user(param, (unsigned int *)rq->ifr_data); /* return value */
+ break;
+
+ case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
+ get_user(address, (unsigned int *)userdata);
+ get_user(param, (unsigned int *)userdata + 1);
+ ret = BMIWriteSOCRegister(hifDevice, address, param);
+ break;
+
+#ifdef HTC_RAW_INTERFACE
+ case AR6000_XIOCTL_HTC_RAW_OPEN:
+ ret = A_OK;
+ if (!arRawIfEnabled(ar)) {
+ /* make sure block size is set in case the target was reset since last
+ * BMI phase (i.e. flashup downloads) */
+ ret = ar6000_set_htc_params(ar->arHifDevice,
+ ar->arTargetType,
+ 0, /* use default yield */
+ 0 /* use default number of HTC ctrl buffers */
+ );
+ if (A_FAILED(ret)) {
+ break;
+ }
+ /* Terminate the BMI phase */
+ ret = BMIDone(hifDevice);
+ if (ret == A_OK) {
+ ret = ar6000_htc_raw_open(ar);
+ }
+ }
+ break;
+
+ case AR6000_XIOCTL_HTC_RAW_CLOSE:
+ if (arRawIfEnabled(ar)) {
+ ret = ar6000_htc_raw_close(ar);
+ arRawIfEnabled(ar) = FALSE;
+ } else {
+ ret = A_ERROR;
+ }
+ break;
+
+ case AR6000_XIOCTL_HTC_RAW_READ:
+ if (arRawIfEnabled(ar)) {
+ unsigned int streamID;
+ get_user(streamID, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ buffer = rq->ifr_data + sizeof(length);
+ ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
+ buffer, length);
+ put_user(ret, (unsigned int *)rq->ifr_data);
+ } else {
+ ret = A_ERROR;
+ }
+ break;
+
+ case AR6000_XIOCTL_HTC_RAW_WRITE:
+ if (arRawIfEnabled(ar)) {
+ unsigned int streamID;
+ get_user(streamID, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ buffer = userdata + sizeof(streamID) + sizeof(length);
+ ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
+ buffer, length);
+ put_user(ret, (unsigned int *)rq->ifr_data);
+ } else {
+ ret = A_ERROR;
+ }
+ break;
+#endif /* HTC_RAW_INTERFACE */
+
+ case AR6000_XIOCTL_BMI_LZ_STREAM_START:
+ get_user(address, (unsigned int *)userdata);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Start Compressed Stream (address: 0x%x)\n", address));
+ ret = BMILZStreamStart(hifDevice, address);
+ break;
+
+ case AR6000_XIOCTL_BMI_LZ_DATA:
+ get_user(length, (unsigned int *)userdata);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Send Compressed Data (length: %d)\n", length));
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ if (copy_from_user(buffer, &userdata[sizeof(length)], length))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = BMILZData(hifDevice, buffer, length);
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+ break;
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+ /*
+ * Optional support for Target-side profiling.
+ * Not needed in production.
+ */
+
+ /* Configure Target-side profiling */
+ case AR6000_XIOCTL_PROF_CFG:
+ {
+ A_UINT32 period;
+ A_UINT32 nbins;
+ get_user(period, (unsigned int *)userdata);
+ get_user(nbins, (unsigned int *)userdata + 1);
+
+ if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) {
+ ret = -EIO;
+ }
+
+ break;
+ }
+
+ /* Start a profiling bucket/bin at the specified address */
+ case AR6000_XIOCTL_PROF_ADDR_SET:
+ {
+ A_UINT32 addr;
+ get_user(addr, (unsigned int *)userdata);
+
+ if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) {
+ ret = -EIO;
+ }
+
+ break;
+ }
+
+ /* START Target-side profiling */
+ case AR6000_XIOCTL_PROF_START:
+ wmi_prof_start_cmd(ar->arWmi);
+ break;
+
+ /* STOP Target-side profiling */
+ case AR6000_XIOCTL_PROF_STOP:
+ wmi_prof_stop_cmd(ar->arWmi);
+ break;
+ case AR6000_XIOCTL_PROF_COUNT_GET:
+ {
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+
+ prof_count_available = FALSE;
+ ret = prof_count_get(dev);
+ if (ret != A_OK) {
+ up(&ar->arSem);
+ ret = -EIO;
+ goto ioctl_done;
+ }
+
+ /* Wait for Target to respond. */
+ wait_event_interruptible(arEvent, prof_count_available);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ if (copy_to_user(userdata, &prof_count_results,
+ sizeof(prof_count_results)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+ case AR6000_IOCTL_WMI_GETREV:
+ {
+ if (copy_to_user(rq->ifr_data, &ar->arVersion,
+ sizeof(ar->arVersion)))
+ {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETPWR:
+ {
+ WMI_POWER_MODE_CMD pwrModeCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&pwrModeCmd, userdata,
+ sizeof(pwrModeCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
+ {
+ WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&ibssPmCaps, userdata,
+ sizeof(ibssPmCaps)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
+ ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
+ {
+ ret = -EIO;
+ }
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arIbssPsEnable = ibssPmCaps.power_saving;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_AP_PS:
+ {
+ WMI_AP_PS_CMD apPsCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&apPsCmd, userdata,
+ sizeof(apPsCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_apps_cmd(ar->arWmi, apPsCmd.psType, apPsCmd.idle_time,
+ apPsCmd.ps_period, apPsCmd.sleep_period) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_PMPARAMS:
+ {
+ WMI_POWER_PARAMS_CMD pmParams;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&pmParams, userdata,
+ sizeof(pmParams)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
+ pmParams.pspoll_number,
+ pmParams.dtim_policy,
+ pmParams.tx_wakeup_policy,
+ pmParams.num_tx_to_wakeup,
+#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+ IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
+#else
+ SEND_POWER_SAVE_FAIL_EVENT_ALWAYS
+#endif
+ ) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETSCAN:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&ar->scParams, userdata,
+ sizeof(ar->scParams)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (CAN_SCAN_IN_CONNECT(ar->scParams.scanCtrlFlags)) {
+ ar->arSkipScan = FALSE;
+ } else {
+ ar->arSkipScan = TRUE;
+ }
+
+ if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period,
+ ar->scParams.fg_end_period,
+ ar->scParams.bg_period,
+ ar->scParams.minact_chdwell_time,
+ ar->scParams.maxact_chdwell_time,
+ ar->scParams.pas_chdwell_time,
+ ar->scParams.shortScanRatio,
+ ar->scParams.scanCtrlFlags,
+ ar->scParams.max_dfsch_act_time,
+ ar->scParams.maxact_scan_per_ssid) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETLISTENINT:
+ {
+ WMI_LISTEN_INT_CMD listenCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&listenCmd, userdata,
+ sizeof(listenCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
+ ret = -EIO;
+ } else {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arListenInterval = param;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_BMISS_TIME:
+ {
+ WMI_BMISS_TIME_CMD bmissCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&bmissCmd, userdata,
+ sizeof(bmissCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETBSSFILTER:
+ {
+ WMI_BSS_FILTER_CMD filt;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&filt, userdata,
+ sizeof(filt)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask)
+ != A_OK) {
+ ret = -EIO;
+ } else {
+ ar->arUserBssFilter = param;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
+ {
+ ret = ar6000_ioctl_set_snr_threshold(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
+ {
+ ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_CLR_RSSISNR:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ }
+ ret = wmi_clr_rssi_snr(ar->arWmi);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
+ {
+ ret = ar6000_ioctl_set_lq_threshold(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
+ {
+ WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setLpreambleCmd, userdata,
+ sizeof(setLpreambleCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status,
+#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP
+ WMI_DONOT_IGNORE_BARKER_IN_ERP
+#else
+ WMI_IGNORE_BARKER_IN_ERP
+#endif
+ ) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_RTS:
+ {
+ WMI_SET_RTS_CMD rtsCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&rtsCmd, userdata,
+ sizeof(rtsCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ar->arRTS = rtsCmd.threshold;
+ if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_WMM:
+ {
+ ret = ar6000_ioctl_set_wmm(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_QOS_SUPP:
+ {
+ ret = ar6000_ioctl_set_qos_supp(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_TXOP:
+ {
+ ret = ar6000_ioctl_set_txop(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_RD:
+ {
+ ret = ar6000_ioctl_get_rd(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
+ {
+ ret = ar6000_ioctl_set_channelParams(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_PROBEDSSID:
+ {
+ ret = ar6000_ioctl_set_probedSsid(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_BADAP:
+ {
+ ret = ar6000_ioctl_set_badAp(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_CREATE_QOS:
+ {
+ ret = ar6000_ioctl_create_qos(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_DELETE_QOS:
+ {
+ ret = ar6000_ioctl_delete_qos(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
+ {
+ ret = ar6000_ioctl_get_qos_queue(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_GET_TARGET_STATS:
+ {
+ ret = ar6000_ioctl_get_target_stats(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
+ {
+ ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
+ {
+ WMI_SET_ASSOC_INFO_CMD cmd;
+ A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ get_user(cmd.ieType, userdata);
+ if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
+ ret = -EIO;
+ } else {
+ get_user(cmd.bufferSize, userdata + 1);
+ if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(assocInfo, userdata + 2,
+ cmd.bufferSize))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
+ cmd.bufferSize,
+ assocInfo) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
+ {
+ ret = ar6000_ioctl_set_access_params(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
+ {
+ ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_FORCE_TARGET_RESET:
+ {
+ if (ar->arHtcTarget)
+ {
+// HTCForceReset(htcTarget);
+ }
+ else
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("ar6000_ioctl cannot attempt reset.\n"));
+ }
+ break;
+ }
+ case AR6000_XIOCTL_TARGET_INFO:
+ case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
+ {
+ /* If we made it to here, then the Target exists and is ready. */
+
+ if (cmd == AR6000_XIOCTL_TARGET_INFO) {
+ if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver,
+ sizeof(ar->arVersion.target_ver)))
+ {
+ ret = -EFAULT;
+ }
+ if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType,
+ sizeof(ar->arTargetType)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
+ {
+ WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
+
+ if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
+ {
+ ret = -EFAULT;
+ } else {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ /* Start a cyclic timer with the parameters provided. */
+ if (hbparam.frequency) {
+ ar->arHBChallengeResp.frequency = hbparam.frequency;
+ }
+ if (hbparam.threshold) {
+ ar->arHBChallengeResp.missThres = hbparam.threshold;
+ }
+
+ /* Delete the pending timer and start a new one */
+ if (timer_pending(&ar->arHBChallengeResp.timer)) {
+ A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+ }
+ A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
+ {
+ A_UINT32 cookie;
+
+ if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+
+ /* Send the challenge on the control channel */
+ if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ break;
+ }
+#ifdef USER_KEYS
+ case AR6000_XIOCTL_USER_SETKEYS:
+ {
+
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
+
+ if (copy_from_user(&ar->user_key_ctrl, userdata,
+ sizeof(ar->user_key_ctrl)))
+ {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+
+ A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
+ break;
+ }
+#endif /* USER_KEYS */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+ case AR6000_XIOCTL_GPIO_OUTPUT_SET:
+ {
+ struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
+
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+
+ if (copy_from_user(&gpio_output_set_cmd, userdata,
+ sizeof(gpio_output_set_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_output_set(dev,
+ gpio_output_set_cmd.set_mask,
+ gpio_output_set_cmd.clear_mask,
+ gpio_output_set_cmd.enable_mask,
+ gpio_output_set_cmd.disable_mask);
+ if (ret != A_OK) {
+ ret = EIO;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_INPUT_GET:
+ {
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+
+ ret = ar6000_gpio_input_get(dev);
+ if (ret != A_OK) {
+ up(&ar->arSem);
+ ret = -EIO;
+ goto ioctl_done;
+ }
+
+ /* Wait for Target to respond. */
+ wait_event_interruptible(arEvent, gpio_data_available);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
+
+ if (copy_to_user(userdata, &gpio_reg_results.value,
+ sizeof(gpio_reg_results.value)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_REGISTER_SET:
+ {
+ struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+
+ if (copy_from_user(&gpio_register_cmd, userdata,
+ sizeof(gpio_register_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_register_set(dev,
+ gpio_register_cmd.gpioreg_id,
+ gpio_register_cmd.value);
+ if (ret != A_OK) {
+ ret = EIO;
+ }
+
+ /* Wait for acknowledgement from Target */
+ wait_event_interruptible(arEvent, gpio_ack_received);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_REGISTER_GET:
+ {
+ struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+
+ if (copy_from_user(&gpio_register_cmd, userdata,
+ sizeof(gpio_register_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
+ if (ret != A_OK) {
+ up(&ar->arSem);
+ ret = -EIO;
+ goto ioctl_done;
+ }
+
+ /* Wait for Target to respond. */
+ wait_event_interruptible(arEvent, gpio_data_available);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
+ if (copy_to_user(userdata, &gpio_reg_results,
+ sizeof(gpio_reg_results)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_INTR_ACK:
+ {
+ struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
+
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+
+ if (copy_from_user(&gpio_intr_ack_cmd, userdata,
+ sizeof(gpio_intr_ack_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
+ if (ret != A_OK) {
+ ret = EIO;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_INTR_WAIT:
+ {
+ /* Wait for Target to report an interrupt. */
+ wait_event_interruptible(arEvent, gpio_intr_available);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ if (copy_to_user(userdata, &gpio_intr_results,
+ sizeof(gpio_intr_results)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ break;
+ }
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+ case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
+ {
+ struct ar6000_dbglog_module_config_s config;
+
+ if (copy_from_user(&config, userdata, sizeof(config))) {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+
+ /* Send the challenge on the control channel */
+ if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
+ config.tsr, config.rep,
+ config.size, config.valid) != A_OK)
+ {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
+ {
+ /* Send the challenge on the control channel */
+ if (ar6000_dbglog_get_debug_logs(ar) != A_OK)
+ {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_ADHOC_BSSID:
+ {
+ WMI_SET_ADHOC_BSSID_CMD adhocBssid;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&adhocBssid, userdata,
+ sizeof(adhocBssid)))
+ {
+ ret = -EFAULT;
+ } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
+ AR6000_ETH_ADDR_LEN) == 0)
+ {
+ ret = -EFAULT;
+ } else {
+
+ A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_OPT_MODE:
+ {
+ WMI_SET_OPT_MODE_CMD optModeCmd;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&optModeCmd, userdata,
+ sizeof(optModeCmd)))
+ {
+ ret = -EFAULT;
+ } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
+ ret = -EFAULT;
+
+ } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_OPT_SEND_FRAME:
+ {
+ WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
+ A_UINT8 data[MAX_OPT_DATA_LEN];
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&optTxFrmCmd, userdata,
+ sizeof(optTxFrmCmd)))
+ {
+ ret = -EFAULT;
+ } else if (copy_from_user(data,
+ userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1,
+ optTxFrmCmd.optIEDataLen))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = wmi_opt_tx_frame_cmd(ar->arWmi,
+ optTxFrmCmd.frmType,
+ optTxFrmCmd.dstAddr,
+ optTxFrmCmd.bssid,
+ optTxFrmCmd.optIEDataLen,
+ data);
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
+ {
+ WMI_SET_RETRY_LIMITS_CMD setRetryParams;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setRetryParams, userdata,
+ sizeof(setRetryParams)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
+ setRetryParams.trafficClass,
+ setRetryParams.maxRetries,
+ setRetryParams.enableNotify) != A_OK)
+ {
+ ret = -EIO;
+ }
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arMaxRetries = setRetryParams.maxRetries;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_BEACON_INTVAL:
+ {
+ WMI_BEACON_INT_CMD bIntvlCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&bIntvlCmd, userdata,
+ sizeof(bIntvlCmd)))
+ {
+ ret = -EFAULT;
+ } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ if(ret == 0) {
+ ar->ap_beacon_interval = bIntvlCmd.beaconInterval;
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ }
+ break;
+ }
+ case IEEE80211_IOCTL_SETAUTHALG:
+ {
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ struct ieee80211req_authalg req;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&req, userdata,
+ sizeof(struct ieee80211req_authalg)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) {
+ ar->arDot11AuthMode |= OPEN_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arGroupCrypto = NONE_CRYPT;
+ }
+ if (req.auth_alg & AUTH_ALG_SHARED_KEY) {
+ ar->arDot11AuthMode |= SHARED_AUTH;
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arGroupCrypto = WEP_CRYPT;
+ ar->arAuthMode = NONE_AUTH;
+ }
+ if (req.auth_alg == AUTH_ALG_LEAP) {
+ ar->arDot11AuthMode = LEAP_AUTH;
+ }
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
+ ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_SET_MAX_SP:
+ ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
+ ret = ar6000_ioctl_get_roam_tbl(dev, rq);
+ break;
+ case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
+ ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
+ break;
+ case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
+ ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
+ break;
+ case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
+ ret = ar6000_ioctl_get_power_mode(dev, rq);
+ break;
+ case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
+ {
+ AR6000_WLAN_STATE state;
+ get_user(state, (unsigned int *)userdata);
+ if (ar6000_set_wlan_state(ar, state)!=A_OK) {
+ ret = -EIO;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
+ ret = ar6000_ioctl_get_roam_data(dev, rq);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BT_STATUS:
+ ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
+ ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT:
+ ret = ar6000_xioctl_set_btcoex_fe_ant_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV:
+ ret = ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG:
+ ret = ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG:
+ ret = ar6000_xioctl_set_btcoex_sco_config_cmd( dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG:
+ ret = ar6000_xioctl_set_btcoex_a2dp_config_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG:
+ ret = ar6000_xioctl_set_btcoex_aclcoex_config_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG:
+ ret = ar60000_xioctl_set_btcoex_debug_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS:
+ ret = ar6000_xioctl_set_btcoex_bt_operating_status_cmd(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG:
+ ret = ar6000_xioctl_get_btcoex_config_cmd(dev, userdata, rq);
+ break;
+
+ case AR6000_XIOCTL_WMI_GET_BTCOEX_STATS:
+ ret = ar6000_xioctl_get_btcoex_stats_cmd(dev, userdata, rq);
+ break;
+
+ case AR6000_XIOCTL_WMI_STARTSCAN:
+ {
+ WMI_START_SCAN_CMD setStartScanCmd, *cmdp;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setStartScanCmd, userdata,
+ sizeof(setStartScanCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (setStartScanCmd.numChannels > 1) {
+ cmdp = A_MALLOC(130);
+ if (copy_from_user(cmdp, userdata,
+ sizeof (*cmdp) +
+ ((setStartScanCmd.numChannels - 1) *
+ sizeof(A_UINT16))))
+ {
+ kfree(cmdp);
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+ } else {
+ cmdp = &setStartScanCmd;
+ }
+
+ if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType,
+ cmdp->forceFgScan,
+ cmdp->isLegacy,
+ cmdp->homeDwellTime,
+ cmdp->forceScanInterval,
+ cmdp->numChannels,
+ cmdp->channelList) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SETFIXRATES:
+ {
+ WMI_FIX_RATES_CMD setFixRatesCmd;
+ A_STATUS returnStatus;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setFixRatesCmd, userdata,
+ sizeof(setFixRatesCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
+ if (returnStatus == A_EINVAL) {
+ ret = -EINVAL;
+ } else if(returnStatus != A_OK) {
+ ret = -EIO;
+ } else {
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ }
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_WMI_GETFIXRATES:
+ {
+ WMI_FIX_RATES_CMD getFixRatesCmd;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ int ret = 0;
+
+ if (ar->bIsDestroyProgress) {
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ /* Used copy_from_user/copy_to_user to access user space data */
+ if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
+ ret = -EFAULT;
+ } else {
+ ar->arRateMask = 0xFFFFFFFF;
+
+ if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ ret = -EIO;
+ goto ioctl_done;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFFFFFF, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret) {
+ getFixRatesCmd.fixRateMask = ar->arRateMask;
+ }
+
+ if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
+ ret = -EFAULT;
+ }
+
+ up(&ar->arSem);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_AUTHMODE:
+ {
+ WMI_SET_AUTH_MODE_CMD setAuthMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setAuthMode, userdata,
+ sizeof(setAuthMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
+ {
+ WMI_SET_REASSOC_MODE_CMD setReassocMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setReassocMode, userdata,
+ sizeof(setReassocMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_DIAG_READ:
+ {
+ A_UINT32 addr, data;
+ get_user(addr, (unsigned int *)userdata);
+ addr = TARG_VTOP(ar->arTargetType, addr);
+ if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+ ret = -EIO;
+ }
+ put_user(data, (unsigned int *)userdata + 1);
+ break;
+ }
+ case AR6000_XIOCTL_DIAG_WRITE:
+ {
+ A_UINT32 addr, data;
+ get_user(addr, (unsigned int *)userdata);
+ get_user(data, (unsigned int *)userdata + 1);
+ addr = TARG_VTOP(ar->arTargetType, addr);
+ if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+ ret = -EIO;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
+ {
+ WMI_SET_KEEPALIVE_CMD setKeepAlive;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ } else if (copy_from_user(&setKeepAlive, userdata,
+ sizeof(setKeepAlive))){
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_PARAMS:
+ {
+ WMI_SET_PARAMS_CMD cmd;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ } else if (copy_from_user(&cmd, userdata,
+ sizeof(cmd))){
+ ret = -EFAULT;
+ } else if (copy_from_user(&cmd, userdata,
+ sizeof(cmd) + cmd.length))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_MCAST_FILTER:
+ {
+ WMI_SET_MCAST_FILTER_CMD cmd;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ } else if (copy_from_user(&cmd, userdata,
+ sizeof(cmd))){
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
+ cmd.multicast_mac[1],
+ cmd.multicast_mac[2],
+ cmd.multicast_mac[3]) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER:
+ {
+ WMI_SET_MCAST_FILTER_CMD cmd;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ } else if (copy_from_user(&cmd, userdata,
+ sizeof(cmd))){
+ ret = -EFAULT;
+ } else {
+ if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
+ cmd.multicast_mac[1],
+ cmd.multicast_mac[2],
+ cmd.multicast_mac[3]) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_MCAST_FILTER:
+ {
+ WMI_MCAST_FILTER_CMD cmd;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ } else if (copy_from_user(&cmd, userdata,
+ sizeof(cmd))){
+ ret = -EFAULT;
+ } else {
+ if (wmi_mcast_filter_cmd(ar->arWmi, cmd.enable) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
+ {
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_GET_KEEPALIVE_CMD getKeepAlive;
+ int ret = 0;
+ if (ar->bIsDestroyProgress) {
+ ret =-EBUSY;
+ goto ioctl_done;
+ }
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ ret = -ERESTARTSYS;
+ goto ioctl_done;
+ }
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ ret = -EBUSY;
+ goto ioctl_done;
+ }
+ if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
+ ret = -EFAULT;
+ } else {
+ getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
+ ar->arKeepaliveConfigured = 0xFF;
+ if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){
+ up(&ar->arSem);
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret) {
+ getKeepAlive.configured = ar->arKeepaliveConfigured;
+ }
+ if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
+ ret = -EFAULT;
+ }
+ up(&ar->arSem);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_APPIE:
+ {
+ WMI_SET_APPIE_CMD appIEcmd;
+ A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
+ A_UINT32 fType,ieLen;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ }
+ get_user(fType, (A_UINT32 *)userdata);
+ appIEcmd.mgmtFrmType = fType;
+ if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
+ ret = -EIO;
+ } else {
+ get_user(ieLen, (A_UINT32 *)(userdata + 4));
+ appIEcmd.ieLen = ieLen;
+ A_PRINTF("WPSIE: Type-%d, Len-%d\n",appIEcmd.mgmtFrmType, appIEcmd.ieLen);
+ if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
+ ret = -EIO;
+ break;
+ }
+ if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
+ appIEcmd.ieLen, appIeInfo) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
+ {
+ WMI_BSS_FILTER_CMD cmd;
+ A_UINT32 filterType;
+
+ if (copy_from_user(&filterType, userdata, sizeof(A_UINT32)))
+ {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+ if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
+ IEEE80211_FILTER_TYPE_PROBE_RESP))
+ {
+ cmd.bssFilter = ALL_BSS_FILTER;
+ } else {
+ cmd.bssFilter = NONE_BSS_FILTER;
+ }
+ if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) {
+ ret = -EIO;
+ } else {
+ ar->arUserBssFilter = cmd.bssFilter;
+ }
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arMgmtFilter = filterType;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
+ {
+ A_UINT32 wsc_status;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ goto ioctl_done;
+ } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32)))
+ {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+ if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) {
+ ret = -EIO;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
+ {
+ A_UINT32 ROM_addr;
+ A_UINT32 RAM_addr;
+ A_UINT32 nbytes;
+ A_UINT32 do_activate;
+ A_UINT32 rompatch_id;
+
+ get_user(ROM_addr, (A_UINT32 *)userdata);
+ get_user(RAM_addr, (A_UINT32 *)userdata + 1);
+ get_user(nbytes, (A_UINT32 *)userdata + 2);
+ get_user(do_activate, (A_UINT32 *)userdata + 3);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n",
+ ROM_addr, RAM_addr, nbytes));
+ ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
+ nbytes, do_activate, &rompatch_id);
+ if (ret == A_OK) {
+ put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
+ {
+ A_UINT32 rompatch_id;
+
+ get_user(rompatch_id, (A_UINT32 *)userdata);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("UNinstall rompatch_id %d\n", rompatch_id));
+ ret = BMIrompatchUninstall(hifDevice, rompatch_id);
+ break;
+ }
+
+ case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
+ case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
+ {
+ A_UINT32 rompatch_count;
+
+ get_user(rompatch_count, (A_UINT32 *)userdata);
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Change rompatch activation count=%d\n", rompatch_count));
+ length = sizeof(A_UINT32) * rompatch_count;
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
+ {
+ ret = -EFAULT;
+ } else {
+ if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
+ ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+ } else {
+ ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+ }
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_SET_IP:
+ {
+ WMI_SET_IP_CMD setIP;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setIP, userdata,
+ sizeof(setIP)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_ip_cmd(ar->arWmi,
+ &setIP) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
+ {
+ WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setHostSleepMode, userdata,
+ sizeof(setHostSleepMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
+ &setHostSleepMode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_WOW_MODE:
+ {
+ WMI_SET_WOW_MODE_CMD setWowMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setWowMode, userdata,
+ sizeof(setWowMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_wow_mode_cmd(ar->arWmi,
+ &setWowMode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_WOW_LIST:
+ {
+ WMI_GET_WOW_LIST_CMD getWowList;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&getWowList, userdata,
+ sizeof(getWowList)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_get_wow_list_cmd(ar->arWmi,
+ &getWowList) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
+ {
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+ WMI_ADD_WOW_PATTERN_CMD cmd;
+ A_UINT8 mask_data[WOW_PATTERN_SIZE]={0};
+ A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0};
+
+ do {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ break;
+ }
+ if(copy_from_user(&cmd, userdata,
+ sizeof(WMI_ADD_WOW_PATTERN_CMD)))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(pattern_data,
+ userdata + 3,
+ cmd.filter_size))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(mask_data,
+ (userdata + 3 + cmd.filter_size),
+ cmd.filter_size))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (wmi_add_wow_pattern_cmd(ar->arWmi,
+ &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK)
+ {
+ ret = -EIO;
+ }
+ } while(FALSE);
+#undef WOW_PATTERN_SIZE
+#undef WOW_MASK_SIZE
+ break;
+ }
+ case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
+ {
+ WMI_DEL_WOW_PATTERN_CMD delWowPattern;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&delWowPattern, userdata,
+ sizeof(delWowPattern)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_del_wow_pattern_cmd(ar->arWmi,
+ &delWowPattern) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
+ if (ar->arHtcTarget != NULL) {
+ HTCDumpCreditStates(ar->arHtcTarget);
+#ifdef HTC_EP_STAT_PROFILING
+ {
+ HTC_ENDPOINT_STATS stats;
+ int i;
+
+ for (i = 0; i < 5; i++) {
+ if (HTCGetEndpointStatistics(ar->arHtcTarget,
+ i,
+ HTC_EP_STAT_SAMPLE_AND_CLEAR,
+ &stats)) {
+ A_PRINTF(KERN_ALERT"------- Profiling Endpoint : %d \n", i);
+ A_PRINTF(KERN_ALERT"TxCreditLowIndications : %d \n", stats.TxCreditLowIndications);
+ A_PRINTF(KERN_ALERT"TxIssued : %d \n", stats.TxIssued);
+ A_PRINTF(KERN_ALERT"TxDropped: %d \n", stats.TxDropped);
+ A_PRINTF(KERN_ALERT"TxPacketsBundled : %d \n", stats.TxPacketsBundled);
+ A_PRINTF(KERN_ALERT"TxBundles : %d \n", stats.TxBundles);
+ A_PRINTF(KERN_ALERT"TxCreditRpts : %d \n", stats.TxCreditRpts);
+ A_PRINTF(KERN_ALERT"TxCreditsRptsFromRx : %d \n", stats.TxCreditRptsFromRx);
+ A_PRINTF(KERN_ALERT"TxCreditsRptsFromOther : %d \n", stats.TxCreditRptsFromOther);
+ A_PRINTF(KERN_ALERT"TxCreditsRptsFromEp0 : %d \n", stats.TxCreditRptsFromEp0);
+ A_PRINTF(KERN_ALERT"TxCreditsFromRx : %d \n", stats.TxCreditsFromRx);
+ A_PRINTF(KERN_ALERT"TxCreditsFromOther : %d \n", stats.TxCreditsFromOther);
+ A_PRINTF(KERN_ALERT"TxCreditsFromEp0 : %d \n", stats.TxCreditsFromEp0);
+ A_PRINTF(KERN_ALERT"TxCreditsConsummed : %d \n", stats.TxCreditsConsummed);
+ A_PRINTF(KERN_ALERT"TxCreditsReturned : %d \n", stats.TxCreditsReturned);
+ A_PRINTF(KERN_ALERT"RxReceived : %d \n", stats.RxReceived);
+ A_PRINTF(KERN_ALERT"RxPacketsBundled : %d \n", stats.RxPacketsBundled);
+ A_PRINTF(KERN_ALERT"RxLookAheads : %d \n", stats.RxLookAheads);
+ A_PRINTF(KERN_ALERT"RxBundleLookAheads : %d \n", stats.RxBundleLookAheads);
+ A_PRINTF(KERN_ALERT"RxBundleIndFromHdr : %d \n", stats.RxBundleIndFromHdr);
+ A_PRINTF(KERN_ALERT"RxAllocThreshHit : %d \n", stats.RxAllocThreshHit);
+ A_PRINTF(KERN_ALERT"RxAllocThreshBytes : %d \n", stats.RxAllocThreshBytes);
+ A_PRINTF(KERN_ALERT"---- \n");
+
+ }
+ }
+ }
+#endif
+ }
+ break;
+ case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
+ if (ar->arHtcTarget != NULL) {
+ struct ar6000_traffic_activity_change data;
+
+ if (copy_from_user(&data, userdata, sizeof(data)))
+ {
+ ret = -EFAULT;
+ goto ioctl_done;
+ }
+ /* note, this is used for testing (mbox ping testing), indicate activity
+ * change using the stream ID as the traffic class */
+ ar6000_indicate_tx_activity(ar,
+ (A_UINT8)data.StreamID,
+ data.Active ? TRUE : FALSE);
+ }
+ break;
+ case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&connectCtrlFlags, userdata,
+ sizeof(connectCtrlFlags)))
+ {
+ ret = -EFAULT;
+ } else {
+ ar->arConnectCtrlFlags = connectCtrlFlags;
+ }
+ break;
+ case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&akmpParams, userdata,
+ sizeof(WMI_SET_AKMP_PARAMS_CMD)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ if (copy_from_user(&pmkidInfo.numPMKID, userdata,
+ sizeof(pmkidInfo.numPMKID)))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(&pmkidInfo.pmkidList,
+ userdata + sizeof(pmkidInfo.numPMKID),
+ pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_WMI_ABORT_SCAN:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ }
+ ret = wmi_abort_scan_cmd(ar->arWmi);
+ break;
+ case AR6000_XIOCTL_AP_HIDDEN_SSID:
+ {
+ A_UINT8 hidden_ssid;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) {
+ ret = -EFAULT;
+ } else {
+ wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid);
+ ar->ap_hidden_ssid = hidden_ssid;
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_STA_LIST:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ A_UINT8 i;
+ ap_get_sta_t temp;
+ A_MEMZERO(&temp, sizeof(temp));
+ for(i=0;i<AP_MAX_NUM_STA;i++) {
+ A_MEMCPY(temp.sta[i].mac, ar->sta_list[i].mac, ATH_MAC_LEN);
+ temp.sta[i].aid = ar->sta_list[i].aid;
+ temp.sta[i].keymgmt = ar->sta_list[i].keymgmt;
+ temp.sta[i].ucipher = ar->sta_list[i].ucipher;
+ temp.sta[i].auth = ar->sta_list[i].auth;
+ }
+ if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp,
+ sizeof(ar->sta_list))) {
+ ret = -EFAULT;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_SET_NUM_STA:
+ {
+ A_UINT8 num_sta;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) {
+ ret = -EFAULT;
+ } else if(num_sta > AP_MAX_NUM_STA) {
+ /* value out of range */
+ ret = -EINVAL;
+ } else {
+ wmi_ap_set_num_sta(ar->arWmi, num_sta);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_SET_ACL_POLICY:
+ {
+ A_UINT8 policy;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&policy, userdata, sizeof(policy))) {
+ ret = -EFAULT;
+ } else if(policy == ar->g_acl.policy) {
+ /* No change in policy */
+ } else {
+ if(!(policy & AP_ACL_RETAIN_LIST_MASK)) {
+ /* clear ACL list */
+ memset(&ar->g_acl,0,sizeof(WMI_AP_ACL));
+ }
+ ar->g_acl.policy = policy;
+ wmi_ap_set_acl_policy(ar->arWmi, policy);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_SET_ACL_MAC:
+ {
+ WMI_AP_ACL_MAC_CMD acl;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&acl, userdata, sizeof(acl))) {
+ ret = -EFAULT;
+ } else {
+ if(acl_add_del_mac(&ar->g_acl, &acl)) {
+ wmi_ap_acl_mac_list(ar->arWmi, &acl);
+ } else {
+ A_PRINTF("ACL list error\n");
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_ACL_LIST:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl,
+ sizeof(WMI_AP_ACL))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_COMMIT_CONFIG:
+ {
+ ret = ar6000_ap_mode_profile_commit(ar);
+ break;
+ }
+ case IEEE80211_IOCTL_GETWPAIE:
+ {
+ struct ieee80211req_wpaie wpaie;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) {
+ ret = -EFAULT;
+ } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) {
+ ret = -EFAULT;
+ } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_CONN_INACT_TIME:
+ {
+ A_UINT32 period;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&period, userdata, sizeof(period))) {
+ ret = -EFAULT;
+ } else {
+ wmi_ap_conn_inact_time(ar->arWmi, period);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_PROT_SCAN_TIME:
+ {
+ WMI_AP_PROT_SCAN_TIME_CMD bgscan;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) {
+ ret = -EFAULT;
+ } else {
+ wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_SET_COUNTRY:
+ {
+ ret = ar6000_ioctl_set_country(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_AP_SET_DTIM:
+ {
+ WMI_AP_SET_DTIM_CMD d;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&d, userdata, sizeof(d))) {
+ ret = -EFAULT;
+ } else {
+ if(d.dtim > 0 && d.dtim < 11) {
+ ar->ap_dtim_period = d.dtim;
+ wmi_ap_set_dtim(ar->arWmi, d.dtim);
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ } else {
+ A_PRINTF("DTIM out of range. Valid range is [1-10]\n");
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT:
+ {
+ WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ }
+ if (copy_from_user(&evtCfgCmd, userdata,
+ sizeof(evtCfgCmd))) {
+ ret = -EFAULT;
+ break;
+ }
+ ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd);
+ break;
+ }
+ case AR6000_XIOCTL_AP_INTRA_BSS_COMM:
+ {
+ A_UINT8 intra=0;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&intra, userdata, sizeof(intra))) {
+ ret = -EFAULT;
+ } else {
+ ar->intra_bss = (intra?1:0);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO:
+ {
+ struct drv_debug_module_s moduleinfo;
+
+ if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ a_dump_module_debug_info_by_name(moduleinfo.modulename);
+ ret = 0;
+ break;
+ }
+ case AR6000_XIOCTL_MODULE_DEBUG_SET_MASK:
+ {
+ struct drv_debug_module_s moduleinfo;
+
+ if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ if (A_FAILED(a_set_module_mask(moduleinfo.modulename, moduleinfo.mask))) {
+ ret = -EFAULT;
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_MODULE_DEBUG_GET_MASK:
+ {
+ struct drv_debug_module_s moduleinfo;
+
+ if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ if (A_FAILED(a_get_module_mask(moduleinfo.modulename, &moduleinfo.mask))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ if (copy_to_user(userdata, &moduleinfo, sizeof(moduleinfo))) {
+ ret = -EFAULT;
+ break;
+ }
+
+ break;
+ }
+#ifdef ATH_AR6K_11N_SUPPORT
+ case AR6000_XIOCTL_DUMP_RCV_AGGR_STATS:
+ {
+ PACKET_LOG *copy_of_pkt_log;
+
+ aggr_dump_stats(ar->aggr_cntxt, &copy_of_pkt_log);
+ if (copy_to_user(rq->ifr_data, copy_of_pkt_log, sizeof(PACKET_LOG))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_SETUP_AGGR:
+ {
+ WMI_ADDBA_REQ_CMD cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ ret = -EFAULT;
+ } else {
+ wmi_setup_aggr_cmd(ar->arWmi, cmd.tid);
+ }
+ }
+ break;
+
+ case AR6000_XIOCTL_DELE_AGGR:
+ {
+ WMI_DELBA_REQ_CMD cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ ret = -EFAULT;
+ } else {
+ wmi_delete_aggr_cmd(ar->arWmi, cmd.tid, cmd.is_sender_initiator);
+ }
+ }
+ break;
+
+ case AR6000_XIOCTL_ALLOW_AGGR:
+ {
+ WMI_ALLOW_AGGR_CMD cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ ret = -EFAULT;
+ } else {
+ wmi_allow_aggr_cmd(ar->arWmi, cmd.tx_allow_aggr, cmd.rx_allow_aggr);
+ }
+ }
+ break;
+
+ case AR6000_XIOCTL_SET_HT_CAP:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&htCap, userdata,
+ sizeof(htCap)))
+ {
+ ret = -EFAULT;
+ } else {
+
+ if (wmi_set_ht_cap_cmd(ar->arWmi, &htCap) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_SET_HT_OP:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&htOp, userdata,
+ sizeof(htOp)))
+ {
+ ret = -EFAULT;
+ } else {
+
+ if (wmi_set_ht_op_cmd(ar->arWmi, htOp.sta_chan_width) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+#endif
+ case AR6000_XIOCTL_ACL_DATA:
+ {
+ void *osbuf = NULL;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (ar6000_create_acl_data_osbuf(dev, (A_UINT8*)userdata, &osbuf) != A_OK) {
+ ret = -EIO;
+ } else {
+ if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n"));
+ } else {
+ /* Send data buffer over HTC */
+ ar6000_acl_data_tx(osbuf, ar->arNetDev);
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_HCI_CMD:
+ {
+ char tmp_buf[512];
+ A_INT8 i;
+ WMI_HCI_CMD *cmd = (WMI_HCI_CMD *)tmp_buf;
+ A_UINT8 size;
+
+ size = sizeof(cmd->cmd_buf_sz);
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(cmd, userdata, size)) {
+ ret = -EFAULT;
+ } else if(copy_from_user(cmd->buf, userdata + size, cmd->cmd_buf_sz)) {
+ ret = -EFAULT;
+ } else {
+ if (wmi_send_hci_cmd(ar->arWmi, cmd->buf, cmd->cmd_buf_sz) != A_OK) {
+ ret = -EIO;
+ }else if(loghci) {
+ A_PRINTF_LOG("HCI Command To PAL --> \n");
+ for(i = 0; i < cmd->cmd_buf_sz; i++) {
+ A_PRINTF_LOG("0x%02x ",cmd->buf[i]);
+ if((i % 10) == 0) {
+ A_PRINTF_LOG("\n");
+ }
+ }
+ A_PRINTF_LOG("\n");
+ A_PRINTF_LOG("==================================\n");
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WLAN_CONN_PRECEDENCE:
+ {
+ WMI_SET_BT_WLAN_CONN_PRECEDENCE cmd;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ ret = -EFAULT;
+ } else {
+ if (cmd.precedence == BT_WLAN_CONN_PRECDENCE_WLAN ||
+ cmd.precedence == BT_WLAN_CONN_PRECDENCE_PAL) {
+ if ( wmi_set_wlan_conn_precedence_cmd(ar->arWmi, cmd.precedence) != A_OK) {
+ ret = -EIO;
+ }
+ } else {
+ ret = -EINVAL;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_STAT:
+ {
+ ret = ar6000_ioctl_get_ap_stats(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_SET_TX_SELECT_RATES:
+ {
+ WMI_SET_TX_SELECT_RATES_CMD masks;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&masks, userdata,
+ sizeof(masks)))
+ {
+ ret = -EFAULT;
+ } else {
+
+ if (wmi_set_tx_select_rates_cmd(ar->arWmi, masks.rateMasks) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_HIDDEN_SSID:
+ {
+ WMI_AP_HIDDEN_SSID_CMD ssid;
+ ssid.hidden_ssid = ar->ap_hidden_ssid;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((WMI_AP_HIDDEN_SSID_CMD *)rq->ifr_data,
+ &ssid, sizeof(WMI_AP_HIDDEN_SSID_CMD))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_COUNTRY:
+ {
+ WMI_AP_SET_COUNTRY_CMD cty;
+ A_MEMCPY(cty.countryCode, ar->ap_country_code, 3);
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((WMI_AP_SET_COUNTRY_CMD *)rq->ifr_data,
+ &cty, sizeof(WMI_AP_SET_COUNTRY_CMD))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_WMODE:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((A_UINT8 *)rq->ifr_data,
+ &ar->ap_wmode, sizeof(A_UINT8))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_DTIM:
+ {
+ WMI_AP_SET_DTIM_CMD dtim;
+ dtim.dtim = ar->ap_dtim_period;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((WMI_AP_SET_DTIM_CMD *)rq->ifr_data,
+ &dtim, sizeof(WMI_AP_SET_DTIM_CMD))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_BINTVL:
+ {
+ WMI_BEACON_INT_CMD bi;
+ bi.beaconInterval = ar->ap_beacon_interval;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((WMI_BEACON_INT_CMD *)rq->ifr_data,
+ &bi, sizeof(WMI_BEACON_INT_CMD))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_GET_RTS:
+ {
+ WMI_SET_RTS_CMD rts;
+ rts.threshold = ar->arRTS;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if(copy_to_user((WMI_SET_RTS_CMD *)rq->ifr_data,
+ &rts, sizeof(WMI_SET_RTS_CMD))) {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_FETCH_TARGET_REGS:
+ {
+ A_UINT32 targregs[AR6003_FETCH_TARG_REGS_COUNT];
+
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ ar6k_FetchTargetRegs(hifDevice, targregs);
+ if (copy_to_user((A_UINT32 *)rq->ifr_data, &targregs, sizeof(targregs)))
+ {
+ ret = -EFAULT;
+ }
+ } else {
+ ret = -EOPNOTSUPP;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_AP_SET_11BG_RATESET:
+ {
+ WMI_AP_SET_11BG_RATESET_CMD rate;
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&rate, userdata, sizeof(rate))) {
+ ret = -EFAULT;
+ } else {
+ wmi_ap_set_rateset(ar->arWmi, rate.rateset);
+ }
+ break;
+ }
+ default:
+ ret = -EOPNOTSUPP;
+ }
+
+ioctl_done:
+ rtnl_lock(); /* restore rtnl state */
+ dev_put(dev);
+
+ return ret;
+}
+
+A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild)
+{
+ A_UINT8 i;
+
+ for(i=0;i<ATH_MAC_LEN;i++) {
+ if((wild & 1<<i) && (new_wild & 1<<i)) continue;
+ if(mac[i] != new_mac[i]) return 1;
+ }
+ if((A_MEMCMP(new_mac, null_mac, 6)==0) && new_wild &&
+ (wild != new_wild)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+A_UINT8 acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl)
+{
+ A_INT8 already_avail=-1, free_slot=-1, i;
+
+ /* To check whether this mac is already there in our list */
+ for(i=AP_ACL_SIZE-1;i>=0;i--)
+ {
+ if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i],
+ acl->wildcard)==0)
+ already_avail = i;
+
+ if(!((1 << i) & a->index))
+ free_slot = i;
+ }
+
+ if(acl->action == ADD_MAC_ADDR)
+ {
+ /* Dont add mac if it is already available */
+ if((already_avail >= 0) || (free_slot == -1))
+ return 0;
+
+ A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN);
+ a->index = a->index | (1 << free_slot);
+ acl->index = free_slot;
+ a->wildcard[free_slot] = acl->wildcard;
+ return 1;
+ }
+ else if(acl->action == DEL_MAC_ADDR)
+ {
+ if(acl->index > AP_ACL_SIZE)
+ return 0;
+
+ if(!(a->index & (1 << acl->index)))
+ return 0;
+
+ A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN);
+ a->index = a->index & ~(1 << acl->index);
+ a->wildcard[acl->index] = 0;
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/drivers/net/wireless/ath6kl/os/linux/netbuf.c b/drivers/net/wireless/ath6kl/os/linux/netbuf.c
new file mode 100644
index 000000000000..62b26c540449
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/netbuf.c
@@ -0,0 +1,233 @@
+
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <a_config.h>
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_packet.h"
+
+#define AR6000_DATA_OFFSET 64
+
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+ skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+ skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q)
+{
+ return((void *) skb_dequeue((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q)
+{
+ return(skb_queue_len((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q)
+{
+ return(skb_queue_empty((struct sk_buff_head *) q));
+}
+
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q)
+{
+ skb_queue_head_init((struct sk_buff_head *) q);
+}
+
+void *
+a_netbuf_alloc(int size)
+{
+ struct sk_buff *skb;
+ size += 2 * (A_GET_CACHE_LINE_BYTES()); /* add some cacheline space at front and back of buffer */
+ skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size);
+ skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + A_GET_CACHE_LINE_BYTES());
+ return ((void *)skb);
+}
+
+/*
+ * Allocate an SKB w.o. any encapsulation requirement.
+ */
+void *
+a_netbuf_alloc_raw(int size)
+{
+ struct sk_buff *skb;
+
+ skb = dev_alloc_skb(size);
+
+ return ((void *)skb);
+}
+
+void
+a_netbuf_free(void *bufPtr)
+{
+ struct sk_buff *skb = (struct sk_buff *)bufPtr;
+
+ dev_kfree_skb(skb);
+}
+
+A_UINT32
+a_netbuf_to_len(void *bufPtr)
+{
+ return (((struct sk_buff *)bufPtr)->len);
+}
+
+void *
+a_netbuf_to_data(void *bufPtr)
+{
+ return (((struct sk_buff *)bufPtr)->data);
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_push(void *bufPtr, A_INT32 len)
+{
+ skb_push((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+ skb_push((struct sk_buff *) bufPtr, len);
+ A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_put(void *bufPtr, A_INT32 len)
+{
+ skb_put((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+ char *start = (char*)(((struct sk_buff *)bufPtr)->data +
+ ((struct sk_buff *)bufPtr)->len);
+ skb_put((struct sk_buff *)bufPtr, len);
+ A_MEMCPY(start, srcPtr, len);
+
+ return A_OK;
+}
+
+
+/*
+ * Trim the network buffer pointed to by bufPtr to len # of bytes
+ */
+A_STATUS
+a_netbuf_setlen(void *bufPtr, A_INT32 len)
+{
+ skb_trim((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer.
+ */
+A_STATUS
+a_netbuf_trim(void *bufPtr, A_INT32 len)
+{
+ skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+ return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer and return the data.
+ */
+A_STATUS
+a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+ char *start = (char*)(((struct sk_buff *)bufPtr)->data +
+ (((struct sk_buff *)bufPtr)->len - len));
+
+ A_MEMCPY(dstPtr, start, len);
+ skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+ return A_OK;
+}
+
+
+/*
+ * Returns the number of bytes available to a a_netbuf_push()
+ */
+A_INT32
+a_netbuf_headroom(void *bufPtr)
+{
+ return (skb_headroom((struct sk_buff *)bufPtr));
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ */
+A_STATUS
+a_netbuf_pull(void *bufPtr, A_INT32 len)
+{
+ skb_pull((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ * and return the data
+ */
+A_STATUS
+a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+ A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len);
+ skb_pull((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+#ifdef EXPORT_HCI_BRIDGE_INTERFACE
+EXPORT_SYMBOL(a_netbuf_to_data);
+EXPORT_SYMBOL(a_netbuf_put);
+EXPORT_SYMBOL(a_netbuf_pull);
+EXPORT_SYMBOL(a_netbuf_alloc);
+EXPORT_SYMBOL(a_netbuf_free);
+#endif
diff --git a/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c b/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c
new file mode 100644
index 000000000000..9d17574aef09
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c
@@ -0,0 +1,2703 @@
+/*
+ *
+ * Copyright (c) 2004-2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#include "ar6000_drv.h"
+
+static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi);
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+
+#if WIRELESS_EXT > 14
+/*
+ * Encode a WPA or RSN information element as a custom
+ * element using the hostap format.
+ */
+static u_int
+encode_ie(void *buf, size_t bufsize,
+ const u_int8_t *ie, size_t ielen,
+ const char *leader, size_t leader_len)
+{
+ u_int8_t *p;
+ int i;
+
+ if (bufsize < leader_len)
+ return 0;
+ p = buf;
+ memcpy(p, leader, leader_len);
+ bufsize -= leader_len;
+ p += leader_len;
+ for (i = 0; i < ielen && bufsize > 2; i++)
+ {
+ p += sprintf((char*)p, "%02x", ie[i]);
+ bufsize -= 2;
+ }
+ return (i == ielen ? p - (u_int8_t *)buf : 0);
+}
+#endif /* WIRELESS_EXT > 14 */
+
+void
+ar6000_scan_node(void *arg, bss_t *ni)
+{
+ struct iw_event iwe;
+#if WIRELESS_EXT > 14
+ char buf[256];
+#endif
+ struct ar_giwscan_param *param;
+ A_CHAR *current_ev;
+ A_CHAR *end_buf;
+ struct ieee80211_common_ie *cie;
+ A_CHAR *current_val;
+ A_INT32 j;
+ A_UINT32 rate_len, data_len = 0;
+
+ param = (struct ar_giwscan_param *)arg;
+
+ current_ev = param->current_ev;
+ end_buf = param->end_buf;
+
+ cie = &ni->ni_cie;
+
+ if ((end_buf - current_ev) > IW_EV_ADDR_LEN)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWAP;
+ iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
+ A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
+ current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe,
+ IW_EV_ADDR_LEN);
+ }
+ param->bytes_needed += IW_EV_ADDR_LEN;
+
+ data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWESSID;
+ iwe.u.data.flags = 1;
+ iwe.u.data.length = cie->ie_ssid[1];
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe,
+ (char*)&cie->ie_ssid[2]);
+ }
+ param->bytes_needed += data_len;
+
+ if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
+ if ((end_buf - current_ev) > IW_EV_UINT_LEN)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWMODE;
+ iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
+ IW_MODE_MASTER : IW_MODE_ADHOC;
+ current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe,
+ IW_EV_UINT_LEN);
+ }
+ param->bytes_needed += IW_EV_UINT_LEN;
+ }
+
+ if ((end_buf - current_ev) > IW_EV_FREQ_LEN)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWFREQ;
+ iwe.u.freq.m = cie->ie_chan * 100000;
+ iwe.u.freq.e = 1;
+ current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe,
+ IW_EV_FREQ_LEN);
+ }
+ param->bytes_needed += IW_EV_FREQ_LEN;
+
+ if ((end_buf - current_ev) > IW_EV_QUAL_LEN)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVQUAL;
+ ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
+ current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe,
+ IW_EV_QUAL_LEN);
+ }
+ param->bytes_needed += IW_EV_QUAL_LEN;
+
+ if ((end_buf - current_ev) > IW_EV_POINT_LEN)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWENCODE;
+ if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
+ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
+ } else {
+ iwe.u.data.flags = IW_ENCODE_DISABLED;
+ }
+ iwe.u.data.length = 0;
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, "");
+ }
+ param->bytes_needed += IW_EV_POINT_LEN;
+
+ /* supported bit rate */
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWRATE;
+ iwe.u.bitrate.fixed = 0;
+ iwe.u.bitrate.disabled = 0;
+ iwe.u.bitrate.value = 0;
+ current_val = current_ev + IW_EV_LCP_LEN;
+ param->bytes_needed += IW_EV_LCP_LEN;
+
+ if (cie->ie_rates != NULL) {
+ rate_len = cie->ie_rates[1];
+ data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
+ if ((end_buf - current_ev) > data_len)
+ {
+ for (j = 0; j < rate_len; j++) {
+ unsigned char val;
+ val = cie->ie_rates[2 + j];
+ iwe.u.bitrate.value =
+ (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
+ current_val = iwe_stream_add_value(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev,
+ current_val,
+ end_buf,
+ &iwe,
+ IW_EV_PARAM_LEN);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+
+ if (cie->ie_xrates != NULL) {
+ rate_len = cie->ie_xrates[1];
+ data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
+ if ((end_buf - current_ev) > data_len)
+ {
+ for (j = 0; j < rate_len; j++) {
+ unsigned char val;
+ val = cie->ie_xrates[2 + j];
+ iwe.u.bitrate.value =
+ (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
+ current_val = iwe_stream_add_value(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev,
+ current_val,
+ end_buf,
+ &iwe,
+ IW_EV_PARAM_LEN);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+ /* remove fixed header if no rates were added */
+ if ((current_val - current_ev) > IW_EV_LCP_LEN)
+ current_ev = current_val;
+
+#if WIRELESS_EXT >= 18
+ /* IE */
+ if (cie->ie_wpa != NULL) {
+ data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVGENIE;
+ iwe.u.data.length = cie->ie_wpa[1] + 2;
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, (char*)cie->ie_wpa);
+ }
+ param->bytes_needed += data_len;
+ }
+
+ if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+ data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVGENIE;
+ iwe.u.data.length = cie->ie_rsn[1] + 2;
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, (char*)cie->ie_rsn);
+ }
+ param->bytes_needed += data_len;
+ }
+
+#endif /* WIRELESS_EXT >= 18 */
+
+ if ((end_buf - current_ev) > IW_EV_CHAR_LEN)
+ {
+ /* protocol */
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWNAME;
+#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484)))
+ if (CHAN_IS_11A(cie->ie_chan)) {
+ if (cie->ie_htcap) {
+ /* 11na */
+ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11na");
+ }
+ else {
+ /* 11a */
+ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a");
+ }
+ } else if ((cie->ie_erp) || (cie->ie_xrates)) {
+ if (cie->ie_htcap) {
+ /* 11ng */
+ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11ng");
+ }
+ else {
+ /* 11g */
+ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g");
+ }
+ } else {
+ /* 11b */
+ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b");
+ }
+ current_ev = iwe_stream_add_event(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, IW_EV_CHAR_LEN);
+ }
+ param->bytes_needed += IW_EV_CHAR_LEN;
+
+#if WIRELESS_EXT > 14
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
+ data_len = iwe.u.data.length + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, buf);
+ }
+ param->bytes_needed += data_len;
+
+#if WIRELESS_EXT < 18
+ if (cie->ie_wpa != NULL) {
+ static const char wpa_leader[] = "wpa_ie=";
+ data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
+ cie->ie_wpa[1]+2,
+ wpa_leader, sizeof(wpa_leader)-1);
+
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, buf);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+
+ if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+ static const char rsn_leader[] = "rsn_ie=";
+ data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
+ cie->ie_rsn[1]+2,
+ rsn_leader, sizeof(rsn_leader)-1);
+
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, buf);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+#endif /* WIRELESS_EXT < 18 */
+
+ if (cie->ie_wmm != NULL) {
+ static const char wmm_leader[] = "wmm_ie=";
+ data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
+ cie->ie_wmm[1]+2,
+ wmm_leader, sizeof(wmm_leader)-1);
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, buf);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+
+ if (cie->ie_ath != NULL) {
+ static const char ath_leader[] = "ath_ie=";
+ data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
+ cie->ie_ath[1]+2,
+ ath_leader, sizeof(ath_leader)-1);
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, buf);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+
+#ifdef WAPI_ENABLE
+ if (cie->ie_wapi != NULL) {
+ static const char wapi_leader[] = "wapi_ie=";
+ data_len = (sizeof(wapi_leader) - 1) + ((cie->ie_wapi[1] + 2) * 2) + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len) {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wapi,
+ cie->ie_wapi[1] + 2,
+ wapi_leader, sizeof(wapi_leader) - 1);
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, buf);
+ }
+ }
+ param->bytes_needed += data_len;
+ }
+#endif /* WAPI_ENABLE */
+
+#endif /* WIRELESS_EXT > 14 */
+
+#if WIRELESS_EXT >= 18
+ if (cie->ie_wsc != NULL) {
+ data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN;
+ if ((end_buf - current_ev) > data_len)
+ {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVGENIE;
+ iwe.u.data.length = cie->ie_wsc[1] + 2;
+ current_ev = iwe_stream_add_point(
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param->info,
+#endif
+ current_ev, end_buf, &iwe, (char*)cie->ie_wsc);
+ }
+ param->bytes_needed += data_len;
+ }
+#endif /* WIRELESS_EXT >= 18 */
+
+ param->current_ev = current_ev;
+}
+
+int
+ar6000_ioctl_giwscan(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ struct ar_giwscan_param param;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ param.current_ev = extra;
+ param.end_buf = extra + data->length;
+ param.bytes_needed = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
+ param.info = info;
+#endif
+
+ /* Translate data to WE format */
+ wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, &param);
+
+ /* check if bytes needed is greater than bytes consumed */
+ if (param.bytes_needed > (param.current_ev - extra))
+ {
+ /* Request one byte more than needed, because when "data->length" equals bytes_needed,
+ it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions
+ checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/
+ data->length = param.bytes_needed + 1;
+
+ return -E2BIG;
+ }
+
+ return 0;
+}
+
+extern int reconnect_flag;
+/* SIOCSIWESSID */
+static int
+ar6000_ioctl_siwessid(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *ssid)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_STATUS status;
+ A_UINT8 arNetworkType;
+ A_UINT8 prevMode = ar->arNetworkType;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+#if defined(WIRELESS_EXT)
+ if (WIRELESS_EXT >= 20) {
+ data->length += 1;
+ }
+#endif
+
+ /*
+ * iwconfig passes a null terminated string with length including this
+ * so we need to account for this
+ */
+ if (data->flags && (!data->length || (data->length == 1) ||
+ ((data->length - 1) > sizeof(ar->arSsid))))
+ {
+ /*
+ * ssid is invalid
+ */
+ return -EINVAL;
+ }
+
+ if (ar->arNextMode == AP_NETWORK) {
+ /* SSID change for AP network - Will take effect on commit */
+ if(A_MEMCMP(ar->arSsid,ssid,32) != 0) {
+ ar->arSsidLen = data->length - 1;
+ A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ }
+ return 0;
+ } else if(ar->arNetworkType == AP_NETWORK) {
+ A_UINT8 ctr;
+ struct sk_buff *skb;
+
+ /* We are switching from AP to STA | IBSS mode, cleanup the AP state */
+ for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) {
+ remove_sta(ar, ar->sta_list[ctr].mac, 0);
+ }
+ A_MUTEX_LOCK(&ar->mcastpsqLock);
+ while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
+ skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
+ A_NETBUF_FREE(skb);
+ }
+ A_MUTEX_UNLOCK(&ar->mcastpsqLock);
+ }
+
+ /* Added for bug 25178, return an IOCTL error instead of target returning
+ Illegal parameter error when either the BSSID or channel is missing
+ and we cannot scan during connect.
+ */
+ if (data->flags) {
+ if (ar->arSkipScan == TRUE &&
+ (ar->arChannelHint == 0 ||
+ (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
+ !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
+ {
+ return -EINVAL;
+ }
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
+ /*
+ * sleep until the command queue drains
+ */
+ wait_event_interruptible_timeout(arEvent,
+ ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ return -EINTR;
+ }
+ }
+
+ if (!data->flags) {
+ arNetworkType = ar->arNetworkType;
+ ar6000_init_profile_info(ar);
+ ar->arNetworkType = arNetworkType;
+ }
+
+ /* Update the arNetworkType */
+ ar->arNetworkType = ar->arNextMode;
+
+
+ if ((prevMode != AP_NETWORK) &&
+ ((ar->arSsidLen) || ((ar->arSsidLen == 0) && ar->arConnected) || (!data->flags)))
+ {
+ if ((!data->flags) ||
+ (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
+ (ar->arSsidLen != (data->length - 1)))
+ {
+ /*
+ * SSID set previously or essid off has been issued.
+ *
+ * Disconnect Command is issued in two cases after wmi is ready
+ * (1) ssid is different from the previous setting
+ * (2) essid off has been issued
+ *
+ */
+ if (ar->arWmiReady == TRUE) {
+ reconnect_flag = 0;
+ status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+ status = wmi_disconnect_cmd(ar->arWmi);
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ if (ar->arSkipScan == FALSE) {
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ }
+ if (!data->flags) {
+ up(&ar->arSem);
+ return 0;
+ }
+ } else {
+ up(&ar->arSem);
+ }
+ }
+ else
+ {
+ /*
+ * SSID is same, so we assume profile hasn't changed.
+ * If the interface is up and wmi is ready, we issue
+ * a reconnect cmd. Issue a reconnect only we are already
+ * connected.
+ */
+ if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE))
+ {
+ reconnect_flag = TRUE;
+ status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
+ ar->arChannelHint);
+ up(&ar->arSem);
+ if (status != A_OK) {
+ return -EIO;
+ }
+ return 0;
+ }
+ else{
+ /*
+ * Dont return if connect is pending.
+ */
+ if(!(ar->arConnectPending)) {
+ up(&ar->arSem);
+ return 0;
+ }
+ }
+ }
+ }
+
+ ar->arSsidLen = data->length - 1;
+ A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+
+ if (ar6000_connect_to_ap(ar)!= A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }else{
+ up(&ar->arSem);
+ }
+ return 0;
+}
+
+/* SIOCGIWESSID */
+static int
+ar6000_ioctl_giwessid(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *essid)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (!ar->arSsidLen) {
+ return -EINVAL;
+ }
+
+ data->flags = 1;
+ data->length = ar->arSsidLen;
+ A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
+
+ return 0;
+}
+
+
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
+{
+ A_UINT8 index;
+ A_UINT8 keyUsage;
+
+ for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
+ if (ar->arWepKeyList[index].arKeyLen) {
+ keyUsage = GROUP_USAGE;
+ if (index == ar->arDefTxKeyIndex) {
+ keyUsage |= TX_USAGE;
+ }
+ wmi_addKey_cmd(ar->arWmi,
+ index,
+ WEP_CRYPT,
+ keyUsage,
+ ar->arWepKeyList[index].arKeyLen,
+ NULL,
+ ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+ NO_SYNC_WMIFLAG);
+ }
+ }
+}
+
+/*
+ * SIOCSIWRATE
+ */
+int
+ar6000_ioctl_siwrate(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT32 kbps;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (rrq->fixed) {
+ kbps = rrq->value / 1000; /* rrq->value is in bps */
+ } else {
+ kbps = -1; /* -1 indicates auto rate */
+ }
+ if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BitRate is not Valid %d\n", kbps));
+ return -EINVAL;
+ }
+ ar->arBitRate = kbps;
+ if(ar->arWmiReady == TRUE)
+ {
+ if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) {
+ return -EINVAL;
+ }
+ }
+ return 0;
+}
+
+/*
+ * SIOCGIWRATE
+ */
+int
+ar6000_ioctl_giwrate(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ int ret = 0;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ if(ar->arWmiReady == TRUE)
+ {
+ ar->arBitRate = 0xFFFF;
+ if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+ wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+ }
+ /* If the interface is down or wmi is not ready or the target is not
+ connected - return the value stored in the device structure */
+ if (!ret) {
+ if (ar->arBitRate == -1) {
+ rrq->fixed = TRUE;
+ rrq->value = 0;
+ } else {
+ rrq->value = ar->arBitRate * 1000;
+ }
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+/*
+ * SIOCSIWTXPOW
+ */
+static int
+ar6000_ioctl_siwtxpow(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT8 dbM;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (rrq->disabled) {
+ return -EOPNOTSUPP;
+ }
+
+ if (rrq->fixed) {
+ if (rrq->flags != IW_TXPOW_DBM) {
+ return -EOPNOTSUPP;
+ }
+ ar->arTxPwr= dbM = rrq->value;
+ ar->arTxPwrSet = TRUE;
+ } else {
+ ar->arTxPwr = dbM = 0;
+ ar->arTxPwrSet = FALSE;
+ }
+ if(ar->arWmiReady == TRUE)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("Set tx pwr cmd %d dbM\n", dbM));
+ wmi_set_txPwr_cmd(ar->arWmi, dbM);
+ }
+ return 0;
+}
+
+/*
+ * SIOCGIWTXPOW
+ */
+int
+ar6000_ioctl_giwtxpow(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ int ret = 0;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
+ {
+ ar->arTxPwr = 0;
+
+ if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+ }
+ /* If the interace is down or wmi is not ready or target is not connected
+ then return value stored in the device structure */
+
+ if (!ret) {
+ if (ar->arTxPwrSet == TRUE) {
+ rrq->fixed = TRUE;
+ }
+ rrq->value = ar->arTxPwr;
+ rrq->flags = IW_TXPOW_DBM;
+ //
+ // IWLIST need this flag to get TxPower
+ //
+ rrq->disabled = 0;
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+/*
+ * SIOCSIWRETRY
+ * since iwconfig only provides us with one max retry value, we use it
+ * to apply to data frames of the BE traffic class.
+ */
+static int
+ar6000_ioctl_siwretry(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (rrq->disabled) {
+ return -EOPNOTSUPP;
+ }
+
+ if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
+ return -EOPNOTSUPP;
+ }
+
+ if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
+ return - EINVAL;
+ }
+ if(ar->arWmiReady == TRUE)
+ {
+ if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
+ rrq->value, 0) != A_OK){
+ return -EINVAL;
+ }
+ }
+ ar->arMaxRetries = rrq->value;
+ return 0;
+}
+
+/*
+ * SIOCGIWRETRY
+ */
+static int
+ar6000_ioctl_giwretry(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ rrq->disabled = 0;
+ switch (rrq->flags & IW_RETRY_TYPE) {
+ case IW_RETRY_LIFETIME:
+ return -EOPNOTSUPP;
+ break;
+ case IW_RETRY_LIMIT:
+ rrq->flags = IW_RETRY_LIMIT;
+ switch (rrq->flags & IW_RETRY_MODIFIER) {
+ case IW_RETRY_MIN:
+ rrq->flags |= IW_RETRY_MIN;
+ rrq->value = WMI_MIN_RETRIES;
+ break;
+ case IW_RETRY_MAX:
+ rrq->flags |= IW_RETRY_MAX;
+ rrq->value = ar->arMaxRetries;
+ break;
+ }
+ break;
+ }
+ return 0;
+}
+
+/*
+ * SIOCSIWENCODE
+ */
+static int
+ar6000_ioctl_siwencode(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *keybuf)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ int index;
+ A_INT32 auth = 0;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if(ar->arNextMode != AP_NETWORK) {
+ /*
+ * Static WEP Keys should be configured before setting the SSID
+ */
+ if (ar->arSsid[0] && erq->length) {
+ return -EIO;
+ }
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ index = erq->flags & IW_ENCODE_INDEX;
+
+ if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+ ((index - 1) > WMI_MAX_KEY_INDEX)))
+ {
+ return -EIO;
+ }
+
+ if (erq->flags & IW_ENCODE_DISABLED) {
+ /*
+ * Encryption disabled
+ */
+ if (index) {
+ /*
+ * If key index was specified then clear the specified key
+ */
+ index--;
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ ar->arWepKeyList[index].arKeyLen = 0;
+ }
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arAuthMode = NONE_AUTH;
+ } else {
+ /*
+ * Enabling WEP encryption
+ */
+ if (index) {
+ index--; /* keyindex is off base 1 in iwconfig */
+ }
+
+ if (erq->flags & IW_ENCODE_OPEN) {
+ auth |= OPEN_AUTH;
+ ar->arDefTxKeyIndex = index;
+ }
+ if (erq->flags & IW_ENCODE_RESTRICTED) {
+ auth |= SHARED_AUTH;
+ }
+
+ if (!auth) {
+ auth = OPEN_AUTH;
+ }
+
+ if (erq->length) {
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
+ return -EIO;
+ }
+
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
+ ar->arWepKeyList[index].arKeyLen = erq->length;
+ ar->arDot11AuthMode = auth;
+ } else {
+ if (ar->arWepKeyList[index].arKeyLen == 0) {
+ return -EIO;
+ }
+ ar->arDefTxKeyIndex = index;
+
+ if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) {
+ wmi_addKey_cmd(ar->arWmi,
+ index,
+ WEP_CRYPT,
+ GROUP_USAGE | TX_USAGE,
+ ar->arWepKeyList[index].arKeyLen,
+ NULL,
+ ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+ NO_SYNC_WMIFLAG);
+ }
+ }
+
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arGroupCrypto = WEP_CRYPT;
+ ar->arAuthMode = NONE_AUTH;
+ }
+
+ if(ar->arNextMode != AP_NETWORK) {
+ /*
+ * profile has changed. Erase ssid to signal change
+ */
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+ return 0;
+}
+
+static int
+ar6000_ioctl_giwencode(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *key)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT8 keyIndex;
+ struct ar_wep_key *wk;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arPairwiseCrypto == NONE_CRYPT) {
+ erq->length = 0;
+ erq->flags = IW_ENCODE_DISABLED;
+ } else {
+ if (ar->arPairwiseCrypto == WEP_CRYPT) {
+ /* get the keyIndex */
+ keyIndex = erq->flags & IW_ENCODE_INDEX;
+ if (0 == keyIndex) {
+ keyIndex = ar->arDefTxKeyIndex;
+ } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
+ (keyIndex - 1 > WMI_MAX_KEY_INDEX))
+ {
+ keyIndex = WMI_MIN_KEY_INDEX;
+ } else {
+ keyIndex--;
+ }
+ erq->flags = keyIndex + 1;
+ erq->flags &= ~IW_ENCODE_DISABLED;
+ wk = &ar->arWepKeyList[keyIndex];
+ if (erq->length > wk->arKeyLen) {
+ erq->length = wk->arKeyLen;
+ }
+ if (wk->arKeyLen) {
+ A_MEMCPY(key, wk->arKey, erq->length);
+ }
+ } else {
+ erq->flags &= ~IW_ENCODE_DISABLED;
+ if (ar->user_saved_keys.keyOk) {
+ erq->length = ar->user_saved_keys.ucast_ik.ik_keylen;
+ if (erq->length) {
+ A_MEMCPY(key, ar->user_saved_keys.ucast_ik.ik_keydata, erq->length);
+ }
+ } else {
+ erq->length = 1; // not really printing any key but let iwconfig know enc is on
+ }
+ }
+
+ if (ar->arDot11AuthMode & OPEN_AUTH) {
+ erq->flags |= IW_ENCODE_OPEN;
+ }
+ if (ar->arDot11AuthMode & SHARED_AUTH) {
+ erq->flags |= IW_ENCODE_RESTRICTED;
+ }
+ }
+
+ return 0;
+}
+
+#if WIRELESS_EXT >= 18
+/*
+ * SIOCSIWGENIE
+ */
+static int
+ar6000_ioctl_siwgenie(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+#ifdef WAPI_ENABLE
+ A_UINT8 *ie = erq->pointer;
+ A_UINT8 ie_type = ie[0];
+ A_UINT16 ie_length = erq->length;
+ A_UINT8 wapi_ie[128];
+#endif
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+#ifdef WAPI_ENABLE
+ if (ie_type == IEEE80211_ELEMID_WAPI) {
+ if(copy_from_user(wapi_ie, ie, ie_length))
+ return -EIO;
+ wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie);
+ }
+#endif
+ return 0;
+}
+
+
+/*
+ * SIOCGIWGENIE
+ */
+static int
+ar6000_ioctl_giwgenie(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ erq->length = 0;
+ erq->flags = 0;
+
+ return 0;
+}
+
+/*
+ * SIOCSIWAUTH
+ */
+static int
+ar6000_ioctl_siwauth(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ A_BOOL profChanged;
+ A_UINT16 param;
+ A_INT32 ret;
+ A_INT32 value;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ param = data->flags & IW_AUTH_INDEX;
+ value = data->value;
+ profChanged = TRUE;
+ ret = 0;
+
+ switch (param) {
+ case IW_AUTH_WPA_VERSION:
+ if (value & IW_AUTH_WPA_VERSION_DISABLED) {
+ ar->arAuthMode = NONE_AUTH;
+ } else if (value & IW_AUTH_WPA_VERSION_WPA) {
+ ar->arAuthMode = WPA_AUTH;
+ } else if (value & IW_AUTH_WPA_VERSION_WPA2) {
+ ar->arAuthMode = WPA2_AUTH;
+ } else {
+ ret = -1;
+ profChanged = FALSE;
+ }
+ break;
+ case IW_AUTH_CIPHER_PAIRWISE:
+ if (value & IW_AUTH_CIPHER_NONE) {
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ } else if (value & IW_AUTH_CIPHER_WEP40) {
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arPairwiseCryptoLen = 5;
+ } else if (value & IW_AUTH_CIPHER_TKIP) {
+ ar->arPairwiseCrypto = TKIP_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ } else if (value & IW_AUTH_CIPHER_CCMP) {
+ ar->arPairwiseCrypto = AES_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ } else if (value & IW_AUTH_CIPHER_WEP104) {
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arPairwiseCryptoLen = 13;
+ } else {
+ ret = -1;
+ profChanged = FALSE;
+ }
+ break;
+ case IW_AUTH_CIPHER_GROUP:
+ if (value & IW_AUTH_CIPHER_NONE) {
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ } else if (value & IW_AUTH_CIPHER_WEP40) {
+ ar->arGroupCrypto = WEP_CRYPT;
+ ar->arGroupCryptoLen = 5;
+ } else if (value & IW_AUTH_CIPHER_TKIP) {
+ ar->arGroupCrypto = TKIP_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ } else if (value & IW_AUTH_CIPHER_CCMP) {
+ ar->arGroupCrypto = AES_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ } else if (value & IW_AUTH_CIPHER_WEP104) {
+ ar->arGroupCrypto = WEP_CRYPT;
+ ar->arGroupCryptoLen = 13;
+ } else {
+ ret = -1;
+ profChanged = FALSE;
+ }
+ break;
+ case IW_AUTH_KEY_MGMT:
+ if (value & IW_AUTH_KEY_MGMT_PSK) {
+ if (WPA_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA_PSK_AUTH;
+ } else if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_PSK_AUTH;
+ } else {
+ ret = -1;
+ }
+ } else if (!(value & IW_AUTH_KEY_MGMT_802_1X)) {
+ ar->arAuthMode = NONE_AUTH;
+ }
+ break;
+ case IW_AUTH_TKIP_COUNTERMEASURES:
+ wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+ profChanged = FALSE;
+ break;
+ case IW_AUTH_DROP_UNENCRYPTED:
+ profChanged = FALSE;
+ break;
+ case IW_AUTH_80211_AUTH_ALG:
+ ar->arDot11AuthMode = 0;
+ if (value & IW_AUTH_ALG_OPEN_SYSTEM) {
+ ar->arDot11AuthMode |= OPEN_AUTH;
+ }
+ if (value & IW_AUTH_ALG_SHARED_KEY) {
+ ar->arDot11AuthMode |= SHARED_AUTH;
+ }
+ if (value & IW_AUTH_ALG_LEAP) {
+ ar->arDot11AuthMode = LEAP_AUTH;
+ }
+ if(ar->arDot11AuthMode == 0) {
+ ret = -1;
+ profChanged = FALSE;
+ }
+ break;
+ case IW_AUTH_WPA_ENABLED:
+ if (!value) {
+ ar->arAuthMode = NONE_AUTH;
+ /* when the supplicant is stopped, it calls this
+ * handler with value=0. The followings need to be
+ * reset if the STA were to connect again
+ * without security
+ */
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ }
+ break;
+ case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+ profChanged = FALSE;
+ break;
+ case IW_AUTH_ROAMING_CONTROL:
+ profChanged = FALSE;
+ break;
+ case IW_AUTH_PRIVACY_INVOKED:
+ if (!value) {
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ }
+ break;
+#ifdef WAPI_ENABLE
+ case IW_AUTH_WAPI_ENABLED:
+ ar->arWapiEnable = value;
+ break;
+#endif
+ default:
+ ret = -1;
+ profChanged = FALSE;
+ break;
+ }
+
+ if (profChanged == TRUE) {
+ /*
+ * profile has changed. Erase ssid to signal change
+ */
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+
+ return ret;
+}
+
+
+/*
+ * SIOCGIWAUTH
+ */
+static int
+ar6000_ioctl_giwauth(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_UINT16 param;
+ A_INT32 ret;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ param = data->flags & IW_AUTH_INDEX;
+ ret = 0;
+ data->value = 0;
+
+
+ switch (param) {
+ case IW_AUTH_WPA_VERSION:
+ if (ar->arAuthMode == NONE_AUTH) {
+ data->value |= IW_AUTH_WPA_VERSION_DISABLED;
+ } else if (ar->arAuthMode == WPA_AUTH) {
+ data->value |= IW_AUTH_WPA_VERSION_WPA;
+ } else if (ar->arAuthMode == WPA2_AUTH) {
+ data->value |= IW_AUTH_WPA_VERSION_WPA2;
+ } else {
+ ret = -1;
+ }
+ break;
+ case IW_AUTH_CIPHER_PAIRWISE:
+ if (ar->arPairwiseCrypto == NONE_CRYPT) {
+ data->value |= IW_AUTH_CIPHER_NONE;
+ } else if (ar->arPairwiseCrypto == WEP_CRYPT) {
+ if (ar->arPairwiseCryptoLen == 13) {
+ data->value |= IW_AUTH_CIPHER_WEP104;
+ } else {
+ data->value |= IW_AUTH_CIPHER_WEP40;
+ }
+ } else if (ar->arPairwiseCrypto == TKIP_CRYPT) {
+ data->value |= IW_AUTH_CIPHER_TKIP;
+ } else if (ar->arPairwiseCrypto == AES_CRYPT) {
+ data->value |= IW_AUTH_CIPHER_CCMP;
+ } else {
+ ret = -1;
+ }
+ break;
+ case IW_AUTH_CIPHER_GROUP:
+ if (ar->arGroupCrypto == NONE_CRYPT) {
+ data->value |= IW_AUTH_CIPHER_NONE;
+ } else if (ar->arGroupCrypto == WEP_CRYPT) {
+ if (ar->arGroupCryptoLen == 13) {
+ data->value |= IW_AUTH_CIPHER_WEP104;
+ } else {
+ data->value |= IW_AUTH_CIPHER_WEP40;
+ }
+ } else if (ar->arGroupCrypto == TKIP_CRYPT) {
+ data->value |= IW_AUTH_CIPHER_TKIP;
+ } else if (ar->arGroupCrypto == AES_CRYPT) {
+ data->value |= IW_AUTH_CIPHER_CCMP;
+ } else {
+ ret = -1;
+ }
+ break;
+ case IW_AUTH_KEY_MGMT:
+ if ((ar->arAuthMode == WPA_PSK_AUTH) ||
+ (ar->arAuthMode == WPA2_PSK_AUTH)) {
+ data->value |= IW_AUTH_KEY_MGMT_PSK;
+ } else if ((ar->arAuthMode == WPA_AUTH) ||
+ (ar->arAuthMode == WPA2_AUTH)) {
+ data->value |= IW_AUTH_KEY_MGMT_802_1X;
+ }
+ break;
+ case IW_AUTH_TKIP_COUNTERMEASURES:
+ // TODO. Save countermeassure enable/disable
+ data->value = 0;
+ break;
+ case IW_AUTH_DROP_UNENCRYPTED:
+ break;
+ case IW_AUTH_80211_AUTH_ALG:
+ if (ar->arDot11AuthMode == OPEN_AUTH) {
+ data->value |= IW_AUTH_ALG_OPEN_SYSTEM;
+ } else if (ar->arDot11AuthMode == SHARED_AUTH) {
+ data->value |= IW_AUTH_ALG_SHARED_KEY;
+ } else if (ar->arDot11AuthMode == LEAP_AUTH) {
+ data->value |= IW_AUTH_ALG_LEAP;
+ } else {
+ ret = -1;
+ }
+ break;
+ case IW_AUTH_WPA_ENABLED:
+ if (ar->arAuthMode == NONE_AUTH) {
+ data->value = 0;
+ } else {
+ data->value = 1;
+ }
+ break;
+ case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+ break;
+ case IW_AUTH_ROAMING_CONTROL:
+ break;
+ case IW_AUTH_PRIVACY_INVOKED:
+ if (ar->arPairwiseCrypto == NONE_CRYPT) {
+ data->value = 0;
+ } else {
+ data->value = 1;
+ }
+ break;
+#ifdef WAPI_ENABLE
+ case IW_AUTH_WAPI_ENABLED:
+ data->value = ar->arWapiEnable;
+ break;
+#endif
+ default:
+ ret = -1;
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCSIWPMKSA
+ */
+static int
+ar6000_ioctl_siwpmksa(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_INT32 ret;
+ A_STATUS status;
+ struct iw_pmksa *pmksa;
+
+ pmksa = (struct iw_pmksa *)extra;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ ret = 0;
+ status = A_OK;
+
+ switch (pmksa->cmd) {
+ case IW_PMKSA_ADD:
+ status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, TRUE);
+ break;
+ case IW_PMKSA_REMOVE:
+ status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, FALSE);
+ break;
+ case IW_PMKSA_FLUSH:
+ if (ar->arConnected == TRUE) {
+ status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+ }
+ break;
+ default:
+ ret=-1;
+ break;
+ }
+ if (status != A_OK) {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+#ifdef WAPI_ENABLE
+
+#define PN_INIT 0x5c365c36
+
+static int ar6000_set_wapi_key(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
+ KEY_USAGE keyUsage = 0;
+ A_INT32 keyLen;
+ A_UINT8 *keyData;
+ A_INT32 index;
+ A_UINT32 *PN;
+ A_INT32 i;
+ A_STATUS status;
+ A_UINT8 wapiKeyRsc[16];
+ CRYPTO_TYPE keyType = WAPI_CRYPT;
+ const A_UINT8 broadcastMac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+ index = erq->flags & IW_ENCODE_INDEX;
+ if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+ ((index - 1) > WMI_MAX_KEY_INDEX))) {
+ return -EIO;
+ }
+
+ index--;
+ if (index < 0 || index > 4) {
+ return -EIO;
+ }
+ keyData = (A_UINT8 *)(ext + 1);
+ keyLen = erq->length - sizeof(struct iw_encode_ext);
+ A_MEMCPY(wapiKeyRsc, ext->tx_seq, sizeof(wapiKeyRsc));
+
+ if (A_MEMCMP(ext->addr.sa_data, broadcastMac, sizeof(broadcastMac)) == 0) {
+ keyUsage |= GROUP_USAGE;
+ PN = (A_UINT32 *)wapiKeyRsc;
+ for (i = 0; i < 4; i++) {
+ PN[i] = PN_INIT;
+ }
+ } else {
+ keyUsage |= PAIRWISE_USAGE;
+ }
+ status = wmi_addKey_cmd(ar->arWmi,
+ index,
+ keyType,
+ keyUsage,
+ keyLen,
+ wapiKeyRsc,
+ keyData,
+ KEY_OP_INIT_WAPIPN,
+ NULL,
+ SYNC_BEFORE_WMIFLAG);
+ if (A_OK != status) {
+ return -EIO;
+ }
+ return 0;
+}
+
+#endif
+
+/*
+ * SIOCSIWENCODEEXT
+ */
+static int
+ar6000_ioctl_siwencodeext(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ A_INT32 index;
+ struct iw_encode_ext *ext;
+ KEY_USAGE keyUsage;
+ A_INT32 keyLen;
+ A_UINT8 *keyData;
+ A_UINT8 keyRsc[8];
+ A_STATUS status;
+ CRYPTO_TYPE keyType;
+#ifdef USER_KEYS
+ struct ieee80211req_key ik;
+#endif /* USER_KEYS */
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+#ifdef USER_KEYS
+ ar->user_saved_keys.keyOk = FALSE;
+#endif /* USER_KEYS */
+
+ index = erq->flags & IW_ENCODE_INDEX;
+
+ if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+ ((index - 1) > WMI_MAX_KEY_INDEX)))
+ {
+ return -EIO;
+ }
+
+ ext = (struct iw_encode_ext *)extra;
+ if (erq->flags & IW_ENCODE_DISABLED) {
+ /*
+ * Encryption disabled
+ */
+ if (index) {
+ /*
+ * If key index was specified then clear the specified key
+ */
+ index--;
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ ar->arWepKeyList[index].arKeyLen = 0;
+ }
+ } else {
+ /*
+ * Enabling WEP encryption
+ */
+ if (index) {
+ index--; /* keyindex is off base 1 in iwconfig */
+ }
+
+ keyUsage = 0;
+ keyLen = erq->length - sizeof(struct iw_encode_ext);
+
+ if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
+ keyUsage = TX_USAGE;
+ ar->arDefTxKeyIndex = index;
+ // Just setting the key index
+ if (keyLen == 0) {
+ return 0;
+ }
+ }
+
+ if (keyLen <= 0) {
+ return -EIO;
+ }
+
+ /* key follows iw_encode_ext */
+ keyData = (A_UINT8 *)(ext + 1);
+
+ switch (ext->alg) {
+ case IW_ENCODE_ALG_WEP:
+ keyType = WEP_CRYPT;
+#ifdef USER_KEYS
+ ik.ik_type = IEEE80211_CIPHER_WEP;
+#endif /* USER_KEYS */
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) {
+ return -EIO;
+ }
+
+ /* Check whether it is static wep. */
+ if (!ar->arConnected) {
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen);
+ ar->arWepKeyList[index].arKeyLen = keyLen;
+
+ return 0;
+ }
+ break;
+ case IW_ENCODE_ALG_TKIP:
+ keyType = TKIP_CRYPT;
+#ifdef USER_KEYS
+ ik.ik_type = IEEE80211_CIPHER_TKIP;
+#endif /* USER_KEYS */
+ break;
+ case IW_ENCODE_ALG_CCMP:
+ keyType = AES_CRYPT;
+#ifdef USER_KEYS
+ ik.ik_type = IEEE80211_CIPHER_AES_CCM;
+#endif /* USER_KEYS */
+ break;
+#ifdef WAPI_ENABLE
+ case IW_ENCODE_ALG_SM4:
+ if (ar->arWapiEnable) {
+ return ar6000_set_wapi_key(dev, info, erq, extra);
+ } else {
+ return -EIO;
+ }
+#endif
+ case IW_ENCODE_ALG_PMK:
+ ar->arConnectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD;
+ return wmi_set_pmk_cmd(ar->arWmi, keyData);
+ default:
+ return -EIO;
+ }
+
+
+ if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+ keyUsage |= GROUP_USAGE;
+ } else {
+ keyUsage |= PAIRWISE_USAGE;
+ }
+
+ if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
+ A_MEMCPY(keyRsc, ext->rx_seq, sizeof(keyRsc));
+ } else {
+ A_MEMZERO(keyRsc, sizeof(keyRsc));
+ }
+
+ if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
+ (GROUP_USAGE & keyUsage))
+ {
+ A_UNTIMEOUT(&ar->disconnect_timer);
+ }
+
+ status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage,
+ keyLen, keyRsc,
+ keyData, KEY_OP_INIT_VAL,
+ (A_UINT8*)ext->addr.sa_data,
+ SYNC_BOTH_WMIFLAG);
+ if (status != A_OK) {
+ return -EIO;
+ }
+
+#ifdef USER_KEYS
+ ik.ik_keyix = index;
+ ik.ik_keylen = keyLen;
+ memcpy(ik.ik_keydata, keyData, keyLen);
+ memcpy(&ik.ik_keyrsc, keyRsc, sizeof(keyRsc));
+ memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
+ if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+ memcpy(&ar->user_saved_keys.bcast_ik, &ik,
+ sizeof(struct ieee80211req_key));
+ } else {
+ memcpy(&ar->user_saved_keys.ucast_ik, &ik,
+ sizeof(struct ieee80211req_key));
+ }
+ ar->user_saved_keys.keyOk = TRUE;
+#endif /* USER_KEYS */
+ }
+
+
+ return 0;
+}
+
+/*
+ * SIOCGIWENCODEEXT
+ */
+static int
+ar6000_ioctl_giwencodeext(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arPairwiseCrypto == NONE_CRYPT) {
+ erq->length = 0;
+ erq->flags = IW_ENCODE_DISABLED;
+ } else {
+ erq->length = 0;
+ }
+
+ return 0;
+}
+#endif // WIRELESS_EXT >= 18
+
+#if WIRELESS_EXT > 20
+static int ar6000_ioctl_siwpower(struct net_device *dev,
+ struct iw_request_info *info,
+ union iwreq_data *wrqu, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_POWER_MODE power_mode;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (wrqu->power.disabled)
+ power_mode = MAX_PERF_POWER;
+ else
+ power_mode = REC_POWER;
+
+ if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
+ return -EIO;
+ return 0;
+}
+
+static int ar6000_ioctl_giwpower(struct net_device *dev,
+ struct iw_request_info *info,
+ union iwreq_data *wrqu, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ WMI_POWER_MODE power_mode;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ power_mode = wmi_get_power_mode_cmd(ar->arWmi);
+
+ if (power_mode == MAX_PERF_POWER)
+ wrqu->power.disabled = 1;
+ else
+ wrqu->power.disabled = 0;
+
+ return 0;
+}
+#endif // WIRELESS_EXT > 20
+
+/*
+ * SIOCGIWNAME
+ */
+int
+ar6000_ioctl_giwname(struct net_device *dev,
+ struct iw_request_info *info,
+ char *name, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ switch (ar->arPhyCapability) {
+ case (WMI_11A_CAPABILITY):
+ strncpy(name, "AR6000 802.11a", IFNAMSIZ);
+ break;
+ case (WMI_11G_CAPABILITY):
+ strncpy(name, "AR6000 802.11g", IFNAMSIZ);
+ break;
+ case (WMI_11AG_CAPABILITY):
+ strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
+ break;
+ case (WMI_11NA_CAPABILITY):
+ strncpy(name, "AR6000 802.11na", IFNAMSIZ);
+ break;
+ case (WMI_11NG_CAPABILITY):
+ strncpy(name, "AR6000 802.11ng", IFNAMSIZ);
+ break;
+ case (WMI_11NAG_CAPABILITY):
+ strncpy(name, "AR6000 802.11nag", IFNAMSIZ);
+ break;
+ default:
+ strncpy(name, "AR6000 802.11", IFNAMSIZ);
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCSIWFREQ
+ */
+int
+ar6000_ioctl_siwfreq(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_freq *freq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ /*
+ * We support limiting the channels via wmiconfig.
+ *
+ * We use this command to configure the channel hint for the connect cmd
+ * so it is possible the target will end up connecting to a different
+ * channel.
+ */
+ if (freq->e > 1) {
+ return -EINVAL;
+ } else if (freq->e == 1) {
+ ar->arChannelHint = freq->m / 100000;
+ } else {
+ if(freq->m) {
+ ar->arChannelHint = wlan_ieee2freq(freq->m);
+ } else {
+ /* Auto Channel Selection */
+ ar->arChannelHint = 0;
+ }
+ }
+
+ ar->ap_profile_flag = 1; /* There is a change in profile */
+
+ A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
+ return 0;
+}
+
+/*
+ * SIOCGIWFREQ
+ */
+int
+ar6000_ioctl_giwfreq(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_freq *freq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arNetworkType == AP_NETWORK) {
+ if(ar->arChannelHint) {
+ freq->m = ar->arChannelHint * 100000;
+ } else if(ar->arACS) {
+ freq->m = ar->arACS * 100000;
+ } else {
+ return -EINVAL;
+ }
+ } else {
+ if (ar->arConnected != TRUE) {
+ return -EINVAL;
+ } else {
+ freq->m = ar->arBssChannel * 100000;
+ }
+ }
+
+ freq->e = 1;
+
+ return 0;
+}
+
+/*
+ * SIOCSIWMODE
+ */
+int
+ar6000_ioctl_siwmode(struct net_device *dev,
+ struct iw_request_info *info,
+ __u32 *mode, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ /*
+ * clear SSID during mode switch in connected state
+ */
+ if(!(ar->arNetworkType == (((*mode) == IW_MODE_INFRA) ? INFRA_NETWORK : ADHOC_NETWORK)) && (ar->arConnected == TRUE) ){
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+
+ switch (*mode) {
+ case IW_MODE_INFRA:
+ ar->arNextMode = INFRA_NETWORK;
+ break;
+ case IW_MODE_ADHOC:
+ ar->arNextMode = ADHOC_NETWORK;
+ break;
+ case IW_MODE_MASTER:
+ ar->arNextMode = AP_NETWORK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* clear all shared parameters between AP and STA|IBSS modes when we
+ * switch between them. Switch between STA & IBSS modes does'nt clear
+ * the shared profile. This is as per the original design for switching
+ * between STA & IBSS.
+ */
+ if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) {
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arAuthMode = NONE_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ ar->arChannelHint = 0;
+ ar->arBssChannel = 0;
+ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+
+ /* SSID has to be cleared to trigger a profile change while switching
+ * between STA & IBSS modes having the same SSID
+ */
+ if (ar->arNetworkType != ar->arNextMode) {
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCGIWMODE
+ */
+int
+ar6000_ioctl_giwmode(struct net_device *dev,
+ struct iw_request_info *info,
+ __u32 *mode, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ switch (ar->arNetworkType) {
+ case INFRA_NETWORK:
+ *mode = IW_MODE_INFRA;
+ break;
+ case ADHOC_NETWORK:
+ *mode = IW_MODE_ADHOC;
+ break;
+ case AP_NETWORK:
+ *mode = IW_MODE_MASTER;
+ break;
+ default:
+ return -EIO;
+ }
+ return 0;
+}
+
+/*
+ * SIOCSIWSENS
+ */
+int
+ar6000_ioctl_siwsens(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *sens, char *extra)
+{
+ return 0;
+}
+
+/*
+ * SIOCGIWSENS
+ */
+int
+ar6000_ioctl_giwsens(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *sens, char *extra)
+{
+ sens->value = 0;
+ sens->fixed = 1;
+
+ return 0;
+}
+
+/*
+ * SIOCGIWRANGE
+ */
+int
+ar6000_ioctl_giwrange(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ struct iw_range *range = (struct iw_range *) extra;
+ int i, ret = 0;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ up(&ar->arSem);
+ return -EBUSY;
+ }
+
+ ar->arNumChannels = -1;
+ A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
+
+ if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ up(&ar->arSem);
+ return -EINTR;
+ }
+
+ data->length = sizeof(struct iw_range);
+ A_MEMZERO(range, sizeof(struct iw_range));
+
+ range->txpower_capa = 0;
+
+ range->min_pmp = 1 * 1024;
+ range->max_pmp = 65535 * 1024;
+ range->min_pmt = 1 * 1024;
+ range->max_pmt = 1000 * 1024;
+ range->pmp_flags = IW_POWER_PERIOD;
+ range->pmt_flags = IW_POWER_TIMEOUT;
+ range->pm_capa = 0;
+
+ range->we_version_compiled = WIRELESS_EXT;
+ range->we_version_source = 13;
+
+ range->retry_capa = IW_RETRY_LIMIT;
+ range->retry_flags = IW_RETRY_LIMIT;
+ range->min_retry = 0;
+ range->max_retry = 255;
+
+ range->num_frequency = range->num_channels = ar->arNumChannels;
+ for (i = 0; i < ar->arNumChannels; i++) {
+ range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
+ range->freq[i].m = ar->arChannelList[i] * 100000;
+ range->freq[i].e = 1;
+ /*
+ * Linux supports max of 32 channels, bail out once you
+ * reach the max.
+ */
+ if (i == IW_MAX_FREQUENCIES) {
+ break;
+ }
+ }
+
+ /* Max quality is max field value minus noise floor */
+ range->max_qual.qual = 0xff - 161;
+
+ /*
+ * In order to use dBm measurements, 'level' must be lower
+ * than any possible measurement (see iw_print_stats() in
+ * wireless tools). It's unclear how this is meant to be
+ * done, but setting zero in these values forces dBm and
+ * the actual numbers are not used.
+ */
+ range->max_qual.level = 0;
+ range->max_qual.noise = 0;
+
+ range->sensitivity = 3;
+
+ range->max_encoding_tokens = 4;
+ /* XXX query driver to find out supported key sizes */
+ range->num_encoding_sizes = 3;
+ range->encoding_size[0] = 5; /* 40-bit */
+ range->encoding_size[1] = 13; /* 104-bit */
+ range->encoding_size[2] = 16; /* 128-bit */
+
+ range->num_bitrates = 0;
+
+ /* estimated maximum TCP throughput values (bps) */
+ range->throughput = 22000000;
+
+ range->min_rts = 0;
+ range->max_rts = 2347;
+ range->min_frag = 256;
+ range->max_frag = 2346;
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+
+/*
+ * SIOCSIWAP
+ * This ioctl is used to set the desired bssid for the connect command.
+ */
+int
+ar6000_ioctl_siwap(struct net_device *dev,
+ struct iw_request_info *info,
+ struct sockaddr *ap_addr, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ap_addr->sa_family != ARPHRD_ETHER) {
+ return -EIO;
+ }
+
+ if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ } else {
+ A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid));
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCGIWAP
+ */
+int
+ar6000_ioctl_giwap(struct net_device *dev,
+ struct iw_request_info *info,
+ struct sockaddr *ap_addr, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arNetworkType == AP_NETWORK) {
+ A_MEMCPY(&ap_addr->sa_data, dev->dev_addr, ATH_MAC_LEN);
+ ap_addr->sa_family = ARPHRD_ETHER;
+ return 0;
+ }
+
+ if (ar->arConnected != TRUE) {
+ return -EINVAL;
+ }
+
+ A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
+ ap_addr->sa_family = ARPHRD_ETHER;
+
+ return 0;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+/*
+ * SIOCSIWMLME
+ */
+int
+ar6000_ioctl_siwmlme(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->bIsDestroyProgress) {
+ return -EBUSY;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (data->pointer && data->length == sizeof(struct iw_mlme)) {
+
+ A_UINT8 arNetworkType;
+ struct iw_mlme mlme;
+
+ if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme)))
+ return -EIO;
+
+ switch (mlme.cmd) {
+
+ case IW_MLME_DEAUTH:
+ /* fall through */
+ case IW_MLME_DISASSOC:
+ if ((ar->arConnected != TRUE) ||
+ (memcmp(ar->arBssid, mlme.addr.sa_data, 6) != 0)) {
+
+ up(&ar->arSem);
+ return -EINVAL;
+ }
+ wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
+ arNetworkType = ar->arNetworkType;
+ ar6000_init_profile_info(ar);
+ ar->arNetworkType = arNetworkType;
+ reconnect_flag = 0;
+ wmi_disconnect_cmd(ar->arWmi);
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ if (ar->arSkipScan == FALSE) {
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ }
+ break;
+
+ case IW_MLME_AUTH:
+ /* fall through */
+ case IW_MLME_ASSOC:
+ /* fall through */
+ default:
+ up(&ar->arSem);
+ return -EOPNOTSUPP;
+ }
+ }
+
+ up(&ar->arSem);
+ return 0;
+}
+#endif /* LINUX_VERSION_CODE */
+
+/*
+ * SIOCGIWAPLIST
+ */
+int
+ar6000_ioctl_iwaplist(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ return -EIO; /* for now */
+}
+
+/*
+ * SIOCSIWSCAN
+ */
+int
+ar6000_ioctl_siwscan(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+#define ACT_DWELLTIME_DEFAULT 105
+#define HOME_TXDRAIN_TIME 100
+#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+ int ret = 0;
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (!ar->arUserBssFilter) {
+ if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+ return -EIO;
+ }
+ }
+
+ if (ar->arConnected) {
+ if (wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+ return -EIO;
+ }
+ }
+
+#ifdef ANDROID_ENV
+#if WIRELESS_EXT >= 18
+ if (data->pointer && (data->length == sizeof(struct iw_scan_req)))
+ {
+ if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID)
+ {
+ struct iw_scan_req req;
+ if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req)))
+ return -EIO;
+ if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK)
+ return -EIO;
+ }
+ else
+ {
+ if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK)
+ return -EIO;
+ }
+ }
+ else
+ {
+ if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK)
+ return -EIO;
+ }
+#endif
+#endif /* ANDROID_ENV */
+
+ if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \
+ 0, 0, 0, NULL) != A_OK) {
+ ret = -EIO;
+ }
+
+ if (ret == 0) {
+ ar->scan_complete = 0;
+ }
+
+ return ret;
+#undef ACT_DWELLTIME_DEFAULT
+#undef HOME_TXDRAIN_TIME
+#undef SCAN_INT
+}
+
+
+/*
+ * Units are in db above the noise floor. That means the
+ * rssi values reported in the tx/rx descriptors in the
+ * driver are the SNR expressed in db.
+ *
+ * If you assume that the noise floor is -95, which is an
+ * excellent assumption 99.5 % of the time, then you can
+ * derive the absolute signal level (i.e. -95 + rssi).
+ * There are some other slight factors to take into account
+ * depending on whether the rssi measurement is from 11b,
+ * 11g, or 11a. These differences are at most 2db and
+ * can be documented.
+ *
+ * NB: various calculations are based on the orinoco/wavelan
+ * drivers for compatibility
+ */
+static void
+ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
+{
+ if (rssi < 0) {
+ iq->qual = 0;
+ } else {
+ iq->qual = rssi;
+ }
+
+ /* NB: max is 94 because noise is hardcoded to 161 */
+ if (iq->qual > 94)
+ iq->qual = 94;
+
+ iq->noise = 161; /* -95dBm */
+ iq->level = iq->noise + iq->qual;
+ iq->updated = 7;
+}
+
+
+int
+ar6000_ioctl_siwcommit(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev);
+
+ if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) {
+ A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
+ return -EOPNOTSUPP;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AP: SSID %s freq %d authmode %d dot11 auth %d"\
+ " PW crypto %d GRP crypto %d\n",
+ ar->arSsid, ar->arChannelHint,
+ ar->arAuthMode, ar->arDot11AuthMode,
+ ar->arPairwiseCrypto, ar->arGroupCrypto));
+
+ ar6000_ap_mode_profile_commit(ar);
+
+ /* if there is a profile switch from STA|IBSS mode to AP mode,
+ * update the host driver association state for the STA|IBSS mode.
+ */
+ if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) {
+ ar->arConnectPending = FALSE;
+ ar->arConnected = FALSE;
+ /* Stop getting pkts from upper stack */
+ netif_stop_queue(ar->arNetDev);
+ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+ ar->arBssChannel = 0;
+ ar->arBeaconInterval = 0;
+
+ /* Flush the Tx queues */
+ ar6000_TxDataCleanup(ar);
+
+ /* Start getting pkts from upper stack */
+ netif_wake_queue(ar->arNetDev);
+ }
+
+ return 0;
+}
+
+/* Structures to export the Wireless Handlers */
+static const iw_handler ath_handlers[] = {
+ (iw_handler) ar6000_ioctl_siwcommit, /* SIOCSIWCOMMIT */
+ (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */
+ (iw_handler) NULL, /* SIOCSIWNWID */
+ (iw_handler) NULL, /* SIOCGIWNWID */
+ (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */
+ (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */
+ (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */
+ (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */
+ (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */
+ (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */
+ (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */
+ (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */
+ (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */
+ (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */
+ (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */
+ (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */
+ (iw_handler) NULL, /* SIOCSIWSPY */
+ (iw_handler) NULL, /* SIOCGIWSPY */
+ (iw_handler) NULL, /* SIOCSIWTHRSPY */
+ (iw_handler) NULL, /* SIOCGIWTHRSPY */
+ (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */
+ (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13)
+ (iw_handler) ar6000_ioctl_siwmlme, /* SIOCSIWMLME */
+#else
+ (iw_handler) NULL, /* -- hole -- */
+#endif /* LINUX_VERSION_CODE */
+ (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */
+ (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */
+ (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */
+ (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */
+ (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */
+ (iw_handler) NULL, /* SIOCSIWNICKN */
+ (iw_handler) NULL, /* SIOCGIWNICKN */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */
+ (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */
+ (iw_handler) NULL, /* SIOCSIWRTS */
+ (iw_handler) NULL, /* SIOCGIWRTS */
+ (iw_handler) NULL, /* SIOCSIWFRAG */
+ (iw_handler) NULL, /* SIOCGIWFRAG */
+ (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */
+ (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */
+ (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */
+ (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */
+ (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */
+ (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */
+#if WIRELESS_EXT > 20
+ (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */
+ (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */
+#endif // WIRELESS_EXT > 20
+#if WIRELESS_EXT >= 18
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */
+ (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */
+ (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */
+ (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */
+ (iw_handler) ar6000_ioctl_siwencodeext, /* SIOCSIWENCODEEXT */
+ (iw_handler) ar6000_ioctl_giwencodeext, /* SIOCGIWENCODEEXT */
+ (iw_handler) ar6000_ioctl_siwpmksa, /* SIOCSIWPMKSA */
+#endif // WIRELESS_EXT >= 18
+};
+
+struct iw_handler_def ath_iw_handler_def = {
+ .standard = (iw_handler *)ath_handlers,
+ .num_standard = ARRAY_SIZE(ath_handlers),
+ .private = NULL,
+ .num_private = 0,
+};
diff --git a/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h b/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h
new file mode 100644
index 000000000000..567a3ff185ca
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h
@@ -0,0 +1,112 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifndef __AGGR_RX_INTERNAL_H__
+#define __AGGR_RX_INTERNAL_H__
+
+#include "a_osapi.h"
+#include "aggr_recv_api.h"
+
+#define AGGR_WIN_IDX(x, y) ((x) % (y))
+#define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x)+1), (y))
+#define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x)-1), (y))
+#define IEEE80211_MAX_SEQ_NO 0xFFF
+#define IEEE80211_NEXT_SEQ_NO(x) (((x) + 1) & IEEE80211_MAX_SEQ_NO)
+
+
+#define NUM_OF_TIDS 8
+#define AGGR_SZ_DEFAULT 8
+
+#define AGGR_WIN_SZ_MIN 2
+#define AGGR_WIN_SZ_MAX 8
+/* TID Window sz is double of what is negotiated. Derive TID_WINDOW_SZ from win_sz, per tid */
+#define TID_WINDOW_SZ(_x) ((_x) << 1)
+
+#define AGGR_NUM_OF_FREE_NETBUFS 16
+
+#define AGGR_GET_RXTID_STATS(_p, _x) (&(_p->stat[(_x)]))
+#define AGGR_GET_RXTID(_p, _x) (&(_p->RxTid[(_x)]))
+
+/* Hold q is a function of win_sz, which is negotiated per tid */
+#define HOLD_Q_SZ(_x) (TID_WINDOW_SZ((_x))*sizeof(OSBUF_HOLD_Q))
+/* AGGR_RX_TIMEOUT value is important as a (too) small value can cause frames to be
+ * delivered out of order and a (too) large value can cause undesirable latency in
+ * certain situations. */
+#define AGGR_RX_TIMEOUT 400 /* Timeout(in ms) for delivery of frames, if they are stuck */
+
+typedef enum {
+ ALL_SEQNO = 0,
+ CONTIGUOUS_SEQNO = 1,
+}DELIVERY_ORDER;
+
+typedef struct {
+ void *osbuf;
+ A_BOOL is_amsdu;
+ A_UINT16 seq_no;
+}OSBUF_HOLD_Q;
+
+
+#if 0
+typedef struct {
+ A_UINT16 seqno_st;
+ A_UINT16 seqno_end;
+}WINDOW_SNAPSHOT;
+#endif
+
+typedef struct {
+ A_BOOL aggr; /* is it ON or OFF */
+ A_BOOL progress; /* TRUE when frames have arrived after a timer start */
+ A_BOOL timerMon; /* TRUE if the timer started for the sake of this TID */
+ A_UINT16 win_sz; /* negotiated window size */
+ A_UINT16 seq_next; /* Next seq no, in current window */
+ A_UINT32 hold_q_sz; /* Num of frames that can be held in hold q */
+ OSBUF_HOLD_Q *hold_q; /* Hold q for re-order */
+#if 0
+ WINDOW_SNAPSHOT old_win; /* Sliding window snapshot - for timeout */
+#endif
+ A_NETBUF_QUEUE_T q; /* q head for enqueuing frames for dispatch */
+ A_MUTEX_T lock;
+}RXTID;
+
+typedef struct {
+ A_UINT32 num_into_aggr; /* hitting at the input of this module */
+ A_UINT32 num_dups; /* duplicate */
+ A_UINT32 num_oow; /* out of window */
+ A_UINT32 num_mpdu; /* single payload 802.3/802.11 frame */
+ A_UINT32 num_amsdu; /* AMSDU */
+ A_UINT32 num_delivered; /* frames delivered to IP stack */
+ A_UINT32 num_timeouts; /* num of timeouts, during which frames delivered */
+ A_UINT32 num_hole; /* frame not present, when window moved over */
+ A_UINT32 num_bar; /* num of resets of seq_num, via BAR */
+}RXTID_STATS;
+
+typedef struct {
+ A_UINT8 aggr_sz; /* config value of aggregation size */
+ A_UINT8 timerScheduled;
+ A_TIMER timer; /* timer for returning held up pkts in re-order que */
+ void *dev; /* dev handle */
+ RX_CALLBACK rx_fn; /* callback function to return frames; to upper layer */
+ RXTID RxTid[NUM_OF_TIDS]; /* Per tid window */
+ ALLOC_NETBUFS netbuf_allocator; /* OS netbuf alloc fn */
+ A_NETBUF_QUEUE_T freeQ; /* pre-allocated buffers - for A_MSDU slicing */
+ RXTID_STATS stat[NUM_OF_TIDS]; /* Tid based statistics */
+ PACKET_LOG pkt_log; /* Log info of the packets */
+}AGGR_INFO;
+
+#endif /* __AGGR_RX_INTERNAL_H__ */
diff --git a/drivers/net/wireless/ath6kl/reorder/makefile b/drivers/net/wireless/ath6kl/reorder/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/reorder/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c b/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c
new file mode 100644
index 000000000000..3bfba4fbc051
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c
@@ -0,0 +1,662 @@
+/*
+ *
+ * Copyright (c) 2010 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+ *
+ */
+
+#ifdef ATH_AR6K_11N_SUPPORT
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include <a_debug.h>
+#include "pkt_log.h"
+#include "aggr_recv_api.h"
+#include "aggr_rx_internal.h"
+#include "wmi.h"
+
+extern A_STATUS
+wmi_dot3_2_dix(void *osbuf);
+
+static void
+aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf);
+
+static void
+aggr_timeout(A_ATH_TIMER arg);
+
+static void
+aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order);
+
+static void
+aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q);
+
+static void *
+aggr_get_osbuf(AGGR_INFO *p_aggr);
+
+void *
+aggr_init(ALLOC_NETBUFS netbuf_allocator)
+{
+ AGGR_INFO *p_aggr = NULL;
+ RXTID *rxtid;
+ A_UINT8 i;
+ A_STATUS status = A_OK;
+
+ A_PRINTF("In aggr_init..\n");
+
+ do {
+ p_aggr = A_MALLOC(sizeof(AGGR_INFO));
+ if(!p_aggr) {
+ A_PRINTF("Failed to allocate memory for aggr_node\n");
+ status = A_ERROR;
+ break;
+ }
+
+ /* Init timer and data structures */
+ A_MEMZERO(p_aggr, sizeof(AGGR_INFO));
+ p_aggr->aggr_sz = AGGR_SZ_DEFAULT;
+ A_INIT_TIMER(&p_aggr->timer, aggr_timeout, p_aggr);
+ p_aggr->timerScheduled = FALSE;
+ A_NETBUF_QUEUE_INIT(&p_aggr->freeQ);
+
+ p_aggr->netbuf_allocator = netbuf_allocator;
+ p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS);
+
+ for(i = 0; i < NUM_OF_TIDS; i++) {
+ rxtid = AGGR_GET_RXTID(p_aggr, i);
+ rxtid->aggr = FALSE;
+ rxtid->progress = FALSE;
+ rxtid->timerMon = FALSE;
+ A_NETBUF_QUEUE_INIT(&rxtid->q);
+ A_MUTEX_INIT(&rxtid->lock);
+ }
+ }while(FALSE);
+
+ A_PRINTF("going out of aggr_init..status %s\n",
+ (status == A_OK) ? "OK":"Error");
+
+ if(status != A_OK) {
+ /* Cleanup */
+ aggr_module_destroy(p_aggr);
+ }
+ return ((status == A_OK) ? p_aggr : NULL);
+}
+
+/* utility function to clear rx hold_q for a tid */
+static void
+aggr_delete_tid_state(AGGR_INFO *p_aggr, A_UINT8 tid)
+{
+ RXTID *rxtid;
+ RXTID_STATS *stats;
+
+ A_ASSERT(tid < NUM_OF_TIDS && p_aggr);
+
+ rxtid = AGGR_GET_RXTID(p_aggr, tid);
+ stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+ if(rxtid->aggr) {
+ aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO);
+ }
+
+ rxtid->aggr = FALSE;
+ rxtid->progress = FALSE;
+ rxtid->timerMon = FALSE;
+ rxtid->win_sz = 0;
+ rxtid->seq_next = 0;
+ rxtid->hold_q_sz = 0;
+
+ if(rxtid->hold_q) {
+ A_FREE(rxtid->hold_q);
+ rxtid->hold_q = NULL;
+ }
+
+ A_MEMZERO(stats, sizeof(RXTID_STATS));
+}
+
+void
+aggr_module_destroy(void *cntxt)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+ RXTID *rxtid;
+ A_UINT8 i, k;
+ A_PRINTF("%s(): aggr = %p\n",_A_FUNCNAME_, p_aggr);
+ A_ASSERT(p_aggr);
+
+ if(p_aggr) {
+ if(p_aggr->timerScheduled) {
+ A_UNTIMEOUT(&p_aggr->timer);
+ p_aggr->timerScheduled = FALSE;
+ }
+
+ for(i = 0; i < NUM_OF_TIDS; i++) {
+ rxtid = AGGR_GET_RXTID(p_aggr, i);
+ /* Free the hold q contents and hold_q*/
+ if(rxtid->hold_q) {
+ for(k = 0; k< rxtid->hold_q_sz; k++) {
+ if(rxtid->hold_q[k].osbuf) {
+ A_NETBUF_FREE(rxtid->hold_q[k].osbuf);
+ }
+ }
+ A_FREE(rxtid->hold_q);
+ }
+ /* Free the dispatch q contents*/
+ while(A_NETBUF_QUEUE_SIZE(&rxtid->q)) {
+ A_NETBUF_FREE(A_NETBUF_DEQUEUE(&rxtid->q));
+ }
+ if (A_IS_MUTEX_VALID(&rxtid->lock)) {
+ A_MUTEX_DELETE(&rxtid->lock);
+ }
+ }
+ /* free the freeQ and its contents*/
+ while(A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
+ A_NETBUF_FREE(A_NETBUF_DEQUEUE(&p_aggr->freeQ));
+ }
+ A_FREE(p_aggr);
+ }
+ A_PRINTF("out aggr_module_destroy\n");
+}
+
+
+void
+aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+
+ A_ASSERT(p_aggr && fn && dev);
+
+ p_aggr->rx_fn = fn;
+ p_aggr->dev = dev;
+}
+
+
+void
+aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+ RXTID_STATS *stats;
+
+ A_ASSERT(p_aggr);
+ stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+ stats->num_bar++;
+
+ aggr_deque_frms(p_aggr, tid, seq_no, ALL_SEQNO);
+}
+
+
+void
+aggr_recv_addba_req_evt(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+ RXTID *rxtid;
+ RXTID_STATS *stats;
+
+ A_ASSERT(p_aggr);
+ rxtid = AGGR_GET_RXTID(p_aggr, tid);
+ stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+ A_PRINTF("%s(): win_sz = %d aggr %d\n", _A_FUNCNAME_, win_sz, rxtid->aggr);
+ if(win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) {
+ A_PRINTF("win_sz %d, tid %d\n", win_sz, tid);
+ }
+
+ if(rxtid->aggr) {
+ /* Just go and deliver all the frames up from this
+ * queue, as if we got DELBA and re-initialize the queue
+ */
+ aggr_delete_tid_state(p_aggr, tid);
+ }
+
+ rxtid->seq_next = seq_no;
+ /* create these queues, only upon receiving of ADDBA for a
+ * tid, reducing memory requirement
+ */
+ rxtid->hold_q = A_MALLOC(HOLD_Q_SZ(win_sz));
+ if((rxtid->hold_q == NULL)) {
+ A_PRINTF("Failed to allocate memory, tid = %d\n", tid);
+ A_ASSERT(0);
+ }
+ A_MEMZERO(rxtid->hold_q, HOLD_Q_SZ(win_sz));
+
+ /* Update rxtid for the window sz */
+ rxtid->win_sz = win_sz;
+ /* hold_q_sz inicates the depth of holding q - which is
+ * a factor of win_sz. Compute once, as it will be used often
+ */
+ rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz);
+ /* There should be no frames on q - even when second ADDBA comes in.
+ * If aggr was previously ON on this tid, we would have cleaned up
+ * the q
+ */
+ if(A_NETBUF_QUEUE_SIZE(&rxtid->q) != 0) {
+ A_PRINTF("ERROR: Frames still on queue ?\n");
+ A_ASSERT(0);
+ }
+
+ rxtid->aggr = TRUE;
+}
+
+void
+aggr_recv_delba_req_evt(void *cntxt, A_UINT8 tid)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+ RXTID *rxtid;
+
+ A_ASSERT(p_aggr);
+ A_PRINTF("%s(): tid %d\n", _A_FUNCNAME_, tid);
+
+ rxtid = AGGR_GET_RXTID(p_aggr, tid);
+
+ if(rxtid->aggr) {
+ aggr_delete_tid_state(p_aggr, tid);
+ }
+}
+
+static void
+aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order)
+{
+ RXTID *rxtid;
+ OSBUF_HOLD_Q *node;
+ A_UINT16 idx, idx_end, seq_end;
+ RXTID_STATS *stats;
+
+ A_ASSERT(p_aggr);
+ rxtid = AGGR_GET_RXTID(p_aggr, tid);
+ stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+ /* idx is absolute location for first frame */
+ idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
+
+ /* idx_end is typically the last possible frame in the window,
+ * but changes to 'the' seq_no, when BAR comes. If seq_no
+ * is non-zero, we will go up to that and stop.
+ * Note: last seq no in current window will occupy the same
+ * index position as index that is just previous to start.
+ * An imp point : if win_sz is 7, for seq_no space of 4095,
+ * then, there would be holes when sequence wrap around occurs.
+ * Target should judiciously choose the win_sz, based on
+ * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz
+ * 2, 4, 8, 16 win_sz works fine).
+ * We must deque from "idx" to "idx_end", including both.
+ */
+ seq_end = (seq_no) ? seq_no : rxtid->seq_next;
+ idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz);
+
+ /* Critical section begins */
+ A_MUTEX_LOCK(&rxtid->lock);
+ do {
+
+ node = &rxtid->hold_q[idx];
+
+ if((order == CONTIGUOUS_SEQNO) && (!node->osbuf))
+ break;
+
+ /* chain frames and deliver frames bcos:
+ * 1. either the frames are in order and window is contiguous, OR
+ * 2. we need to deque frames, irrespective of holes
+ */
+ if(node->osbuf) {
+ if(node->is_amsdu) {
+ aggr_slice_amsdu(p_aggr, rxtid, &node->osbuf);
+ } else {
+ A_NETBUF_ENQUEUE(&rxtid->q, node->osbuf);
+ }
+ node->osbuf = NULL;
+ } else {
+ stats->num_hole++;
+ }
+
+ /* window is moving */
+ rxtid->seq_next = IEEE80211_NEXT_SEQ_NO(rxtid->seq_next);
+ idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
+ } while(idx != idx_end);
+ /* Critical section ends */
+ A_MUTEX_UNLOCK(&rxtid->lock);
+
+ stats->num_delivered += A_NETBUF_QUEUE_SIZE(&rxtid->q);
+ aggr_dispatch_frames(p_aggr, &rxtid->q);
+}
+
+static void *
+aggr_get_osbuf(AGGR_INFO *p_aggr)
+{
+ void *buf = NULL;
+
+ /* Starving for buffers? get more from OS
+ * check for low netbuffers( < 1/4 AGGR_NUM_OF_FREE_NETBUFS) :
+ * re-allocate bufs if so
+ * allocate a free buf from freeQ
+ */
+ if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) {
+ p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS);
+ }
+
+ if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
+ buf = A_NETBUF_DEQUEUE(&p_aggr->freeQ);
+ }
+
+ return buf;
+}
+
+
+static void
+aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf)
+{
+ void *new_buf;
+ A_UINT16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len;
+ A_UINT8 *framep;
+
+ /* Frame format at this point:
+ * [DIX hdr | 802.3 | 802.3 | ... | 802.3]
+ *
+ * Strip the DIX header.
+ * Iterate through the osbuf and do:
+ * grab a free netbuf from freeQ
+ * find the start and end of a frame
+ * copy it to netbuf(Vista can do better here)
+ * convert all msdu's(802.3) frames to upper layer format - os routine
+ * -for now lets convert from 802.3 to dix
+ * enque this to dispatch q of tid
+ * repeat
+ * free the osbuf - to OS. It's been sliced.
+ */
+
+ mac_hdr_len = sizeof(ATH_MAC_HDR);
+ framep = A_NETBUF_DATA(*osbuf) + mac_hdr_len;
+ amsdu_len = A_NETBUF_LEN(*osbuf) - mac_hdr_len;
+
+ while(amsdu_len > mac_hdr_len) {
+ /* Begin of a 802.3 frame */
+ payload_8023_len = A_BE2CPU16(((ATH_MAC_HDR *)framep)->typeOrLen);
+#define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508
+#define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46
+ if(payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) {
+ A_PRINTF("802.3 AMSDU frame bound check failed. len %d\n", payload_8023_len);
+ break;
+ }
+ frame_8023_len = payload_8023_len + mac_hdr_len;
+ new_buf = aggr_get_osbuf(p_aggr);
+ if(new_buf == NULL) {
+ A_PRINTF("No buffer available \n");
+ break;
+ }
+
+ A_MEMCPY(A_NETBUF_DATA(new_buf), framep, frame_8023_len);
+ A_NETBUF_PUT(new_buf, frame_8023_len);
+ if (wmi_dot3_2_dix(new_buf) != A_OK) {
+ A_PRINTF("dot3_2_dix err..\n");
+ A_NETBUF_FREE(new_buf);
+ break;
+ }
+
+ A_NETBUF_ENQUEUE(&rxtid->q, new_buf);
+
+ /* Is this the last subframe within this aggregate ? */
+ if ((amsdu_len - frame_8023_len) == 0) {
+ break;
+ }
+
+ /* Add the length of A-MSDU subframe padding bytes -
+ * Round to nearest word.
+ */
+ frame_8023_len = ((frame_8023_len + 3) & ~3);
+
+ framep += frame_8023_len;
+ amsdu_len -= frame_8023_len;
+ }
+
+ A_NETBUF_FREE(*osbuf);
+ *osbuf = NULL;
+}
+
+void
+aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+ RXTID *rxtid;
+ RXTID_STATS *stats;
+ A_UINT16 idx, st, cur, end;
+ A_UINT16 *log_idx;
+ OSBUF_HOLD_Q *node;
+ PACKET_LOG *log;
+
+ A_ASSERT(p_aggr);
+ A_ASSERT(tid < NUM_OF_TIDS);
+
+ rxtid = AGGR_GET_RXTID(p_aggr, tid);
+ stats = AGGR_GET_RXTID_STATS(p_aggr, tid);
+
+ stats->num_into_aggr++;
+
+ if(!rxtid->aggr) {
+ if(is_amsdu) {
+ aggr_slice_amsdu(p_aggr, rxtid, osbuf);
+ stats->num_amsdu++;
+ aggr_dispatch_frames(p_aggr, &rxtid->q);
+ }
+ return;
+ }
+
+ /* Check the incoming sequence no, if it's in the window */
+ st = rxtid->seq_next;
+ cur = seq_no;
+ end = (st + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO;
+ /* Log the pkt info for future analysis */
+ log = &p_aggr->pkt_log;
+ log_idx = &log->last_idx;
+ log->info[*log_idx].cur = cur;
+ log->info[*log_idx].st = st;
+ log->info[*log_idx].end = end;
+ *log_idx = IEEE80211_NEXT_SEQ_NO(*log_idx);
+
+ if(((st < end) && (cur < st || cur > end)) ||
+ ((st > end) && (cur > end) && (cur < st))) {
+ /* the cur frame is outside the window. Since we know
+ * our target would not do this without reason it must
+ * be assumed that the window has moved for some valid reason.
+ * Therefore, we dequeue all frames and start fresh.
+ */
+ A_UINT16 extended_end;
+
+ extended_end = (end + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO;
+
+ if(((end < extended_end) && (cur < end || cur > extended_end)) ||
+ ((end > extended_end) && (cur > extended_end) && (cur < end))) {
+ // dequeue all frames in queue and shift window to new frame
+ aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO);
+ //set window start so that new frame is last frame in window
+ if(cur >= rxtid->hold_q_sz-1) {
+ rxtid->seq_next = cur - (rxtid->hold_q_sz-1);
+ }else{
+ rxtid->seq_next = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur);
+ }
+ } else {
+ // dequeue only those frames that are outside the new shifted window
+ if(cur >= rxtid->hold_q_sz-1) {
+ st = cur - (rxtid->hold_q_sz-1);
+ }else{
+ st = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur);
+ }
+
+ aggr_deque_frms(p_aggr, tid, st, ALL_SEQNO);
+ }
+
+ stats->num_oow++;
+ }
+
+ idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz);
+
+ /*enque the frame, in hold_q */
+ node = &rxtid->hold_q[idx];
+
+ A_MUTEX_LOCK(&rxtid->lock);
+ if(node->osbuf) {
+ /* Is the cur frame duplicate or something beyond our
+ * window(hold_q -> which is 2x, already)?
+ * 1. Duplicate is easy - drop incoming frame.
+ * 2. Not falling in current sliding window.
+ * 2a. is the frame_seq_no preceding current tid_seq_no?
+ * -> drop the frame. perhaps sender did not get our ACK.
+ * this is taken care of above.
+ * 2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ);
+ * -> Taken care of it above, by moving window forward.
+ *
+ */
+ A_NETBUF_FREE(node->osbuf);
+ stats->num_dups++;
+ }
+
+ node->osbuf = *osbuf;
+ node->is_amsdu = is_amsdu;
+ node->seq_no = seq_no;
+ if(node->is_amsdu) {
+ stats->num_amsdu++;
+ } else {
+ stats->num_mpdu++;
+ }
+ A_MUTEX_UNLOCK(&rxtid->lock);
+
+ *osbuf = NULL;
+ aggr_deque_frms(p_aggr, tid, 0, CONTIGUOUS_SEQNO);
+
+ if(p_aggr->timerScheduled) {
+ rxtid->progress = TRUE;
+ }else{
+ for(idx=0 ; idx<rxtid->hold_q_sz ; idx++) {
+ if(rxtid->hold_q[idx].osbuf) {
+ /* there is a frame in the queue and no timer so
+ * start a timer to ensure that the frame doesn't remain
+ * stuck forever. */
+ p_aggr->timerScheduled = TRUE;
+ A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0);
+ rxtid->progress = FALSE;
+ rxtid->timerMon = TRUE;
+ break;
+ }
+ }
+ }
+}
+
+/*
+ * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
+ * hold Q state. Examples include when a Connect event or disconnect event is
+ * received.
+ */
+void
+aggr_reset_state(void *cntxt)
+{
+ A_UINT8 tid;
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+
+ A_ASSERT(p_aggr);
+
+ for(tid=0 ; tid<NUM_OF_TIDS ; tid++) {
+ aggr_delete_tid_state(p_aggr, tid);
+ }
+}
+
+
+static void
+aggr_timeout(A_ATH_TIMER arg)
+{
+ A_UINT8 i,j;
+ AGGR_INFO *p_aggr = (AGGR_INFO *)arg;
+ RXTID *rxtid;
+ RXTID_STATS *stats;
+ /*
+ * If the q for which the timer was originally started has
+ * not progressed then it is necessary to dequeue all the
+ * contained frames so that they are not held forever.
+ */
+ for(i = 0; i < NUM_OF_TIDS; i++) {
+ rxtid = AGGR_GET_RXTID(p_aggr, i);
+ stats = AGGR_GET_RXTID_STATS(p_aggr, i);
+
+ if(rxtid->aggr == FALSE ||
+ rxtid->timerMon == FALSE ||
+ rxtid->progress == TRUE) {
+ continue;
+ }
+ // dequeue all frames in for this tid
+ stats->num_timeouts++;
+ A_PRINTF("TO: st %d end %d\n", rxtid->seq_next, ((rxtid->seq_next + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO));
+ aggr_deque_frms(p_aggr, i, 0, ALL_SEQNO);
+ }
+
+ p_aggr->timerScheduled = FALSE;
+ // determine whether a new timer should be started.
+ for(i = 0; i < NUM_OF_TIDS; i++) {
+ rxtid = AGGR_GET_RXTID(p_aggr, i);
+
+ if(rxtid->aggr == TRUE && rxtid->hold_q) {
+ for(j = 0 ; j < rxtid->hold_q_sz ; j++)
+ {
+ if(rxtid->hold_q[j].osbuf)
+ {
+ p_aggr->timerScheduled = TRUE;
+ rxtid->timerMon = TRUE;
+ rxtid->progress = FALSE;
+ break;
+ }
+ }
+
+ if(j >= rxtid->hold_q_sz) {
+ rxtid->timerMon = FALSE;
+ }
+ }
+ }
+
+ if(p_aggr->timerScheduled) {
+ /* Rearm the timer*/
+ A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0);
+ }
+
+}
+
+static void
+aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q)
+{
+ void *osbuf;
+
+ while((osbuf = A_NETBUF_DEQUEUE(q))) {
+ p_aggr->rx_fn(p_aggr->dev, osbuf);
+ }
+}
+
+void
+aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf)
+{
+ AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt;
+ RXTID *rxtid;
+ RXTID_STATS *stats;
+ A_UINT8 i;
+
+ *log_buf = &p_aggr->pkt_log;
+ A_PRINTF("\n\n================================================\n");
+ A_PRINTF("tid: num_into_aggr, dups, oow, mpdu, amsdu, delivered, timeouts, holes, bar, seq_next\n");
+ for(i = 0; i < NUM_OF_TIDS; i++) {
+ stats = AGGR_GET_RXTID_STATS(p_aggr, i);
+ rxtid = AGGR_GET_RXTID(p_aggr, i);
+ A_PRINTF("%d: %d %d %d %d %d %d %d %d %d : %d\n", i, stats->num_into_aggr, stats->num_dups,
+ stats->num_oow, stats->num_mpdu,
+ stats->num_amsdu, stats->num_delivered, stats->num_timeouts,
+ stats->num_hole, stats->num_bar,
+ rxtid->seq_next);
+ }
+ A_PRINTF("================================================\n\n");
+
+}
+
+#endif /* ATH_AR6K_11N_SUPPORT */
diff --git a/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h b/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h
new file mode 100644
index 000000000000..708b6b044d27
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h
@@ -0,0 +1,397 @@
+//------------------------------------------------------------------------------
+// <copyright file="ieee80211.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _NET80211_IEEE80211_H_
+#define _NET80211_IEEE80211_H_
+
+#include "athstartpack.h"
+
+/*
+ * 802.11 protocol definitions.
+ */
+#define IEEE80211_WEP_KEYLEN 5 /* 40bit */
+#define IEEE80211_WEP_IVLEN 3 /* 24bit */
+#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
+#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
+#define IEEE80211_WEP_NKID 4 /* number of key ids */
+
+/*
+ * 802.11i defines an extended IV for use with non-WEP ciphers.
+ * When the EXTIV bit is set in the key id byte an additional
+ * 4 bytes immediately follow the IV for TKIP. For CCMP the
+ * EXTIV bit is likewise set but the 8 bytes represent the
+ * CCMP header rather than IV+extended-IV.
+ */
+#define IEEE80211_WEP_EXTIV 0x20
+#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */
+#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */
+
+#define IEEE80211_CRC_LEN 4
+
+#ifdef WAPI_ENABLE
+#define IEEE80211_WAPI_EXTIVLEN 10 /* extended IV length */
+#endif /* WAPI ENABLE */
+
+
+#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */
+/* is 802.11 address multicast/broadcast? */
+#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01)
+#define IEEE80211_IS_BROADCAST(_a) (*(_a) == 0xFF)
+#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN)
+#define WEP_TRAILER IEEE80211_WEP_CRCLEN
+#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \
+ IEEE80211_WEP_EXTIVLEN)
+#define CCMP_TRAILER IEEE80211_WEP_MICLEN
+#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \
+ IEEE80211_WEP_EXTIVLEN)
+#define TKIP_TRAILER IEEE80211_WEP_CRCLEN
+#define TKIP_MICLEN IEEE80211_WEP_MICLEN
+
+
+#define IEEE80211_ADDR_EQ(addr1, addr2) \
+ (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
+
+#define IEEE80211_ADDR_COPY(dst,src) A_MEMCPY(dst,src,IEEE80211_ADDR_LEN)
+
+#define IEEE80211_KEYBUF_SIZE 16
+#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */
+
+/*
+ * NB: these values are ordered carefully; there are lots of
+ * of implications in any reordering. In particular beware
+ * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
+ */
+#define IEEE80211_CIPHER_WEP 0
+#define IEEE80211_CIPHER_TKIP 1
+#define IEEE80211_CIPHER_AES_OCB 2
+#define IEEE80211_CIPHER_AES_CCM 3
+#define IEEE80211_CIPHER_CKIP 5
+#define IEEE80211_CIPHER_CCKM_KRK 6
+#define IEEE80211_CIPHER_NONE 7 /* pseudo value */
+
+#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1)
+
+#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
+ (((len) == 5) || ((len) == 13) || ((len) == 16))
+
+
+
+/*
+ * generic definitions for IEEE 802.11 frames
+ */
+PREPACK struct ieee80211_frame {
+ A_UINT8 i_fc[2];
+ A_UINT8 i_dur[2];
+ A_UINT8 i_addr1[IEEE80211_ADDR_LEN];
+ A_UINT8 i_addr2[IEEE80211_ADDR_LEN];
+ A_UINT8 i_addr3[IEEE80211_ADDR_LEN];
+ A_UINT8 i_seq[2];
+ /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
+ /* see below */
+} POSTPACK;
+
+PREPACK struct ieee80211_qosframe {
+ A_UINT8 i_fc[2];
+ A_UINT8 i_dur[2];
+ A_UINT8 i_addr1[IEEE80211_ADDR_LEN];
+ A_UINT8 i_addr2[IEEE80211_ADDR_LEN];
+ A_UINT8 i_addr3[IEEE80211_ADDR_LEN];
+ A_UINT8 i_seq[2];
+ A_UINT8 i_qos[2];
+} POSTPACK;
+
+#define IEEE80211_FC0_VERSION_MASK 0x03
+#define IEEE80211_FC0_VERSION_SHIFT 0
+#define IEEE80211_FC0_VERSION_0 0x00
+#define IEEE80211_FC0_TYPE_MASK 0x0c
+#define IEEE80211_FC0_TYPE_SHIFT 2
+#define IEEE80211_FC0_TYPE_MGT 0x00
+#define IEEE80211_FC0_TYPE_CTL 0x04
+#define IEEE80211_FC0_TYPE_DATA 0x08
+
+#define IEEE80211_FC0_SUBTYPE_MASK 0xf0
+#define IEEE80211_FC0_SUBTYPE_SHIFT 4
+/* for TYPE_MGT */
+#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00
+#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10
+#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20
+#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30
+#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40
+#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50
+#define IEEE80211_FC0_SUBTYPE_BEACON 0x80
+#define IEEE80211_FC0_SUBTYPE_ATIM 0x90
+#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0
+#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0
+#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0
+/* for TYPE_CTL */
+#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0
+#define IEEE80211_FC0_SUBTYPE_RTS 0xb0
+#define IEEE80211_FC0_SUBTYPE_CTS 0xc0
+#define IEEE80211_FC0_SUBTYPE_ACK 0xd0
+#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0
+#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0
+/* for TYPE_DATA (bit combination) */
+#define IEEE80211_FC0_SUBTYPE_DATA 0x00
+#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10
+#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20
+#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30
+#define IEEE80211_FC0_SUBTYPE_NODATA 0x40
+#define IEEE80211_FC0_SUBTYPE_CFACK 0x50
+#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60
+#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
+#define IEEE80211_FC0_SUBTYPE_QOS 0x80
+#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0
+
+#define IEEE80211_FC1_DIR_MASK 0x03
+#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */
+#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */
+#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */
+#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */
+
+#define IEEE80211_FC1_MORE_FRAG 0x04
+#define IEEE80211_FC1_RETRY 0x08
+#define IEEE80211_FC1_PWR_MGT 0x10
+#define IEEE80211_FC1_MORE_DATA 0x20
+#define IEEE80211_FC1_WEP 0x40
+#define IEEE80211_FC1_ORDER 0x80
+
+#define IEEE80211_SEQ_FRAG_MASK 0x000f
+#define IEEE80211_SEQ_FRAG_SHIFT 0
+#define IEEE80211_SEQ_SEQ_MASK 0xfff0
+#define IEEE80211_SEQ_SEQ_SHIFT 4
+
+#define IEEE80211_NWID_LEN 32
+
+/*
+ * 802.11 rate set.
+ */
+#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */
+#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */
+
+#define WMM_NUM_AC 4 /* 4 AC categories */
+
+#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */
+#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */
+#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */
+#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */
+#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */
+#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */
+#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */
+#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */
+
+#define WMM_AC_TO_TID(_ac) ( \
+ ((_ac) == WMM_AC_VO) ? 6 : \
+ ((_ac) == WMM_AC_VI) ? 5 : \
+ ((_ac) == WMM_AC_BK) ? 1 : \
+ 0)
+
+#define TID_TO_WMM_AC(_tid) ( \
+ ((_tid) < 1) ? WMM_AC_BE : \
+ ((_tid) < 3) ? WMM_AC_BK : \
+ ((_tid) < 6) ? WMM_AC_VI : \
+ WMM_AC_VO)
+/*
+ * Management information element payloads.
+ */
+
+enum {
+ IEEE80211_ELEMID_SSID = 0,
+ IEEE80211_ELEMID_RATES = 1,
+ IEEE80211_ELEMID_FHPARMS = 2,
+ IEEE80211_ELEMID_DSPARMS = 3,
+ IEEE80211_ELEMID_CFPARMS = 4,
+ IEEE80211_ELEMID_TIM = 5,
+ IEEE80211_ELEMID_IBSSPARMS = 6,
+ IEEE80211_ELEMID_COUNTRY = 7,
+ IEEE80211_ELEMID_CHALLENGE = 16,
+ /* 17-31 reserved for challenge text extension */
+ IEEE80211_ELEMID_PWRCNSTR = 32,
+ IEEE80211_ELEMID_PWRCAP = 33,
+ IEEE80211_ELEMID_TPCREQ = 34,
+ IEEE80211_ELEMID_TPCREP = 35,
+ IEEE80211_ELEMID_SUPPCHAN = 36,
+ IEEE80211_ELEMID_CHANSWITCH = 37,
+ IEEE80211_ELEMID_MEASREQ = 38,
+ IEEE80211_ELEMID_MEASREP = 39,
+ IEEE80211_ELEMID_QUIET = 40,
+ IEEE80211_ELEMID_IBSSDFS = 41,
+ IEEE80211_ELEMID_ERP = 42,
+ IEEE80211_ELEMID_HTCAP_ANA = 45, /* Address ANA, and non-ANA story, for interop. CL#171733 */
+ IEEE80211_ELEMID_RSN = 48,
+ IEEE80211_ELEMID_XRATES = 50,
+ IEEE80211_ELEMID_HTINFO_ANA = 61,
+#ifdef WAPI_ENABLE
+ IEEE80211_ELEMID_WAPI = 68,
+#endif
+ IEEE80211_ELEMID_TPC = 150,
+ IEEE80211_ELEMID_CCKM = 156,
+ IEEE80211_ELEMID_VENDOR = 221, /* vendor private */
+};
+
+#define ATH_OUI 0x7f0300 /* Atheros OUI */
+#define ATH_OUI_TYPE 0x01
+#define ATH_OUI_SUBTYPE 0x01
+#define ATH_OUI_VERSION 0x00
+
+#define WPA_OUI 0xf25000
+#define WPA_OUI_TYPE 0x01
+#define WPA_VERSION 1 /* current supported version */
+
+#define WPA_CSE_NULL 0x00
+#define WPA_CSE_WEP40 0x01
+#define WPA_CSE_TKIP 0x02
+#define WPA_CSE_CCMP 0x04
+#define WPA_CSE_WEP104 0x05
+
+#define WPA_ASE_NONE 0x00
+#define WPA_ASE_8021X_UNSPEC 0x01
+#define WPA_ASE_8021X_PSK 0x02
+
+#define RSN_OUI 0xac0f00
+#define RSN_VERSION 1 /* current supported version */
+
+#define RSN_CSE_NULL 0x00
+#define RSN_CSE_WEP40 0x01
+#define RSN_CSE_TKIP 0x02
+#define RSN_CSE_WRAP 0x03
+#define RSN_CSE_CCMP 0x04
+#define RSN_CSE_WEP104 0x05
+
+#define RSN_ASE_NONE 0x00
+#define RSN_ASE_8021X_UNSPEC 0x01
+#define RSN_ASE_8021X_PSK 0x02
+
+#define RSN_CAP_PREAUTH 0x01
+
+#define WMM_OUI 0xf25000
+#define WMM_OUI_TYPE 0x02
+#define WMM_INFO_OUI_SUBTYPE 0x00
+#define WMM_PARAM_OUI_SUBTYPE 0x01
+#define WMM_VERSION 1
+
+/* WMM stream classes */
+#define WMM_NUM_AC 4
+#define WMM_AC_BE 0 /* best effort */
+#define WMM_AC_BK 1 /* background */
+#define WMM_AC_VI 2 /* video */
+#define WMM_AC_VO 3 /* voice */
+
+/* TSPEC related */
+#define ACTION_CATEGORY_CODE_TSPEC 17
+#define ACTION_CODE_TSPEC_ADDTS 0
+#define ACTION_CODE_TSPEC_ADDTS_RESP 1
+#define ACTION_CODE_TSPEC_DELTS 2
+
+typedef enum {
+ TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
+ TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
+ TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
+ TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
+ TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
+ TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
+ TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
+ TSPEC_STATUS_CODE_DELTS_SENT = 0x30,
+ TSPEC_STATUS_CODE_DELTS_RECV = 0x31,
+} TSPEC_STATUS_CODE;
+
+#define TSPEC_TSID_MASK 0xF
+#define TSPEC_TSID_S 1
+
+/*
+ * WMM/802.11e Tspec Element
+ */
+typedef PREPACK struct wmm_tspec_ie_t {
+ A_UINT8 elementId;
+ A_UINT8 len;
+ A_UINT8 oui[3];
+ A_UINT8 ouiType;
+ A_UINT8 ouiSubType;
+ A_UINT8 version;
+ A_UINT16 tsInfo_info;
+ A_UINT8 tsInfo_reserved;
+ A_UINT16 nominalMSDU;
+ A_UINT16 maxMSDU;
+ A_UINT32 minServiceInt;
+ A_UINT32 maxServiceInt;
+ A_UINT32 inactivityInt;
+ A_UINT32 suspensionInt;
+ A_UINT32 serviceStartTime;
+ A_UINT32 minDataRate;
+ A_UINT32 meanDataRate;
+ A_UINT32 peakDataRate;
+ A_UINT32 maxBurstSize;
+ A_UINT32 delayBound;
+ A_UINT32 minPhyRate;
+ A_UINT16 sba;
+ A_UINT16 mediumTime;
+} POSTPACK WMM_TSPEC_IE;
+
+
+/*
+ * BEACON management packets
+ *
+ * octet timestamp[8]
+ * octet beacon interval[2]
+ * octet capability information[2]
+ * information element
+ * octet elemid
+ * octet length
+ * octet information[length]
+ */
+
+#define IEEE80211_BEACON_INTERVAL(beacon) \
+ ((beacon)[8] | ((beacon)[9] << 8))
+#define IEEE80211_BEACON_CAPABILITY(beacon) \
+ ((beacon)[10] | ((beacon)[11] << 8))
+
+#define IEEE80211_CAPINFO_ESS 0x0001
+#define IEEE80211_CAPINFO_IBSS 0x0002
+#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004
+#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008
+#define IEEE80211_CAPINFO_PRIVACY 0x0010
+#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020
+#define IEEE80211_CAPINFO_PBCC 0x0040
+#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080
+/* bits 8-9 are reserved */
+#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400
+#define IEEE80211_CAPINFO_APSD 0x0800
+/* bit 12 is reserved */
+#define IEEE80211_CAPINFO_DSSSOFDM 0x2000
+/* bits 14-15 are reserved */
+
+/*
+ * Authentication Modes
+ */
+
+enum ieee80211_authmode {
+ IEEE80211_AUTH_NONE = 0,
+ IEEE80211_AUTH_OPEN = 1,
+ IEEE80211_AUTH_SHARED = 2,
+ IEEE80211_AUTH_8021X = 3,
+ IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */
+ /* NB: these are used only for ioctls */
+ IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */
+ IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */
+ IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */
+};
+
+#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/
+
+#include "athendpack.h"
+
+#endif /* _NET80211_IEEE80211_H_ */
diff --git a/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h b/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h
new file mode 100644
index 000000000000..faa1d653509e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h
@@ -0,0 +1,81 @@
+//------------------------------------------------------------------------------
+// <copyright file="ieee80211_node.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _IEEE80211_NODE_H_
+#define _IEEE80211_NODE_H_
+
+/*
+ * Node locking definitions.
+ */
+#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \
+ A_MUTEX_DELETE(&(_nt)->nt_nodelock); }
+
+#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_ASSERT(_nt)
+
+/*
+ * Node reference counting definitions.
+ *
+ * ieee80211_node_initref initialize the reference count to 1
+ * ieee80211_node_incref add a reference
+ * ieee80211_node_decref remove a reference
+ * ieee80211_node_dectestref remove a reference and return 1 if this
+ * is the last reference, otherwise 0
+ * ieee80211_node_refcnt reference count for printing (only)
+ */
+#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1)
+#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++)
+#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--)
+#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 1)
+#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt)
+
+#define IEEE80211_NODE_HASHSIZE 32
+/* simple hash is enough for variation of macaddr */
+#define IEEE80211_NODE_HASH(addr) \
+ (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
+ IEEE80211_NODE_HASHSIZE)
+
+/*
+ * Table of ieee80211_node instances. Each ieee80211com
+ * has at least one for holding the scan candidates.
+ * When operating as an access point or in ibss mode there
+ * is a second table for associated stations or neighbors.
+ */
+struct ieee80211_node_table {
+ void *nt_wmip; /* back reference */
+ A_MUTEX_T nt_nodelock; /* on node table */
+ struct bss *nt_node_first; /* information of all nodes */
+ struct bss *nt_node_last; /* information of all nodes */
+ struct bss *nt_hash[IEEE80211_NODE_HASHSIZE];
+ const char *nt_name; /* for debugging */
+ A_UINT32 nt_scangen; /* gen# for timeout scan */
+ A_TIMER nt_inact_timer;
+ A_UINT8 isTimerArmed; /* is the node timer armed */
+ A_UINT32 nt_nodeAge; /* node aging time */
+#ifdef OS_ROAM_MANAGEMENT
+ A_UINT32 nt_si_gen; /* gen# for scan indication*/
+#endif
+};
+
+#define WLAN_NODE_INACT_TIMEOUT_MSEC 120000
+
+#endif /* _IEEE80211_NODE_H_ */
diff --git a/drivers/net/wireless/ath6kl/wlan/src/makefile b/drivers/net/wireless/ath6kl/wlan/src/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c
new file mode 100644
index 000000000000..4f87d031459c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c
@@ -0,0 +1,569 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_node.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// IEEE 802.11 node handling support.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#define ATH_MODULE_NAME wlan
+#include <a_debug.h>
+#include "htc.h"
+#include "htc_api.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include <ieee80211_node.h>
+
+#define ATH_DEBUG_WLAN ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef DEBUG
+
+static ATH_DEBUG_MASK_DESCRIPTION wlan_debug_desc[] = {
+ { ATH_DEBUG_WLAN , "General WLAN Node Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(wlan,
+ "wlan",
+ "WLAN Node Management",
+ ATH_DEBUG_MASK_DEFAULTS,
+ ATH_DEBUG_DESCRIPTION_COUNT(wlan_debug_desc),
+ wlan_debug_desc);
+
+#endif
+
+static void wlan_node_timeout(A_ATH_TIMER arg);
+
+static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt,
+ const A_UINT8 *macaddr);
+
+bss_t *
+wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
+{
+ bss_t *ni;
+
+ ni = A_MALLOC_NOWAIT(sizeof(bss_t));
+
+ if (ni != NULL) {
+ if (wh_size)
+ {
+ ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
+ if (ni->ni_buf == NULL) {
+ A_FREE(ni);
+ ni = NULL;
+ return ni;
+ }
+ }
+ } else {
+ return ni;
+ }
+
+ /* Make sure our lists are clean */
+ ni->ni_list_next = NULL;
+ ni->ni_list_prev = NULL;
+ ni->ni_hash_next = NULL;
+ ni->ni_hash_prev = NULL;
+
+ //
+ // ni_scangen never initialized before and during suspend/resume of winmobile,
+ // that some junk has been stored in this, due to this scan list didn't properly updated
+ //
+ ni->ni_scangen = 0;
+
+#ifdef OS_ROAM_MANAGEMENT
+ ni->ni_si_gen = 0;
+#endif
+
+ return ni;
+}
+
+void
+wlan_node_free(bss_t *ni)
+{
+ if (ni->ni_buf != NULL) {
+ A_FREE(ni->ni_buf);
+ }
+ A_FREE(ni);
+}
+
+void
+wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+ const A_UINT8 *macaddr)
+{
+ int hash;
+ A_UINT32 timeoutValue = 0;
+
+ A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
+ hash = IEEE80211_NODE_HASH (macaddr);
+ ieee80211_node_initref (ni); /* mark referenced */
+
+ timeoutValue = nt->nt_nodeAge;
+
+ ni->ni_tstamp = A_GET_MS (timeoutValue);
+
+ IEEE80211_NODE_LOCK_BH(nt);
+
+ /* Insert at the end of the node list */
+ ni->ni_list_next = NULL;
+ ni->ni_list_prev = nt->nt_node_last;
+ if(nt->nt_node_last != NULL)
+ {
+ nt->nt_node_last->ni_list_next = ni;
+ }
+ nt->nt_node_last = ni;
+ if(nt->nt_node_first == NULL)
+ {
+ nt->nt_node_first = ni;
+ }
+
+ /* Insert into the hash list i.e. the bucket */
+ if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
+ {
+ nt->nt_hash[hash]->ni_hash_prev = ni;
+ }
+ ni->ni_hash_prev = NULL;
+ nt->nt_hash[hash] = ni;
+
+ if (!nt->isTimerArmed) {
+ A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0);
+ nt->isTimerArmed = TRUE;
+ }
+
+ IEEE80211_NODE_UNLOCK_BH(nt);
+}
+
+static bss_t *
+_ieee80211_find_node(struct ieee80211_node_table *nt,
+ const A_UINT8 *macaddr)
+{
+ bss_t *ni;
+ int hash;
+
+ IEEE80211_NODE_LOCK_ASSERT(nt);
+
+ hash = IEEE80211_NODE_HASH(macaddr);
+ for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
+ if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
+ ieee80211_node_incref(ni); /* mark referenced */
+ return ni;
+ }
+ }
+ return NULL;
+}
+
+bss_t *
+wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
+{
+ bss_t *ni;
+
+ IEEE80211_NODE_LOCK(nt);
+ ni = _ieee80211_find_node(nt, macaddr);
+ IEEE80211_NODE_UNLOCK(nt);
+ return ni;
+}
+
+/*
+ * Reclaim a node. If this is the last reference count then
+ * do the normal free work. Otherwise remove it from the node
+ * table and mark it gone by clearing the back-reference.
+ */
+void
+wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
+{
+ IEEE80211_NODE_LOCK(nt);
+
+ if(ni->ni_list_prev == NULL)
+ {
+ /* First in list so fix the list head */
+ nt->nt_node_first = ni->ni_list_next;
+ }
+ else
+ {
+ ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+ }
+
+ if(ni->ni_list_next == NULL)
+ {
+ /* Last in list so fix list tail */
+ nt->nt_node_last = ni->ni_list_prev;
+ }
+ else
+ {
+ ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+ }
+
+ if(ni->ni_hash_prev == NULL)
+ {
+ /* First in list so fix the list head */
+ int hash;
+ hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+ nt->nt_hash[hash] = ni->ni_hash_next;
+ }
+ else
+ {
+ ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+ }
+
+ if(ni->ni_hash_next != NULL)
+ {
+ ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+ }
+ wlan_node_free(ni);
+
+ IEEE80211_NODE_UNLOCK(nt);
+}
+
+static void
+wlan_node_dec_free(bss_t *ni)
+{
+ if (ieee80211_node_dectestref(ni)) {
+ wlan_node_free(ni);
+ }
+}
+
+void
+wlan_free_allnodes(struct ieee80211_node_table *nt)
+{
+ bss_t *ni;
+
+ while ((ni = nt->nt_node_first) != NULL) {
+ wlan_node_reclaim(nt, ni);
+ }
+}
+
+void
+wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+ void *arg)
+{
+ bss_t *ni;
+ A_UINT32 gen;
+
+ gen = ++nt->nt_scangen;
+
+ IEEE80211_NODE_LOCK(nt);
+ for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+ if (ni->ni_scangen != gen) {
+ ni->ni_scangen = gen;
+ (void) ieee80211_node_incref(ni);
+ (*f)(arg, ni);
+ wlan_node_dec_free(ni);
+ }
+ }
+ IEEE80211_NODE_UNLOCK(nt);
+}
+
+/*
+ * Node table support.
+ */
+void
+wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
+{
+ int i;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt));
+ IEEE80211_NODE_LOCK_INIT(nt);
+
+ A_REGISTER_MODULE_DEBUG_INFO(wlan);
+
+ nt->nt_node_first = nt->nt_node_last = NULL;
+ for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
+ {
+ nt->nt_hash[i] = NULL;
+ }
+
+ A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
+ nt->isTimerArmed = FALSE;
+ nt->nt_wmip = wmip;
+ nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC;
+
+ //
+ // nt_scangen never initialized before and during suspend/resume of winmobile,
+ // that some junk has been stored in this, due to this scan list didn't properly updated
+ //
+ nt->nt_scangen = 0;
+
+#ifdef OS_ROAM_MANAGEMENT
+ nt->nt_si_gen = 0;
+#endif
+}
+
+void
+wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge)
+{
+ nt->nt_nodeAge = nodeAge;
+ return;
+}
+static void
+wlan_node_timeout (A_ATH_TIMER arg)
+{
+ struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
+ bss_t *bss, *nextBss;
+ A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
+ A_UINT32 timeoutValue = 0;
+
+ timeoutValue = nt->nt_nodeAge;
+
+ wmi_get_current_bssid(nt->nt_wmip, myBssid);
+
+ bss = nt->nt_node_first;
+ while (bss != NULL)
+ {
+ nextBss = bss->ni_list_next;
+ if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
+ {
+
+ if (bss->ni_tstamp <= A_GET_MS(0))
+ {
+ /*
+ * free up all but the current bss - if set
+ */
+ wlan_node_reclaim(nt, bss);
+ }
+ else
+ {
+ /*
+ * Re-arm timer, only when we have a bss other than
+ * current bss AND it is not aged-out.
+ */
+ reArmTimer = TRUE;
+ }
+ }
+ bss = nextBss;
+ }
+
+ if (reArmTimer)
+ A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0);
+
+ nt->isTimerArmed = reArmTimer;
+}
+
+void
+wlan_node_table_cleanup(struct ieee80211_node_table *nt)
+{
+ A_UNTIMEOUT(&nt->nt_inact_timer);
+ A_DELETE_TIMER(&nt->nt_inact_timer);
+ wlan_free_allnodes(nt);
+ IEEE80211_NODE_LOCK_DESTROY(nt);
+}
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID)
+{
+ bss_t *ni = NULL;
+ A_UCHAR *pIESsid = NULL;
+
+ IEEE80211_NODE_LOCK (nt);
+
+ for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+ pIESsid = ni->ni_cie.ie_ssid;
+ if (pIESsid[1] <= 32) {
+
+ // Step 1 : Check SSID
+ if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+ //
+ // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID
+ // Profile, otherwise check whether WPA2 or WPA
+ //
+ if (TRUE == bMatchSSID) {
+ ieee80211_node_incref (ni); /* mark referenced */
+ IEEE80211_NODE_UNLOCK (nt);
+ return ni;
+ }
+
+ // Step 2 : if SSID matches, check WPA or WPA2
+ if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) {
+ ieee80211_node_incref (ni); /* mark referenced */
+ IEEE80211_NODE_UNLOCK (nt);
+ return ni;
+ }
+ if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) {
+ ieee80211_node_incref(ni); /* mark referenced */
+ IEEE80211_NODE_UNLOCK (nt);
+ return ni;
+ }
+ }
+ }
+ }
+
+ IEEE80211_NODE_UNLOCK (nt);
+
+ return NULL;
+}
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni)
+{
+ IEEE80211_NODE_LOCK (nt);
+ wlan_node_dec_free (ni);
+ IEEE80211_NODE_UNLOCK (nt);
+}
+
+void
+wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni)
+{
+ if(ni->ni_list_prev == NULL)
+ {
+ /* First in list so fix the list head */
+ nt->nt_node_first = ni->ni_list_next;
+ }
+ else
+ {
+ ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+ }
+
+ if(ni->ni_list_next == NULL)
+ {
+ /* Last in list so fix list tail */
+ nt->nt_node_last = ni->ni_list_prev;
+ }
+ else
+ {
+ ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+ }
+
+ if(ni->ni_hash_prev == NULL)
+ {
+ /* First in list so fix the list head */
+ int hash;
+ hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+ nt->nt_hash[hash] = ni->ni_hash_next;
+ }
+ else
+ {
+ ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+ }
+
+ if(ni->ni_hash_next != NULL)
+ {
+ ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+ }
+}
+
+bss_t *
+wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid)
+{
+ bss_t *bss, *nextBss;
+
+ IEEE80211_NODE_LOCK(nt);
+
+ bss = nt->nt_node_first;
+
+ while (bss != NULL)
+ {
+ nextBss = bss->ni_list_next;
+
+ if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0)
+ {
+ wlan_node_remove_core (nt, bss);
+ IEEE80211_NODE_UNLOCK(nt);
+ return bss;
+ }
+
+ bss = nextBss;
+ }
+
+ IEEE80211_NODE_UNLOCK(nt);
+ return NULL;
+}
+
+bss_t *
+wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode,
+ A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp)
+{
+ bss_t *ni = NULL;
+ bss_t *best_ni = NULL;
+ A_UCHAR *pIESsid = NULL;
+
+ IEEE80211_NODE_LOCK (nt);
+
+ for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+ pIESsid = ni->ni_cie.ie_ssid;
+ if (pIESsid[1] <= 32) {
+
+ // Step 1 : Check SSID
+ if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+ if (ni->ni_cie.ie_capInfo & 0x10)
+ {
+
+ if ((NULL != ni->ni_cie.ie_rsn) && (WPA2_PSK_AUTH == authMode))
+ {
+ /* WPA2 */
+ if (NULL == best_ni)
+ {
+ best_ni = ni;
+ }
+ else if (ni->ni_rssi > best_ni->ni_rssi)
+ {
+ best_ni = ni;
+ }
+ }
+ else if ((NULL != ni->ni_cie.ie_wpa) && (WPA_PSK_AUTH == authMode))
+ {
+ /* WPA */
+ if (NULL == best_ni)
+ {
+ best_ni = ni;
+ }
+ else if (ni->ni_rssi > best_ni->ni_rssi)
+ {
+ best_ni = ni;
+ }
+ }
+ else if (WEP_CRYPT == pairwiseCryptoType)
+ {
+ /* WEP */
+ if (NULL == best_ni)
+ {
+ best_ni = ni;
+ }
+ else if (ni->ni_rssi > best_ni->ni_rssi)
+ {
+ best_ni = ni;
+ }
+ }
+ }
+ else
+ {
+ /* open AP */
+ if ((OPEN_AUTH == authMode) && (NONE_CRYPT == pairwiseCryptoType))
+ {
+ if (NULL == best_ni)
+ {
+ best_ni = ni;
+ }
+ else if (ni->ni_rssi > best_ni->ni_rssi)
+ {
+ best_ni = ni;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ IEEE80211_NODE_UNLOCK (nt);
+
+ return best_ni;
+}
+
diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c
new file mode 100644
index 000000000000..0d5bce78165f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c
@@ -0,0 +1,196 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_recv_beacon.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// IEEE 802.11 input handling.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+
+#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \
+ if ((_len) < (_minlen)) { \
+ return A_EINVAL; \
+ } \
+} while (0)
+
+#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \
+ if ((__elem) == NULL) { \
+ return A_EINVAL; \
+ } \
+ if ((__elem)[1] > (__maxlen)) { \
+ return A_EINVAL; \
+ } \
+} while (0)
+
+
+/* unaligned little endian access */
+#define LE_READ_2(p) \
+ ((A_UINT16) \
+ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8)))
+
+#define LE_READ_4(p) \
+ ((A_UINT32) \
+ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \
+ (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+
+static int __inline
+iswpaoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
+}
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+/* unused functions for now */
+#if 0
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+ return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+static int __inline
+iswmminfo(const A_UINT8 *frm)
+{
+ return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
+}
+#endif
+
+static int __inline
+isatherosoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
+}
+
+static int __inline
+iswscoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI);
+}
+
+A_STATUS
+wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
+{
+ A_UINT8 *frm, *efrm;
+ A_UINT8 elemid_ssid = FALSE;
+
+ frm = buf;
+ efrm = (A_UINT8 *) (frm + framelen);
+
+ /*
+ * beacon/probe response frame format
+ * [8] time stamp
+ * [2] beacon interval
+ * [2] capability information
+ * [tlv] ssid
+ * [tlv] supported rates
+ * [tlv] country information
+ * [tlv] parameter set (FH/DS)
+ * [tlv] erp information
+ * [tlv] extended supported rates
+ * [tlv] WMM
+ * [tlv] WPA or RSN
+ * [tlv] Atheros Advanced Capabilities
+ */
+ IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
+ A_MEMZERO(cie, sizeof(*cie));
+
+ cie->ie_tstamp = frm; frm += 8;
+ cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2;
+ cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2;
+ cie->ie_chan = 0;
+
+ while (frm < efrm) {
+ switch (*frm) {
+ case IEEE80211_ELEMID_SSID:
+ if (!elemid_ssid) {
+ cie->ie_ssid = frm;
+ elemid_ssid = TRUE;
+ }
+ break;
+ case IEEE80211_ELEMID_RATES:
+ cie->ie_rates = frm;
+ break;
+ case IEEE80211_ELEMID_COUNTRY:
+ cie->ie_country = frm;
+ break;
+ case IEEE80211_ELEMID_FHPARMS:
+ break;
+ case IEEE80211_ELEMID_DSPARMS:
+ cie->ie_chan = frm[2];
+ break;
+ case IEEE80211_ELEMID_TIM:
+ cie->ie_tim = frm;
+ break;
+ case IEEE80211_ELEMID_IBSSPARMS:
+ break;
+ case IEEE80211_ELEMID_XRATES:
+ cie->ie_xrates = frm;
+ break;
+ case IEEE80211_ELEMID_ERP:
+ if (frm[1] != 1) {
+ //A_PRINTF("Discarding ERP Element - Bad Len\n");
+ return A_EINVAL;
+ }
+ cie->ie_erp = frm[2];
+ break;
+ case IEEE80211_ELEMID_RSN:
+ cie->ie_rsn = frm;
+ break;
+ case IEEE80211_ELEMID_HTCAP_ANA:
+ cie->ie_htcap = frm;
+ break;
+ case IEEE80211_ELEMID_HTINFO_ANA:
+ cie->ie_htop = frm;
+ break;
+#ifdef WAPI_ENABLE
+ case IEEE80211_ELEMID_WAPI:
+ cie->ie_wapi = frm;
+ break;
+#endif
+ case IEEE80211_ELEMID_VENDOR:
+ if (iswpaoui(frm)) {
+ cie->ie_wpa = frm;
+ } else if (iswmmoui(frm)) {
+ cie->ie_wmm = frm;
+ } else if (isatherosoui(frm)) {
+ cie->ie_ath = frm;
+ } else if(iswscoui(frm)) {
+ cie->ie_wsc = frm;
+ }
+ break;
+ default:
+ break;
+ }
+ frm += frm[1] + 2;
+ }
+ IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
+ IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
+
+ return A_OK;
+}
diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c
new file mode 100644
index 000000000000..0d1c24ec1ca6
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c
@@ -0,0 +1,57 @@
+//------------------------------------------------------------------------------
+// <copyright file="wlan_utils.c" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This module implements frequently used wlan utilies
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+
+/*
+ * converts ieee channel number to frequency
+ */
+A_UINT16
+wlan_ieee2freq(int chan)
+{
+ if (chan == 14) {
+ return 2484;
+ }
+ if (chan < 14) { /* 0-13 */
+ return (2407 + (chan*5));
+ }
+ if (chan < 27) { /* 15-26 */
+ return (2512 + ((chan-15)*20));
+ }
+ return (5000 + (chan*5));
+}
+
+/*
+ * Converts MHz frequency to IEEE channel number.
+ */
+A_UINT32
+wlan_freq2ieee(A_UINT16 freq)
+{
+ if (freq == 2484)
+ return 14;
+ if (freq < 2484)
+ return (freq - 2407) / 5;
+ if (freq < 5000)
+ return 15 + ((freq - 2512) / 20);
+ return (freq - 5000) / 5;
+}
diff --git a/drivers/net/wireless/ath6kl/wmi/makefile b/drivers/net/wireless/ath6kl/wmi/makefile
new file mode 100644
index 000000000000..6e53a111b67f
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wmi/makefile
@@ -0,0 +1,22 @@
+#------------------------------------------------------------------------------
+# <copyright file="makefile" company="Atheros">
+# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation;
+#
+# Software distributed under the License is distributed on an "AS
+# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# rights and limitations under the License.
+#
+#
+#------------------------------------------------------------------------------
+#==============================================================================
+# Author(s): ="Atheros"
+#==============================================================================
+!INCLUDE $(_MAKEENVROOT)\makefile.def
+
+
+
diff --git a/drivers/net/wireless/ath6kl/wmi/wmi.c b/drivers/net/wireless/ath6kl/wmi/wmi.c
new file mode 100644
index 000000000000..3a7667d2c39e
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wmi/wmi.c
@@ -0,0 +1,6536 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi.c" company="Atheros">
+// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This module implements the hardware independent layer of the
+// Wireless Module Interface (WMI) protocol.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include "htc.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include <ieee80211.h>
+#include <ieee80211_node.h>
+#include "dset_api.h"
+#include "gpio_api.h"
+#include "wmi_host.h"
+#include "a_drv.h"
+#include "a_drv_api.h"
+#define ATH_MODULE_NAME wmi
+#include "a_debug.h"
+#include "dbglog_api.h"
+#include "roaming.h"
+
+#define ATH_DEBUG_WMI ATH_DEBUG_MAKE_MODULE_MASK(0)
+
+#ifdef DEBUG
+
+static ATH_DEBUG_MASK_DESCRIPTION wmi_debug_desc[] = {
+ { ATH_DEBUG_WMI , "General WMI Tracing"},
+};
+
+ATH_DEBUG_INSTANTIATE_MODULE_VAR(wmi,
+ "wmi",
+ "Wireless Module Interface",
+ ATH_DEBUG_MASK_DEFAULTS,
+ ATH_DEBUG_DESCRIPTION_COUNT(wmi_debug_desc),
+ wmi_debug_desc);
+
+#endif
+
+#ifndef REXOS
+#define DBGARG _A_FUNCNAME_
+#define DBGFMT "%s() : "
+#define DBG_WMI ATH_DEBUG_WMI
+#define DBG_ERROR ATH_DEBUG_ERR
+#define DBG_WMI2 ATH_DEBUG_WMI
+#define A_DPRINTF AR_DEBUG_PRINTF
+#endif
+
+static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+
+static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_sync_point(struct wmi_t *wmip);
+
+static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+
+static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+
+static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+static A_STATUS
+wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex);
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG syncflag);
+
+A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size);
+A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size);
+
+void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip,
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip,
+ WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static A_STATUS
+wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+
+static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+#ifdef ATH_AR6K_11N_SUPPORT
+static A_STATUS wmi_addba_req_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_addba_resp_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_delba_req_event_rx(struct wmi_t *, A_UINT8 *, int);
+static A_STATUS wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_btcoex_stats_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+static A_STATUS wmi_hci_event_rx(struct wmi_t *, A_UINT8 *, int);
+
+#ifdef WAPI_ENABLE
+static A_STATUS wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+#endif
+
+#if defined(UNDER_CE)
+#if defined(NDIS51_MINIPORT)
+unsigned int processDot11Hdr = 0;
+#else
+unsigned int processDot11Hdr = 1;
+#endif
+#else
+extern unsigned int processDot11Hdr;
+#endif
+
+int wps_enable;
+static const A_INT32 wmi_rateTable[][2] = {
+ //{W/O SGI, with SGI}
+ {1000, 1000},
+ {2000, 2000},
+ {5500, 5500},
+ {11000, 11000},
+ {6000, 6000},
+ {9000, 9000},
+ {12000, 12000},
+ {18000, 18000},
+ {24000, 24000},
+ {36000, 36000},
+ {48000, 48000},
+ {54000, 54000},
+ {6500, 7200},
+ {13000, 14400},
+ {19500, 21700},
+ {26000, 28900},
+ {39000, 43300},
+ {52000, 57800},
+ {58500, 65000},
+ {65000, 72200},
+ {13500, 15000},
+ {27000, 30000},
+ {40500, 45000},
+ {54000, 60000},
+ {81000, 90000},
+ {108000, 120000},
+ {121500, 135000},
+ {135000, 150000},
+ {0, 0}};
+
+#define MODE_A_SUPPORT_RATE_START ((A_INT32) 4)
+#define MODE_A_SUPPORT_RATE_STOP ((A_INT32) 11)
+
+#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START
+#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP
+
+#define MODE_B_SUPPORT_RATE_START ((A_INT32) 0)
+#define MODE_B_SUPPORT_RATE_STOP ((A_INT32) 3)
+
+#define MODE_G_SUPPORT_RATE_START ((A_INT32) 0)
+#define MODE_G_SUPPORT_RATE_STOP ((A_INT32) 11)
+
+#define MODE_GHT20_SUPPORT_RATE_START ((A_INT32) 0)
+#define MODE_GHT20_SUPPORT_RATE_STOP ((A_INT32) 19)
+
+#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_GHT20_SUPPORT_RATE_STOP + 1)
+
+/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
+const A_UINT8 up_to_ac[]= {
+ WMM_AC_BE,
+ WMM_AC_BK,
+ WMM_AC_BK,
+ WMM_AC_BE,
+ WMM_AC_VI,
+ WMM_AC_VI,
+ WMM_AC_VO,
+ WMM_AC_VO,
+ };
+
+#include "athstartpack.h"
+
+/* This stuff is used when we want a simple layer-3 visibility */
+typedef PREPACK struct _iphdr {
+ A_UINT8 ip_ver_hdrlen; /* version and hdr length */
+ A_UINT8 ip_tos; /* type of service */
+ A_UINT16 ip_len; /* total length */
+ A_UINT16 ip_id; /* identification */
+ A_INT16 ip_off; /* fragment offset field */
+#define IP_DF 0x4000 /* dont fragment flag */
+#define IP_MF 0x2000 /* more fragments flag */
+#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */
+ A_UINT8 ip_ttl; /* time to live */
+ A_UINT8 ip_p; /* protocol */
+ A_UINT16 ip_sum; /* checksum */
+ A_UINT8 ip_src[4]; /* source and dest address */
+ A_UINT8 ip_dst[4];
+} POSTPACK iphdr;
+
+#include "athendpack.h"
+
+A_INT16 rssi_event_value = 0;
+A_INT16 snr_event_value = 0;
+
+A_BOOL is_probe_ssid = FALSE;
+
+void *
+wmi_init(void *devt)
+{
+ struct wmi_t *wmip;
+
+ A_REGISTER_MODULE_DEBUG_INFO(wmi);
+
+ wmip = A_MALLOC(sizeof(struct wmi_t));
+ if (wmip == NULL) {
+ return (NULL);
+ }
+ A_MEMZERO(wmip, sizeof(*wmip));
+ A_MUTEX_INIT(&wmip->wmi_lock);
+ wmip->wmi_devt = devt;
+ wlan_node_table_init(wmip, &wmip->wmi_scan_table);
+ wmi_qos_state_init(wmip);
+
+ wmip->wmi_powerMode = REC_POWER;
+ wmip->wmi_phyMode = WMI_11G_MODE;
+
+ wmip->wmi_pair_crypto_type = NONE_CRYPT;
+ wmip->wmi_grp_crypto_type = NONE_CRYPT;
+
+ return (wmip);
+}
+
+void
+wmi_qos_state_init(struct wmi_t *wmip)
+{
+ A_UINT8 i;
+
+ if (wmip == NULL) {
+ return;
+ }
+ LOCK_WMI(wmip);
+
+ /* Initialize QoS States */
+ wmip->wmi_numQoSStream = 0;
+
+ wmip->wmi_fatPipeExists = 0;
+
+ for (i=0; i < WMM_NUM_AC; i++) {
+ wmip->wmi_streamExistsForAC[i]=0;
+ }
+
+ UNLOCK_WMI(wmip);
+
+ A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1);
+}
+
+void
+wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid)
+{
+ A_ASSERT( eid != ENDPOINT_UNUSED);
+ wmip->wmi_endpoint_id = eid;
+}
+
+HTC_ENDPOINT_ID
+wmi_get_control_ep(struct wmi_t * wmip)
+{
+ return(wmip->wmi_endpoint_id);
+}
+
+void
+wmi_shutdown(struct wmi_t *wmip)
+{
+ if (wmip != NULL) {
+ wlan_node_table_cleanup(&wmip->wmi_scan_table);
+ if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) {
+ A_MUTEX_DELETE(&wmip->wmi_lock);
+ }
+ A_FREE(wmip);
+ }
+}
+
+/*
+ * performs DIX to 802.3 encapsulation for transmit packets.
+ * uses passed in buffer. Returns buffer or NULL if failed.
+ * Assumes the entire DIX header is contigous and that there is
+ * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
+ */
+A_STATUS
+wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
+{
+ A_UINT8 *datap;
+ A_UINT16 typeorlen;
+ ATH_MAC_HDR macHdr;
+ ATH_LLC_SNAP_HDR *llcHdr;
+
+ A_ASSERT(osbuf != NULL);
+
+ if (A_NETBUF_HEADROOM(osbuf) <
+ (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+ {
+ return A_NO_MEMORY;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+ if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+ /*
+ * packet is already in 802.3 format - return success
+ */
+ A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+ return (A_OK);
+ }
+
+ /*
+ * Save mac fields and length to be inserted later
+ */
+ A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+ A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+ macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR));
+
+ /*
+ * Make room for LLC+SNAP headers
+ */
+ if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+ llcHdr->dsap = 0xAA;
+ llcHdr->ssap = 0xAA;
+ llcHdr->cntl = 0x03;
+ llcHdr->orgCode[0] = 0x0;
+ llcHdr->orgCode[1] = 0x0;
+ llcHdr->orgCode[2] = 0x0;
+ llcHdr->etherType = typeorlen;
+
+ return (A_OK);
+}
+
+A_STATUS wmi_meta_add(struct wmi_t *wmip, void *osbuf, A_UINT8 *pVersion,void *pTxMetaS)
+{
+ switch(*pVersion){
+ case 0:
+ return (A_OK);
+ case WMI_META_VERSION_1:
+ {
+ WMI_TX_META_V1 *pV1= NULL;
+ A_ASSERT(osbuf != NULL);
+ if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ pV1 = (WMI_TX_META_V1 *)A_NETBUF_DATA(osbuf);
+ /* the pktID is used in conjunction with txComplete messages
+ * allowing the target to notify which tx requests have been
+ * completed and how. */
+ pV1->pktID = 0;
+ /* the ratePolicyID allows the host to specify which rate policy
+ * to use for transmitting this packet. 0 means use default behavior. */
+ pV1->ratePolicyID = 0;
+ A_ASSERT(pVersion != NULL);
+ /* the version must be used to populate the meta field of the WMI_DATA_HDR */
+ *pVersion = WMI_META_VERSION_1;
+ return (A_OK);
+ }
+#ifdef CONFIG_CHECKSUM_OFFLOAD
+ case WMI_META_VERSION_2:
+ {
+ WMI_TX_META_V2 *pV2 ;
+ A_ASSERT(osbuf != NULL);
+ if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) {
+ return A_NO_MEMORY;
+ }
+ pV2 = (WMI_TX_META_V2 *)A_NETBUF_DATA(osbuf);
+ A_MEMCPY(pV2,(WMI_TX_META_V2 *)pTxMetaS,sizeof(WMI_TX_META_V2));
+ return (A_OK);
+ }
+#endif
+ default:
+ return (A_OK);
+ }
+}
+
+/* Adds a WMI data header */
+A_STATUS
+wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData,
+ WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS)
+{
+ WMI_DATA_HDR *dtHdr;
+// A_UINT8 metaVersion = 0;
+ A_STATUS status;
+
+ A_ASSERT(osbuf != NULL);
+
+ /* adds the meta data field after the wmi data hdr. If metaVersion
+ * is returns 0 then no meta field was added. */
+ if ((status = wmi_meta_add(wmip, osbuf, &metaVersion,pTxMetaS)) != A_OK) {
+ return status;
+ }
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+ A_MEMZERO(dtHdr, sizeof(WMI_DATA_HDR));
+
+ WMI_DATA_HDR_SET_MSG_TYPE(dtHdr, msgType);
+ WMI_DATA_HDR_SET_DATA_TYPE(dtHdr, data_type);
+
+ if (bMoreData) {
+ WMI_DATA_HDR_SET_MORE_BIT(dtHdr);
+ }
+
+ WMI_DATA_HDR_SET_META(dtHdr, metaVersion);
+ //dtHdr->rssi = 0;
+
+ return (A_OK);
+}
+
+
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled)
+{
+ A_UINT8 *datap;
+ A_UINT8 trafficClass = WMM_AC_BE;
+ A_UINT16 ipType = IP_ETHERTYPE;
+ WMI_DATA_HDR *dtHdr;
+ A_BOOL streamExists = FALSE;
+ A_UINT8 userPriority;
+ A_UINT32 hdrsize, metasize;
+ ATH_LLC_SNAP_HDR *llcHdr;
+
+ WMI_CREATE_PSTREAM_CMD cmd;
+
+ A_ASSERT(osbuf != NULL);
+
+ //
+ // Initialize header size
+ //
+ hdrsize = 0;
+
+ datap = A_NETBUF_DATA(osbuf);
+ dtHdr = (WMI_DATA_HDR *)datap;
+ metasize = (WMI_DATA_HDR_GET_META(dtHdr))? WMI_MAX_TX_META_SZ : 0;
+
+ if (!wmmEnabled)
+ {
+ /* If WMM is disabled all traffic goes as BE traffic */
+ userPriority = 0;
+ }
+ else
+ {
+ if (processDot11Hdr)
+ {
+ hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize +
+ hdrsize);
+
+
+ }
+ else
+ {
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize +
+ sizeof(ATH_MAC_HDR));
+ }
+
+ if (llcHdr->etherType == A_CPU2BE16(ipType))
+ {
+ /* Extract the endpoint info from the TOS field in the IP header */
+
+ userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority);
+ }
+ else
+ {
+ userPriority = layer2Priority & 0x7;
+ }
+ }
+
+ trafficClass = convert_userPriority_to_trafficClass(userPriority);
+
+ WMI_DATA_HDR_SET_UP(dtHdr, userPriority);
+ //dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */
+
+ LOCK_WMI(wmip);
+ streamExists = wmip->wmi_fatPipeExists;
+ UNLOCK_WMI(wmip);
+
+ if (!(streamExists & (1 << trafficClass)))
+ {
+
+ A_MEMZERO(&cmd, sizeof(cmd));
+ cmd.trafficClass = trafficClass;
+ cmd.userPriority = userPriority;
+ cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
+ /* Implicit streams are created with TSID 0xFF */
+
+ cmd.tsid = WMI_IMPLICIT_PSTREAM;
+ wmi_create_pstream_cmd(wmip, &cmd);
+ }
+
+ return trafficClass;
+}
+
+A_STATUS
+wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode)
+{
+ A_UINT8 *datap;
+ A_UINT16 typeorlen;
+ ATH_MAC_HDR macHdr;
+ ATH_LLC_SNAP_HDR *llcHdr;
+ struct ieee80211_frame *wh;
+ A_UINT32 hdrsize;
+
+ A_ASSERT(osbuf != NULL);
+
+ if (A_NETBUF_HEADROOM(osbuf) <
+ (sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+ {
+ return A_NO_MEMORY;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+ if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+/*
+ * packet is already in 802.3 format - return success
+ */
+ A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+ goto AddDot11Hdr;
+ }
+
+ /*
+ * Save mac fields and length to be inserted later
+ */
+ A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+ A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+ macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR));
+
+ // Remove the Ethernet hdr
+ A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR));
+ /*
+ * Make room for LLC+SNAP headers
+ */
+ if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+ datap = A_NETBUF_DATA(osbuf);
+
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap);
+ llcHdr->dsap = 0xAA;
+ llcHdr->ssap = 0xAA;
+ llcHdr->cntl = 0x03;
+ llcHdr->orgCode[0] = 0x0;
+ llcHdr->orgCode[1] = 0x0;
+ llcHdr->orgCode[2] = 0x0;
+ llcHdr->etherType = typeorlen;
+
+AddDot11Hdr:
+ /* Make room for 802.11 hdr */
+ if (wmip->wmi_is_wmm_enabled)
+ {
+ hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+ if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK)
+ {
+ return A_NO_MEMORY;
+ }
+ wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf);
+ wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS;
+ }
+ else
+ {
+ hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32));
+ if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK)
+ {
+ return A_NO_MEMORY;
+ }
+ wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf);
+ wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA;
+ }
+ /* Setup the SA & DA */
+ IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac);
+
+ if (mode == INFRA_NETWORK) {
+ IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac);
+ }
+ else if (mode == ADHOC_NETWORK) {
+ IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac);
+ }
+
+ return (A_OK);
+}
+
+A_STATUS
+wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+ A_UINT8 *datap;
+ struct ieee80211_frame *pwh,wh;
+ A_UINT8 type,subtype;
+ ATH_LLC_SNAP_HDR *llcHdr;
+ ATH_MAC_HDR macHdr;
+ A_UINT32 hdrsize;
+
+ A_ASSERT(osbuf != NULL);
+ datap = A_NETBUF_DATA(osbuf);
+
+ pwh = (struct ieee80211_frame *)datap;
+ type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
+ subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
+
+ A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame));
+
+ /* strip off the 802.11 hdr*/
+ if (subtype == IEEE80211_FC0_SUBTYPE_QOS) {
+ hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32));
+ A_NETBUF_PULL(osbuf, hdrsize);
+ } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) {
+ A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame));
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap);
+
+ macHdr.typeOrLen = llcHdr->etherType;
+
+ switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) {
+ case IEEE80211_FC1_DIR_NODS:
+ IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1);
+ IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2);
+ break;
+ case IEEE80211_FC1_DIR_TODS:
+ IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3);
+ IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2);
+ break;
+ case IEEE80211_FC1_DIR_FROMDS:
+ IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1);
+ IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3);
+ break;
+ case IEEE80211_FC1_DIR_DSTODS:
+ break;
+ }
+
+ // Remove the LLC Hdr.
+ A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR));
+
+ // Insert the ATH MAC hdr.
+
+ A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR));
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR));
+
+ return A_OK;
+}
+
+/*
+ * performs 802.3 to DIX encapsulation for received packets.
+ * Assumes the entire 802.3 header is contigous.
+ */
+A_STATUS
+wmi_dot3_2_dix(void *osbuf)
+{
+ A_UINT8 *datap;
+ ATH_MAC_HDR macHdr;
+ ATH_LLC_SNAP_HDR *llcHdr;
+
+ A_ASSERT(osbuf != NULL);
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+ macHdr.typeOrLen = llcHdr->etherType;
+
+ if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+ return (A_OK);
+}
+
+/*
+ * Removes a WMI data header
+ */
+A_STATUS
+wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+ A_ASSERT(osbuf != NULL);
+
+ return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR)));
+}
+
+void
+wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
+{
+ wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
+}
+
+/*
+ * WMI Extended Event received from Target.
+ */
+A_STATUS
+wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
+{
+ WMIX_CMD_HDR *cmd;
+ A_UINT16 id;
+ A_UINT8 *datap;
+ A_UINT32 len;
+ A_STATUS status = A_OK;
+
+ if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ return A_ERROR;
+ }
+
+ cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ id = cmd->commandId;
+
+ if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ return A_ERROR;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+ len = A_NETBUF_LEN(osbuf);
+
+ switch (id) {
+ case (WMIX_DSETOPENREQ_EVENTID):
+ status = wmi_dset_open_req_rx(wmip, datap, len);
+ break;
+#ifdef CONFIG_HOST_DSET_SUPPORT
+ case (WMIX_DSETCLOSE_EVENTID):
+ status = wmi_dset_close_rx(wmip, datap, len);
+ break;
+ case (WMIX_DSETDATAREQ_EVENTID):
+ status = wmi_dset_data_req_rx(wmip, datap, len);
+ break;
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+ case (WMIX_GPIO_INTR_EVENTID):
+ wmi_gpio_intr_rx(wmip, datap, len);
+ break;
+ case (WMIX_GPIO_DATA_EVENTID):
+ wmi_gpio_data_rx(wmip, datap, len);
+ break;
+ case (WMIX_GPIO_ACK_EVENTID):
+ wmi_gpio_ack_rx(wmip, datap, len);
+ break;
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+ case (WMIX_HB_CHALLENGE_RESP_EVENTID):
+ wmi_hbChallengeResp_rx(wmip, datap, len);
+ break;
+ case (WMIX_DBGLOG_EVENTID):
+ wmi_dbglog_event_rx(wmip, datap, len);
+ break;
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+ case (WMIX_PROF_COUNT_EVENTID):
+ wmi_prof_count_rx(wmip, datap, len);
+ break;
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+ default:
+ A_DPRINTF(DBG_WMI|DBG_ERROR,
+ (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+ wmip->wmi_stats.cmd_id_err++;
+ status = A_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/*
+ * Control Path
+ */
+A_UINT32 cmdRecvNum;
+
+A_STATUS
+wmi_control_rx(struct wmi_t *wmip, void *osbuf)
+{
+ WMI_CMD_HDR *cmd;
+ A_UINT16 id;
+ A_UINT8 *datap;
+ A_UINT32 len, i, loggingReq;
+ A_STATUS status = A_OK;
+
+ A_ASSERT(osbuf != NULL);
+ if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) {
+ A_NETBUF_FREE(osbuf);
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ return A_ERROR;
+ }
+
+ cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ id = cmd->commandId;
+
+ if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+ A_NETBUF_FREE(osbuf);
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ return A_ERROR;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+ len = A_NETBUF_LEN(osbuf);
+
+ loggingReq = 0;
+
+ ar6000_get_driver_cfg(wmip->wmi_devt,
+ AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS,
+ &loggingReq);
+
+ if(loggingReq) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id));
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum));
+ for(i = 0; i < len; i++)
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i]));
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n"));
+ }
+
+ LOCK_WMI(wmip);
+ cmdRecvNum++;
+ UNLOCK_WMI(wmip);
+
+ switch (id) {
+ case (WMI_GET_BITRATE_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG));
+ status = wmi_bitrate_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_CHANNEL_LIST_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG));
+ status = wmi_channelList_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_TX_PWR_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG));
+ status = wmi_txPwr_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_READY_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
+ status = wmi_ready_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
+ break;
+ case (WMI_CONNECT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
+ status = wmi_connect_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_DISCONNECT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
+ status = wmi_disconnect_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_PEER_NODE_EVENTID):
+ A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG));
+ status = wmi_peer_node_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_TKIP_MICERR_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
+ status = wmi_tkip_micerr_event_rx(wmip, datap, len);
+ break;
+ case (WMI_BSSINFO_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG));
+ {
+ /*
+ * convert WMI_BSS_INFO_HDR2 to WMI_BSS_INFO_HDR
+ * Take a local copy of the WMI_BSS_INFO_HDR2 from the wmi buffer
+ * and reconstruct the WMI_BSS_INFO_HDR in its place
+ */
+ WMI_BSS_INFO_HDR2 bih2;
+ WMI_BSS_INFO_HDR *bih;
+ A_MEMCPY(&bih2, datap, sizeof(WMI_BSS_INFO_HDR2));
+
+ A_NETBUF_PUSH(osbuf, 4);
+ datap = A_NETBUF_DATA(osbuf);
+ len = A_NETBUF_LEN(osbuf);
+ bih = (WMI_BSS_INFO_HDR *)datap;
+
+ bih->channel = bih2.channel;
+ bih->frameType = bih2.frameType;
+ bih->snr = bih2.snr;
+ bih->rssi = bih2.snr - 95;
+ bih->ieMask = bih2.ieMask;
+ A_MEMCPY(bih->bssid, bih2.bssid, ATH_MAC_LEN);
+
+ status = wmi_bssInfo_event_rx(wmip, datap, len);
+ A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ }
+ break;
+ case (WMI_REGDOMAIN_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG));
+ status = wmi_regDomain_event_rx(wmip, datap, len);
+ break;
+ case (WMI_PSTREAM_TIMEOUT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
+ status = wmi_pstream_timeout_event_rx(wmip, datap, len);
+ /* pstreams are fatpipe abstractions that get implicitly created.
+ * User apps only deal with thinstreams. creation of a thinstream
+ * by the user or data traffic flow in an AC triggers implicit
+ * pstream creation. Do we need to send this event to App..?
+ * no harm in sending it.
+ */
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_NEIGHBOR_REPORT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
+ status = wmi_neighborReport_event_rx(wmip, datap, len);
+ break;
+ case (WMI_SCAN_COMPLETE_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
+ status = wmi_scanComplete_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_CMDERROR_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
+ status = wmi_errorEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_STATISTICS_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG));
+ status = wmi_statsEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_RSSI_THRESHOLD_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG));
+ status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_ERROR_REPORT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
+ status = wmi_reportErrorEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_OPT_RX_FRAME_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
+ status = wmi_opt_frame_event_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_ROAM_TBL_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG));
+ status = wmi_roam_tbl_event_rx(wmip, datap, len);
+ break;
+ case (WMI_EXTENSION_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG));
+ status = wmi_control_rx_xtnd(wmip, osbuf);
+ break;
+ case (WMI_CAC_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG));
+ status = wmi_cac_event_rx(wmip, datap, len);
+ break;
+ case (WMI_CHANNEL_CHANGE_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG));
+ status = wmi_channel_change_event_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_ROAM_DATA_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG));
+ status = wmi_roam_data_event_rx(wmip, datap, len);
+ break;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ case (WMI_TEST_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG));
+ status = wmi_tcmd_test_report_rx(wmip, datap, len);
+ break;
+#endif
+ case (WMI_GET_FIXRATES_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG));
+ status = wmi_ratemask_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_TX_RETRY_ERR_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
+ status = wmi_txRetryErrEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_SNR_THRESHOLD_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
+ status = wmi_snrThresholdEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_LQ_THRESHOLD_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
+ status = wmi_lqThresholdEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_APLIST_EVENTID):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
+ status = wmi_aplistEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_KEEPALIVE_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG));
+ status = wmi_keepalive_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_WOW_LIST_EVENTID):
+ status = wmi_get_wow_list_event_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_PMKID_LIST_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG));
+ status = wmi_get_pmkid_list_event_rx(wmip, datap, len);
+ break;
+ case (WMI_PSPOLL_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG));
+ status = wmi_pspoll_event_rx(wmip, datap, len);
+ break;
+ case (WMI_DTIMEXPIRY_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG));
+ status = wmi_dtimexpiry_event_rx(wmip, datap, len);
+ break;
+ case (WMI_SET_PARAMS_REPLY_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG));
+ status = wmi_set_params_event_rx(wmip, datap, len);
+ break;
+#ifdef ATH_AR6K_11N_SUPPORT
+ case (WMI_ADDBA_REQ_EVENTID):
+ status = wmi_addba_req_event_rx(wmip, datap, len);
+ break;
+ case (WMI_ADDBA_RESP_EVENTID):
+ status = wmi_addba_resp_event_rx(wmip, datap, len);
+ break;
+ case (WMI_DELBA_REQ_EVENTID):
+ status = wmi_delba_req_event_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_BTCOEX_CONFIG_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_CONFIG_EVENTID", DBGARG));
+ status = wmi_btcoex_config_event_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_BTCOEX_STATS_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_STATS_EVENTID", DBGARG));
+ status = wmi_btcoex_stats_event_rx(wmip, datap, len);
+ break;
+#endif
+ case (WMI_TX_COMPLETE_EVENTID):
+ {
+ int index;
+ TX_COMPLETE_MSG_V1 *pV1;
+ WMI_TX_COMPLETE_EVENT *pEv = (WMI_TX_COMPLETE_EVENT *)datap;
+ A_PRINTF("comp: %d %d %d\n", pEv->numMessages, pEv->msgLen, pEv->msgType);
+
+ for(index = 0 ; index < pEv->numMessages ; index++) {
+ pV1 = (TX_COMPLETE_MSG_V1 *)(datap + sizeof(WMI_TX_COMPLETE_EVENT) + index*sizeof(TX_COMPLETE_MSG_V1));
+ A_PRINTF("msg: %d %d %d %d\n", pV1->status, pV1->pktID, pV1->rateIdx, pV1->ackFailures);
+ }
+ }
+ break;
+ case (WMI_HCI_EVENT_EVENTID):
+ status = wmi_hci_event_rx(wmip, datap, len);
+ break;
+#ifdef WAPI_ENABLE
+ case (WMI_WAPI_REKEY_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_WAPI_REKEY_EVENTID", DBGARG));
+ status = wmi_wapi_rekey_event_rx(wmip, datap, len);
+ break;
+#endif
+ default:
+ A_DPRINTF(DBG_WMI|DBG_ERROR,
+ (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+ wmip->wmi_stats.cmd_id_err++;
+ status = A_ERROR;
+ break;
+ }
+
+ A_NETBUF_FREE(osbuf);
+
+ return status;
+}
+
+/* Send a "simple" wmi command -- one with no arguments */
+static A_STATUS
+wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG));
+}
+
+/* Send a "simple" extended wmi command -- one with no arguments.
+ Enabling this command only if GPIO or profiling support is enabled.
+ This is to suppress warnings on some platforms */
+#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT)
+static A_STATUS
+wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG));
+}
+#endif
+
+static A_STATUS
+wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
+
+ if (len < sizeof(WMI_READY_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+ wmip->wmi_ready = TRUE;
+ A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability,
+ ev->version);
+
+ return A_OK;
+}
+
+#define LE_READ_4(p) \
+ ((A_UINT32) \
+ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \
+ (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+ return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+
+static A_STATUS
+wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CONNECT_EVENT *ev;
+ A_UINT8 *pie,*peie;
+
+ if (len < sizeof(WMI_CONNECT_EVENT))
+ {
+ return A_EINVAL;
+ }
+ ev = (WMI_CONNECT_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+ DBGARG, ev->channel,
+ ev->bssid[0], ev->bssid[1], ev->bssid[2],
+ ev->bssid[3], ev->bssid[4], ev->bssid[5]));
+
+ A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
+
+ /* initialize pointer to start of assoc rsp IEs */
+ pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen +
+ sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16) + /* status Code */
+ sizeof(A_UINT16) ; /* associd */
+
+ /* initialize pointer to end of assoc rsp IEs */
+ peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen;
+
+ while (pie < peie)
+ {
+ switch (*pie)
+ {
+ case IEEE80211_ELEMID_VENDOR:
+ if (iswmmoui(pie))
+ {
+ if(iswmmparam (pie))
+ {
+ wmip->wmi_is_wmm_enabled = TRUE;
+ }
+ }
+ break;
+ }
+
+ if (wmip->wmi_is_wmm_enabled)
+ {
+ break;
+ }
+ pie += pie[1] + 2;
+ }
+
+ A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid,
+ ev->listenInterval, ev->beaconInterval,
+ (NETWORK_TYPE) ev->networkType, ev->beaconIeLen,
+ ev->assocReqLen, ev->assocRespLen,
+ ev->assocInfo);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_REG_DOMAIN_EVENT *ev;
+
+ if (len < sizeof(*ev)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_REG_DOMAIN_EVENT *)datap;
+
+ A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_NEIGHBOR_REPORT_EVENT *ev;
+ int numAps;
+
+ if (len < sizeof(*ev)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
+ numAps = ev->numberOfAps;
+
+ if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
+ return A_EINVAL;
+ }
+
+ A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_DISCONNECT_EVENT *ev;
+
+ if (len < sizeof(WMI_DISCONNECT_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ ev = (WMI_DISCONNECT_EVENT *)datap;
+
+ A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
+
+ wmip->wmi_is_wmm_enabled = FALSE;
+ wmip->wmi_pair_crypto_type = NONE_CRYPT;
+ wmip->wmi_grp_crypto_type = NONE_CRYPT;
+
+ A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
+ ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_PEER_NODE_EVENT *ev;
+
+ if (len < sizeof(WMI_PEER_NODE_EVENT)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_PEER_NODE_EVENT *)datap;
+ if (ev->eventCode == PEER_NODE_JOIN_EVENT) {
+ A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG));
+ } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) {
+ A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG));
+ }
+
+ A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TKIP_MICERR_EVENT *ev;
+
+ if (len < sizeof(*ev)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ ev = (WMI_TKIP_MICERR_EVENT *)datap;
+ A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ bss_t *bss = NULL;
+ WMI_BSS_INFO_HDR *bih;
+ A_UINT8 *buf;
+ A_UINT32 nodeCachingAllowed = 1;
+ A_UCHAR cached_ssid_len = 0;
+ A_UCHAR cached_ssid_buf[IEEE80211_NWID_LEN] = {0};
+ A_UINT8 beacon_ssid_len = 0;
+
+ if (len <= sizeof(WMI_BSS_INFO_HDR)) {
+ return A_EINVAL;
+ }
+
+ bih = (WMI_BSS_INFO_HDR *)datap;
+ bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+
+ if (bih->rssi > 0) {
+ if (NULL == bss)
+ return A_OK; //no node found in the table, just drop the node with incorrect RSSI
+ else
+ bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX
+ }
+
+ A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len);
+ /* What is driver config for wlan node caching? */
+ if(ar6000_get_driver_cfg(wmip->wmi_devt,
+ AR6000_DRIVER_CFG_GET_WLANNODECACHING,
+ &nodeCachingAllowed) != A_OK) {
+ return A_EINVAL;
+ }
+
+ if(!nodeCachingAllowed) {
+ return A_OK;
+ }
+
+ buf = datap + sizeof(WMI_BSS_INFO_HDR);
+ len -= sizeof(WMI_BSS_INFO_HDR);
+
+ A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, "
+ "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG,
+ bih->channel, (unsigned char) bih->rssi, bih->bssid[0],
+ bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4],
+ bih->bssid[5]));
+
+ if(wps_enable && (bih->frameType == PROBERESP_FTYPE) )
+ return A_OK;
+
+ if (bss != NULL) {
+ /*
+ * Free up the node. Not the most efficient process given
+ * we are about to allocate a new node but it is simple and should be
+ * adequate.
+ */
+
+ /* In case of hidden AP, beacon will not have ssid,
+ * but a directed probe response will have it,
+ * so cache the probe-resp-ssid if already present. */
+ if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType))
+ {
+ A_UCHAR *ie_ssid;
+
+ ie_ssid = bss->ni_cie.ie_ssid;
+ if(ie_ssid && (ie_ssid[1] <= IEEE80211_NWID_LEN) && (ie_ssid[2] != 0))
+ {
+ cached_ssid_len = ie_ssid[1];
+ memcpy(cached_ssid_buf, ie_ssid + 2, cached_ssid_len);
+ }
+ }
+
+ wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+ }
+
+ /* beacon/probe response frame format
+ * [8] time stamp
+ * [2] beacon interval
+ * [2] capability information
+ * [tlv] ssid */
+ beacon_ssid_len = buf[SSID_IE_LEN_INDEX];
+
+ /* If ssid is cached for this hidden AP, then change buffer len accordingly. */
+ if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) &&
+ (0 != cached_ssid_len) &&
+ (0 == beacon_ssid_len || (cached_ssid_len > beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1])))
+ {
+ len += (cached_ssid_len - beacon_ssid_len);
+ }
+
+ bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+ if (bss == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ bss->ni_snr = bih->snr;
+ bss->ni_rssi = bih->rssi;
+ A_ASSERT(bss->ni_buf != NULL);
+
+ /* In case of hidden AP, beacon will not have ssid,
+ * but a directed probe response will have it,
+ * so place the cached-ssid(probe-resp) in the bssinfo. */
+ if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) &&
+ (0 != cached_ssid_len) &&
+ (0 == beacon_ssid_len || (beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1])))
+ {
+ A_UINT8 *ni_buf = bss->ni_buf;
+ int buf_len = len;
+
+ /* copy the first 14 bytes such as
+ * time-stamp(8), beacon-interval(2), cap-info(2), ssid-id(1), ssid-len(1). */
+ A_MEMCPY(ni_buf, buf, SSID_IE_LEN_INDEX + 1);
+
+ ni_buf[SSID_IE_LEN_INDEX] = cached_ssid_len;
+ ni_buf += (SSID_IE_LEN_INDEX + 1);
+
+ buf += (SSID_IE_LEN_INDEX + 1);
+ buf_len -= (SSID_IE_LEN_INDEX + 1);
+
+ /* copy the cached ssid */
+ A_MEMCPY(ni_buf, cached_ssid_buf, cached_ssid_len);
+ ni_buf += cached_ssid_len;
+
+ buf += beacon_ssid_len;
+ buf_len -= beacon_ssid_len;
+
+ if (cached_ssid_len > beacon_ssid_len)
+ buf_len -= (cached_ssid_len - beacon_ssid_len);
+
+ /* now copy the rest of bytes */
+ A_MEMCPY(ni_buf, buf, buf_len);
+ }
+ else
+ A_MEMCPY(bss->ni_buf, buf, len);
+
+ bss->ni_framelen = len;
+ if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
+ wlan_node_free(bss);
+ return A_EINVAL;
+ }
+
+ /*
+ * Update the frequency in ie_chan, overwriting of channel number
+ * which is done in wlan_parse_beacon
+ */
+ bss->ni_cie.ie_chan = bih->channel;
+ wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ bss_t *bss;
+ WMI_OPT_RX_INFO_HDR *bih;
+ A_UINT8 *buf;
+
+ if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
+ return A_EINVAL;
+ }
+
+ bih = (WMI_OPT_RX_INFO_HDR *)datap;
+ buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
+ len -= sizeof(WMI_OPT_RX_INFO_HDR);
+
+ A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG,
+ bih->bssid[4], bih->bssid[5]));
+
+ bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+ if (bss != NULL) {
+ /*
+ * Free up the node. Not the most efficient process given
+ * we are about to allocate a new node but it is simple and should be
+ * adequate.
+ */
+ wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+ }
+
+ bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+ if (bss == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ bss->ni_snr = bih->snr;
+ bss->ni_cie.ie_chan = bih->channel;
+ A_ASSERT(bss->ni_buf != NULL);
+ A_MEMCPY(bss->ni_buf, buf, len);
+ wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+ return A_OK;
+}
+
+ /* This event indicates inactivity timeout of a fatpipe(pstream)
+ * at the target
+ */
+static A_STATUS
+wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_PSTREAM_TIMEOUT_EVENT *ev;
+
+ if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
+ return A_EINVAL;
+ }
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG));
+
+ ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
+
+ /* When the pstream (fat pipe == AC) timesout, it means there were no
+ * thinStreams within this pstream & it got implicitly created due to
+ * data flow on this AC. We start the inactivity timer only for
+ * implicitly created pstream. Just reset the host state.
+ */
+ /* Set the activeTsids for this AC to 0 */
+ LOCK_WMI(wmip);
+ wmip->wmi_streamExistsForAC[ev->trafficClass]=0;
+ wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass);
+ UNLOCK_WMI(wmip);
+
+ /*Indicate inactivity to driver layer for this fatpipe (pstream)*/
+ A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_BIT_RATE_REPLY *reply;
+ A_INT32 rate;
+ A_UINT32 sgi,index;
+ /* 54149:
+ * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY.
+ * since there is difference in the length and to avoid returning
+ * error value.
+ */
+ if (len < sizeof(WMI_BIT_RATE_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_BIT_RATE_REPLY *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex));
+
+ if (reply->rateIndex == (A_INT8) RATE_AUTO) {
+ rate = RATE_AUTO;
+ } else {
+ // the SGI state is stored as the MSb of the rateIndex
+ index = reply->rateIndex & 0x7f;
+ sgi = (reply->rateIndex & 0x80)? 1:0;
+ rate = wmi_rateTable[index][sgi];
+ }
+
+ A_WMI_BITRATE_RX(wmip->wmi_devt, rate);
+ return A_OK;
+}
+
+static A_STATUS
+wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_FIX_RATES_REPLY *reply;
+
+ if (len < sizeof(WMI_FIX_RATES_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_FIX_RATES_REPLY *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask));
+
+ A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CHANNEL_LIST_REPLY *reply;
+
+ if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_CHANNEL_LIST_REPLY *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels,
+ reply->channelList);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TX_PWR_REPLY *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TX_PWR_REPLY *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM);
+
+ return A_OK;
+}
+static A_STATUS
+wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_GET_KEEPALIVE_CMD *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_GET_KEEPALIVE_CMD *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured);
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_DSETOPENREQ_EVENT *dsetopenreq;
+
+ if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
+ return A_EINVAL;
+ }
+ dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id));
+ A_WMI_DSET_OPEN_REQ(wmip->wmi_devt,
+ dsetopenreq->dset_id,
+ dsetopenreq->targ_dset_handle,
+ dsetopenreq->targ_reply_fn,
+ dsetopenreq->targ_reply_arg);
+
+ return A_OK;
+}
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS
+wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_DSETCLOSE_EVENT *dsetclose;
+
+ if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
+ A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_DSETDATAREQ_EVENT *dsetdatareq;
+
+ if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
+ A_WMI_DSET_DATA_REQ(wmip->wmi_devt,
+ dsetdatareq->access_cookie,
+ dsetdatareq->offset,
+ dsetdatareq->length,
+ dsetdatareq->targ_buf,
+ dsetdatareq->targ_reply_fn,
+ dsetdatareq->targ_reply_arg);
+
+ return A_OK;
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+static A_STATUS
+wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_SCAN_COMPLETE_EVENT *ev;
+
+ ev = (WMI_SCAN_COMPLETE_EVENT *)datap;
+ A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status);
+ is_probe_ssid = FALSE;
+
+ return A_OK;
+}
+
+/*
+ * Target is reporting a programming error. This is for
+ * developer aid only. Target only checks a few common violations
+ * and it is responsibility of host to do all error checking.
+ * Behavior of target after wmi error event is undefined.
+ * A reset is recommended.
+ */
+static A_STATUS
+wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CMD_ERROR_EVENT *ev;
+
+ ev = (WMI_CMD_ERROR_EVENT *)datap;
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId));
+ switch (ev->errorCode) {
+ case (INVALID_PARAM):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n"));
+ break;
+ case (ILLEGAL_STATE):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n"));
+ break;
+ case (INTERNAL_ERROR):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n"));
+ break;
+ }
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, datap, len);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_RSSI_THRESHOLD_EVENT *reply;
+ WMI_RSSI_THRESHOLD_VAL newThreshold;
+ WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+ SQ_THRESHOLD_PARAMS *sq_thresh =
+ &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI];
+ A_UINT8 upper_rssi_threshold, lower_rssi_threshold;
+ A_INT16 rssi;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+ newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range;
+ rssi = reply->rssi;
+
+ /*
+ * Identify the threshold breached and communicate that to the app. After
+ * that install a new set of thresholds based on the signal quality
+ * reported by the target
+ */
+ if (newThreshold) {
+ /* Upper threshold breached */
+ if (rssi < sq_thresh->upper_threshold[0]) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: "
+ " %d\n", DBGARG, rssi));
+ } else if ((rssi < sq_thresh->upper_threshold[1]) &&
+ (rssi >= sq_thresh->upper_threshold[0]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD1_ABOVE;
+ } else if ((rssi < sq_thresh->upper_threshold[2]) &&
+ (rssi >= sq_thresh->upper_threshold[1]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD2_ABOVE;
+ } else if ((rssi < sq_thresh->upper_threshold[3]) &&
+ (rssi >= sq_thresh->upper_threshold[2]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD3_ABOVE;
+ } else if ((rssi < sq_thresh->upper_threshold[4]) &&
+ (rssi >= sq_thresh->upper_threshold[3]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD4_ABOVE;
+ } else if ((rssi < sq_thresh->upper_threshold[5]) &&
+ (rssi >= sq_thresh->upper_threshold[4]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD5_ABOVE;
+ } else if (rssi >= sq_thresh->upper_threshold[5]) {
+ newThreshold = WMI_RSSI_THRESHOLD6_ABOVE;
+ }
+ } else {
+ /* Lower threshold breached */
+ if (rssi > sq_thresh->lower_threshold[0]) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: "
+ "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0]));
+ } else if ((rssi > sq_thresh->lower_threshold[1]) &&
+ (rssi <= sq_thresh->lower_threshold[0]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD6_BELOW;
+ } else if ((rssi > sq_thresh->lower_threshold[2]) &&
+ (rssi <= sq_thresh->lower_threshold[1]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD5_BELOW;
+ } else if ((rssi > sq_thresh->lower_threshold[3]) &&
+ (rssi <= sq_thresh->lower_threshold[2]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD4_BELOW;
+ } else if ((rssi > sq_thresh->lower_threshold[4]) &&
+ (rssi <= sq_thresh->lower_threshold[3]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD3_BELOW;
+ } else if ((rssi > sq_thresh->lower_threshold[5]) &&
+ (rssi <= sq_thresh->lower_threshold[4]))
+ {
+ newThreshold = WMI_RSSI_THRESHOLD2_BELOW;
+ } else if (rssi <= sq_thresh->lower_threshold[5]) {
+ newThreshold = WMI_RSSI_THRESHOLD1_BELOW;
+ }
+ }
+ /* Calculate and install the next set of thresholds */
+ lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh,
+ sq_thresh->lower_threshold_valid_count);
+ upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh,
+ sq_thresh->upper_threshold_valid_count);
+ /* Issue a wmi command to install the thresholds */
+ cmd.thresholdAbove1_Val = upper_rssi_threshold;
+ cmd.thresholdBelow1_Val = lower_rssi_threshold;
+ cmd.weight = sq_thresh->weight;
+ cmd.pollTime = sq_thresh->polling_interval;
+
+ rssi_event_value = rssi;
+
+ if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n",
+ DBGARG));
+ }
+
+ A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi);
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_ERROR_REPORT_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CAC_EVENT *reply;
+ WMM_TSPEC_IE *tspec_ie;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_CAC_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) &&
+ (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) {
+ tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion);
+
+ wmi_delete_pstream_cmd(wmip, reply->ac,
+ (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK);
+ }
+ else if (reply->cac_indication == CAC_INDICATION_NO_RESP) {
+ A_UINT16 activeTsids;
+ A_UINT8 i;
+
+ /* following assumes that there is only one outstanding ADDTS request
+ when this event is received */
+ LOCK_WMI(wmip);
+ activeTsids = wmip->wmi_streamExistsForAC[reply->ac];
+ UNLOCK_WMI(wmip);
+
+ for (i = 0; i < sizeof(activeTsids) * 8; i++) {
+ if ((activeTsids >> i) & 1) {
+ break;
+ }
+ }
+ if (i < (sizeof(activeTsids) * 8)) {
+ wmi_delete_pstream_cmd(wmip, reply->ac, i);
+ }
+ }
+
+ A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac,
+ reply->cac_indication, reply->statusCode,
+ reply->tspecSuggestion);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CHANNEL_CHANGE_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_CHANNEL_CHANGE_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel,
+ reply->newChannel);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_HB_CHALLENGE_RESP_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG));
+
+ A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_ROAM_TBL *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_ROAM_TBL *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_ROAM_DATA *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_ROAM_DATA *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_SNR_THRESHOLD_EVENT *reply;
+ SQ_THRESHOLD_PARAMS *sq_thresh =
+ &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR];
+ WMI_SNR_THRESHOLD_VAL newThreshold;
+ WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+ A_UINT8 upper_snr_threshold, lower_snr_threshold;
+ A_INT16 snr;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_SNR_THRESHOLD_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range;
+ snr = reply->snr;
+ /*
+ * Identify the threshold breached and communicate that to the app. After
+ * that install a new set of thresholds based on the signal quality
+ * reported by the target
+ */
+ if (newThreshold) {
+ /* Upper threshold breached */
+ if (snr < sq_thresh->upper_threshold[0]) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: "
+ "%d\n", DBGARG, snr));
+ } else if ((snr < sq_thresh->upper_threshold[1]) &&
+ (snr >= sq_thresh->upper_threshold[0]))
+ {
+ newThreshold = WMI_SNR_THRESHOLD1_ABOVE;
+ } else if ((snr < sq_thresh->upper_threshold[2]) &&
+ (snr >= sq_thresh->upper_threshold[1]))
+ {
+ newThreshold = WMI_SNR_THRESHOLD2_ABOVE;
+ } else if ((snr < sq_thresh->upper_threshold[3]) &&
+ (snr >= sq_thresh->upper_threshold[2]))
+ {
+ newThreshold = WMI_SNR_THRESHOLD3_ABOVE;
+ } else if (snr >= sq_thresh->upper_threshold[3]) {
+ newThreshold = WMI_SNR_THRESHOLD4_ABOVE;
+ }
+ } else {
+ /* Lower threshold breached */
+ if (snr > sq_thresh->lower_threshold[0]) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: "
+ "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0]));
+ } else if ((snr > sq_thresh->lower_threshold[1]) &&
+ (snr <= sq_thresh->lower_threshold[0]))
+ {
+ newThreshold = WMI_SNR_THRESHOLD4_BELOW;
+ } else if ((snr > sq_thresh->lower_threshold[2]) &&
+ (snr <= sq_thresh->lower_threshold[1]))
+ {
+ newThreshold = WMI_SNR_THRESHOLD3_BELOW;
+ } else if ((snr > sq_thresh->lower_threshold[3]) &&
+ (snr <= sq_thresh->lower_threshold[2]))
+ {
+ newThreshold = WMI_SNR_THRESHOLD2_BELOW;
+ } else if (snr <= sq_thresh->lower_threshold[3]) {
+ newThreshold = WMI_SNR_THRESHOLD1_BELOW;
+ }
+ }
+
+ /* Calculate and install the next set of thresholds */
+ lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh,
+ sq_thresh->lower_threshold_valid_count);
+ upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh,
+ sq_thresh->upper_threshold_valid_count);
+
+ /* Issue a wmi command to install the thresholds */
+ cmd.thresholdAbove1_Val = upper_snr_threshold;
+ cmd.thresholdBelow1_Val = lower_snr_threshold;
+ cmd.weight = sq_thresh->weight;
+ cmd.pollTime = sq_thresh->polling_interval;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n"
+ ,DBGARG, snr, newThreshold, lower_snr_threshold,
+ upper_snr_threshold));
+
+ snr_event_value = snr;
+
+ if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n",
+ DBGARG));
+ }
+ A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_LQ_THRESHOLD_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_LQ_THRESHOLD_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt,
+ (WMI_LQ_THRESHOLD_VAL) reply->range,
+ reply->lq);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_UINT16 ap_info_entry_size;
+ WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap;
+ WMI_AP_INFO_V1 *ap_info_v1;
+ A_UINT8 i;
+
+ if (len < sizeof(WMI_APLIST_EVENT)) {
+ return A_EINVAL;
+ }
+
+ if (ev->apListVer == APLIST_VER1) {
+ ap_info_entry_size = sizeof(WMI_AP_INFO_V1);
+ ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList;
+ } else {
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP));
+ if (len < (int)(sizeof(WMI_APLIST_EVENT) +
+ (ev->numAP - 1) * ap_info_entry_size))
+ {
+ return A_EINVAL;
+ }
+
+ /*
+ * AP List Ver1 Contents
+ */
+ for (i = 0; i < ev->numAP; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\
+ "Channel %d\n", i,
+ ap_info_v1->bssid[0], ap_info_v1->bssid[1],
+ ap_info_v1->bssid[2], ap_info_v1->bssid[3],
+ ap_info_v1->bssid[4], ap_info_v1->bssid[5],
+ ap_info_v1->channel));
+ ap_info_v1++;
+ }
+ return A_OK;
+}
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_UINT32 dropped;
+
+ dropped = *((A_UINT32 *)datap);
+ datap += sizeof(dropped);
+ len -= sizeof(dropped);
+ A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, (A_INT8*)datap, len);
+ return A_OK;
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS
+wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
+ gpio_intr->intr_mask, gpio_intr->input_values));
+
+ A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
+ gpio_data->reg_id, gpio_data->value));
+
+ A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_GPIO_ACK_RX();
+
+ return A_OK;
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+/*
+ * Called to send a wmi command. Command specific data is already built
+ * on osbuf and current osbuf->data points to it.
+ */
+A_STATUS
+wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG syncflag)
+{
+ A_STATUS status;
+#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID))
+ WMI_CMD_HDR *cHdr;
+ HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id;
+
+ A_ASSERT(osbuf != NULL);
+
+ if (syncflag >= END_WMIFLAG) {
+ A_NETBUF_FREE(osbuf);
+ return A_EINVAL;
+ }
+
+ if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+ /*
+ * We want to make sure all data currently queued is transmitted before
+ * the cmd execution. Establish a new sync point.
+ */
+ wmi_sync_point(wmip);
+ }
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+ A_NETBUF_FREE(osbuf);
+ return A_NO_MEMORY;
+ }
+
+ cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ cHdr->commandId = (A_UINT16) cmdId;
+ cHdr->info1 = 0; // added for virtual interface
+
+ /*
+ * Only for OPT_TX_CMD, use BE endpoint.
+ */
+ if (IS_OPT_TX_CMD(cmdId)) {
+ if ((status=wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE, FALSE,0,NULL)) != A_OK) {
+ A_NETBUF_FREE(osbuf);
+ return status;
+ }
+ eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE);
+ }
+ A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid);
+
+ if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+ /*
+ * We want to make sure all new data queued waits for the command to
+ * execute. Establish a new sync point.
+ */
+ wmi_sync_point(wmip);
+ }
+ return (A_OK);
+#undef IS_OPT_TX_CMD
+}
+
+A_STATUS
+wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG syncflag)
+{
+ WMIX_CMD_HDR *cHdr;
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+ A_NETBUF_FREE(osbuf);
+ return A_NO_MEMORY;
+ }
+
+ cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ cHdr->commandId = (A_UINT32) cmdId;
+
+ return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
+}
+
+A_STATUS
+wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
+ DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
+ CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
+ CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen,
+ int ssidLength, A_UCHAR *ssid,
+ A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags)
+{
+ void *osbuf;
+ WMI_CONNECT_CMD *cc;
+
+ if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
+ return A_EINVAL;
+ }
+ if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD));
+
+ cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cc, sizeof(*cc));
+
+ if (ssidLength)
+ {
+ A_MEMCPY(cc->ssid, ssid, ssidLength);
+ }
+
+ cc->ssidLength = ssidLength;
+ cc->networkType = netType;
+ cc->dot11AuthMode = dot11AuthMode;
+ cc->authMode = authMode;
+ cc->pairwiseCryptoType = pairwiseCrypto;
+ cc->pairwiseCryptoLen = pairwiseCryptoLen;
+ cc->groupCryptoType = groupCrypto;
+ cc->groupCryptoLen = groupCryptoLen;
+ cc->channel = channel;
+ cc->ctrl_flags = ctrl_flags;
+
+ if (bssid != NULL) {
+ A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+ }
+
+ wmip->wmi_pair_crypto_type = pairwiseCrypto;
+ wmip->wmi_grp_crypto_type = groupCrypto;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
+{
+ void *osbuf;
+ WMI_RECONNECT_CMD *cc;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD));
+
+ cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cc, sizeof(*cc));
+
+ cc->channel = channel;
+
+ if (bssid != NULL) {
+ A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disconnect_cmd(struct wmi_t *wmip)
+{
+ A_STATUS status;
+
+ /* Bug fix for 24817(elevator bug) - the disconnect command does not
+ need to do a SYNC before.*/
+ status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID);
+
+ return status;
+}
+
+A_STATUS
+wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+ A_BOOL forceFgScan, A_BOOL isLegacy,
+ A_UINT32 homeDwellTime, A_UINT32 forceScanInterval,
+ A_INT8 numChan, A_UINT16 *channelList)
+{
+ void *osbuf;
+ WMI_START_SCAN_CMD *sc;
+ A_INT8 size;
+
+ size = sizeof (*sc);
+
+ if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
+ return A_EINVAL;
+ }
+
+ if (numChan) {
+ if (numChan > WMI_MAX_CHANNELS) {
+ return A_EINVAL;
+ }
+ size += sizeof(A_UINT16) * (numChan - 1);
+ }
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf));
+ sc->scanType = scanType;
+ sc->forceFgScan = forceFgScan;
+ sc->isLegacy = isLegacy;
+ sc->homeDwellTime = homeDwellTime;
+ sc->forceScanInterval = forceScanInterval;
+ sc->numChannels = numChan;
+ if (numChan) {
+ A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16));
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+ A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+ A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec,
+ A_UINT16 pas_chdw_msec,
+ A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+ A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid)
+{
+ void *osbuf;
+ WMI_SCAN_PARAMS_CMD *sc;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*sc));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*sc));
+
+ sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(sc, sizeof(*sc));
+ sc->fg_start_period = fg_start_sec;
+ sc->fg_end_period = fg_end_sec;
+ sc->bg_period = bg_sec;
+ sc->minact_chdwell_time = minact_chdw_msec;
+ sc->maxact_chdwell_time = maxact_chdw_msec;
+ sc->pas_chdwell_time = pas_chdw_msec;
+ sc->shortScanRatio = shScanRatio;
+ sc->scanCtrlFlags = scanCtrlFlags;
+ sc->max_dfsch_act_time = max_dfsch_act_time;
+ sc->maxact_scan_per_ssid = maxact_scan_per_ssid;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask)
+{
+ void *osbuf;
+ WMI_BSS_FILTER_CMD *cmd;
+
+ if (filter >= LAST_BSS_FILTER) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->bssFilter = filter;
+ cmd->ieMask = ieMask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+ A_UINT8 ssidLength, A_UCHAR *ssid)
+{
+ void *osbuf;
+ WMI_PROBED_SSID_CMD *cmd;
+
+ if (index > MAX_PROBED_SSID_INDEX) {
+ return A_EINVAL;
+ }
+ if (ssidLength > sizeof(cmd->ssid)) {
+ return A_EINVAL;
+ }
+ if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
+ return A_EINVAL;
+ }
+ if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
+ return A_EINVAL;
+ }
+
+ if (flag & SPECIFIC_SSID_FLAG) {
+ is_probe_ssid = TRUE;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->entryIndex = index;
+ cmd->flag = flag;
+ cmd->ssidLength = ssidLength;
+ A_MEMCPY(cmd->ssid, ssid, ssidLength);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
+{
+ void *osbuf;
+ WMI_LISTEN_INT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->listenInterval = listenInterval;
+ cmd->numBeacons = listenBeacons;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
+{
+ void *osbuf;
+ WMI_BMISS_TIME_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->bmissTime = bmissTime;
+ cmd->numBeacons = bmissBeacons;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+ A_UINT8 ieLen, A_UINT8 *ieInfo)
+{
+ void *osbuf;
+ WMI_SET_ASSOC_INFO_CMD *cmd;
+ A_UINT16 cmdLen;
+
+ cmdLen = sizeof(*cmd) + ieLen - 1;
+ osbuf = A_NETBUF_ALLOC(cmdLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, cmdLen);
+
+ cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, cmdLen);
+ cmd->ieType = ieType;
+ cmd->bufferSize = ieLen;
+ A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
+{
+ void *osbuf;
+ WMI_POWER_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->powerMode = powerMode;
+ wmip->wmi_powerMode = powerMode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+ A_UINT16 atim_windows, A_UINT16 timeout_value)
+{
+ void *osbuf;
+ WMI_IBSS_PM_CAPS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->power_saving = pmEnable;
+ cmd->ttl = ttl;
+ cmd->atim_windows = atim_windows;
+ cmd->timeout_value = timeout_value;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time,
+ A_UINT32 ps_period, A_UINT8 sleep_period)
+{
+ void *osbuf;
+ WMI_AP_PS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_AP_PS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->psType = psType;
+ cmd->idle_time = idle_time;
+ cmd->ps_period = ps_period;
+ cmd->sleep_period = sleep_period;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_AP_PS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+ A_UINT16 psPollNum, A_UINT16 dtimPolicy,
+ A_UINT16 tx_wakeup_policy, A_UINT16 num_tx_to_wakeup,
+ A_UINT16 ps_fail_event_policy)
+{
+ void *osbuf;
+ WMI_POWER_PARAMS_CMD *pm;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*pm));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*pm));
+
+ pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(pm, sizeof(*pm));
+ pm->idle_period = idlePeriod;
+ pm->pspoll_number = psPollNum;
+ pm->dtim_policy = dtimPolicy;
+ pm->tx_wakeup_policy = tx_wakeup_policy;
+ pm->num_tx_to_wakeup = num_tx_to_wakeup;
+ pm->ps_fail_event_policy = ps_fail_event_policy;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
+{
+ void *osbuf;
+ WMI_DISC_TIMEOUT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->disconnectTimeout = timeout;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
+ A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
+ A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr,
+ WMI_SYNC_FLAG sync_flag)
+{
+ void *osbuf;
+ WMI_ADD_CIPHER_KEY_CMD *cmd;
+
+ if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
+ (keyMaterial == NULL))
+ {
+ return A_EINVAL;
+ }
+
+ if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->keyIndex = keyIndex;
+ cmd->keyType = keyType;
+ cmd->keyUsage = keyUsage;
+ cmd->keyLength = keyLength;
+ A_MEMCPY(cmd->key, keyMaterial, keyLength);
+#ifdef WAPI_ENABLE
+ if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) {
+#else
+ if (NULL != keyRSC) {
+#endif // WAPI_ENABLE
+ A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
+ }
+ cmd->key_op_ctrl = key_op_ctrl;
+
+ if(macAddr) {
+ A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
+}
+
+A_STATUS
+wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
+{
+ void *osbuf;
+ WMI_ADD_KRK_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_krk_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID);
+}
+
+A_STATUS
+wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
+{
+ void *osbuf;
+ WMI_DELETE_CIPHER_KEY_CMD *cmd;
+
+ if (keyIndex > WMI_MAX_KEY_INDEX) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->keyIndex = keyIndex;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+ A_BOOL set)
+{
+ void *osbuf;
+ WMI_SET_PMKID_CMD *cmd;
+
+ if (bssid == NULL) {
+ return A_EINVAL;
+ }
+
+ if ((set == TRUE) && (pmkId == NULL)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+ if (set == TRUE) {
+ A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
+ cmd->enable = PMKID_ENABLE;
+ } else {
+ A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
+ cmd->enable = PMKID_DISABLE;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
+{
+ void *osbuf;
+ WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+ WMI_SET_AKMP_PARAMS_CMD *akmpParams)
+{
+ void *osbuf;
+ WMI_SET_AKMP_PARAMS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->akmpInfo = akmpParams->akmpInfo;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+ WMI_SET_PMKID_LIST_CMD *pmkInfo)
+{
+ void *osbuf;
+ WMI_SET_PMKID_LIST_CMD *cmd;
+ A_UINT16 cmdLen;
+ A_UINT8 i;
+
+ cmdLen = sizeof(pmkInfo->numPMKID) +
+ pmkInfo->numPMKID * sizeof(WMI_PMKID);
+
+ osbuf = A_NETBUF_ALLOC(cmdLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, cmdLen);
+ cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->numPMKID = pmkInfo->numPMKID;
+
+ for (i = 0; i < cmd->numPMKID; i++) {
+ A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i],
+ WMI_PMKID_LEN);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_pmkid_list_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID);
+}
+
+A_STATUS
+wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid)
+{
+ WMI_DATA_HDR *dtHdr;
+
+ A_ASSERT( eid != wmip->wmi_endpoint_id);
+ A_ASSERT(osbuf != NULL);
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+ dtHdr->info =
+ (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid));
+
+ return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid));
+}
+
+typedef struct _WMI_DATA_SYNC_BUFS {
+ A_UINT8 trafficClass;
+ void *osbuf;
+}WMI_DATA_SYNC_BUFS;
+
+static A_STATUS
+wmi_sync_point(struct wmi_t *wmip)
+{
+ void *cmd_osbuf;
+ WMI_SYNC_CMD *cmd;
+ WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC];
+ A_UINT8 i,numPriStreams=0;
+ A_STATUS status = A_OK;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ memset(dataSyncBufs,0,sizeof(dataSyncBufs));
+
+ /* lock out while we walk through the priority list and assemble our local array */
+ LOCK_WMI(wmip);
+
+ for (i=0; i < WMM_NUM_AC ; i++) {
+ if (wmip->wmi_fatPipeExists & (1 << i)) {
+ numPriStreams++;
+ dataSyncBufs[numPriStreams-1].trafficClass = i;
+ }
+ }
+
+ UNLOCK_WMI(wmip);
+
+ /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */
+
+ do {
+ /*
+ * We allocate all network buffers needed so we will be able to
+ * send all required frames.
+ */
+ cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (cmd_osbuf == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ /* In the SYNC cmd sent on the control Ep, send a bitmap of the data
+ * eps on which the Data Sync will be sent
+ */
+ cmd->dataSyncMap = wmip->wmi_fatPipeExists;
+
+ for (i=0; i < numPriStreams ; i++) {
+ dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0);
+ if (dataSyncBufs[i].osbuf == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+ } //end for
+
+ /* if Buffer allocation for any of the dataSync fails, then do not
+ * send the Synchronize cmd on the control ep
+ */
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /*
+ * Send sync cmd followed by sync data messages on all endpoints being
+ * used
+ */
+ status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
+ NO_SYNC_WMIFLAG);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* cmd buffer sent, we no longer own it */
+ cmd_osbuf = NULL;
+
+ for(i=0; i < numPriStreams; i++) {
+ A_ASSERT(dataSyncBufs[i].osbuf != NULL);
+ status = wmi_dataSync_send(wmip,
+ dataSyncBufs[i].osbuf,
+ A_WMI_Ac2EndpointID(wmip->wmi_devt,
+ dataSyncBufs[i].
+ trafficClass)
+ );
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* we don't own this buffer anymore, NULL it out of the array so it
+ * won't get cleaned up */
+ dataSyncBufs[i].osbuf = NULL;
+ } //end for
+
+ } while(FALSE);
+
+ /* free up any resources left over (possibly due to an error) */
+
+ if (cmd_osbuf != NULL) {
+ A_NETBUF_FREE(cmd_osbuf);
+ }
+
+ for (i = 0; i < numPriStreams; i++) {
+ if (dataSyncBufs[i].osbuf != NULL) {
+ A_NETBUF_FREE(dataSyncBufs[i].osbuf);
+ }
+ }
+
+ return (status);
+}
+
+A_STATUS
+wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
+{
+ void *osbuf;
+ WMI_CREATE_PSTREAM_CMD *cmd;
+ A_UINT8 fatPipeExistsForAC=0;
+ A_INT32 minimalPHY = 0;
+ A_INT32 nominalPHY = 0;
+
+ /* Validate all the parameters. */
+ if( !((params->userPriority < 8) &&
+ (params->userPriority <= 0x7) &&
+ (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) &&
+ (params->trafficDirection == UPLINK_TRAFFIC ||
+ params->trafficDirection == DNLINK_TRAFFIC ||
+ params->trafficDirection == BIDIR_TRAFFIC) &&
+ (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
+ params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
+ (params->voicePSCapability == DISABLE_FOR_THIS_AC ||
+ params->voicePSCapability == ENABLE_FOR_THIS_AC ||
+ params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
+ (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) )
+ {
+ return A_EINVAL;
+ }
+
+ //
+ // check nominal PHY rate is >= minimalPHY, so that DUT
+ // can allow TSRS IE
+ //
+
+ // get the physical rate
+ minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps
+
+ // check minimal phy < nominal phy rate
+ //
+ if (params->nominalPHY >= minimalPHY)
+ {
+ nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG,
+ minimalPHY, nominalPHY));
+
+ params->nominalPHY = nominalPHY;
+ }
+ else
+ {
+ params->nominalPHY = 0;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG,
+ params->trafficClass, params->tsid));
+
+ cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ A_MEMCPY(cmd, params, sizeof(*cmd));
+
+ /* this is an implicitly created Fat pipe */
+ if ((A_UINT32)params->tsid == (A_UINT32)WMI_IMPLICIT_PSTREAM) {
+ LOCK_WMI(wmip);
+ fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+ wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+ UNLOCK_WMI(wmip);
+ } else {
+ /* this is an explicitly created thin stream within a fat pipe */
+ LOCK_WMI(wmip);
+ fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+ wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<<params->tsid);
+ /* if a thinstream becomes active, the fat pipe automatically
+ * becomes active
+ */
+ wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+ UNLOCK_WMI(wmip);
+ }
+
+ /* Indicate activty change to driver layer only if this is the
+ * first TSID to get created in this AC explicitly or an implicit
+ * fat pipe is getting created.
+ */
+ if (!fatPipeExistsForAC) {
+ A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass);
+ }
+
+ /* mike: should be SYNC_BEFORE_WMIFLAG */
+ return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid)
+{
+ void *osbuf;
+ WMI_DELETE_PSTREAM_CMD *cmd;
+ A_STATUS status;
+ A_UINT16 activeTsids=0;
+
+ /* validate the parameters */
+ if (trafficClass > 3) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass));
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->trafficClass = trafficClass;
+ cmd->tsid = tsid;
+
+ LOCK_WMI(wmip);
+ activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+ UNLOCK_WMI(wmip);
+
+ /* Check if the tsid was created & exists */
+ if (!(activeTsids & (1<<tsid))) {
+
+ A_NETBUF_FREE(osbuf);
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "TSID %d does'nt exist for trafficClass: %d\n", DBGARG, tsid, trafficClass));
+ /* TODO: return a more appropriate err code */
+ return A_ERROR;
+ }
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Sending delete_pstream_cmd: trafficClass: %d tsid=%d\n", DBGARG, trafficClass, tsid));
+
+ status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
+ SYNC_BEFORE_WMIFLAG));
+
+ LOCK_WMI(wmip);
+ wmip->wmi_streamExistsForAC[trafficClass] &= ~(1<<tsid);
+ activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+ UNLOCK_WMI(wmip);
+
+
+ /* Indicate stream inactivity to driver layer only if all tsids
+ * within this AC are deleted.
+ */
+ if(!activeTsids) {
+ A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass);
+ wmip->wmi_fatPipeExists &= ~(1<<trafficClass);
+ }
+
+ return status;
+}
+
+A_STATUS
+wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask)
+{
+ void *osbuf;
+ WMI_FRAME_RATES_CMD *cmd;
+ A_UINT8 frameType;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT " type %02X, subType %02X, rateMask %04x\n", DBGARG, type, subType, rateMask));
+
+ if((type != IEEE80211_FRAME_TYPE_MGT && type != IEEE80211_FRAME_TYPE_CTL) ||
+ (subType > 15)){
+
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ frameType = (A_UINT8)((subType << 4) | type);
+
+ cmd->bEnableMask = bEnable;
+ cmd->frameType = frameType;
+ cmd->frameRateMask = rateMask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * used to set the bit rate. rate is in Kbps. If rate == -1
+ * then auto selection is used.
+ */
+A_STATUS
+wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate)
+{
+ void *osbuf;
+ WMI_BIT_RATE_CMD *cmd;
+ A_INT8 drix, mrix, crix;
+
+ if (dataRate != -1) {
+ drix = wmi_validate_bitrate(wmip, dataRate);
+ if(drix == A_EINVAL){
+ return A_EINVAL;
+ }
+ } else {
+ drix = -1;
+ }
+
+ if (mgmtRate != -1) {
+ mrix = wmi_validate_bitrate(wmip, mgmtRate);
+ if(mrix == A_EINVAL){
+ return A_EINVAL;
+ }
+ } else {
+ mrix = -1;
+ }
+ if (ctlRate != -1) {
+ crix = wmi_validate_bitrate(wmip, ctlRate);
+ if(crix == A_EINVAL){
+ return A_EINVAL;
+ }
+ } else {
+ crix = -1;
+ }
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->rateIndex = drix;
+ cmd->mgmtRateIndex = mrix;
+ cmd->ctlRateIndex = crix;
+
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_bitrate_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID);
+}
+
+/*
+ * Returns TRUE iff the given rate index is legal in the current PHY mode.
+ */
+A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex)
+{
+ WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode;
+ A_BOOL isValid = TRUE;
+ switch(phyMode) {
+ case WMI_11A_MODE:
+ if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ case WMI_11B_MODE:
+ if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ case WMI_11GONLY_MODE:
+ if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ case WMI_11G_MODE:
+ case WMI_11AG_MODE:
+ if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+ default:
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ return isValid;
+}
+
+A_INT8
+wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate)
+{
+ A_INT8 i;
+ if (rate != -1)
+ {
+ for (i=0;;i++)
+ {
+ if (wmi_rateTable[(A_UINT32) i][0] == 0) {
+ return A_EINVAL;
+ }
+ if (wmi_rateTable[(A_UINT32) i][0] == rate) {
+ break;
+ }
+ }
+ }
+ else{
+ i = -1;
+ }
+
+ if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) {
+ return A_EINVAL;
+ }
+
+ return i;
+}
+
+A_STATUS
+wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask)
+{
+ void *osbuf;
+ WMI_FIX_RATES_CMD *cmd;
+#if 0
+ A_INT32 rateIndex;
+/* This check does not work for AR6003 as the HT modes are enabled only when
+ * the STA is connected to a HT_BSS and is not based only on channel. It is
+ * safe to skip this check however because rate control will only use rates
+ * that are permitted by the valid rate mask and the fix rate mask. Meaning
+ * the fix rate mask is not sufficient by itself to cause an invalid rate
+ * to be used. */
+ /* Make sure all rates in the mask are valid in the current PHY mode */
+ for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) {
+ if((1 << rateIndex) & (A_UINT32)fixRatesMask) {
+ if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG));
+ return A_EINVAL;
+ }
+ }
+ }
+#endif
+
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->fixRateMask = fixRatesMask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_ratemask_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID);
+}
+
+A_STATUS
+wmi_get_channelList_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID);
+}
+
+/*
+ * used to generate a wmi sey channel Parameters cmd.
+ * mode should always be specified and corresponds to the phy mode of the
+ * wlan.
+ * numChan should alway sbe specified. If zero indicates that all available
+ * channels should be used.
+ * channelList is an array of channel frequencies (in Mhz) which the radio
+ * should limit its operation to. It should be NULL if numChan == 0. Size of
+ * array should correspond to numChan entries.
+ */
+A_STATUS
+wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+ WMI_PHY_MODE mode, A_INT8 numChan,
+ A_UINT16 *channelList)
+{
+ void *osbuf;
+ WMI_CHANNEL_PARAMS_CMD *cmd;
+ A_INT8 size;
+
+ size = sizeof (*cmd);
+
+ if (numChan) {
+ if (numChan > WMI_MAX_CHANNELS) {
+ return A_EINVAL;
+ }
+ size += sizeof(A_UINT16) * (numChan - 1);
+ }
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ wmip->wmi_phyMode = mode;
+ cmd->scanParam = scanParam;
+ cmd->phyMode = mode;
+ cmd->numChannels = numChan;
+ A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+ SQ_THRESHOLD_PARAMS *sq_thresh =
+ &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI];
+ /*
+ * Parse the command and store the threshold values here. The checks
+ * for valid values can be put here
+ */
+ sq_thresh->weight = rssiCmd->weight;
+ sq_thresh->polling_interval = rssiCmd->pollTime;
+
+ sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->upper_threshold_valid_count = 6;
+
+ /* List sorted in descending order */
+ sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR;
+ sq_thresh->lower_threshold_valid_count = 6;
+
+ if (!rssi_event_value) {
+ /*
+ * Configuring the thresholds to their extremes allows the host to get an
+ * event from the target which is used for the configuring the correct
+ * thresholds
+ */
+ rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0];
+ rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0];
+ } else {
+ /*
+ * In case the user issues multiple times of rssi_threshold_setting,
+ * we should not use the extreames anymore, the target does not expect that.
+ */
+ rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh,
+ sq_thresh->upper_threshold_valid_count);
+ rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh,
+ sq_thresh->lower_threshold_valid_count);
+}
+}
+
+A_STATUS
+wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+
+ /* Check these values are in ascending order */
+ if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val ||
+ rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val ||
+ rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val ||
+ rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val ||
+ rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val ||
+ rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val ||
+ rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val ||
+ rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val ||
+ rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val ||
+ rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val)
+ {
+ return A_EINVAL;
+ }
+
+ wmi_cache_configure_rssithreshold(wmip, rssiCmd);
+
+ return (wmi_send_rssi_threshold_params(wmip, rssiCmd));
+}
+
+A_STATUS
+wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd)
+{
+ void *osbuf;
+ WMI_SET_IP_CMD *cmd;
+
+ /* Multicast address are not valid */
+ if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) ||
+ (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD));
+ cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip,
+ WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_SET_HOST_SLEEP_MODE_CMD *cmd;
+ A_UINT16 activeTsids=0;
+ A_UINT8 streamExists=0;
+ A_UINT8 i;
+
+ if( hostModeCmd->awake == hostModeCmd->asleep) {
+ return A_EINVAL;
+ }
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD));
+
+ if(hostModeCmd->asleep) {
+ /*
+ * Relinquish credits from all implicitly created pstreams since when we
+ * go to sleep. If user created explicit thinstreams exists with in a
+ * fatpipe leave them intact for the user to delete
+ */
+ LOCK_WMI(wmip);
+ streamExists = wmip->wmi_fatPipeExists;
+ UNLOCK_WMI(wmip);
+
+ for(i=0;i< WMM_NUM_AC;i++) {
+ if (streamExists & (1<<i)) {
+ LOCK_WMI(wmip);
+ activeTsids = wmip->wmi_streamExistsForAC[i];
+ UNLOCK_WMI(wmip);
+ /* If there are no user created thin streams delete the fatpipe */
+ if(!activeTsids) {
+ streamExists &= ~(1<<i);
+ /*Indicate inactivity to drv layer for this fatpipe(pstream)*/
+ A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt,i);
+ }
+ }
+ }
+
+ /* Update the fatpipes that exists*/
+ LOCK_WMI(wmip);
+ wmip->wmi_fatPipeExists = streamExists;
+ UNLOCK_WMI(wmip);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wow_mode_cmd(struct wmi_t *wmip,
+ WMI_SET_WOW_MODE_CMD *wowModeCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_SET_WOW_MODE_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_wow_list_cmd(struct wmi_t *wmip,
+ WMI_GET_WOW_LIST_CMD *wowListCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_GET_WOW_LIST_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+static A_STATUS
+wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_GET_WOW_LIST_REPLY *reply;
+
+ if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_GET_WOW_LIST_REPLY *)datap;
+
+ A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters,
+ reply);
+
+ return A_OK;
+}
+
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_ADD_WOW_PATTERN_CMD *addWowCmd,
+ A_UINT8* pattern, A_UINT8* mask,
+ A_UINT8 pattern_size)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_ADD_WOW_PATTERN_CMD *cmd;
+ A_UINT8 *filter_mask = NULL;
+
+ size = sizeof (*cmd);
+
+ size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8));
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->filter_list_id = addWowCmd->filter_list_id;
+ cmd->filter_offset = addWowCmd->filter_offset;
+ cmd->filter_size = addWowCmd->filter_size;
+
+ A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size);
+
+ filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size);
+ A_MEMCPY(filter_mask, mask, addWowCmd->filter_size);
+
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_DEL_WOW_PATTERN_CMD *delWowCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_DEL_WOW_PATTERN_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+void
+wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+ SQ_THRESHOLD_PARAMS *sq_thresh =
+ &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR];
+ /*
+ * Parse the command and store the threshold values here. The checks
+ * for valid values can be put here
+ */
+ sq_thresh->weight = snrCmd->weight;
+ sq_thresh->polling_interval = snrCmd->pollTime;
+
+ sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val;
+ sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val;
+ sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val;
+ sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val;
+ sq_thresh->upper_threshold_valid_count = 4;
+
+ /* List sorted in descending order */
+ sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val;
+ sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val;
+ sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val;
+ sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val;
+ sq_thresh->lower_threshold_valid_count = 4;
+
+ if (!snr_event_value) {
+ /*
+ * Configuring the thresholds to their extremes allows the host to get an
+ * event from the target which is used for the configuring the correct
+ * thresholds
+ */
+ snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0];
+ snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0];
+ } else {
+ /*
+ * In case the user issues multiple times of snr_threshold_setting,
+ * we should not use the extreames anymore, the target does not expect that.
+ */
+ snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh,
+ sq_thresh->upper_threshold_valid_count);
+ snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh,
+ sq_thresh->lower_threshold_valid_count);
+ }
+
+}
+A_STATUS
+wmi_set_snr_threshold_params(struct wmi_t *wmip,
+ WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+ if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val ||
+ snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val ||
+ snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val ||
+ snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val ||
+ snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val ||
+ snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val)
+ {
+ return A_EINVAL;
+ }
+ wmi_cache_configure_snrthreshold(wmip, snrCmd);
+ return (wmi_send_snr_threshold_params(wmip, snrCmd));
+}
+
+A_STATUS
+wmi_clr_rssi_snr(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(int));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lq_threshold_params(struct wmi_t *wmip,
+ WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_LQ_THRESHOLD_PARAMS_CMD *cmd;
+ /* These values are in ascending order */
+ if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val ||
+ lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val ||
+ lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val ||
+ lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val ||
+ lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val ||
+ lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) {
+
+ return A_EINVAL;
+ }
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ cmd->bitmask = mask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source)
+{
+ void *osbuf;
+ WMIX_HB_CHALLENGE_RESP_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->cookie = cookie;
+ cmd->source = source;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+ A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+ A_UINT32 valid)
+{
+ void *osbuf;
+ WMIX_DBGLOG_CFG_MODULE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->config.cfgmmask = mmask;
+ cmd->config.cfgtsr = tsr;
+ cmd->config.cfgrep = rep;
+ cmd->config.cfgsize = size;
+ cmd->config.cfgvalid = valid;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_stats_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID);
+}
+
+A_STATUS
+wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
+{
+ void *osbuf;
+ WMI_ADD_BAD_AP_CMD *cmd;
+
+ if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->badApIndex = apIndex;
+ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG));
+}
+
+A_STATUS
+wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
+{
+ void *osbuf;
+ WMI_DELETE_BAD_AP_CMD *cmd;
+
+ if (apIndex > WMI_MAX_BAD_AP_INDEX) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->badApIndex = apIndex;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_abort_scan_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID);
+}
+
+A_STATUS
+wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
+{
+ void *osbuf;
+ WMI_SET_TX_PWR_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->dbM = dbM;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_txPwr_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID);
+}
+
+A_UINT16
+wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass)
+{
+ A_UINT16 activeTsids=0;
+
+ LOCK_WMI(wmip);
+ activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+ UNLOCK_WMI(wmip);
+
+ return activeTsids;
+}
+
+A_STATUS
+wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID);
+}
+
+A_STATUS
+wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
+{
+ void *osbuf;
+ A_UINT32 size = sizeof(A_UINT8);
+ WMI_TARGET_ROAM_DATA *cmd;
+
+ osbuf = A_NETBUF_ALLOC(size); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf));
+ cmd->roamDataType = roamDataType;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+ A_UINT8 size)
+{
+ void *osbuf;
+ WMI_SET_ROAM_CTRL_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ A_MEMCPY(cmd, p, size);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+ WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+ A_UINT8 size)
+{
+ void *osbuf;
+ WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd;
+
+ /* These timers can't be zero */
+ if(!pCmd->psPollTimeout || !pCmd->triggerTimeout ||
+ !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD ||
+ pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) ||
+ !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD ||
+ pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD))
+ return A_EINVAL;
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ A_MEMCPY(cmd, pCmd, size);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+/* Send a command to Target to change GPIO output pins. */
+A_STATUS
+wmi_gpio_output_set(struct wmi_t *wmip,
+ A_UINT32 set_mask,
+ A_UINT32 clear_mask,
+ A_UINT32 enable_mask,
+ A_UINT32 disable_mask)
+{
+ void *osbuf;
+ WMIX_GPIO_OUTPUT_SET_CMD *output_set;
+ int size;
+
+ size = sizeof(*output_set);
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
+ set_mask, clear_mask, enable_mask, disable_mask));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+ output_set->set_mask = set_mask;
+ output_set->clear_mask = clear_mask;
+ output_set->enable_mask = enable_mask;
+ output_set->disable_mask = disable_mask;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target requesting state of the GPIO input pins */
+A_STATUS
+wmi_gpio_input_get(struct wmi_t *wmip)
+{
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID);
+}
+
+/* Send a command to the Target that changes the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_set(struct wmi_t *wmip,
+ A_UINT32 gpioreg_id,
+ A_UINT32 value)
+{
+ void *osbuf;
+ WMIX_GPIO_REGISTER_SET_CMD *register_set;
+ int size;
+
+ size = sizeof(*register_set);
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+ register_set->gpioreg_id = gpioreg_id;
+ register_set->value = value;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target to fetch the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_get(struct wmi_t *wmip,
+ A_UINT32 gpioreg_id)
+{
+ void *osbuf;
+ WMIX_GPIO_REGISTER_GET_CMD *register_get;
+ int size;
+
+ size = sizeof(*register_get);
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
+
+ register_get->gpioreg_id = gpioreg_id;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target acknowledging some GPIO interrupts. */
+A_STATUS
+wmi_gpio_intr_ack(struct wmi_t *wmip,
+ A_UINT32 ack_mask)
+{
+ void *osbuf;
+ WMIX_GPIO_INTR_ACK_CMD *intr_ack;
+ int size;
+
+ size = sizeof(*intr_ack);
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
+
+ intr_ack->ack_mask = ack_mask;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+A_STATUS
+wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac, A_UINT16 txop, A_UINT8 eCWmin,
+ A_UINT8 eCWmax, A_UINT8 aifsn)
+{
+ void *osbuf;
+ WMI_SET_ACCESS_PARAMS_CMD *cmd;
+
+ if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
+ (aifsn > WMI_MAX_AIFSN_ACPARAM) || (ac >= WMM_NUM_AC))
+ {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->txop = txop;
+ cmd->eCWmin = eCWmin;
+ cmd->eCWmax = eCWmax;
+ cmd->aifsn = aifsn;
+ cmd->ac = ac;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+ A_UINT8 trafficClass, A_UINT8 maxRetries,
+ A_UINT8 enableNotify)
+{
+ void *osbuf;
+ WMI_SET_RETRY_LIMITS_CMD *cmd;
+
+ if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
+ (frameType != DATA_FRAMETYPE))
+ {
+ return A_EINVAL;
+ }
+
+ if (maxRetries > WMI_MAX_RETRIES) {
+ return A_EINVAL;
+ }
+
+ if (frameType != DATA_FRAMETYPE) {
+ trafficClass = 0;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->frameType = frameType;
+ cmd->trafficClass = trafficClass;
+ cmd->maxRetries = maxRetries;
+ cmd->enableNotify = enableNotify;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
+{
+ if (bssid != NULL) {
+ A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
+ }
+}
+
+A_STATUS
+wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
+{
+ void *osbuf;
+ WMI_SET_OPT_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->optMode = optMode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
+ SYNC_BOTH_WMIFLAG));
+}
+
+A_STATUS
+wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+ A_UINT8 frmType,
+ A_UINT8 *dstMacAddr,
+ A_UINT8 *bssid,
+ A_UINT16 optIEDataLen,
+ A_UINT8 *optIEData)
+{
+ void *osbuf;
+ WMI_OPT_TX_FRAME_CMD *cmd;
+ osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd)));
+
+ cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1));
+
+ cmd->frmType = frmType;
+ cmd->optIEDataLen = optIEDataLen;
+ //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd));
+ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+ A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
+ A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
+{
+ void *osbuf;
+ WMI_BEACON_INT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->beaconInterval = intvl;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
+{
+ void *osbuf;
+ WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->voicePktSize = voicePktSize;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
+{
+ void *osbuf;
+ WMI_SET_MAX_SP_LEN_CMD *cmd;
+
+ /* maxSPLen is a two-bit value. If user trys to set anything
+ * other than this, then its invalid
+ */
+ if(maxSPLen & ~0x03)
+ return A_EINVAL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->maxSPLen = maxSPLen;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_determine_userPriority(
+ A_UINT8 *pkt,
+ A_UINT32 layer2Pri)
+{
+ A_UINT8 ipPri;
+ iphdr *ipHdr = (iphdr *)pkt;
+
+ /* Determine IPTOS priority */
+ /*
+ * IP Tos format :
+ * (Refer Pg 57 WMM-test-plan-v1.2)
+ * IP-TOS - 8bits
+ * : DSCP(6-bits) ECN(2-bits)
+ * : DSCP - P2 P1 P0 X X X
+ * where (P2 P1 P0) form 802.1D
+ */
+ ipPri = ipHdr->ip_tos >> 5;
+ ipPri &= 0x7;
+
+ if ((layer2Pri & 0x7) > ipPri)
+ return ((A_UINT8)layer2Pri & 0x7);
+ else
+ return ipPri;
+}
+
+A_UINT8
+convert_userPriority_to_trafficClass(A_UINT8 userPriority)
+{
+ return (up_to_ac[userPriority & 0x7]);
+}
+
+A_UINT8
+wmi_get_power_mode_cmd(struct wmi_t *wmip)
+{
+ return wmip->wmi_powerMode;
+}
+
+A_STATUS
+wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
+{
+ A_STATUS ret = A_OK;
+
+#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0)
+#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF 0
+#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF 0
+#define TSPEC_DELAY_BOUND_ATHEROS_DEF 0
+#define TSPEC_MEDIUM_TIME_ATHEROS_DEF 0
+#define TSPEC_SBA_ATHEROS_DEF 0x2000 /* factor is 1 */
+
+ /* Verify TSPEC params for ATHEROS compliance */
+ if(tspecCompliance == ATHEROS_COMPLIANCE) {
+ if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) ||
+ (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) ||
+ (pCmd->minDataRate != pCmd->meanDataRate) ||
+ (pCmd->minDataRate != pCmd->peakDataRate) ||
+ (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) ||
+ (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) ||
+ (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) ||
+ (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) {
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG));
+ //A_PRINTF("%s: Invalid TSPEC params\n", __func__);
+ ret = A_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
+
+ return A_OK;
+}
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+A_STATUS
+wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+ void *osbuf;
+ WMI_SET_AUTH_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->mode = mode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+ void *osbuf;
+ WMI_SET_REASSOC_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->mode = mode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy)
+{
+ void *osbuf;
+ WMI_SET_LPREAMBLE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->status = status;
+ cmd->preamblePolicy = preamblePolicy;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold)
+{
+ void *osbuf;
+ WMI_SET_RTS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->threshold = threshold;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status)
+{
+ void *osbuf;
+ WMI_SET_WMM_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->status = status;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_qos_supp_cmd(struct wmi_t *wmip, A_UINT8 status)
+{
+ void *osbuf;
+ WMI_SET_QOS_SUPP_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_QOS_SUPP_CMD*)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->status = status;
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_QOS_SUPP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg)
+{
+ void *osbuf;
+ WMI_SET_WMM_TXOP_CMD *cmd;
+
+ if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) )
+ return A_EINVAL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->txopEnable = cfg;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode)
+{
+ void *osbuf;
+ WMI_AP_SET_COUNTRY_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ A_MEMCPY(cmd->countryCode,countryCode,3);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/* WMI layer doesn't need to know the data type of the test cmd.
+ This would be beneficial for customers like Qualcomm, who might
+ have different test command requirements from differnt manufacturers
+ */
+A_STATUS
+wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len)
+{
+ void *osbuf;
+ char *data;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ osbuf= A_NETBUF_ALLOC(len);
+ if(osbuf == NULL)
+ {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, len);
+ data = A_NETBUF_DATA(osbuf);
+ A_MEMCPY(data, buf, len);
+
+ return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+#endif
+
+A_STATUS
+wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status)
+{
+ void *osbuf;
+ WMI_SET_BT_STATUS_CMD *cmd;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Enter - streamType=%d, status=%d\n", streamType, status));
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->streamType = streamType;
+ cmd->status = status;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd)
+{
+ void *osbuf;
+ WMI_SET_BT_PARAMS_CMD* alloc_cmd;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("cmd params is %d\n", cmd->paramType));
+
+ if (cmd->paramType == BT_PARAM_SCO) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n", cmd->info.scoParams.numScoCyclesForceTrigger,
+ cmd->info.scoParams.dataResponseTimeout,
+ cmd->info.scoParams.stompScoRules,
+ cmd->info.scoParams.scoOptFlags,
+ cmd->info.scoParams.stompDutyCyleVal,
+ cmd->info.scoParams.stompDutyCyleMaxVal,
+ cmd->info.scoParams.psPollLatencyFraction,
+ cmd->info.scoParams.noSCOSlots,
+ cmd->info.scoParams.noIdleSlots,
+ cmd->info.scoParams.scoOptOffRssi,
+ cmd->info.scoParams.scoOptOnRssi,
+ cmd->info.scoParams.scoOptRtsCount));
+ }
+ else if (cmd->paramType == BT_PARAM_A2DP) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("A2DP params %d %d %d %d %d %d %d %d\n", cmd->info.a2dpParams.a2dpWlanUsageLimit,
+ cmd->info.a2dpParams.a2dpBurstCntMin,
+ cmd->info.a2dpParams.a2dpDataRespTimeout,
+ cmd->info.a2dpParams.a2dpOptFlags,
+ cmd->info.a2dpParams.isCoLocatedBtRoleMaster,
+ cmd->info.a2dpParams.a2dpOptOffRssi,
+ cmd->info.a2dpParams.a2dpOptOnRssi,
+ cmd->info.a2dpParams.a2dpOptRtsCount));
+ }
+ else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Ant config %d\n", cmd->info.antType));
+ }
+ else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("co-located BT %d\n", cmd->info.coLocatedBtDev));
+ }
+ else if (cmd->paramType == BT_PARAM_ACLCOEX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("ACL params %d %d %d\n", cmd->info.aclCoexParams.aclWlanMediumUsageTime,
+ cmd->info.aclCoexParams.aclBtMediumUsageTime,
+ cmd->info.aclCoexParams.aclDataRespTimeout));
+ }
+ else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG));
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_FE_ANT_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_FE_ANT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_FE_ANT_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+
+A_STATUS
+wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+ A_PRINTF("colocated bt = %d\n", alloc_cmd->btcoexCoLocatedBTdev);
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD* cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_SCO_CONFIG_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_SCO_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_SCO_CONFIG_CMDID ,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_A2DP_CONFIG_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_A2DP_CONFIG_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_A2DP_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_A2DP_CONFIG_CMDID ,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip,
+ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID ,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_DEBUG_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_DEBUG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_DEBUG_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_DEBUG_CMDID ,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip,
+ WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd)
+{
+ void *osbuf;
+ WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd)
+{
+ void *osbuf;
+ WMI_GET_BTCOEX_CONFIG_CMD *alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ alloc_cmd = (WMI_GET_BTCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_GET_BTCOEX_CONFIG_CMD));
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_BTCOEX_CONFIG_CMDID ,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_btcoex_stats_cmd(struct wmi_t *wmip)
+{
+
+ return wmi_simple_cmd(wmip, WMI_GET_BTCOEX_STATS_CMDID);
+
+}
+
+A_STATUS
+wmi_get_keepalive_configured(struct wmi_t *wmip)
+{
+ void *osbuf;
+ WMI_GET_KEEPALIVE_CMD *cmd;
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_get_keepalive_cmd(struct wmi_t *wmip)
+{
+ return wmip->wmi_keepaliveInterval;
+}
+
+A_STATUS
+wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval)
+{
+ void *osbuf;
+ WMI_SET_KEEPALIVE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->keepaliveInterval = keepaliveInterval;
+ wmip->wmi_keepaliveInterval = keepaliveInterval;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer)
+{
+ void *osbuf;
+ WMI_SET_PARAMS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd) + length);
+
+ cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->opcode = opcode;
+ cmd->length = length;
+ A_MEMCPY(cmd->buffer, buffer, length);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4)
+{
+ void *osbuf;
+ WMI_SET_MCAST_FILTER_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->multicast_mac[0] = 0x01;
+ cmd->multicast_mac[1] = 0x00;
+ cmd->multicast_mac[2] = 0x5e;
+ cmd->multicast_mac[3] = dot2&0x7F;
+ cmd->multicast_mac[4] = dot3;
+ cmd->multicast_mac[5] = dot4;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4)
+{
+ void *osbuf;
+ WMI_SET_MCAST_FILTER_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->multicast_mac[0] = 0x01;
+ cmd->multicast_mac[1] = 0x00;
+ cmd->multicast_mac[2] = 0x5e;
+ cmd->multicast_mac[3] = dot2&0x7F;
+ cmd->multicast_mac[4] = dot3;
+ cmd->multicast_mac[5] = dot4;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable)
+{
+ void *osbuf;
+ WMI_MCAST_FILTER_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->enable = enable;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_MCAST_FILTER_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen,
+ A_UINT8 *ieInfo)
+{
+ void *osbuf;
+ WMI_SET_APPIE_CMD *cmd;
+ A_UINT16 cmdLen;
+
+ cmdLen = sizeof(*cmd) + ieLen - 1;
+ osbuf = A_NETBUF_ALLOC(cmdLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, cmdLen);
+
+ cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, cmdLen);
+
+ cmd->mgmtFrmType = mgmtFrmType;
+ cmd->ieLen = ieLen;
+ A_MEMCPY(cmd->ieInfo, ieInfo, ieLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen)
+{
+ void *osbuf;
+ A_UINT8 *data;
+
+ osbuf = A_NETBUF_ALLOC(dataLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, dataLen);
+
+ data = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(data, cmd, dataLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_INT32
+wmi_get_rate(A_INT8 rateindex)
+{
+ if (rateindex == RATE_AUTO) {
+ return 0;
+ } else {
+ return(wmi_rateTable[(A_UINT32) rateindex][0]);
+ }
+}
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss)
+{
+ if (NULL != bss)
+ {
+ wlan_node_return (&wmip->wmi_scan_table, bss);
+ }
+}
+
+void
+wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge)
+{
+ wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge);
+}
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID)
+{
+ bss_t *node = NULL;
+ node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid,
+ ssidLength, bIsWPA2, bMatchSSID);
+ return node;
+}
+
+
+void
+wmi_free_allnodes(struct wmi_t *wmip)
+{
+ wlan_free_allnodes(&wmip->wmi_scan_table);
+}
+
+bss_t *
+wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+ bss_t *ni=NULL;
+ ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+ return ni;
+}
+
+void
+wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+ bss_t *ni=NULL;
+
+ ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+ if (ni != NULL) {
+ wlan_node_reclaim(&wmip->wmi_scan_table, ni);
+ }
+
+ return;
+}
+
+A_STATUS
+wmi_dset_open_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT32 access_cookie,
+ A_UINT32 dset_size,
+ A_UINT32 dset_version,
+ A_UINT32 targ_handle,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg)
+{
+ void *osbuf;
+ WMIX_DSETOPEN_REPLY_CMD *open_reply;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip));
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*open_reply));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*open_reply));
+ open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+ open_reply->status = status;
+ open_reply->targ_dset_handle = targ_handle;
+ open_reply->targ_reply_fn = targ_reply_fn;
+ open_reply->targ_reply_arg = targ_reply_arg;
+ open_reply->access_cookie = access_cookie;
+ open_reply->size = dset_size;
+ open_reply->version = dset_version;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+ WMI_PMKID_LIST_REPLY *reply;
+ A_UINT32 expected_len;
+
+ if (len < sizeof(WMI_PMKID_LIST_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_PMKID_LIST_REPLY *)datap;
+ expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN;
+
+ if (len < expected_len) {
+ return A_EINVAL;
+ }
+
+ A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID,
+ reply->pmkidList, reply->bssidList[0]);
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+ WMI_SET_PARAMS_REPLY *reply;
+
+ if (len < sizeof(WMI_SET_PARAMS_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_SET_PARAMS_REPLY *)datap;
+
+ if (A_OK == reply->status)
+ {
+
+ }
+ else
+ {
+
+ }
+
+ return A_OK;
+}
+
+
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+A_STATUS
+wmi_dset_data_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT8 *user_buf,
+ A_UINT32 length,
+ A_UINT32 targ_buf,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg)
+{
+ void *osbuf;
+ WMIX_DSETDATA_REPLY_CMD *data_reply;
+ A_UINT32 size;
+
+ size = sizeof(*data_reply) + length;
+
+ if (size <= length) {
+ return A_ERROR;
+ }
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+ data_reply->status = status;
+ data_reply->targ_buf = targ_buf;
+ data_reply->targ_reply_fn = targ_reply_fn;
+ data_reply->targ_reply_arg = targ_reply_arg;
+ data_reply->length = length;
+
+ if (status == A_OK) {
+ if (a_copy_from_user(data_reply->buf, user_buf, length)) {
+ A_NETBUF_FREE(osbuf);
+ return A_ERROR;
+ }
+ }
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+A_STATUS
+wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status)
+{
+ void *osbuf;
+ char *cmd;
+
+ wps_enable = status;
+
+ osbuf = a_netbuf_alloc(sizeof(1));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ a_netbuf_put(osbuf, sizeof(1));
+
+ cmd = (char *)(a_netbuf_to_data(osbuf));
+
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd[0] = (status?1:0);
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
+A_STATUS
+wmi_prof_cfg_cmd(struct wmi_t *wmip,
+ A_UINT32 period,
+ A_UINT32 nbins)
+{
+ void *osbuf;
+ WMIX_PROF_CFG_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->period = period;
+ cmd->nbins = nbins;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr)
+{
+ void *osbuf;
+ WMIX_PROF_ADDR_SET_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->addr = addr;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_prof_start_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID);
+}
+
+A_STATUS
+wmi_prof_stop_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID);
+}
+
+A_STATUS
+wmi_prof_count_get_cmd(struct wmi_t *wmip)
+{
+ return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID);
+}
+
+/* Called to handle WMIX_PROF_CONT_EVENTID */
+static A_STATUS
+wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG,
+ prof_data->addr, prof_data->count));
+
+ A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count);
+
+ return A_OK;
+}
+#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
+
+#ifdef OS_ROAM_MANAGEMENT
+
+#define ETHERNET_MAC_ADDRESS_LENGTH 6
+
+void
+wmi_scan_indication (struct wmi_t *wmip)
+{
+ struct ieee80211_node_table *nt;
+ A_UINT32 gen;
+ A_UINT32 size;
+ A_UINT32 bsssize;
+ bss_t *bss;
+ A_UINT32 numbss;
+ PNDIS_802_11_BSSID_SCAN_INFO psi;
+ PBYTE pie;
+ NDIS_802_11_FIXED_IEs *pFixed;
+ NDIS_802_11_VARIABLE_IEs *pVar;
+ A_UINT32 RateSize;
+
+ struct ar6kScanIndication
+ {
+ NDIS_802_11_STATUS_INDICATION ind;
+ NDIS_802_11_BSSID_SCAN_INFO_LIST slist;
+ } *pAr6kScanIndEvent;
+
+ nt = &wmip->wmi_scan_table;
+
+ ++nt->nt_si_gen;
+
+
+ gen = nt->nt_si_gen;
+
+ size = offsetof(struct ar6kScanIndication, slist) +
+ offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo);
+
+ numbss = 0;
+
+ IEEE80211_NODE_LOCK(nt);
+
+ //calc size
+ for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) {
+ if (bss->ni_si_gen != gen) {
+ bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs);
+ bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs);
+
+#ifdef SUPPORT_WPA2
+ if (bss->ni_cie.ie_rsn) {
+ bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2;
+ }
+#endif
+ if (bss->ni_cie.ie_wpa) {
+ bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2;
+ }
+
+ // bsssize must be a multiple of 4 to maintain alignment.
+ bsssize = (bsssize + 3) & ~3;
+
+ size += bsssize;
+
+ numbss++;
+ }
+ }
+
+ if (0 == numbss)
+ {
+// RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n"));
+ ar6000_scan_indication (wmip->wmi_devt, NULL, 0);
+ IEEE80211_NODE_UNLOCK (nt);
+ return;
+ }
+
+ pAr6kScanIndEvent = A_MALLOC(size);
+
+ if (NULL == pAr6kScanIndEvent)
+ {
+ IEEE80211_NODE_UNLOCK(nt);
+ return;
+ }
+
+ A_MEMZERO(pAr6kScanIndEvent, size);
+
+ //copy data
+ pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList;
+ pAr6kScanIndEvent->slist.Version = 1;
+ pAr6kScanIndEvent->slist.NumItems = numbss;
+
+ psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0];
+
+ for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) {
+ if (bss->ni_si_gen != gen) {
+
+ bss->ni_si_gen = gen;
+
+ //Set scan time
+ psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC;
+
+ // Copy data to bssid_ex
+ bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs);
+ bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs);
+
+#ifdef SUPPORT_WPA2
+ if (bss->ni_cie.ie_rsn) {
+ bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2;
+ }
+#endif
+ if (bss->ni_cie.ie_wpa) {
+ bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2;
+ }
+
+ // bsssize must be a multiple of 4 to maintain alignment.
+ bsssize = (bsssize + 3) & ~3;
+
+ psi->Bssid.Length = bsssize;
+
+ memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH);
+
+
+//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) ||
+// ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70)))
+// RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5]));
+
+ psi->Bssid.Ssid.SsidLength = 0;
+ pie = bss->ni_cie.ie_ssid;
+
+ if (pie) {
+ // Format of SSID IE is:
+ // Type (1 octet)
+ // Length (1 octet)
+ // SSID (Length octets)
+ //
+ // Validation of the IE should have occurred within WMI.
+ //
+ if (pie[1] <= 32) {
+ psi->Bssid.Ssid.SsidLength = pie[1];
+ memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength);
+ }
+ }
+ psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0;
+
+ //Post the RSSI value relative to the Standard Noise floor value.
+ psi->Bssid.Rssi = bss->ni_rssi;
+
+ if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) {
+
+ if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) {
+ psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24;
+ }
+ else {
+ psi->Bssid.NetworkTypeInUse = Ndis802_11DS;
+ }
+ }
+ else {
+ psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5;
+ }
+
+ psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration);
+ psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us)
+ psi->Bssid.Configuration.ATIMWindow = 0;
+ psi->Bssid.Configuration.DSConfig = bss->ni_cie.ie_chan * 1000;
+ psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS;
+
+ RateSize = 0;
+ pie = bss->ni_cie.ie_rates;
+ if (pie) {
+ RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX;
+ memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize);
+ }
+ pie = bss->ni_cie.ie_xrates;
+ if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) {
+ memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2],
+ (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize));
+ }
+
+ // Copy the fixed IEs
+ psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs);
+
+ pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs;
+ memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp));
+ pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt;
+ pFixed->Capabilities = bss->ni_cie.ie_capInfo;
+
+ // Copy selected variable IEs
+
+ pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs));
+
+#ifdef SUPPORT_WPA2
+ // Copy the WPAv2 IE
+ if (bss->ni_cie.ie_rsn) {
+ pie = bss->ni_cie.ie_rsn;
+ psi->Bssid.IELength += pie[1] + 2;
+ memcpy(pVar, pie, pie[1] + 2);
+ pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2);
+ }
+#endif
+ // Copy the WPAv1 IE
+ if (bss->ni_cie.ie_wpa) {
+ pie = bss->ni_cie.ie_wpa;
+ psi->Bssid.IELength += pie[1] + 2;
+ memcpy(pVar, pie, pie[1] + 2);
+ pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2);
+ }
+
+ // Advance buffer pointer
+ psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid));
+ }
+ }
+
+ IEEE80211_NODE_UNLOCK(nt);
+
+// wmi_free_allnodes(wmip);
+
+// RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss));
+
+ ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size);
+
+ A_FREE(pAr6kScanIndEvent);
+}
+#endif
+
+A_UINT8
+ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh,
+ A_UINT32 size)
+{
+ A_UINT32 index;
+ A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1];
+
+ /* The list is already in sorted order. Get the next lower value */
+ for (index = 0; index < size; index ++) {
+ if (rssi < sq_thresh->upper_threshold[index]) {
+ threshold = (A_UINT8)sq_thresh->upper_threshold[index];
+ break;
+ }
+ }
+
+ return threshold;
+}
+
+A_UINT8
+ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh,
+ A_UINT32 size)
+{
+ A_UINT32 index;
+ A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1];
+
+ /* The list is already in sorted order. Get the next lower value */
+ for (index = 0; index < size; index ++) {
+ if (rssi > sq_thresh->lower_threshold[index]) {
+ threshold = (A_UINT8)sq_thresh->lower_threshold[index];
+ break;
+ }
+ }
+
+ return threshold;
+}
+static A_STATUS
+wmi_send_rssi_threshold_params(struct wmi_t *wmip,
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+static A_STATUS
+wmi_send_snr_threshold_params(struct wmi_t *wmip,
+ WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_SNR_THRESHOLD_PARAMS_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+ cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd)
+{
+ void *osbuf;
+ WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id)
+{
+ wmi_get_current_bssid (wmip, id);
+ return wlan_node_remove (&wmip->wmi_scan_table, id);
+}
+
+A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss)
+{
+ wlan_setup_node (&wmip->wmi_scan_table, bss, id);
+ return A_OK;
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+static A_STATUS
+wmi_addba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_ADDBA_REQ_EVENT *cmd = (WMI_ADDBA_REQ_EVENT *)datap;
+
+ A_WMI_AGGR_RECV_ADDBA_REQ_EVT(wmip->wmi_devt, cmd);
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_addba_resp_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_ADDBA_RESP_EVENT *cmd = (WMI_ADDBA_RESP_EVENT *)datap;
+
+ A_WMI_AGGR_RECV_ADDBA_RESP_EVT(wmip->wmi_devt, cmd);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_delba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_DELBA_EVENT *cmd = (WMI_DELBA_EVENT *)datap;
+
+ A_WMI_AGGR_RECV_DELBA_REQ_EVT(wmip->wmi_devt, cmd);
+
+ return A_OK;
+}
+
+A_STATUS
+wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_BTCOEX_CONFIG_EVENT(wmip->wmi_devt, datap, len);
+
+ return A_OK;
+}
+
+
+A_STATUS
+wmi_btcoex_stats_event_rx(struct wmi_t * wmip,A_UINT8 * datap,int len)
+{
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_BTCOEX_STATS_EVENT(wmip->wmi_devt, datap, len);
+
+ return A_OK;
+
+}
+#endif
+
+static A_STATUS
+wmi_hci_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_HCI_EVENT *cmd = (WMI_HCI_EVENT *)datap;
+ A_WMI_HCI_EVENT_EVT(wmip->wmi_devt, cmd);
+
+ return A_OK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//// ////
+//// AP mode functions ////
+//// ////
+////////////////////////////////////////////////////////////////////////////////
+/*
+ * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG
+ *
+ * When AR6K in AP mode, This command will be called after
+ * changing ssid, channel etc. It will pass the profile to
+ * target with a flag which will indicate which parameter changed,
+ * also if this flag is 0, there was no change in parametes, so
+ * commit cmd will not be sent to target. Without calling this IOCTL
+ * the changes will not take effect.
+ */
+A_STATUS
+wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p)
+{
+ void *osbuf;
+ WMI_CONNECT_CMD *cm;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cm));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cm));
+ cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cm, sizeof(*cm));
+
+ A_MEMCPY(cm,p,sizeof(*cm));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID
+ *
+ * This command will be used to enable/disable hidden ssid functioanlity of
+ * beacon. If it is enabled, ssid will be NULL in beacon.
+ */
+A_STATUS
+wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid)
+{
+ void *osbuf;
+ WMI_AP_HIDDEN_SSID_CMD *hs;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD));
+ hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(hs, sizeof(*hs));
+
+ hs->hidden_ssid = hidden_ssid;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid));
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA
+ *
+ * This command is used to limit max num of STA that can connect
+ * with this AP. This value should not exceed AP_MAX_NUM_STA (this
+ * is max num of STA supported by AP). Value was already validated
+ * in ioctl.c
+ */
+A_STATUS
+wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta)
+{
+ void *osbuf;
+ WMI_AP_SET_NUM_STA_CMD *ns;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD));
+ ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(ns, sizeof(*ns));
+
+ ns->num_sta = num_sta;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta));
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC
+ *
+ * This command is used to send list of mac of STAs which will
+ * be allowed to connect with this AP. When this list is empty
+ * firware will allow all STAs till the count reaches AP_MAX_NUM_STA.
+ */
+A_STATUS
+wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl)
+{
+ void *osbuf;
+ WMI_AP_ACL_MAC_CMD *a;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD));
+ a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(a, sizeof(*a));
+ A_MEMCPY(a,acl,sizeof(*acl));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_MLME
+ *
+ * This command is used to send list of mac of STAs which will
+ * be allowed to connect with this AP. When this list is empty
+ * firware will allow all STAs till the count reaches AP_MAX_NUM_STA.
+ */
+A_STATUS
+wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason)
+{
+ void *osbuf;
+ WMI_AP_SET_MLME_CMD *mlme;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD));
+ mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(mlme, sizeof(*mlme));
+
+ mlme->cmd = cmd;
+ A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN);
+ mlme->reason = reason;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_PSPOLL_EVENT *ev;
+
+ if (len < sizeof(WMI_PSPOLL_EVENT)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_PSPOLL_EVENT *)datap;
+
+ A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid);
+ return A_OK;
+}
+
+static A_STATUS
+wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len)
+{
+ A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt);
+ return A_OK;
+}
+
+#ifdef WAPI_ENABLE
+static A_STATUS
+wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len)
+{
+ A_UINT8 *ev;
+
+ if (len < 7) {
+ return A_EINVAL;
+ }
+ ev = (A_UINT8 *)datap;
+
+ A_WMI_WAPI_REKEY_EVENT(wmip->wmi_devt, *ev, &ev[1]);
+ return A_OK;
+}
+#endif
+
+A_STATUS
+wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag)
+{
+ WMI_AP_SET_PVB_CMD *cmd;
+ void *osbuf = NULL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD));
+ cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->aid = aid;
+ cmd->flag = flag;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period)
+{
+ WMI_AP_CONN_INACT_CMD *cmd;
+ void *osbuf = NULL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD));
+ cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->period = period;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell)
+{
+ WMI_AP_PROT_SCAN_TIME_CMD *cmd;
+ void *osbuf = NULL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD));
+ cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->period_min = period;
+ cmd->dwell_ms = dwell;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim)
+{
+ WMI_AP_SET_DTIM_CMD *cmd;
+ void *osbuf = NULL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD));
+ cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->dtim = dtim;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY
+ *
+ * This command is used to set ACL policay. While changing policy, if you
+ * want to retain the existing MAC addresses in the ACL list, policy should be
+ * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared.
+ * If there is no chage in policy, the list will be intact.
+ */
+A_STATUS
+wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy)
+{
+ void *osbuf;
+ WMI_AP_ACL_POLICY_CMD *po;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+}
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD));
+ po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(po, sizeof(*po));
+
+ po->policy = policy;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset)
+{
+ void *osbuf;
+ WMI_AP_SET_11BG_RATESET_CMD *rs;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_11BG_RATESET_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_11BG_RATESET_CMD));
+ rs = (WMI_AP_SET_11BG_RATESET_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(rs, sizeof(*rs));
+
+ rs->rateset = rateset;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_11BG_RATESET_CMDID, NO_SYNC_WMIFLAG));
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+A_STATUS
+wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd)
+{
+ void *osbuf;
+ WMI_SET_HT_CAP_CMD *htCap;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*htCap));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*htCap));
+
+ htCap = (WMI_SET_HT_CAP_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(htCap, sizeof(*htCap));
+ A_MEMCPY(htCap, cmd, sizeof(*htCap));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_CAP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width)
+{
+ void *osbuf;
+ WMI_SET_HT_OP_CMD *htInfo;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*htInfo));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*htInfo));
+
+ htInfo = (WMI_SET_HT_OP_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(htInfo, sizeof(*htInfo));
+ htInfo->sta_chan_width = sta_chan_width;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_OP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+#endif
+
+A_STATUS
+wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray)
+{
+ void *osbuf;
+ WMI_SET_TX_SELECT_RATES_CMD *pData;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*pData));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*pData));
+
+ pData = (WMI_SET_TX_SELECT_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMCPY(pData, pMaskArray, sizeof(*pData));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_SELECT_RATES_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz)
+{
+ void *osbuf;
+ WMI_HCI_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + sz);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd) + sz);
+ cmd = (WMI_HCI_CMD *)(A_NETBUF_DATA(osbuf));
+
+ cmd->cmd_buf_sz = sz;
+ A_MEMCPY(cmd->buf, buf, sz);
+ return (wmi_cmd_send(wmip, osbuf, WMI_HCI_CMD_CMDID, NO_SYNC_WMIFLAG));
+}
+
+#ifdef ATH_AR6K_11N_SUPPORT
+A_STATUS
+wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask)
+{
+ void *osbuf;
+ WMI_ALLOW_AGGR_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ALLOW_AGGR_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->tx_allow_aggr = tx_tidmask;
+ cmd->rx_allow_aggr = rx_tidmask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ALLOW_AGGR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid)
+{
+ void *osbuf;
+ WMI_ADDBA_REQ_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADDBA_REQ_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->tid = tid;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADDBA_REQ_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink)
+{
+ void *osbuf;
+ WMI_DELBA_REQ_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELBA_REQ_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->tid = tid;
+ cmd->is_sender_initiator = uplink; /* uplink =1 - uplink direction, 0=downlink direction */
+
+ /* Delete the local aggr state, on host */
+ return (wmi_cmd_send(wmip, osbuf, WMI_DELBA_REQ_CMDID, NO_SYNC_WMIFLAG));
+}
+#endif
+
+A_STATUS
+wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion,
+ A_BOOL rxDot11Hdr, A_BOOL defragOnHost)
+{
+ void *osbuf;
+ WMI_RX_FRAME_FORMAT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_RX_FRAME_FORMAT_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->dot11Hdr = (rxDot11Hdr==TRUE)? 1:0;
+ cmd->defragOnHost = (defragOnHost==TRUE)? 1:0;
+ cmd->metaVersion = rxMetaVersion; /* */
+
+ /* Delete the local aggr state, on host */
+ return (wmi_cmd_send(wmip, osbuf, WMI_RX_FRAME_FORMAT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode)
+{
+ void *osbuf;
+ WMI_SET_THIN_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_THIN_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->enable = (bThinMode==TRUE)? 1:0;
+
+ /* Delete the local aggr state, on host */
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_THIN_MODE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence)
+{
+ void *osbuf;
+ WMI_SET_BT_WLAN_CONN_PRECEDENCE *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_BT_WLAN_CONN_PRECEDENCE *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->precedence = precedence;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk)
+{
+ void *osbuf;
+ WMI_SET_PMK_CMD *p;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_PMK_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_SET_PMK_CMD));
+
+ p = (WMI_SET_PMK_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(p, sizeof(*p));
+
+ A_MEMCPY(p->pmk, pmk, WMI_PMK_LEN);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+bss_t *
+wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+ A_UINT32 ssidLength,
+ A_UINT32 dot11AuthMode, A_UINT32 authMode,
+ A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp)
+{
+ bss_t *node = NULL;
+ node = wlan_find_matching_Ssidnode (&wmip->wmi_scan_table, pSsid,
+ ssidLength, dot11AuthMode, authMode, pairwiseCryptoType, grpwiseCryptoTyp);
+
+ return node;
+}
+
+A_UINT16
+wmi_ieee2freq (int chan)
+{
+ A_UINT16 freq = 0;
+ freq = wlan_ieee2freq (chan);
+ return freq;
+
+}
+
+A_UINT32
+wmi_freq2ieee (A_UINT16 freq)
+{
+ A_UINT16 chan = 0;
+ chan = wlan_freq2ieee (freq);
+ return chan;
+}
diff --git a/drivers/net/wireless/ath6kl/wmi/wmi_host.h b/drivers/net/wireless/ath6kl/wmi/wmi_host.h
new file mode 100644
index 000000000000..474e239e316c
--- /dev/null
+++ b/drivers/net/wireless/ath6kl/wmi/wmi_host.h
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+// <copyright file="wmi_host.h" company="Atheros">
+// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License version 2 as
+// published by the Free Software Foundation;
+//
+// Software distributed under the License is distributed on an "AS
+// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+// implied. See the License for the specific language governing
+// rights and limitations under the License.
+//
+//
+//------------------------------------------------------------------------------
+//==============================================================================
+// This file contains local definitios for the wmi host module.
+//
+// Author(s): ="Atheros"
+//==============================================================================
+#ifndef _WMI_HOST_H_
+#define _WMI_HOST_H_
+
+#include "roaming.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct wmi_stats {
+ A_UINT32 cmd_len_err;
+ A_UINT32 cmd_id_err;
+};
+
+#define SSID_IE_LEN_INDEX 13
+
+/* Host side link management data structures */
+#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6
+#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS
+#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS
+typedef struct sq_threshold_params_s {
+ A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS];
+ A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS];
+ A_UINT32 upper_threshold_valid_count;
+ A_UINT32 lower_threshold_valid_count;
+ A_UINT32 polling_interval;
+ A_UINT8 weight;
+ A_UINT8 last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target.
+ A_UINT8 last_rssi_poll_event; //Not sure if it belongs to host or target
+} SQ_THRESHOLD_PARAMS;
+struct wmi_t {
+ A_BOOL wmi_ready;
+ A_BOOL wmi_numQoSStream;
+ A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC];
+ A_UINT8 wmi_fatPipeExists;
+ void *wmi_devt;
+ struct wmi_stats wmi_stats;
+ struct ieee80211_node_table wmi_scan_table;
+ A_UINT8 wmi_bssid[ATH_MAC_LEN];
+ A_UINT8 wmi_powerMode;
+ A_UINT8 wmi_phyMode;
+ A_UINT8 wmi_keepaliveInterval;
+ A_MUTEX_T wmi_lock;
+ HTC_ENDPOINT_ID wmi_endpoint_id;
+ SQ_THRESHOLD_PARAMS wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX];
+ CRYPTO_TYPE wmi_pair_crypto_type;
+ CRYPTO_TYPE wmi_grp_crypto_type;
+ A_BOOL wmi_is_wmm_enabled;
+};
+
+
+#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock);
+#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_HOST_H_ */