diff options
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_chip.c | 10 | ||||
| -rw-r--r-- | ret.ou | 0 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index 9b5bb7eba279..7b28328c92f8 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -17,7 +17,7 @@ logical_chip_type_t getChipType(void) char physicalRev; logical_chip_type_t chip; - physicalID = devId750; /* either 0x718 or 0x750 */ + physicalID = devId750;//either 0x718 or 0x750 physicalRev = revId750; if (physicalID == 0x718) @@ -257,7 +257,7 @@ int ddk750_initHw(initchip_param_t *pInitParam) unsigned int ulReg; #if 0 - /* move the code to map regiter function. */ + //move the code to map regiter function. if (getChipType() == SM718) { /* turn on big endian bit*/ ulReg = PEEK32(0x74); @@ -488,6 +488,7 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) } } + //printk("Finally: pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD); return ret; } @@ -579,9 +580,14 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ } /* Restore input frequency from Khz to hz unit */ +// pPLL->inputFreq *= 1000; ulRequestClk *= 1000; pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */ + /* Output debug information */ + //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk)); + //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD)); + /* Return actual frequency that the PLL can set */ ret = calcPLL(pPLL); return ret; diff --git a/ret.ou b/ret.ou deleted file mode 100644 index e69de29bb2d1..000000000000 --- a/ret.ou +++ /dev/null |