diff options
| -rw-r--r-- | arch/arm/mach-imx/common.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-imx/cpuidle-imx6q.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-imx/pm-imx6q.c | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index baf439dc22d8..cdbddfa2a42f 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -139,7 +139,7 @@ void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_chicken_bit(void); +void imx6q_set_int_mem_clk_lpm(void); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index 23ddfb693b2d..6bcae0479049 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void) /* Need to enable SCU standby for entering WAIT modes */ imx_scu_standby_enable(); - /* Set chicken bit to get a reliable WAIT mode support */ - imx6q_set_chicken_bit(); + /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ + imx6q_set_int_mem_clk_lpm(); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 7a9b98589db7..30af3c0e1bf3 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -56,15 +56,15 @@ #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) #define CGPR 0x64 -#define BM_CGPR_CHICKEN_BIT (0x1 << 17) +#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) static void __iomem *ccm_base; -void imx6q_set_chicken_bit(void) +void imx6q_set_int_mem_clk_lpm(void) { u32 val = readl_relaxed(ccm_base + CGPR); - val |= BM_CGPR_CHICKEN_BIT; + val |= BM_CGPR_INT_MEM_CLK_LPM; writel_relaxed(val, ccm_base + CGPR); } |