diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index de9d4fcfb0eb..61eb7048ca49 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -286,6 +286,11 @@ #power-domain-cells = <0>; power-domains = <&pd_conn>; }; + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = <SC_R_USB_2_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; pd_conn_sdch0: PD_CONN_SDHC_0 { reg = <SC_R_SDHC_0>; #power-domain-cells = <0>; @@ -1412,6 +1417,32 @@ dmas = <&dma_apbh 0>; dma-names = "rx-tx"; power-domains = <&pd_conn_nand>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QXP_USB3_PHY_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usb2_phy>; + }; + + usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_USB3_LPM_CLK>, + <&clk IMX8QXP_USB3_BUS_CLK>, + <&clk IMX8QXP_USB3_ACLK>, + <&clk IMX8QXP_USB3_IPG_CLK>, + <&clk IMX8QXP_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; status = "disabled"; }; |