diff options
| -rw-r--r-- | drivers/staging/dwc2/core.c | 27 | ||||
| -rw-r--r-- | drivers/staging/dwc2/core.h | 5 | ||||
| -rw-r--r-- | drivers/staging/dwc2/hw.h | 3 | ||||
| -rw-r--r-- | drivers/staging/dwc2/pci.c | 2 |
4 files changed, 32 insertions, 5 deletions
diff --git a/drivers/staging/dwc2/core.c b/drivers/staging/dwc2/core.c index 825c5e5f157f..06dae67a9d62 100644 --- a/drivers/staging/dwc2/core.c +++ b/drivers/staging/dwc2/core.c @@ -2376,14 +2376,29 @@ int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) { + int valid = 0; int retval = 0; - if (DWC2_PARAM_TEST(val, 8, 8) && DWC2_PARAM_TEST(val, 16, 16)) { + switch (hsotg->hw_params.utmi_phy_data_width) { + case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: + valid = (val == 8); + break; + case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: + valid = (val == 16); + break; + case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: + valid = (val == 8 || val == 16); + break; + } + + if (!valid) { if (val >= 0) { - dev_err(hsotg->dev, "Wrong value for phy_utmi_width\n"); - dev_err(hsotg->dev, "phy_utmi_width must be 8 or 16\n"); + dev_err(hsotg->dev, + "%d invalid for phy_utmi_width. Check HW configuration.\n", + val); } - val = 8; + val = (hsotg->hw_params.utmi_phy_data_width == + GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); retval = -EINVAL; } @@ -2660,6 +2675,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); + hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> + GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; /* fifo sizes */ hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> @@ -2684,6 +2701,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) hw->hs_phy_type); dev_dbg(hsotg->dev, " fs_phy_type=%d\n", hw->fs_phy_type); + dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n", + hw->utmi_phy_data_width); dev_dbg(hsotg->dev, " num_dev_ep=%d\n", hw->num_dev_ep); dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", diff --git a/drivers/staging/dwc2/core.h b/drivers/staging/dwc2/core.h index e4eb3a0d0b5b..ecfcad83f767 100644 --- a/drivers/staging/dwc2/core.h +++ b/drivers/staging/dwc2/core.h @@ -239,6 +239,10 @@ struct dwc2_core_params { * 2 - FS pins shared with UTMI+ pins * 3 - FS pins shared with ULPI pins * @total_fifo_size: Total internal RAM for FIFOs (bytes) + * @utmi_phy_data_width UTMI+ PHY data width + * 0 - 8 bits + * 1 - 16 bits + * 2 - 8 or 16 bits * @snpsid: Value from SNPSID register */ struct dwc2_hw_params { @@ -263,6 +267,7 @@ struct dwc2_hw_params { unsigned num_dev_perio_in_ep:4; unsigned total_fifo_size:16; unsigned power_optimized:1; + unsigned utmi_phy_data_width:2; u32 snpsid; }; diff --git a/drivers/staging/dwc2/hw.h b/drivers/staging/dwc2/hw.h index fafdc199b2b5..9c92a3c7588a 100644 --- a/drivers/staging/dwc2/hw.h +++ b/drivers/staging/dwc2/hw.h @@ -302,6 +302,9 @@ #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 #define GHWCFG4_XHIBER (1 << 7) #define GHWCFG4_HIBER (1 << 6) #define GHWCFG4_MIN_AHB_FREQ (1 << 5) diff --git a/drivers/staging/dwc2/pci.c b/drivers/staging/dwc2/pci.c index fdfbc719663c..9020260d5df8 100644 --- a/drivers/staging/dwc2/pci.c +++ b/drivers/staging/dwc2/pci.c @@ -74,7 +74,7 @@ static const struct dwc2_core_params dwc2_module_params = { .max_packet_count = 511, .host_channels = -1, .phy_type = -1, - .phy_utmi_width = 16, /* 16 bits - NOT DETECTABLE */ + .phy_utmi_width = -1, .phy_ulpi_ddr = -1, .phy_ulpi_ext_vbus = -1, .i2c_enable = -1, |