diff options
| -rw-r--r-- | arch/arm/mach-zynq/slcr.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 44a4ab62e9a8..1836d5a34606 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void) */ void zynq_slcr_cpu_start(int cpu) { - /* enable CPUn */ - writel(SLCR_A9_CPU_CLKSTOP << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); - /* enable CLK for CPUn */ - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_RST << cpu); + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu) */ void zynq_slcr_cpu_stop(int cpu) { - /* stop CLK and reset CPUn */ - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** |