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-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml22
-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml48
-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt5
-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml78
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.yaml13
6 files changed, 166 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml
new file mode 100644
index 000000000000..a3dc04ec9c54
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,imx-sc-secvio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX Security Violation driver
+
+maintainers:
+ - Franck LENORMAND <franck.lenormand@nxp.com>
+
+description: |
+ Receive security violation from the SNVS via the SCU firmware. Allow to
+ register notifier for additional processing
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx-sc-secvio
+
+required:
+ - compatible
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
index b5cb374dc47d..10a91cc8b997 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
@@ -8,7 +8,7 @@ Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
- reg : should contain base address and length of DCFG memory-mapped registers
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml
new file mode 100644
index 000000000000..fe2c2b69b63c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,s400-api.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,s400-api.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S400 Baseline API module
+
+maintainers:
+ - Alice Guo <alice.guo@nxp.com>
+
+description: |
+ In the Sentinel application, the security subsystem uses S4 MU-AP to
+ communicate and coordinate with the SoC host processor. The s400-api firmware
+ driver provides the services to transmit data to and receive data from the
+ S4 MU-AP.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8ulp-s400
+
+ mboxes:
+ description: |
+ Use the mailbox provided by S4 MU-AP device to communicate with the S400.
+ It should contain 2 mailboxes, one for transmitting messages and another
+ for receiving.
+ maxItems: 1
+
+ mbox-names:
+ items:
+ - const: tx
+ - const: rx
+
+required:
+ - compatible
+ - mboxes
+ - mbox-names
+
+additionalProperties: false
+
+examples:
+ - |
+ s400-api {
+ compatible = "fsl,imx8ulp-s400";
+ mboxes = <&s4muap 0 0 &s4muap 1 0>;
+ mbox-names = "tx", "rx";
+ };
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index bcf3ab532797..f8a15c8eb86e 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -134,7 +134,9 @@ RTC bindings based on SCU Message Protocol
------------------------------------------------------------
Required properties:
-- compatible: should be "fsl,imx8qxp-sc-rtc";
+- compatible: should be one of:
+ "fsl,imx8dxl-sc-rtc";
+ "fsl,imx8qxp-sc-rtc";
Optional Child nodes:
@@ -147,6 +149,7 @@ OCOTP bindings based on SCU Message Protocol
------------------------------------------------------------
Required properties:
- compatible: Should be one of:
+ "fsl,imx8dxl-scu-ocotp",
"fsl,imx8qm-scu-ocotp",
"fsl,imx8qxp-scu-ocotp".
- #address-cells: Must be 1. Contains byte index
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml
new file mode 100644
index 000000000000..c36bea2079c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,seco_mu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8 SECO MU driver
+
+maintainers:
+ - Aisheng Dong <aisheng.dong@nxp.com>
+
+description: |
+ Create char devices in /dev as channels of the form /dev/seco_muXchY with X
+ the id of the driver and Y for each users. It allows to send and receive
+ messages to the SECO.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx-seco-mu
+
+ mboxes:
+ description:
+ List of <&phandle type channel> - 4 channels for TX, 4 channels for RX,
+ 1 channel for TXDB (see mailbox/fsl,mu.txt)
+ maxItems: 9
+
+ mbox-names:
+ items:
+ - const: txdb
+ - const: rxdb
+
+ fsl,seco_mu_id:
+ description:
+ Identify the driver instance, used to create the channels, default to 1
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0,1,2,3]
+
+ fsl,seco_max_users:
+ description:
+ Number of channels to create, default to 4
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0,1,2,3,4,5,6,7,8,9]
+
+ fsl,cmd_tag:
+ description:
+ Tag in message header for commands on this MU, default to 0x17
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint8
+ - enum: [0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e]
+
+ fsl,rsp_tag:
+ description:
+ Tag in message header for responses on this MU, default to 0xe1
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint8
+ - enum: [0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8]
+
+required:
+ - compatible
+ - mboxes
+ - mbox-names
+
+examples:
+ - |
+ seco_mu: seco_mu {
+ compatible = "fsl,imx-seco-mu";
+ mbox-names = "txdb", "rxdb";
+ mboxes = <&mu 2 0
+ &mu 3 0>;
+
+ fsl,seco_mu_id = <1>;
+ fsl,seco_max_users = <4>;
+ fsl,cmd_tag = /bits/ 8 <0x17>;
+ fsl,rsp_tag = /bits/ 8 <0xe1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 60f4862ba15e..1346c9cc0f37 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -706,6 +706,12 @@ properties:
- fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit
- const: fsl,imx7ulp
+ - description: i.MX8DXL based Boards
+ items:
+ - enum:
+ - fsl,imx8dxl-evk # i.MX8DXL EVK Board
+ - const: fsl,imx8dxl
+
- description: i.MX8MM based Boards
items:
- enum:
@@ -822,6 +828,12 @@ properties:
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
+ - description: i.MX8ULP based Boards
+ items:
+ - enum:
+ - fsl,imx8ulp-evk # i.MX8ULP EVK Board
+ - const: fsl,imx8ulp
+
- description:
Freescale Vybrid Platform Device Tree Bindings
@@ -886,6 +898,7 @@ properties:
- enum:
- fsl,ls1021a-moxa-uc-8410a
- fsl,ls1021a-qds
+ - fsl,ls1021a-tsn
- fsl,ls1021a-twr
- const: fsl,ls1021a