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-rw-r--r--Documentation/devicetree/bindings/display/bridge/sec_dsim.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
index 9bc5e9dd2539..fd4246136d37 100644
--- a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
+++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt
@@ -16,6 +16,9 @@ Required properties:
"pll-ref" - DSIM PHY PLL reference clock
- assigned-clocks: phandles to clocks that requires initial configuration
- assigned-clock-rates: rates of the clocks that requires initial configuration
+- pref-clk: Assign DPHY PLL reference clock frequency. If not exists,
+ DSIM bridge driver will use the default lock frequency
+ which is 27MHz.
- port: input and output port nodes with endpoint definitions as
defined in Documentation/devicetree/bindings/graph.txt;
the input port should be connected to an encoder or a