diff options
Diffstat (limited to 'Documentation/devicetree/bindings/dma')
| -rw-r--r-- | Documentation/devicetree/bindings/dma/fsl-edma-v3.txt | 126 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/dma/fsl-edma.txt | 36 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/dma/fsl-imx-dma.txt | 15 |
3 files changed, 171 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt new file mode 100644 index 000000000000..54982ce162b8 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt @@ -0,0 +1,126 @@ +* Freescale enhanced Direct Memory Access(eDMA-v3) Controller + + The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated + on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by + programmble memory-mapped registers. Specific DMA request source has fixed channel. + +* eDMA Controller +Required properties: +- compatible : + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC + - "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM + - "fsl,imx8ulp-edma" for eDMA used on i.MX8ULP +- reg : Specifies base physical address(s) and size of the eDMA channel registers. + Each eDMA channel has separated register's address and size. The first one + is Manage Page address space. +- interrupts : A list of interrupt-specifiers, each channel has one interrupt. +- interrupt-names : Should contain below template: + "edmaX-chanX-Xx" + | | |---> receive/transmit, r or t + | |---> channel id, the max number is 32 + |---> edma controller instance, 0, 1, 2,..etc + +- #dma-cells : Must be <3>. + The 1st cell specifies the channel ID, but source/event id on i.mx8ulp + The 2nd cell specifies the channel priority. + The 3rd cell specifies the channel attributes which include below: + BIT(0): transmit or receive: + 0: transmit, 1: receive. + BIT(1): local or remote access: + 0: local, 1: remote. + BIT(2): dualfifo case or not(only in Audio cyclic now): + 0: not dual fifo case, 1: dualfifo case. + See the SoC's reference manual for all the supported request sources. +- dma-channels : Number of channels supported by the controller + +Optional properties : +- power-domains: Power domains for edma channel used. +- power-domain-names: Power domains name for edma channel used. +- clocks : A list of phandle and clock-specifier pairs, one for each entry in + clock-names. The first one is for Manage Page +- clock-names : A list of channel clock names. + +Examples: +edma0: dma-controller@40018000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <4>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15"; + status = "okay"; +}; + +or i.mx8ulp: + edma1: dma-controller@29010000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x29010000 0x10000>, + <0x29020000 0x10000>, + <0x29030000 0x10000>; + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma1-chan0-tx", + "edma1-chan1-tx"; + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, + <&pcc3 IMX8ULP_CLK_DMA1_CH1>; + clock-names = "edma-mp-clk", + "edma1-chan0-clk", + "edma1-chan1-clk"; + status = "okay"; + }; + +* DMA clients +DMA client drivers that uses the DMA function must use the format described +in the dma.txt file, using a three-cell specifier for each channel: the 1st +specifies the channel number, the 2nd specifies the priority, and the 3rd +specifies the channel type is for transmit or receive: 0: transmit, 1: receive. + +Examples: +lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>; + clock-names = "ipg"; + assigned-clock-names = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>, + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; +}; + +or i.mx8ulp: +lpuart5: serial@293a0000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x293a0000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_LPOSC>; + assigned-clock-rates = <24000000>; + dmas = <&edma1 58 0 0>, <&edma1 57 0 1>; + dma-names = "tx","rx"; + + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index ee1754739b4b..4c1d66a62083 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -12,13 +12,14 @@ Required properties: - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the LS1028A SoC. + - "fsl,s32v234-edma" for eDMA used similar to that on S32V234 SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing control register's address and size. - interrupts : A list of interrupt-specifiers, one for each entry in - interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel - per transmission interrupt, total 16 channel interrupt and 1 + interrupt-names on SoCs similar to vf610 or S32V234. But for i.mx7ulp + per channel per transmission interrupt, total 16 channel interrupt and 1 error interrupt(located in the last), no interrupt-names list on i.mx7ulp for clean on dts. - #dma-cells : Must be <2>. @@ -39,10 +40,15 @@ Optional properties: - big-endian: If present registers and hardware scatter/gather descriptors of the eDMA are implemented in big endian mode, otherwise in little mode. -- interrupt-names : Should contain the below on vf610 similar SoC but not used - on i.mx7ulp similar SoC: - "edma-tx" - the transmission interrupt - "edma-err" - the error interrupt +- interrupt-names : Should contain the entries below: + - on vf610 similar SoC: + "edma-tx" - the transmission interrupt + "edma-err" - the error interrupt + - on S32V234 similar SoC: + "edma-tx_0-15" - the transmission interrupt for CH0-15 + "edma-tx_16-31" - the transmission interrupt for CH16-31 + "edma-err" - the error interrupt for CH0-31 + - not used on i.mx7ulp similar SoC. Examples: @@ -91,6 +97,24 @@ edma1: dma-controller@40080000 { <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; /* i.mx7ulp */ +edma: dma-controller@40002000 { + #dma-cells = <2>; + compatible = "fsl,s32v234-edma"; + reg = <0x0 0x40002000 0x0 0x2000>, + <0x0 0x40031000 0x0 0x1000>, + <0x0 0x400A1000 0x0 0x1000>; + dma-channels = <32>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx_0-15", + "edma-tx_16-31", + "edma-err"; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks S32V234_CLK_SYS6>, + <&clks S32V234_CLK_SYS6>; +}; /* S32V234 */ + * DMA clients DMA client drivers that uses the DMA function must use the format described in the dma.txt file, using a two-cell specifier for each channel: the 1st diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt index 7bd8847d6394..d10a9c1d2ce6 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt @@ -16,6 +16,21 @@ Optional properties: - #dma-channels : Number of DMA channels supported. Should be 16. - #dma-requests : Number of DMA requests supported. +* DMA capability limitation + +Specify the DMA capability limitations. +For example, some SoCs only support up to 32bit DMA capability, although +they are 64bit SoCs. + +- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA + capability. + +Example: + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + Example: dma: dma@10001000 { |