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-rw-r--r--Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt8
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index 4c32ef0b7db8..009f4bfa1590 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -197,7 +197,9 @@ of the following host1x client modules:
- sor: serial output resource
Required properties:
- - compatible: "nvidia,tegra124-sor"
+ - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
+ must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
+ is tegra132.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
@@ -222,7 +224,9 @@ of the following host1x client modules:
- nvidia,dpaux: phandle to a DispayPort AUX interface
- dpaux: DisplayPort AUX interface
- - compatible: "nvidia,tegra124-dpaux"
+ - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
+ must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
+ <chip> is tegra132.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.