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Diffstat (limited to 'Documentation/devicetree/bindings/media')
3 files changed, 213 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/media/imx8-isi.txt b/Documentation/devicetree/bindings/media/imx8-isi.txt new file mode 100644 index 000000000000..7739121f0ca6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-isi.txt @@ -0,0 +1,33 @@ +NXP Image Sensor Interface +======================== + +The Image Sensor Interface (ISI) is used to obtain the image data for +processing in its pipeline channels. Each pipeline processes the image +line from a configured source and performs one or more functions that +are configured by software, such as down scaling, color space conversion, +de-interlacing, alpha insertion, cropping and rotation (horizontal and +vertical). The processed image is stored into programmable memory locations. + +Required properties: +- compatible: should be "fsl,imx8-isi", where SoC can be one of imx8qxp, imx8qm +- reg: the register base and size for the device registers +- interrupts: the ISI interrupt, high level active +- clock-names: should be "per" +- clocks: the ISI AXI clock +- interface: specify ISI input, virtual channel and output, + <Input MIPI_VCx Output> + Input : 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx : 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM + +Example: + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&img_lpcg IMX_IMG_LPCG_PDMA0_CLK>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + }; diff --git a/Documentation/devicetree/bindings/media/imx8-jpeg.txt b/Documentation/devicetree/bindings/media/imx8-jpeg.txt new file mode 100644 index 000000000000..16b01daa7a2a --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-jpeg.txt @@ -0,0 +1,107 @@ +Freescale i.MX8QXP/QM JPEG encoder/decoder +========================= + +jpegdec node +-------------- + +This is the device node for the JPEG decoder in i.MXQXP/QM SoC, an +ISO/IEC 10918-1 JPEG standard compliant decoder, for Baseline +and Extended Sequential DCT modes. + +Required properties: + +- compatible : "fsl,imx8-jpgdec"; +- reg : base address and length of the register set for the device; +- interrupts : list of interrupts for jpeg decoder +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- assigned-clock-rates : the value should be 200MHz; +- power-domains : a list of phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; + + +Optional properties: +- clock-names : must contain clock names to match entries in the + clock property; +- power-domain-name : must contain matching names for entries in the + the power-domains property. + + +example: + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + power-domain-names = "pd_isi_ch0", "pd_dec_mp", + "pd_dec_s0", "pd_dec_s1", + "pd_dec_s2", "pd_dec_s3"; + status = "disabled"; + + +jpegenc node +-------------- + +This is the device node for the JPEG encoder in i.MXQXP/QM SoC, +similar with the JPEG decoder above. + +Required properties: + +- compatible : "fsl,imx8-jpgenc"; +- reg : base address and length of the register set for the device; +- interrupts : list of interrupts for jpeg encoder +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- assigned-clock-rates : the value should be 200MHz; +- power-domains : a list of phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; + + +Optional properties: +- clock-names : must contain clock names to match entries in the + clock property; +- power-domain-name : must contain matching names for entries in the + the power-domains property. + + +example: + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + power-domain-names = "pd_isi_ch0", "pd_enc_mp", + "pd_enc_s0", "pd_enc_s1", + "pd_enc_s2", "pd_enc_s3"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt b/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt new file mode 100644 index 000000000000..3c69e3e52b8c --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt @@ -0,0 +1,73 @@ +Freescale i.MX8QXP/QM MIPI CSI2 +========================= + +mipi_csi2 node +-------------- + +This is the device node for the MIPI CSI-2 receiver core in i.MXQXP/QM SoC. + +Required properties: + +- compatible : "fsl,mxc-mipi-csi2"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- clock-names : must contain "clk_core", "clk_esc" and "clk_pxl" entries, + matching entries in the clock property; +- assigned-clock-rates : the value should be 360MHz and 72MHz; +- power-domains : a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; +- power-domain-name : must contain "pd_csi", "pd_isi_ch0". + +Optional properties: +- virtual-channel: whether use mipi csi virtual channel + +The device node should contain one 'port' child nodes with one child 'endpoint' +node, according to the bindings defined in: + Documentation/devicetree/bindings/ media/video-interfaces.txt. + The following are properties specific to those nodes. + +port node +--------- + +- reg : (required) can take the values 0 which mean the port is a + sink port; + +endpoint node +------------- + +- data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; this + shall only be applied to port 0 (sink port), the array's + content is unused only its length is meaningful, + in this case the maximum length supported is 2; + +example: + + mipi_csi: csi@58227000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>, + <&img_lpcg IMX_IMG_LPCG_CSI0_PXL_LINK_CLK>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; + + }; |