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-rw-r--r--Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml7
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
index a24588474625..d4d5851cb981 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
@@ -12,13 +12,13 @@ maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
- The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
- 32-bit bus width configurations.
+ The ZynqMP and i.MX8MP DDR ECC controller has an optional ECC support in 64-bit
+ and 32-bit bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
- These both ECC controllers correct single bit ECC errors and detect double bit
+ These all ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
properties:
@@ -26,6 +26,7 @@ properties:
enum:
- xlnx,zynq-ddrc-a05
- xlnx,zynqmp-ddrc-2.40a
+ - fsl,imx8mp-ddrc
interrupts:
maxItems: 1