diff options
Diffstat (limited to 'Documentation/devicetree/bindings/net')
10 files changed, 503 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 16aa192c118e..2ad7f79ad371 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -46,6 +46,9 @@ patternProperties: type: object description: Ethernet switch ports + allOf: + - $ref: "http://devicetree.org/schemas/net/ethernet-controller.yaml#" + properties: reg: description: Port number @@ -73,11 +76,14 @@ patternProperties: dsa-tag-protocol: description: Instead of the default, the switch will use this tag protocol if - possible. Useful when a device supports multiple protcols and + possible. Useful when a device supports multiple protocols and the default is incompatible with the Ethernet device. enum: - dsa - edsa + - ocelot + - ocelot-8021q + - seville phy-handle: true @@ -91,6 +97,10 @@ patternProperties: managed: true + rx-internal-delay-ps: true + + tx-internal-delay-ps: true + required: - reg diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml index f978f8719d8e..24cd733c11d1 100644 --- a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml +++ b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml @@ -74,10 +74,42 @@ properties: - compatible - reg +patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + allOf: + - if: + properties: + phy-mode: + contains: + enum: + - rgmii + - rgmii-rxid + - rgmii-txid + - rgmii-id + then: + properties: + rx-internal-delay-ps: + $ref: "#/$defs/internal-delay-ps" + tx-internal-delay-ps: + $ref: "#/$defs/internal-delay-ps" + required: - compatible - reg +$defs: + internal-delay-ps: + description: + Disable tunable delay lines using 0 ps, or enable them and select + the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps + (101.7 degree shift) in increments of 0.9 degrees (20 ps). + enum: + [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840, + 1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080, + 2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260] + unevaluatedProperties: false examples: @@ -97,29 +129,40 @@ examples: port@0 { phy-handle = <&rgmii_phy6>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <0>; }; port@1 { phy-handle = <&rgmii_phy3>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <1>; }; port@2 { phy-handle = <&rgmii_phy4>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <2>; }; port@3 { + phy-handle = <&rgmii_phy4>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <3>; }; port@4 { ethernet = <&enet2>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <4>; fixed-link { diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 8c73f67c43ca..f057117764af 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,9 +3,10 @@ Required properties: - compatible: should be one of: - "qca,qca8327" - "qca,qca8334" - "qca,qca8337" + "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package + "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package + "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package + "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package - #size-cells: must be 0 - #address-cells: must be 1 @@ -13,6 +14,17 @@ Required properties: Optional properties: - reset-gpios: GPIO to be used to reset the whole device +- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open + drain or eeprom presence. This is needed for broken + devices that have wrong configuration or when the oem + decided to not use pin strapping and fallback to sw + regs. +- qca,led-open-drain: Set leds to open-drain mode. This requires the + qca,ignore-power-on-sel to be set or the driver will fail + to probe. This is needed if the oem doesn't use pin + strapping to set this mode and prefers to set it using sw + regs. The pin strapping related to led open drain mode is + the pin B68 for QCA832x and B49 for QCA833x Subnodes: @@ -29,7 +41,11 @@ the mdio MASTER is used as communication. Don't use mixed external and internal mdio-bus configurations, as this is not supported by the hardware. -The CPU port of this switch is always port 0. +This switch support 2 CPU port. Normally and advised configuration is with +CPU port set to port 0. It is also possible to set the CPU port to port 6 +if the device requires it. The driver will configure the switch to the defined +port. With both CPU port declared the first CPU port is selected as primary +and the secondary CPU ignored. A CPU port node has the following optional node: @@ -37,6 +53,20 @@ A CPU port node has the following optional node: managed entity. See Documentation/devicetree/bindings/net/fixed-link.txt for details. +- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. + Mostly used in qca8327 with CPU port 0 set to + sgmii. +- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. +- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX + chain along with Signal Detection. + This should NOT be enabled for qca8327. If enabled with + qca8327 the sgmii port won't correctly init and an err + is printed. + This can be required for qca8337 switch with revision 2. + A warning is displayed when used with revision greater + 2. + With CPU port set to sgmii and qca8337 it is advised + to set this unless a communication problem is observed. For QCA8K the 'fixed-link' sub-node supports only the following properties: diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt index b6ae8541bd55..7959ec237983 100644 --- a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt +++ b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt @@ -9,6 +9,7 @@ SMI-based Realtek devices. Required properties: - compatible: must be exactly one of: + "realtek,rtl8365mb" (4+1 ports) "realtek,rtl8366" "realtek,rtl8366rb" (4+1 ports) "realtek,rtl8366s" (4+1 ports) @@ -62,6 +63,8 @@ and subnodes of DSA switches. Examples: +An example for the RTL8366RB: + switch { compatible = "realtek,rtl8366rb"; /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ @@ -151,3 +154,87 @@ switch { }; }; }; + +An example for the RTL8365MB-VC: + +switch { + compatible = "realtek,rtl8365mb"; + mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + + switch_intc: interrupt-controller { + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + port@0 { + reg = <0>; + label = "swp0"; + phy-handle = <ðphy0>; + }; + port@1 { + reg = <1>; + label = "swp1"; + phy-handle = <ðphy1>; + }; + port@2 { + reg = <2>; + label = "swp2"; + phy-handle = <ðphy2>; + }; + port@3 { + reg = <3>; + label = "swp3"; + phy-handle = <ðphy3>; + }; + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: phy@0 { + reg = <0>; + interrupt-parent = <&switch_intc>; + interrupts = <0>; + }; + ethphy1: phy@1 { + reg = <1>; + interrupt-parent = <&switch_intc>; + interrupts = <1>; + }; + ethphy2: phy@2 { + reg = <2>; + interrupt-parent = <&switch_intc>; + interrupts = <2>; + }; + ethphy3: phy@3 { + reg = <3>; + interrupt-parent = <&switch_intc>; + interrupts = <3>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index b0933a8c295a..953562d89c89 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -32,6 +32,15 @@ properties: - minItems: 6 maxItems: 6 + nvmem-mac-address: + allOf: + - $ref: /schemas/types.yaml#definitions/uint8-array + - minItems: 6 + maxItems: 6 + description: + Specifies the MAC address that was read from nvmem-cells and dynamically + add the property in device node; + max-frame-size: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -52,6 +61,11 @@ properties: nvmem-cell-names: const: mac-address + nvmem_macaddr_swap: + $ref: /schemas/types.yaml#/definitions/flag + description: + swap bytes order for the 6 bytes of MAC address + phy-connection-type: description: Specifies interface type between the Ethernet device and a physical diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml index eca41443fcce..7f5dc9a82888 100644 --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml @@ -164,6 +164,12 @@ properties: req_gpr is the gpr register offset for ENET stop request. req_bit is the gpr bit offset for ENET stop request. + mii-exclusive: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present, each MAC has their exclusive MDIO bus in current board + design, otherwise multiple MACs share one MDIO bus to reduce Pins utilize. + mdio: type: object description: diff --git a/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt new file mode 100644 index 000000000000..4b38312c9b7f --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt @@ -0,0 +1,199 @@ +============================================================================= +NXP Programmable Packet Forwarding Engine Device Bindings + +CONTENTS + - PFE Node + - Ethernet Node + +============================================================================= +PFE Node + +DESCRIPTION + +PFE Node has all the properties associated with Packet Forwarding Engine block. + +PROPERTIES + +- compatible + Usage: required + Value type: <stringlist> + Definition: Must include "fsl,pfe" + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. + Specifies the offset of the following registers: + - PFE configuration registers + - DDR memory used by PFE + +- fsl,pfe-num-interfaces + Usage: required + Value type: <u32> + Definition: Must be present. Value can be either one or two. + +- interrupts + Usage: required + Value type: <prop-encoded-array> + Definition: Three interrupts are specified in this property. + - HIF interrupt + - HIF NO COPY interrupt + - Wake On LAN interrupt + +- interrupt-names + Usage: required + Value type: <stringlist> + Definition: Following strings are defined for the 3 interrupts. + "pfe_hif" - HIF interrupt + "pfe_hif_nocpy" - HIF NO COPY interrupt + "pfe_wol" - Wake On LAN interrupt + +- memory-region + Usage: required + Value type: <phandle> + Definition: phandle to a node describing reserved memory used by pfe. + Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +- fsl,pfe-scfg + Usage: required + Value type: <phandle> + Definition: phandle for scfg. + +- fsl,rcpm-wakeup + Usage: required + Value type: <phandle> + Definition: phandle for rcpm. + +- clocks + Usage: required + Value type: <phandle> + Definition: phandle for clockgen. + +- clock-names + Usage: required + Value type: <string> + Definition: phandle for clock name. + +EXAMPLE + +pfe: pfe@04000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + pfe_mac0: ethernet@0 { + }; + + pfe_mac1: ethernet@1 { + }; +}; + +============================================================================= +Ethernet Node + +DESCRIPTION + +Ethernet Node has all the properties associated with PFE used by platforms to +connect to PHY: + +PROPERTIES + +- compatible + Usage: required + Value type: <stringlist> + Definition: Must include "fsl,pfe-gemac-port" + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. + Specifies the gemacid of the interface. + +- fsl,gemac-bus-id + Usage: required + Value type: <u32> + Definition: Must be present. Value should be the id of the bus + connected to gemac. + +- fsl,gemac-phy-id (deprecated binding) + Usage: required + Value type: <u32> + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be the id of the phy + connected to gemac. + +- fsl,mdio-mux-val + Usage: required + Value type: <u32> + Definition: Must be present. Value can be either 0 or 2 or 3. + This value is used to configure the mux to enable mdio. + +- phy-mode + Usage: required + Value type: <string> + Definition: Must include "sgmii" + +- fsl,pfe-phy-if-flags (deprecated binding) + Usage: required + Value type: <u32> + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be 0 by default. + If there is not phy connected, this need to be 1. + +- phy-handle + Usage: optional + Value type: <phandle> + Definition: phandle to the PHY device connected to this device. + +- mdio : A required subnode which specifies the mdio bus in the PFE and used as +a container for phy nodes according to ../phy.txt. + +EXAMPLE + +ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; +}; + + +ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,gemac-bus-id = <0x1>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; +}; + +mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; +}; diff --git a/Documentation/devicetree/bindings/net/imx-shmem-net.txt b/Documentation/devicetree/bindings/net/imx-shmem-net.txt new file mode 100644 index 000000000000..e1fe220c5a41 --- /dev/null +++ b/Documentation/devicetree/bindings/net/imx-shmem-net.txt @@ -0,0 +1,37 @@ +i.MX SHMEM-NET implementations + +A network device to communicate with another domain. +Communication is done through shared memory + and synchronized by Mailbox Units of imx. +Use Mailbox Units side A to communicate with side B. + +Required properties: +- compatible : "fsl,imx-shmem-net". +- rxfirst: The flag that indicates the position of the RX buffer, + one of the two partitions must set it. +- mub-partition: The id number of the remote processors, + used on i.mx8qm for partition reset. The default + value is 3 in driver without this property. +- mbox-names: the mailbox channel names. +- mboxes: the mailboxes list containing: + MU name, channel type (0 for TX, 1 for RX) and channel id. +- memory-region: the coherent memory shared across domains. + +===================================================================== + +Example: + +imx_shmem_net: imx_shmem_net { + compatible = "fsl,imx-shmem-net"; + mub-partition = <1>; + mbox-names = "tx", "rx"; + mboxes = <&lsio_mu8b 0 1 + &lsio_mu8b 1 1>; + status = "disabled"; +}; + +&imx_shmem_net{ + memory-region = <&shmem_dma_reserved>; + status = "okay"; +}; + diff --git a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml index 948677ade6d1..d7748dd33199 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml @@ -51,6 +51,9 @@ examples: switch@10 { compatible = "qca,qca8337"; reg = <0x10>; - /* ... */ + + ports { + /* ... */ + }; }; }; diff --git a/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml b/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml new file mode 100644 index 000000000000..9565b0e8e7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/nxp,wifi-wake-host.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/nxp,wifi-wake-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP 89xx wireless devices + +maintainers: + - Sherry Sun <sherry.sun@nxp.com> + +description: + This node provides properties for controlling the NXP 89XX wireless device. + The node is expected to be specified as a child node to the PCIE/SDIO + controller that connects the device to the system. + +properties: + compatible: + const: nxp,wifi-wake-host + + interrupts: + maxItems: 1 + description: | + Specifies attributes for the out-of-band interrupt (host-wake). + + interrupt-names: + const: host-wake + description: | + Name of the out-of-band interrupt, which must be set to "host-wake". + +required: + - compatible + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mq-clock.h> + + pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + disable-gpio = <&gpio5 10 1>; + reset-gpio = <&gpio5 12 1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_250M>; + vph-supply = <&vgen5_reg>; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpio5>; + interrupts = <11 8>; + interrupt-names = "host-wake"; + }; + }; |