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-rw-r--r--Documentation/devicetree/bindings/serial/8250.yaml30
-rw-r--r--Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml95
-rw-r--r--Documentation/devicetree/bindings/serial/mtk-uart.txt1
-rw-r--r--Documentation/devicetree/bindings/serial/samsung_uart.yaml18
-rw-r--r--Documentation/devicetree/bindings/serial/serial.yaml12
-rw-r--r--Documentation/devicetree/bindings/serial/st,stm32-uart.yaml59
6 files changed, 196 insertions, 19 deletions
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index f54cae9ff7b2..f0506a917793 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -12,8 +12,13 @@ maintainers:
allOf:
- $ref: /schemas/serial.yaml#
- if:
- required:
- - aspeed,sirq-polarity-sense
+ anyOf:
+ - required:
+ - aspeed,lpc-io-reg
+ - required:
+ - aspeed,lpc-interrupts
+ - required:
+ - aspeed,sirq-polarity-sense
then:
properties:
compatible:
@@ -55,6 +60,7 @@ properties:
- const: aspeed,ast2500-vuart
- const: intel,xscale-uart
- const: mrvl,pxa-uart
+ - const: nuvoton,wpcm450-uart
- const: nuvoton,npcm750-uart
- const: nvidia,tegra20-uart
- const: nxp,lpc3220-uart
@@ -165,7 +171,6 @@ properties:
property.
tx-threshold:
- $ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the TX FIFO low water indication for parts with programmable
TX FIFO thresholds.
@@ -188,6 +193,21 @@ properties:
offset and bit number to identify how the SIRQ polarity should be
configured. One possible data source is the LPC/eSPI mode bit. Only
applicable to aspeed,ast2500-vuart.
+ deprecated: true
+
+ aspeed,lpc-io-reg:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
+
+ aspeed,lpc-interrupts:
+ $ref: "/schemas/types.yaml#/definitions/uint32-array"
+ minItems: 2
+ maxItems: 2
+ description: |
+ A 2-cell property describing the VUART SIRQ number and SIRQ
+ polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
+ applicable to aspeed,ast2500-vuart.
required:
- reg
@@ -220,6 +240,7 @@ examples:
};
- |
#include <dt-bindings/clock/aspeed-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
@@ -227,7 +248,8 @@ examples:
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
- aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
+ aspeed,lpc-io-reg = <0x3f8>;
+ aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
...
diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml
new file mode 100644
index 000000000000..46c62745f901
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom 8250 based serial port devicetree bindings
+
+maintainers:
+ - Al Cooper <alcooperx@gmail.com>
+
+allOf:
+ - $ref: /schemas/serial.yaml#
+
+description: |+
+ The Broadcom UART is based on the basic 8250 UART but with
+ enhancements for more accurate high speed baud rates and support
+ for DMA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm7271-uart
+ - brcm,bcm7278-uart
+
+ reg:
+ minItems: 1
+ maxItems: 5
+
+ reg-names:
+ description: The UART register block and optionally the DMA register blocks.
+ oneOf:
+ - items:
+ - const: uart
+ - items:
+ - const: uart
+ - const: dma_arb
+ - const: dma_rx
+ - const: dma_tx
+ - const: dma_intr2
+
+ clocks:
+ minItems: 1
+
+ clock-names:
+ const: sw_baud
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ description: The UART interrupt and optionally the DMA interrupt.
+ minItems: 1
+ items:
+ - const: uart
+ - const: dma
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial@840d000 {
+ compatible = "brcm,bcm7271-uart";
+ reg = <0x840d000 0x20>;
+ reg-names = "uart";
+ interrupts = <0x0 0x62 0x4>;
+ interrupt-names = "uart";
+ clocks = <&scmi_clk 190>;
+ clock-names = "sw_baud";
+ };
+
+ serial@840e000 {
+ compatible = "brcm,bcm7271-uart";
+ reg = <0x840e000 0x20>,
+ <0x840e080 0x8>,
+ <0x840e100 0xa8>,
+ <0x840e200 0x4c>,
+ <0x840e300 0x30>;
+ reg-names = "uart", "dma_arb", "dma_rx", "dma_tx", "dma_intr2";
+ interrupts = <0x0 0x62 0x4>, <0x0 0x75 0x4>;
+ interrupt-names = "uart", "dma";
+ clocks = <&scmi_clk 190>;
+ clock-names = "sw_baud";
+ };
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 647b5aee86f3..64c4fb59acd1 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -20,6 +20,7 @@ Required properties:
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
+ * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
* "mediatek,mt8516-uart" for MT8516 compatible UARTS
* "mediatek,mt6577-uart" for MT6577 and all of the above
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index 21ee627b2ced..97ec8a093bf3 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Samsung S3C, S5P and Exynos SoC UART Controller
+title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
@@ -19,6 +19,7 @@ properties:
compatible:
items:
- enum:
+ - apple,s5l-uart
- samsung,s3c2410-uart
- samsung,s3c2412-uart
- samsung,s3c2440-uart
@@ -51,6 +52,16 @@ properties:
- pattern: '^clk_uart_baud[0-3]$'
- pattern: '^clk_uart_baud[0-3]$'
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for RX
+ - description: DMA controller phandle and request line for TX
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
interrupts:
description: RX interrupt and optionally TX interrupt.
minItems: 1
@@ -68,9 +79,11 @@ required:
- interrupts
- reg
-additionalProperties: false
+unevaluatedProperties: false
allOf:
+ - $ref: /schemas/serial.yaml#
+
- if:
properties:
compatible:
@@ -96,6 +109,7 @@ allOf:
compatible:
contains:
enum:
+ - apple,s5l-uart
- samsung,exynos4210-uart
then:
properties:
diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml
index 65e75d040521..2fdf4ed198da 100644
--- a/Documentation/devicetree/bindings/serial/serial.yaml
+++ b/Documentation/devicetree/bindings/serial/serial.yaml
@@ -75,6 +75,16 @@ properties:
type: boolean
description: CTS and RTS pins are swapped.
+ rx-threshold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ RX FIFO threshold configuration (in bytes).
+
+ tx-threshold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ TX FIFO threshold configuration (in bytes).
+
if:
required:
- uart-has-rtscts
@@ -134,7 +144,7 @@ examples:
interrupts = <1>;
bluetooth {
- compatible = "brcm,bcm43341-bt";
+ compatible = "brcm,bcm4330-bt";
interrupt-parent = <&gpio>;
interrupts = <10>;
};
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 8631678283f9..71a6426bc558 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -9,9 +9,6 @@ maintainers:
title: STMicroelectronics STM32 USART bindings
-allOf:
- - $ref: rs485.yaml
-
properties:
compatible:
enum:
@@ -40,6 +37,8 @@ properties:
uart-has-rtscts: true
+ rx-tx-swap: true
+
dmas:
minItems: 1
maxItems: 2
@@ -66,13 +65,46 @@ properties:
linux,rs485-enabled-at-boot-time: true
rs485-rx-during-tx: true
-if:
- required:
- - st,hw-flow-ctrl
-then:
- properties:
- cts-gpios: false
- rts-gpios: false
+ rx-threshold:
+ description:
+ If value is set to 1, RX FIFO threshold is disabled.
+ enum: [1, 2, 4, 8, 12, 14, 16]
+ default: 8
+
+ tx-threshold:
+ description:
+ If value is set to 1, TX FIFO threshold is disabled.
+ enum: [1, 2, 4, 8, 12, 14, 16]
+ default: 8
+
+allOf:
+ - $ref: rs485.yaml#
+ - $ref: serial.yaml#
+ - if:
+ required:
+ - st,hw-flow-ctrl
+ then:
+ properties:
+ cts-gpios: false
+ rts-gpios: false
+ - if:
+ properties:
+ compatible:
+ const: st,stm32-uart
+ then:
+ properties:
+ rx-tx-swap: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32-uart
+ - st,stm32f7-uart
+ then:
+ properties:
+ rx-threshold: false
+ tx-threshold: false
required:
- compatible
@@ -80,19 +112,22 @@ required:
- interrupts
- clocks
-additionalProperties: false
+additionalProperties:
+ type: object
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
usart1: serial@40011000 {
- compatible = "st,stm32-uart";
+ compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 164>;
dmas = <&dma2 2 4 0x414 0x0>,
<&dma2 7 4 0x414 0x0>;
dma-names = "rx", "tx";
+ rx-threshold = <4>;
+ tx-threshold = <4>;
rs485-rts-active-low;
};