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-rw-r--r--Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt77
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml81
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml88
3 files changed, 246 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt b/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt
new file mode 100644
index 000000000000..f27e843a8d82
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt
@@ -0,0 +1,77 @@
+i.MX RPMSG platform implementations
+
+Distributed framework is used in IMX RPMSG implementation, refer to the
+following requirements:
+ - The CAN functions contained in M core and RTOS should be ready and
+ complete functional in 50ms after AMP system is turned on.
+ - Partition reset. System wouldn't be stalled by the exceptions (e.x
+ the reset triggered by the system hang) occurred at the other side.
+ And the RPMSG mechanism should be recovered automactilly after the
+ partition reset is completed.
+In this scenario, the M core and RTOS would be kicked off by bootloader
+firstly, then A core and Linux would be loaded later. Both M core/RTOS
+and A core/Linux are running independly.
+One physical memory region used to store the vring is mandatory required
+to pre-reserved and well-knowned by both A core and M core
+
+Required properties:
+- compatible: "fsl,imx8qxp-rpmsg", "fsl,imx8mq-rpmsg", "fsl,imx8mm-rpmsg",
+ "fsl,imx8qm-rpmsg", "fsl,imx7ulp-rpmsg", "fsl,imx7d-rpmsg",
+ "fsl,imx6sx-rpmsg".
+- vdev-nums: The number of the remote virtual devices.
+- reg: The reserved phisical DDR memory used to store vring descriptors.
+
+Optional properties:
+- rpmsg_dma_reserved: The reserved per device dma pool, that used to
+ allocate the shared memory buffers from the per device.
+ And it is optional for some platforms, since the system dma pool
+ is used to allocate the shared memory buffers directly on them.
+- mub-partition: The partition ID of muB side, that's optional
+ and used on i.mx8qm/8qxp for partition reset. The default
+ value is 3 in driver without this property.
+
+=====================================================================
+Mailbox used by iMX RPMSG
+
+- mboxes: mailboxes used in the RPMSG transactions.
+- mbox-names: names of the mailboxes used in RPMSG.
+ - "tx":TX channel with 32bit transmit register and IRQ transmit
+ - "rx":RX channel with 32bit receive register and IRQ support
+ - "rxdb":RX doorbell channel.
+
+Example:
+Rpmsg node in board dts file.
+&rpmsg{
+ /*
+ * 64K for one rpmsg instance:
+ */
+ vdev-nums = <2>;
+ reg = <0x0 0x90000000 0x0 0x20000>;
+ status = "okay";
+};
+
+SOC level dts node definitions:
+rpmsg_reserved: rpmsg@0x90000000 {
+ no-map;
+ reg = <0 0x90000000 0 0x400000>;
+};
+rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0 0x90400000 0 0x1C00000>;
+};
+rpmsg: rpmsg{
+ compatible = "fsl,imx8qxp-rpmsg";
+ /* up to now, the following channels are used in imx rpmsg
+ * - tx1/rx1: messages channel.
+ * - general interrupt1: remote proc finish re-init rpmsg stack
+ * when A core is partition reset.
+ */
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu5 0 1
+ &lsio_mu5 1 1
+ &lsio_mu5 3 1>;
+ mub-partition = <3>;
+ memory-region = <&rpmsg_dma_reserved>;
+ status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..775c08d763b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 Media blk-ctrl
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description:
+ The i.MX93 MEDIAMIX domain contains control and status registers known
+ as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include
+ clocking, reset, and miscellaneous top-level controls for peripherals
+ within the MEDIAMIX domain
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx93-media-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 10
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: nic
+ - const: disp
+ - const: cam
+ - const: pxp
+ - const: lcdif
+ - const: isi
+ - const: csi
+ - const: dsi
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx93-clock.h>
+ #include <dt-bindings/power/imx93-power.h>
+
+ media_blk_ctrl: blk_ctrl@4ac10000 {
+ compatible = "fsl,imx93-media-blk-ctrl", "syscon";
+ reg = <0x4ac10000 0x10000>;
+ power-domains = <&mediamix>;
+ clocks = <&clk IMX93_CLK_MEDIA_APB>,
+ <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_NIC_MEDIA_GATE>,
+ <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+ <&clk IMX93_CLK_CAM_PIX>,
+ <&clk IMX93_CLK_PXP_GATE>,
+ <&clk IMX93_CLK_LCDIF_GATE>,
+ <&clk IMX93_CLK_ISI_GATE>,
+ <&clk IMX93_CLK_MIPI_CSI_GATE>,
+ <&clk IMX93_CLK_MIPI_DSI_GATE>;
+ clock-names = "apb", "axi", "nic", "disp", "cam",
+ "pxp", "lcdif", "isi", "csi", "dsi";
+ #power-domain-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml
new file mode 100644
index 000000000000..d45c1458b9c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-src.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX9 System Reset Controller
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description: |
+ The System Reset Controller (SRC) is responsible for the generation of
+ all the system reset signals and boot argument latching.
+
+ Its main functions are as follows,
+ - Deals with all global system reset sources from other modules,
+ and generates global system reset.
+ - Responsible for power gating of MIXs (Slices) and their memory
+ low power control.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx93-src
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ slice:
+ type: object
+ description: list of power domains provided by this controller.
+
+ patternProperties:
+ "power-domain@[0-9]$":
+ type: object
+ properties:
+
+ '#power-domain-cells':
+ const: 0
+
+ reg:
+ description: |
+ Power domain index. Valid values are defined in
+ include/dt-bindings/power/imx93-power.h for fsl,imx93-src
+ maxItems: 1
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled
+ during domain power-up sequencing to ensure reset
+ propagation into devices located inside this power domain.
+ minItems: 1
+ maxItems: 5
+
+ required:
+ - '#power-domain-cells'
+ - reg
+
+required:
+ - compatible
+ - reg
+ - slice
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx93-clock.h>
+ #include <dt-bindings/power/imx93-power.h>
+
+ src@44460000 {
+ compatible = "fsl,imx93-src", "syscon";
+ reg = <0x44460000 0x10000>;
+
+ slice {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mediamix: power-domain@0 {
+ reg = <IMX93_POWER_DOMAIN_MEDIAMIX>;
+ #power-domain-cells = <0>;
+ clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_MEDIA_APB>;
+ };
+ };
+ };