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-rw-r--r--Documentation/sound/alsa/soc/DAI.txt358
-rw-r--r--Documentation/sound/alsa/soc/clocking.txt13
2 files changed, 271 insertions, 100 deletions
diff --git a/Documentation/sound/alsa/soc/DAI.txt b/Documentation/sound/alsa/soc/DAI.txt
index 919de76bab8d..251545a88693 100644
--- a/Documentation/sound/alsa/soc/DAI.txt
+++ b/Documentation/sound/alsa/soc/DAI.txt
@@ -12,7 +12,8 @@ The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
frame is 21uS long and is divided into 13 time slots.
-The AC97 specification can be found at http://intel.com/
+The AC97 specification can be found at :-
+http://www.intel.com/design/chipsets/audio/ac97_r23.pdf
I2S
@@ -77,16 +78,16 @@ sample rates first and then test your interface.
struct snd_soc_dai_mode is defined (in soc.h) as:-
/* SoC DAI mode */
-struct snd_soc_hw_mode {
- unsigned int fmt:16; /* SND_SOC_DAIFMT_* */
- unsigned int tdm:16; /* SND_SOC_DAITDM_* */
- unsigned int pcmfmt:6; /* SNDRV_PCM_FORMAT_* */
- unsigned int pcmrate:16; /* SND_SOC_DAIRATE_* */
- unsigned int pcmdir:2; /* SND_SOC_DAIDIR_* */
- unsigned int flags:8; /* hw flags */
- unsigned int fs:32; /* mclk to rate dividers */
- unsigned int bfs:16; /* mclk to bclk dividers */
- unsigned long priv; /* private mode data */
+struct snd_soc_dai_mode {
+ u16 fmt; /* SND_SOC_DAIFMT_* */
+ u16 tdm; /* SND_SOC_HWTDM_* */
+ u64 pcmfmt; /* SNDRV_PCM_FMTBIT_* */
+ u16 pcmrate; /* SND_SOC_HWRATE_* */
+ u16 pcmdir:2; /* SND_SOC_HWDIR_* */
+ u16 flags:8; /* hw flags */
+ u16 fs; /* mclk to rate divider */
+ u64 bfs; /* mclk to bclk dividers */
+ unsigned long priv; /* private mode data */
};
fmt:
@@ -140,14 +141,14 @@ pcmfmt:
The hardware PCM format. This describes the PCM formats supported by the DAI
mode e.g.
- .hwpcmfmt = SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
SNDRV_PCM_FORMAT_S24_3LE
pcmrate:
----------
The PCM sample rates supported by the DAI mode. e.g.
- .hwpcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000
@@ -161,9 +162,14 @@ flags:
--------
The DAI hardware flags supported by the mode.
-SND_SOC_DAI_BFS_DIV
-This flag states that bit clock is generated by dividing MCLK in this mode, if
-this flag is absent the bitclock generated by mulitiplying sample rate.
+/* use bfs mclk divider mode (BCLK = MCLK / x) */
+#define SND_SOC_DAI_BFS_DIV 0x1
+/* use bfs rate mulitplier (BCLK = RATE * x)*/
+#define SND_SOC_DAI_BFS_RATE 0x2
+/* use bfs rcw multiplier (BCLK = RATE * CHN * WORD SIZE) */
+#define SND_SOC_DAI_BFS_RCW 0x4
+/* capture and playback can use different clocks */
+#define SND_SOC_DAI_ASYNC 0x8
NOTE: Bitclock division and mulitiplication modes can be safely matched by the
core logic.
@@ -181,7 +187,7 @@ depends on the codec or CPU DAI).
The BFS supported by the DAI mode. This can either be the ratio between the
bitclock (BCLK) and the sample rate OR the ratio between the system clock and
-the sample rate. Depends on the SND_SOC_DAI_BFS_DIV flag above.
+the sample rate. Depends on the flags above.
priv:
-----
@@ -207,10 +213,15 @@ Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
BCLK of either MCLK/2 or MCLK/4.
/* codec master */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 256, SND_SOC_FSBD(2) | SND_SOC_FSBD(4)},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(2) | SND_SOC_FSBD(4),
+ }
Example 2
@@ -219,32 +230,95 @@ Simple codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
BCLK of either Rate * 32 or Rate * 64.
/* codec master */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
- 256, SND_SOC_FSB(32) | SND_SOC_FSB(64)},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .fs = 256,
+ .bfs = 32,
+ },
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .fs = 256,
+ .bfs = 64,
+ },
Example 3
---------
+Codec that runs at 8k & 48k @ 256FS in master mode, can generate a BCLK that
+is a multiple of Rate * channels * word size. (RCW) i.e.
+
+ BCLK = 8000 * 2 * 16 (8k, stereo, 16bit)
+ = 256kHz
+
+This codecs supports a RCW multiple of 1,2
+
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RCW,
+ .fs = 256,
+ .bfs = SND_SOC_FSBW(1) | SND_SOC_FSBW(2),
+ }
+
+
+Example 4
+---------
Codec that only runs at 8k & 48k @ 256FS in master mode, can generate a
BCLK of either Rate * 32 or Rate * 64. Codec can also run in slave mode as long
as BCLK is rate * 32 or rate * 64.
/* codec master */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
- 256, SND_SOC_FSB(32) | SND_SOC_FSB(64)},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .fs = 256,
+ .bfs = 32,
+ },
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .fs = 256,
+ .bfs = 64,
+ },
/* codec slave */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
- SND_SOC_FS_ALL, SND_SOC_FSB(32) | SND_SOC_FSB(64)},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmdir = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .fs = SND_SOC_FS_ALL,
+ .bfs = 32,
+ },
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmdir = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .fs = SND_SOC_FS_ALL,
+ .bfs = 64,
+ },
-Example 4
+Example 5
---------
Codec that only runs at 8k, 16k, 32k, 48k, 96k @ 128FS, 192FS & 256FS in master
mode and can generate a BCLK of MCLK / (1,2,4,8,16). Codec can also run in slave
@@ -259,29 +333,48 @@ mode as and does not care about FS or BCLK (as long as there is enough bandwidth
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
/* codec master @ 128, 192 & 256 FS */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 128, CODEC_FSB},
-
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 192, CODEC_FSB},
-
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 256, CODEC_FSB},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = CODEC_RATES,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 128,
+ .bfs = CODEC_FSB,
+ },
+
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = CODEC_RATES,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 192,
+ .bfs = CODEC_FSB
+ },
+
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = CODEC_RATES,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = CODEC_FSB,
+ },
/* codec slave */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
- SND_SOC_FS_ALL, SND_SOC_FSB_ALL},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = CODEC_RATES,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .fs = SND_SOC_FS_ALL,
+ .bfs = SND_SOC_FSB_ALL,
+ },
-Example 5
+Example 6
---------
Codec that only runs at 8k, 44.1k, 48k @ different FS in master mode (for use
with a fixed MCLK) and can generate a BCLK of MCLK / (1,2,4,8,16).
@@ -298,45 +391,66 @@ sizes.
SNDRV_PCM_FORMAT_S24_3LE | SNDRV_PCM_FORMAT_S24_LE | SNDRV_PCM_FORMAT_S32_LE)
/* codec master */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_8000,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 1536, CODEC_FSB},
-
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_44100,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 272, CODEC_FSB},
-
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, SNDRV_PCM_RATE_48000,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, SND_SOC_DAI_BFS_DIV,
- 256, CODEC_FSB},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 1536,
+ .bfs = CODEC_FSB,
+ },
+
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_44100,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 272,
+ .bfs = CODEC_FSB,
+ },
+
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_48000,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = CODEC_FSB,
+ },
/* codec slave */
- {SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0),
- SNDRV_PCM_FORMAT_S16_LE, CODEC_RATES,
- SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE, 0,
- SND_SOC_FS_ALL, SND_SOC_FSB_ALL},
+ {
+ .fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FORMAT_S16_LE,
+ .pcmrate = CODEC_RATES,
+ .pcmdir = SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE,
+ .fs = SND_SOC_FS_ALL,
+ .bfs = SND_SOC_FSB_ALL,
+ },
-Example 6
+Example 7
---------
AC97 Codec that does not support VRA (i.e only runs at 48k).
#define AC97_DIR \
(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
-
#define AC97_PCM_FORMATS \
(SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S18_3LE | \
SNDRV_PCM_FORMAT_S20_3LE)
/* AC97 with no VRA */
- {0, 0, AC97_PCM_FORMATS, SNDRV_PCM_RATE_48000},
+ {
+ .pcmfmt = AC97_PCM_FORMATS,
+ .pcmrate = SNDRV_PCM_RATE_48000,
+ }
-Example 7
+Example 8
---------
CPU DAI that supports 8k - 48k @ 256FS and BCLK = MCLK / 4 in master mode.
@@ -354,27 +468,79 @@ BCLK = 64 * rate. (Intel XScale I2S controller).
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
+ /* priv is divider */
+ static struct snd_soc_dai_mode pxa2xx_i2s_modes[] = {
/* pxa2xx I2S frame and clock master modes */
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- SNDRV_PCM_RATE_8000, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
- SND_SOC_FSBD(4), 0x48},
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- SNDRV_PCM_RATE_11025, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
- SND_SOC_FSBD(4), 0x34},
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- SNDRV_PCM_RATE_16000, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
- SND_SOC_FSBD(4), 0x24},
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- SNDRV_PCM_RATE_22050, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
- SND_SOC_FSBD(4), 0x1a},
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- SNDRV_PCM_RATE_44100, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
- SND_SOC_FSBD(4), 0xd},
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- SNDRV_PCM_RATE_48000, PXA_I2S_DIR, SND_SOC_DAI_BFS_DIV, 256,
- SND_SOC_FSBD(4), 0xc},
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_8000,
+ .pcmdir = PXA_I2S_DIR,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(4),
+ .priv = 0x48,
+ },
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_11025,
+ .pcmdir = PXA_I2S_DIR,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(4),
+ .priv = 0x34,
+ },
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_16000,
+ .pcmdir = PXA_I2S_DIR,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(4),
+ .priv = 0x24,
+ },
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_22050,
+ .pcmdir = PXA_I2S_DIR,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(4),
+ .priv = 0x1a,
+ },
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_44100,
+ .pcmdir = PXA_I2S_DIR,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(4),
+ .priv = 0xd,
+ },
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBS_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = SNDRV_PCM_RATE_48000,
+ .pcmdir = PXA_I2S_DIR,
+ .flags = SND_SOC_DAI_BFS_DIV,
+ .fs = 256,
+ .bfs = SND_SOC_FSBD(4),
+ .priv = 0xc,
+ },
/* pxa2xx I2S frame master and clock slave mode */
- {PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBM_CFS, SND_SOC_DAITDM_LRDW(0,0), SNDRV_PCM_FORMAT_S16_LE,
- PXA_I2S_RATES, PXA_I2S_DIR, 0, SND_SOC_FS_ALL, SND_SOC_FSB(64)},
-
+ {
+ .fmt = PXA_I2S_DAIFMT | SND_SOC_DAIFMT_CBM_CFS,
+ .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
+ .pcmrate = PXA_I2S_RATES,
+ .pcmdir = PXA_I2S_DIR,
+ .fs = SND_SOC_FS_ALL,
+ .flags = SND_SOC_DAI_BFS_RATE,
+ .bfs = 64,
+ .priv = 0x48,
+ },
+};
diff --git a/Documentation/sound/alsa/soc/clocking.txt b/Documentation/sound/alsa/soc/clocking.txt
index 88a16c9e1979..1f55fd8cb117 100644
--- a/Documentation/sound/alsa/soc/clocking.txt
+++ b/Documentation/sound/alsa/soc/clocking.txt
@@ -26,9 +26,9 @@ between the codec and CPU.
The DAI also has a frame clock to signal the start of each audio frame. This
clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
-runs at exactly the sample rate.
+runs at exactly the sample rate (LRC = Rate).
-Bit Clock is usually always a ratio of MCLK or a multiple of LRC. i.e.
+Bit Clock can be generated as follows:-
BCLK = MCLK / x
@@ -36,9 +36,14 @@ BCLK = MCLK / x
BCLK = LRC * x
+ or
+
+BCLK = LRC * Channels * Word Size
+
This relationship depends on the codec or SoC CPU in particular. ASoC can quite
-easily match a codec that generates BCLK by division (FSBD) with a CPU that
-generates BCLK by multiplication (FSB).
+easily match BCLK generated by division (SND_SOC_DAI_BFS_DIV) with BCLK by
+multiplication (SND_SOC_DAI_BFS_RATE) or BCLK generated by
+Rate * Channels * Word size (RCW or SND_SOC_DAI_BFS_RCW).
ASoC Clocking
generated by cgit v1.2.3 (git 2.0.4) at 2024-12-27 08:19:25 +0000