diff options
Diffstat (limited to 'Documentation')
120 files changed, 3949 insertions, 50 deletions
diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index 3acc4f1a6f84..4a5a887181c3 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -436,6 +436,8 @@ sysrq.txt - info on the magic SysRq key. target/ - directory with info on generating TCM v4 fabric .ko modules +tee.txt + - info on the TEE subsystem and drivers this_cpu_ops.txt - List rationale behind and the way to use this_cpu operations. thermal/ diff --git a/Documentation/ABI/testing/sysfs-class-typec b/Documentation/ABI/testing/sysfs-class-typec new file mode 100644 index 000000000000..d4a3d23eb09c --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-typec @@ -0,0 +1,276 @@ +USB Type-C port devices (eg. /sys/class/typec/port0/) + +What: /sys/class/typec/<port>/data_role +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + The supported USB data roles. This attribute can be used for + requesting data role swapping on the port. Swapping is supported + as synchronous operation, so write(2) to the attribute will not + return until the operation has finished. The attribute is + notified about role changes so that poll(2) on the attribute + wakes up. Change on the role will also generate uevent + KOBJ_CHANGE on the port. The current role is show in brackets, + for example "[host] device" when DRP port is in host mode. + + Valid values: host, device + +What: /sys/class/typec/<port>/power_role +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + The supported power roles. This attribute can be used to request + power role swap on the port when the port supports USB Power + Delivery. Swapping is supported as synchronous operation, so + write(2) to the attribute will not return until the operation + has finished. The attribute is notified about role changes so + that poll(2) on the attribute wakes up. Change on the role will + also generate uevent KOBJ_CHANGE. The current role is show in + brackets, for example "[source] sink" when in source mode. + + Valid values: source, sink + +What: /sys/class/typec/<port>/vconn_source +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows is the port VCONN Source. This attribute can be used to + request VCONN swap to change the VCONN Source during connection + when both the port and the partner support USB Power Delivery. + Swapping is supported as synchronous operation, so write(2) to + the attribute will not return until the operation has finished. + The attribute is notified about VCONN source changes so that + poll(2) on the attribute wakes up. Change on VCONN source also + generates uevent KOBJ_CHANGE. + + Valid values: + - "no" when the port is not the VCONN Source + - "yes" when the port is the VCONN Source + +What: /sys/class/typec/<port>/power_operation_mode +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows the current power operational mode the port is in. The + power operation mode means current level for VBUS. In case USB + Power Delivery communication is used for negotiating the levels, + power operation mode should show "usb_power_delivery". + + Valid values: + - default + - 1.5A + - 3.0A + - usb_power_delivery + +What: /sys/class/typec/<port>/preferred_role +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + The user space can notify the driver about the preferred role. + It should be handled as enabling of Try.SRC or Try.SNK, as + defined in USB Type-C specification, in the port drivers. By + default the preferred role should come from the platform. + + Valid values: source, sink, none (to remove preference) + +What: /sys/class/typec/<port>/supported_accessory_modes +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Space separated list of accessory modes, defined in the USB + Type-C specification, the port supports. + +What: /sys/class/typec/<port>/usb_power_delivery_revision +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Revision number of the supported USB Power Delivery + specification, or 0 when USB Power Delivery is not supported. + +What: /sys/class/typec/<port>/usb_typec_revision +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Revision number of the supported USB Type-C specification. + + +USB Type-C partner devices (eg. /sys/class/typec/port0-partner/) + +What: /sys/class/typec/<port>-partner/accessory_mode +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows the Accessory Mode name when the partner is an Accessory. + The Accessory Modes are defined in USB Type-C Specification. + +What: /sys/class/typec/<port>-partner/supports_usb_power_delivery +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows if the partner supports USB Power Delivery communication: + Valid values: yes, no + +What: /sys/class/typec/<port>-partner>/identity/ +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + This directory appears only if the port device driver is capable + of showing the result of Discover Identity USB power delivery + command. That will not always be possible even when USB power + delivery is supported, for example when USB power delivery + communication for the port is mostly handled in firmware. If the + directory exists, it will have an attribute file for every VDO + in Discover Identity command result. + +What: /sys/class/typec/<port>-partner/identity/id_header +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + ID Header VDO part of Discover Identity command result. The + value will show 0 until Discover Identity command result becomes + available. The value can be polled. + +What: /sys/class/typec/<port>-partner/identity/cert_stat +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Cert Stat VDO part of Discover Identity command result. The + value will show 0 until Discover Identity command result becomes + available. The value can be polled. + +What: /sys/class/typec/<port>-partner/identity/product +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Product VDO part of Discover Identity command result. The value + will show 0 until Discover Identity command result becomes + available. The value can be polled. + + +USB Type-C cable devices (eg. /sys/class/typec/port0-cable/) + +Note: Electronically Marked Cables will have a device also for one cable plug +(eg. /sys/class/typec/port0-plug0). If the cable is active and has also SOP +Double Prime controller (USB Power Deliver specification ch. 2.4) it will have +second device also for the other plug. Both plugs may have alternate modes as +described in USB Type-C and USB Power Delivery specifications. + +What: /sys/class/typec/<port>-cable/type +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows if the cable is active. + Valid values: active, passive + +What: /sys/class/typec/<port>-cable/plug_type +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows type of the plug on the cable: + - type-a - Standard A + - type-b - Standard B + - type-c + - captive + +What: /sys/class/typec/<port>-cable/identity/ +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + This directory appears only if the port device driver is capable + of showing the result of Discover Identity USB power delivery + command. That will not always be possible even when USB power + delivery is supported. If the directory exists, it will have an + attribute for every VDO returned by Discover Identity command. + +What: /sys/class/typec/<port>-cable/identity/id_header +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + ID Header VDO part of Discover Identity command result. The + value will show 0 until Discover Identity command result becomes + available. The value can be polled. + +What: /sys/class/typec/<port>-cable/identity/cert_stat +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Cert Stat VDO part of Discover Identity command result. The + value will show 0 until Discover Identity command result becomes + available. The value can be polled. + +What: /sys/class/typec/<port>-cable/identity/product +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Product VDO part of Discover Identity command result. The value + will show 0 until Discover Identity command result becomes + available. The value can be polled. + + +Alternate Mode devices. + +The alternate modes will have Standard or Vendor ID (SVID) assigned by USB-IF. +The ports, partners and cable plugs can have alternate modes. A supported SVID +will consist of a set of modes. Every SVID a port/partner/plug supports will +have a device created for it, and every supported mode for a supported SVID will +have its own directory under that device. Below <dev> refers to the device for +the alternate mode. + +What: /sys/class/typec/<port|partner|cable>/<dev>/svid +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + The SVID (Standard or Vendor ID) assigned by USB-IF for this + alternate mode. + +What: /sys/class/typec/<port|partner|cable>/<dev>/mode<index>/ +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Every supported mode will have its own directory. The name of + a mode will be "mode<index>" (for example mode1), where <index> + is the actual index to the mode VDO returned by Discover Modes + USB power delivery command. + +What: /sys/class/typec/<port|partner|cable>/<dev>/mode<index>/description +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows description of the mode. The description is optional for + the drivers, just like with the Billboard Devices. + +What: /sys/class/typec/<port|partner|cable>/<dev>/mode<index>/vdo +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows the VDO in hexadecimal returned by Discover Modes command + for this mode. + +What: /sys/class/typec/<port|partner|cable>/<dev>/mode<index>/active +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Shows if the mode is active or not. The attribute can be used + for entering/exiting the mode with partners and cable plugs, and + with the port alternate modes it can be used for disabling + support for specific alternate modes. Entering/exiting modes is + supported as synchronous operation so write(2) to the attribute + does not return until the enter/exit mode operation has + finished. The attribute is notified when the mode is + entered/exited so poll(2) on the attribute wakes up. + Entering/exiting a mode will also generate uevent KOBJ_CHANGE. + + Valid values: yes, no + +What: /sys/class/typec/<port>/<dev>/mode<index>/supported_roles +Date: April 2017 +Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> +Description: + Space separated list of the supported roles. + + This attribute is available for the devices describing the + alternate modes a port supports, and it will not be exposed with + the devices presenting the alternate modes the partners or cable + plugs support. + + Valid values: source, sink diff --git a/Documentation/ABI/testing/sysfs-platform-chipidea-usb2 b/Documentation/ABI/testing/sysfs-platform-chipidea-usb2 new file mode 100644 index 000000000000..b0f4684a83fe --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-chipidea-usb2 @@ -0,0 +1,9 @@ +What: /sys/bus/platform/devices/ci_hdrc.0/role +Date: Mar 2017 +Contact: Peter Chen <peter.chen@nxp.com> +Description: + It returns string "gadget" or "host" when read it, it indicates + current controller role. + + It will do role switch when write "gadget" or "host" to it. + Only controller at dual-role configuration supports writing. diff --git a/Documentation/block/biodoc.txt b/Documentation/block/biodoc.txt index 918e1e0d0e78..01ddeaf64b0f 100644 --- a/Documentation/block/biodoc.txt +++ b/Documentation/block/biodoc.txt @@ -348,7 +348,7 @@ Drivers can now specify a request prepare function (q->prep_rq_fn) that the block layer would invoke to pre-build device commands for a given request, or perform other preparatory processing for the request. This is routine is called by elv_next_request(), i.e. typically just before servicing a request. -(The prepare function would not be called for requests that have REQ_DONTPREP +(The prepare function would not be called for requests that have RQF_DONTPREP enabled) Aside: @@ -553,8 +553,8 @@ struct request { struct request_list *rl; } -See the rq_flag_bits definitions for an explanation of the various flags -available. Some bits are used by the block layer or i/o scheduler. +See the req_ops and req_flag_bits definitions for an explanation of the various +flags available. Some bits are used by the block layer or i/o scheduler. The behaviour of the various sector counts are almost the same as before, except that since we have multi-segment bios, current_nr_sectors refers diff --git a/Documentation/cpu-freq/governors.txt b/Documentation/cpu-freq/governors.txt index c15aa75f5227..0cf9a6bff6a5 100644 --- a/Documentation/cpu-freq/governors.txt +++ b/Documentation/cpu-freq/governors.txt @@ -28,6 +28,7 @@ Contents: 2.3 Userspace 2.4 Ondemand 2.5 Conservative +2.6 Interactive 3. The Governor Interface in the CPUfreq Core @@ -218,6 +219,91 @@ a decision on when to decrease the frequency while running in any speed. Load for frequency increase is still evaluated every sampling rate. +2.6 Interactive +--------------- + +The CPUfreq governor "interactive" is designed for latency-sensitive, +interactive workloads. This governor sets the CPU speed depending on +usage, similar to "ondemand" and "conservative" governors, but with a +different set of configurable behaviors. + +The tunable values for this governor are: + +above_hispeed_delay: When speed is at or above hispeed_freq, wait for +this long before raising speed in response to continued high load. +The format is a single delay value, optionally followed by pairs of +CPU speeds and the delay to use at or above those speeds. Colons can +be used between the speeds and associated delays for readability. For +example: + + 80000 1300000:200000 1500000:40000 + +uses delay 80000 uS until CPU speed 1.3 GHz, at which speed delay +200000 uS is used until speed 1.5 GHz, at which speed (and above) +delay 40000 uS is used. If speeds are specified these must appear in +ascending order. Default is 20000 uS. + +boost: If non-zero, immediately boost speed of all CPUs to at least +hispeed_freq until zero is written to this attribute. If zero, allow +CPU speeds to drop below hispeed_freq according to load as usual. +Default is zero. + +boostpulse: On each write, immediately boost speed of all CPUs to +hispeed_freq for at least the period of time specified by +boostpulse_duration, after which speeds are allowed to drop below +hispeed_freq according to load as usual. Its a write-only file. + +boostpulse_duration: Length of time to hold CPU speed at hispeed_freq +on a write to boostpulse, before allowing speed to drop according to +load as usual. Default is 80000 uS. + +go_hispeed_load: The CPU load at which to ramp to hispeed_freq. +Default is 99%. + +hispeed_freq: An intermediate "high speed" at which to initially ramp +when CPU load hits the value specified in go_hispeed_load. If load +stays high for the amount of time specified in above_hispeed_delay, +then speed may be bumped higher. Default is the maximum speed allowed +by the policy at governor initialization time. + +io_is_busy: If set, the governor accounts IO time as CPU busy time. + +min_sample_time: The minimum amount of time to spend at the current +frequency before ramping down. Default is 80000 uS. + +target_loads: CPU load values used to adjust speed to influence the +current CPU load toward that value. In general, the lower the target +load, the more often the governor will raise CPU speeds to bring load +below the target. The format is a single target load, optionally +followed by pairs of CPU speeds and CPU loads to target at or above +those speeds. Colons can be used between the speeds and associated +target loads for readability. For example: + + 85 1000000:90 1700000:99 + +targets CPU load 85% below speed 1GHz, 90% at or above 1GHz, until +1.7GHz and above, at which load 99% is targeted. If speeds are +specified these must appear in ascending order. Higher target load +values are typically specified for higher speeds, that is, target load +values also usually appear in an ascending order. The default is +target load 90% for all speeds. + +timer_rate: Sample rate for reevaluating CPU load when the CPU is not +idle. A deferrable timer is used, such that the CPU will not be woken +from idle to service this timer until something else needs to run. +(The maximum time to allow deferring this timer when not running at +minimum speed is configurable via timer_slack.) Default is 20000 uS. + +timer_slack: Maximum additional time to defer handling the governor +sampling timer beyond timer_rate when running at speeds above the +minimum. For platforms that consume additional power at idle when +CPUs are running at speeds greater than minimum, this places an upper +bound on how long the timer will be deferred prior to re-evaluating +load and dropping speed. For example, if timer_rate is 20000uS and +timer_slack is 10000uS then timers will be deferred for up to 30msec +when not at lowest speed. A value of -1 means defer timers +indefinitely at all speeds. Default is 80000 uS. + 3. The Governor Interface in the CPUfreq Core ============================================= diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt new file mode 100644 index 000000000000..d38834c67dff --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt @@ -0,0 +1,31 @@ +OP-TEE Device Tree Bindings + +OP-TEE is a piece of software using hardware features to provide a Trusted +Execution Environment. The security can be provided with ARM TrustZone, but +also by virtualization or a separate chip. + +We're using "linaro" as the first part of the compatible property for +the reference implementation maintained by Linaro. + +* OP-TEE based on ARM TrustZone required properties: + +- compatible : should contain "linaro,optee-tz" + +- method : The method of calling the OP-TEE Trusted OS. Permitted + values are: + + "smc" : SMC #0, with the register assignments specified + in drivers/tee/optee/optee_smc.h + + "hvc" : HVC #0, with the register assignments specified + in drivers/tee/optee/optee_smc.h + + + +Example: + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/mxc_ion.txt b/Documentation/devicetree/bindings/arm/freescale/mxc_ion.txt new file mode 100644 index 000000000000..cb3e96775284 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/mxc_ion.txt @@ -0,0 +1,23 @@ +ION Memory Manager (ION) + +ION is a memory manager that allows for sharing of buffers between different +processes and between user space and kernel space. ION manages different +memory spaces by separating the memory spaces into "heaps". + +Required properties for Ion + +- compatible: "fsl,mxc-ion" + + +All child nodes of a fsl,mxc-ion node are interpreted as Ion heap +configurations. + +Required properties for Ion heaps + +- fsl,heap-id: The ID of the ION heap. + +Example: + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt index fa511db18408..49c4135dd9f2 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.txt +++ b/Documentation/devicetree/bindings/ata/imx-sata.txt @@ -7,6 +7,7 @@ Required properties: - compatible : should be one of the following: - "fsl,imx53-ahci" for i.MX53 SATA controller - "fsl,imx6q-ahci" for i.MX6Q SATA controller + - "fsl,imx8qm-ahci" for i.MX8QM SATA controller - interrupts : interrupt mapping for SATA IRQ - reg : registers mapping - clocks : list of clock specifiers, must contain an entry for each @@ -22,6 +23,9 @@ Optional properties: for the list of legal values for these options. - fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA link. +- fsl,phy-imp: PHY impedance ratio value refer to the differnt HW design. + Set it to 0x6c when 85OHM is used, keep it to default value 0x80 when + 100OHM is used. Examples: diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt new file mode 100644 index 000000000000..b2f4dac59d49 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -0,0 +1,59 @@ +* Clock bindings for Freescale i.MX7ULP + +i.MX7ULP Clock functions are under joint control of the System +Clock Generation (SCG) modules, Peripheral Clock Control (PCC) +modules, and Core Mode Controller (CMC)1 blocks + +The clocking scheme provides clear separation between M4 domain +and A7 domain. Except for a few clock sources shared between two +domains, such as the System Oscillator clock, the Slow IRC (SIRC), +and and the Fast IRC clock (FIRCLK), clock sources and clock +management are separated and contained within each domain. + +M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. +A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. + +Note: this binding doc is only for A7 clock domain. + +Required properties: + +- compatible: Should be "fsl,imx7ulp-scg0" or "fsl,imx7ulp-scg1". +- reg : Should contain registers location and length. +- #clock-cells: Should be <1>. +- clocks: Should contain the fixed input clocks. +- clock-name: Should contain the following clock names:"cm4_rosc", + "cm4_sosc", "cm4_sirc", "cm4_firc" for scg0. +Or + Should contain the following clock names:"rsoc", "sosc", + "sirc", "firc", "upll", "mpll" for scg1. + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +See include/dt-bindings/clock/imx7ulp-clock.h +for the full list of i.MX7ULP clock IDs. + +Examples: + +#include <dt-bindings/clock/imx7ulp-clock.h> + +clks: scg1@403e0000 { + compatible = "fsl,imx7ulp-clock"; + reg = <0x403e0000 0x10000>; + clocks = <&rsoc>, <&sosc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "rsoc", "sosc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; +}; + +usdhc1: usdhc@40380000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt index 6949e50f1f16..120792d13669 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt @@ -10,7 +10,7 @@ Required properties: Example: dcp@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; + compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp", "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; interrupts = <52 53>; status = "okay"; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index adeca34c5a33..01294c0cbe43 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -1,6 +1,7 @@ ===================================================================== SEC 4 Device Tree Binding Copyright (C) 2008-2011 Freescale Semiconductor Inc. +Copyright 2017 NXP CONTENTS -Overview @@ -10,6 +11,7 @@ Copyright (C) 2008-2011 Freescale Semiconductor Inc. -Run Time Integrity Check (RTIC) Memory Node -Secure Non-Volatile Storage (SNVS) Node -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node + -CAAM Secure Memory Storage Interface -Full Example NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator @@ -118,6 +120,12 @@ PROPERTIES Definition: A list of clock name strings in the same order as the clocks property. + - first-jr-index + Usage: required only for i.MX8QM and i.MX8QXP + Value type: <u32> + Definition: Specifies the first job ring index assigned to kernel + to read aliased register since CAAM page 0 is not accessible. + Note: All other standard properties (see the ePAPR) are allowed but are optional. @@ -140,6 +148,49 @@ EXAMPLE }; ===================================================================== +SEC 4 Page 0 + +Description + + Most of CAAM's configuration registers are accessible in block0 + of CAAM's register space. These registers are intended to be + accessed by specially privileged software (e.g. boot software, + hypervisor, secure operating system). + +PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,sec-v4.0-ctrl". + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical + address and length of the SEC4 configuration registers. + + - secure-status + Usage: required + Value type: <string> + Definition: Must include "okay". + + - status + Usage: required + Value type: <string> + Definition: Must include "disabled". + +EXAMPLE + sec_ctrl: ctrl@0 { + /* CAAM Page 0 only accessible */ + /* by secure world */ + compatible = "fsl,sec-v4.0-ctrl"; + reg = <0x2100000 0x1000>; + secure-status = "okay"; + status = "disabled"; + }; + +===================================================================== Job Ring (JR) Node Child of the crypto node defines data processing interface to SEC 4 @@ -395,6 +446,15 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: <u32> Definition: LP register offset. default it is 0x34. + - clocks + Usage: optional + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the source clock for + snvs register access. If i.MX clk driver defines the clock node, + it needs user to specify the clocks in device tree for all modules + with snvs LP/HP registers access. The modules involved snvs LP/HP + registers access are snvs-power key, snvs-rtc, and caam. + EXAMPLE sec_mon_rtc_lp@1 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; @@ -445,6 +505,27 @@ EXAMPLE: }; ===================================================================== +CAAM Secure Memory Storage Interface + + A CAAM-SM child node that defines Secure Memory. + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,imx6q-caam-sm". + + - regmap + Usage: required + Value type: <phandle> + Definition: this is phandle to the register map node. + +EXAMPLE + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x1ffff>; + }; + +===================================================================== FULL EXAMPLE crypto: crypto@300000 { @@ -534,4 +615,9 @@ FULL EXAMPLE }; }; + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x1ffff>; + }; + ===================================================================== diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt index 6532a59c9b43..0064ff610ade 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt @@ -1,10 +1,10 @@ -Analog Device ADV7511(W)/13/33 HDMI Encoders +Analog Device ADV7511(W)/13/33/35 HDMI Encoders ----------------------------------------- -The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters -compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, -S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while -the others support RGB interface. +The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video +transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space +conversion, S/PDIF, CEC and HDCP. ADV7533 and ADV7535 support the DSI interface +for input pixels, while the others support RGB interface. Required properties: @@ -13,6 +13,7 @@ Required properties: "adi,adv7511w" "adi,adv7513" "adi,adv7533" + "adi,adv7535" - reg: I2C slave address @@ -38,7 +39,7 @@ The following input format properties are required except in "rgb 1x" and - adi,input-justification: The input bit justification ("left", "evenly", "right"). -The following properties are required for ADV7533: +The following properties are required for ADV7533 and ADV7535: - adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should be one of 1, 2, 3 or 4. @@ -53,18 +54,26 @@ Optional properties: - adi,embedded-sync: The input uses synchronization signals embedded in the data stream (similar to BT.656). Defaults to separate H/V synchronization signals. -- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing - generator. The chip will rely on the sync signals in the DSI data lanes, - rather than generate its own timings for HDMI output. +- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the + internal timing generator. The chip will rely on the sync signals in the DSI + data lanes, rather than generate its own timings for HDMI output. +- adi,dsi-channel: Only for ADV7533 and ADV7535. DSI channel number to be used + when communicating with the DSI peripheral. It should be one of 0, 1, 2 or 3. +- adi,addr-cec: Only for ADV7533 and ADV7535. The I2C DSI-CEC register map + address to be programmed into the MAIN register map. +- adi,addr-edid: Only for ADV7533 and ADV7535. The I2C EDID register map + to be programmed into the MAIN register map. +- adi,addr-pkt: Only for ADV7533 and ADV7535. The I2C PACKET register map + to be programmed into the MAIN register map. Required nodes: The ADV7511 has two video ports. Their connections are modelled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. -- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the - remote endpoint phandle should be a reference to a valid mipi_dsi_host device - node. +- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533 and + ADV7535, the remote endpoint phandle should be a reference to a valid + mipi_dsi_host device node. - Video port 1 for the HDMI output diff --git a/Documentation/devicetree/bindings/display/bridge/it6263.txt b/Documentation/devicetree/bindings/display/bridge/it6263.txt new file mode 100644 index 000000000000..5bab1bd4dacc --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/it6263.txt @@ -0,0 +1,29 @@ +ITE IT6263 LVDS to HDMI bridge bindings + +Required properties: + - compatible: "ite,it6263" + - reg: i2c address of the bridge + - video input: this subnode can contain a video input port node + to connect the bridge to a LVDS output interface (See this + documentation [1]). + +Optional properties: + - split-mode: boolean. if this exists, split mode is enabled, + otherwise, single mode is enabled. + - reset-gpios: OF device-tree gpio specification for SYSRSTN pin. + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4 5>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/nwl_dsi.txt b/Documentation/devicetree/bindings/display/bridge/nwl_dsi.txt new file mode 100644 index 000000000000..5d4242bae3f0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/nwl_dsi.txt @@ -0,0 +1,115 @@ +Northwest Logic MIPI-DSI bridge bindings + +The MIPI-DSI host controller drives the video signals from +display controller to video peripherals using DSI protocol. +This is an un-managed DSI bridge. In order to use this bridge, an encoder +or bridge must be implemented to manage the platform specific initializations. + +Required properties: +- compatible: "nwl,mipi-dsi" +- reg: the register range of the MIPI-DSI controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks + "phy_ref" - PHY_REF clock + "tx_esc" - TX_ESC clock (used in escape mode) + "rx_esc" - RX_ESC clock (used in escape mode) +- assigned-clocks: phandles to clocks that requires initial configuration +- assigned-clock-rates: rates of the clocks that requires initial configuration + The following clocks needs to have an initial configuration: + "tx_esc" and "rx_esc" +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an encoder or a + bridge that manages this MIPI-DSI host and the output + port should be connected to a panel or a bridge input + port +- phys: phandle to the phy module representing the DPHY + inside MIPI-DSI IP block +- phy-names: should be "dphy" + + +Optional properties: +- power-domains phandle to the power domain +- interrupt-parent phandle to the interrupt parent, if there is one; + usually, on i.MX8qm and i.MX8qxp there is an irq + steer handling the MIPI DSI interrupts +- assigned-clock-parents phandles to parent clocks that needs to be assigned as + parents to clocks defined in assigned-clocks + +* The clock assignments must follow the rules defined in: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +Example: + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi0>; + clocks = + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>; + assigned-clock-rates = <18000000>, <72000000>; + power-domains = <&pd_mipi0>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + + port@0 { + mipi_dsi_bridge1_in: endpoint { + remote-endpoint = <&mipi_dsi1_out>; + }; + }; + + port@1 { + mipi_dsi0_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; + +Another example, for a platform with a complex clock tree, like 8QXP: + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>, + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; + assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-parents = + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>; + power-domains = <&pd_mipi_dsi0>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + + port@0 { + mipi_dsi_bridge1_in: endpoint { + remote-endpoint = <&mipi_dsi1_out>; + }; + }; + + port@1 { + mipi_dsi0_out: endpoint { + remote-endpoint = <&adv7535_0_in>; + }; + }; + }; + +* Here, we set the clock parents for the *_SEL clocks (which are the sources of +the *_CLK clocks) and also the clock rate of the *_CLK clocks. diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt new file mode 100644 index 000000000000..9bc5e9dd2539 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt @@ -0,0 +1,57 @@ +Samsung MIPI DSIM bridge bindings + +The MIPI DSIM host controller drives the video signals from +display controller to video peripherals using DSI protocol. +This is an un-managed DSI bridge. In order to use this bridge, +an encoder or bridge must be implemented to manage the platform +specific initializations. + +Required properties: +- compatible: "fsl,imx8mm-mipi-dsim" +- reg: the register range of the MIPI DSIM controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + "cfg" - DSIM access clock + "pll-ref" - DSIM PHY PLL reference clock +- assigned-clocks: phandles to clocks that requires initial configuration +- assigned-clock-rates: rates of the clocks that requires initial configuration +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an encoder or a + bridge that manages this MIPI DSIM host and the output + port should be connected to a panel or a bridge input + port + +Optional properties: +-dsi-gpr: a phandle which provides the MIPI DSIM control and gpr registers + +example: + mipi_dsi: mipi_dsi@32E10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x0 0x32e10000 0x0 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>, + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>, + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + dsi-gpr = <&dispmix_gpr>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/display/imx/dsi_nwl.txt b/Documentation/devicetree/bindings/display/imx/dsi_nwl.txt new file mode 100644 index 000000000000..f37ddfe45c6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/dsi_nwl.txt @@ -0,0 +1,78 @@ +NXP specific extensions to the Northwest Logic MIPI-DSI +================================ + +Platform specific extentions for the NWL MIPI-DSI host controller found in +MX8 platforms. This is an encoder/bridge that manages the platform specific +initializations required for the NWL MIPI-DSI host. + +Required properties: +- compatible: "fsl,<chip>-mipi-dsi" + The following strings are expected: + "fsl,imx8qm-mipi-dsi" + "fsl,imx8qxp-mipi-dsi" +- reg: the register range of the MIPI-DSI controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks + The following clocks are expected on all platforms: + "phy_ref" - PHY_REF clock + "tx_esc" - TX_ESC clock (used in escape mode) + "rx_esc" - RX_ESC clock (used in escape mode) + The following clocks are expected on i.MX8qm and i.MX8qxp: + "bypass" - bypass clock + "pixel" - pixel clock (for the pixel link) +- assigned-clocks: phandles to clocks that requires initial configuration +- assigned-clock-rates: rates of the clocks that requires initial configuration + The following clocks needs to have an initial configuration: + "tx_esc" and "rx_esc" +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to a display + interface and the output port should be connected to a + NWL MIPI-DSI host +- phys: phandle to the phy module representing the DPHY + inside MIPI-DSI IP block +- phy-names: should be "dphy" + +Optional properties: +- power-domains phandle to the power domain +- interrupt-parent phandle to the interrupt parent, if there is one; + usually, on i.MX8qm and i.MX8qxp there is an irq + steer handling the MIPI DSI interrupts +- csr phandle to the CSR register set (required on i.MX8qm + and i.MX8qxp for the reset functions) +- assigned-clock-parents phandles to parent clocks that needs to be assigned as + parents to clocks defined in assigned-clocks +- sync-pol horizontal and vertical sync polarity of the input + signal; can be <0> for LOW (negative) or <1> for HIGH + (positive) polarity; default value is <0>, when this + property is ommited +- pwr-delay delay used in enable, before enabling the clocks; this is + useful when the PLL needs some time to become stable; + this value represents milliseconds + +Example: + mipi_dsi1: mipi_dsi { + compatible = "fsl,imx8qxp-mipi-dsi"; + clocks = + <&clk IMX8QXP_MIPI0_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_BYPASS_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi_dsi0>; + csr = <&mipi_dsi_csr1>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi1_in: endpoint { + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi1_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_in>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 971c3eedb1c7..33c28ac807fb 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -53,6 +53,254 @@ ipu: ipu@18000000 { }; }; +Freescale i.MX DPU +==================== + +Required properties: +- compatible: Should be "fsl,<chip>-dpu" +- reg: should be register base and length as documented in the + datasheet +- intsteer: phandle pointing to interrupt steer. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- clocks, clock-names: phandles to the DPU clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + The following clocks are expected on i.MX8qm and i.MX8qxp: + "pll0" - PLL clock for display interface 0 + "pll1" - PLL clock for display interface 1 + "disp0" - pixel clock for display interface 0 + "disp1" - pixel clock for display interface 1 + The needed clock numbers for each are documented in + Documentation/devicetree/bindings/clock/imx8qm-clock.txt, and in + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt. +- power-domains: phandle pointing to power domain. +- fsl,dpr-channels: phandles to the DPR channels attached to this DPU, + sorted by memory map addresses. Only valid for i.MX8qm and i.MX8qxp. +Optional properties: +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 and 1 should correspond to display interface 0 and + display interface 1, respectively. + +example: + +dpu: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu1_intsteer>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", + "irq_stream1a", + "irq_stream1b", + "irq_reserved0", + "irq_reserved1", + "irq_blit"; + clocks = <&clk IMX8QM_DC0_PLL0_CLK>, + <&clk IMX8QM_DC0_PLL1_CLK>, + <&clk IMX8QM_DC0_DISP0_CLK>, + <&clk IMX8QM_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd_dc0>; + fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, + <&dpr1_channel3>, <&dpr2_channel1>, + <&dpr2_channel2>, <&dpr2_channel3>; + + dpu1_disp1: port@1 { + reg = <1>; + + dpu1_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb1_lvds0>; + }; + + dpu1_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb1_lvds1>; + }; + }; +}; + + +NXP i.MX Display Controller Subsystem (DCSS) +============================================= + +Required properties: +- compatible: Should be "nxp,<chip>-dcss" +- reg: should be register base and length as documented in the + datasheet. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- interrupt-parent: contains the phandle to IRQ Steer module. +- clocks, clock-names: phandles to the DCSS clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt +- disp-dev: can take following values: + - hdmi_disp: DCSS output goes to HDMI + - mipi_disp: DCSS output goes to MIPI_DSI +Optional properties: +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 and 1 should correspond to display interface 0 and + display interface 1, respectively. + + +example: + +dcss_drm: dcss@0x32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x0 0x32e00000 0x0 0x30000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>, + <6 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dpr_dc_ch0", "dpr_dc_ch1", "dpr_dc_ch2", "ctx_ld", + "dtg_prg1"; + interrupt-parent = <&irqsteer_dcss>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, + <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; + clock-names = "apb", "axi", "rtrm", "pixel", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_APB_SRC>, + <&clk IMX8MQ_CLK_DISP_AXI_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, + <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, + <&clk IMX8MQ_CLK_DISP_DTRC_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rate = <800000000>, <800000000>, <800000000>, <594000000>, <25000000>; + + disp-dev = "hdmi_disp"; + + status = "okay"; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_imx_stub: imx_stub_conenc { + remote-endpoint = <&imx_stub_conenc0>; + }; + }; +}; + +NXP i.MX eLCDIF (Enhanced LCD Interface) +======================================== +Required properties: +- compatible: should be "fsl,imx8mm-lcdif" +- reg: should be register base and length as documented in the + datasheet. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- interrupt-parent: contains the phandle to IRQ Steer module. +- clocks, clock-names: phandles to the LCDIF clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt +- assigned-clocks, assigned-clock-parents, assigned-clock-rate: configure + LCDIF related clock sources, clock source parents and clock source rates. +- lcdif-gpr: a phandle which provides the LCDIF control and gpr registers + configuration. +Optional properties: +- port@0: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 should correspond to display interface 0. + +example: + lcdif: lcdif@32E00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-lcdif"; + reg = <0x0 0x32e00000 0x0 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_DIV>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_SRC>, + <&clk IMX8MM_CLK_DISP_AXI_SRC>, + <&clk IMX8MM_CLK_DISP_APB_SRC>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + lcdif-gpr = <&dispmix_gpr>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + +Freescale i.MX8 PRG (Prefetch Resolve Gasket) +============================================= +Required properties: +- compatible: should be "fsl,<chip>-prg" +- reg: should be register base and length as documented in the + datasheet +- clocks: phandles to the PRG apb and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt, + Documentation/devicetree/bindings/clock/imx8qm-clock.txt and + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt +- clock-names: should be "apb" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +prg@56040000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56040000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG0_APB_CLK>, + <&clk IMX8QM_DC0_PRG0_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; +}; + +Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) +======================================================= +Required properties: +- compatible: should be "fsl,<chip>-dpr-channel" +- reg: should be register base and length as documented in the + datasheet +- fsl,sc-resource: SCU resource number as described in + Documentation/devicetree/bindings/soc/fsl/imx_rsrc.txt +- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one + is the primary PRG and the second one(if available) is the auxiliary PRG + which is used to fetch luma chunk of a YUV frame with 2 planars. +- clocks: phandles to the DPRC apb, b and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt, + Documentation/devicetree/bindings/clock/imx8qm-clock.txt and + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt +- clock-names: should be "apb", "b" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +dpr-channel@56100000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56100000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_VIDEO0>; + fsl,prgs = <&prg4>, <&prg5>; + clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>, + <&clk IMX8QM_DC0_DPR1_B_CLK>, + <&clk IMX8QM_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; +}; + Parallel display support ======================== diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index a407462c885e..4d51efe81461 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -9,10 +9,16 @@ nodes describing each of the two LVDS encoder channels of the bridge. Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. + - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or + "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb". + All LDB versions are similar. + i.MX6q/dl has an additional multiplexer in the front to select + any of the two or four IPU display interfaces as input for each + LVDS channel. + i.MX8qm LDB supports 10bit RGB input and needs an additional + phy. + i.MX8qxp LDB only supports one LVDS encoder channel(either + channel0 or channel1). - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. @@ -29,17 +35,32 @@ Required properties: On i.MX6q the following additional clocks are needed: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux + The following clocks are expected on i.MX8qm: + "pixel" - pixel clock + "bypass" - bypass clock + The following clocks are expected on i.MX8qxp: + "pixel" - pixel clock + "bypass" - bypass clock + "aux_pixel" - pixel clock of the auxiliary LDB + "aux_bypass" - bypass clock of the auxiliary LDB The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in Documentation/devicetree/bindings/clock/imx6q-clock.txt. +- power-domains : phandle pointing to power domain, only required by i.MX8qm and + i.MX8qxp. Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q + - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm + and i.MX8qxp - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q + not used on i.MX6q, i.MX8qm and i.MX8qxp - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual - channel mode + channel mode(i.MX8qxp uses two LDBs to support this). Note that when + i.MX8qxp LDB works in dual channel mode, only the primary LDB node + should be active and the auxiliary LDB node should be disabled. + - aux-gpr : the phandle points to the auxiliary LVDS region containing + the LVDS control register(only required by i.MX8qxp) LVDS Channel ============ @@ -57,9 +78,16 @@ Required properties: (lvds-channel@[0,1], respectively). On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. + On i.MX8qm, the two channels of LDB connect to one display interface of DPU. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm + and i.MX8qxp) must be connected to a panel input port or a bridge input port. + Optionally, the output port can be left out if display-timings are used + instead. + - phys: the phandle for the LVDS PHY devices. Valid only on i.MX8qm and + i.MX8qxp. For i.MX8qxp, two PHYs should be provided for LVDS + channel0, one for primary LDB and the other for auxiliary LDB. + - phy-names: should be "ldb_phy" for i.MX8qm, and "ldb_phy", "aux_ldb_phy" + for i.MX8qxp. Valid only on i.MX8qm and i.MX8qxp. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing @@ -69,6 +97,7 @@ Optional properties (required if display-timings are used): This describes how the color bits are laid out in the serialized LVDS signal. - fsl,data-width : should be <18> or <24> + Additionally, <30> for i.MX8qm. example: diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt index 96ec5179c8a0..7040fb0dfa2b 100644 --- a/Documentation/devicetree/bindings/display/mxsfb.txt +++ b/Documentation/devicetree/bindings/display/mxsfb.txt @@ -1,20 +1,69 @@ * Freescale MXS LCD Interface (LCDIF) +New bindings: +============= Required properties: -- compatible: Should be "fsl,<chip>-lcdif". Supported chips include - imx23 and imx28. -- reg: Address and length of the register set for lcdif -- interrupts: Should contain lcdif interrupts -- display : phandle to display node (see below for details) +- compatible: Should be "fsl,imx23-lcdif" for i.MX23. + Should be "fsl,imx28-lcdif" for i.MX28. + Should be "fsl,imx6sx-lcdif" for i.MX6SX. +- reg: Address and length of the register set for LCDIF +- interrupts: Should contain LCDIF interrupt +- clocks: A list of phandle + clock-specifier pairs, one for each + entry in 'clock-names'. +- clock-names: A list of clock names. For MXSFB it should contain: + - "pix" for the LCDIF block clock + - (MX6SX-only) "axi", "disp_axi" for the bus interface clock + +Required sub-nodes: + - port: The connection to an encoder chip. + +Optional properties: +- max-res: an array with a maximum of two integers, representing the + maximum supported resolution, in the form of + <maxX>, <maxY>; if one of the item is <0>, the default + driver-defined maximum resolution for that axis is used + +Example: + + lcdif1: display-controller@2220000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; + reg = <0x02220000 0x4000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pix", "axi", "disp_axi"; + + port { + parallel_out: endpoint { + remote-endpoint = <&panel_in_parallel>; + }; + }; + }; + +Deprecated bindings: +==================== +Required properties: +- compatible: Should be "fsl,imx23-lcdif" for i.MX23. + Should be "fsl,imx28-lcdif" for i.MX28. +- reg: Address and length of the register set for LCDIF +- interrupts: Should contain LCDIF interrupts +- display: phandle to display node (see below for details) + +Optional properties: +- disp-dev: Display device driver name +- disp-videomode: Display device video mode name; this is used if the panel + supports multiple video modes, in order to chose the right one (see below for + examples) * display node Required properties: -- bits-per-pixel : <16> for RGB565, <32> for RGB888/666. -- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>. +- bits-per-pixel: <16> for RGB565, <32> for RGB888/666. +- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>. Required sub-node: -- display-timings : Refer to binding doc display-timing.txt for details. +- display-timings: Refer to binding doc display-timing.txt for details. Examples: @@ -47,3 +96,46 @@ lcdif@80030000 { }; }; }; + +Examples - optional properties: + +Snippet from imx7d-sdb-mipi-dsi.dts: + +&lcdif { + disp-dev = "mipi_dsi_samsung"; + disp-videomode = "TRUULY-WVGA-SYNC-LOW"; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + +In the above example, the panel supports 2 video modes (snippet from +drivers/video/fbdev/mxc/mxcfb_hx8363_wvga.c): + +#define ACTIVE_HIGH_NAME "TRUULY-WVGA-SYNC-HIGH" +#define ACTIVE_LOW_NAME "TRUULY-WVGA-SYNC-LOW" + +static struct fb_videomode truly_lcd_modedb[] = { + { + ACTIVE_HIGH_NAME, 50, 480, 854, 41042, + 40, 60, + 3, 3, + 8, 4, + 0x0, + FB_VMODE_NONINTERLACED, + 0, + }, { + ACTIVE_LOW_NAME, 50, 480, 854, 41042, + 40, 60, + 3, 3, + 8, 4, + FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, + 0, + }, +}; diff --git a/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt new file mode 100644 index 000000000000..b245b4d68d0f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt @@ -0,0 +1,9 @@ +Japan Display Inc. 10.1" WUXGA (1920x1200) TFT LCD panel + +The panel has dual LVDS channels. + +Required properties: +- compatible: should be "jdi,tx26d202vm0bwa" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt new file mode 100644 index 000000000000..efda9db05eec --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt @@ -0,0 +1,61 @@ +Raydium RM67171 OLED LCD panel with MIPI-DSI protocol + +Required properties: +- compatible: "raydium,rm67191" +- reg: virtual channel for MIPI-DSI protocol + must be <0> +- dsi-lanes: number of DSI lanes to be used + must be <3> or <4> +- port: input port node with endpoint definition as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to a MIPI-DSI device + driver + +Optional properties: +- reset-gpio: a GPIO spec for the RST_B GPIO pin +- display-timings: timings for the connected panel according to [1] +- pinctrl-0 phandle to the pin settings for the reset pin +- panel-width-mm: physical panel width [mm] +- panel-height-mm: physical panel height [mm] +- video-mode: Video data transfer mode + must be <0>, <1> or <2> as + follows: + <0>: Burst mode + <1>: Non-burst mode with sync event + <2>: Non-burst mode with sync pulse + +[1]: Documentation/devicetree/bindings/display/display-timing.txt + +Example: + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + display-timings { + timing { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hback-porch = <11>; + hfront-porch = <4>; + vback-porch = <48>; + vfront-porch = <20>; + hsync-len = <5>; + vsync-len = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi1_out>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt new file mode 100644 index 000000000000..a8d05427f954 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt @@ -0,0 +1,73 @@ +* Freescale enhanced Direct Memory Access(eDMA-v3) Controller + + The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated + on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by + programmble memory-mapped registers. Specific DMA request source has fixed channel. + +* eDMA Controller +Required properties: +- compatible : + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC + - "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM +- reg : Specifies base physical address(s) and size of the eDMA channel registers. + Each eDMA channel has separated register's address and size. +- interrupts : A list of interrupt-specifiers, each channel has one interrupt. +- interrupt-names : Should contain below template: + "edmaX-chanX-Xx" + | | |---> receive/transmit, r or t + | |---> channel id, the max number is 32 + |---> edma controller instance, 0, 1, 2,..etc + +- #dma-cells : Must be <3>. + The 1st cell specifies the channel ID. + The 2nd cell specifies the channel priority. + The 3rd cell specifies the channel attributes which include below: + BIT(0): transmit or receive: + 0: transmit, 1: receive. + BIT(1): local or remote access: + 0: local, 1: remote. + BIT(2): dualfifo case or not(only in Audio cyclic now): + 0: not dual fifo case, 1: dualfifo case. + See the SoC's reference manual for all the supported request sources. +- dma-channels : Number of channels supported by the controller + +Examples: +edma0: dma-controller@40018000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <4>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; +}; + +* DMA clients +DMA client drivers that uses the DMA function must use the format described +in the dma.txt file, using a three-cell specifier for each channel: the 1st +specifies the channel number, the 2nd specifies the priority, and the 3rd +specifies the channel type is for transmit or receive: 0: transmit, 1: receive. + +Examples: +lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>; + clock-names = "ipg"; + assigned-clock-names = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index 191d7bd8a6fe..fc4eb68f50f2 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -9,6 +9,7 @@ group, DMAMUX0 or DMAMUX1, but not both. Required properties: - compatible : - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC + - "nxp,imx7ulp-edma" for eDMA used similar to that on NXP i.MX7ULP SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt index 7bd8847d6394..63010924d42a 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt @@ -46,3 +46,18 @@ Example: dma-names = "rx-tx"; ... }; + +* DMA capability limitation + +Specify the DMA capability limitations. +For example, some SoCs only support up to 32bit DMA capability, although +they are 64bit SoCs. + +- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA + capability. + +Example: + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 3c9a57a8443b..80174b587df3 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -9,6 +9,7 @@ Required properties: "fsl,imx53-sdma" "fsl,imx6q-sdma" "fsl,imx7d-sdma" + "fsl,imx8mq-sdma" The -to variants should be preferred since they allow to determine the correct ROM script addresses needed for the driver to work without additional firmware. @@ -50,8 +51,14 @@ The full ID of peripheral types can be found below. 22 SSI Dual FIFO (needs firmware ver >= 2) 23 Shared ASRC 24 SAI + 25 HDMI Audio -The third cell specifies the transfer priority as below. +The third cell specifies the transfer priority and software done +as below. + + Bit31: sw_done + Bit15~Bit8: selector + Bit7~Bit0: priority level ID transfer priority ------------------------- @@ -59,6 +66,9 @@ The third cell specifies the transfer priority as below. 1 Medium 2 Low +For example: 0x80000000 means sw_done enabled for done0 sector and + High priority for PDM on i.mx8mm. + Optional properties: - gpr : The phandle to the General Purpose Register (GPR) node. @@ -67,6 +77,7 @@ Optional properties: reg is the GPR register offset. shift is the bit position inside the GPR register. val is the value of the bit (0 or 1). +- fsl,ratio-1-1: AHB/SDMA core clock ration 1:1, 2:1 without this. Examples: diff --git a/Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt b/Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt new file mode 100644 index 000000000000..1865132a0441 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt @@ -0,0 +1,28 @@ +PTN5150 Extcon device + +NXP PTN5150 is an i2c interface Type-C application chip, it can detect +CC flip, attach and detech, the user can get these events through +i2c registers by GPIO interrupt. + +Required properties: +- compatible: Should be "nxp,ptn5150" +- connect-gpios: gpio interrupt for attach and detach events. +- reg: i2c slave address + +Example: +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + connect-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt index af0b903de293..dfc14f71e81f 100644 --- a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt +++ b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt @@ -5,7 +5,10 @@ connected to a GPIO pin. Required properties: - compatible: Should be "linux,extcon-usb-gpio" + +Either one of id-gpio or vbus-gpio must be present. Both can be present as well. - id-gpio: gpio for USB ID pin. See gpio binding. +- vbus-gpio: gpio for USB VBUS pin. Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below: extcon_usb1 { diff --git a/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt b/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt new file mode 100644 index 000000000000..b8d27ef108fe --- /dev/null +++ b/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt @@ -0,0 +1,105 @@ +* FSL IPUv3 Display/FB + +The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics +subsystem in an application processor. The goal of the IPU is to provide +comprehensive support for the flow of data from an image sensor or/and to a +display device. + +Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC. +Each IPU unit has two display interfaces. + +Required properties for IPU: +- bypass_reset :Bypass reset to avoid display channel being. + stopped by probe since it may start to work in bootloader: 0 or 1. +- compatible : should be "fsl,imx6q-ipu". +- reg : the register address range. +- interrupts : the error and sync interrupts request. +- clocks : the clock sources that it depends on. +- clock-names: the related clock names. +- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in + Documentation/devicetree/bindings/reset/ for details. + +Required properties for fb: +- compatible : should be "fsl,mxc_sdc_fb". +- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi". +- mode_str : "CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel, + "1920x1080M@60" for hdmi. +- default_bpp : default bits per pixel: 8/16/24/32 +- int_clk : use internal clock as pixel clock: 0 or 1 +- late_init : to avoid display channel being re-initialized + as we've probably setup the channel in bootloader: 0 or 1 +- interface_pix_fmt : display interface pixel format as below: + RGB666 IPU_PIX_FMT_RGB666 + RGB565 IPU_PIX_FMT_RGB565 + RGB24 IPU_PIX_FMT_RGB24 + BGR24 IPU_PIX_FMT_BGR24 + GBR24 IPU_PIX_FMT_GBR24 + YUV444 IPU_PIX_FMT_YUV444 + YUYV IPU_PIX_FMT_YUYV + UYVY IPU_PIX_FMT_UYVY + YVYV IPU_PIX_FMT_YVYU + VYUY IPU_PIX_FMT_VYUY + +Required properties for display: +- compatible : should be "fsl,lcd" for lcd panel +- reg : the register address range if necessary to have. +- interrupts : the error and sync interrupts if necessary to have. +- clocks : the clock sources that it depends on if necessary to have. +- clock-names: the related clock names if necessary to have. +- ipu_id : ipu id for the first display device: 0 or 1 +- disp_id : display interface id for the first display interface: 0 or 1 +- default_ifmt : save as above display interface pixel format for lcd +- pinctrl-names : should be "default" +- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the + IPU connected. +- gpr : the mux controller for the display engine's display interfaces and the display encoder + (only valid for mipi dsi now). +- disp-power-on-supply : the regulator to control display panel's power. + (only valid for mipi dsi now). +- resets : the gpio pin to reset the display device(only valid for mipi display panel now). +- lcd_panel : the video mode name for the display device(only valid for mipi display panel now). +- dev_id : the display engine's identity within the system, which intends to replace ipu_id + (only valid for mipi dsi now). + +Example for IPU: + ipu1: ipu@02400000 { + compatible = "fsl,imx6q-ipu"; + reg = <0x02400000 0x400000>; + interrupts = <0 6 0x4 0 5 0x4>; + clocks = <&clks 130>, <&clks 131>, <&clks 132>, + <&clks 39>, <&clks 40>, + <&clks 135>, <&clks 136>; + clock-names = "bus", "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; + resets = <&src 2>; + bypass_reset = <0>; + }; + +Example for fb: + fb0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + +Example for mipi dsi display: + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks 138>, <&clks 204>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + dev_id = <0>; + disp_id = <0>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on> + resets = <&mipi_dsi_reset>; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt new file mode 100644 index 000000000000..25001da92da5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt @@ -0,0 +1,57 @@ +Device-Tree bindings for drivers/gpio/gpio-imx-rpmsg.c gpio driver over +rpmsg. On i.mx7ULP PTA PTB are connected on M4 side, so rpmsg gpio driver +needed to get/set gpio status from M4 side by rpmsg. + +Required properties: +- compatible : Should be "fsl,imx-rpmsg-gpio". +- port_idx : Specify the GPIO PORT index, PTA:0, PTB:1. +- gpio-controller : Mark the device node as a gpio controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. The first cell is the GPIO number. + The second cell bits[3:0] is used to specify trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Examples: + +aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; +}; + +rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio0>; + status = "okay"; +}; + +rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio1>; + status = "okay"; +}; + +&skeleton_node { + interrupt-parent = <&rpmsg_gpio1>; + interrupts = <7 2>; + wakeup-gpios = <&rpmsg_gpio1 7 GPIO_ACTIVE_LOW>; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt index 436cc99c6598..42130d9a2ef2 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt @@ -5,7 +5,9 @@ functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of each, and each PORT module has its own interrupt. Required properties for GPIO node: -- compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio" +- compatible : Should be "fsl,<soc>-gpio", below is supported list: + "fsl,vf610-gpio" + "fsl,imx7ulp-gpio" - reg : The first reg tuple represents the PORT module, the second tuple the GPIO module. - interrupts : Should be the port interrupt shared by all 32 pins. @@ -25,6 +27,12 @@ Required properties for GPIO node: Note: Each GPIO port should have an alias correctly numbered in "aliases" node. +Optional properties: +- clocks : phandle + clock specifier pairs, one for each entry in + clock-names. +- clock-names : should contain: "port" - the Port module clock and + "gpio" - the GPIO module clock. + Examples: aliases { diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt new file mode 100644 index 000000000000..8aa0ccba8936 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt @@ -0,0 +1,20 @@ +* Freescale Low Power Inter IC (LPI2C) for i.MX + +Required properties: +- compatible : + - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc + - "fsl,imx8qm-lpi2c" for LPI2C compatible with the one integrated on i.MX8QM soc +- reg : address and length of the lpi2c master registers +- interrupt-parent : core interrupt controller +- interrupts : lpi2c interrupt +- clocks : lpi2c clock specifier + +Examples: + +lpi2c7: lpi2c7@40A50000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x40A50000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPI2C7>; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt index cf53d5fba20a..4f64e145cb2b 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt @@ -4,7 +4,8 @@ Required Properties: - compatible: Must contain one of the following. "nxp,pca9540", "nxp,pca9542", "nxp,pca9543", "nxp,pca9544", - "nxp,pca9545", "nxp,pca9546", "nxp,pca9547", "nxp,pca9548" + "nxp,pca9545", "nxp,pca9546", "nxp,pca9547", "nxp,pca9548", + "nxp,pca9646" - reg: The I2C address of the device. diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index fbbad6446741..78188250ce3b 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -42,6 +42,9 @@ domintech,dmard09 DMARD09: 3-axis Accelerometer epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE +fsl,fxas2100x FXAS2100X: Gyroscope sensor +fsl,fxos8700 FXOS8700: Accelerometer + Magnetometer Combo +fsl,isl29023 ISL29023: Intersil ISL29023 ambient light sensor fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer diff --git a/Documentation/devicetree/bindings/input/imx-rpmsg-input.txt b/Documentation/devicetree/bindings/input/imx-rpmsg-input.txt new file mode 100644 index 000000000000..397d1957e6fd --- /dev/null +++ b/Documentation/devicetree/bindings/input/imx-rpmsg-input.txt @@ -0,0 +1,12 @@ +Device-Tree bindings for inputc/rpmsg_input.c input driver over +rpmsg. For NXP i.MX7ULP EVK platform, all sensors connect with +M4, A core access sensor should communicate with M4 core by rpmsg +bus. + +Required properties: + - compatible = "fsl,rpmsg-input"; + +Examples: + rpmsg_sensor: rpmsg-sensor { + compatible = "fsl,rpmsg-input"; + }; diff --git a/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt b/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt new file mode 100644 index 000000000000..1084baa48d4f --- /dev/null +++ b/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt @@ -0,0 +1,22 @@ +Device-Tree bindings for input/keyboard/imx_sc_pwrkey.c poweron/off driver +over SCU. On i.mx8QM/QXP poweron/off key is connected on SCU side, so need +to get key event by MU. + +Required properties: + - compatible = "fsl,imx8-pwrkey"; + +Each button/key looked as the sub node: +Required properties: + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - wakeup-source: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + diff --git a/Documentation/devicetree/bindings/input/rpmsg-keys.txt b/Documentation/devicetree/bindings/input/rpmsg-keys.txt new file mode 100644 index 000000000000..d9279802cc9c --- /dev/null +++ b/Documentation/devicetree/bindings/input/rpmsg-keys.txt @@ -0,0 +1,33 @@ +Device-Tree bindings for input/keyboard/rpmsg-keys.c keys driver over +rpmsg. On i.mx7ULP keys are connected on M4 side, so rpmsg-keys driver +needed to get the key status from M4 side by rpmsg. + +Required properties: + - compatible = "fsl,rpmsg-keys"; + +Each button/key looked as the sub node: +Required properties: + - label: the key name + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - rpmsg-key,wakeup: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + rpmsg-key,wakeup; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + rpmsg-key,wakeup; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + diff --git a/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt new file mode 100644 index 000000000000..8e5257db88f6 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt @@ -0,0 +1,48 @@ +FocalTech touch controller + +The focaltech controller is connected to host processor via i2c. +The controller generates interrupts when the user touches the panel. +The host controller is expected to read the touch coordinates over +i2c and pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "focaltech,fts" + - reg : i2c slave address of the device, should be <0x38> + - interrupt-parent : parent of interrupt + - interrupts : irq gpio, "0x02" stands for that the irq triggered by falling edge. + - focaltech,irq-gpio : irq gpio, same as "interrupts" node. + - focaltech,reset-gpio : reset gpio + - focaltech,num-max-touches : maximum number of touches support + - focaltech,display-coords : display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY. + +Optional properties: + - focaltech,have-key : specify if virtual keys are supported + - focaltech,key-number : number of keys + - focaltech,keys : virtual key codes mapping to the coords + - focaltech,key-y-coord : constant y coordinate of keys, depends on the y resolution + - focaltech,key-x-coords : constant x coordinates of keys, depends on the x resolution + - focaltech,swap-xy : swap x-y coordinates + - focaltech,panel-type : set panel type, default is FT5416 panel + - focaltech,scaling-down-half : scale down the x-y coordiantes to half + + +Example: + i2c@f9927000 { + focaltech@38{ + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x02>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 1920>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + focaltech,swap-xy; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt new file mode 100644 index 000000000000..a41a0b993006 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt @@ -0,0 +1,18 @@ +* VTL Touchscreen Controller + +Required properties: +- compatible: must be "vtl,ct365" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller +- interrupts: touch controller interrupt +- gpios: the gpio pin to be used for reset + +Example: + + touchscreen@01 { + compatible = "vtl,ct365"; + reg = <0x01>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + gpios = <&gpio4 10 0>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,imx-intmux.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,imx-intmux.txt new file mode 100644 index 000000000000..8598a92bcf67 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,imx-intmux.txt @@ -0,0 +1,55 @@ +* NXP i.MX8QM/i.MX8QXP INTMUX Interrupt Multiplexing + +Required properties: +- compatible: "nxp,imx-intmux". +- reg: should contain IC registers location and length. +- clocks : ipg clock for intmux. +- interrupts: an interrupt to the parent interrupt controller. +- interrupt-controller: identifies the node as an interrupt controller. +- interrupt-parent: gic interrupt controller, link to parent +- #interrupt-cells: the number of cells to define an interrupt, should be 2. + The first cell is the IRQ number, the second cell is used to specify + one of the supported IRQ types: + IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, + IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, + IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, + IRQ_TYPE_LEVEL_LOW = active low level-sensitive. + +Optional properties: +- nxp,intmux_chans: specify the interrupt channel number, default is 1. + +Examples: + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QXP_CM40_I2C_CLK>, + <&clk IMX8QXP_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,imx-irqsteer.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,imx-irqsteer.txt new file mode 100644 index 000000000000..671622c296f0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,imx-irqsteer.txt @@ -0,0 +1,44 @@ +* NXP i.MX8QM/i.MX8QXP IRQSteer Interrupt Controllers + +Required properties: +- compatible: "nxp,imx-irqsteer". +- reg: should contain IC registers location and length. +- clocks : ipg clock for irqsteer. +- interrupts: an interrupt to the parent interrupt controller. +- interrupt-controller: identifies the node as an interrupt controller. +- interrupt-parent: gic interrupt controller, link to parent +- #interrupt-cells: the number of cells to define an interrupt, should be 2. + The first cell is the IRQ number, the second cell is used to specify + one of the supported IRQ types: + IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, + IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, + IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, + IRQ_TYPE_LEVEL_LOW = active low level-sensitive. + +Optional properties: +- nxp,irqsteer_chans: specify the interrupt channel number, default is 1. + +Examples: + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56260000 0x0 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + power-domains = <&pd_hdmi_i2c0>; + }; + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56266000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_hdmi_i2c0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov5640.txt b/Documentation/devicetree/bindings/media/i2c/ov5640.txt new file mode 100644 index 000000000000..e37fef7bc6c2 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ov5640.txt @@ -0,0 +1,114 @@ +* Omnivision OV5640 image sensor + +The Omnivision OV5640 is a 1/4" color CMOS QSXGA 5 megapixel image sensor. +All image processing functions are programmable through the SCCB interface +or embedded microcontroller. +The OV5640 supports both a digital video parallel port and a dual lane +serial MIPI port. + +The OV5640 sensor supports multiple resolutions output, such as QSXGA, 1080p, +720p, VGA, QVGA. It also can support YUV422/420, YCbCr422, RGB565/555/444, +CCIR656 or raw RGB output formats. + + +Required Properties: +- compatible: should be "ovti,ov5640_mipi" +- clocks: reference to the csi_mclk input clock. +- clock-names: should be "csi_mclk". +- reg: I2C slave address +- csi-id: virtual channel for this sensor +- mclk: used to calculate xvclk (sensor master input clock, xvclk = mclk /10000) + + +Optional Properties: +- rst-gpios: reference to the GPIO connected to the resetb pin, if any. +- pwn-gpios: reference to the GPIO connected to the pwdn pin, if any. + +The device node must contain one 'port' child node for its digital output +video port, in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Please note that the default I2C slave address is 0x3c. +In case dual-camera is used, it might be necessary to change +the I2C slave address for both cameras, and disable the reset pin, +this is if the board has only one reset line for both cameras, for +example imx-8mq-evk rev B3. Also, unique csi-id is needed for each +camera. See the dual-camera example. + + +Example for single camera: + +i2c1: i2c@30a20000 { + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + + +Example for dual-camera: + + ov5640_mipi: ov5640_mipi@1c { + compatible = "ovti,ov5640_mipi"; + reg = <0x1c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + + ov5640_mipi2: ov5640_mipi2@2c { + compatible = "ovti,ov5640_mipi"; + reg = <0x2c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt index 408f768686f1..29bc9182ea50 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ b/Documentation/devicetree/bindings/mfd/syscon.txt @@ -13,12 +13,18 @@ Required properties: - compatible: Should contain "syscon". - reg: the register region can be accessed from syscon -Optional property: +Optional properties: - reg-io-width: the size (in bytes) of the IO accesses that should be performed on the device. +- clocks: clock used for accessing the regmap Examples: gpr: iomuxc-gpr@020e0000 { compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e0000 0x38>; }; + +hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ +}; diff --git a/Documentation/devicetree/bindings/mlb/mxc_mlb.txt b/Documentation/devicetree/bindings/mlb/mxc_mlb.txt new file mode 100644 index 000000000000..e19c4e364d25 --- /dev/null +++ b/Documentation/devicetree/bindings/mlb/mxc_mlb.txt @@ -0,0 +1,26 @@ +*MediaLB (MLB) for i.MX + +Required properties: +- compatible : + - "fsl,imx6sx-mlb50" for MLB compatible with the one integrated on i.MX6SX soc + - "fsl,imx6q-mlb150" for MLB compatible with the one integrated on i.MX6Q and i.MX8 soc +- reg : address and length for mlb registers +- interrupt-parent : core interrupt controller +- interrupts : MLB Break/Error interrupt and ahb interrupt + Two ahb interrupt for imx6, ahb_int[0] and ahb_int[1] + One ahb interrupt for imx8, ahb_int[0] +- clocks : mlb clock specifier + +Examples: + +mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 3e29050ec769..229fe25a54c8 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -35,6 +35,13 @@ Optional properties: This property allows user to change the tuning step to more than one delay cells which is useful for some special boards or cards when the default tuning step can't find the proper delay window within limited tuning retries. +- fsl,strobe-dll-delay-target: Specify the strobe dll control slave delay target. + This delay target programming host controller loopback read clock, and this + property allows user to change the delay target for the strobe input read clock. + If not use this property, driver default set the delay target to value 7. + Only eMMC HS400 mode need to take care of this property. +- wifi-host : assigned as a wifi host. + This is required for Broadcom BCM WiFi cards to do card detect Examples: diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt index e25436861867..9029b45b8a22 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt @@ -18,6 +18,8 @@ Optional properties: "ext_clock" (External clock provided to the card). - post-power-on-delay-ms : Delay in ms after powering the card and de-asserting the reset-gpios (if any) +- power-off-delay-us : Delay in us after asserting the reset-gpios (if any) + during power off of the card. Example: diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 8a377827695b..4d89892c7d4b 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -12,6 +12,8 @@ Only one of the properties in this section should be supplied: - broken-cd: There is no card detection available; polling must be used. - cd-gpios: Specify GPIOs for card detection, see gpio binding - non-removable: non-removable slot (like eMMC); assume always present. + - cd-post: postone card detect from start host for non-removable cards + and let client driver to start it when ready Optional properties: - bus-width: Number of data lines, can be <1>, <4>, or <8>. The default @@ -40,6 +42,7 @@ Optional properties: - cap-mmc-hw-reset: eMMC hardware reset is supported - cap-sdio-irq: enable SDIO IRQ signalling on this interface - full-pwr-cycle: full power cycle of the card is supported +- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported @@ -74,6 +77,9 @@ Optional SDIO properties: - keep-power-in-suspend: Preserves card power during a suspend/resume cycle - wakeup-source: Enables wake up of host system on SDIO IRQ assertion (Legacy property supported: "enable-sdio-wakeup") +- pm-ignore-notify: Ignore mmc PM notify. This will prevent MMC core automatically + to re-detect cards after sysem resume back. + MMC power --------- diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt index c34aa6f8a424..951655466a11 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt @@ -1,5 +1,11 @@ * Freescale Quad Serial Peripheral Interface(QuadSPI) +The QuadSPI controller acts as the SPI master. It is described with a node +for the controller and a set of child nodes for each SPI NOR flash. + +Part I - The DT node for the controller: +------------------------------ + Required properties: - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", "fsl,imx7d-qspi", "fsl,imx6ul-qspi", @@ -24,6 +30,16 @@ Optional properties: (Please check the board's schematic.) - big-endian : That means the IP register is big endian +Part II - The DT nodes for each SPI NOR flash +------------------------------ +Required properties: +- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at + +Optional properties: + Please refer to the Documentation/devicetree/bindings/mtd/spi-nor-flash.txt + If you set the "spi-nor,ddr-quad-read-dummy", it means you enable the DDR + quad read feature for the driver. + Example: qspi0: quadspi@40044000 { diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt index d02acaff3c35..2b7133639fd8 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt @@ -4,7 +4,8 @@ The GPMI nand controller provides an interface to control the NAND flash chips. Required properties: - - compatible : should be "fsl,<chip>-gpmi-nand" + - compatible : should be "fsl,<chip>-gpmi-nand", the chip should be imx23, + imx28, imx6q, imx6qp, imx6sx, imx6ul, imx7d or imx6ull. - reg : should contain registers location and length for gpmi and bch. - reg-names: Should contain the reg names "gpmi-nand" and "bch" - interrupts : BCH interrupt number. @@ -35,6 +36,10 @@ Optional properties: partitions written from Linux with this feature turned on may not be accessible by the BootROM code. + - fsl,legacy-bch-geometry: Use legacy bch geometry(ECC scheme) that + compatible with 3.10 kernel. Without the property, + software may use ECC strength according to NAND chip + spec, e.g. ONFI standard. The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. diff --git a/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt b/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt new file mode 100644 index 000000000000..aba4d54233d2 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt @@ -0,0 +1,7 @@ +This file defines some DT properties for specific SPI NOR flash features. +The SPI NOR controller drivers may refer to this file, such as fsl-quadspi.txt + +Optional properties: + - spi-nor,ddr-quad-read-dummy: The dummy cycles used by the DDR Quad read. + Please refer to the chip's datasheet. This + property can be 4 or 6 which is less then 8. diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 56d6cc336e1c..a99d922bd662 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -17,6 +17,20 @@ Optional properties: - clock-frequency : The oscillator frequency driving the flexcan device - xceiver-supply: Regulator that powers the CAN transceiver +- stop-mode: register bits of stop mode control, the format is + <&gpr req_gpr req_bit ack_gpr ack_bit>. + gpr is the phandle to general purpose register node. + req_gpr is the gpr register offset of CAN stop request. + req_bit is the bit offset of CAN stop request. + ack_gpr is the gpr register offset of CAN stop acknowledge. + ack_bit is the bit offset of CAN stop acknowledge. +- trx_en_gpio : enable gpio +- trx_stby_gpio : standby gpio +- trx_nerr_gpio : NERR gpio +- disable-fd-mode : disable CAN FD mode support. Valid since i.MX8 series. +- clk-src : Selects the clock source to the CAN Protocol Engine (PE). It's SoC + Implementation dependent. Refer to RM for detailed definition. + 0: clock source 0 1: clock source 1 Example: diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index a1e3693cca16..555731a9eece 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -5,6 +5,13 @@ Required properties: - reg : Address and length of the register set for the device - interrupts : Should contain fec interrupt - phy-mode : See ethernet.txt file in the same directory +- clock-name: Should be the names of the clocks + - "ipg" for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing + - "ahb" for MAC ipg_clk, ipg_clk_mac that are bus clock + - "ptp" for IEEE1588 timer clock + - "enet_clk_ref" for MAC transmit/receiver reference clock + - "enet_out" output clock for external device +- clocks: Phandles to input clocks. Optional properties: - phy-reset-gpios : Should specify the gpio for phy reset @@ -30,6 +37,12 @@ Optional properties: - fsl,err006687-workaround-present: If present indicates that the system has the hardware workaround for ERR006687 applied and does not need a software workaround. +- fsl,wakeup_irq : The property define the wakeup irq index in enet irq source. +- stop-mode : If present, indicates soc need to set gpr bit to request stop + mode. +- fsl,ar8031-phy-fixup : If present, indicates board need to do phy fixup setting. +- mii-exclusive: If present, each MAC has their exclusive MDIO bus in current board + design, otherwise mutiple MACs share one MDIO bus to reduce Pins utilize. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 83aeb1f5a645..c1de909e5231 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie" +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie", + "fsl,imx8qm-pcie","fsl,imx8qxp-pcie","fsl,imx8mq-pcie","fsl,imx8mm-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -12,6 +13,8 @@ Required properties: - "msi": The interrupt that is asserted when an MSI is received - clock-names: Must include the following additional entries: - "pcie_phy" +- ext_osc: use the external oscillator or not. +- hard-wired: the port is hard wired in hw design or not. Optional properties: - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 @@ -34,6 +37,22 @@ Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: - "pcie_inbound_axi" +Additional required properties for imx8 pcie: +- hsio : should be <&hsio>. + The phandle points to the hsio region containing the hsio + such as the pcie and sata control registers. +- hsio-cfg: hsio configration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. +- ctrl-id: used to distinguish pciea or pcieb. + 0: pciea, 1: pcieb. +- cpu-base-addr: the base cpu address mapped from hsio address. + Example: + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + hsio = <&hsio>; + ctrl-id = <0>; /* pciea */ + cpu-base-addr = <0x40000000>; Example: pcie@0x01000000 { diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt b/Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt new file mode 100644 index 000000000000..7d36747871fa --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-combo-phy.txt @@ -0,0 +1,20 @@ +Mixel LVDS combo PHY + +Required properties: +- compatible: must be "mixel,lvds-combo-phy". +- reg: offset and length of the register block. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +Example: + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_mipi_dsi0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/phy/mixel,lvds-phy.txt b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.txt new file mode 100644 index 000000000000..27fb5a4c182d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,lvds-phy.txt @@ -0,0 +1,39 @@ +Mixel LVDS PHY + +This LVDS PHY supports two LVDS channels. + +Required properties: +- compatible: must be "mixel,lvds-phy". +- reg: offset and length of the register block. +- #address-cells: number of address cells for the LVDS channel subnodes, must + be <1>. +- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +The LVDS PHY device tree node should have the subnodes corresponding to the two +LVDS channels. These subnodes must contain the following properties: +- reg: the PHY ID. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. + +Example: + ldb1_phy: ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds0>; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file mode 100644 index 000000000000..c868b39a88b7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt @@ -0,0 +1,23 @@ +Mixel DSI DPHY for MX8 + +The MIPI-DSI DPHY IP block found on MX8 platforms comes along the MIPI-DSI +IP from Northwest Logic and represents the physical layer for the electrical +signals for DSI. + +Required properties: +- compatible: "mixel,<soc>-mipi-dsi-phy" +- reg: the register range of the PHY controller +- #phy-cells: number of cells in PHY, as defined in + Documentation/devicetree/bindings/phy/phy-bindings.txt + this must be <0> + +Optional properties: +- power-domains: phandle to power domain + +Example: + mipi0_phy: mipi0_phy@56228300 { + compatible = "mixel,imx8qm-mipi-dsi-phy"; + reg = <0x0 0x56228300 0x0 0x100>; + power-domains = <&pd_mipi0>; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index 1d25b04cd05e..415dc0d05805 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -7,6 +7,8 @@ Required properties: * "fsl,imx6sl-usbphy" for imx6sl * "fsl,vf610-usbphy" for Vybrid vf610 * "fsl,imx6sx-usbphy" for imx6sx + * "fsl,imx6ul-usbphy" for imx6ul + * "fsl,imx7ulp-usbphy" for imx7ulp "fsl,imx23-usbphy" is still a fallback for other strings - reg: Should contain registers location and length - interrupts: Should contain phy interrupt @@ -21,6 +23,9 @@ Optional properties: that terminates the DP output signal. Default: 45 - fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of the 17.78mA TX reference current. Default: 100 +- tx-d-cal: Try to adjust this value to improve signal quality, and pass + USB Certification, the value is from 0x0 to 0xf, and the register offset + is 0x10 (USBPHY_TX). Example: usbphy1: usbphy@020c9000 { @@ -28,4 +33,5 @@ usbphy1: usbphy@020c9000 { reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; fsl,anatop = <&anatop>; + tx-d-cal = <0x5>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file mode 100644 index 000000000000..541aead62607 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt @@ -0,0 +1,33 @@ +* Freescale i.MX7ULP IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7ulp-iomuxc-0" or "fsl,imx7ulp-iomuxc-1" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a + pin working on a specific function, CONFIG is the pad setting value like + pull-up for this pin. Please refer to imx7ulp datasheet for the valid pad + config settings. + +NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux and +config register as follows: +<mux_conf_reg input_reg mux_mode input_val> + +CONFIG bits definition: +PAD_CTL_OBE (1 << 17) +PAD_CTL_IBE (1 << 16) +PAD_CTL_LK (1 << 15) +PAD_CTL_DSE_HIGH (1 << 6) +PAD_CTL_DSE_STD (0 << 6) +PAD_CTL_ODE_OPEN_DRAIN (1 << 5) +PAD_CTL_ODE_PUSH_PULL (0 << 5) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_STD (0 << 2) +PAD_CTL_PE_PULL (1 << 1) +PAD_CTL_PS_UP (1 << 0) +PAD_CTL_PS_DOWN (0 << 0) + +Refer to imx7ulp-pinfunc.h in device tree source folder for all available +imx7ulp PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt new file mode 100644 index 000000000000..380233d3931a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt @@ -0,0 +1,36 @@ +* Freescale i.MX8M Mini IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx8mm-iomuxc" for IOMUXC controller. +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + pins-imx8mm.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_LVTTL (1 << 8) +PAD_CTL_HYS (1 << 7) +PAD_CTL_PUE (1 << 6) +PAD_CTL_ODE (1 << 5) +PAD_CTL_SRE_SLOW (0 << 3) +PAD_CTL_SRE_MED (1 << 3) +PAD_CTL_SRE_FAST (2 << 3) +PAD_CTL_SRE_MAX (3 << 3) +PAD_CTL_DSE_HIZ (0 << 0) +PAD_CTL_DSE_255 (1 << 0) +PAD_CTL_DSE_105 (2 << 0) +PAD_CTL_DSE_75 (3 << 0) +PAD_CTL_DSE_85 (4 << 0) +PAD_CTL_DSE_65 (5 << 0) +PAD_CTL_DSE_45 (6 << 0) +PAD_CTL_DSE_40 (7 << 0) + +iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt new file mode 100644 index 000000000000..efee1106a6d6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt @@ -0,0 +1,36 @@ +* Freescale i.MX8M Qual IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx8mq-iomuxc" for IOMUXC controller. +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + pins-imx8mq.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Qual + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_LVTTL (1 << 8) +PAD_CTL_HYS (1 << 7) +PAD_CTL_PUE (1 << 6) +PAD_CTL_ODE (1 << 5) +PAD_CTL_SRE_SLOW (0 << 3) +PAD_CTL_SRE_MED (1 << 3) +PAD_CTL_SRE_FAST (2 << 3) +PAD_CTL_SRE_MAX (3 << 3) +PAD_CTL_DSE_HIZ (0 << 0) +PAD_CTL_DSE_255 (1 << 0) +PAD_CTL_DSE_105 (2 << 0) +PAD_CTL_DSE_75 (3 << 0) +PAD_CTL_DSE_85 (4 << 0) +PAD_CTL_DSE_65 (5 << 0) +PAD_CTL_DSE_45 (6 << 0) +PAD_CTL_DSE_40 (7 << 0) + +iomuxc: iomuxc@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qm-pinctrl.txt new file mode 100644 index 000000000000..68423ea288bc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qm-pinctrl.txt @@ -0,0 +1,73 @@ +* Freescale i.MX8QM IOMUX Controller + +Required properties: +- compatible: "fsl,imx8qm-iomuxc" +- fsl,pins: each entry consists of 2 integers. Its format is + <pin_id pin_config>. + +pin_config definition: +- i.MX8QM have different pad types, please refer to below pad + register definitions, the pinctrl driver will just write the + pin_config into the hardware register. + +typedef union _hw_pad_iomux +{ + uint32_t U; + struct _hw_pad_iomux_bitfields0 + { + uint32_t GP : 19; /*!< [18:0] GP controls. */ + uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */ + uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t CONFIG : 2; /*!< [26:25] Config. */ + uint32_t IFMUX : 3; /*!< [29:27] Mux. */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } B; + struct _hw_pad_iomux_28fdsoi + { + uint32_t DSE : 3; /*!< [2:0] Drive strength. */ + uint32_t _reserved1 : 2; /*!< [4:3] */ + uint32_t PS : 2; /*!< [6:5] Pull select. */ + uint32_t _reserved2 : 12; /*!< [18:7] */ + uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */ + uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t CONFIG : 2; /*!< [26:25] Config. */ + uint32_t IFMUX : 3; /*!< [29:27] Mux. */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } FDS0I28; + struct _hw_pad_iomux_28fdsoi_hsic + { + uint32_t DSE : 3; /*!< [2:0] Drive strength. */ + uint32_t HYS : 1; /*!< [3] Hysteresis. */ + uint32_t PUS : 2; /*!< [5:4] Pull-up select. */ + uint32_t PKE : 1; /*!< [6] Pad keeper enable. */ + uint32_t PUE : 1; /*!< [7] Pull-up enable. */ + uint32_t _reserved2 : 11; /*!< [18:8] */ + uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */ + uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t CONFIG : 2; /*!< [26:25] Config. */ + uint32_t IFMUX : 3; /*!< [29:27] Mux. */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } FDS0I28_HSIC; + struct _hw_pad_iomux_28fdsoi_comp + { + uint32_t COMPEN : 3; /*!< [2:0] Mode. */ + uint32_t FASTFRZ : 1; /*!< [3] Fast freeze. */ + uint32_t PSW_OVR : 1; /*!< [4] 2.5 volt override */ + uint32_t RASRCP : 4; /*!< [8:5] PMOS comp. */ + uint32_t RASRCN : 4; /*!< [12:9] NMOS comp. */ + uint32_t NASRC_SEL : 1; /*!< [13] Read NASRC select. */ + uint32_t COMPOK : 1; /*!< [14] Comp status. */ + uint32_t NASRC : 4; /*!< [18:15] NASRC value. */ + uint32_t _reserved2 : 4; /*!< [22:19] */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t _reserved3 : 5; /*!< [29:25] */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } FDS0I28_COMP; +} hw_pad_iomux_t; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt new file mode 100644 index 000000000000..4ea92de8e1ca --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt @@ -0,0 +1,73 @@ +* Freescale i.MX8QXP IOMUX Controller + +Required properties: +- compatible: "fsl,imx8qxp-iomuxc" +- fsl,pins: each entry consists of 2 integers. Its format is + <pin_id pin_config>. + +pin_config definition: +- i.MX8QXP have different pad types, please refer to below pad + register definitions, the pinctrl driver will just write the + pin_config into the hardware register. + +typedef union _hw_pad_iomux +{ + uint32_t U; + struct _hw_pad_iomux_bitfields0 + { + uint32_t GP : 19; /*!< [18:0] GP controls. */ + uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */ + uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t CONFIG : 2; /*!< [26:25] Config. */ + uint32_t IFMUX : 3; /*!< [29:27] Mux. */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } B; + struct _hw_pad_iomux_28fdsoi + { + uint32_t DSE : 3; /*!< [2:0] Drive strength. */ + uint32_t _reserved1 : 2; /*!< [4:3] */ + uint32_t PS : 2; /*!< [6:5] Pull select. */ + uint32_t _reserved2 : 12; /*!< [18:7] */ + uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */ + uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t CONFIG : 2; /*!< [26:25] Config. */ + uint32_t IFMUX : 3; /*!< [29:27] Mux. */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } FDS0I28; + struct _hw_pad_iomux_28fdsoi_hsic + { + uint32_t DSE : 3; /*!< [2:0] Drive strength. */ + uint32_t HYS : 1; /*!< [3] Hysteresis. */ + uint32_t PUS : 2; /*!< [5:4] Pull-up select. */ + uint32_t PKE : 1; /*!< [6] Pad keeper enable. */ + uint32_t PUE : 1; /*!< [7] Pull-up enable. */ + uint32_t _reserved2 : 11; /*!< [18:8] */ + uint32_t WAKEUP : 3; /*!< [21:19] Wakeup controls. */ + uint32_t WAKEUP_ENB : 1; /*!< [22] Wakeup write enable. */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t CONFIG : 2; /*!< [26:25] Config. */ + uint32_t IFMUX : 3; /*!< [29:27] Mux. */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } FDS0I28_HSIC; + struct _hw_pad_iomux_28fdsoi_comp + { + uint32_t COMPEN : 3; /*!< [2:0] Mode. */ + uint32_t FASTFRZ : 1; /*!< [3] Fast freeze. */ + uint32_t PSW_OVR : 1; /*!< [4] 2.5 volt override */ + uint32_t RASRCP : 4; /*!< [8:5] PMOS comp. */ + uint32_t RASRCN : 4; /*!< [12:9] NMOS comp. */ + uint32_t NASRC_SEL : 1; /*!< [13] Read NASRC select. */ + uint32_t COMPOK : 1; /*!< [14] Comp status. */ + uint32_t NASRC : 4; /*!< [18:15] NASRC value. */ + uint32_t _reserved2 : 4; /*!< [22:19] */ + uint32_t LPCONFIG : 2; /*!< [24:23] Low-power config. */ + uint32_t _reserved3 : 5; /*!< [29:25] */ + uint32_t GP_ENB : 1; /*!< [30] GP write enable. */ + uint32_t IFMUX_ENB : 1; /*!< [31] Mux write enable. */ + } FDS0I28_COMP; +} hw_pad_iomux_t; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index b73c96d24f59..05ede5f4509a 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -71,6 +71,13 @@ pinctrl-names: The list of names to assign states. List entry 0 defines the name for integer state ID 0, list entry 1 for state ID 1, and so on. +pinctrl-assert-gpios: + List of phandles, each pointing at a GPIO which is used by some + board design to steer pins between two peripherals on the board. + It plays like a board level pin multiplexer to choose different + functions for given pins by pulling up/down the GPIOs. See + bindings/gpio/gpio.txt for details of how to specify GPIO. + For example: /* For a client device requiring named states */ diff --git a/Documentation/devicetree/bindings/pwm/nxp,tpm-pwm.txt b/Documentation/devicetree/bindings/pwm/nxp,tpm-pwm.txt new file mode 100644 index 000000000000..ac445a7ceb93 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nxp,tpm-pwm.txt @@ -0,0 +1,18 @@ +NXP TPM PWM controller + +Required properties: +- compatible: should be "nxp,tpm-pwm" +- reg: physical base address and length of the controller's registers +- #pwm-cells: should be 2. See pwm.txt in this directory for a description of + the cells format. +- nxp,pwm-number: the number of PWM devices + +Example: + +pwm0: tpm@40250000 { + compatible = "nxp,tpm-pwm"; + reg = <0x40250000 0x1000>; + nxp,pwm-number = <6>; + #pwm-cells = <2>; +}; + diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt index 37c4ea076f88..03ea26d9ccba 100644 --- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt @@ -14,6 +14,7 @@ Optional properties: - anatop-delay-bit-shift: Bit shift for the step time register - anatop-delay-bit-width: Number of bits used in the step time register - vin-supply: The supply for this regulator +- anatop-enable-bit: Regulator output offset bit, only for 3p0, 2p5, and 1p1. Any property defined as part of the core regulator binding, defined in regulator.txt, can also be used. @@ -35,4 +36,5 @@ Example: anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1300000>; + anatop-enable-bit = <0>; }; diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt index 9b40db88f637..997174a46518 100644 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt @@ -3,6 +3,8 @@ PFUZE100 family of regulators Required properties: - compatible: "fsl,pfuze100", "fsl,pfuze200", "fsl,pfuze3000" - reg: I2C slave address +- fsl,lpsr-mode: some registers need to be saved and restored in lpsr mode + for pfuze3000 Required child node: - regulators: This is the list of child nodes that specify the regulator diff --git a/Documentation/devicetree/bindings/reset/gpio-reset.txt b/Documentation/devicetree/bindings/reset/gpio-reset.txt new file mode 100644 index 000000000000..7d45d8b810ea --- /dev/null +++ b/Documentation/devicetree/bindings/reset/gpio-reset.txt @@ -0,0 +1,36 @@ +GPIO reset controller +===================== + +A GPIO reset controller controls a single GPIO that is connected to the reset +pin of a peripheral IC. Please also refer to reset.txt in this directory for +common reset controller binding usage. + +Required properties: +- compatible: Should be "gpio-reset" +- reset-gpios: A gpio used as reset line. The gpio specifier for this property + depends on the gpio controller that provides the gpio. +- #reset-cells: 0, see below + +Optional properties: +- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for + this duration to reset. +- reset-post-delay-ms: delay in milliseconds to wait after reset. +- initially-in-reset: boolean. If not set, the initial state should be a + deasserted reset line. If this property exists, the + reset line should be kept in reset. + +example: + +sii902x_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + initially-in-reset; + #reset-cells = <0>; +}; + +/* Device with nRESET pin connected to GPIO5_0 */ +sii902x@39 { + /* ... */ + resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */ +}; diff --git a/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt new file mode 100644 index 000000000000..331520494c95 --- /dev/null +++ b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt @@ -0,0 +1,60 @@ +i.MX RPMSG platform implementations + +Required properties: +- compatible : "fsl,imx7d-rpmsg", "fsl,imx6sx-rpmsg". + "fsl,rpmsg-bus", "simple-bus", "fsl,imx8qxp-rpmsg". + "fsl,imx8qm-rpmsg". +- vdev-nums : The number of the remote virtual devices. +- reg : The reserved DDR phisical memory used to store + vring descriptors. +- multi-core-id: The id number of the remote processors. + And it is optional for the legacy platforms, since they + only have one remote processors. + + +===================================================================== +message unit module for RPMSG + +- mu_rpmsg : The message unit module used to do the communications + between the asymmetric cores. +- compatible : "fsl,imx8mq-mu", "fsl,imx6sx-mu", "fsl,imx-mu-rpmsg1". + Different mu module would be used by the different remote processor. + The "fsl, imx6sx-mu" is used by the first remote processor. + The "fsl,imx-mu-rpmsg1" is used by the second remote process. +- reg : Should contain MU registers location and length. +- interrupts : interrupt mapping for RPMSG MU IRQ +- interrupt-parent : A single value that points to the interrupt + parent to which the child domain is being mapped. + Value must be "&intmux_cm40" or "&intmux_cm41" + +Example: +rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + status = "disabled"; +}; + +&rpmsg{ + vdev-nums = <1>; + reg = <0xbfff0000 0x10000>; + status = "okay"; +}; + +imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu_rpmsg: mu_rpmsg@37440000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x37440000 0x0 0x10000>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + status = "disabled"; + }; +}; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005efbcb8..9ad9ddc7c666 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,14 +6,24 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization + - "fsl,imx8qm-lpuart"for lpuart compatible with the one integrated + on i.MX8QM SoC with 32-bit little-endian register organization, which + is based on i.MX7ULP lpuart IP but add EEOP new feature. - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- clock-names : should contain: "ipg" - the uart clock +- clock-names : should contain: "ipg" - the uart peripheral register accessing + clock source, if "per" clock missing, the "ipg" clock also is the uart module + clock. Optional properties: - dmas: A list of two dma specifiers, one for each entry in dma-names. - dma-names: should contain "tx" and "rx". +- clocks : phandle + clock specifier pairs, one for each entry in clock-names +- clock-names : "per" - the uart module clock. + clock. Note: Optional properties for DMA support. Write them both or both not. diff --git a/Documentation/devicetree/bindings/sim/imx_emvsim.txt b/Documentation/devicetree/bindings/sim/imx_emvsim.txt new file mode 100644 index 000000000000..29efb4a956ff --- /dev/null +++ b/Documentation/devicetree/bindings/sim/imx_emvsim.txt @@ -0,0 +1,22 @@ +* NXP EMVSIM for i.MX8 + +Required properties: +- compatible : + - "fsl,imx8-emvsim" for EMVSIM compatible with the one integrated on i.MX8 soc +- reg : address and length of EMVSIM registers +- interrupt : core interrupt controller +- clocks : EMVSIM clock specifier +- power-domains : power domain for EMVSIM + +Examples: + +emvsim0: sim0@5a0d0000 { + compatible = "fsl,imx8-emvsim"; + reg = <0x0 0x5a0d0000 0x0 0x10000>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_EMVSIM0_CLK>, + <&clk IMX8QM_EMVSIM0_IPG_CLK>; + clock-names = "sim", "ipg"; + power-domains = <&pd_ldo1_sim>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sim/imx_sim.txt b/Documentation/devicetree/bindings/sim/imx_sim.txt new file mode 100644 index 000000000000..58e709b09ae3 --- /dev/null +++ b/Documentation/devicetree/bindings/sim/imx_sim.txt @@ -0,0 +1,20 @@ +* NXP SIMv2 for i.MX6ul and i.MX7d + +Required properties: +- compatible : + - "fsl,imx7d-sim" for SIMv2 compatible with the one integrated on i.MX7d soc + - "fsl,imx6ul-sim" for SIMv2 compatible with the one integrated on i.MX6ul soc +- reg : address and length of SIMv2 registers +- interrupt : core interrupt controller +- clocks : SIMv2 clock specifier + +Examples: + +sim2: sim@021b4000 { + compatible = "fsl,imx6ul-sim"; + reg = <0x021b4000 0x4000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_SIM2>; + clock-names = "sim"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/soc/fsl/gpc.txt b/Documentation/devicetree/bindings/soc/fsl/gpc.txt new file mode 100644 index 000000000000..a7d29282f8e3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/gpc.txt @@ -0,0 +1,56 @@ +* General Power Controller (GPC) +------------------------------------------- +The General Power Controller (GPC) module controls the following functions: + - Provide low power mode control for A7 and M4 platform + - Provide Power domain management all ARM and SOC power domain + - Provide domain control mechanism based on A7 and M4 CPU domain + - Provide handshake with CCM for clock management in low power mode + - Provide handshake with SRC for power down and power up sequence + - Provide handshake with Analog for Deep Sleep Mode control + +Required properties: + - reg : Offset and length of the register set of the GPC block. + - compatible : Must contain a chip-specific GPC block compatible string + and (if applicable) may contain a chassis-version GPC compatible + string. Chip-specific strings are of the form "fsl,<chip>-gpc", + such as: + * "fsl,imx7d-gpc" + * "fsl,imx7s-gpc" + - interrupt-controller : Specifies that this is an interrupt controller + +Example: +The GPC node for imx7d: + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + }; + +* Power Gating Controller (PGC) +------------------------------------------- +The Power Gating Controller (PGC) is a power management component that controls the +power-down and power-up sequencing of individual subsystems. +The PGC block is found inside GPC, and share the same register. + +Required properties: + - compatible : Must contain a chip-specific PGC block compatible string + and (if applicable) may contain a chassis-version PGC compatible + string. Chip-specific strings are of the form "fsl,<chip>-pgc", + such as: + * "fsl,imx7d-pgc" + * "fsl,imx7s-pgc" + - *-supply : Specifies the regulators that can be managed by this PGC. For exampe: + * "mipi-phy-supply = <®_1p0d>;" + +Example: +The PGC node for imx7d: + pgc { + compatible = "fsl,imx7d-pgc"; + mipi-phy-supply = <®_1p0d>; + pcie-phy-supply = <®_1p0d>; + vcc-supply = <®_1p2>; + }; diff --git a/Documentation/devicetree/bindings/sound/ak4458.txt b/Documentation/devicetree/bindings/sound/ak4458.txt new file mode 100644 index 000000000000..b9e6eb3b103d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak4458.txt @@ -0,0 +1,23 @@ +AK4458 audio DAC + +This device supports both I2C and SPI modes. + +Required properties: + +- compatible : "asahi-kasei,ak4458" +- reg : The I2C address of the device for I2C, the chip select number for SPI. +- asahi-kasei,pdn-gpios: A GPIO specifier for the GPIO controlling + the power down & reset pin. +- asahi-kasei,mute-gpios: A GPIO specifier for the GPIO controlling + the soft mute pin. + +Example: + +&i2c { + ak4458: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + asahi-kasei,pdn-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH> + asahi-kasei,mute-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH> + }; +}; diff --git a/Documentation/devicetree/bindings/sound/ak4497.txt b/Documentation/devicetree/bindings/sound/ak4497.txt new file mode 100644 index 000000000000..f1fd59f3c959 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak4497.txt @@ -0,0 +1,23 @@ +AK4497 audio codec + +This device supports I2C mode only. + +Required properties: + +- compatible : "asahi-kasei,ak4497" +- reg : The I2C address of the device. +- asahi-kasei,pdn-gpio: A GPIO specifier for the GPIO controlling + the power down & reset pin. +- asahi-kasei,mute-gpio: A GPIO specifier for the GPIO controlling + the soft mute pin. + +Example: + +&i2c { + ak4458: ak4458@0x10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + asahi-kasei,pdn-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH> + asahi-kasei,mute-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH> + }; +}; diff --git a/Documentation/devicetree/bindings/sound/ak5558.txt b/Documentation/devicetree/bindings/sound/ak5558.txt new file mode 100644 index 000000000000..11b36f9c9fee --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak5558.txt @@ -0,0 +1,20 @@ +AK5558 audio ADC + +This device supports I2C mode only. + +Required properties: + +- compatible : "asahi-kasei,ak5558" +- reg : The I2C address of the device for I2C. +- asahi-kasei,pdn-gpios: A GPIO specifier for the GPIO controlling + the power down & reset pin. + +Example: + +&i2c { + ak5558: ak5558@10 { + compatible = "asahi-kasei,ak5558"; + reg = <0x10>; + asahi-kasei,pdn-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,acm.txt b/Documentation/devicetree/bindings/sound/fsl,acm.txt new file mode 100644 index 000000000000..05d224ad18ab --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,acm.txt @@ -0,0 +1,18 @@ +NXP Audio Clock Mux (ACM) + +The Audio Clock Mux (ACM) is a collection of control registers and multiplexers +that are used to route the audio source clocks to the audio peripherals. +Each audio peripheral has its dedicated audio clock mux and control register. + +Required properties: + + - compatible : Contains "nxp,imx8qm-acm". + - reg : Offset and length of the register set for the device. + +Example: + +acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,amix.txt b/Documentation/devicetree/bindings/sound/fsl,amix.txt new file mode 100644 index 000000000000..d4920e88e466 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,amix.txt @@ -0,0 +1,67 @@ +NXP Audio Mixer (AMIX). + +The Audio Mixer is a on-chip functional module that allows mixing of two audio +streams into a single audio stream. Audio Mixer has two input serial audio +interfaces. These are driven by two Synchronous Audio interface modules (SAI). +Each input serial interface carries 8 audio channels in its frame in TDM manner. +Mixer mixes audio samples of corresponding channels from two interfaces into a +single sample. Before mixing, audio samples of two inputs can be attenuated +based on configuration. The output of the Audio Mixer is also a serial audio +interface. Like input interfaces it has the same TDM frame format. This output +is used to drive the serial DAC TDM interface of audio codec and also sent to +the external pins along with the receive path of normal audio SAI module for +readback by the CPU. + +The output of Audio mixer can be selected from any of the three streams + - serial audio input 1 + - serial audio input 2 + - Mixed audio + +Mixing operation is independent of audio sample rate but the two audio input +streams must have same audio sample rate with same number of channels in TDM +frame to be eligible for mixing. + +Device driver required properties: +================================= + - compatible : Compatible list, contains "fsl,imx8qm-amix" + + - reg : Offset and length of the register set for the device. + + - clocks : Must contain an entry for each entry in clock-names. + + - clock-names : Must include the "ipg" for register access. + + - power-domains : Must contain the phandle to the AMIX power domain node + +Device driver configuration example: +====================================== + amix: amix@59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + }; + +Machine driver required properties: +=================================== + - compatible : Compatible list, contains "fsl,imx-audio-amix" + + - model : Short audio card description. + + - dais : Must contain a list of phandles to AMIX connected + DAIs. The current implementation requires two phandles + to SAI interfaces to be provided, the first SAI in the + list being used to route the AMIX output. + + - amix-controller : Must contain the phandle to the AMIX device node. + +Machine driver configuration example: +==================================== + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai4>, <&sai5>; + amix-controller = <&amix>; + }; + diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index 3e26a9478e57..702aef99fc61 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -8,7 +8,8 @@ three substreams within totally 10 channels. Required properties: - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". + - compatible : Contains "fsl,imx35-asrc", "fsl,imx53-asrc", + "fsl,imx8qm-asrc0" or "fsl,imx8qm-asrc1". - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/fsl,dsp.txt b/Documentation/devicetree/bindings/sound/fsl,dsp.txt new file mode 100644 index 000000000000..84bc228b4e32 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,dsp.txt @@ -0,0 +1,16 @@ +NXP DSP + +The IP is from Cadence. + +Required properties: + + - compatible : Contains "fsl,imx8qxp-dsp". + - reg : Offset and length of the register set for the device. + +Example: + +dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reg = <0x0 0x596e8000 0x0 0x88000>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index cd3ee5d84f03..bcb4d3fa2f9e 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt @@ -7,8 +7,9 @@ other DSPs. It has up to six transmitters and four receivers. Required properties: - - compatible : Compatible list, must contain "fsl,imx35-esai" or - "fsl,vf610-esai" + - compatible : Compatible list, must contain "fsl,imx6ull-esai", + "fsl,imx8qxp-v1-esai", "fsl,imx8qm-esai" + "fsl,imx35-esai" or "fsl,vf610-esai" - reg : Offset and length of the register set for the device. @@ -46,6 +47,10 @@ Required properties: will be in use as default, or the big endian mode will be in use for all the device registers. + - fsl,dma-buffer-size: It specify the audio buffer size of playback and + capture. If this property is absent, using the default value of audio buffer + size. + Example: esai: esai@02024000 { diff --git a/Documentation/devicetree/bindings/sound/fsl,micfil.txt b/Documentation/devicetree/bindings/sound/fsl,micfil.txt new file mode 100644 index 000000000000..d7830af62062 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,micfil.txt @@ -0,0 +1,38 @@ +Freescale MICFIL PDM Interface (MICFIL). + +The MICFIL digital interface provides a 16-bit audio signal from a PDM +microphone bitstream in a configurable output sampling rate. + +Required properties: + + - compatible : Compatible list, contains "fsl,imx8mm-micfil" + + - reg : Offset and length of the register set for the device. + + - interrupts : Contains the micfil interrupts. + + - clocks : Must contain an entry for each entry in clock-names. + + - clock-names : Must include the "ipg_clk" for register access and + "ipg_clk_app" for internal micfil clock. + + - dmas : Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. + + - dma-names : One "rx" dma must be configured. + +Example: +micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>; + clock-names = "ipg_clk", "ipg_clk_app"; + dmas = <&sdma2 24 26 0x80000000>; + dma-names = "rx"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.txt b/Documentation/devicetree/bindings/sound/fsl,mqs.txt new file mode 100644 index 000000000000..4e81e902541c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.txt @@ -0,0 +1,23 @@ +fsl,mqs audio CODEC + +Required properties: + + - compatible : must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs" + "fsl,imx8qm-mqs", "fsl,imx8qxp-mqs". + + - clocks : a list of phandles + clock-specifiers, one for each entry in + clock-names + + - clock-names : must contain "mclk" + + - gpr : the gpr node. + +Example: + +mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt new file mode 100644 index 000000000000..5f8c6cbbe5da --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt @@ -0,0 +1,21 @@ +Freescale rpmsg i2s interface. + +The rpmsg i2s is based on RPMSG that used communicating with M4 core, +which provides a synchronous audio interface that supports fullduplex +serial interfaces with frame synchronization such as I2S. + +Required properties: + + - compatible : Compatible list, contains "fsl,imx7ulp-rpmsg-i2s". + "fsl,imx8mq-rpmsg-i2s", "fsl,imx8qxp-rpmsg-i2s" + + - fsl,audioindex : This is an index indicating the audio device index in + the M4 side. + +Example: +rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx7ulp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index 4ca39ddc0417..564d96856512 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -6,7 +6,10 @@ a fibre cable. Required properties: - - compatible : Compatible list, must contain "fsl,imx35-spdif". + - compatible : Compatible list, must contain "fsl,imx35-spdif", + "fsl,vf610-spdif", "fsl,imx8qm-spdif", + "fsl,imx8qxp-v1-spdif", "fsl,imx8mq-spdif", + "fsl,imx8mm-spdif" - reg : Offset and length of the register set for the device. @@ -37,6 +40,10 @@ Required properties: will be in use as default, or the big endian mode will be in use for all the device registers. + - fsl,dma-buffer-size: It specify the audio buffer size of playback and + capture. If this property is absent, using the default value of audio buffer + size. + Example: spdif: spdif@02004000 { diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt index 5b76be45d18b..3ad10966d3a5 100644 --- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt +++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt @@ -62,6 +62,10 @@ Optional properties: "ac97-slave" - AC97 mode, SSI is clock slave "ac97-master" - AC97 mode, SSI is clock master +- fsl,dma-buffer-size: It specify the audio buffer size of playback and + capture. If this property is absent, using the default value of audio buffer + size. + Child 'codec' node required properties: - compatible: Compatible list, contains the name of the codec diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 740b467adf7d..13528e46d05b 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -8,7 +8,8 @@ codec/DSP interfaces. Required properties: - compatible : Compatible list, contains "fsl,vf610-sai", - "fsl,imx6sx-sai" or "fsl,imx6ul-sai" + "fsl,imx6sx-sai", "fsl,imx6ul-sai", + "fsl,imx8qm-sai" or "fsl,imx8mq-sai" - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt new file mode 100644 index 000000000000..a442d3edd62d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with AK4458 DAC + +Required properties: + +- compatible : "fsl,imx-audio-ak4458", "fsl,imx-audio-ak4458-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the AK4458 audio DAC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, AK4458 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "AOUTL1", "Playback", + "AOUTR1", "Playback", + "AOUTL2", "Playback", + "AOUTR2", "Playback", + "AOUTL3", "Playback", + "AOUTR3", "Playback", + "AOUTL4", "Playback", + "AOUTR4", "Playback"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt new file mode 100644 index 000000000000..7eeeeeda74f5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt @@ -0,0 +1,27 @@ +Freescale i.MX audio complex with AK4497 DAC + +Required properties: + +- compatible : "fsl,imx-audio-ak4497", "fsl,imx-audio-ak4497-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the ak4497 audio DAC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, ak4497 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + audio-routing = + "AOUTLN", "Playback", + "AOUTLP", "Playback", + "AOUTRN", "Playback", + "AOUTRP", "Playback", +}; + diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt new file mode 100644 index 000000000000..7b62fbb14f8d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with AK5558 ADC + +Required properties: + +- compatible : "fsl,imx-audio-ak5558", "fsl,imx-audio-ak5558-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the AK5558 audio ADC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, AK5558 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "AIN1", "Capture", + "AIN2", "Capture", + "AIN3", "Capture", + "AIN4", "Capture", + "AIN5", "Capture", + "AIN6", "Capture", + "AIN7", "Capture", + "AIN8", "Capture"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt b/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt new file mode 100644 index 000000000000..2b46b385f021 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt @@ -0,0 +1,16 @@ +Freescale i.MX audio complex with Cadence HDMI + +Required properties: +- compatible : "fsl,imx-audio-cdnhdmi" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of the i.MX SAI controller +- protocol : 0 is hdmi, 1 is dp. + +Example: + +sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <0>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt new file mode 100644 index 000000000000..7e5148f081b3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt @@ -0,0 +1,27 @@ +Freescale i.MX audio complex with CS42888 codec + +Required properties: +- compatible : "fsl,imx-audio-cs42888", or + "fsl,imx8qm-sabreauto-cs42888" or + "fsl,imx8qxp-sabreauto-cs42888" +- model : The user-visible name of this sound complex +- esai-controller : The phandle of the i.MX SSI controller +- audio-codec : The phandle of the CS42888 audio codec + +Optional properties: +- asrc-controller : The phandle of the i.MX ASRC controller +- audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names could be power + supplies, CS42888 pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "cs42888-audio"; + esai-controller = <&esai>; + asrc-controller = <&asrc_p2p>; + audio-codec = <&codec>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt new file mode 100644 index 000000000000..10ae15a645d3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt @@ -0,0 +1,18 @@ +Freescale i.MX audio complex with mqs codec + +Required properties: +- compatible : "fsl,imx-audio-mqs", "fsl,imx8qm-lpddr4-arm2-mqs", "fsl,imx8qxp-lpddr4-arm2-mqs" +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX sai controller +- audio-codec : The phandle of the mqs audio codec + +Example: + +sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; +}; + diff --git a/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt new file mode 100644 index 000000000000..3f015974ffeb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt @@ -0,0 +1,13 @@ +Freescale i.MX audio complex with rpmsg devices + +Required properties: +- compatible : "fsl,imx-audio-rpmsg" +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX rpmsg i2s device. + +Example: +sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "rpmsg-audio"; + cpu-dai = <&rpmsg_i2s>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt new file mode 100644 index 000000000000..53cd34afe6b8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt @@ -0,0 +1,24 @@ +Freescale i.MX audio complex with si476x codec + +Required properties: +- compatible : "fsl,imx-audio-si476x" +- model : The user-visible name of this sound complex +- ssi-controller : The phandle of the i.MX SSI controller + +- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) +- mux-ext-port : The external port of the i.MX audio muxer + +Note: The AUDMUX port numbering should start at 1, which is consistent with +hardware manual. + +Example: + +sound { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si476x"; + + ssi-controller = <&ssi1>; + mux-int-port = <2>; + mux-ext-port = <5>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt new file mode 100644 index 000000000000..b3e3c01464bd --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt @@ -0,0 +1,29 @@ +Freescale i.MX audio complex with WM8524 codec + +Required properties: + + - compatible : "fsl,imx-audio-wm8524" + + - model : The user-visible name of this sound complex + + - audio-cpu : The phandle of CPU DAI + + - audio-codec : The phandle of the WM8962 audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names could be power supplies, WM8524 + pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt new file mode 100644 index 000000000000..dd153b5df3f3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt @@ -0,0 +1,68 @@ +Freescale i.MX audio complex with WM8960 codec + +Required properties: + + - compatible : "fsl,imx-audio-wm8960", "fsl,imx7d-evk-wm8960" + + - model : The user-visible name of this sound complex + + - cpu-dai : The phandle of CPU DAI + + - audio-codec : The phandle of the WM8960 audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names could be power supplies, WM8960 + pins, and the jacks on the board: + + Power supplies: + * Mic Bias + + Board connectors: + * Mic Jack + * Headphone Jack + * Ext Spk + +Optional properties: +- hp-det-gpios : The gpio pin to detect plug in/out event that happens to + Headphone jack. +- mic-det-gpios: The gpio pin to detect plug in/out event that happens to + Microphone jack. + +Example: + + sound: sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&gpio1 0 0>; + mic-det-gpios = <&gpio1 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt index acea71bee34f..06bc12d4cc76 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt @@ -6,7 +6,7 @@ Required properties: - model : The user-visible name of this sound complex - - ssi-controller : The phandle of the i.MX SSI controller + - cpu-dai : The phandle of CPU DAI - audio-codec : The phandle of the WM8962 audio codec @@ -31,13 +31,19 @@ Required properties: Note: The AUDMUX port numbering should start at 1, which is consistent with hardware manual. +Optional properties: +- hp-det-gpios : The gpio pin to detect plug in/out event that happens to + Headphone jack. +- mic-det-gpios: The gpio pin to detect plug in/out event that happens to + Microphone jack. + Example: sound { compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -50,4 +56,6 @@ sound { "DMICDAT", "DMIC"; mux-int-port = <2>; mux-ext-port = <3>; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; }; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-xtor.txt b/Documentation/devicetree/bindings/sound/imx-audio-xtor.txt new file mode 100644 index 000000000000..ed55891bca96 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-xtor.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with Freescale DAI transceiver. +Currently supports Freescale SAI or ESAI digital audio interface. + +Required properties: + + - compatible : "fsl,imx-audio-xtor" + + - model : The user-visible name of this sound complex + + - cpu-dai : The phandle of the i.MX DAI, currently supports + SAI or ESAI controller + +Optional properties: + + - asrc-controller : The phandle of the i.MX ASRC controller associated with DAI. + +Examples: + +sound-xtor-sai { + compatible = "fsl,imx-audio-xtor"; + model = "xtor-audio-sai"; + cpu-dai = <&sai0>; + asrc-controller = <&asrc0>; +}; + +sound-xtor-esai { + compatible = "fsl,imx-audio-xtor"; + model = "xtor-audio-esai"; + cpu-dai = <&esai0>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-pdm-mic.txt b/Documentation/devicetree/bindings/sound/imx-pdm-mic.txt new file mode 100644 index 000000000000..bde8313cba7e --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-pdm-mic.txt @@ -0,0 +1,16 @@ +Freescale i.MX audio complex PDM microphone + +Required properties: +- compatible: "fsl,imx-pdm-mic" +- model: The user-visible name of this sound complex +- audio-cpu : The phandle of the i.MX SAI controller +- decimation : The PDM decimation factor <64> + +Example: + +sound-pdm { + compatible = "fsl,imx-pdm-mic"; + model = "imx-pdm-audio"; + audio-cpu = <&sai3>; + decimation = <64>; +}; diff --git a/Documentation/devicetree/bindings/sound/wm8524.txt b/Documentation/devicetree/bindings/sound/wm8524.txt new file mode 100644 index 000000000000..df0f557d41d7 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/wm8524.txt @@ -0,0 +1,16 @@ +WM8524 audio CODEC + +This device does not use I2C or SPI but a simple Hardware Control Interface. + +Required properties: + + - compatible : "wlf,wm8524" + + - wlf,mute-gpios: a GPIO spec for the MUTE pin. + +Example: + +codec: wm8524@0 { + compatible = "wlf,wm8524"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW> +}; diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt index 7f82b59ec8f9..d15b9c82fd15 100644 --- a/Documentation/devicetree/bindings/sound/wm8962.txt +++ b/Documentation/devicetree/bindings/sound/wm8962.txt @@ -13,6 +13,14 @@ Optional properties: of R51 (Class D Control 2) gets set, indicating that the speaker is in mono mode. + - amic-mono: This is a boolean property. If present, indicating that the + analog micphone is hardware mono input, the driver would enable monomix + for it. + + - dmic-mono: This is a boolean property. If present, indicating that the + digital micphone is hardware mono input, the driver would enable monomix + for it. + - mic-cfg : Default register value for R48 (Additional Control 4). If absent, the default should be the register default. diff --git a/Documentation/devicetree/bindings/staging/ion/fsl-heap.txt b/Documentation/devicetree/bindings/staging/ion/fsl-heap.txt new file mode 100644 index 000000000000..427ba5068842 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/ion/fsl-heap.txt @@ -0,0 +1,19 @@ +Freescale ION unmapped heap for i.MX + +Unmapped heap are used for security purpose, providing secure data +path buffers for video decode and display. + +Required properties +- compatible: + - "fsl,display-heap" for display ion heap + - "fsl,vpu-heap" for vpu decoder ion heap + +Required properties for Ion heaps +- memory-region: one reserved mem region pointer. + +Example: + ion-display-region { + compatible = "fsl,display-heap", "linux,ion-heap-unmapped"; + memory-region = <&display_region>; + }; + diff --git a/Documentation/devicetree/bindings/staging/ion/imx-ion-pool.txt b/Documentation/devicetree/bindings/staging/ion/imx-ion-pool.txt new file mode 100644 index 000000000000..31caca806fa1 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/ion/imx-ion-pool.txt @@ -0,0 +1,17 @@ +Freescale reserved memory regions + +iMX reserved memory pool, being merged into cma region + +Required properties +- compatible: "imx-ion-pool" + +Required properties: + - reg: (standard definition) static memory range + + +Example: + vpu_region: imx_ion@2 { + compatible = "imx-ion-pool"; + reg = <0x0 0xe4000000 0 0x02000000>; + }; + diff --git a/Documentation/devicetree/bindings/thermal/imx-sc-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-sc-thermal.txt new file mode 100644 index 000000000000..290e3bc3c4af --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/imx-sc-thermal.txt @@ -0,0 +1,17 @@ +* IMX8QM/QXP SoC Temperature Sensor + +Required properties: +- compatible : +- "nxp,imx8qm-sc-tsens" +- "nxp,imx8qxp-sc-tsens" + +- reg: Address range of the thermal registers +- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. +- tsens-num: the number of temp sensor on this SOC. + +Example: +tsens: thermal-sensor@ { + compatible = "nxp,imx8qm-sc-tsens"; + tsens-num = <5>; + #thermal-sensor-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt new file mode 100644 index 000000000000..4a9d0c5d9ae0 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt @@ -0,0 +1,17 @@ +* Temperature Monitor (TMU) on Freescale i.MX8MM SoCs + +Required properties: +- compatible : "fsl,imx8mm-tmu" +- reg: Address and length of the register +- clocks : thermal sensor's clock source. +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. +Example: + +tmu: tmu@0x30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x0 0x30260000 0x0 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <0>; +}; + diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt new file mode 100644 index 000000000000..b4aa7ddb5b13 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt @@ -0,0 +1,28 @@ +NXP Low Power Timer/Pulse Width Modulation Module (TPM) + +The Timer/PWM Module (TPM) supports input capture, output compare, +and the generation of PWM signals to control electric motor and power +management applications. The counter, compare and capture registers +are clocked by an asynchronous clock that can remain enabled in low +power modes. TPM can support global counter bus where one TPM drives +the counter bus for the others, provided bit width is the same. + +Required properties: + +- compatible : should be "fsl,imx7ulp-tpm" +- reg : Specifies base physical address and size of the register sets + for the clock event device and clock source device. +- interrupts : Should be the clock event device interrupt. +- clocks : The clocks provided by the SoC to drive the timer, must contain + an entry for each entry in clock-names. +- clock-names : Must include the following entries: "igp" and "per". + +Example: +tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; +}; diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt new file mode 100644 index 000000000000..13daee1b053b --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cdns-usb3.txt @@ -0,0 +1,39 @@ +* Cadence USB3 Controller + +Required properties: +- compatible: "Cadence,usb3"; +- reg: base address and length of the registers +- interrupts: interrupt for the USB controller +- interrupt-parent: the interrupt parent for this module +- clocks: reference to the USB clock +- clock-names: the name of clocks +- cdns3,usbphy: reference to the USB PHY + +Optional properties: +- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" +- extcon: extcon phandler for cdns3 device +- power-domains: the power domain for cdns3 controller and phy + +Examples: + +usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_USB3_LPM_CLK>, + <&clk IMX8QM_USB3_BUS_CLK>, + <&clk IMX8QM_USB3_ACLK>, + <&clk IMX8QM_USB3_IPG_CLK>, + <&clk IMX8QM_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index 0e03344e2e8b..1fc8a564efaa 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -10,6 +10,8 @@ Required properties: "fsl,imx6sx-usb" "fsl,imx6ul-usb" "fsl,imx7d-usb" + "fsl,imx7ulp-usb" + "fsl,imx8qm-usb" "lsi,zevio-usb" "qcom,ci-hdrc" "chipidea,usb2" @@ -76,6 +78,7 @@ Optional properties: needs to make sure it does not send more than 90% maximum_periodic_data_per_frame. The use case is multiple transactions, but less frame rate. +- ci-disable-lpm: Some chipidea hardware need to disable low power mode i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one @@ -84,8 +87,23 @@ i.mx specific properties - over-current-active-high: over current signal polarity is high active, typically over current signal polarity is low active. - external-vbus-divider: enables off-chip resistor divider for Vbus +- imx6-usb-charger-detection: enable imx6 usb charger detect function, + only set it when the user wants SoC usb charger detection capabilities. + If the user wants to use charger IC's usb charger detection capabilities, + please do not set it. +- fsl,anatop: phandle for anatop module, anatop module is only existed + at imx6 SoC series. +- pinctrl-names: for names of hsic pin group +- pinctrl-0: hsic "idle" pin group +- pinctrl-1: hsic "active" pin group +- osc-clkgate-delay: the delay between powering up the xtal 24MHz clock + and release the clock to the digital logic inside the analog block, + 0 <= osc-clkgate-delay <= 7. +- power-polarity-active-high: add this property if port power function of ehci + is used to enable vbus, and the vbus power supply chip enable signal is high + active. -Example: +Examples: usb@f7ed0000 { compatible = "chipidea,usb2"; @@ -103,3 +121,21 @@ Example: extcon = <0>, <&usb_id>; phy-clkgate-delay-us = <400>; }; + + usb@02184000 { /* USB OTG */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 0x04>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + disable-over-current; + external-vbus-divider; + imx6-usb-charger-detection; + fsl,anatop = <&anatop>; + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_1>; + pinctrl-1 = <&pinctrl_usbh2_2>; + osc-clkgate-delay = <0x3>; + maximum-speed = "full-speed"; + tpl-support; + }; diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index e3e6983288e3..98a587232d5f 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -53,6 +53,9 @@ Optional properties: - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame length adjustment when the fladj_30mhz_sdbnd signal is invalid or incorrect. +- snps,power-down-scale: Value for number of scale(16kHz) of suspend clock if + the default value is not correct, valid range is 2~8000, means suspend + clock is from 32KHz to 125MHz. - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. diff --git a/Documentation/devicetree/bindings/usb/typec-tcpci.txt b/Documentation/devicetree/bindings/usb/typec-tcpci.txt new file mode 100644 index 000000000000..7ef2167ba767 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/typec-tcpci.txt @@ -0,0 +1,40 @@ +TCPCI(Typec port cotroller interface) binding +--------------------------------------------- + +Required properties: +- compatible: should be "usb,tcpci". +- reg: the i2c slave address of typec port controller device. +- interrupt-parent: the phandle to the interrupt controller which provides + the interrupt. +- interrupts: interrupt specification for tcpci alert. +- port-type: typec port type. +- default-role: preferred power role if port type is "drp". + +Required properties only for power source or drp: +- src-pdos + +Required properties only for power sink or drp: +- snk-pdos +- max-snk-mv +- max-snk-ma +- op-snk-mw + +Optional properties: +- sink-disable: disable vbus sink in sink role in case we only can be source + for power but need dual data role. + +Example: + +ptn5110@50 { + compatible = "usb,tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + port-type = "drp"; + default-role = "sink"; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <1000>; + op-snk-mw = <9000>; +}; diff --git a/Documentation/devicetree/bindings/usb/typec.txt b/Documentation/devicetree/bindings/usb/typec.txt new file mode 100644 index 000000000000..f1339dce5978 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/typec.txt @@ -0,0 +1,50 @@ +Generic typec and power delivery properties +------------------------------------------- + +Required properties: +- port-type: should be one of "drp", "dfp" or "ufp". +- default-role: preferred power role if drp, should be "sink" or "source". +- src-pdos: An array of u32 with each entry providing supported power + source data object(PDO), the detailed bit definitions of + PDO can be found in "Universal Serial Bus Power Delivery + Specification" chapter 6.4.1.2 Source_Capabilities Message, + the order of each entry(PDO) should follow the PD spec chapter + 6.4.1. Required only for power source and power dual role with + power delivery support. +- snk-pdos: An array of u32 with each entry providing supported power + sink data object(PDO), the detailed bit definitions of PDO + can be found in "Universal Serial Bus Power Delivery + Specification" chapter 6.4.1.3 Sink Capabilities Message, + the order of each entry(PDO) should follow the PD spec chapter + 6.4.1. Required only for power sink and power dual role with + power delivery support. +- max-snk-mv: The max voltage the sink can support in millivoltage, required + only for power sink and power dual role with power delivery + support. +- max-snk-ma: The max current the sink can support in milliampere, required + only for power sink and power dual role with power delivery + support. +- op-snk-mw: Sink required operating power in milliwatts, if source offered + power is less then it, Capability Mismatch is set, required + only for power sink and power dual role with power delivery + support. +- max-snk-mw: The max power the sink can support in milliwatts, required + for power sink and power dual role with power delivery support, + power sink needs this property to get the max current based on + the selected PDO. + +Example: + +ptn5110@50 { + compatible = "usb,tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + port-type = "drp"; + default-role = "sink"; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <1000>; + op-snk-mw = <9000>; +}; diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index 7790c819859a..56b010001e50 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -27,6 +27,8 @@ Optional properties: - clocks: reference to a clock - usb3-lpm-capable: determines if platform is USB3 LPM capable - quirk-broken-port-ped: set if the controller has broken port disable mechanism + - usb3-resume-missing-cas: set if the CAS(Cold Attach Status) may lose in case + device plugged in while system sleep. Example: usb@f0931000 { diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt index f1e27faf528e..fe37ac11e873 100644 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt @@ -7,6 +7,8 @@ Required properties: "fsl,vf610-usbmisc" for Vybrid vf610 "fsl,imx6sx-usbmisc" for imx6sx "fsl,imx7d-usbmisc" for imx7d + "fsl,imx6ul-usbmisc" for imx6ul + "fsl,imx7ulp-usbmisc" for imx7ulp - reg: Should contain registers location and length Examples: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index bceffffb7502..66e19acd021b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -144,6 +144,7 @@ iom Iomega Corporation isee ISEE 2007 S.L. isil Intersil issi Integrated Silicon Solutions Inc. +ite ITE Tech. Inc. jdi Japan Display Inc. jedec JEDEC Solid State Technology Association karo Ka-Ro electronics GmbH @@ -156,6 +157,7 @@ lacie LaCie lantiq Lantiq Semiconductor lenovo Lenovo Group Ltd. lg LG Corporation +linaro Linaro Limited linux Linux-specific binding lltc Linear Technology Corporation lsi LSI Corp. (LSI Logic) @@ -172,6 +174,7 @@ microcrystal Micro Crystal AG micron Micron Technology Inc. minix MINIX Technology Ltd. mitsubishi Mitsubishi Electric Corporation +mixel Mixel, Inc. mosaixtech Mosaix Technologies, Inc. moxa Moxa mpl MPL AG @@ -192,6 +195,7 @@ nintendo Nintendo nokia Nokia nuvoton Nuvoton Technology Corporation nvidia NVIDIA +nwl Northwest Logic nxp NXP Semiconductors okaya Okaya Electric America, Inc. olimex OLIMEX Ltd. diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt index 107280ef0025..10771fbf9c63 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt @@ -5,6 +5,9 @@ Required properties: - reg : Should contain WDT registers location and length - interrupts : Should contain WDT interrupt +For imx8-wdt, it's a software watchdog which implemented by timer tick +in SCFW. In this case, only compatible name required. + Optional properties: - big-endian: If present the watchdog device's registers are implemented in big endian mode, otherwise in native mode(same with CPU), for more diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst index bb4254d19cbb..2059b608a0ac 100644 --- a/Documentation/gpu/drm-kms-helpers.rst +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -214,6 +214,18 @@ EDID Helper Functions Reference .. kernel-doc:: drivers/gpu/drm/drm_edid.c :export: +SCDC Helper Functions Reference +=============================== + +.. kernel-doc:: drivers/gpu/drm/drm_scdc_helper.c + :doc: scdc helpers + +.. kernel-doc:: include/drm/drm_scdc_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_scdc_helper.c + :export: + Rectangle Utilities Reference ============================= diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 81c7f2bb7daf..002331b0b48a 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -308,6 +308,7 @@ Code Seq#(hex) Include File Comments 0xA3 80-8F Port ACL in development: <mailto:tlewis@mindspring.com> 0xA3 90-9F linux/dtlk.h +0xA4 00-1F uapi/linux/tee.h Generic TEE subsystem 0xAA 00-3F linux/uapi/linux/userfaultfd.h 0xAB 00-1F linux/nbd.h 0xAC 00-1F linux/raw.h @@ -321,6 +322,7 @@ Code Seq#(hex) Include File Comments 0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca> 0xB3 00 linux/mmc/ioctl.h 0xB4 00-0F linux/gpio.h <mailto:linux-gpio@vger.kernel.org> +0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc@vger.kernel.org> 0xC0 00-0F linux/usb/iowarrior.h 0xCA 00-0F uapi/misc/cxl.h 0xCA 80-8F uapi/scsi/cxlflash_ioctl.h diff --git a/Documentation/mmc/mmc-dev-attrs.txt b/Documentation/mmc/mmc-dev-attrs.txt index 404a0e9e92b0..dcd1252877fb 100644 --- a/Documentation/mmc/mmc-dev-attrs.txt +++ b/Documentation/mmc/mmc-dev-attrs.txt @@ -30,6 +30,7 @@ All attributes are read-only. rel_sectors Reliable write sector count ocr Operation Conditions Register dsr Driver Stage Register + cmdq_en Command Queue enabled: 1 => enabled, 0 => not enabled Note on Erase Size and Preferred Erase Size: diff --git a/Documentation/tee.txt b/Documentation/tee.txt new file mode 100644 index 000000000000..718599357596 --- /dev/null +++ b/Documentation/tee.txt @@ -0,0 +1,118 @@ +TEE subsystem +This document describes the TEE subsystem in Linux. + +A TEE (Trusted Execution Environment) is a trusted OS running in some +secure environment, for example, TrustZone on ARM CPUs, or a separate +secure co-processor etc. A TEE driver handles the details needed to +communicate with the TEE. + +This subsystem deals with: + +- Registration of TEE drivers + +- Managing shared memory between Linux and the TEE + +- Providing a generic API to the TEE + +The TEE interface +================= + +include/uapi/linux/tee.h defines the generic interface to a TEE. + +User space (the client) connects to the driver by opening /dev/tee[0-9]* or +/dev/teepriv[0-9]*. + +- TEE_IOC_SHM_ALLOC allocates shared memory and returns a file descriptor + which user space can mmap. When user space doesn't need the file + descriptor any more, it should be closed. When shared memory isn't needed + any longer it should be unmapped with munmap() to allow the reuse of + memory. + +- TEE_IOC_VERSION lets user space know which TEE this driver handles and + the its capabilities. + +- TEE_IOC_OPEN_SESSION opens a new session to a Trusted Application. + +- TEE_IOC_INVOKE invokes a function in a Trusted Application. + +- TEE_IOC_CANCEL may cancel an ongoing TEE_IOC_OPEN_SESSION or TEE_IOC_INVOKE. + +- TEE_IOC_CLOSE_SESSION closes a session to a Trusted Application. + +There are two classes of clients, normal clients and supplicants. The latter is +a helper process for the TEE to access resources in Linux, for example file +system access. A normal client opens /dev/tee[0-9]* and a supplicant opens +/dev/teepriv[0-9]. + +Much of the communication between clients and the TEE is opaque to the +driver. The main job for the driver is to receive requests from the +clients, forward them to the TEE and send back the results. In the case of +supplicants the communication goes in the other direction, the TEE sends +requests to the supplicant which then sends back the result. + +OP-TEE driver +============= + +The OP-TEE driver handles OP-TEE [1] based TEEs. Currently it is only the ARM +TrustZone based OP-TEE solution that is supported. + +Lowest level of communication with OP-TEE builds on ARM SMC Calling +Convention (SMCCC) [2], which is the foundation for OP-TEE's SMC interface +[3] used internally by the driver. Stacked on top of that is OP-TEE Message +Protocol [4]. + +OP-TEE SMC interface provides the basic functions required by SMCCC and some +additional functions specific for OP-TEE. The most interesting functions are: + +- OPTEE_SMC_FUNCID_CALLS_UID (part of SMCCC) returns the version information + which is then returned by TEE_IOC_VERSION + +- OPTEE_SMC_CALL_GET_OS_UUID returns the particular OP-TEE implementation, used + to tell, for instance, a TrustZone OP-TEE apart from an OP-TEE running on a + separate secure co-processor. + +- OPTEE_SMC_CALL_WITH_ARG drives the OP-TEE message protocol + +- OPTEE_SMC_GET_SHM_CONFIG lets the driver and OP-TEE agree on which memory + range to used for shared memory between Linux and OP-TEE. + +The GlobalPlatform TEE Client API [5] is implemented on top of the generic +TEE API. + +Picture of the relationship between the different components in the +OP-TEE architecture. + + User space Kernel Secure world + ~~~~~~~~~~ ~~~~~~ ~~~~~~~~~~~~ + +--------+ +-------------+ + | Client | | Trusted | + +--------+ | Application | + /\ +-------------+ + || +----------+ /\ + || |tee- | || + || |supplicant| \/ + || +----------+ +-------------+ + \/ /\ | TEE Internal| + +-------+ || | API | + + TEE | || +--------+--------+ +-------------+ + | Client| || | TEE | OP-TEE | | OP-TEE | + | API | \/ | subsys | driver | | Trusted OS | + +-------+----------------+----+-------+----+-----------+-------------+ + | Generic TEE API | | OP-TEE MSG | + | IOCTL (TEE_IOC_*) | | SMCCC (OPTEE_SMC_CALL_*) | + +-----------------------------+ +------------------------------+ + +RPC (Remote Procedure Call) are requests from secure world to kernel driver +or tee-supplicant. An RPC is identified by a special range of SMCCC return +values from OPTEE_SMC_CALL_WITH_ARG. RPC messages which are intended for the +kernel are handled by the kernel driver. Other RPC messages will be forwarded to +tee-supplicant without further involvement of the driver, except switching +shared memory buffer representation. + +References: +[1] https://github.com/OP-TEE/optee_os +[2] http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html +[3] drivers/tee/optee/optee_smc.h +[4] drivers/tee/optee/optee_msg.h +[5] http://www.globalplatform.org/specificationsdevice.asp look for + "TEE Client API Specification v1.0" and click download. diff --git a/Documentation/usb/chipidea.txt b/Documentation/usb/chipidea.txt index edf7cdfddc88..2b0c435f4cc9 100644 --- a/Documentation/usb/chipidea.txt +++ b/Documentation/usb/chipidea.txt @@ -32,7 +32,10 @@ cat /sys/kernel/debug/ci_hdrc.0/registers B-device should take host role and enumrate A-device. 4) A-device switch back to host. - On B-device: + On A-device: + echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req + + or, on B-device: echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req or, by introducing HNP polling, B-Host can know when A-peripheral wish @@ -74,6 +77,14 @@ cat /sys/kernel/debug/ci_hdrc.0/registers "On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification July 27, 2012 Revision 2.0 version 1.1a" +1.4 OTG compliance test +---------------------- +Only below 3 popular gadget drivers are declared to be USB OTG and EH 2.0 +compliant(with otg descriptor comply with USB OTG and EH 2.0 as a peripheral): +- mass storage +- ether +- serial + 2. How to enable USB as system wakeup source ----------------------------------- Below is the example for how to enable USB as system wakeup source diff --git a/Documentation/usb/typec.rst b/Documentation/usb/typec.rst new file mode 100644 index 000000000000..b67a46779de9 --- /dev/null +++ b/Documentation/usb/typec.rst @@ -0,0 +1,184 @@ + +USB Type-C connector class +========================== + +Introduction +------------ + +The typec class is meant for describing the USB Type-C ports in a system to the +user space in unified fashion. The class is designed to provide nothing else +except the user space interface implementation in hope that it can be utilized +on as many platforms as possible. + +The platforms are expected to register every USB Type-C port they have with the +class. In a normal case the registration will be done by a USB Type-C or PD PHY +driver, but it may be a driver for firmware interface such as UCSI, driver for +USB PD controller or even driver for Thunderbolt3 controller. This document +considers the component registering the USB Type-C ports with the class as "port +driver". + +On top of showing the capabilities, the class also offer user space control over +the roles and alternate modes of ports, partners and cable plugs when the port +driver is capable of supporting those features. + +The class provides an API for the port drivers described in this document. The +attributes are described in Documentation/ABI/testing/sysfs-class-typec. + +User space interface +-------------------- +Every port will be presented as its own device under /sys/class/typec/. The +first port will be named "port0", the second "port1" and so on. + +When connected, the partner will be presented also as its own device under +/sys/class/typec/. The parent of the partner device will always be the port it +is attached to. The partner attached to port "port0" will be named +"port0-partner". Full path to the device would be +/sys/class/typec/port0/port0-partner/. + +The cable and the two plugs on it may also be optionally presented as their own +devices under /sys/class/typec/. The cable attached to the port "port0" port +will be named port0-cable and the plug on the SOP Prime end (see USB Power +Delivery Specification ch. 2.4) will be named "port0-plug0" and on the SOP +Double Prime end "port0-plug1". The parent of a cable will always be the port, +and the parent of the cable plugs will always be the cable. + +If the port, partner or cable plug supports Alternate Modes, every supported +Alternate Mode SVID will have their own device describing them. Note that the +Alternate Mode devices will not be attached to the typec class. The parent of an +alternate mode will be the device that supports it, so for example an alternate +mode of port0-partner will be presented under /sys/class/typec/port0-partner/. +Every mode that is supported will have its own group under the Alternate Mode +device named "mode<index>", for example /sys/class/typec/port0/<alternate +mode>/mode1/. The requests for entering/exiting a mode can be done with "active" +attribute file in that group. + +Driver API +---------- + +Registering the ports +~~~~~~~~~~~~~~~~~~~~~ + +The port drivers will describe every Type-C port they control with struct +typec_capability data structure, and register them with the following API: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_register_port typec_unregister_port + +When registering the ports, the prefer_role member in struct typec_capability +deserves special notice. If the port that is being registered does not have +initial role preference, which means the port does not execute Try.SNK or +Try.SRC by default, the member must have value TYPEC_NO_PREFERRED_ROLE. +Otherwise if the port executes Try.SNK by default, the member must have value +TYPEC_DEVICE, and with Try.SRC the value must be TYPEC_HOST. + +Registering Partners +~~~~~~~~~~~~~~~~~~~~ + +After successful connection of a partner, the port driver needs to register the +partner with the class. Details about the partner need to be described in struct +typec_partner_desc. The class copies the details of the partner during +registration. The class offers the following API for registering/unregistering +partners. + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_register_partner typec_unregister_partner + +The class will provide a handle to struct typec_partner if the registration was +successful, or NULL. + +If the partner is USB Power Delivery capable, and the port driver is able to +show the result of Discover Identity command, the partner descriptor structure +should include handle to struct usb_pd_identity instance. The class will then +create a sysfs directory for the identity under the partner device. The result +of Discover Identity command can then be reported with the following API: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_partner_set_identity + +Registering Cables +~~~~~~~~~~~~~~~~~~ + +After successful connection of a cable that supports USB Power Delivery +Structured VDM "Discover Identity", the port driver needs to register the cable +and one or two plugs, depending if there is CC Double Prime controller present +in the cable or not. So a cable capable of SOP Prime communication, but not SOP +Double Prime communication, should only have one plug registered. For more +information about SOP communication, please read chapter about it from the +latest USB Power Delivery specification. + +The plugs are represented as their own devices. The cable is registered first, +followed by registration of the cable plugs. The cable will be the parent device +for the plugs. Details about the cable need to be described in struct +typec_cable_desc and about a plug in struct typec_plug_desc. The class copies +the details during registration. The class offers the following API for +registering/unregistering cables and their plugs: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_register_cable typec_unregister_cable typec_register_plug + typec_unregister_plug + +The class will provide a handle to struct typec_cable and struct typec_plug if +the registration is successful, or NULL if it isn't. + +If the cable is USB Power Delivery capable, and the port driver is able to show +the result of Discover Identity command, the cable descriptor structure should +include handle to struct usb_pd_identity instance. The class will then create a +sysfs directory for the identity under the cable device. The result of Discover +Identity command can then be reported with the following API: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_cable_set_identity + +Notifications +~~~~~~~~~~~~~ + +When the partner has executed a role change, or when the default roles change +during connection of a partner or cable, the port driver must use the following +APIs to report it to the class: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_set_data_role typec_set_pwr_role typec_set_vconn_role + typec_set_pwr_opmode + +Alternate Modes +~~~~~~~~~~~~~~~ + +USB Type-C ports, partners and cable plugs may support Alternate Modes. Each +Alternate Mode will have identifier called SVID, which is either a Standard ID +given by USB-IF or vendor ID, and each supported SVID can have 1 - 6 modes. The +class provides struct typec_mode_desc for describing individual mode of a SVID, +and struct typec_altmode_desc which is a container for all the supported modes. + +Ports that support Alternate Modes need to register each SVID they support with +the following API: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_port_register_altmode + +If a partner or cable plug provides a list of SVIDs as response to USB Power +Delivery Structured VDM Discover SVIDs message, each SVID needs to be +registered. + +API for the partners: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_partner_register_altmode + +API for the Cable Plugs: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_plug_register_altmode + +So ports, partners and cable plugs will register the alternate modes with their +own functions, but the registration will always return a handle to struct +typec_altmode on success, or NULL. The unregistration will happen with the same +function: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_unregister_altmode + +If a partner or cable plug enters or exits a mode, the port driver needs to +notify the class with the following API: + +.. kernel-doc:: drivers/usb/typec/typec.c + :functions: typec_altmode_update_active |