diff options
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 193 |
1 files changed, 184 insertions, 9 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 827196339893..b85246ee78da 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -49,10 +49,6 @@ config GENERIC_CLOCKEVENTS_BROADCAST depends on GENERIC_CLOCKEVENTS default y if SMP && !LOCAL_TIMERS -config MMU - bool - default y - config NO_IOPORT bool default n @@ -194,6 +190,13 @@ source "kernel/Kconfig.freezer" menu "System Type" +config MMU + bool "MMU-based Paged Memory Management Support" + default y + help + Select if you want MMU-based virtualised addressing space + support by paged memory management. If unsure, say 'Y'. + choice prompt "ARM system type" default ARCH_VERSATILE @@ -590,6 +593,19 @@ config ARCH_W90X900 Support for Nuvoton (Winbond logic dept.) ARM9 processor,You can login www.mcuos.com or www.nuvoton.com to know more. +config ARCH_MPS + bool "ARM Ltd. Microcontroller Prototyping System" + depends on !MMU + select ARM_AMBA + select HAVE_CLK + select COMMON_CLKDEV + select ICST307 + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + This enables support for ARM Ltd. Microcontroller Prototyping + System platform. + endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -676,6 +692,8 @@ source "arch/arm/mach-msm/Kconfig" source "arch/arm/mach-w90x900/Kconfig" +source "arch/arm/mach-mps/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -706,6 +724,105 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_364296 + bool "Enable partial low interrupt latency mode for ARM1136" + depends on CPU_V6 && !SMP + default n + help + This options enables the workaround for the 364296 ARM1136 + r0pX errata (possible cache data corruption with + hit-under-miss enabled). It sets the undocumented bit 31 in + the auxiliary control register and the FI bit in the control + register, thus disabling hit-under-miss without putting the + processor into full low interrupt latency mode. ARM11MPCore + is not affected. + +config ARM_ERRATA_411920 + bool "Workaround for the global I cache invalidation on ARM1136" + depends on CPU_V6 && !SMP + default n + help + Invalidation of the Instruction Cache operation can + fail. This Erratum is present in 1136, 1156 and 1176. It + does not affect the MPCore. This option enables the ARM Ltd. + recommended workaround. + +config ARM_ERRATA_351422 + bool "Spinlocks using LDREX and STREX instructions can livelock" + depends on CPU_V6 && SMP + default n + help + According to the ARM11MPCore Erratum 351422 (r0p0), under + extremely rare conditions, in an MPCore node consisting of + at least 3 CPUs, two CPUs trying to perform a STREX to data + on the same shared cache line can enter a livelock + situation. This option adds variable spinning time to the + locking routines. + +config ARM_ERRATA_430973 + bool "Stale prediction on replaced interworking branch on Cortex-A8" + depends on CPU_V7 + default n + help + This option enables the workaround for the 430973 Cortex-A8 + (r1p0) erratum. If a code sequence containing an ARM/Thumb + interworking branch is replaced with another code sequence + at the same virtual address, whether due to self-modifying + code or virtual to physical address re-mapping, Cortex-A8 + does not recover from the stale interworking branch + prediction. This results in Cortex-A8 executing the new code + sequence in the incorrect ARM or Thumb state. + +config ARM_ERRATA_458693 + bool "Processor deadlock when a false hazard is created on Cortex-A8" + depends on CPU_V7 + default n + help + This option enables the workaround for the 458693 Cortex-A8 + (r2p0) erratum. For very specific sequences of memory + operations, it is possible for a hazard condition intended + for a cache line to instead be incorrectly associated with a + different cache line. This false hazard might then cause a + processor deadlock. + +config ARM_ERRATA_460075 + bool "Data written to the L2 cache can be overwritten with stale data on Cortex-A8" + depends on CPU_V7 + default n + help + This option enables the workaround for the 458692 Cortex-A8 + (r2p0) erratum. Any asynchronous access to the L2 cache may + encounter a situation in which recent store transactions to + the L2 cache are lost and overwritten with stale memory + contents from external memory. + +config ARM_ERRATUM_451034 + bool "Enable workaround for ARM erratum 451034" + depends on VFPv3 + help + On Cortex-A8 r1p0 and r1p1, executing a NEON store with an integer + store in the store buffer, can cause a processor deadlock under + certain conditions. + + See ARM Cortex-A8 Errata Notice (PR120-PRDC-008070) for full details. + + Say Y to include a partial workaround. + + WARNING: Even with this option enabled, userspace code can trigger + the deadlock. To safely run untrusted code, a different fix is + required. + +config ARM_ERRATA_484863 + bool "The Cache Sync operation does not guarantee that the the Eviction Buffer is empty" + depends on CACHE_L2X0 + default n + help + According to the L220 Erratum 484863, the actual behaviour of + the L220 cache controller is that the Cache Sync operation + only ensures that the Write Buffer and the Write Allocate + Buffer are empty but not the Eviction Buffer. This option + enables the first workaround from the Errata document. + endmenu source "arch/arm/common/Kconfig" @@ -773,7 +890,7 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) + depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX) select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have @@ -830,7 +947,7 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP) + depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP || MACH_REALVIEW_PBX) default y help Enable support for local timers on SMP platforms, rather then the @@ -859,6 +976,23 @@ config HZ default AT91_TIMER_HZ if ARCH_AT91 default 100 +config THUMB2_KERNEL + bool "Compile the kernel in Thumb-2 mode" + depends on (CPU_V7 || CPU_V7M) && EXPERIMENTAL + default n + select AEABI + select ARM_ASM_UNIFIED + help + By enabling this option, the kernel will be compiled in + Thumb-2 mode. A compiler/assembler that understand the unified + ARM-Thumb syntax is needed. + + If unsure, say N. + +config ARM_ASM_UNIFIED + bool + default n + config AEABI bool "Use the ARM EABI to compile the kernel" help @@ -876,7 +1010,7 @@ config AEABI config OABI_COMPAT bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" - depends on AEABI && EXPERIMENTAL + depends on AEABI && !CPU_V7M && EXPERIMENTAL default y help This option preserves the old syscall interface along with the @@ -925,7 +1059,7 @@ config LEDS ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_AT91 || ARCH_DAVINCI || \ - ARCH_KS8695 || MACH_RD88F5182 + ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. @@ -1082,11 +1216,43 @@ config ATAGS_PROC Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec. +config NAKED_BOOT + bool "Kernel image for naked booting environments" + depends on CMDLINE != "" + default n + help + This produces a kernel binary that can simply be moved onto + the target machine and jumped to without any sort of boot + protocol from the bootloader. This should only be used in + cases where the bootloader fails to implement the required + calling convention for executing the kernel as described in + the file Documentation/arm/Booting. + + The use of this option imposes many restrictions on the kernel + as it may not support more than one target machine, and all + boot parameters such as memory size and root filesystem device + have to be hardcoded in the default kernel command string (see + CONFIG_CMDLINE). + + If dynamic ram configuration, multi-machine support or the + ability for the user to specify a kernel command string at + boot without the need for recompiling the kernel each time + is required, then the bootloader must implement the boot + protocol as described in Documentation/arm/Booting and this + config option not be used. + + Please consider fixing your bootloader according to the + documented boot protocol in all cases, or choose one + from the many excellent open source bootloaders available + on the net which already support the required boot protocol. + + If you're not sure what this is all about then say N. + endmenu menu "CPU Power Management" -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || ARCH_REALVIEW) source "drivers/cpufreq/Kconfig" @@ -1126,6 +1292,15 @@ config CPU_FREQ_PXA default y select CPU_FREQ_DEFAULT_GOV_USERSPACE +config CPU_FREQ_REALVIEW + tristate "CPUfreq driver for ARM RealView platform" + depends on CPU_FREQ && MACH_REALVIEW_PB1176 + default y + help + This enables the CPUfreq driver for ARM RealView platform. + + If in doubt, say Y. + endif source "drivers/cpuidle/Kconfig" |