diff options
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 17921468d1c7..3ee1818540e7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1243,7 +1243,7 @@ config ARM_ERRATA_742231 capabilities of the processor. config PL310_ERRATA_588369 - bool "Clean & Invalidate maintenance operations do not invalidate clean lines" + bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" depends on CACHE_L2X0 help The PL310 L2 cache controller implements three types of Clean & @@ -1268,7 +1268,7 @@ config ARM_ERRATA_720789 entries regardless of the ASID. config PL310_ERRATA_727915 - bool "Background Clean & Invalidate by Way operation can cause data corruption" + bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" depends on CACHE_L2X0 help PL310 implements the Clean & Invalidate by Way L2 cache maintenance @@ -1301,8 +1301,8 @@ config ARM_ERRATA_751472 operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. -config ARM_ERRATA_753970 - bool "ARM errata: cache sync operation may be faulty" +config PL310_ERRATA_753970 + bool "PL310 errata: cache sync operation may be faulty" depends on CACHE_PL310 help This option enables the workaround for the 753970 PL310 (r3p0) erratum. @@ -1364,6 +1364,18 @@ config ARM_ERRATA_764369 relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. +config PL310_ERRATA_769419 + bool "PL310 errata: no automatic Store Buffer drain" + depends on CACHE_L2X0 + help + On revisions of the PL310 prior to r3p2, the Store Buffer does + not automatically drain. This can cause normal, non-cacheable + writes to be retained when the memory system is idle, leading + to suboptimal I/O performance for drivers using coherent DMA. + This option adds a write barrier to the cpu_idle loop so that, + on systems with an outer cache, the store buffer is drained + explicitly. + endmenu source "arch/arm/common/Kconfig" @@ -1977,7 +1989,7 @@ endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" - depends on !ZBOOT_ROM + depends on !ZBOOT_ROM && !ARM_LPAE help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM @@ -2007,7 +2019,7 @@ config XIP_PHYS_ADDR config KEXEC bool "Kexec system call (EXPERIMENTAL)" - depends on EXPERIMENTAL + depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot |