diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 212 |
1 files changed, 1 insertions, 211 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 40c88fa69b53..2e9879f2b65f 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -646,7 +646,7 @@ #size-cells = <1>; ranges = <0 0x020cc000 0x4000>; - snvs_rtc: snvs-rtc-lp@34 { + snvs-rtc-lp@34 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; reg = <0x34 0x58>; interrupts = <0 19 0x04 0 20 0x04>; @@ -1069,24 +1069,6 @@ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 >; }; - - pinctrl_audmux_4: audmux-4 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_audmux_5: audmux-5 { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 - >; - }; }; ecspi1 { @@ -1111,23 +1093,6 @@ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 >; }; - pinctrl_ecspi1_3: ecspi1grp-3 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 - >; - }; - }; - - ecspi2 { - pinctrl_ecspi2_1: ecspi2grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - >; - }; }; ecspi3 { @@ -1140,16 +1105,6 @@ }; }; - ecspi4 { - pinctrl_ecspi4_1: ecspi4grp-1 { - fsl,pins = < - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - >; - }; - }; - enet { pinctrl_enet_1: enetgrp-1 { fsl,pins = < @@ -1234,21 +1189,6 @@ >; }; - /* RMII */ - pinctrl_enet_5: enetgrp-5 { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) - >; - }; }; esai { @@ -1296,12 +1236,6 @@ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 >; }; - pinctrl_flexcan1_3: flexcan1grp-3 { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 - >; - }; }; flexcan2 { @@ -1552,65 +1486,6 @@ >; }; - pinctrl_ipu1_5: ipu1grp-5 { - fsl,pins = < - MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 - MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 /* DE */ - MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 /* HSync */ - MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 /* VSync */ - MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 - MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 - MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 - MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 - MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 - MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 - MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 - MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 - MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 - MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 - MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 - MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 - MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 - MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 - MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 - MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 - MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 - MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 - MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 - MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 - MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 - MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 - MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 - MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 - >; - }; - - pinctrl_ipu1_6: ipu1grp-6 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - >; - }; }; mlb { @@ -1706,12 +1581,6 @@ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 >; }; - - pinctrl_spdif_3: spdifgrp-3 { - fsl,pins = < - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; }; uart1 { @@ -1728,23 +1597,6 @@ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 >; }; - - pinctrl_uart1_3: uart1grp-3 { /* DTE mode */ - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart1_4: uart1grp-4 { /* Additional DTR, DSR, DCD */ - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; }; uart2 { @@ -1763,31 +1615,6 @@ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 >; }; - - pinctrl_uart2_3: uart2grp-3 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2_4: uart2grp-4 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2_5: uart2grp-5 { /* DTE mode */ - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 - >; - }; }; uart3 { @@ -1799,7 +1626,6 @@ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; }; - pinctrl_uart3_2: uart3grp-2 { fsl,pins = < MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 @@ -1808,19 +1634,6 @@ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 >; }; - - pinctrl_uart3_3: uart3grp-3 { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 - >; - }; - pinctrl_uart3_4: uart3grp-4 { /* DTE mode */ - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 - >; - }; }; uart4 { @@ -1832,15 +1645,6 @@ }; }; - uart5 { - pinctrl_uart5_1: uart5grp-1 { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - }; - usbotg { pinctrl_usbotg_1: usbotggrp-1 { fsl,pins = < @@ -1896,20 +1700,6 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 >; }; - pinctrl_usdhc1_2: usdhc1grp-2 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 - >; - }; }; usdhc2 { |