diff options
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 24 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 111 |
2 files changed, 135 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 580631278e79..af7e6cdf60bb 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -240,5 +240,29 @@ MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 >; }; + pinctrl_ipu2_2: ipu2grp-2 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xD1 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xD1 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xD1 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xF9 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xF9 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xF9 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xF9 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xF9 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xF9 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xF9 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xF9 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xF9 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xF9 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xF9 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xF9 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xF9 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xF9 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xF9 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xF9 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2e9879f2b65f..81466bcee415 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1069,6 +1069,14 @@ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 >; }; + pinctrl_audmux_4: audmux-4 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; }; ecspi1 { @@ -1093,6 +1101,23 @@ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 >; }; + pinctrl_ecspi1_3: ecspi1grp-3 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 + >; + }; + }; + + ecspi2 { + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + >; + }; }; ecspi3 { @@ -1236,6 +1261,12 @@ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 >; }; + pinctrl_flexcan1_3: flexcan1grp-3 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 + >; + }; }; flexcan2 { @@ -1486,6 +1517,38 @@ >; }; + pinctrl_ipu1_5: ipu1grp-5 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 /* DE */ + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 /* HSync */ + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 /* VSync */ + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 + >; + }; }; mlb { @@ -1597,6 +1660,15 @@ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 >; }; + + pinctrl_uart1_3: uart1grp-3 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; }; uart2 { @@ -1615,6 +1687,31 @@ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 >; }; + + pinctrl_uart2_3: uart2grp-3 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2_4: uart2grp-4 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_5: uart2grp-5 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; }; uart3 { @@ -1700,6 +1797,20 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 >; }; + pinctrl_usdhc1_2: usdhc1grp-2 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 + >; + }; }; usdhc2 { |