diff options
Diffstat (limited to 'arch/arm/mach-mx37')
| -rw-r--r-- | arch/arm/mach-mx37/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mx37/bus_freq.c | 149 | ||||
| -rw-r--r-- | arch/arm/mach-mx37/clock.c | 32 | ||||
| -rw-r--r-- | arch/arm/mach-mx37/lpmodes.c | 408 | ||||
| -rw-r--r-- | arch/arm/mach-mx37/mx37_3stack.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-mx37/system.c | 22 |
6 files changed, 70 insertions, 561 deletions
diff --git a/arch/arm/mach-mx37/Makefile b/arch/arm/mach-mx37/Makefile index 2b3eeadfc495..35cf4806b685 100644 --- a/arch/arm/mach-mx37/Makefile +++ b/arch/arm/mach-mx37/Makefile @@ -4,7 +4,7 @@ # Object file lists. -obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o lpmodes.o dptc.o bus_freq.o +obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o dptc.o bus_freq.o obj-$(CONFIG_MACH_MX37_3DS) += mx37_3stack.o mx37_3stack_gpio.o diff --git a/arch/arm/mach-mx37/bus_freq.c b/arch/arm/mach-mx37/bus_freq.c index 6af034605451..d6cde4a21487 100644 --- a/arch/arm/mach-mx37/bus_freq.c +++ b/arch/arm/mach-mx37/bus_freq.c @@ -39,6 +39,7 @@ #define LP_LPM_VOLTAGE 1050000 #define LP_LOWFREQ_VOLTAGE 1050000 #define LP_NORMAL_VOLTAGE 1200000 +#define GP_LPAPM_FREQ 200000000 DEFINE_SPINLOCK(bus_freq_lock); @@ -69,70 +70,47 @@ char *gp_reg_id = "SW1"; char *lp_reg_id = "SW2"; static struct cpu_wp *cpu_wp_tbl; -struct dvfs_wp dvfs_core_setpoint[] = {{33, 7, 33, 10, 10, 0x10}, - {22, 0, 33, 10, 10, 0x10},}; +struct dvfs_wp dvfs_core_setpoint[] = { + {33, 8, 33, 10, 10, 0x08}, + {26, 0, 33, 20, 10, 0x08}, + {28, 8, 33, 20, 30, 0x08}, + {26, 0, 33, 20, 10, 0x08},}; int set_low_bus_freq(void) { int ret = 0; - unsigned long lp_lpm_clk; unsigned long flags; + int reg; + unsigned long lp_lpm_clk; - struct clk *p_clk; - struct clk *amode_parent_clk; - - if (low_bus_freq_mode) - return ret; - - if (clk_get_rate(cpu_clk) != 200000000) - return; - - clk_disable(uart_clk); - - lp_lpm_clk = clk_get_rate(lp_apm); - amode_parent_clk = lp_apm; - p_clk = clk_get_parent(periph_apm_clk); spin_lock_irqsave(&bus_freq_lock, flags); - /* Make sure osc_clk is the parent of lp_apm. */ - if (clk_get_parent(amode_parent_clk) != osc) - clk_set_parent(amode_parent_clk, osc); - - /* Set the parent of periph_apm_clk to be lp_apm */ - clk_set_parent(periph_apm_clk, amode_parent_clk); - amode_parent_clk = periph_apm_clk; - - p_clk = clk_get_parent(main_bus_clk); - /* Set the parent of main_bus_clk to be periph_apm_clk */ - clk_set_parent(main_bus_clk, amode_parent_clk); - clk_set_rate(ahb_clk, lp_lpm_clk); - /* Set the emi_internal clock to 24MHz */ - clk_set_rate(emi_intr_clk, lp_lpm_clk); - if (clk_get_parent(emi_core_clk) != ahb_clk) - clk_set_rate(emi_core_clk, lp_lpm_clk); - - if (clk_get_usecount(axi_a_clk) != 0) - clk_set_rate(axi_a_clk, lp_lpm_clk); + if (low_bus_freq_mode || (clk_get_rate(cpu_clk) != GP_LPAPM_FREQ)) { + spin_unlock_irqrestore(&bus_freq_lock, flags); + return ret; + } - if (clk_get_usecount(axi_b_clk) != 0) - clk_set_rate(axi_b_clk, lp_lpm_clk); + if (clk_get_rate(cpu_clk) != GP_LPAPM_FREQ) + return ret; - if (clk_get_usecount(axi_c_clk) != 0) - clk_set_rate(axi_c_clk, lp_lpm_clk); + lp_lpm_clk = clk_get_rate(periph_apm_clk) / 8; - amode_parent_clk = emi_core_clk; + /* Set the parent of peripheral_apm_clk to be lpapm */ + clk_set_parent(periph_apm_clk, pll1); + /* Set the LP clocks */ + clk_set_parent(main_bus_clk, periph_apm_clk); - p_clk = clk_get_parent(arm_axi_clk); - if (p_clk != amode_parent_clk) - clk_set_parent(arm_axi_clk, amode_parent_clk); + clk_set_rate(axi_a_clk, clk_round_rate(axi_a_clk, lp_lpm_clk)); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, lp_lpm_clk)); + clk_set_rate(axi_c_clk, clk_round_rate(axi_c_clk, lp_lpm_clk)); + clk_set_rate(emi_core_clk, clk_round_rate(emi_core_clk, lp_lpm_clk)); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, lp_lpm_clk)); + /* Set the emi_intr_clk to be at 24MHz. */ + clk_set_rate(emi_intr_clk, clk_round_rate(emi_intr_clk, lp_lpm_clk)); - p_clk = clk_get_parent(vpu_clk); - if (p_clk != amode_parent_clk) - clk_set_parent(vpu_clk, amode_parent_clk); + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; - p_clk = clk_get_parent(vpu_core_clk); - if (p_clk != amode_parent_clk) - clk_set_parent(vpu_core_clk, amode_parent_clk); spin_unlock_irqrestore(&bus_freq_lock, flags); /* Set the voltage to 1.05V for the LP domain. */ @@ -143,23 +121,18 @@ int set_low_bus_freq(void) return ret; } - low_bus_freq_mode = 1; - high_bus_freq_mode = 0; return ret; } int set_high_bus_freq(int high_bus_freq) { - struct clk *p_clk; - struct clk *rmode_parent_clk; int ret = 0; unsigned long flags; + unsigned long lp_lpm_clk; if (!low_bus_freq_mode) return ret; - low_bus_freq_mode = 0; - /* Set the voltage to 1.25V for the LP domain. */ ret = regulator_set_voltage(lp_regulator, 1250000, 1250000); udelay(100); @@ -168,28 +141,27 @@ int set_high_bus_freq(int high_bus_freq) return ret; } - rmode_parent_clk = pll2; spin_lock_irqsave(&bus_freq_lock, flags); - /* Set the dividers before setting the parent clock. */ - if (clk_get_usecount(axi_a_clk) != 0) - clk_set_rate(axi_a_clk, 4800000); - if (clk_get_usecount(axi_b_clk) != 0) - clk_set_rate(axi_b_clk, 4000000); - if (clk_get_usecount(axi_c_clk) != 0) - clk_set_rate(axi_c_clk, 6000000); - if (clk_get_parent(emi_core_clk) != ahb_clk) - clk_set_rate(emi_core_clk, 4800000); - - clk_set_rate(ahb_clk, 4800000); + low_bus_freq_mode = 0; + + /* Set the LP clocks. */ + lp_lpm_clk = clk_get_rate(periph_apm_clk); + clk_set_rate(axi_a_clk, clk_round_rate(axi_a_clk, lp_lpm_clk/5)); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, lp_lpm_clk/5)); + clk_set_rate(axi_c_clk, clk_round_rate(axi_c_clk, lp_lpm_clk/5)); + clk_set_rate(emi_core_clk, clk_round_rate(emi_core_clk, lp_lpm_clk/5)); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, lp_lpm_clk/5)); /* Set emi_intr clock back to divide by 2. */ - clk_set_rate(emi_intr_clk, 2400000); + clk_set_rate(emi_intr_clk, clk_round_rate(emi_intr_clk, lp_lpm_clk/10)); + /* Set the parent of main_bus_clk to be pll2 */ - clk_set_parent(main_bus_clk, rmode_parent_clk); - spin_unlock_irqrestore(&bus_freq_lock, flags); + clk_set_parent(main_bus_clk, pll2); - clk_enable(uart_clk); high_bus_freq_mode = 1; + + spin_unlock_irqrestore(&bus_freq_lock, flags); + return ret; } @@ -240,16 +212,25 @@ void setup_pll(void) /* MFN */ __raw_writel(p->mfn, MXC_DPLL1_BASE + MXC_PLL_DP_HFS_MFN); } - - /* Set PLL2_PODF to be 3 */ - reg = __raw_readl(MXC_CCM_CCSR); - reg |= 2 << MXC_CCM_CCSR_PLL2_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CCSR); - /* Set the parent of STEP_CLK to be PLL2 */ - reg = __raw_readl(MXC_CCM_CCSR); - reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | - (2 << MXC_CCM_CCSR_STEP_SEL_OFFSET); - __raw_writel(reg, MXC_CCM_CCSR); + if (clk_get_usecount(pll2) != 0) { + /* Set the temporal frequency to be PLL2 */ + /* Set PLL2_PODF to be 3. */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= 2 << MXC_CCM_CCSR_PLL2_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CCSR); + /* Set the parent of STEP_CLK to be PLL2 */ + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (2 << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + } else { + /* Set the temporal frequency to be lp-apm */ + /* Set the parent of STEP_CLK to be lp-apm */ + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (0 << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + } } /*! @@ -385,7 +366,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(pll1); } - lp_regulator = regulator_get(NULL, lp_reg_id); if (IS_ERR(lp_regulator)) { clk_put(ahb_clk); @@ -394,7 +374,7 @@ static int __devinit busfreq_probe(struct platform_device *pdev) } low_bus_freq_mode = 0; - high_bus_freq_mode = 0; + high_bus_freq_mode = 1; cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); @@ -413,7 +393,6 @@ static struct platform_driver busfreq_driver = { * * @return The function always returns 0. */ - static int __init busfreq_init(void) { if (platform_driver_register(&busfreq_driver) != 0) { diff --git a/arch/arm/mach-mx37/clock.c b/arch/arm/mach-mx37/clock.c index 3d3938ca3d9b..b39b3c09e37c 100644 --- a/arch/arm/mach-mx37/clock.c +++ b/arch/arm/mach-mx37/clock.c @@ -363,6 +363,7 @@ static struct clk pll1_sw_clk = { static struct clk pll2_sw_clk = { .name = "pll2", .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, .recalc = _clk_pll_recalc, .enable = _clk_pll_enable, .disable = _clk_pll_disable, @@ -494,9 +495,6 @@ static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) if (emi_intr_clk.usecount == 0) emi_intr_clk.enable(&emi_intr_clk); - if (ipu_clk[0].usecount == 0) - ipu_clk[0].enable(&ipu_clk[0]); - if (parent == &pll2_sw_clk) { reg = __raw_readl(MXC_CCM_CBCDR6) & ~MXC_CCM_CBCDR6_PERIPH_CLK_SEL; @@ -524,9 +522,6 @@ static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) if (emi_intr_clk.usecount == 0) emi_intr_clk.disable(&emi_intr_clk); - if (ipu_clk[0].usecount == 0) - ipu_clk[0].enable(&ipu_clk[0]); - return 0; } @@ -762,10 +757,6 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) reg |= (div - 1) << MXC_CCM_CBCDR2_AHB_PODF_OFFSET; __raw_writel(reg, MXC_CCM_CBCDR2); - /* Set the Load-dividers bit in CCM */ - reg = __raw_readl(MXC_CCM_CCDR); - reg |= MXC_CCM_CCDR_LOAD_DIVIDERS; - __raw_writel(reg, MXC_CCM_CCDR); clk->rate = rate; return 0; @@ -918,10 +909,6 @@ static struct clk emi_core_clk = { .set_rate = _clk_emi_core_set_rate, .round_rate = _clk_emi_core_round_rate, .flags = RATE_PROPAGATES, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGR5_CG11_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable_inwait, }; static struct clk ahbmux1_clk = { @@ -2393,12 +2380,6 @@ static int _clk_ipu_enable(struct clk *clk) reg = __raw_readl(MXC_CCM_CCDR); reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; __raw_writel(reg, MXC_CCM_CCDR); - - /* Handshake with IPU when LPM is entered as its enabled. */ - reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); - return 0; } @@ -2411,11 +2392,6 @@ static void _clk_ipu_disable(struct clk *clk) reg = __raw_readl(MXC_CCM_CCDR); reg |= MXC_CCM_CCDR_IPU_HS_MASK; __raw_writel(reg, MXC_CCM_CCDR); - - /* No handshake with IPU when LPM is entered as its not enabled. */ - reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); } static int _clk_ipu_set_parent(struct clk *clk, struct clk *parent) @@ -3060,9 +3036,6 @@ int __init mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&vpu_clk[0], &axi_a_clk); clk_set_parent(&vpu_clk[1], &axi_a_clk); - clk_set_parent(&emi_core_clk, &ahb_clk); - clk_set_rate(&emi_core_clk, clk_round_rate(&emi_core_clk, 130000000)); - propagate_rate(&emi_core_clk); clk_set_rate(&emi_intr_clk, clk_round_rate(&emi_intr_clk, 66000000)); /* Change the NFC clock rate to be 1:3 ratio with emi clock. */ clk_set_rate(&nfc_clk, clk_round_rate(&nfc_clk, @@ -3070,8 +3043,11 @@ int __init mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&usb_phy_clk, &osc_clk); + clk_set_parent(&periph_apm_clk, &lp_apm_clk); + clk_set_parent(&cko1_clk, &ipg_perclk); clk_set_rate(&cko1_clk, 8000000); + /* Set the current working point. */ cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); for (i = 0; i < cpu_wp_nr; i++) { diff --git a/arch/arm/mach-mx37/lpmodes.c b/arch/arm/mach-mx37/lpmodes.c deleted file mode 100644 index 7685a5c249a0..000000000000 --- a/arch/arm/mach-mx37/lpmodes.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/*! - * @file mx37_lpmodes.c - * - * @brief Driver for the Freescale Semiconductor MXC low power modes setup. - * - * MX37 is designed to play and video with minimal power consumption. - * This driver enables the platform to enter and exit audio and video low - * power modes. - * - * @ingroup PM - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/fs.h> -#include <linux/interrupt.h> -#include <linux/jiffies.h> -#include <linux/device.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/workqueue.h> -#include <linux/platform_device.h> -#include <mach/clock.h> -#include <mach/hardware.h> -#include <linux/regulator/consumer.h> -#include "crm_regs.h" - -#define ARM_LP_CLK 200000000 -#define GP_LPM_VOLTAGE 850000 -#define LP_LPM_VOLTAGE 1000000 -#define GP_NORMAL_VOLTAGE 1000000 -#define LP_NORMAL_VOLTAGE 1200000 - -static int org_cpu_rate; -int lp_video_mode; -int lp_audio_mode; -static struct device *lpmode_dev; - -void enter_lp_video_mode(void) -{ - int ret = 0; - - struct clk *p_clk; - struct clk *tclk; - struct clk *vmode_parent_clk; - struct regulator *gp_core; - - tclk = clk_get(NULL, "main_bus_clk"); - vmode_parent_clk = clk_get(NULL, "pll2"); - p_clk = clk_get_parent(tclk); - - if (p_clk != vmode_parent_clk) { - clk_set_parent(tclk, vmode_parent_clk); - - clk_set_rate(clk_get(NULL, "axi_a_clk"), 133000000); - clk_set_rate(clk_get(NULL, "axi_b_clk"), 66500000); - clk_set_rate(clk_get(NULL, "axi_c_clk"), 166000000); - clk_set_rate(clk_get(NULL, "emi_core_clk"), 133000000); - clk_set_rate(clk_get(NULL, "nfc_clk"), 26600000); - clk_set_rate(clk_get(NULL, "ahb_clk"), 133000000); - } - - /* move VPU clock to source from the emi_core_clk */ - tclk = clk_get(NULL, "vpu_clk"); - vmode_parent_clk = clk_get(NULL, "emi_core_clk"); - if (clk_get_parent(tclk) != vmode_parent_clk) - clk_set_parent(tclk, vmode_parent_clk); - - tclk = clk_get(NULL, "vpu_core_clk"); - if (clk_get_parent(tclk) != vmode_parent_clk) - clk_set_parent(tclk, vmode_parent_clk); - - tclk = clk_get(NULL, "arm_axi_clk"); - if (clk_get_parent(tclk) != vmode_parent_clk) - clk_set_parent(tclk, vmode_parent_clk); - - tclk = clk_get(NULL, "ddr_clk"); - vmode_parent_clk = clk_get(NULL, "axi_c_clk"); - if (clk_get_parent(tclk) != vmode_parent_clk) - clk_set_parent(tclk, vmode_parent_clk); - - /* disable PLL3 */ - tclk = clk_get(NULL, "pll3"); - if (tclk->usecount == 1) - clk_disable(tclk); - - tclk = clk_get(NULL, "cpu_clk"); - org_cpu_rate = clk_get_rate(tclk); - - ret = clk_set_rate(tclk, ARM_LP_CLK); - if (ret != 0) - printk(KERN_DEBUG "cannot set CPU clock rate\n"); - - /* Set the voltage to 0.8v for the GP domain. */ - - if (!board_is_rev(BOARD_REV_2)) - gp_core = regulator_get(NULL, "DCDC1"); - else - gp_core = regulator_get(NULL, "SW1"); - - ret = regulator_set_voltage(gp_core, GP_LPM_VOLTAGE, GP_LPM_VOLTAGE); - if (ret < 0) - printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!\n"); - - lp_video_mode = 1; -} - -void exit_lp_video_mode(void) -{ - int ret = 0; - static struct clk *tclk; - struct regulator *gp_core; - - /*Set the voltage to 0.8v for the GP domain. */ - if (!board_is_rev(BOARD_REV_2)) - gp_core = regulator_get(NULL, "DCDC1"); - else - gp_core = regulator_get(NULL, "SW1"); - - ret = regulator_set_voltage(gp_core, GP_NORMAL_VOLTAGE, GP_NORMAL_VOLTAGE); - if (ret < 0) - printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); - - tclk = clk_get(NULL, "cpu_clk"); - - ret = clk_set_rate(tclk, org_cpu_rate); - if (ret != 0) - printk(KERN_DEBUG "cannot set CPU clock rate\n"); - - lp_video_mode = 0; -} - -void enter_lp_audio_mode(void) -{ - int ret = 0; - - struct clk *p_clk; - struct clk *tclk; - struct clk *amode_parent_clk; - struct regulator *gp_core; - struct regulator *lp_core; - - tclk = clk_get(NULL, "ipu_clk"); - if (clk_get_usecount(tclk) != 0) { - printk(KERN_INFO - "Cannot enter AUDIO LPM mode - display is still active\n"); - return; - } - - tclk = clk_get(NULL, "periph_apm_clk"); - amode_parent_clk = clk_get(NULL, "lp_apm"); - p_clk = clk_get_parent(tclk); - - /* Make sure osc_clk is the parent of lp_apm. */ - clk_set_parent(amode_parent_clk, clk_get(NULL, "osc")); - - /* Set the parent of periph_apm_clk to be lp_apm */ - clk_set_parent(tclk, amode_parent_clk); - amode_parent_clk = tclk; - - tclk = clk_get(NULL, "main_bus_clk"); - p_clk = clk_get_parent(tclk); - /* Set the parent of main_bus_clk to be periph_apm_clk */ - clk_set_parent(tclk, amode_parent_clk); - - clk_set_rate(clk_get(NULL, "axi_a_clk"), 24000000); - clk_set_rate(clk_get(NULL, "axi_b_clk"), 24000000); - clk_set_rate(clk_get(NULL, "axi_c_clk"), 24000000); - clk_set_rate(clk_get(NULL, "emi_core_clk"), 24000000); - clk_set_rate(clk_get(NULL, "nfc_clk"), 4800000); - clk_set_rate(clk_get(NULL, "ahb_clk"), 24000000); - - amode_parent_clk = clk_get(NULL, "emi_core_clk"); - - tclk = clk_get(NULL, "arm_axi_clk"); - p_clk = clk_get_parent(tclk); - if (p_clk != amode_parent_clk) { - clk_set_parent(tclk, amode_parent_clk); - } - - tclk = clk_get(NULL, "vpu_clk"); - p_clk = clk_get_parent(tclk); - if (p_clk != amode_parent_clk) { - clk_set_parent(tclk, amode_parent_clk); - } - - tclk = clk_get(NULL, "vpu_core_clk"); - p_clk = clk_get_parent(tclk); - if (p_clk != amode_parent_clk) { - clk_set_parent(tclk, amode_parent_clk); - } - - /* disable PLL3 */ - tclk = clk_get(NULL, "pll3"); - if (tclk->usecount == 1) - clk_disable(tclk); - - /* disable PLL2 */ - tclk = clk_get(NULL, "pll2"); - if (tclk->usecount == 1) - clk_disable(tclk); - - /* Set the voltage to 1.0v for the LP domain. */ - if (!board_is_rev(BOARD_REV_2)) - lp_core = regulator_get(NULL, "DCDC4"); - else - lp_core = regulator_get(NULL, "SW2"); - - if (lp_core != NULL) { - ret = regulator_set_voltage(lp_core, LP_LPM_VOLTAGE, LP_LPM_VOLTAGE); - if (ret < 0) - printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!!\n"); - } - - tclk = clk_get(NULL, "cpu_clk"); - org_cpu_rate = clk_get_rate(tclk); - - ret = clk_set_rate(tclk, ARM_LP_CLK); - if (ret != 0) - printk(KERN_DEBUG "cannot set CPU clock rate\n"); - - /* Set the voltage to 0.8v for the GP domain. */ - if (!board_is_rev(BOARD_REV_2)) - gp_core = regulator_get(NULL, "DCDC1"); - else - gp_core = regulator_get(NULL, "SW1"); - - if (gp_core != NULL) { - ret = regulator_set_voltage(gp_core, GP_LPM_VOLTAGE, GP_LPM_VOLTAGE); - if (ret < 0) - printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!\n"); - } - lp_audio_mode = 1; -} - -void exit_lp_audio_mode(void) -{ - struct regulator *gp_core; - struct regulator *lp_core; - struct clk *tclk; - struct clk *p_clk; - struct clk *rmode_parent_clk; - int ret; - - lp_audio_mode = 0; - /* Set the voltage to 1.2v for the LP domain. */ - if (!board_is_rev(BOARD_REV_2)) - lp_core = regulator_get(NULL, "DCDC4"); - else - lp_core = regulator_get(NULL, "SW2"); - - if (lp_core != NULL) { - ret = regulator_set_voltage(lp_core, LP_NORMAL_VOLTAGE, LP_NORMAL_VOLTAGE); - if (ret < 0) - printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!!!\n"); - } - - /* Set the voltage to 1.0v for the GP domain. */ - if (!board_is_rev(BOARD_REV_2)) - gp_core = regulator_get(NULL, "DCDC1"); - else - gp_core = regulator_get(NULL, "SW1"); - - ret = regulator_set_voltage(gp_core, GP_NORMAL_VOLTAGE, GP_NORMAL_VOLTAGE); - if (ret < 0) - printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); - - tclk = clk_get(NULL, "cpu_clk"); - - ret = clk_set_rate(tclk, org_cpu_rate); - if (ret != 0) - printk(KERN_DEBUG "cannot set CPU clock rate\n"); - - rmode_parent_clk = clk_get(NULL, "pll2"); - clk_enable(rmode_parent_clk); - - tclk = clk_get(NULL, "main_bus_clk"); - p_clk = clk_get_parent(tclk); - - /* Set the dividers before setting the parent clock. */ - clk_set_rate(clk_get(NULL, "axi_a_clk"), 4800000); - clk_set_rate(clk_get(NULL, "axi_b_clk"), 4000000); - clk_set_rate(clk_get(NULL, "axi_c_clk"), 6000000); - clk_set_rate(clk_get(NULL, "emi_core_clk"), 4800000); - clk_set_rate(clk_get(NULL, "ahb_clk"), 4800000); - - /* Set the parent of main_bus_clk to be pll2 */ - clk_set_parent(tclk, rmode_parent_clk); - udelay(5); -} - -static ssize_t lp_curr_mode(struct device *dev, - struct device_attribute *attr, char *buf) -{ - if (lp_video_mode) - return sprintf(buf, "in lp_video_mode\n"); - else if (lp_audio_mode) - return sprintf(buf, "in lp_audio_mode\n"); - else - return sprintf(buf, "in normal mode\n"); -} - -static ssize_t set_lp_mode(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - printk(KERN_DEBUG "In set_lp_mode() \n"); - - if (strstr(buf, "enable_lp_video") != NULL) { - if (!lp_video_mode) - enter_lp_video_mode(); - } else if (strstr(buf, "disable_lp_video") != NULL) { - if (lp_video_mode) - exit_lp_video_mode(); - } else if (strstr(buf, "enable_lp_audio") != NULL) { - if (!lp_audio_mode) - enter_lp_audio_mode(); - } else if (strstr(buf, "disable_lp_audio") != NULL) { - if (lp_audio_mode) - exit_lp_audio_mode(); - } - return size; -} - -static DEVICE_ATTR(lp_modes, 0644, lp_curr_mode, set_lp_mode); - -/*! - * This is the probe routine for the lp_mode driver. - * - * @param pdev The platform device structure - * - * @return The function returns 0 on success - * - */ -static int __devinit mx37_lpmode_probe(struct platform_device *pdev) -{ - u32 res = 0; - lpmode_dev = &pdev->dev; - - res = sysfs_create_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); - if (res) { - printk(KERN_ERR - "lpmode_dev: Unable to register sysdev entry for lpmode_dev"); - return res; - } - - if (res != 0) { - printk(KERN_ERR "lpmode_dev: Unable to start"); - return res; - } - lp_video_mode = 0; - lp_audio_mode = 0; - - return 0; -} - -static struct platform_driver mx37_lpmode_driver = { - .driver = { - .name = "mx37_lpmode", - }, - .probe = mx37_lpmode_probe, -}; - -/*! - * Initialise the mx37_lpmode_driver. - * - * @return The function always returns 0. - */ - -static int __init lpmode_init(void) -{ - if (platform_driver_register(&mx37_lpmode_driver) != 0) { - printk(KERN_ERR "mx37_lpmode_driver register failed\n"); - return -ENODEV; - } - - printk(KERN_INFO "LPMode driver module loaded\n"); - return 0; -} - -static void __exit lpmode_cleanup(void) -{ - sysfs_remove_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); - - /* Unregister the device structure */ - platform_driver_unregister(&mx37_lpmode_driver); -} - -module_init(lpmode_init); -module_exit(lpmode_cleanup); - -MODULE_AUTHOR("Freescale Semiconductor, Inc."); -MODULE_DESCRIPTION("LPMode driver"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx37/mx37_3stack.c b/arch/arm/mach-mx37/mx37_3stack.c index b9e88e57daab..80b55bcbd999 100644 --- a/arch/arm/mach-mx37/mx37_3stack.c +++ b/arch/arm/mach-mx37/mx37_3stack.c @@ -72,14 +72,6 @@ static struct cpu_wp cpu_wp_auto[] = { .mfn = 13, .cpu_voltage = 1050000,}, { - .pll_rate = 400000000, - .cpu_rate = 400000000, - .pdf = 1, - .mfi = 8, - .mfd = 2, - .mfn = 1, - .cpu_voltage = 950000,}, - { .pll_rate = 200000000, .cpu_rate = 200000000, .pdf = 3, @@ -87,19 +79,11 @@ static struct cpu_wp cpu_wp_auto[] = { .mfd = 2, .mfn = 1, .cpu_voltage = 850000,}, - { - .pll_rate = 600000000, - .cpu_rate = 600000000, - .pdf = 0, - .mfi = 6, - .mfd = 3, - .mfn = 1, - .cpu_voltage = 1200000,}, }; struct cpu_wp *get_cpu_wp(int *wp) { - *wp = 3; + *wp = 2; return cpu_wp_auto; } diff --git a/arch/arm/mach-mx37/system.c b/arch/arm/mach-mx37/system.c index d40549b29ddc..78685f625813 100644 --- a/arch/arm/mach-mx37/system.c +++ b/arch/arm/mach-mx37/system.c @@ -36,9 +36,6 @@ extern int mxc_jtag_enabled; extern int low_bus_freq_mode; -static struct clk *pll1_main; -static struct clk *pll1_sw_clk; -static struct clk *lp_apm_clk; static struct clk *gpc_dvfs_clk; /* set cpu low power mode before WFI instruction */ @@ -96,8 +93,6 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if ((mxc_cpu_is_rev(CHIP_REV_1_0)) != 1) __raw_writel(empgcr0, MXC_EMPGC0_ARM_EMPGCR); - __raw_writel(empgcr1, MXC_EMPGC1_ARM_EMPGCR); - flush_cache_all(); if (gpc_dvfs_clk == NULL) @@ -105,18 +100,6 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) /* gpc clock is needed for SRPG */ clk_enable(gpc_dvfs_clk); - if (low_bus_freq_mode) { - if (pll1_sw_clk == NULL) - pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); - if (lp_apm_clk == NULL) - lp_apm_clk = clk_get(NULL, "lp_apm"); - if (pll1_main == NULL) - pll1_main = clk_get(NULL, "pll1_main_clk"); - - /* Move the ARM to run off the 24MHz clock. Shutdown the PLL1 */ - /* Change the source of pll1_sw_clk to be the step_clk */ - clk_set_parent(pll1_sw_clk, lp_apm_clk); - } } void mxc_pg_enable(struct platform_device *pdev) @@ -172,11 +155,6 @@ void arch_idle(void) cpu_do_idle(); /* gpc clock is needed for SRPG */ clk_disable(gpc_dvfs_clk); - if (low_bus_freq_mode) { - /* Move ARM back to PLL from step clk. */ - /* Move the PLL1 back to the pll1_main_clk */ - clk_set_parent(pll1_sw_clk, pll1_main); - } } } |