diff options
Diffstat (limited to 'arch/arm/mach-mx6/board-mx6dl_phyflex.h')
| -rw-r--r-- | arch/arm/mach-mx6/board-mx6dl_phyflex.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/board-mx6dl_phyflex.h b/arch/arm/mach-mx6/board-mx6dl_phyflex.h index f2ad9316e18f..3c1464111662 100644 --- a/arch/arm/mach-mx6/board-mx6dl_phyflex.h +++ b/arch/arm/mach-mx6/board-mx6dl_phyflex.h @@ -20,6 +20,13 @@ #define _BOARD_MX6DL_PHYFLEX_H #include <mach/iomux-mx6dl.h> +#define PHYFLEX_MX6DL_CLKO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) + +#define PHYFLEX_MX6DL_PAD_GPIO_5__CCM_CLKO \ + (MX6DL_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(PHYFLEX_CLKO_PAD_CTRL)) + + static iomux_v3_cfg_t mx6dl_phyflex_pads[] = { /* GPIOs for revision control */ @@ -145,6 +152,50 @@ static iomux_v3_cfg_t mx6dl_phyflex_pads[] = { MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE, + + /* ipu1 csi0 */ + MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC, + MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK, + MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC, + MX6DL_PAD_CSI0_DATA_EN__GPIO_5_20, + PHYFLEX_MX6DL_PAD_GPIO_5__CCM_CLKO, + MX6DL_PAD_ENET_RX_ER__GPIO_1_24, + MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_D_10, + MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_D_11, + MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_D_12, + MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_D_13, + MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_D_14, + MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_D_15, + MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_D_16, + MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_D_17, + MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_D_18, + MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_D_19, + + /* ipu1 csi1 */ + MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK, + MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC, + MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC, + MX6DL_PAD_EIM_DA10__GPIO_3_10, + MX6DL_PAD_EIM_DA9__IPU1_CSI1_D_0, + MX6DL_PAD_EIM_DA8__IPU1_CSI1_D_1, + MX6DL_PAD_EIM_DA7__IPU1_CSI1_D_2, + MX6DL_PAD_EIM_DA6__IPU1_CSI1_D_3, + MX6DL_PAD_EIM_DA5__IPU1_CSI1_D_4, + MX6DL_PAD_EIM_DA4__IPU1_CSI1_D_5, + MX6DL_PAD_EIM_DA3__IPU1_CSI1_D_6, + MX6DL_PAD_EIM_DA2__IPU1_CSI1_D_7, + MX6DL_PAD_EIM_DA1__IPU1_CSI1_D_8, + MX6DL_PAD_EIM_DA0__IPU1_CSI1_D_9, + MX6DL_PAD_EIM_EB1__IPU1_CSI1_D_10, + MX6DL_PAD_EIM_EB0__GPIO_2_28, + MX6DL_PAD_EIM_A17__IPU1_CSI1_D_12, + MX6DL_PAD_EIM_A18__IPU1_CSI1_D_13, + MX6DL_PAD_EIM_A19__IPU1_CSI1_D_14, + MX6DL_PAD_EIM_A20__IPU1_CSI1_D_15, + MX6DL_PAD_EIM_A21__IPU1_CSI1_D_16, + MX6DL_PAD_EIM_A22__IPU1_CSI1_D_17, + MX6DL_PAD_EIM_A23__IPU1_CSI1_D_18, + MX6DL_PAD_EIM_A24__IPU1_CSI1_D_19, }; #endif /* _BOARD_MX6DL_PHYFLEX_H */ |