diff options
Diffstat (limited to 'arch/arm/mach-mx6/cpu_regulator-mx6.c')
| -rw-r--r-- | arch/arm/mach-mx6/cpu_regulator-mx6.c | 70 |
1 files changed, 44 insertions, 26 deletions
diff --git a/arch/arm/mach-mx6/cpu_regulator-mx6.c b/arch/arm/mach-mx6/cpu_regulator-mx6.c index d905132e98b1..59bc3832d00f 100644 --- a/arch/arm/mach-mx6/cpu_regulator-mx6.c +++ b/arch/arm/mach-mx6/cpu_regulator-mx6.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -97,12 +97,32 @@ void mx6_cpu_regulator_init(void) } else { curr_cpu = clk_get_rate(cpu_clk); cpu_op_tbl = get_cpu_op(&cpu_op_nr); - /* Set the core to max frequency requested. */ + + soc_regulator = regulator_get(NULL, soc_reg_id); + if (IS_ERR(soc_regulator)) + printk(KERN_ERR "%s: failed to get soc regulator\n", + __func__); + else + /* set soc to highest setpoint voltage. */ + regulator_set_voltage(soc_regulator, + cpu_op_tbl[0].soc_voltage, + cpu_op_tbl[0].soc_voltage); + + pu_regulator = regulator_get(NULL, pu_reg_id); + if (IS_ERR(pu_regulator)) + printk(KERN_ERR "%s: failed to get pu regulator\n", + __func__); + else + /* set pu to higheset setpoint voltage. */ + regulator_set_voltage(pu_regulator, + cpu_op_tbl[0].pu_voltage, + cpu_op_tbl[0].pu_voltage); + /* set the core to higheset setpoint voltage. */ regulator_set_voltage(cpu_regulator, cpu_op_tbl[0].cpu_voltage, cpu_op_tbl[0].cpu_voltage); if (enable_ldo_mode == LDO_MODE_BYPASSED) { - /*digital bypass VDDPU/VDDSOC/VDDARM*/ + /* digital bypass VDDPU/VDDSOC/VDDARM */ reg = __raw_readl(ANADIG_REG_CORE); reg &= ~BM_ANADIG_REG_CORE_REG0_TRG; reg |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f); @@ -111,14 +131,15 @@ void mx6_cpu_regulator_init(void) reg &= ~BM_ANADIG_REG_CORE_REG2_TRG; reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f); __raw_writel(reg, ANADIG_REG_CORE); - /* Mask the ANATOP brown out interrupt in the GPC. */ + /* mask the ANATOP brown out irq in the GPC. */ reg = __raw_readl(gpc_base + 0x14); reg |= 0x80000000; __raw_writel(reg, gpc_base + 0x14); } + clk_set_rate(cpu_clk, cpu_op_tbl[0].cpu_rate); - /*Fix loops-per-jiffy */ + /* fix loops-per-jiffy */ #ifdef CONFIG_SMP for_each_online_cpu(cpu) per_cpu(cpu_data, cpu).loops_per_jiffy = @@ -141,27 +162,24 @@ void mx6_cpu_regulator_init(void) #endif } } - soc_regulator = regulator_get(NULL, soc_reg_id); - if (IS_ERR(soc_regulator)) - printk(KERN_ERR "%s: failed to get soc regulator\n", __func__); - pu_regulator = regulator_get(NULL, pu_reg_id); - if (IS_ERR(pu_regulator)) - printk(KERN_ERR "%s: failed to get pu regulator\n", __func__); - /*If use ldo bypass and VDDPU_IN is single supplied - *by external pmic, it means VDDPU_IN can be turned off if GPU/VPU driver - *not running.In this case we should set external_pureg which can be used - *in pu_enable/pu_disable of arch/arm/mach-mx6/mx6_anatop_regulator.c to - *enable or disable external VDDPU regulator from pmic. But for FSL - *reference boards, VDDSOC_IN connect with VDDPU_IN, so we didn't set - *pu_reg_id to the external pmic regulator supply name in the board file. - *In this case external_pureg should be 0 and can't turn off extern pmic - *regulator, but can turn off VDDPU by internal anatop power gate. - * - *If enable internal ldo , external_pureg will be 0, and - *VDDPU can be turned off by internal anatop anatop power gate. - * - */ - else if (!IS_ERR(pu_regulator) && strcmp(pu_reg_id, "cpu_vddgpu")) + /* + * if use ldo bypass and VDDPU_IN is single supplied + * by external pmic, it means VDDPU_IN can be turned off + * if GPU/VPU driver not running.In this case we should set + * external_pureg which can be used in pu_enable/pu_disable of + * arch/arm/mach-mx6/mx6_anatop_regulator.c to + * enable or disable external VDDPU regulator from pmic. But for FSL + * reference boards, VDDSOC_IN connect with VDDPU_IN, so we didn't set + * pu_reg_id to the external pmic regulator supply name in the board + * file. In this case external_pureg should be 0 and can't turn off + * extern pmic regulator, but can turn off VDDPU by internal anatop + * power gate. + * + * if enable internal ldo , external_pureg will be 0, and + * VDDPU can be turned off by internal anatop anatop power gate. + * + */ + if (!IS_ERR(pu_regulator) && strcmp(pu_reg_id, "cpu_vddgpu")) external_pureg = 1; } |