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Diffstat (limited to 'arch/arm/mach-mx6/pm.c')
-rw-r--r--arch/arm/mach-mx6/pm.c27
1 files changed, 19 insertions, 8 deletions
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index 6e306c279d20..d9c04e11bed0 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -176,9 +176,8 @@ static void usb_power_up_handler(void)
static void disp_power_down(void)
{
-#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
- !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
- if (cpu_is_mx6sl()) {
+ if (cpu_is_mx6sl() && (mx6sl_revision() >= IMX_CHIP_REVISION_1_2)) {
+
__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
@@ -194,14 +193,11 @@ static void disp_power_down(void)
~MXC_CCM_CCGRx_CG1_MASK, MXC_CCM_CCGR3);
}
-#endif
}
static void disp_power_up(void)
{
-#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
- !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
- if (cpu_is_mx6sl()) {
+ if (cpu_is_mx6sl() && (mx6sl_revision() >= IMX_CHIP_REVISION_1_2)) {
/*
* Need to enable EPDC/LCDIF pix clock, and
* EPDC/LCDIF/PXP axi clock before power up.
@@ -217,7 +213,6 @@ static void disp_power_up(void)
__raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET);
__raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
}
-#endif
}
static void mx6_suspend_store(void)
@@ -342,6 +337,14 @@ static int mx6_suspend_enter(suspend_state_t state)
return -EINVAL;
}
+ /*
+ * L2 can exit by 'reset' or Inband beacon (from remote EP)
+ * toggling phy_powerdown has same effect as 'inband beacon'
+ * So, toggle bit18 of GPR1, to fix errata
+ * "PCIe PCIe does not support L2 Power Down"
+ */
+ __raw_writel(__raw_readl(IOMUXC_GPR1) | (1 << 18), IOMUXC_GPR1);
+
if (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY) {
local_flush_tlb_all();
@@ -405,6 +408,14 @@ static int mx6_suspend_enter(suspend_state_t state)
cpu_do_idle();
}
+ /*
+ * L2 can exit by 'reset' or Inband beacon (from remote EP)
+ * toggling phy_powerdown has same effect as 'inband beacon'
+ * So, toggle bit18 of GPR1, to fix errata
+ * "PCIe PCIe does not support L2 Power Down"
+ */
+ __raw_writel(__raw_readl(IOMUXC_GPR1) & (~(1 << 18)), IOMUXC_GPR1);
+
return 0;
}