diff options
Diffstat (limited to 'arch/arm/mach-ns9xxx/include')
30 files changed, 2391 insertions, 186 deletions
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h index f7e9196eb9ab..247c0034e573 100644 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ b/arch/arm/mach-ns9xxx/include/mach/board.h @@ -31,10 +31,18 @@ || machine_is_cc9p9215js() \ ) +#define board_is_jsccw9p9215() (0 \ + || machine_is_ccw9p9215js() \ + ) + #define board_is_jscc9p9360() (0 \ || machine_is_cc9p9360js() \ ) +#define board_is_jscme9210() (0 \ + || machine_is_cme9210js() \ + ) + #define board_is_uncbas() (0 \ || machine_is_cc7ucamry() \ ) diff --git a/arch/arm/mach-ns9xxx/include/mach/display/CUSTOM.h b/arch/arm/mach-ns9xxx/include/mach/display/CUSTOM.h new file mode 100644 index 000000000000..2eceb4b94494 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/display/CUSTOM.h @@ -0,0 +1,18 @@ + + + +/* +#define CUSTOM_DISPLAY \ +{ \ + .display_name = "CUSTOM", \ + .width = , \ + .height = , \ + .control = NS9360_DISPLAY_CONTROL, \ + .timing = { \ + NS9360_DISPLAY_TIMING0, \ + NS9360_DISPLAY_TIMING1, \ + NS9360_DISPLAY_TIMING2, \ + }, \ + .clock = NS9360_DISPLAY_CLOCK, \ +} +*/
\ No newline at end of file diff --git a/arch/arm/mach-ns9xxx/include/mach/display/Kconfig b/arch/arm/mach-ns9xxx/include/mach/display/Kconfig new file mode 100644 index 000000000000..842eb775185e --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/display/Kconfig @@ -0,0 +1,36 @@ +# arch/arm/mach-ns9xxx/displays/Kconfig +# +# Copyright 2009 Digi International Inc +# + +if (CC9P9360JS_FB || CCX9C_FB) + +comment "Display selection" + +config NS9XXX_FB_VGA + bool "CRT VGA video support" + depends on ! (CC9P9360JS_SERIAL_PORTA_FULL || CCX9C_SERIAL_PORTA_FULL || CCW9C_SERIAL_PORTA_FULL) + def_bool y + help + This enables the video support for the VGA intrface. + +config NS9XXX_FB_LQ057Q3DC12I + bool "LQ057Q3DC12I TFT LCD support" + depends on ! (CC9P9360JS_SERIAL_PORTA_FULL || CCX9C_SERIAL_PORTA_FULL || CCW9C_SERIAL_PORTA_FULL) + help + This enables the support for the LQ057Q3DC12I TFT display. + +config NS9XXX_FB_LQ064V3DG01 + bool "LQ064V3DG01 TFT LCD support" + depends on ! (CC9P9360JS_SERIAL_PORTA_FULL || CCX9C_SERIAL_PORTA_FULL || CCW9C_SERIAL_PORTA_FULL) + help + This enables the support for the LQ064V3DG01 TFT display. + +config NS9XXX_FB_CUSTOM + bool "Custom display support" + depends on ! (CC9P9360JS_SERIAL_PORTA_FULL || CCX9C_SERIAL_PORTA_FULL || CCW9C_SERIAL_PORTA_FULL) + help + This enables the support for a customer specific display. + displays/CUSTOM.h has to be modified when selecting this. + +endif diff --git a/arch/arm/mach-ns9xxx/include/mach/display/LQ057Q3DC12I.h b/arch/arm/mach-ns9xxx/include/mach/display/LQ057Q3DC12I.h new file mode 100644 index 000000000000..afaf151cab2b --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/display/LQ057Q3DC12I.h @@ -0,0 +1,27 @@ + +#define LQ057Q3DC12I_DISPLAY \ +{ \ + .display_name = "LQ057Q3DC12I", \ + .width = 320, \ + .height = 240, \ + .control = LCD_CONTROL_WATERMARK | \ + LCD_CONTROL_PWR | \ + LCD_CONTROL_TFT | \ + LCD_CONTROL_BGR | \ + LCD_CONTROL_BPP_16 | \ + LCD_CONTROL_EN, \ + .timing = { \ + LCD_TIMING0_HBP(8) | \ + LCD_TIMING0_HFP(39) | \ + LCD_TIMING0_HSW(2) | \ + LCD_TIMING0_PPL(320 / 16 - 1),\ + LCD_TIMING1_VBP(6) | \ + LCD_TIMING1_VFP(5) | \ + LCD_TIMING1_VSW(0) | \ + LCD_TIMING1_LPP(240 - 1), \ + LCD_TIMING2_CPL(320 - 1) | \ + LCD_TIMING2_IHS | \ + LCD_TIMING2_IVS, \ + }, \ + .clock = 7000000, \ +} diff --git a/arch/arm/mach-ns9xxx/include/mach/display/LQ064V3DG01.h b/arch/arm/mach-ns9xxx/include/mach/display/LQ064V3DG01.h new file mode 100644 index 000000000000..e801e5f0766e --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/display/LQ064V3DG01.h @@ -0,0 +1,28 @@ + +#define LQ064V3DG01_DISPLAY \ +{ \ + .display_name = "LQ064V3DG01", \ + .width = 640, \ + .height = 480, \ + .control = LCD_CONTROL_WATERMARK | \ + LCD_CONTROL_PWR | \ + LCD_CONTROL_TFT | \ + LCD_CONTROL_BGR | \ + LCD_CONTROL_BPP_16 | \ + LCD_CONTROL_EN, \ + .timing = { \ + LCD_TIMING0_HBP(40) | \ + LCD_TIMING0_HFP(8) | \ + LCD_TIMING0_HSW(96) | \ + LCD_TIMING0_PPL(640 / 16 - 1),\ + LCD_TIMING1_VBP(31) | \ + LCD_TIMING1_VFP(2) | \ + LCD_TIMING1_VSW(2) | \ + LCD_TIMING1_LPP(480 - 1), \ + LCD_TIMING2_CPL(640 - 1) | \ + LCD_TIMING2_IPC | \ + LCD_TIMING2_IHS | \ + LCD_TIMING2_IVS, \ + }, \ + .clock = 28000000, \ +} diff --git a/arch/arm/mach-ns9xxx/include/mach/display/VGA.h b/arch/arm/mach-ns9xxx/include/mach/display/VGA.h new file mode 100644 index 000000000000..63f79f2440a6 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/display/VGA.h @@ -0,0 +1,29 @@ + +#define VGA_DISPLAY \ +{ \ + .display_name = "VGA", \ + .width = 640, \ + .height = 480, \ + .control = LCD_CONTROL_WATERMARK | \ + LCD_CONTROL_PWR | \ + LCD_CONTROL_TFT | \ + LCD_CONTROL_BGR | \ + LCD_CONTROL_BPP_16 | \ + LCD_CONTROL_EN, \ + .timing = { \ + LCD_TIMING0_HBP(40) | \ + LCD_TIMING0_HFP(8) | \ + LCD_TIMING0_HSW(96) | \ + LCD_TIMING0_PPL(640 / 16 - 1),\ + LCD_TIMING1_VBP(25) | \ + LCD_TIMING1_VFP(2) | \ + LCD_TIMING1_VSW(2) | \ + LCD_TIMING1_LPP(480 - 1), \ + LCD_TIMING2_CPL(640 - 1) | \ + LCD_TIMING2_BCD | \ + LCD_TIMING2_IPC | \ + LCD_TIMING2_IHS | \ + LCD_TIMING2_IVS, \ + }, \ + .clock = 0, /* external */ \ +} diff --git a/arch/arm/mach-ns9xxx/include/mach/display/displays.h b/arch/arm/mach-ns9xxx/include/mach/display/displays.h new file mode 100644 index 000000000000..5fa5ca1de4d6 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/display/displays.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-ns9xxx/displays/displays.h + * + * Copyright (C) 2009 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include <mach/ns9360fb.h> + +#if defined(CONFIG_NS9XXX_FB_VGA) +#include <mach/display/VGA.h> +#endif + +#if defined(CONFIG_NS9XXX_FB_LQ057Q3DC12I) +#include <mach/display/LQ057Q3DC12I.h> +#endif + +#if defined(CONFIG_NS9XXX_FB_LQ064V3DG01) +#include <mach/display/LQ064V3DG01.h> +#endif + +#if defined(CONFIG_NS9XXX_FB_CUSTOM) +#include <mach/display/CUSTOM.h> +#endif + +/* List of supported displays */ +struct ns9360fb_display display_list[] = { +#if defined(CONFIG_NS9XXX_FB_VGA) + VGA_DISPLAY, +#endif +#if defined(CONFIG_NS9XXX_FB_LQ057Q3DC12I) + LQ057Q3DC12I_DISPLAY, +#endif +#if defined(CONFIG_NS9XXX_FB_LQ064V3DG01) + LQ064V3DG01_DISPLAY, +#endif +#if defined(CONFIG_NS9XXX_FB_CUSTOM) + CUSTOM_DISPLAY, +#endif +}; + + diff --git a/arch/arm/mach-ns9xxx/include/mach/dma-ns921x.h b/arch/arm/mach-ns9xxx/include/mach/dma-ns921x.h new file mode 100644 index 000000000000..9fcbee4caa39 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/dma-ns921x.h @@ -0,0 +1,140 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/dma-ns921x.h + * + * Copyright (C) 2009 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + */ + + +#ifndef __ASM_ARCH_NS921X_DMA_H +#define __ASM_ARCH_NS921X_DMA_H + +#include <mach/hardware.h> + +/* External DMA control nad status registers. Valid channels are 1 and 2 */ +#define NS921X_DMA_BDP(x) __REG(0xa0800000 + ((x-1) & 0x1) * 0x10) +#define NS921X_DMA_CR(x) __REG(0xa0800004 + ((x-1) & 0x1) * 0x10) +#define NS921X_DMA_STIE(x) __REG(0xa0800008 + ((x-1) & 0x1) * 0x10) +#define NS921X_DMA_PCS(x) __REG(0xa080000c + ((x-1) & 0x1) * 0x10) + +/* Control register masks */ +#define NS921X_DMA_CR_CE (0x1 << 31) +#define NS921X_DMA_CR_CA (0x1 << 30) +#define NS921X_DMA_CR_CG (0x1 << 29) +#define NS921X_DMA_CR_SW_MA (0x3 << 27) +#define NS921X_DMA_CR_SW_8b (0x0 << 27) +#define NS921X_DMA_CR_SW_16b (0x1 << 27) +#define NS921X_DMA_CR_SW_32b (0x2 << 27) +#define NS921X_DMA_CR_DW_MA (0x3 << 25) +#define NS921X_DMA_CR_DW_8b (0x0 << 25) +#define NS921X_DMA_CR_DW_16b (0x1 << 25) +#define NS921X_DMA_CR_DW_32b (0x2 << 25) +#define NS921X_DMA_CR_SB_MA (0x3 << 23) +#define NS921X_DMA_CR_SB_1B (0x0 << 23) +#define NS921X_DMA_CR_SB_4B (0x1 << 23) +#define NS921X_DMA_CR_SB_16B (0x2 << 23) +#define NS921X_DMA_CR_SB_32B (0x3 << 23) +#define NS921X_DMA_CR_DB_MA (0x3 << 21) +#define NS921X_DMA_CR_DB_1B (0x0 << 21) +#define NS921X_DMA_CR_DB_4B (0x1 << 21) +#define NS921X_DMA_CR_DB_16B (0x2 << 21) +#define NS921X_DMA_CR_DB_32B (0x3 << 21) +#define NS921X_DMA_CR_SINC_N (0x1 << 20) +#define NS921X_DMA_CR_DINC_N (0x1 << 19) +#define NS921X_DMA_CR_POL (0x1 << 18) +#define NS921X_DMA_CR_MODE (0x1 << 17) +#define NS921X_DMA_CR_MODE_FBW (0x0 << 17) +#define NS921X_DMA_CR_MODE_FBR (0x1 << 17) +#define NS921X_DMA_CR_RESET (0x1 << 16) +#define NS921X_DMA_CR_STATE_MA (0x3f << 10) +#define NS921X_DMA_CR_INDEX_MA (0x3ff << 0) + +/* Status and interrupt enable masks */ +#define NS921X_DMA_STIE_NCIP (0x1 << 31) +#define NS921X_DMA_STIE_ECIP (0x1 << 30) +#define NS921X_DMA_STIE_NRIP (0x1 << 29) +#define NS921X_DMA_STIE_CAIP (0x1 << 28) +#define NS921X_DMA_STIE_PCIP (0x1 << 27) +#define NS921X_DMA_STIE_NCIE (0x1 << 24) +#define NS921X_DMA_STIE_ECIE (0x1 << 23) +#define NS921X_DMA_STIE_NRIE (0x1 << 22) +#define NS921X_DMA_STIE_CAIE (0x1 << 21) +#define NS921X_DMA_STIE_PCIE (0x1 << 20) +#define NS921X_DMA_STIE_IE_ALL (0x1f << 20) +#define NS921X_DMA_STIE_WRAP (0x1 << 19) +#define NS921X_DMA_STIE_DONE (0x1 << 18) +#define NS921X_DMA_STIE_LAST (0x1 << 17) +#define NS921X_DMA_STIE_FULL (0x1 << 16) +#define NS921X_DMA_STIE_BLEN_MA (0xffff << 0) + +/* Peripheral CS register */ +#define NS921X_DMA_PCS_SEL_MA (0x3 << 0) +#define NS921X_DMA_PCS_CS0 (0x0 << 0) +#define NS921X_DMA_PCS_CS1 (0x1 << 0) +#define NS921X_DMA_PCS_CS2 (0x2 << 0) +#define NS921X_DMA_PCS_CS3 (0x3 << 0) + +#define EXT_DMA_DESC_CTRL_WRAP (0x1 << 15) +#define EXT_DMA_DESC_CTRL_INT (0x1 << 14) +#define EXT_DMA_DESC_CTRL_LAST (0x1 << 13) +#define EXT_DMA_DESC_CTRL_FULL (0x1 << 12) +#define EXT_DMA_DESC_CTRL_ALL (EXT_DMA_DESC_CTRL_FULL | \ + EXT_DMA_DESC_CTRL_INT | \ + EXT_DMA_DESC_CTRL_LAST | \ + EXT_DMA_DESC_CTRL_WRAP) + +struct ext_dma_desc_t { + unsigned int src; + unsigned int length; + unsigned int dest; + unsigned short status; + unsigned short control; +}__attribute__((__packed__)); + + +/* + * IO-HUB constans and macros + * The maximal number of DMA-buffer descriptors comes from the NET+OS + * distribution (iop_private.h) + */ +#define IOHUB_MAX_DMA_BUFFERS (64) +#define IOHUB_MAX_DMA_LENGTH (65535) + +#define IOHUB_DMA_DESC_CTRL_WRAP EXT_DMA_DESC_CTRL_WRAP +#define IOHUB_DMA_DESC_CTRL_INT EXT_DMA_DESC_CTRL_INT +#define IOHUB_DMA_DESC_CTRL_LAST EXT_DMA_DESC_CTRL_LAST +#define IOHUB_DMA_DESC_CTRL_FULL EXT_DMA_DESC_CTRL_FULL +#define IOHUB_DMA_DESC_CTRL_ALL EXT_DMA_DESC_CTRL_ALL + +struct iohub_dma_desc_t { + unsigned int src; + unsigned int length; + unsigned int reserved; + unsigned short status; + unsigned short control; +}__attribute__((packed, aligned)); + + +#define IOHUB_DMA_DESC_LENGTH sizeof(struct iohub_dma_desc_t) + +/* This is the FIFO used for the DMA-transfers of the IOHUB (e.g. FIMs) */ +struct iohub_dma_fifo_t { + int length; + struct iohub_dma_desc_t **descs; + dma_addr_t phys_descs; + struct iohub_dma_desc_t *first; + struct iohub_dma_desc_t *last; + struct iohub_dma_desc_t *dma_first; + struct iohub_dma_desc_t *dma_last; + struct iohub_dma_desc_t *dma_next; + struct iohub_dma_desc_t *next_free; + unsigned long rx_error, tx_error; + unsigned long rx_error1, tx_error2; +}__attribute__((__packed__)); + +#endif /* ifndef __ASM_ARCH_NS912X_DMA_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/fim-firmware.h b/arch/arm/mach-ns9xxx/include/mach/fim-firmware.h new file mode 100644 index 000000000000..6bdd0e05333d --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/fim-firmware.h @@ -0,0 +1,101 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/fim-firmware.h + * + * Copyright (C) 2006 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * !Revision: $Revision: 1.0 $ + * !Author: Luis Galdos + * !Desc: + * !References: + */ + + +#ifndef _FIM_FIRMWARE_H +#define _FIM_FIRMWARE_H + + + +#define FIM_NUM_HWA_CONF_REGS (14) +#define FIM_NS9215_MAX_INSTRUCTIONS (1024) + + +typedef enum { + FIM_NS9215 = 0, +} fim_processors_t; + +#define PROCESSOR_TYPE_VALID(t) (t == FIM_NS9215) /* || (t == ADD_NEW_ONE_HERE) */ + + +typedef enum { + FIM_FORMAT_0 = 0, +} fim_formats_t; + +#define FORMAT_TYPE_VALID(t) (t == FIM_FORMAT_0) /* || (t == ADD_NEW_ONE_HERE) */ + +typedef enum { + FIM_PROCESSOR_PIC0, + FIM_PROCESSOR_PIC1 +} fim_processor_index_t; + +typedef enum { + FIM_HW_ASSIST_MODE_NONE, + FIM_HW_ASSIST_MODE_GENERIC, + FIM_HW_ASSIST_MODE_CAN, +} fim_hw_assit_t; + +typedef enum { + FIM_CLK_DIV_2, + FIM_CLK_DIV_4, + FIM_CLK_DIV_8, + FIM_CLK_DIV_16, + FIM_CLK_DIV_32, + FIM_CLK_DIV_64, + FIM_CLK_DIV_128, + FIM_CLK_DIV_256 +} fim_output_clk_div_t; + +typedef enum { + FIM_SIGBUS_SIGNAL_0, + FIM_SIGBUS_SIGNAL_1, + FIM_SIGBUS_SIGNAL_2, + FIM_SIGBUS_SIGNAL_3, + FIM_SIGBUS_SIGNAL_4, + FIM_SIGBUS_SIGNAL_5, + FIM_SIGBUS_SIGNAL_6, + FIM_SIGBUS_SIGNAL_7, + FIM_SIGBUS_CONTROL_0, + FIM_SIGBUS_CONTROL_1, + FIM_SIGBUS_CONTROL_2, + FIM_SIGBUS_CONTROL_3, + FIM_SIGBUS_16_BIT_BUS, + FIM_SIGBUS_24_BIT_BUS +} fim_signal_bus_t; + + + +/* + * The macro FIM_FIRMWARE_BUILDER is set by the build-system of the FIM-firmware + * See the Makefile under ../firmware/Makefile for more infos. + */ +struct fim_program_t { + fim_processors_t processor; + fim_formats_t format; + fim_hw_assit_t hw_mode; + fim_output_clk_div_t clkdiv; + unsigned int hwa_cfg[FIM_NUM_HWA_CONF_REGS]; + unsigned int length; +#ifndef FIM_FIRMWARE_BUILDER + unsigned short data[FIM_NS9215_MAX_INSTRUCTIONS]; +#endif +} __attribute__((packed, aligned)); + + +#endif /* _FIM_FIRMWARE_H */ + + + diff --git a/arch/arm/mach-ns9xxx/include/mach/fim-ns921x.h b/arch/arm/mach-ns9xxx/include/mach/fim-ns921x.h new file mode 100644 index 000000000000..6fbc61488f32 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/fim-ns921x.h @@ -0,0 +1,466 @@ +/* -*- linux-c -*- + * arch/arm/mach-ns9xxx/include/mach/fim-ns921x.h + * + * Copyright (C) 2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * !Revision: $Revision: 1.25 $ + * !Author: Silvano Najera, Luis Galdos + * !Descr: + * !References: + */ + + +#ifndef _NS921X_FIM_CORE_H +#define _NS921X_FIM_CORE_H + + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/firmware.h> +#include <linux/platform_device.h> +#include <linux/kfifo.h> +#include <linux/list.h> +#include <linux/interrupt.h> + +#include <mach/dma-ns921x.h> + + +#define FIM_MAX_FIRMWARE_NAME 32 + + +/* For DMA handling... */ +#define FIM_DMA_NCIP (0x1) +#define FIM_DMA_NRIP (0x2) +#define FIM_DMA_ECIP (0x4) +#define FIM_DMA_CAIP (0x8) +#define FIM_DMA_CANCELLED FIM_DMA_CAIP +#define FIM_DMA_FLUSHED (0x10) +#define FIM_DMA_SUCCESS (FIM_DMA_NCIP | FIM_DMA_NRIP) + + +#define FIM_MAX_PIC_INDEX (1) +#define FIM_MIN_PIC_INDEX (0) +#define FIM_NR_PICS (FIM_MAX_PIC_INDEX-FIM_MIN_PIC_INDEX+1) + + +/* @XXX: Place this macros in another place? */ +#define NS92XX_FIM_GEN_CTRL_STOP_PIC ~NS92XX_FIM_GEN_CTRL_PROGMEM +#define NS92XX_FIM_GEN_CTRL_START_PIC NS92XX_FIM_GEN_CTRL_PROGMEM + + + +/* Please note that the maximal DMA-buffer size is 64kB */ +/* @FIXME: Check that the maximal size of the descriptors is littler than one page */ +#define PIC_DMA_RX_BUFFERS (10) +#define PIC_DMA_TX_BUFFERS (10) +#define PIC_DMA_BUFFER_SIZE (1 * PAGE_SIZE) + +/* + * Internal structure for handling with the DMA-buffer descriptors + * p_desc : Physical descriptors address + * v_desc : Virtual access address for the descriptors + * v_buf : Virtual address of the memory buffers + * length : Configured length of this buffer + * tasked : Used for locking the descriptor + */ +struct pic_dma_desc_t { + dma_addr_t src; + size_t length; + atomic_t tasked; + void *private; + int total_length; +}; + + +/* + * Structure used by the FIM-API to configure the DMA-buffer and buffer-descriptors. + * rxnr : Number of RX-DMA-buffers + * rxsz : Size of each DMA-buffer (in Bytes) + * txnr : Number of TX-DMA-buffers + * txsz : Size for each TX-buffer (in Bytes) + */ +struct fim_dma_cfg_t { + int rxnr; + int rxsz; + int txnr; + int txsz; +}; + + +/* + * This structure should be used for transferring data with the API + * length : Date length to transfer + * data : Data buffer + * private : The API will not touch this pointer + * sent : The external driver can use it for waking up sleeping processes + */ +struct fim_buffer_t { + int length; + unsigned char *data; + void *private; + int sent; +}; + + +/* @TODO: We need perhaps another PIC-structure for the U-Boot */ +struct pic_t { + int irq; + struct device *dev; + struct fim_driver *driver; + void __iomem *reg_addr; + void __iomem *instr_addr; + void __iomem *hwa_addr; + void __iomem *iohub_addr; + spinlock_t lock; + int index; + atomic_t irq_enabled; + atomic_t requested; + + /* RX-DMA structures */ + struct iohub_dma_fifo_t rx_fifo; + spinlock_t rx_lock; + struct fim_dma_cfg_t dma_cfg; + + /* Variables for the DMA-memory buffers */ + dma_addr_t dma_phys; + void __iomem *dma_virt; + size_t dma_size; + + /* Data for the handling of the TX-DMA buffers */ + spinlock_t tx_lock; + struct pic_dma_desc_t *tx_desc; + struct iohub_dma_fifo_t tx_fifo; + atomic_t tx_tasked; + atomic_t tx_aborted; + struct tasklet_struct rx_tasklet; + + /* Info data for the sysfs */ + char fw_name[FIM_MAX_FIRMWARE_NAME]; + int fw_length; + + /* Functions for a low level access to the PICs */ + int (* is_running)(struct pic_t *); + int (* start_at_zero)(struct pic_t *); + int (* stop_and_reset)(struct pic_t *); + int (* download_firmware)(struct pic_t *, const unsigned char *); + int (* get_ctrl_reg)(struct pic_t *, int , unsigned int *); + void (* set_ctrl_reg)(struct pic_t *, int , unsigned int ); + int (* send_interrupt)(struct pic_t *, u32 ); + void (* ack_interrupt)(struct pic_t * , int ); +}; + + +/* + * Structure with the GPIOs to use for the driver to be initialized + * nr : GPIO number + * name : Name to use for the GPIO + * picval : Value to pass to the PIC-firmware + * func : Function to be configured for the GPIO + */ +struct fim_gpio_t { + int nr; + char *name; + unsigned char picval; /* Value to pass to firmware */ + unsigned int func; +}; + +#define FIM_LAST_GPIO -2 +#define FIM_GPIO_DONT_USE -1 + +/* + * Internal structure for allocating a FIM driver + * picnr : Number of the PIC to use for this driver + * fw_code : Firmware code that should be used as firmware + * fw_name : Name of the firmware to get over the firmware layer + * driver : Driver structure + * dev : Device that should be set by the FIM-API + * driver_data : The API will not touch this member + * fim_isr : Called when the PIC generates an interrupt + * dma_tx_isr : TX-callback function. Called in interrupt context + * dma_rx_isr : RX-callback. Called inside the interrupt context + * dma_cfg : If NULL then the API will use the default config + * verbose : Used by the FIM-core for printing sys messages (debug, infos, etc.) + */ +struct fim_driver { + int picnr; + const unsigned char *fw_code; + const char *fw_name; + struct device_driver driver; + struct device *dev; + void (*fim_isr)(struct fim_driver *, int, unsigned char, unsigned int); + void (*dma_tx_isr)(struct fim_driver *, int, struct fim_buffer_t *); + void (*dma_rx_isr)(struct fim_driver *, int, struct fim_buffer_t *); + void (*dma_error_isr)(struct fim_driver *, ulong rx_err, ulong tx_err); + void *driver_data; + struct fim_dma_cfg_t *dma_cfg; + int verbose; +}; + + + +/* + * Structure for the FIM-devices with UART-support + * If a GPIO should not be used, then it's required to disable it by using the + * above macro 'FIM_GPIO_DONT_USE' + * + * fim_nr : Number of the FIM to use for the device + * gpio_nr : GPIO to use for the interface line + * fim_cfg : Currently not used + */ +struct fim_serial_platform_data { + int fim_nr; + + int rx_gpio_nr; + unsigned int rx_gpio_func; + unsigned int rx_fim_cfg; + + int tx_gpio_nr; + unsigned int tx_gpio_func; + unsigned int tx_fim_cfg; + + int cts_gpio_nr; + unsigned int cts_gpio_func; + unsigned int cts_fim_cfg; + + int rts_gpio_nr; + unsigned int rts_gpio_func; + unsigned int rts_fim_cfg; +}; + + +/* Macro for the configuration of the GPIOs for the FIM-serial driver */ +#define NS921X_FIM_SERIAL_GPIOS(rx, tx, rts, cts, func) \ + .rx_gpio_nr = rx, \ + .rx_gpio_func = func, \ + .tx_gpio_nr = tx, \ + .tx_gpio_func = func, \ + .rts_gpio_nr = rts, \ + .rts_gpio_func = func, \ + .cts_gpio_nr = cts, \ + .cts_gpio_func = func + + +/* + * Structure for the FIM-devices with SDIO-support + * If a GPIO should not be used, then it's required to disable it by using the + * macro 'FIM_GPIO_DONT_USE' + * + * fim_nr : Number of the FIM to use for the device + * host_caps : Specific host capabilities (see: linux/mmc/host.h) + */ +struct fim_sdio_platform_data { + int fim_nr; + unsigned int host_caps; /* Host capabilities */ + + int d0_gpio_nr; /* data 0 */ + unsigned int d0_gpio_func; + int d1_gpio_nr; /* data 1 */ + unsigned int d1_gpio_func; + int d2_gpio_nr; /* data 2 */ + unsigned int d2_gpio_func; + int d3_gpio_nr; /* data 3 */ + unsigned int d3_gpio_func; + int wp_gpio_nr; /* write protect */ + unsigned int wp_gpio_func; + int cd_gpio_nr; /* card detect */ + unsigned int cd_gpio_func; + int clk_gpio_nr; /* clock */ + unsigned int clk_gpio_func; + int cmd_gpio_nr; /* command */ + unsigned int cmd_gpio_func; +}; + + +/* + * Use the below macro if all the GPIOs can be configured with the same function + * number (this is the normal case) + */ +#define NS921X_FIM_SDIO_GPIOS(d0, d1, d2, d3, wp, cd, clk, cmd, func) \ + .d0_gpio_nr = d0, \ + .d0_gpio_func = func, \ + .d1_gpio_nr = d1, \ + .d1_gpio_func = func, \ + .d2_gpio_nr = d2, \ + .d2_gpio_func = func, \ + .d3_gpio_nr = d3, \ + .d3_gpio_func = func, \ + .wp_gpio_nr = wp, \ + .wp_gpio_func = func, \ + .cd_gpio_nr = cd, \ + .cd_gpio_func = func, \ + .clk_gpio_nr = clk, \ + .clk_gpio_func = func, \ + .cmd_gpio_nr = cmd, \ + .cmd_gpio_func = func + +/* + * The new FIM board doesn't connect all the lines to the FIM. The CMD + * and CD are not connected to the FIM. + */ +#define NS921X_FIM_SDIO_GPIOS_FIM(d0, d1, d2, d3, clk, cmd, func) \ + .d0_gpio_nr = d0, \ + .d0_gpio_func = func, \ + .d1_gpio_nr = d1, \ + .d1_gpio_func = func, \ + .d2_gpio_nr = d2, \ + .d2_gpio_func = func, \ + .d3_gpio_nr = d3, \ + .d3_gpio_func = func, \ + .clk_gpio_nr = clk, \ + .clk_gpio_func = func, \ + .cmd_gpio_nr = cmd, \ + .cmd_gpio_func = func + +/* + * Structure for the FIM-devices with CAN-support + * If a GPIO should not be used, then it's required to disable it by using the + * above macro 'FIM_GPIO_DONT_USE' + * + * fim_nr : Number of the FIM to use for the device + * gpio_nr : GPIO to use for the interface line + */ +struct fim_can_platform_data { + + int fim_nr; + int fim_can_bitrate; + + int rx_gpio_nr; + unsigned int rx_gpio_func; + int tx_gpio_nr; + unsigned int tx_gpio_func; +}; + +/* Macro for the configuration of the GPIOs for the FIM CAN driver */ +#define NS921X_FIM_CAN_GPIOS(rx, tx, func) \ + .rx_gpio_nr = rx, \ + .rx_gpio_func = func, \ + .tx_gpio_nr = tx, \ + .tx_gpio_func = func + +/* + * Structure for the FIM-devices with USB support + * If a GPIO should not be used, then it's required to disable it by using the + * above macro 'FIM_GPIO_DONT_USE' + * + * fim_nr : Number of the FIM to use for the device + * gpio_nr : GPIO to use for the interface line + */ +struct fim_usb_platform_data { + + int fim_nr; + + int (*init)(struct device *); + int (*exit)(struct device *); + + int vp_gpio_nr; + unsigned int vp_gpio_func; + int vm_gpio_nr; + unsigned int vm_gpio_func; + int rcv_gpio_nr; + unsigned int rcv_gpio_func; + int oe_l_gpio_nr; + unsigned int oe_l_gpio_func; + int enum_gpio_nr; + unsigned int enum_gpio_func; + int spnd_gpio_nr; + unsigned int spnd_gpio_func; +}; + +/* + * Macro for the configuration of the GPIOs for the FIM USB driver + * IMPORTANT: The FIM-firmware is able to control the DP, DM, OE and RCV pins, but NOT + * the lines for the enumeration (ENUM) and suspend (SPND). The 'func_out' defines the + * function for the output GPIOs + */ +#define NS921X_FIM_USB_GPIOS(vp, vm, rcv, oe_l, enume, spnd, func, func_out) \ + .vp_gpio_nr = vp, \ + .vp_gpio_func = func, \ + .vm_gpio_nr = vm, \ + .vm_gpio_func = func, \ + .rcv_gpio_nr = rcv, \ + .rcv_gpio_func = func, \ + .oe_l_gpio_nr = oe_l, \ + .oe_l_gpio_func = func, \ + .enum_gpio_nr = enume, \ + .enum_gpio_func = func_out, \ + .spnd_gpio_nr = spnd, \ + .spnd_gpio_func = func_out + +/* Macros for building the FIM-drivers as loadable modules */ +#if defined(MODULE) +# define NS921X_FIM_NUMBERS_PARAM(number) \ + static int number = -1; \ + module_param_named(fims, number, int, 0644); +#else +# define NS921X_FIM_NUMBERS_PARAM(number) \ + static int number = FIM_NR_PICS; +#endif + +/* Call the function for checking the FIM module parameter */ +#if defined(MODULE) +inline int fim_check_numbers_param(int number) \ +{ \ + if (number < 0 || number > FIM_NR_PICS) \ + return -1; \ + else \ + return 0; \ +} +inline int fim_check_device_id(int number, uint id) { \ + int ret; \ + if (id < 0) \ + ret = 1; \ + else if (number == FIM_NR_PICS && id < number) \ + ret = 0; \ + else if (number < FIM_NR_PICS && id == number) \ + ret = 0; \ + else \ + ret = 1; \ + return ret; \ +} +#else +# define fim_check_numbers_param(number) (0) +# define fim_check_device_id(number, id) (id < 0 || id >= number) +#endif + +/* These are the functions of the FIM-API */ +int fim_register_driver(struct fim_driver *driver); +int fim_unregister_driver(struct fim_driver *driver); +int fim_send_interrupt2(struct fim_driver *driver, unsigned int code); +int fim_get_exp_reg(struct fim_driver *driver, int nr, unsigned int *value); +int fim_enable_irq(struct fim_driver *driver); +int fim_disable_irq(struct fim_driver *driver); +int fim_send_buffer(struct fim_driver *driver, const struct fim_buffer_t *bufdesc); +int fim_tx_buffers_room(struct fim_driver *driver); +int fim_tx_buffers_level(struct fim_driver *driver); +int fim_send_reset(struct fim_driver *driver); +int fim_send_start(struct fim_driver *driver); +int fim_send_stop(struct fim_driver *driver); +void fim_flush_rx(struct fim_driver *driver); +void fim_flush_tx(struct fim_driver *driver); +struct fim_buffer_t *fim_alloc_buffer(struct fim_driver *driver, int length, + unsigned int gfp_flags); +void fim_free_buffer(struct fim_driver *driver, struct fim_buffer_t *buffer); +void fim_set_ctrl_reg(struct fim_driver *driver, int reg, unsigned int val); +void fim_set_exp_reg(struct fim_driver *driver, int reg, unsigned int val); +int fim_get_ctrl_reg(struct fim_driver *driver, int reg, unsigned int *val); +int fim_get_stat_reg(struct fim_driver *driver, int reg, unsigned int *val); +struct pic_t *fim_request_pic(int picnr); +void fim_free_pic(struct pic_t *pic); +void fim_print_fifo_status(struct fim_driver *driver); +int fim_number_pics(void); +int fim_download_firmware(struct fim_driver *driver); +int fim_is_running(struct fim_driver *driver); + +int fim_dma_stop(struct fim_driver *fim); +int fim_dma_start(struct fim_driver *fim, struct fim_dma_cfg_t *cfg); + +#endif /* ifndef _NS921X_FIM_CORE_H */ + + + diff --git a/arch/arm/mach-ns9xxx/include/mach/fim-uncompress.h b/arch/arm/mach-ns9xxx/include/mach/fim-uncompress.h new file mode 100644 index 000000000000..0f77d72bbc5d --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/fim-uncompress.h @@ -0,0 +1,93 @@ +/* -*- linux-c -*- + * + * arch/arm/mach-ns9xxx/include/mach/fim-uncompress.h + * + * Copyright (C) 2009 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * !Authors: Hector Palacios, Luis Galdos + * !Desc: + * !References: + */ + +#ifndef __FIM_UNCROMPRESS_H +#define __FIM_UNCROMPRESS_H + +#include <asm/io.h> + +#define NS921X_FIM0 __REG(0x90000000) +#define NS921X_FIM1 __REG(0x90008000) + +#define FIM_SERIAL_DATA_BITS (8) + +#define NS92XX_FIM_CTRL0_REG (0x10) +#define NS92XX_FIM_EXP0_REG (0x50) +#define NS92XX_FIM_CTRL_REG(i) (NS92XX_FIM_CTRL0_REG + 4*i) +#define NS92XX_FIM_EXP_REG(i) (NS92XX_FIM_EXP0_REG + 4*i) + +#define NS92XX_FIM_REG_BASE_PA (0x90001000) +#define NS92XX_FIM_REG_BASE_PA (0x90001000) +#define NS92XX_FIM_REG_OFFSET (0x8000) +#define FIM_REG_ADDR(x) (NS92XX_FIM_REG_BASE_PA + \ + (x * NS92XX_FIM_REG_OFFSET)) +#define NS921X_FIM_ENABLED(base) (__raw_readl((base) + 0x1000) \ + & (1 << 31)) +#define NS92XX_FIM_GEN_CTRL_REG (0x00) +#define NS92XX_FIM_GEN_CTRL_INTTOPIC (0x00007f00) +#define NS92XX_FIM_GEN_CTRL_INTACKRD (0x00000080) +#define NS92XX_FIM_INT_MASK(code) (code<<8) + +#define FIM_SERIAL_INT_INSERT_CHAR (0x01) + +static int fim_send_interrupt(int pic_num, unsigned int code) +{ + unsigned int stopcnt; + u32 status; + + code = NS92XX_FIM_INT_MASK(code); + status = readl(FIM_REG_ADDR(pic_num) + NS92XX_FIM_GEN_CTRL_REG); + writel(status | code, FIM_REG_ADDR(pic_num) + NS92XX_FIM_GEN_CTRL_REG); + + /* This loop is perhaps problematic, exit with a timeout */ + stopcnt = 0xFFFF; + do { + status = readl(FIM_REG_ADDR(pic_num) + NS92XX_FIM_GEN_CTRL_REG); + stopcnt--; + } while (!(status & NS92XX_FIM_GEN_CTRL_INTACKRD) && stopcnt); + + if (!stopcnt) { + return 1; + } + + /* Reset the interrupt bits for the PIC acknowledge */ + status &= ~NS92XX_FIM_GEN_CTRL_INTTOPIC; + writel(status, FIM_REG_ADDR(pic_num) + NS92XX_FIM_GEN_CTRL_REG); + + stopcnt = 0xFFFF; + do { + status = readl(FIM_REG_ADDR(pic_num) + NS92XX_FIM_GEN_CTRL_REG); + stopcnt--; + } while ((status & NS92XX_FIM_GEN_CTRL_INTACKRD) && stopcnt); + + if (!stopcnt) { + return 1; + } + + return 0; +} + +static void fim_set_ctrl_reg(int pic_num, int reg, unsigned int val) +{ + writel(val, FIM_REG_ADDR(pic_num) + NS92XX_FIM_CTRL_REG(reg)); +} + +static int fim_get_exp_reg(int pic_num, int nr) +{ + return readl(FIM_REG_ADDR(pic_num) + NS92XX_FIM_EXP_REG(nr)); +} + +#endif /* __FIM_UNCROMPRESS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h index 5eb349032579..40e246dabdcc 100644 --- a/arch/arm/mach-ns9xxx/include/mach/gpio.h +++ b/arch/arm/mach-ns9xxx/include/mach/gpio.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-ns9xxx/include/mach/gpio.h * - * Copyright (C) 2007 by Digi International Inc. + * Copyright (C) 2007,2008 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -11,21 +11,457 @@ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H +#include <linux/spinlock.h> #include <asm/errno.h> +#include <asm/io.h> +#include <mach/hardware.h> +#include <mach/processor.h> -int gpio_request(unsigned gpio, const char *label); +#include <mach/regs-io-ns921x.h> +#include <mach/regs-bbu.h> + + +/* Macros for configuring the GPIO-functions */ +#if defined(CONFIG_PROCESSOR_NS9210) || defined(CONFIG_PROCESSOR_NS9215) +# define NS921X_GPIO_FUNC_0 (0x00) +# define NS921X_GPIO_FUNC_1 (0x01) +# define NS921X_GPIO_FUNC_2 (0x02) +# define NS921X_GPIO_FUNC_3 (0x03) +# define NS921X_GPIO_FUNC_4 (0x04) + +# define NS921X_GPIO_FUNC_GPIO NS921X_GPIO_FUNC_3 + +# define NS921X_GPIO_INPUT (0x00) +# define NS921X_GPIO_OUTPUT (0x01) + +# define NS921X_GPIO_INVERT (0x01) +# define NS921X_GPIO_DONT_INVERT (0x00) + +# define NS921X_GPIO_ENABLE_PULLUP (0x00) +# define NS921X_GPIO_DISABLE_PULLUP (0x01) +#endif + +/* Macros for configuring the GPIO-functions */ +#if defined(CONFIG_PROCESSOR_NS9360) +# define NS9360_GPIO_FUNC_0 (0x00) +# define NS9360_GPIO_FUNC_1 (0x01) +# define NS9360_GPIO_FUNC_2 (0x02) +# define NS9360_GPIO_FUNC_3 (0x03) +# define NS9360_GPIO_FUNC_4 (0x04) + +# define NS9360_GPIO_FUNC_GPIO NS9360_GPIO_FUNC_3 + +# define NS9360_GPIO_INPUT (0x00) +# define NS9360_GPIO_OUTPUT (0x01) + +# define NS9360_GPIO_INVERT (0x01) +# define NS9360_GPIO_DONT_INVERT (0x00) +#endif + + +struct gpio_to_irq_map { + unsigned gpio; + unsigned irq; + int func; +}; + +#define NS9XXX_NUM_GPIO 0 + +#if defined(CONFIG_PROCESSOR_NS9210) +# define NS9XXX_NUM_GPIO_NS9210 108 +# if NS9XXX_NUM_GPIO < NS9XXX_NUM_GPIO_NS9210 +# undef NS9XXX_NUM_GPIO +# define NS9XXX_NUM_GPIO NS9XXX_NUM_GPIO_NS9210 +# endif +static inline int gpio_issocgpio_ns9210(unsigned gpio) +{ + return gpio < NS9XXX_NUM_GPIO_NS9210 && !(gpio >= 50 && gpio < 105); +} +#endif + +#if defined(CONFIG_PROCESSOR_NS9215) +# define NS9XXX_NUM_GPIO_NS9215 108 +# if NS9XXX_NUM_GPIO < NS9XXX_NUM_GPIO_NS9215 +# undef NS9XXX_NUM_GPIO +# define NS9XXX_NUM_GPIO NS9XXX_NUM_GPIO_NS9215 +# endif +static inline int gpio_issocgpio_ns9215(unsigned gpio) +{ + return gpio < NS9XXX_NUM_GPIO_NS9215; +} +#endif + +static const inline struct gpio_to_irq_map *gpio_get_map(unsigned gpio, + const struct gpio_to_irq_map map[], size_t array_size) +{ + /* TODO: check if a binary search yields some performance advantage */ + int i; + + for (i = 0; i < array_size; ++i) { + if (map[i].gpio == gpio) + return &map[i]; + } + + return NULL; +} + +#if defined(CONFIG_PROCESSOR_NS921X) +const struct gpio_to_irq_map *gpio_get_map_ns921x(unsigned gpio) __attribute__((const)); + +static inline void gpio_configure_ns921x_unlocked(unsigned gpio, + int dir, int inv, int func, int dispullup) +{ + void __iomem *conf = NS921X_IO_GPIOCONFx(gpio / 4); + u32 confval; + + confval = __raw_readl(conf); + REGSETIM_IDX(confval, NS921X_IO_GPIOCONFx, DIR, gpio & 3, dir); + REGSETIM_IDX(confval, NS921X_IO_GPIOCONFx, INV, gpio & 3, inv); + REGSETIM_IDX(confval, NS921X_IO_GPIOCONFx, FUNC, gpio & 3, func); + if (gpio != 9 && gpio != 12 && (gpio < 102 || gpio > 105)) + REGSETIM_IDX(confval, NS921X_IO_GPIOCONFx, PUEN, gpio & 3, dispullup); + else { + if (dispullup) + pr_warning("cannot disable pullup for gpio %u\n", gpio); + + REGSETIM_IDX(confval, NS921X_IO_GPIOCONFx, PUEN, gpio & 3, 0); + } + + __raw_writel(confval, conf); +} + +static inline void gpio_configure_ns921x(unsigned gpio, + int dir, int inv, int func, int dispullup) +{ + unsigned long flags; + + local_irq_save(flags); + + gpio_configure_ns921x_unlocked(gpio, dir, inv, func, dispullup); + + local_irq_restore(flags); +} + +static inline int gpio_get_value_ns921x(unsigned gpio) +{ + void __iomem *stat = NS921X_IO_GPIOSTATx(gpio / 32); + + return (__raw_readl(stat) >> (gpio & 31)) & 1; +} + +static inline void gpio_set_value_ns921x_unlocked(unsigned gpio, int value) +{ + void __iomem *ctrl = NS921X_IO_GPIOCTRLx(gpio / 32); + u32 ctrlval; + + ctrlval = __raw_readl(ctrl); + + if (value) + ctrlval |= 1 << (gpio & 31); + else + ctrlval &= ~(1 << (gpio & 31)); + + __raw_writel(ctrlval, ctrl); +} + +static inline int gpio_direction_input_ns921x_unlocked(unsigned gpio) +{ + gpio_configure_ns921x_unlocked(gpio, 0, 0, 3, 0); + return 0; +} + +static inline int gpio_direction_irqinput_ns921x_unlocked(unsigned gpio) +{ + const struct gpio_to_irq_map *map = gpio_get_map_ns921x(gpio); + + if (map) { + gpio_configure_ns921x_unlocked(gpio, 0, 0, map->func, 0); + return 0; + } else + return gpio_direction_input_ns921x_unlocked(gpio); +} + +static inline int gpio_direction_output_ns921x_unlocked(unsigned gpio, + int value) +{ + gpio_set_value_ns921x_unlocked(gpio, value); + gpio_configure_ns921x_unlocked(gpio, 1, 0, 3, 0); + return 0; +} + +#endif /* if defined(CONFIG_PROCESSOR_NS921X) */ + +#if defined(CONFIG_PROCESSOR_NS9360) +# define NS9XXX_NUM_GPIO_NS9360 73 +# if NS9XXX_NUM_GPIO < NS9XXX_NUM_GPIO_NS9360 +# undef NS9XXX_NUM_GPIO +# define NS9XXX_NUM_GPIO NS9XXX_NUM_GPIO_NS9360 +# endif +static inline void __iomem *gpio_ns9360_gstataddr(unsigned gpio) +{ + if (gpio < 32) + return NS9360_BBU_GSTAT1; + else if (gpio < 64) + return NS9360_BBU_GSTAT2; + else + return NS9360_BBU_GSTAT3; +} + +static inline void __iomem *gpio_ns9360_gctrladdr(unsigned gpio) +{ + if (gpio < 32) + return NS9360_BBU_GCTRL1; + else if (gpio < 64) + return NS9360_BBU_GCTRL2; + else + return NS9360_BBU_GCTRL3; +} + +static inline void __iomem *gpio_ns9360_gconfaddr(unsigned gpio) +{ + if (gpio < 56) + return NS9360_BBU_GCONFb1(gpio / 8); + else + /* this could be optimised away on + * ns9750 only builds, but it isn't ... + */ + return NS9360_BBU_GCONFb2((gpio - 56) / 8); +} + +static inline int gpio_issocgpio_ns9360(unsigned gpio) +{ + return gpio <= 72; +} + +const struct gpio_to_irq_map *gpio_get_map_ns9360(unsigned gpio) __attribute__((const)); + +static inline void gpio_configure_ns9360_unlocked(unsigned gpio, + int dir, int inv, int func) +{ + void __iomem *conf = gpio_ns9360_gconfaddr(gpio); + u32 confval; + + confval = __raw_readl(conf); + REGSETIM_IDX(confval, NS9360_BBU_GCONFx, DIR, gpio & 7, dir); + REGSETIM_IDX(confval, NS9360_BBU_GCONFx, INV, gpio & 7, inv); + REGSETIM_IDX(confval, NS9360_BBU_GCONFx, FUNC, gpio & 7, func); + __raw_writel(confval, conf); +} + +static inline void gpio_configure_ns9360(unsigned gpio, + int dir, int inv, int func) +{ + unsigned long flags; + + local_irq_save(flags); + + gpio_configure_ns9360_unlocked(gpio, dir, inv, func); + + local_irq_restore(flags); +} + +static inline int gpio_get_value_ns9360(unsigned gpio) +{ + void __iomem *stat = gpio_ns9360_gstataddr(gpio); + + return (__raw_readl(stat) >> (gpio & 31)) & 1; +} + +static inline void gpio_set_value_ns9360_unlocked(unsigned gpio, int value) +{ + void __iomem *ctrl = gpio_ns9360_gctrladdr(gpio); + u32 ctrlval; + + ctrlval = __raw_readl(ctrl); + + if (value) + ctrlval |= 1 << (gpio & 31); + else + ctrlval &= ~(1 << (gpio & 31)); + + __raw_writel(ctrlval, ctrl); +} + +static inline int gpio_direction_input_ns9360_unlocked(unsigned gpio) +{ + gpio_configure_ns9360_unlocked(gpio, 0, 0, 3); + return 0; +} + +static inline int gpio_direction_irqinput_ns9360_unlocked(unsigned gpio) +{ + const struct gpio_to_irq_map *map = gpio_get_map_ns9360(gpio); + if (map) { + gpio_configure_ns9360_unlocked(gpio, 0, 0, map->func); + return 0; + } else + return gpio_direction_input_ns9360_unlocked(gpio); +} + +static inline int gpio_direction_output_ns9360_unlocked(unsigned gpio, + int value) +{ + gpio_set_value_ns9360_unlocked(gpio, value); + gpio_configure_ns9360_unlocked(gpio, 1, 0, 3); + return 0; +} + +#endif /* if defined(CONFIG_PROCESSOR_NS9360) */ + +static inline int gpio_issocgpio(unsigned gpio) +{ +#if defined(CONFIG_PROCESSOR_NS9210) + if (processor_is_ns9210()) + return gpio_issocgpio_ns9210(gpio); + else +#endif +#if defined(CONFIG_PROCESSOR_NS9215) + if (processor_is_ns9215()) + return gpio_issocgpio_ns9215(gpio); + else +#endif +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + return gpio_issocgpio_ns9360(gpio); + else +#endif + BUG(); + + BUG(); + + return 0; +} + +#if defined(CONFIG_GPIOLIB) + +#include <asm-generic/gpio.h> + +static inline int gpio_get_value(unsigned gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + return __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + return __gpio_cansleep(gpio); +} + +#else /* if defined(CONFIG_GPIOLIB) */ + +extern spinlock_t gpio_lock; + +int gpio_request(unsigned gpio, const char *label); void gpio_free(unsigned gpio); -int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); +static inline int gpio_get_value(unsigned gpio) +{ +#if defined(CONFIG_PROCESSOR_NS921X) + if (processor_is_ns921x()) + return gpio_get_value_ns921x(gpio); + else +#endif +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + return gpio_get_value_ns9360(gpio); + else +#endif + BUG(); +} + +static inline void gpio_set_value_unlocked(unsigned gpio, int value) +{ +#if defined(CONFIG_PROCESSOR_NS921X) + if (processor_is_ns921x()) + gpio_set_value_ns921x_unlocked(gpio, value); + else +#endif +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + gpio_set_value_ns9360_unlocked(gpio, value); + else +#endif + BUG(); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + unsigned long flags; + + BUG_ON(!gpio_issocgpio(gpio)); + + spin_lock_irqsave(&gpio_lock, flags); + + gpio_set_value_unlocked(gpio, value); + + spin_unlock_irqrestore(&gpio_lock, flags); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + if (likely(gpio_issocgpio(gpio))) { + int ret = -EINVAL; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + +#if defined(CONFIG_PROCESSOR_NS921X) + if (processor_is_ns921x()) + ret = gpio_direction_irqinput_ns921x_unlocked(gpio); + else +#endif +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + ret = gpio_direction_irqinput_ns9360_unlocked(gpio); + else +#endif + BUG(); + + spin_unlock_irqrestore(&gpio_lock, flags); -int gpio_direction_input(unsigned gpio); + return ret; + } else + return -EINVAL; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + if (likely(gpio_issocgpio(gpio))) { + int ret = -EINVAL; + unsigned long flags; -int gpio_direction_output(unsigned gpio, int value); + spin_lock_irqsave(&gpio_lock, flags); -int gpio_get_value(unsigned gpio); +#if defined(CONFIG_PROCESSOR_NS921X) + if (processor_is_ns921x()) + ret = gpio_direction_output_ns921x_unlocked(gpio, + value); + else +#endif +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + ret = gpio_direction_output_ns9360_unlocked(gpio, + value); + else +#endif + BUG(); + + spin_unlock_irqrestore(&gpio_lock, flags); + + return ret; + } else + return -EINVAL; +} + +#include <asm-generic/gpio.h> + +#endif /* if defined(CONFIG_GPIOLIB) / else */ -void gpio_set_value(unsigned gpio, int value); /* * ns9xxx can use gpio pins to trigger an irq, but it's not generic @@ -33,6 +469,23 @@ void gpio_set_value(unsigned gpio, int value); */ static inline int gpio_to_irq(unsigned gpio) { +#if defined(CONFIG_PROCESSOR_NS921X) + if (processor_is_ns921x()) { + const struct gpio_to_irq_map *map = gpio_get_map_ns921x(gpio); + + if (map) + return map->irq; + } +#endif +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) { + const struct gpio_to_irq_map *map = gpio_get_map_ns9360(gpio); + + if (map) + return map->irq; + } +#endif + return -EINVAL; } @@ -41,7 +494,4 @@ static inline int irq_to_gpio(unsigned irq) return -EINVAL; } -/* get the cansleep() stubs */ -#include <asm-generic/gpio.h> - #endif /* ifndef __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h index 6dbb2030f563..46299b18433e 100644 --- a/arch/arm/mach-ns9xxx/include/mach/hardware.h +++ b/arch/arm/mach-ns9xxx/include/mach/hardware.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-ns9xxx/include/mach/hardware.h * - * Copyright (C) 2006 by Digi International Inc. + * Copyright (C) 2006-2008 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -30,7 +30,9 @@ #define __REGSHIFT(mask) ((mask) & (-(mask))) #define __REGBIT(bit) ((u32)1 << (bit)) +#define __REGBIT_SHIFT(bit, shift) ((u32)1 << ((bit) + (shift))) #define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) +#define __REGBITS_SHIFT(hbit, lbit, shift) __REGBITS((hbit) + (shift), (lbit) + (shift)) #define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) #ifndef __ASSEMBLY__ @@ -66,13 +68,13 @@ __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) # define REGGETIM_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) / \ + __REGGET(var, reg ## _ ## field((idx))) / \ __REGSHIFT(reg ## _ ## field((idx))) #else # define __REG(x) io_p2v(x) -# define __REG2(x, y) io_p2v((x) + 4 * (y)) +# define __REG2(x, y) io_p2v((x) + (y)) #endif diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h index 13483949e210..f72bd08e5de9 100644 --- a/arch/arm/mach-ns9xxx/include/mach/irqs.h +++ b/arch/arm/mach-ns9xxx/include/mach/irqs.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-ns9xxx/include/mach/irqs.h * - * Copyright (C) 2006,2007 by Digi International Inc. + * Copyright (C) 2006-2008 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -11,14 +11,48 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -/* NetSilicon 9360 */ +/* Digi ns921x */ #define IRQ_NS9XXX_WATCHDOG 0 #define IRQ_NS9XXX_AHBBUSERR 1 -#define IRQ_NS9360_BBUSAGG 2 -/* irq 3 is reserved for NS9360 */ +#define IRQ_NS921X_EXTDMA 2 +#define IRQ_NS921X_CPUWAKE 3 #define IRQ_NS9XXX_ETHRX 4 #define IRQ_NS9XXX_ETHTX 5 -#define IRQ_NS9XXX_ETHPHY 6 +#define IRQ_NS9XXX_ETHPHY 6 /* reserved for ns9210 */ +#define IRQ_NS921X_UARTA 7 +#define IRQ_NS921X_UARTB 8 +#define IRQ_NS921X_UARTC 9 +#define IRQ_NS921X_UARTD 10 +#define IRQ_NS921X_SPI 11 +#define IRQ_NS921X_PIC0 12 +#define IRQ_NS921X_PIC1 13 +#define IRQ_NS9215_ADC 14 +#define IRQ_NS9215_EPL 15 +#define IRQ_NS921X_I2C 16 +#define IRQ_NS9215_RTC 17 +#define IRQ_NS921X_TIMER0 18 +#define IRQ_NS921X_TIMER1 19 +#define IRQ_NS921X_TIMER2 20 +#define IRQ_NS921X_TIMER3 21 +#define IRQ_NS921X_TIMER4 22 +#define IRQ_NS921X_TIMER5 23 +#define IRQ_NS921X_TIMER6 24 +#define IRQ_NS921X_TIMER7 25 +#define IRQ_NS921X_TIMER8 26 +#define IRQ_NS921X_TIMER9 27 +#define IRQ_NS9XXX_EXT0 28 +#define IRQ_NS9XXX_EXT1 29 +#define IRQ_NS9XXX_EXT2 30 +#define IRQ_NS9XXX_EXT3 31 + +/* NetSilicon 9360 */ +/* IRQ_NS9XXX_WATCHDOG 0 */ +/* IRQ_NS9XXX_AHBBUSERR 1 */ +#define IRQ_NS9360_BBUSAGG 2 +/* irq 3 is reserved for NS9360 */ +/* IRQ_NS9XXX_ETHRX 3 */ +/* IRQ_NS9XXX_ETHTX 4 */ +/* IRQ_NS9XXX_ETHPHY 5 */ #define IRQ_NS9360_LCD 7 #define IRQ_NS9360_SERBRX 8 #define IRQ_NS9360_SERBTX 9 @@ -40,37 +74,39 @@ #define IRQ_NS9360_USBHOST 25 #define IRQ_NS9360_USBDEVICE 26 #define IRQ_NS9360_IEEE1284 27 -#define IRQ_NS9XXX_EXT0 28 -#define IRQ_NS9XXX_EXT1 29 -#define IRQ_NS9XXX_EXT2 30 -#define IRQ_NS9XXX_EXT3 31 +/* IRQ_NS9XXX_EXT0 28 */ +/* IRQ_NS9XXX_EXT1 29 */ +/* IRQ_NS9XXX_EXT2 30 */ +/* IRQ_NS9XXX_EXT3 31 */ + +#define IRQ_NS9360_BBUS(irq) (32 + irq) -#define BBUS_IRQ(irq) (32 + irq) +#define IRQ_NS9360_BBUS_DMA IRQ_NS9360_BBUS(0) +#define IRQ_NS9360_BBUS_SERBRX IRQ_NS9360_BBUS(2) +#define IRQ_NS9360_BBUS_SERBTX IRQ_NS9360_BBUS(3) +#define IRQ_NS9360_BBUS_SERARX IRQ_NS9360_BBUS(4) +#define IRQ_NS9360_BBUS_SERATX IRQ_NS9360_BBUS(5) +#define IRQ_NS9360_BBUS_SERCRX IRQ_NS9360_BBUS(6) +#define IRQ_NS9360_BBUS_SERCTX IRQ_NS9360_BBUS(7) +#define IRQ_NS9360_BBUS_SERDRX IRQ_NS9360_BBUS(8) +#define IRQ_NS9360_BBUS_SERDTX IRQ_NS9360_BBUS(9) +#define IRQ_NS9360_BBUS_I2C IRQ_NS9360_BBUS(10) +#define IRQ_NS9360_BBUS_1284 IRQ_NS9360_BBUS(11) +#define IRQ_NS9360_BBUS_UTIL IRQ_NS9360_BBUS(12) +#define IRQ_NS9360_BBUS_RTC IRQ_NS9360_BBUS(13) +#define IRQ_NS9360_BBUS_USBHST IRQ_NS9360_BBUS(14) +#define IRQ_NS9360_BBUS_USBDEV IRQ_NS9360_BBUS(15) +#define IRQ_NS9360_BBUS_AHBDMA1 IRQ_NS9360_BBUS(24) +#define IRQ_NS9360_BBUS_AHBDMA2 IRQ_NS9360_BBUS(25) -#define IRQ_BBUS_DMA BBUS_IRQ(0) -#define IRQ_BBUS_SERBRX BBUS_IRQ(2) -#define IRQ_BBUS_SERBTX BBUS_IRQ(3) -#define IRQ_BBUS_SERARX BBUS_IRQ(4) -#define IRQ_BBUS_SERATX BBUS_IRQ(5) -#define IRQ_BBUS_SERCRX BBUS_IRQ(6) -#define IRQ_BBUS_SERCTX BBUS_IRQ(7) -#define IRQ_BBUS_SERDRX BBUS_IRQ(8) -#define IRQ_BBUS_SERDTX BBUS_IRQ(9) -#define IRQ_BBUS_I2C BBUS_IRQ(10) -#define IRQ_BBUS_1284 BBUS_IRQ(11) -#define IRQ_BBUS_UTIL BBUS_IRQ(12) -#define IRQ_BBUS_RTC BBUS_IRQ(13) -#define IRQ_BBUS_USBHST BBUS_IRQ(14) -#define IRQ_BBUS_USBDEV BBUS_IRQ(15) -#define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24) -#define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25) +#define IRQ_NS9360_BBUDMA(irq) (58 + irq) /* * these Interrupts are specific for the a9m9750dev board. * They are generated by an FPGA that interrupts the CPU on * IRQ_NS9360_EXT2 */ -#define FPGA_IRQ(irq) (64 + irq) +#define FPGA_IRQ(irq) (74 + irq) #define IRQ_FPGA_UARTA FPGA_IRQ(0) #define IRQ_FPGA_UARTB FPGA_IRQ(1) @@ -81,6 +117,6 @@ #define IRQ_FPGA_CAN0 FPGA_IRQ(6) #define IRQ_FPGA_CAN1 FPGA_IRQ(7) -#define NR_IRQS 72 +#define NR_IRQS 82 #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h index f851a6b7da6c..6c497bf87084 100644 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ b/arch/arm/mach-ns9xxx/include/mach/module.h @@ -31,6 +31,11 @@ || machine_is_cc9p9215js() \ ) +#define module_is_ccw9p9215() (0 \ + || machine_is_ccw9p9215() \ + || machine_is_ccw9p9215js() \ + ) + #define module_is_cc9p9360() (0 \ || machine_is_a9m9360() \ || machine_is_cc9p9360dev() \ @@ -49,6 +54,11 @@ || machine_is_ccw9c() \ ) +#define module_is_cme9210() (0 \ + || machine_is_cme9210() \ + || machine_is_cme9210js() \ + ) + #define module_is_inc20otter() (0 \ || machine_is_inc20otter() \ ) diff --git a/arch/arm/mach-ns9xxx/include/mach/ns921x-serial.h b/arch/arm/mach-ns9xxx/include/mach/ns921x-serial.h new file mode 100644 index 000000000000..e879492fe10a --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/ns921x-serial.h @@ -0,0 +1,22 @@ +/* + * include/linux/ns9360.h + * + * Copyright (C) 2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef __NS921X_SERIAL_H__ +#define __NS921X_SERIAL_H__ + + +struct ns921x_uart_data { + unsigned int gpios[8]; + unsigned int nr_gpios; + unsigned int rtsen; /* RTS for 485 transceiver control */ +}; + +#endif diff --git a/arch/arm/mach-ns9xxx/include/mach/ns9360fb.h b/arch/arm/mach-ns9xxx/include/mach/ns9360fb.h new file mode 100644 index 000000000000..cacb56c17997 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/ns9360fb.h @@ -0,0 +1,26 @@ +#ifndef __NS9360FB_H__ +#define __NS9360FB_H__ + + +struct ns9360fb_display { + + /* Display name */ + char *display_name; + + unsigned height; + unsigned width; + unsigned clock; + + u32 timing[4]; + u32 control; + + void (*display_power_enable)(int); +}; + +struct ns9360fb_pdata { + unsigned num_displays; /* number of defined displays */ + struct ns9360fb_display *displays; /* attached diplays info */ + struct ns9360fb_display *display; /* attached diplays info */ +}; + +#endif diff --git a/arch/arm/mach-ns9xxx/include/mach/ns9xxx-pwm.h b/arch/arm/mach-ns9xxx/include/mach/ns9xxx-pwm.h new file mode 100644 index 000000000000..b48527482cd3 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/ns9xxx-pwm.h @@ -0,0 +1,146 @@ +/* + * drivers/pwm/ns9xxx-pwm.h + * + * Copyright (C) 2009 Digi International Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __NS9XXX_PWM_HEADER_H +#define __NS9XXX_PWM_HEADER_H + +/* Maximal number of available channels */ +#define NS9XXX_PWM_CHANNEL_MAX 10 + +/* This is the data for the PWM channels */ +struct ns9xxx_pwm_channel { + int timer; + int gpio; + + /* Additional channel configuration variables ... */ +}; + +/* */ +struct ns9xxx_pwm_pdata { + unsigned int number_channels; + struct ns9xxx_pwm_channel *channels; +}; + + + + +#define NS921X_TMC_T0E (1 << 0) /* Timer enable */ +#define NS921X_TMC_T1E (1 << 1) +#define NS921X_TMC_T2E (1 << 2) +#define NS921X_TMC_T3E (1 << 3) +#define NS921X_TMC_T4E (1 << 4) +#define NS921X_TMC_T5E (1 << 5) +#define NS921X_TMC_T6E (1 << 6) +#define NS921X_TMC_T7E (1 << 7) +#define NS921X_TMC_T8E (1 << 8) +#define NS921X_TMC_T9E (1 << 9) +#define NS921X_TMC_T6HSE (1 << 10) /* High step enable */ +#define NS921X_TMC_T6LSE (1 << 11) /* Low step enable */ +#define NS921X_TMC_T6RSE (1 << 12) /* Reload step enable */ +#define NS921X_TMC_T7HSE (1 << 13) +#define NS921X_TMC_T7LSE (1 << 14) +#define NS921X_TMC_T7RSE (1 << 15) +#define NS921X_TMC_T8HSE (1 << 16) +#define NS921X_TMC_T8LSE (1 << 17) +#define NS921X_TMC_T8RSE (1 << 18) +#define NS921X_TMC_T9HSE (1 << 19) +#define NS921X_TMC_T9LSE (1 << 20) +#define NS921X_TMC_T9RSE (1 << 21) + +#define NS921X_TCR_RELOADEN (1 << 0) /* Reload enable */ +#define NS921X_TCR_BITTIMER (1 << 1) /* 32 or 16 bit timer */ +#define NS921X_TCR_UPDOWN (1 << 2) /* Up/Down select */ +#define NS921X_TCR_INTSEL (1 << 3) /* Interrupt select */ + +#define NS921X_TCR_TMODE(x) ((x) & (0x3 << 4)) /* Timer mode */ +#define NS921X_TCR_TMODE_MASK (0x3 << 4) +#define NS921X_TCR_TMODE_INT (0 << 4) +#define NS921X_TCR_TMODE_EXTLOW (1 << 4) +#define NS921X_TCR_TMODE_EXTHIGH (2 << 4) +/* @TODO: Complete the remaining macros */ +//#define NS921X_TCR_TMODE (2 << 4) /* Timer mode */ + +#define NS921X_TCR_TCLKSEL (0xf << 6) /* Timer clock set */ +#define NS921X_TCR_TCLKSEL_MASK (0xf << 6) +#define NS921X_TCR_TCLKSEL_AHB (0x1 << 6) +#define NS921X_TCR_INTCLR (1 << 10) /* Interrupt clear */ +#define NS921X_TCR_DEBUGMODE (1 << 11) /* Debug mode */ +#define NS921X_TCR_CAPCOMP (7 << 12) /* Capture and compare mode functions */ +#define NS921X_TCR_TE (1 << 15) /* Timer enable */ +#define NS921X_TCR_TMODE2 (3 << 16) /* Timer mode 2 */ +#define NS921X_TCR_TMODE2_PWM (1 << 16) /* Timer mode 2 */ + +#define NS921X_TCR_RELOADMODE2 (1 << 18) /* Reload mode */ + +#define NS921X_THIGHREG (32 << 0) /* PWM output toggles high when timer counter reaches this value */ +#define NS921X_TLOWREG (32 << 0) /* PWM toggles low when counter reaches this value */ + +#define NS921X_HISTEP_DIR (1 << 31) /* High step direction */ +#define NS921X_HISTEP (15 << 16) /* High step */ +#define NS921X_LOWSTEP_DIR (1 << 15) /* Low step direction */ +#define NS921X_LOWSTEP (15 << 0) /* Low step */ + +#define NS921X_RELOADSTEPDIR (1 << 15) /* Reload step direction */ +#define NS921X_RELOADSTEP (15 << 0) /* Reload step */ + +#define NS921X_TIMECOMP (16 << 16) /* Timer compare register or timer reload bits 31:16 count register */ +#define NS921X_TIMERELOADBITS (16 << 0) /* Timer reload bits 15:00 count register */ + +#define NS921X_TIMERCAP (16 << 16) /* Timer capture register or timer read bits 31:16 register */ +#define NS921X_TIMERREAD (16 << 0) /* Timer read bits 15:00 register */ + + + +#if 0 +struct pwm_channel { + void __iomem *regs; + unsigned index; + unsigned long mck; +}; + +extern int pwm_channel_alloc(int index, struct pwm_channel *ch); +extern int pwm_channel_free(struct pwm_channel *ch); + +extern int pwm_clk_alloc(unsigned prescale, unsigned div); +extern void pwm_clk_free(unsigned clk); + +extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled); + +#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1) +#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0) + +/* periodic interrupts, mostly for CUPD changes to period or cycle */ +extern int pwm_channel_handler(struct pwm_channel *ch, + void (*handler)(struct pwm_channel *ch)); + +static inline void +pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val) +{ + __raw_writel(val, pwmc->regs + offset); +} + +static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset) +{ + return __raw_readl(pwmc->regs + offset); +} + +#endif /* __LINUX_NS9XXX_PWM_H */ + +#endif /* __NS9XXX_PWM_HEADER_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h index 9f77f746a386..a36ce171b4e3 100644 --- a/arch/arm/mach-ns9xxx/include/mach/processor.h +++ b/arch/arm/mach-ns9xxx/include/mach/processor.h @@ -16,12 +16,14 @@ #define processor_is_ns9210() (0 \ || module_is_cc7ucamry() \ || module_is_cc9p9210() \ + || module_is_cme9210() \ || module_is_inc20otter() \ || module_is_otter() \ ) #define processor_is_ns9215() (0 \ || module_is_cc9p9215() \ + || module_is_ccw9p9215() \ ) #define processor_is_ns9360() (0 \ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h index af227c058fb9..564498990063 100644 --- a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h +++ b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h @@ -8,38 +8,51 @@ * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ -#ifndef __ASM_ARCH_REGSBBU_H -#define __ASM_ARCH_REGSBBU_H +#ifndef __ASM_ARCH_REGS_BBU_H +#define __ASM_ARCH_REGS_BBU_H #include <mach/hardware.h> /* BBus Utility */ +#define NS9360_BBU_MSR __REG(0x90600000) + /* GPIO Configuration Registers block 1 */ /* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is - * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register - * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ -#define BBU_GCONFb1(x) __REG2(0x90600010, (x)) -#define BBU_GCONFb2(x) __REG2(0x90600100, (x)) - -#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) -#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) -#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) -#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) -#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) -#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) -#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) -#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) -#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) -#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) -#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) - -#define BBU_GCTRL1 __REG(0x90600030) -#define BBU_GCTRL2 __REG(0x90600034) -#define BBU_GCTRL3 __REG(0x90600120) - -#define BBU_GSTAT1 __REG(0x90600040) -#define BBU_GSTAT2 __REG(0x90600044) -#define BBU_GSTAT3 __REG(0x90600130) - -#endif /* ifndef __ASM_ARCH_REGSBBU_H */ + * at 0 for each block. That is, NS9360_BBU_GCONFb1(0) is GPIO Configuration + * Register #1, NS9360_BBU_GCONFb2(0) is GPIO Configuration Register #8. */ +#define NS9360_BBU_GCONFb1(x) __REG2(0x90600010, (x)) +#define NS9360_BBU_GCONFb2(x) __REG2(0x90600100, (x)) + +#define __NS9360_BBU_GCONFx_SHIFT(m) (((m) & 7) << 2) + +#define NS9360_BBU_GCONFx_DIR(m) __REGBIT_SHIFT(3, __NS9360_BBU_GCONFx_SHIFT(m)) +#define NS9360_BBU_GCONFx_DIR_INPUT(m) __REGVAL(NS9360_BBU_GCONFx_DIR(m), 0) +#define NS9360_BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(NS9360_BBU_GCONFx_DIR(m), 1) +#define NS9360_BBU_GCONFx_INV(m) __REGBIT_SHIFT(2, __NS9360_BBU_GCONFx_SHIFT(m)) +#define NS9360_BBU_GCONFx_INV_NO(m) __REGVAL(NS9360_BBU_GCONFx_INV(m), 0) +#define NS9360_BBU_GCONFx_INV_YES(m) __REGVAL(NS9360_BBU_GCONFx_INV(m), 1) +#define NS9360_BBU_GCONFx_FUNC(m) __REGBITS_SHIFT(1, 0, __NS9360_BBU_GCONFx_SHIFT(m)) +#define NS9360_BBU_GCONFx_FUNC_0(m) __REGVAL(NS9360_BBU_GCONFx_FUNC(m), 0) +#define NS9360_BBU_GCONFx_FUNC_1(m) __REGVAL(NS9360_BBU_GCONFx_FUNC(m), 1) +#define NS9360_BBU_GCONFx_FUNC_2(m) __REGVAL(NS9360_BBU_GCONFx_FUNC(m), 2) +#define NS9360_BBU_GCONFx_FUNC_3(m) __REGVAL(NS9360_BBU_GCONFx_FUNC(m), 3) + +#define NS9360_BBU_GCTRL1 __REG(0x90600030) +#define NS9360_BBU_GCTRL2 __REG(0x90600034) +#define NS9360_BBU_GCTRL3 __REG(0x90600120) + +#define NS9360_BBU_GSTAT1 __REG(0x90600040) +#define NS9360_BBU_GSTAT2 __REG(0x90600044) +#define NS9360_BBU_GSTAT3 __REG(0x90600130) + +#define NS9360_BBUS_USB __REG(0x90600070) + +#define NS9360_BBUS_DMA_ISTAT __REG(0x90600060) +#define NS9360_BBUS_DMA_IEN __REG(0x90600064) + +#define NS9360_BBUS_ISTAT __REG(0xa0401000) +#define NS9360_BBUS_IEN __REG(0xa0401004) +#define NS9360_BBUS_IEN_GLBL (1 << 31) + +#endif /* ifndef __ASM_ARCH_REGS_BBU_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-io-ns921x.h b/arch/arm/mach-ns9xxx/include/mach/regs-io-ns921x.h new file mode 100644 index 000000000000..948a273a9621 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/regs-io-ns921x.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/regs-io-ns921x.h + * + * Copyright (C) 2007-2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __ASM_ARCH_REGSIONS921X_H +#define __ASM_ARCH_REGSIONS921X_H + +#include <mach/hardware.h> + +#define __NS921X_IO_GPIOCONF_SHIFT(m) (((m) & 3) << 3) + +/* I/O Control Module */ + +/* NOTE: the first GPIO has number #0, this is different from NS9360 which + * starts at #1 */ + +/* GPIO Configuration Register */ +#define NS921X_IO_GPIOCONFx(x) __REG2(0xa0902000, (x)) + +#define NS921X_IO_GPIOCONFx_FUNC(m) __REGBITS_SHIFT(5, 3, __NS921X_IO_GPIOCONF_SHIFT(m)) +#define NS921X_IO_GPIOCONFx_DIR(m) __REGBIT(2 + __NS921X_IO_GPIOCONF_SHIFT(m)) +#define NS921X_IO_GPIOCONFx_DIR_IN(m) __REGVAL(NS921X_IO_GPIOCONF_DIR(m), 0) +#define NS921X_IO_GPIOCONFx_DIR_OUT(m) __REGVAL(NS921X_IO_GPIOCONF_DIR(m), 1) +#define NS921X_IO_GPIOCONFx_INV(m) __REGBIT(1 + __NS921X_IO_GPIOCONF_SHIFT(m)) +#define NS921X_IO_GPIOCONFx_INV_OFF(m) __REGVAL(NS921X_IO_GPIOCONF_INV(m), 0) +#define NS921X_IO_GPIOCONFx_INV_ON(m) __REGVAL(NS921X_IO_GPIOCONF_INV(m), 1) +#define NS921X_IO_GPIOCONFx_PUEN(m) __REGBIT(__NS921X_IO_GPIOCONF_SHIFT(m)) +#define NS921X_IO_GPIOCONFx_PUEN_EN(m) __REGVAL(NS921X_IO_GPIOCONF_PUEN(m), 0) +#define NS921X_IO_GPIOCONFx_PUEN_DIS(m) __REGVAL(NS921X_IO_GPIOCONF_PUEN(m), 1) + +#define NS921X_IO_GPIOCTRLx(x) __REG2(0xa090206c, (x)) + +#define NS921X_IO_GPIOSTATx(x) __REG2(0xa090207c, (x)) + +#endif /* ifndef __ASM_ARCH_REGSSYSNS921X_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-iohub-ns921x.h b/arch/arm/mach-ns9xxx/include/mach/regs-iohub-ns921x.h new file mode 100644 index 000000000000..8b274bb8bcd8 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/regs-iohub-ns921x.h @@ -0,0 +1,133 @@ +/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns921x.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * !Revision: $Revision: 1.0 $
+ * !Author: Luis Galdos
+ * !Desc:
+ * !References:
+ */
+
+#ifndef __ASM_ARCH_REGSIOHUB_NS921X_H
+#define __ASM_ARCH_REGSIOHUB_NS921X_H
+
+#include <mach/hardware.h>
+#include <mach/regs-sys-common.h>
+
+#define IOHUB_REG_BASE_PA (0x90000000)
+#define IOHUB_REG_BASE_VA io_p2v(IOHUB_REG_BASE_PA)
+#define IOHUB_REG_OFFSET (0x8000)
+#define IOHUB_FIM0_BASE_PA IOHUB_REG_BASE_PA
+#define IOHUB_FIM1_BASE_PA (IOHUB_REG_BASE_PA + IOHUB_REG_OFFSET)
+#define IOHUB_FIM0_BASE_VA io_p2v(IOHUB_FIM0_BASE_PA)
+#define IOHUB_FIM1_BASE_VA io_p2v(IOHUB_FIM1_BASE_PA)
+
+/* Register offsets for the IOHUB-components */
+#define IOHUB_IFS_REG (0x00)
+
+#define IOHUB_RX_DMA_CTRL_REG (0x04)
+#define IOHUB_RX_DMA_BUFPTR_REG (0x08)
+#define IOHUB_RX_DMA_ICTRL_REG (0x0C)
+#define IOHUB_RX_DIR_REG (0x10)
+#define IOHUB_RX_DIR_FIFO_REG (0x14)
+#define IOHUB_TX_DMA_CTRL_REG (0x18)
+#define IOHUB_TX_DMA_BUFPTR_REG (0x1C)
+#define IOHUB_TX_ICTRL_REG (0x20)
+#define IOHUB_TX_FIFO_REG (0x28)
+#define IOHUB_TX_DIR_REG (0x2C)
+
+/* DMA RX control bits */
+#define IOHUB_RX_DMA_CTRL_CE (1<<31)
+#define IOHUB_RX_DMA_CTRL_CA (1<<30)
+#define IOHUB_RX_DMA_CTRL_FLEXIO (1<<29)
+#define IOHUB_RX_DMA_CTRL_DIRECT (1<<28)
+#define IOHUB_RX_DMA_CTRL_STATE (0xFC00)
+#define IOHUB_RX_DMA_CTRL_INDEX (0x03FF)
+
+
+/* DMA TX control bits */
+#define IOHUB_TX_DMA_CTRL_CE (1<<31)
+#define IOHUB_TX_DMA_CTRL_CA (1<<30)
+#define IOHUB_TX_DMA_CTRL_FLEXIO (1<<29)
+#define IOHUB_TX_DMA_CTRL_DIRECT (1<<28)
+#define IOHUB_TX_DMA_CTRL_STATE (0xFC00)
+#define IOHUB_TX_DMA_CTRL_INDEXEN (1<<27)
+#define IOHUB_TX_DMA_CTRL_INDEX(i) (i & 0x03FF)
+
+
+
+/* Interrupt and FIFO status register */
+#define IOHUB_IFS_RXNCIP (1<<31)
+#define IOHUB_IFS_RXECIP (1<<30)
+#define IOHUB_IFS_RXNRIP (1<<29)
+#define IOHUB_IFS_RXCAIP (1<<28)
+#define IOHUB_IFS_TXNCIP (1<<24)
+#define IOHUB_IFS_TXECIP (1<<23)
+#define IOHUB_IFS_TXNRIP (1<<22)
+#define IOHUB_IFS_TXCAIP (1<<21)
+#define IOHUB_IFS_TXFUFIP (1<<20)
+#define IOHUB_IFS_TXFSRIP (1<<19)
+#define IOHUB_IFS_MODIP (1<<18)
+#define IOHUB_IFS_DMA_TX (IOHUB_IFS_TXNCIP | \
+ IOHUB_IFS_TXNRIP | \
+ IOHUB_IFS_TXECIP | \
+ IOHUB_IFS_TXCAIP)
+#define IOHUB_IFS_DMA_RX (IOHUB_IFS_RXNCIP | \
+ IOHUB_IFS_RXNRIP | \
+ IOHUB_IFS_RXECIP | \
+ IOHUB_IFS_RXCAIP)
+
+/* Interrupt configuration register */
+#define IOHUB_ICTRL_RXTHRS(val) (val<<28)
+#define IOHUB_ICTRL_RXFOFIE (1<<26)
+#define IOHUB_ICTRL_RXFSRIE (1<<25)
+#define IOHUB_ICTRL_RXNCIE (1<<24)
+#define IOHUB_ICTRL_RXECIE (1<<23)
+#define IOHUB_ICTRL_RXNRIE (1<<22)
+#define IOHUB_ICTRL_RXCAIE (1<<21)
+#define IOHUB_ICTRL_RXPCIE (1<<20)
+#define IOHUB_ICTRL_WSTAT (1<<19)
+#define IOHUB_ICTRL_ISTAT (1<<18)
+#define IOHUB_ICTRL_LSTAT (1<<17)
+#define IOHUB_ICTRL_FSTAT (1<<16)
+#define IOHUB_ICTRL_BLENSTAT (0xFF)
+#define IOHUB_ICTRL_RXALLE (IOHUB_ICTRL_RXFOFIE | \
+ IOHUB_ICTRL_RXFSRIE | \
+ IOHUB_ICTRL_RXNCIE | \
+ IOHUB_ICTRL_RXECIE | \
+ IOHUB_ICTRL_RXNRIE | \
+ IOHUB_ICTRL_RXCAIE | \
+ IOHUB_ICTRL_RXPCIE)
+
+
+#define IOHUB_ICTRL_TXTHRS(val) (val<<28)
+#define IOHUB_ICTRL_TXFUFIE (1<<26)
+#define IOHUB_ICTRL_TXFSRIE (1<<25)
+#define IOHUB_ICTRL_TXNCIE (1<<24)
+#define IOHUB_ICTRL_TXECIE (1<<23)
+#define IOHUB_ICTRL_TXNRIE (1<<22)
+#define IOHUB_ICTRL_TXCAIE (1<<21)
+#define IOHUB_ICTRL_WSTAT (1<<19)
+#define IOHUB_ICTRL_ISTAT (1<<18)
+#define IOHUB_ICTRL_LSTAT (1<<17)
+#define IOHUB_ICTRL_FSTAT (1<<16)
+#define IOHUB_ICTRL_BLENSTAT (0xFF)
+#define IOHUB_ICTRL_TXALLE (IOHUB_ICTRL_TXFUFIE | \
+ IOHUB_ICTRL_TXFSRIE | \
+ IOHUB_ICTRL_TXNCIE | \
+ IOHUB_ICTRL_TXECIE | \
+ IOHUB_ICTRL_TXNRIE | \
+ IOHUB_ICTRL_TXCAIE)
+
+
+
+#endif /* ifndef __ASM_ARCH_REGSIOHUB_NS921X_H */
+
+
+
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-lcd-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-lcd-ns9360.h new file mode 100644 index 000000000000..7beabc4729bc --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/regs-lcd-ns9360.h @@ -0,0 +1,88 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/regs-lcd-ns9360.h + * + * Copyright (C) 2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_REGSLCDNS9360_H +#define __ASM_ARCH_REGSLCDNS9360_H + +#define LCD_TIMING0 0x00 +#define LCD_TIMING0_HBP(x) (((x) & 0xFF) << 24) +#define LCD_TIMING0_HFP(x) (((x) & 0xFF) << 16) +#define LCD_TIMING0_HSW(x) (((x) & 0xFF) << 8) +#define LCD_TIMING0_PPL(x) (((x) & 0x3F) << 2) + +#define LCD_TIMING1 0x04 +#define LCD_TIMING1_VBP(x) (((x) & 0xFF) << 24) +#define LCD_TIMING1_VFP(x) (((x) & 0xFF) << 16) +#define LCD_TIMING1_VSW(x) (((x) & 0x3F) << 10) +#define LCD_TIMING1_LPP(x) (((x) & 0x3FF)) + +#define LCD_TIMING2 0x08 +#define LCD_TIMING2_BCD (1 << 26) +#define LCD_TIMING2_CPL(x) (((x) & 0x3FF) << 16) +#define LCD_TIMING2_IOE (1 << 14) +#define LCD_TIMING2_IPC (1 << 13) +#define LCD_TIMING2_IHS (1 << 12) +#define LCD_TIMING2_IVS (1 << 11) +#define LCD_TIMING2_ACB(x) (((x) & 0x1F) << 6) +#define LCD_TIMING2_PCD(x) (((x) & 0x1F)) + +#define LCD_TIMING3 0x0c +#define LCD_TIMING3_LEE (1 << 16) +#define LCD_TIMING3_LED(x) (((x) & 0x7F)) + +#define LCD_UPBASE 0x10 +#define LCD_UPBASE_V(x) (((x) & 0x3FFFFFFF)<<2) + +#define LCD_LPBASE 0x14 +#define LCD_PBASE_V(x) (((x) & 0x3FFFFFFF)<<2) + +#define LCD_IRENABLE 0x18 +#define LCD_IRENABLE_MBERR (1 << 3) +#define LCD_IRENABLE_VCOMP (1 << 2) +#define LCD_IRENABLE_LNBU (1 << 1) + +#define LCD_CONTROL 0x1c +#define LCD_CONTROL_WATERMARK (1 << 16) +#define LCD_CONTROL_VCOMP_MA (3 << 12) +#define LCD_CONTROL_VCOMP_VS (0 << 12) +#define LCD_CONTROL_VCOMP_BP (1 << 12) +#define LCD_CONTROL_VCOMP_AV (2 << 12) +#define LCD_CONTROL_VCOMP_FP (3 << 12) +#define LCD_CONTROL_PWR (1 << 11) +#define LCD_CONTROL_BEPO (1 << 10) +#define LCD_CONTROL_BEBO (1 << 9) +#define LCD_CONTROL_BGR (1 << 8) +#define LCD_CONTROL_DUAL (1 << 7) +#define LCD_CONTROL_MONO8 (1 << 6) +#define LCD_CONTROL_TFT (1 << 5) +#define LCD_CONTROL_BW (1 << 4) +#define LCD_CONTROL_BPP_MA (7 << 1) +#define LCD_CONTROL_BPP_1 (0 << 1) +#define LCD_CONTROL_BPP_2 (1 << 1) +#define LCD_CONTROL_BPP_4 (2 << 1) +#define LCD_CONTROL_BPP_8 (3 << 1) +#define LCD_CONTROL_BPP_16 (4 << 1) +#define LCD_CONTROL_EN (1 << 0) + +#define LCD_STATUS 0x20 +#define LCD_STATUS_MBERROR (4 << 1) +#define LCD_STATUS_VCOMP (3 << 1) +#define LCD_STATUS_LNBU (2 << 1) + +#define LCD_INTR 0x24 +#define LCD_INTR_MBERROR (4 << 1) +#define LCD_INTR_VCOMP (3 << 1) +#define LCD_INTR_LNBUINTR (2 << 1) + +#define LCD_UPCURRENT 0x28 +#define LCD_LPCURRENT 0x2c + +#endif diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h index 14f91dfd5736..3041d3f6f44a 100644 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h +++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h * - * Copyright (C) 2007 by Digi International Inc. + * Copyright (C) 2007,2008 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -18,6 +18,12 @@ /* Interrupt Configuration registers */ #define SYS_IC(x) __REG2(0xa0900144, (x)) +#define __SYS_IC_FIELDNUM(i) (3 - ((i) & 3)) +#define __SYS_IC_SHIFT(i) (((i) & 3) << 3) +#define SYS_IC_IE(i) __REGBIT(7 + __SYS_IC_SHIFT(i)) +#define SYS_IC_IE_EN(i) __REGVAL(SYS_IC_IE(i), 1) +#define SYS_IC_IE_DIS(i) __REGVAL(SYS_IC_IE(i), 0) +#define SYS_IC_ISD(i) __REGBITS_SHIFT(4, 0, __SYS_IC_SHIFT(i)) /* ISRADDR */ #define SYS_ISRADDR __REG(0xa0900164) @@ -28,4 +34,43 @@ /* Interrupt Status Raw */ #define SYS_ISR __REG(0xa090016c) +/* Active Interrupt Level ID Status register */ +#define SYS_AILID __REG(0xa090018c) + +/* System Memory Chip Select x Dynamic Memory Base */ +#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1) + +/* System Memory Chip Select x Dynamic Memory Mask */ +#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1) + +/* System Memory Chip Select x Static Memory Base */ +#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1) + +/* System Memory Chip Select x Static Memory Base: Chip select x base */ +#define SYS_SMCSSMB_CSxB __REGBITS(31, 12) + +/* System Memory Chip Select x Static Memory Mask */ +#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1) + +/* System Memory Chip Select x Static Memory Mask: Chip select x mask */ +#define SYS_SMCSSMM_CSxM __REGBITS(31, 12) + +/* System Memory Chip Select x Static Memory Mask: Chip select x enable */ +#define SYS_SMCSSMM_CSEx __REGBIT(0) +#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0) +#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1) + +/* General purpose, user-defined ID register */ +#define SYS_GENID __REG(0xa0900210) + + +#define SYS_EIxCTRL(i) __REG2(0xa0900214, (i)) +#define SYS_EIxCTRL_CLEAR __REGBIT(2) +#define SYS_EIxCTRL_PLTY __REGBIT(1) +#define SYS_EIxCTRL_PLTY_HIGH __REGVAL(SYS_EIxCTRL_PLTY, 0) +#define SYS_EIxCTRL_PLTY_LOW __REGVAL(SYS_EIxCTRL_PLTY, 1) +#define SYS_EIxCTRL_TYPE __REGBIT(0) +#define SYS_EIxCTRL_TYPE_LEVEL __REGVAL(SYS_EIxCTRL_TYPE, 0) +#define SYS_EIxCTRL_TYPE_EDGE __REGVAL(SYS_EIxCTRL_TYPE, 1) + #endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns921x.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns921x.h new file mode 100644 index 000000000000..a8e4410806c6 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns921x.h @@ -0,0 +1,154 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns921x.h + * + * Copyright (C) 2007,2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __ASM_ARCH_REGSSYSNS921X_H +#define __ASM_ARCH_REGSSYSNS921X_H + +#include <mach/hardware.h> +#include <mach/regs-sys-common.h> + +/* System Control Module */ + +/* Timer Master Control */ +#define SYS_TMC __REG(0xa0900024) +#define SYS_TMC_T9RSE __REGBIT(21) +#define SYS_TMC_T9LSE __REGBIT(20) +#define SYS_TMC_T9HSE __REGBIT(19) +#define SYS_TMC_T8RSE __REGBIT(18) +#define SYS_TMC_T8LSE __REGBIT(17) +#define SYS_TMC_T8HSE __REGBIT(16) +#define SYS_TMC_T7RSE __REGBIT(15) +#define SYS_TMC_T7LSE __REGBIT(14) +#define SYS_TMC_T7HSE __REGBIT(13) +#define SYS_TMC_T6RSE __REGBIT(12) +#define SYS_TMC_T6LSE __REGBIT(11) +#define SYS_TMC_T6HSE __REGBIT(10) +#define SYS_TMC_T9E __REGBIT(9) +#define SYS_TMC_T8E __REGBIT(8) +#define SYS_TMC_T7E __REGBIT(7) +#define SYS_TMC_T6E __REGBIT(6) +#define SYS_TMC_T5E __REGBIT(5) +#define SYS_TMC_T4E __REGBIT(4) +#define SYS_TMC_T3E __REGBIT(3) +#define SYS_TMC_T2E __REGBIT(2) +#define SYS_TMC_T1E __REGBIT(1) +#define SYS_TMC_T0E __REGBIT(0) + +/* Timer x Reload Count and Compare register */ +#define SYS_TRCC(x) __REG2(0xa0900028, (x)) + +/* Timer x Read and Capture register */ +#define SYS_TRC(x) __REG2(0xa0900050, (x)) + +/* Interrupt Vector Address Register Level x */ +#define SYS_IVA(x) __REG2(0xa09000c4, (x)) + +/* Clock Configuration register */ +#define SYS_CLOCK __REG(0xa090017c) +#define SYS_CLOCK_CSC __REGBITS(31, 29) +#define SYS_CLOCK_CSSEL __REGBIT(25) +#define SYS_CLOCK_EXTDMA __REGBIT(14) +#define SYS_CLOCK_RTC __REGBIT(12) +#define SYS_CLOCK_I2C __REGBIT(11) +#define SYS_CLOCK_AES __REGBIT(9) +#define SYS_CLOCK_ADC __REGBIT(8) +#define SYS_CLOCK_SPI __REGBIT(5) +#define SYS_CLOCK_UARTx(i) __REGBIT(1 + (i)) +#define SYS_CLOCK_UARTD SYS_CLOCK_UARTx(3) +#define SYS_CLOCK_UARTC SYS_CLOCK_UARTx(2) +#define SYS_CLOCK_UARTB SYS_CLOCK_UARTx(1) +#define SYS_CLOCK_UARTA SYS_CLOCK_UARTx(0) +#define SYS_CLOCK_ETH __REGBIT(0) + +#define SYS_RESET __REG(0xa0900180) + +/* PLL Configuration register */ +#define SYS_PLL __REG(0xa0900188) +#define SYS_PLL_NF __REGBITS(16, 8) +#define SYS_PLL_BP __REGBIT(7) +#define SYS_PLL_OD __REGBITS(6, 5) +#define SYS_PLL_NR __REGBITS(4, 0) + +/* Timer x Control register */ +#define SYS_TC(x) __REG2(0xa0900190, (x)) +#define SYS_TCx_RELMODE __REGBIT(18) +#define SYS_TCx_RELMODE_FULL __REGVAL(SYS_TCx_RELMODE, 0) +#define SYS_TCx_RELMODE_HALF __REGVAL(SYS_TCx_RELMODE, 1) +#define SYS_TCx_MODE2 __REGBITS(17, 16) +#define SYS_TCx_MODE2_00 __REGVAL(SYS_TCx_MODE2, 0) +#define SYS_TCx_MODE2_01 __REGVAL(SYS_TCx_MODE2, 1) +#define SYS_TCx_MODE2_10 __REGVAL(SYS_TCx_MODE2, 2) +#define SYS_TCx_MODE2_11 __REGVAL(SYS_TCx_MODE2, 3) +#define SYS_TCx_TE __REGBIT(15) +#define SYS_TCx_TE_DIS __REGVAL(SYS_TCx_TE, 0) +#define SYS_TCx_TE_EN __REGVAL(SYS_TCx_TE, 1) +#define SYS_TCx_CAPCOMP __REGBITS(14,12) +#define SYS_TCx_CAPCOMP_000 __REGVAL(SYS_TCx_CAPCOMP, 0) +#define SYS_TCx_DEBUG __REGBIT(11) +#define SYS_TCx_DEBUG_CONT __REGVAL(SYS_TCx_DEBUG, 0) +#define SYS_TCx_DEBUG_STOP __REGVAL(SYS_TCx_DEBUG, 1) +#define SYS_TCx_INTCLR __REGBIT(10) +#define SYS_TCx_TCS __REGBITS(9, 6) +#define SYS_TCx_TCS_2AHB __REGVAL(SYS_TCx_TCS, 0) +#define SYS_TCx_TCS_AHB __REGVAL(SYS_TCx_TCS, 1) +#define SYS_TCx_MODE __REGBITS(5, 4) +#define SYS_TCx_MODE_INTERNAL __REGVAL(SYS_TCx_MODE, 0) +#define SYS_TCx_MODE_CONCA __REGVAL(SYS_TCx_MODE, 3) +#define SYS_TCx_INTSEL __REGBIT(3) +#define SYS_TCx_INTSEL_DIS __REGVAL(SYS_TCx_INTSEL, 0) +#define SYS_TCx_INTSEL_EN __REGVAL(SYS_TCx_INTSEL, 1) +#define SYS_TCx_UPDOWN __REGBIT(2) +#define SYS_TCx_UPDOWN_UP __REGVAL(SYS_TCx_UPDOWN, 0) +#define SYS_TCx_UPDOWN_DOWN __REGVAL(SYS_TCx_UPDOWN, 1) +#define SYS_TCx_BITTIMER __REGBIT(1) +#define SYS_TCx_BITTIMER_16 __REGVAL(SYS_TCx_BITTIMER, 0) +#define SYS_TCx_BITTIMER_32 __REGVAL(SYS_TCx_BITTIMER, 1) +#define SYS_TCx_RELENBL __REGBIT(0) +#define SYS_TCx_RELENBL_DIS __REGVAL(SYS_TCx_RELENBL, 0) +#define SYS_TCx_RELENBL_EN __REGVAL(SYS_TCx_RELENBL, 1) + +/* Timer Registers */ +#define SYS_THR(x) __REG2(0xa0900078, (x)) /* Timer 6-9 High Registers */ +#define SYS_TLR(x) __REG2(0xa0900088, (x)) /* Timer 6-9 Low Registers */ +#define SYS_THLSR(x) __REG2(0xa0900098, (x)) /* Timer 6-9 High Low Step Register */ +#define SYS_TRELSR(x) __REG2(0xa09000a8, (x)) /* Timer 6-9 Reload Step Register */ +#define SYS_TRELCCR(x) __REG2(0xa0900028, (x)) /* Timer 0-9 Reload Count and Compare Register */ +#define SYS_TRCR(x) __REG2(0xa0900050, (x)) /* Timer 0-9 Read and Capture Register */ + +/* */ +#define SYS_RTCMC __REG(0xa0900224) +#define SYS_RTCMC_SS __REGBIT(4) +#define SYS_RTCMC_RIS __REGBIT(3) +#define SYS_RTCMC_MIS __REGBIT(2) +#define SYS_RTCMC_MODE __REGBIT(1) +#define SYS_RTCMC_MODE_STANDBY __REGVAL(SYS_RTCMC_MODE, 0) +#define SYS_RTCMC_MODE_NORMAL __REGVAL(SYS_RTCMC_MODE, 1) +#define SYS_RTCMC_RIC __REGBIT(0) + +/* */ +#define SYS_POWER __REG(0xa0900228) +#define SYS_POWER_SLFRFSH __REGBIT(21) +#define SYS_POWER_INTCLR __REGBIT(20) +#define SYS_POWER_EXTIRQx(i) __REGBIT(16 + (i)) +#define SYS_POWER_EXTIRQ3 SYS_POWER_EXTIRQx(3) +#define SYS_POWER_EXTIRQ2 SYS_POWER_EXTIRQx(2) +#define SYS_POWER_EXTIRQ1 SYS_POWER_EXTIRQx(1) +#define SYS_POWER_EXTIRQ0 SYS_POWER_EXTIRQx(0) +#define SYS_POWER_RTC SYS_CLOCK_RTC +#define SYS_POWER_I2C SYS_CLOCK_I2C +#define SYS_POWER_SPI SYS_CLOCK_SPI +#define SYS_POWER_UARTx(i) SYS_CLOCK_UARTx(i) +#define SYS_POWER_UARTD SYS_POWER_UARTx(3) +#define SYS_POWER_UARTC SYS_POWER_UARTx(2) +#define SYS_POWER_UARTB SYS_POWER_UARTx(1) +#define SYS_POWER_UARTA SYS_POWER_UARTx(0) +#define SYS_POWER_ETH SYS_CLOCK_ETH + +#endif /* ifndef __ASM_ARCH_REGSSYSNS921X_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h index 8ff254d9901c..30236e6fbc49 100644 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h +++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h * - * Copyright (C) 2006,2007 by Digi International Inc. + * Copyright (C) 2006-2008 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -30,6 +30,12 @@ /* Timer Interrupt Status register */ #define SYS_TIS __REG(0xa0900170) +#define SYS_CLOCK __REG(0xa090017c) +#define SYS_CLOCK_LPCSEXT __REGBIT(9) + +#define SYS_RESET __REG(0xa0900180) +#define SYS_RESET_LCDC __REGBIT(5) + /* PLL Configuration register */ #define SYS_PLL __REG(0xa0900188) @@ -100,32 +106,6 @@ #define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0) #define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1) -/* System Memory Chip Select x Dynamic Memory Base */ -#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1) - -/* System Memory Chip Select x Dynamic Memory Mask */ -#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1) - -/* System Memory Chip Select x Static Memory Base */ -#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1) - -/* System Memory Chip Select x Static Memory Base: Chip select x base */ -#define SYS_SMCSSMB_CSxB __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask */ -#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1) - -/* System Memory Chip Select x Static Memory Mask: Chip select x mask */ -#define SYS_SMCSSMM_CSxM __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask: Chip select x enable */ -#define SYS_SMCSSMM_CSEx __REGBIT(0) -#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0) -#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1) - -/* General purpose, user-defined ID register */ -#define SYS_GENID __REG(0xa0900210) - /* External Interrupt x Control register */ #define SYS_EIC(x) __REG2(0xa0900214, (x)) @@ -145,4 +125,7 @@ #define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) #define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) +/* RTC Clock Control register */ +#define SYS_RTCCC __REG(0xa0900224) + #endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/spi.h b/arch/arm/mach-ns9xxx/include/mach/spi.h new file mode 100644 index 000000000000..801d01b838d6 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/spi.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/spi.h + * + * Copyright (C) 2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. +*/ +#ifndef __ASM_ARCH_SPI_H +#define __ASM_ARCH_SPI_H + +#define SPI_MOSI_GPIO_OFFSET 0 +#define SPI_MISO_GPIO_OFFSET 1 +#define SPI_CLK_GPIO_OFFSET 2 +#define SPI_EN_GPIO_OFFSET 3 + + +#define SPI_MAX_GPIO 10 + +struct spi_ns9xxx_data { + char gpios[SPI_MAX_GPIO]; + char gpio_funcs[SPI_MAX_GPIO]; + char nr_gpios; +}; + +#endif /* ifndef __ASM_ARCH_SPI_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h index e2068c57415f..e4ae479dc5b2 100644 --- a/arch/arm/mach-ns9xxx/include/mach/system.h +++ b/arch/arm/mach-ns9xxx/include/mach/system.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-ns9xxx/include/mach/system.h * - * Copyright (C) 2006,2007 by Digi International Inc. + * Copyright (C) 2006-2008 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -13,15 +13,32 @@ #include <asm/proc-fns.h> #include <mach/processor.h> -#include <mach/processor-ns9360.h> static inline void arch_idle(void) { - cpu_do_idle(); + /* + * When a Camry (i.e. ns921x) executes + * + * mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt + * + * the CPU is stopped, so are all timers. This is not something I want + * to handle. As the "wait for interrupt" instruction is part of + * cpu_arm926_do_idle, it's not called for it. + */ + if (!processor_is_ns921x()) + cpu_do_idle(); } +void ns921x_reset(char); +void ns9360_reset(char); + static inline void arch_reset(char mode) { +#ifdef CONFIG_PROCESSOR_NS921X + if (processor_is_ns921x()) + ns921x_reset(mode); + else +#endif #ifdef CONFIG_PROCESSOR_NS9360 if (processor_is_ns9360()) ns9360_reset(mode); diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h index 734a8d8bd578..e901b4e10610 100644 --- a/arch/arm/mach-ns9xxx/include/mach/timex.h +++ b/arch/arm/mach-ns9xxx/include/mach/timex.h @@ -12,7 +12,7 @@ #define __ASM_ARCH_TIMEX_H /* - * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h. + * value for CLOCK_TICK_RATE stolen from include/asm-arm/arch-s3c2410/timex.h. * See there for an explanation. */ #define CLOCK_TICK_RATE 12000000 diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h index 1b12d324b087..fc9b0a424230 100644 --- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h +++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h @@ -11,15 +11,21 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include <linux/io.h> - -#define __REG(x) ((void __iomem __force *)(x)) +#include <asm/io.h> +#define __REG(x) ((void __iomem __force *)(x)) static void putc_dummy(char c, void __iomem *base) { /* nothing */ } +#if defined(CONFIG_PROCESSOR_NS9360) +# define NS9360_UARTA __REG(0x90200040) +# define NS9360_UARTB __REG(0x90200000) +# define NS9360_UARTC __REG(0x90300000) +# define NS9360_UARTD __REG(0x90300040) +# define NS9360_UART_ENABLED(base) \ + (__raw_readl(NS9360_UARTA) & (1 << 31)) static void putc_ns9360(char c, void __iomem *base) { static int t = 0x10000; @@ -34,22 +40,16 @@ static void putc_ns9360(char c, void __iomem *base) } } while (t); } - -static void putc_a9m9750dev(char c, void __iomem *base) -{ - static int t = 0x10000; - do { - if (t) - --t; - - if (__raw_readb(base + 5) & (1 << 5)) { - __raw_writeb(c, base); - t = 0x10000; - break; - } - } while (t); - -} +#endif + +#if defined(CONFIG_PROCESSOR_NS921X) +# define NS921XSYS_CLOCK __REG(0xa090017c) +# define NS921X_UARTA __REG(0x90010000) +# define NS921X_UARTB __REG(0x90018000) +# define NS921X_UARTC __REG(0x90020000) +# define NS921X_UARTD __REG(0x90028000) +# define NS921X_UART_ENABLED(base) \ + (__raw_readl((base) + 0x1000) & (1 << 29)) static void putc_ns921x(char c, void __iomem *base) { @@ -66,79 +66,96 @@ static void putc_ns921x(char c, void __iomem *base) } while (t); } -#define MSCS __REG(0xA0900184) +#include "fim-uncompress.h" -#define NS9360_UARTA __REG(0x90200040) -#define NS9360_UARTB __REG(0x90200000) -#define NS9360_UARTC __REG(0x90300000) -#define NS9360_UARTD __REG(0x90300040) +static void putc_ns921x_fim(char ch, void __iomem *base) +{ + unsigned int status; + unsigned short data = 1; + int pic = 0; -#define NS9360_UART_ENABLED(base) \ - (__raw_readl(NS9360_UARTA) & (1 << 31)) + if ('\n' == ch) + ch = '\r'; -#define A9M9750DEV_UARTA __REG(0x40000000) + data = (data << FIM_SERIAL_DATA_BITS) | (ch & ((1 << FIM_SERIAL_DATA_BITS) - 1)); -#define NS921XSYS_CLOCK __REG(0xa090017c) -#define NS921X_UARTA __REG(0x90010000) -#define NS921X_UARTB __REG(0x90018000) -#define NS921X_UARTC __REG(0x90020000) -#define NS921X_UARTD __REG(0x90028000) + /* Check if the PIC is tasked with another send-char request */ + do { + status = fim_get_exp_reg(pic, 0); + } while (status & FIM_SERIAL_INT_INSERT_CHAR); -#define NS921X_UART_ENABLED(base) \ - (__raw_readl((base) + 0x1000) & (1 << 29)) + /* And send the char using the interrupt function */ + fim_set_ctrl_reg(pic, 0, data & 0xFF); + fim_set_ctrl_reg(pic, 1, (data >> 8) & 0xFF); + fim_send_interrupt(pic, FIM_SERIAL_INT_INSERT_CHAR); +} +#endif static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) { - if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { - /* ns9360 or ns9750 */ - if (NS9360_UART_ENABLED(NS9360_UARTA)) { - *putc = putc_ns9360; - *base = NS9360_UARTA; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { - *putc = putc_ns9360; - *base = NS9360_UARTB; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { - *putc = putc_ns9360; - *base = NS9360_UARTC; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { - *putc = putc_ns9360; - *base = NS9360_UARTD; - return; - } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { - *putc = putc_a9m9750dev; - *base = A9M9750DEV_UARTA; - return; - } - } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { - /* ns921x */ - u32 clock = __raw_readl(NS921XSYS_CLOCK); - - if ((clock & (1 << 1)) && - NS921X_UART_ENABLED(NS921X_UARTA)) { - *putc = putc_ns921x; - *base = NS921X_UARTA; - return; - } else if ((clock & (1 << 2)) && - NS921X_UART_ENABLED(NS921X_UARTB)) { - *putc = putc_ns921x; - *base = NS921X_UARTB; - return; - } else if ((clock & (1 << 3)) && - NS921X_UART_ENABLED(NS921X_UARTC)) { - *putc = putc_ns921x; - *base = NS921X_UARTC; - return; - } else if ((clock & (1 << 4)) && - NS921X_UART_ENABLED(NS921X_UARTD)) { - *putc = putc_ns921x; - *base = NS921X_UARTD; - return; - } +#if defined(CONFIG_PROCESSOR_NS9360) + /* ns9360 */ + if (NS9360_UART_ENABLED(NS9360_UARTA)) { + *putc = putc_ns9360; + *base = NS9360_UARTA; + return; + } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { + *putc = putc_ns9360; + *base = NS9360_UARTB; + return; + } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { + *putc = putc_ns9360; + *base = NS9360_UARTC; + return; + } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { + *putc = putc_ns9360; + *base = NS9360_UARTD; + return; } - +#elif defined(CONFIG_PROCESSOR_NS921X) + /* ns921x */ + u32 clock = __raw_readl(NS921XSYS_CLOCK); + + if ((clock & (1 << 1)) && + NS921X_UART_ENABLED(NS921X_UARTA)) { + *putc = putc_ns921x; + *base = NS921X_UARTA; + return; + } else if ((clock & (1 << 2)) && + NS921X_UART_ENABLED(NS921X_UARTB)) { + *putc = putc_ns921x; + *base = NS921X_UARTB; + return; + } else if ((clock & (1 << 3)) && + NS921X_UART_ENABLED(NS921X_UARTC)) { + *putc = putc_ns921x; + *base = NS921X_UARTC; + return; + } else if ((clock & (1 << 4)) && + NS921X_UART_ENABLED(NS921X_UARTD)) { + *putc = putc_ns921x; + *base = NS921X_UARTD; + return; + } +# if defined(CONFIG_SERIAL_FIM_CONSOLE) + /* None of the standard UARTs is enabled. Try with the FIMs */ +# if defined(CONFIG_FIM_ZERO_SERIAL_SELECTED) && !defined(CONFIG_FIM_ONE_SERIAL_SELECTED) + /* Try with UART on FIM0 */ + else if (NS921X_FIM_ENABLED(NS921X_FIM0)) { + *putc = putc_ns921x_fim; + *base = NS921X_FIM0; + return; + } +# elif !defined(CONFIG_FIM_ZERO_SERIAL_SELECTED) && defined(CONFIG_FIM_ONE_SERIAL_SELECTED) + /* Try with UART on FIM1 */ + else if (NS921X_FIM_ENABLED(NS921X_FIM1)) { + *putc = putc_ns921x_fim; + *base = NS921X_FIM1; + return; + } +# endif /* FIM_x */ +# endif /* SERIAL_FIM_CONSOLE */ +#endif /* PROCESSOR_x */ *putc = putc_dummy; } @@ -147,7 +164,7 @@ void __iomem *base; static void putc(char c) { - myputc(c, base); + myputc(c, base); } static void arch_decomp_setup(void) |