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Diffstat (limited to 'arch/arm/mach-omap2/cclock33xx_data.c')
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544ce4f02..0346de56436c 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -862,6 +862,33 @@ static struct clk_hw_omap wdt1_fck_hw = {
DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
+static const char *pwmss_clk_parents[] = {
+ "dpll_per_m2_ck",
+};
+
+static const struct clk_ops ehrpwm_tbclk_ops = {
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
+ NULL, NULL, 0,
+ AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+ AM33XX_PWMSS0_TBCLKEN_SHIFT,
+ NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
+ NULL, NULL, 0,
+ AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+ AM33XX_PWMSS1_TBCLKEN_SHIFT,
+ NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
+ NULL, NULL, 0,
+ AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+ AM33XX_PWMSS2_TBCLKEN_SHIFT,
+ NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
/*
* clkdev
*/
@@ -942,6 +969,9 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
+ CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
+ CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
+ CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
};