diff options
Diffstat (limited to 'arch/arm/mach-s3c6400')
| -rw-r--r-- | arch/arm/mach-s3c6400/Kconfig | 25 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/Makefile | 10 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/include/mach/dma.h | 59 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/include/mach/map.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/include/mach/regs-clock.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/include/mach/system.h | 8 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/mach-smdk6400.c | 96 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/s3c6400.c | 89 | ||||
| -rw-r--r-- | arch/arm/mach-s3c6400/setup-sdhci.c | 63 |
9 files changed, 368 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig index 6da82b5c09ba..f5af212066c3 100644 --- a/arch/arm/mach-s3c6400/Kconfig +++ b/arch/arm/mach-s3c6400/Kconfig @@ -5,4 +5,27 @@ # # Licensed under GPLv2 -# Currently nothing here, this will be added later +# Configuration options for the S3C6410 CPU + +config CPU_S3C6400 + bool + select CPU_S3C6400_INIT + select CPU_S3C6400_CLOCK + help + Enable S3C6400 CPU support + +config S3C6400_SETUP_SDHCI + bool + help + Internal configuration for default SDHCI + setup for S3C6400. + +# S36400 Macchine support + +config MACH_SMDK6400 + bool "SMDK6400" + select CPU_S3C6400 + select S3C_DEV_HSMMC + select S3C6400_SETUP_SDHCI + help + Machine support for the Samsung SMDK6400 diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile index 8f397db25b87..df1ce4aa03e5 100644 --- a/arch/arm/mach-s3c6400/Makefile +++ b/arch/arm/mach-s3c6400/Makefile @@ -12,4 +12,12 @@ obj- := # Core support for S3C6400 system -obj-n += blank.o +obj-$(CONFIG_CPU_S3C6400) += s3c6400.o + +# setup support + +obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o + +# Machine support + +obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h index 9771ac2cb07e..1067619f0ba0 100644 --- a/arch/arm/mach-s3c6400/include/mach/dma.h +++ b/arch/arm/mach-s3c6400/include/mach/dma.h @@ -11,6 +11,63 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ -/* currently nothing here, placeholder */ +#define S3C_DMA_CHANNELS (16) + +/* see mach-s3c2410/dma.h for notes on dma channel numbers */ + +/* Note, for the S3C64XX architecture we keep the DMACH_ + * defines in the order they are allocated to [S]DMA0/[S]DMA1 + * so that is easy to do DHACH_ -> DMA controller conversion + */ +enum dma_ch { + /* DMA0/SDMA0 */ + DMACH_UART0 = 0, + DMACH_UART0_SRC2, + DMACH_UART1, + DMACH_UART1_SRC2, + DMACH_UART2, + DMACH_UART2_SRC2, + DMACH_UART3, + DMACH_UART3_SRC2, + DMACH_PCM0_TX, + DMACH_PCM0_RX, + DMACH_I2S0_OUT, + DMACH_I2S0_IN, + DMACH_SPI0_TX, + DMACH_SPI0_RX, + DMACH_HSI_I2SV40_TX, + DMACH_HSI_I2SV40_RX, + + /* DMA1/SDMA1 */ + DMACH_PCM1_TX = 16, + DMACH_PCM1_RX, + DMACH_I2S1_OUT, + DMACH_I2S1_IN, + DMACH_SPI1_TX, + DMACH_SPI1_RX, + DMACH_AC97_PCMOUT, + DMACH_AC97_PCMIN, + DMACH_AC97_MICIN, + DMACH_PWM, + DMACH_IRDA, + DMACH_EXTERNAL, + DMACH_RES1, + DMACH_RES2, + DMACH_SECURITY_RX, /* SDMA1 only */ + DMACH_SECURITY_TX, /* SDMA1 only */ + DMACH_MAX /* the end */ +}; + +static __inline__ int s3c_dma_has_circular(void) +{ + /* we will be supporting ciruclar buffers as soon as we have DMA + * engine support. + */ + return 1; +} + +#define S3C2410_DMAF_CIRCULAR (1 << 0) + +#include <plat/dma.h> #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 8199972ed5bd..5057d9948d35 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -39,6 +39,8 @@ #define S3C_VA_UART3 S3C_VA_UARTx(3) #define S3C64XX_PA_FB (0x77100000) +#define S3C64XX_PA_USB_HSOTG (0x7C000000) +#define S3C64XX_PA_WATCHDOG (0x7E004000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_IIS0 (0x7F002000) #define S3C64XX_PA_IIS1 (0x7F003000) @@ -57,6 +59,8 @@ #define S3C64XX_PA_MODEM (0x74108000) #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) +#define S3C64XX_PA_USBHOST (0x74300000) + /* place VICs close together */ #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) @@ -69,5 +73,7 @@ #define S3C_PA_IIC S3C64XX_PA_IIC0 #define S3C_PA_IIC1 S3C64XX_PA_IIC1 #define S3C_PA_FB S3C64XX_PA_FB +#define S3C_PA_USBHOST S3C64XX_PA_USBHOST +#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h new file mode 100644 index 000000000000..a6c7f4eb3a1b --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - clock register compatibility with s3c24xx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <plat/regs-clock.h> + diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h index 090cfd969bc7..2e58cb7a7147 100644 --- a/arch/arm/mach-s3c6400/include/mach/system.h +++ b/arch/arm/mach-s3c6400/include/mach/system.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ +#include <plat/watchdog-reset.h> + static void arch_idle(void) { /* nothing here yet */ @@ -18,7 +20,11 @@ static void arch_idle(void) static void arch_reset(char mode, const char *cmd) { - /* nothing here yet */ + if (mode != 's') + arch_wdt_reset(); + + /* if all else fails, or mode was for soft, jump to 0 */ + cpu_reset(0); } #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c new file mode 100644 index 000000000000..ab19285389a7 --- /dev/null +++ b/arch/arm/mach-s3c6400/mach-smdk6400.c @@ -0,0 +1,96 @@ +/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/io.h> + +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/regs-serial.h> + +#include <plat/s3c6400.h> +#include <plat/clock.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/iic.h> + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, +}; + +static struct map_desc smdk6400_iodesc[] = {}; + +static void __init smdk6400_map_io(void) +{ + s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); +} + +static struct platform_device *smdk6400_devices[] __initdata = { + &s3c_device_hsmmc1, + &s3c_device_i2c0, +}; + +static struct i2c_board_info i2c_devs[] __initdata = { + { I2C_BOARD_INFO("wm8753", 0x1A), }, + { I2C_BOARD_INFO("24c08", 0x50), }, +}; + +static void __init smdk6400_machine_init(void) +{ + i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs)); + platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices)); +} + +MACHINE_START(SMDK6400, "SMDK6400") + /* Maintainer: Ben Dooks <ben@fluff.org> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C64XX_PA_SDRAM + 0x100, + + .init_irq = s3c6400_init_irq, + .map_io = smdk6400_map_io, + .init_machine = smdk6400_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c new file mode 100644 index 000000000000..1ece887d90bb --- /dev/null +++ b/arch/arm/mach-s3c6400/s3c6400.c @@ -0,0 +1,89 @@ +/* linux/arch/arm/mach-s3c6410/cpu.c + * + * Copyright 2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/sysdev.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <asm/irq.h> + +#include <plat/cpu-freq.h> +#include <plat/regs-serial.h> +#include <plat/regs-clock.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> +#include <plat/sdhci.h> +#include <plat/iic-core.h> +#include <plat/s3c6400.h> + +void __init s3c6400_map_io(void) +{ + /* setup SDHCI */ + + s3c6400_default_sdhci0(); + s3c6400_default_sdhci1(); + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); +} + +void __init s3c6400_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initialising clocks\n", __func__); + s3c24xx_register_baseclocks(xtal); + s3c64xx_register_clocks(); + s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK); + s3c6400_setup_clocks(); +} + +void __init s3c6400_init_irq(void) +{ + /* VIC0 does not have IRQS 5..7, + * VIC1 is fully populated. */ + s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); +} + +struct sysdev_class s3c6400_sysclass = { + .name = "s3c6400-core", +}; + +static struct sys_device s3c6400_sysdev = { + .cls = &s3c6400_sysclass, +}; + +static int __init s3c6400_core_init(void) +{ + return sysdev_class_register(&s3c6400_sysclass); +} + +core_initcall(s3c6400_core_init); + +int __init s3c6400_init(void) +{ + printk("S3C6400: Initialising architecture\n"); + + return sysdev_register(&s3c6400_sysdev); +} diff --git a/arch/arm/mach-s3c6400/setup-sdhci.c b/arch/arm/mach-s3c6400/setup-sdhci.c new file mode 100644 index 000000000000..b93dafbee1f4 --- /dev/null +++ b/arch/arm/mach-s3c6400/setup-sdhci.c @@ -0,0 +1,63 @@ +/* linux/arch/arm/mach-s3c6410/setup-sdhci.c + * + * Copyright 2008 Simtec Electronics + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <linux/mmc/card.h> +#include <linux/mmc/host.h> + +#include <plat/regs-sdhci.h> +#include <plat/sdhci.h> + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *s3c6400_hsmmc_clksrcs[4] = { + [0] = "hsmmc", + [1] = "hsmmc", + [2] = "mmc_bus", + /* [3] = "48m", - note not succesfully used yet */ +}; + +void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} + |