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-rw-r--r--arch/arm/mach-spear3xx/Kconfig34
-rw-r--r--arch/arm/mach-spear3xx/Makefile13
-rw-r--r--arch/arm/mach-spear3xx/Makefile.boot4
-rw-r--r--arch/arm/mach-spear3xx/clock.c280
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h42
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h130
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h47
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/spear300.c335
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c75
-rw-r--r--arch/arm/mach-spear3xx/spear310.c391
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c81
-rw-r--r--arch/arm/mach-spear3xx/spear320.c390
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c79
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c152
19 files changed, 1359 insertions, 1041 deletions
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..d9fe11cb6f16 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,19 @@
if ARCH_SPEAR3XX
menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
- bool "SPEAr300 Evaluation Board"
- select MACH_SPEAR300
- help
- Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
- bool "SPEAr310 Evaluation Board"
- select MACH_SPEAR310
- help
- Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
- bool "SPEAr320 Evaluation Board"
- select MACH_SPEAR320
- help
- Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
config MACH_SPEAR300
- bool "SPEAr300"
+ bool "SPEAr300 Machine support with Device Tree"
help
- Supports ST SPEAr300 Machine
+ Supports ST SPEAr300 machine configured via the device-tree
config MACH_SPEAR310
- bool "SPEAr310"
+ bool "SPEAr310 Machine support with Device Tree"
help
- Supports ST SPEAr310 Machine
+ Supports ST SPEAr310 machine configured via the device-tree
config MACH_SPEAR320
- bool "SPEAr320"
+ bool "SPEAr320 Machine support with Device Tree"
help
- Supports ST SPEAr320 Machine
-
+ Supports ST SPEAr320 machine configured via the device-tree
+endmenu
endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..17b5d83cf2d5 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
#
# common files
-obj-y += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o
# spear300 specific files
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
# spear310 specific files
obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
# spear320 specific files
obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f55223..cd6c11099083 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,12 +11,112 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/of_platform.h>
#include <asm/mach-types.h>
#include <plat/clock.h>
#include <mach/misc_regs.h>
+#include <mach/spear.h>
+
+#define PLL1_CTR (MISC_BASE + 0x008)
+#define PLL1_FRQ (MISC_BASE + 0x00C)
+#define PLL1_MOD (MISC_BASE + 0x010)
+#define PLL2_CTR (MISC_BASE + 0x014)
+/* PLL_CTR register masks */
+#define PLL_ENABLE 2
+#define PLL_MODE_SHIFT 4
+#define PLL_MODE_MASK 0x3
+#define PLL_MODE_NORMAL 0
+#define PLL_MODE_FRACTION 1
+#define PLL_MODE_DITH_DSB 2
+#define PLL_MODE_DITH_SSB 3
+
+#define PLL2_FRQ (MISC_BASE + 0x018)
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT 0
+#define PLL_DIV_N_MASK 0xFF
+#define PLL_DIV_P_SHIFT 8
+#define PLL_DIV_P_MASK 0x7
+#define PLL_NORM_FDBK_M_SHIFT 24
+#define PLL_NORM_FDBK_M_MASK 0xFF
+#define PLL_DITH_FDBK_M_SHIFT 16
+#define PLL_DITH_FDBK_M_MASK 0xFFFF
+
+#define PLL2_MOD (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG (MISC_BASE + 0x020)
+#define CORE_CLK_CFG (MISC_BASE + 0x024)
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT 10
+#define PLL_HCLK_RATIO_MASK 0x3
+#define HCLK_PCLK_RATIO_SHIFT 8
+#define HCLK_PCLK_RATIO_MASK 0x3
+
+#define PERIP_CLK_CFG (MISC_BASE + 0x028)
+/* PERIP_CLK_CFG register masks */
+#define UART_CLK_SHIFT 4
+#define UART_CLK_MASK 0x1
+#define FIRDA_CLK_SHIFT 5
+#define FIRDA_CLK_MASK 0x3
+#define GPT0_CLK_SHIFT 8
+#define GPT1_CLK_SHIFT 11
+#define GPT2_CLK_SHIFT 12
+#define GPT_CLK_MASK 0x1
+#define AUX_CLK_PLL3_VAL 0
+#define AUX_CLK_PLL1_VAL 1
+
+#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
+/* PERIP1_CLK_ENB register masks */
+#define UART_CLK_ENB 3
+#define SSP_CLK_ENB 5
+#define I2C_CLK_ENB 7
+#define JPEG_CLK_ENB 8
+#define FIRDA_CLK_ENB 10
+#define GPT1_CLK_ENB 11
+#define GPT2_CLK_ENB 12
+#define ADC_CLK_ENB 15
+#define RTC_CLK_ENB 17
+#define GPIO_CLK_ENB 18
+#define DMA_CLK_ENB 19
+#define SMI_CLK_ENB 21
+#define GMAC_CLK_ENB 23
+#define USBD_CLK_ENB 24
+#define USBH_CLK_ENB 25
+#define C3_CLK_ENB 31
+
+#define RAS_CLK_ENB (MISC_BASE + 0x034)
+
+#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT 0
+#define GPT_MSCALE_MASK 0xFFF
+#define GPT_NSCALE_SHIFT 12
+#define GPT_NSCALE_MASK 0xF
+
+#define AMEM_CLK_CFG (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
+#define UART_CLK_SYNT (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB 31
+#define AUX_EQ_SEL_SHIFT 30
+#define AUX_EQ_SEL_MASK 1
+#define AUX_EQ1_SEL 0
+#define AUX_EQ2_SEL 1
+#define AUX_XSCALE_SHIFT 16
+#define AUX_XSCALE_MASK 0xFFF
+#define AUX_YSCALE_SHIFT 0
+#define AUX_YSCALE_MASK 0xFFF
/* root clks */
/* 32 KHz oscillator clock */
@@ -411,6 +511,21 @@ static struct clk usbd_clk = {
.recalc = &follow_parent,
};
+/* clock derived from usbh clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &usbh_clk,
+ .recalc = &follow_parent,
+};
+
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &usbh_clk,
+ .recalc = &follow_parent,
+};
+
/* clock derived from ahb clk */
/* apb masks structure */
static struct bus_clk_masks apb_masks = {
@@ -652,109 +767,126 @@ static struct clk pwm_clk = {
/* array of all spear 3xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
- { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+ CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
/* root clks */
- { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
- { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
+ CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+ CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
/* clock derived from 32 KHz osc clk */
- { .dev_id = "rtc-spear", .clk = &rtc_clk},
+ CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
/* clock derived from 24 MHz osc clk */
- { .con_id = "pll1_clk", .clk = &pll1_clk},
- { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
- { .dev_id = "wdt", .clk = &wdt_clk},
+ CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+ CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+ CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
/* clock derived from pll1 clk */
- { .con_id = "cpu_clk", .clk = &cpu_clk},
- { .con_id = "ahb_clk", .clk = &ahb_clk},
- { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
- { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
- { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
- { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
- { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
- { .dev_id = "uart", .clk = &uart_clk},
- { .dev_id = "firda", .clk = &firda_clk},
- { .dev_id = "gpt0", .clk = &gpt0_clk},
- { .dev_id = "gpt1", .clk = &gpt1_clk},
- { .dev_id = "gpt2", .clk = &gpt2_clk},
+ CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+ CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+ CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+ CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+ CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+ CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
+ CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+ CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
+ CLKDEV_INIT("firda", NULL, &firda_clk),
+ CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+ CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+ CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
/* clock derived from pll3 clk */
- { .dev_id = "designware_udc", .clk = &usbd_clk},
- { .con_id = "usbh_clk", .clk = &usbh_clk},
+ CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+ CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
+ /* clock derived from usbh clk */
+ CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+ CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
/* clock derived from ahb clk */
- { .con_id = "apb_clk", .clk = &apb_clk},
- { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
- { .dev_id = "dma", .clk = &dma_clk},
- { .dev_id = "jpeg", .clk = &jpeg_clk},
- { .dev_id = "gmac", .clk = &gmac_clk},
- { .dev_id = "smi", .clk = &smi_clk},
- { .dev_id = "c3", .clk = &c3_clk},
+ CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+ CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
+ CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
+ CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+ CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
+ CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+ CLKDEV_INIT("c3", NULL, &c3_clk),
/* clock derived from apb clk */
- { .dev_id = "adc", .clk = &adc_clk},
- { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
- { .dev_id = "gpio", .clk = &gpio_clk},
+ CLKDEV_INIT("adc", NULL, &adc_clk),
+ CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
+ CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
};
/* array of all spear 300 clock lookups */
#ifdef CONFIG_MACH_SPEAR300
static struct clk_lookup spear300_clk_lookups[] = {
- { .dev_id = "clcd", .clk = &clcd_clk},
- { .con_id = "fsmc", .clk = &fsmc_clk},
- { .dev_id = "gpio1", .clk = &gpio1_clk},
- { .dev_id = "keyboard", .clk = &kbd_clk},
- { .dev_id = "sdhci", .clk = &sdhci_clk},
+ CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
+ CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
+ CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
+ CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
+ CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
};
+
+void __init spear300_clk_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
+ clk_register(&spear300_clk_lookups[i]);
+
+ clk_init();
+}
#endif
/* array of all spear 310 clock lookups */
#ifdef CONFIG_MACH_SPEAR310
static struct clk_lookup spear310_clk_lookups[] = {
- { .con_id = "fsmc", .clk = &fsmc_clk},
- { .con_id = "emi", .clk = &emi_clk},
- { .dev_id = "uart1", .clk = &uart1_clk},
- { .dev_id = "uart2", .clk = &uart2_clk},
- { .dev_id = "uart3", .clk = &uart3_clk},
- { .dev_id = "uart4", .clk = &uart4_clk},
- { .dev_id = "uart5", .clk = &uart5_clk},
+ CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
+ CLKDEV_INIT(NULL, "emi", &emi_clk),
+ CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
+ CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
+ CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
+ CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
+ CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
};
+
+void __init spear310_clk_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
+ clk_register(&spear310_clk_lookups[i]);
+
+ clk_init();
+}
#endif
/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320
static struct clk_lookup spear320_clk_lookups[] = {
- { .dev_id = "clcd", .clk = &clcd_clk},
- { .con_id = "fsmc", .clk = &fsmc_clk},
- { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
- { .con_id = "emi", .clk = &emi_clk},
- { .dev_id = "pwm", .clk = &pwm_clk},
- { .dev_id = "sdhci", .clk = &sdhci_clk},
- { .dev_id = "c_can_platform.0", .clk = &can0_clk},
- { .dev_id = "c_can_platform.1", .clk = &can1_clk},
- { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
- { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
- { .dev_id = "uart1", .clk = &uart1_clk},
- { .dev_id = "uart2", .clk = &uart2_clk},
-};
-#endif
-
-void __init spear3xx_clk_init(void)
+ CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
+ CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
+ CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
+ CLKDEV_INIT(NULL, "emi", &emi_clk),
+ CLKDEV_INIT("pwm", NULL, &pwm_clk),
+ CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
+ CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
+ CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
+ CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
+ CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
+ CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
+ CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
+};
+
+void __init spear320_clk_init(void)
{
- int i, cnt;
- struct clk_lookup *lookups;
-
- if (machine_is_spear300()) {
- cnt = ARRAY_SIZE(spear300_clk_lookups);
- lookups = spear300_clk_lookups;
- } else if (machine_is_spear310()) {
- cnt = ARRAY_SIZE(spear310_clk_lookups);
- lookups = spear310_clk_lookups;
- } else {
- cnt = ARRAY_SIZE(spear320_clk_lookups);
- lookups = spear320_clk_lookups;
- }
+ int i;
for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
clk_register(&spear_clk_lookups[i]);
- for (i = 0; i < cnt; i++)
- clk_register(&lookups[i]);
+ for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
+ clk_register(&spear320_clk_lookups[i]);
clk_init();
}
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..e4f4d721cda2 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,6 +14,7 @@
#ifndef __MACH_GENERIC_H
#define __MACH_GENERIC_H
+#include <linux/amba/pl08x.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
@@ -21,26 +22,15 @@
#include <asm/mach/map.h>
#include <plat/padmux.h>
-/* spear3xx declarations */
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
-
/* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
/* Add spear3xx family function declarations here */
-void __init spear3xx_clk_init(void);
-void __init spear_setup_timer(void);
+void __init spear_setup_timer(resource_size_t base, int irq);
void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
void spear_restart(char, const char *);
@@ -99,9 +89,6 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
/* pad mux modes */
extern struct pmx_mode spear300_nand_mode;
extern struct pmx_mode spear300_nor_mode;
@@ -133,16 +120,13 @@ extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
extern struct pmx_dev spear300_pmx_gpio1;
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
- u8 pmx_dev_count);
+/* Add spear300 machine declarations here */
+void __init spear300_clk_init(void);
#endif /* CONFIG_MACH_SPEAR300 */
/* spear310 declarations */
#ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
/* pad mux devices */
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
extern struct pmx_dev spear310_pmx_emi_cs_2_3;
@@ -153,16 +137,13 @@ extern struct pmx_dev spear310_pmx_fsmc;
extern struct pmx_dev spear310_pmx_rs485_0_1;
extern struct pmx_dev spear310_pmx_tdm0;
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
- u8 pmx_dev_count);
+/* Add spear310 machine declarations here */
+void __init spear310_clk_init(void);
#endif /* CONFIG_MACH_SPEAR310 */
/* spear320 declarations */
#ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
/* pad mux modes */
extern struct pmx_mode spear320_auto_net_smii_mode;
extern struct pmx_mode spear320_auto_net_mii_mode;
@@ -193,9 +174,8 @@ extern struct pmx_dev spear320_pmx_smii0;
extern struct pmx_dev spear320_pmx_smii1;
extern struct pmx_dev spear320_pmx_i2c1;
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
- u8 pmx_dev_count);
+/* Add spear320 machine declarations here */
+void __init spear320_clk_init(void);
#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x) (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..319620a1afb4 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,15 @@
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
-/* SPEAr3xx IRQ definitions */
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
+/* FIXME: probe all these from DT */
#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
#define SPEAR3XX_IRQ_CPU_GPT1_1 2
-#define SPEAR3XX_IRQ_CPU_GPT1_2 3
-#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
-#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
-#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
-#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
-#define SPEAR3XX_IRQ_BASIC_DMA 8
-#define SPEAR3XX_IRQ_BASIC_SMI 9
-#define SPEAR3XX_IRQ_BASIC_RTC 10
-#define SPEAR3XX_IRQ_BASIC_GPIO 11
-#define SPEAR3XX_IRQ_BASIC_WDT 12
-#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
-#define SPEAR3XX_IRQ_SYS_ERROR 14
-#define SPEAR3XX_IRQ_WAKEUP_RCV 15
-#define SPEAR3XX_IRQ_JPEG 16
-#define SPEAR3XX_IRQ_IRDA 17
-#define SPEAR3XX_IRQ_ADC 18
-#define SPEAR3XX_IRQ_UART 19
-#define SPEAR3XX_IRQ_SSP 20
-#define SPEAR3XX_IRQ_I2C 21
-#define SPEAR3XX_IRQ_MAC_1 22
-#define SPEAR3XX_IRQ_MAC_2 23
-#define SPEAR3XX_IRQ_USB_DEV 24
-#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
-#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
-#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
-#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
#define SPEAR3XX_IRQ_GEN_RAS_1 28
#define SPEAR3XX_IRQ_GEN_RAS_2 29
#define SPEAR3XX_IRQ_GEN_RAS_3 30
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
#define SPEAR3XX_IRQ_VIC_END 32
-
#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
-
-/*
- * GPIO pins virtual irqs
- * Use the lowest number for the GPIO virtual IRQs base on which subarchs
- * we have compiled in
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
-#else
-#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
-#endif
-
-#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_PLGPIO_COUNT 102
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
- SPEAR3XX_PLGPIO_COUNT)
-#else
-#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
-#endif
-
-#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
-#define NR_IRQS SPEAR3XX_VIRQ_END
+#define NR_IRQS 160
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..e0ab72e61507 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,7 @@
#ifndef __MACH_MISC_REGS_H
#define __MACH_MISC_REGS_H
-#include <mach/hardware.h>
-
#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR (MISC_BASE + 0x004)
-#define PLL1_CTR (MISC_BASE + 0x008)
-#define PLL1_FRQ (MISC_BASE + 0x00C)
-#define PLL1_MOD (MISC_BASE + 0x010)
-#define PLL2_CTR (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE 2
-#define PLL_MODE_SHIFT 4
-#define PLL_MODE_MASK 0x3
-#define PLL_MODE_NORMAL 0
-#define PLL_MODE_FRACTION 1
-#define PLL_MODE_DITH_DSB 2
-#define PLL_MODE_DITH_SSB 3
-
-#define PLL2_FRQ (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT 0
-#define PLL_DIV_N_MASK 0xFF
-#define PLL_DIV_P_SHIFT 8
-#define PLL_DIV_P_MASK 0x7
-#define PLL_NORM_FDBK_M_SHIFT 24
-#define PLL_NORM_FDBK_M_MASK 0xFF
-#define PLL_DITH_FDBK_M_SHIFT 16
-#define PLL_DITH_FDBK_M_MASK 0xFFFF
-
-#define PLL2_MOD (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG (MISC_BASE + 0x020)
-#define CORE_CLK_CFG (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT 10
-#define PLL_HCLK_RATIO_MASK 0x3
-#define HCLK_PCLK_RATIO_SHIFT 8
-#define HCLK_PCLK_RATIO_MASK 0x3
-
-#define PERIP_CLK_CFG (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define UART_CLK_SHIFT 4
-#define UART_CLK_MASK 0x1
-#define FIRDA_CLK_SHIFT 5
-#define FIRDA_CLK_MASK 0x3
-#define GPT0_CLK_SHIFT 8
-#define GPT1_CLK_SHIFT 11
-#define GPT2_CLK_SHIFT 12
-#define GPT_CLK_MASK 0x1
-#define AUX_CLK_PLL3_VAL 0
-#define AUX_CLK_PLL1_VAL 1
-
-#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART_CLK_ENB 3
-#define SSP_CLK_ENB 5
-#define I2C_CLK_ENB 7
-#define JPEG_CLK_ENB 8
-#define FIRDA_CLK_ENB 10
-#define GPT1_CLK_ENB 11
-#define GPT2_CLK_ENB 12
-#define ADC_CLK_ENB 15
-#define RTC_CLK_ENB 17
-#define GPIO_CLK_ENB 18
-#define DMA_CLK_ENB 19
-#define SMI_CLK_ENB 21
-#define GMAC_CLK_ENB 23
-#define USBD_CLK_ENB 24
-#define USBH_CLK_ENB 25
-#define C3_CLK_ENB 31
-
-#define SOC_CORE_ID (MISC_BASE + 0x030)
-#define RAS_CLK_ENB (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST 8
-
-#define SOC_USER_ID (MISC_BASE + 0x03C)
-#define RAS_SOF_RST (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT 0
-#define GPT_MSCALE_MASK 0xFFF
-#define GPT_NSCALE_SHIFT 12
-#define GPT_NSCALE_MASK 0xF
-
-#define AMEM_CLK_CFG (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
-#define UART_CLK_SYNT (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB 31
-#define AUX_EQ_SEL_SHIFT 30
-#define AUX_EQ_SEL_MASK 1
-#define AUX_EQ1_SEL 0
-#define AUX_EQ2_SEL 1
-#define AUX_XSCALE_SHIFT 16
-#define AUX_XSCALE_MASK 0xFFF
-#define AUX_YSCALE_SHIFT 0
-#define AUX_YSCALE_MASK 0xFFF
-
-#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR (MISC_BASE + 0x104)
-#define BIST1_STS_RES (MISC_BASE + 0x108)
-#define BIST2_STS_RES (MISC_BASE + 0x10C)
-#define BIST3_STS_RES (MISC_BASE + 0x110)
-#define BIST4_STS_RES (MISC_BASE + 0x114)
-#define BIST5_STS_RES (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..6d4dadc67633 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,27 @@
#define __MACH_SPEAR3XX_H
#include <asm/memory.h>
-#include <mach/spear300.h>
-#include <mach/spear310.h>
-#include <mach/spear320.h>
-
-#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
-
-#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
/* ICM1 - Low speed connection */
#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
+#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
/* ML1 - Multi Layer CPU Subsystem */
#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
+#define SPEAR3XX_CPU_TMR_BASE UL(0xF0000000)
/* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear300.h
- *
- * SPEAr300 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR300
-
-#ifndef __MACH_SPEAR300_H
-#define __MACH_SPEAR300_H
-
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG 0x54
-#define SPEAR300_INT_STS_MASK_REG 0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
-
-#define SPEAR300_CLCD_BASE UL(0x60000000)
-#define SPEAR300_SDHCI_BASE UL(0x70000000)
-#define SPEAR300_NAND_0_BASE UL(0x80000000)
-#define SPEAR300_NAND_1_BASE UL(0x84000000)
-#define SPEAR300_NAND_2_BASE UL(0x88000000)
-#define SPEAR300_NAND_3_BASE UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE UL(0x90000000)
-#define SPEAR300_NOR_1_BASE UL(0x91000000)
-#define SPEAR300_NOR_2_BASE UL(0x92000000)
-#define SPEAR300_NOR_3_BASE UL(0x93000000)
-#define SPEAR300_FSMC_BASE UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
-#define SPEAR300_GPIO_BASE UL(0xA9000000)
-
-#endif /* __MACH_SPEAR300_H */
-
-#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear310.h
- *
- * SPEAr310 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR310
-
-#ifndef __MACH_SPEAR310_H
-#define __MACH_SPEAR310_H
-
-#define SPEAR310_NAND_BASE UL(0x40000000)
-#define SPEAR310_FSMC_BASE UL(0x44000000)
-#define SPEAR310_UART1_BASE UL(0xB2000000)
-#define SPEAR310_UART2_BASE UL(0xB2080000)
-#define SPEAR310_UART3_BASE UL(0xB2100000)
-#define SPEAR310_UART4_BASE UL(0xB2180000)
-#define SPEAR310_UART5_BASE UL(0xB2200000)
-#define SPEAR310_HDLC_BASE UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG 0x04
-#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
-
-#endif /* __MACH_SPEAR310_H */
-
-#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear320.h
- *
- * SPEAr320 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR320
-
-#ifndef __MACH_SPEAR320_H
-#define __MACH_SPEAR320_H
-
-#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
-#define SPEAR320_FSMC_BASE UL(0x4C000000)
-#define SPEAR320_NAND_BASE UL(0x50000000)
-#define SPEAR320_I2S_BASE UL(0x60000000)
-#define SPEAR320_SDHCI_BASE UL(0x70000000)
-#define SPEAR320_CLCD_BASE UL(0x90000000)
-#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
-#define SPEAR320_CAN0_BASE UL(0xA1000000)
-#define SPEAR320_CAN1_BASE UL(0xA2000000)
-#define SPEAR320_UART1_BASE UL(0xA3000000)
-#define SPEAR320_UART2_BASE UL(0xA4000000)
-#define SPEAR320_SSP0_BASE UL(0xA5000000)
-#define SPEAR320_SSP1_BASE UL(0xA6000000)
-#define SPEAR320_I2C_BASE UL(0xA7000000)
-#define SPEAR320_PWM_BASE UL(0xA8000000)
-#define SPEAR320_SMII0_BASE UL(0xAA000000)
-#define SPEAR320_SMII1_BASE UL(0xAB000000)
-#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG 0x04
-#define SPEAR320_INT_CLR_MASK_REG 0x04
-#define SPEAR320_INT_ENB_MASK_REG 0x08
-#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
-
-#endif /* __MACH_SPEAR320_H */
-
-#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..febcdd8d4e92 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,21 +3,62 @@
*
* SPEAr300 machine source file
*
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
#include <plat/shirq.h>
#include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE UL(0x50000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG 0x54
+#define SPEAR300_INT_STS_MASK_REG 0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
+
+#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
+
+
+/* SPEAr300 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
/* pad multiplexing support */
/* muxing registers */
@@ -423,45 +464,275 @@ static struct spear_shirq shirq_ras1 = {
},
};
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
- .gpio_base = 8,
- .irq_base = SPEAR300_GPIO1_INT_BASE,
+/* padmux devices to enable */
+static struct pmx_dev *spear300_evb_pmx_devs[] = {
+ /* spear3xx specific devices */
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp_cs,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
+
+ /* spear300 specific devices */
+ &spear300_pmx_fsmc_2_chips,
+ &spear300_pmx_clcd,
+ &spear300_pmx_telecom_sdhci_4bit,
+ &spear300_pmx_gpio1,
};
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
- {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+ {
+ .bus_id = "uart0_rx",
+ .min_signal = 2,
+ .max_signal = 2,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart0_tx",
+ .min_signal = 3,
+ .max_signal = 3,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp0_rx",
+ .min_signal = 8,
+ .max_signal = 8,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp0_tx",
+ .min_signal = 9,
+ .max_signal = 9,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "i2c_rx",
+ .min_signal = 10,
+ .max_signal = 10,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "i2c_tx",
+ .min_signal = 11,
+ .max_signal = 11,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "irda",
+ .min_signal = 12,
+ .max_signal = 12,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "adc",
+ .min_signal = 13,
+ .max_signal = 13,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "to_jpeg",
+ .min_signal = 14,
+ .max_signal = 14,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "from_jpeg",
+ .min_signal = 15,
+ .max_signal = 15,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras0_rx",
+ .min_signal = 0,
+ .max_signal = 0,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras0_tx",
+ .min_signal = 1,
+ .max_signal = 1,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras1_rx",
+ .min_signal = 2,
+ .max_signal = 2,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras1_tx",
+ .min_signal = 3,
+ .max_signal = 3,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras2_rx",
+ .min_signal = 4,
+ .max_signal = 4,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras2_tx",
+ .min_signal = 5,
+ .max_signal = 5,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras3_rx",
+ .min_signal = 6,
+ .max_signal = 6,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras3_tx",
+ .min_signal = 7,
+ .max_signal = 7,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras4_rx",
+ .min_signal = 8,
+ .max_signal = 8,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras4_tx",
+ .min_signal = 9,
+ .max_signal = 9,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras5_rx",
+ .min_signal = 10,
+ .max_signal = 10,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras5_tx",
+ .min_signal = 11,
+ .max_signal = 11,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras6_rx",
+ .min_signal = 12,
+ .max_signal = 12,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras6_tx",
+ .min_signal = 13,
+ .max_signal = 13,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras7_rx",
+ .min_signal = 14,
+ .max_signal = 14,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras7_tx",
+ .min_signal = 15,
+ .max_signal = 15,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ },
+};
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
- u8 pmx_dev_count)
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+ &pl022_plat_data),
+ OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+ &pl080_plat_data),
+ {}
+};
+
+static void __init spear300_dt_init(void)
{
- int ret = 0;
+ int ret = -EINVAL;
+
+ pl080_plat_data.slave_channels = spear300_dma_info;
+ pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
- /* call spear3xx family common init function */
- spear3xx_init();
+ of_platform_populate(NULL, of_default_bus_match_table,
+ spear300_auxdata_lookup, NULL);
/* shared irq registration */
shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
if (shirq_ras1.regs.base) {
ret = spear_shirq_register(&shirq_ras1);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ\n");
+ pr_err("Error registering Shared IRQ\n");
}
- /* pmx initialization */
- pmx_driver.mode = pmx_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = pmx_dev_count;
+ if (of_machine_is_compatible("st,spear300-evb")) {
+ /* pmx initialization */
+ pmx_driver.mode = &spear300_photo_frame_mode;
+ pmx_driver.devs = spear300_evb_pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
+
+ pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
+ if (pmx_driver.base) {
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registration failed. err no: %d\n",
+ ret);
+ /* Free Mapping, device selection already done */
+ iounmap(pmx_driver.base);
+ }
- pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
- if (pmx_driver.base) {
- ret = pmx_register(&pmx_driver);
if (ret)
- printk(KERN_ERR "padmux: registration failed. err no"
- ": %d\n", ret);
- /* Free Mapping, device selection already done */
- iounmap(pmx_driver.base);
+ pr_err("Initialization Failed");
}
}
+
+static const char * const spear300_dt_board_compat[] = {
+ "st,spear300",
+ "st,spear300-evb",
+ NULL,
+};
+
+static void __init spear300_map_io(void)
+{
+ spear3xx_map_io();
+ spear300_clk_init();
+}
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+ .map_io = spear300_map_io,
+ .init_irq = spear3xx_dt_init_irq,
+ .handle_irq = vic_handle_irq,
+ .timer = &spear3xx_timer,
+ .init_machine = spear300_dt_init,
+ .restart = spear_restart,
+ .dt_compat = spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
- /* spear3xx specific devices */
- &spear3xx_pmx_i2c,
- &spear3xx_pmx_ssp_cs,
- &spear3xx_pmx_ssp,
- &spear3xx_pmx_mii,
- &spear3xx_pmx_uart0,
-
- /* spear300 specific devices */
- &spear300_pmx_fsmc_2_chips,
- &spear300_pmx_clcd,
- &spear300_pmx_telecom_sdhci_4bit,
- &spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
- /* spear3xx specific devices */
- &spear3xx_gpio_device,
- &spear3xx_uart_device,
-
- /* spear300 specific devices */
- &spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
- /* spear3xx specific devices */
-
- /* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
- unsigned int i;
-
- /* call spear300 machine init function */
- spear300_init(&spear300_photo_frame_mode, pmx_devs,
- ARRAY_SIZE(pmx_devs));
-
- /* Add Platform Devices */
- platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
- /* Add Amba Devices */
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
- amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
- .atag_offset = 0x100,
- .map_io = spear3xx_map_io,
- .init_irq = spear3xx_init_irq,
- .handle_irq = vic_handle_irq,
- .timer = &spear3xx_timer,
- .init_machine = spear300_evb_init,
- .restart = spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..b26e41566b50 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,19 +3,84 @@
*
* SPEAr310 machine source file
*
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
#include <plat/shirq.h>
#include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
+
+#define SPEAR310_UART1_BASE UL(0xB2000000)
+#define SPEAR310_UART2_BASE UL(0xB2080000)
+#define SPEAR310_UART3_BASE UL(0xB2100000)
+#define SPEAR310_UART4_BASE UL(0xB2180000)
+#define SPEAR310_UART5_BASE UL(0xB2200000)
+#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG 0x04
+#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
+
+#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
+
+/* SPEAr310 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
+
/* pad multiplexing support */
/* muxing registers */
@@ -255,17 +320,271 @@ static struct spear_shirq shirq_intrcomm_ras = {
},
};
-/* Add spear310 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear310_evb_pmx_devs[] = {
+ /* spear3xx specific devices */
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_gpio_pin0,
+ &spear3xx_pmx_gpio_pin1,
+ &spear3xx_pmx_gpio_pin2,
+ &spear3xx_pmx_gpio_pin3,
+ &spear3xx_pmx_gpio_pin4,
+ &spear3xx_pmx_gpio_pin5,
+ &spear3xx_pmx_uart0,
+
+ /* spear310 specific devices */
+ &spear310_pmx_emi_cs_0_1_4_5,
+ &spear310_pmx_emi_cs_2_3,
+ &spear310_pmx_uart1,
+ &spear310_pmx_uart2,
+ &spear310_pmx_uart3_4_5,
+ &spear310_pmx_fsmc,
+ &spear310_pmx_rs485_0_1,
+ &spear310_pmx_tdm0,
+};
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
- u8 pmx_dev_count)
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+ {
+ .bus_id = "uart0_rx",
+ .min_signal = 2,
+ .max_signal = 2,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart0_tx",
+ .min_signal = 3,
+ .max_signal = 3,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp0_rx",
+ .min_signal = 8,
+ .max_signal = 8,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp0_tx",
+ .min_signal = 9,
+ .max_signal = 9,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "i2c_rx",
+ .min_signal = 10,
+ .max_signal = 10,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "i2c_tx",
+ .min_signal = 11,
+ .max_signal = 11,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "irda",
+ .min_signal = 12,
+ .max_signal = 12,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "adc",
+ .min_signal = 13,
+ .max_signal = 13,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "to_jpeg",
+ .min_signal = 14,
+ .max_signal = 14,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "from_jpeg",
+ .min_signal = 15,
+ .max_signal = 15,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart1_rx",
+ .min_signal = 0,
+ .max_signal = 0,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart1_tx",
+ .min_signal = 1,
+ .max_signal = 1,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart2_rx",
+ .min_signal = 2,
+ .max_signal = 2,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart2_tx",
+ .min_signal = 3,
+ .max_signal = 3,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart3_rx",
+ .min_signal = 4,
+ .max_signal = 4,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart3_tx",
+ .min_signal = 5,
+ .max_signal = 5,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart4_rx",
+ .min_signal = 6,
+ .max_signal = 6,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart4_tx",
+ .min_signal = 7,
+ .max_signal = 7,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart5_rx",
+ .min_signal = 8,
+ .max_signal = 8,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart5_tx",
+ .min_signal = 9,
+ .max_signal = 9,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras5_rx",
+ .min_signal = 10,
+ .max_signal = 10,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras5_tx",
+ .min_signal = 11,
+ .max_signal = 11,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras6_rx",
+ .min_signal = 12,
+ .max_signal = 12,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras6_tx",
+ .min_signal = 13,
+ .max_signal = 13,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras7_rx",
+ .min_signal = 14,
+ .max_signal = 14,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ras7_tx",
+ .min_signal = 15,
+ .max_signal = 15,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ },
+};
+
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+ {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart1_tx",
+ .dma_rx_param = "uart1_rx",
+ }, {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart2_tx",
+ .dma_rx_param = "uart2_rx",
+ }, {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart3_tx",
+ .dma_rx_param = "uart3_rx",
+ }, {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart4_tx",
+ .dma_rx_param = "uart4_rx",
+ }, {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart5_tx",
+ .dma_rx_param = "uart5_rx",
+ },
+};
+
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+ &pl022_plat_data),
+ OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+ &pl080_plat_data),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+ &spear310_uart_data[0]),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+ &spear310_uart_data[1]),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+ &spear310_uart_data[2]),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+ &spear310_uart_data[3]),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+ &spear310_uart_data[4]),
+ {}
+};
+
+static void __init spear310_dt_init(void)
{
void __iomem *base;
int ret = 0;
- /* call spear3xx family common init function */
- spear3xx_init();
+ pl080_plat_data.slave_channels = spear310_dma_info;
+ pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
+ of_platform_populate(NULL, of_default_bus_match_table,
+ spear310_auxdata_lookup, NULL);
/* shared irq registration */
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +593,59 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
shirq_ras1.regs.base = base;
ret = spear_shirq_register(&shirq_ras1);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 1\n");
+ pr_err("Error registering Shared IRQ 1\n");
/* shirq 2 */
shirq_ras2.regs.base = base;
ret = spear_shirq_register(&shirq_ras2);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 2\n");
+ pr_err("Error registering Shared IRQ 2\n");
/* shirq 3 */
shirq_ras3.regs.base = base;
ret = spear_shirq_register(&shirq_ras3);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 3\n");
+ pr_err("Error registering Shared IRQ 3\n");
/* shirq 4 */
shirq_intrcomm_ras.regs.base = base;
ret = spear_shirq_register(&shirq_intrcomm_ras);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 4\n");
+ pr_err("Error registering Shared IRQ 4\n");
+ }
+
+ if (of_machine_is_compatible("st,spear310-evb")) {
+ /* pmx initialization */
+ pmx_driver.base = base;
+ pmx_driver.mode = NULL;
+ pmx_driver.devs = spear310_evb_pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
+
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registration failed. err no: %d\n",
+ ret);
}
+}
- /* pmx initialization */
- pmx_driver.base = base;
- pmx_driver.mode = pmx_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear310_dt_board_compat[] = {
+ "st,spear310",
+ "st,spear310-evb",
+ NULL,
+};
- ret = pmx_register(&pmx_driver);
- if (ret)
- printk(KERN_ERR "padmux: registration failed. err no: %d\n",
- ret);
+static void __init spear310_map_io(void)
+{
+ spear3xx_map_io();
+ spear310_clk_init();
}
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+ .map_io = spear310_map_io,
+ .init_irq = spear3xx_dt_init_irq,
+ .handle_irq = vic_handle_irq,
+ .timer = &spear3xx_timer,
+ .init_machine = spear310_dt_init,
+ .restart = spear_restart,
+ .dt_compat = spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
- /* spear3xx specific devices */
- &spear3xx_pmx_i2c,
- &spear3xx_pmx_ssp,
- &spear3xx_pmx_gpio_pin0,
- &spear3xx_pmx_gpio_pin1,
- &spear3xx_pmx_gpio_pin2,
- &spear3xx_pmx_gpio_pin3,
- &spear3xx_pmx_gpio_pin4,
- &spear3xx_pmx_gpio_pin5,
- &spear3xx_pmx_uart0,
-
- /* spear310 specific devices */
- &spear310_pmx_emi_cs_0_1_4_5,
- &spear310_pmx_emi_cs_2_3,
- &spear310_pmx_uart1,
- &spear310_pmx_uart2,
- &spear310_pmx_uart3_4_5,
- &spear310_pmx_fsmc,
- &spear310_pmx_rs485_0_1,
- &spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
- /* spear3xx specific devices */
- &spear3xx_gpio_device,
- &spear3xx_uart_device,
-
- /* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
- /* spear3xx specific devices */
-
- /* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
- unsigned int i;
-
- /* call spear310 machine init function */
- spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
- /* Add Platform Devices */
- platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
- /* Add Amba Devices */
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
- amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
- .atag_offset = 0x100,
- .map_io = spear3xx_map_io,
- .init_irq = spear3xx_init_irq,
- .handle_irq = vic_handle_irq,
- .timer = &spear3xx_timer,
- .init_machine = spear310_evb_init,
- .restart = spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..2f5979b0c169 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,19 +3,85 @@
*
* SPEAr320 machine source file
*
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
#include <plat/shirq.h>
#include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
+
+#define SPEAR320_UART1_BASE UL(0xA3000000)
+#define SPEAR320_UART2_BASE UL(0xA4000000)
+#define SPEAR320_SSP0_BASE UL(0xA5000000)
+#define SPEAR320_SSP1_BASE UL(0xA6000000)
+#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG 0x04
+#define SPEAR320_INT_CLR_MASK_REG 0x04
+#define SPEAR320_INT_ENB_MASK_REG 0x08
+#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
+
+/* SPEAr320 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
/* pad multiplexing support */
/* muxing registers */
@@ -508,17 +574,271 @@ static struct spear_shirq shirq_intrcomm_ras = {
},
};
-/* Add spear320 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear320_evb_pmx_devs[] = {
+ /* spear3xx specific devices */
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
+
+ /* spear320 specific devices */
+ &spear320_pmx_fsmc,
+ &spear320_pmx_sdhci,
+ &spear320_pmx_i2s,
+ &spear320_pmx_uart1,
+ &spear320_pmx_uart2,
+ &spear320_pmx_can,
+ &spear320_pmx_pwm0,
+ &spear320_pmx_pwm1,
+ &spear320_pmx_pwm2,
+ &spear320_pmx_mii1,
+};
+
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+ {
+ .bus_id = "uart0_rx",
+ .min_signal = 2,
+ .max_signal = 2,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "uart0_tx",
+ .min_signal = 3,
+ .max_signal = 3,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp0_rx",
+ .min_signal = 8,
+ .max_signal = 8,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp0_tx",
+ .min_signal = 9,
+ .max_signal = 9,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "i2c0_rx",
+ .min_signal = 10,
+ .max_signal = 10,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "i2c0_tx",
+ .min_signal = 11,
+ .max_signal = 11,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "irda",
+ .min_signal = 12,
+ .max_signal = 12,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "adc",
+ .min_signal = 13,
+ .max_signal = 13,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "to_jpeg",
+ .min_signal = 14,
+ .max_signal = 14,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "from_jpeg",
+ .min_signal = 15,
+ .max_signal = 15,
+ .muxval = 0,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB1,
+ }, {
+ .bus_id = "ssp1_rx",
+ .min_signal = 0,
+ .max_signal = 0,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "ssp1_tx",
+ .min_signal = 1,
+ .max_signal = 1,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "ssp2_rx",
+ .min_signal = 2,
+ .max_signal = 2,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "ssp2_tx",
+ .min_signal = 3,
+ .max_signal = 3,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "uart1_rx",
+ .min_signal = 4,
+ .max_signal = 4,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "uart1_tx",
+ .min_signal = 5,
+ .max_signal = 5,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "uart2_rx",
+ .min_signal = 6,
+ .max_signal = 6,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "uart2_tx",
+ .min_signal = 7,
+ .max_signal = 7,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "i2c1_rx",
+ .min_signal = 8,
+ .max_signal = 8,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "i2c1_tx",
+ .min_signal = 9,
+ .max_signal = 9,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "i2c2_rx",
+ .min_signal = 10,
+ .max_signal = 10,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "i2c2_tx",
+ .min_signal = 11,
+ .max_signal = 11,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "i2s_rx",
+ .min_signal = 12,
+ .max_signal = 12,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "i2s_tx",
+ .min_signal = 13,
+ .max_signal = 13,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "rs485_rx",
+ .min_signal = 14,
+ .max_signal = 14,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ }, {
+ .bus_id = "rs485_tx",
+ .min_signal = 15,
+ .max_signal = 15,
+ .muxval = 1,
+ .cctl = 0,
+ .periph_buses = PL08X_AHB2,
+ },
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+ {
+ .bus_id = 1,
+ .enable_dma = 1,
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "ssp1_tx",
+ .dma_rx_param = "ssp1_rx",
+ .num_chipselect = 2,
+ }, {
+ .bus_id = 2,
+ .enable_dma = 1,
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "ssp2_tx",
+ .dma_rx_param = "ssp2_rx",
+ .num_chipselect = 2,
+ }
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+ {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart1_tx",
+ .dma_rx_param = "uart1_rx",
+ }, {
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "uart2_tx",
+ .dma_rx_param = "uart2_rx",
+ },
+};
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
- u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+ &pl022_plat_data),
+ OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+ &pl080_plat_data),
+ OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+ &spear320_ssp_data[0]),
+ OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+ &spear320_ssp_data[1]),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+ &spear320_uart_data[0]),
+ OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+ &spear320_uart_data[1]),
+ {}
+};
+
+static void __init spear320_dt_init(void)
{
void __iomem *base;
int ret = 0;
- /* call spear3xx family common init function */
- spear3xx_init();
+ pl080_plat_data.slave_channels = spear320_dma_info;
+ pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
+ of_platform_populate(NULL, of_default_bus_match_table,
+ spear320_auxdata_lookup, NULL);
/* shared irq registration */
base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +847,53 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
shirq_ras1.regs.base = base;
ret = spear_shirq_register(&shirq_ras1);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 1\n");
+ pr_err("Error registering Shared IRQ 1\n");
/* shirq 3 */
shirq_ras3.regs.base = base;
ret = spear_shirq_register(&shirq_ras3);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 3\n");
+ pr_err("Error registering Shared IRQ 3\n");
/* shirq 4 */
shirq_intrcomm_ras.regs.base = base;
ret = spear_shirq_register(&shirq_intrcomm_ras);
if (ret)
- printk(KERN_ERR "Error registering Shared IRQ 4\n");
+ pr_err("Error registering Shared IRQ 4\n");
+ }
+
+ if (of_machine_is_compatible("st,spear320-evb")) {
+ /* pmx initialization */
+ pmx_driver.base = base;
+ pmx_driver.mode = &spear320_auto_net_mii_mode;
+ pmx_driver.devs = spear320_evb_pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
+
+ ret = pmx_register(&pmx_driver);
+ if (ret)
+ pr_err("padmux: registration failed. err no: %d\n",
+ ret);
}
+}
- /* pmx initialization */
- pmx_driver.base = base;
- pmx_driver.mode = pmx_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear320_dt_board_compat[] = {
+ "st,spear320",
+ "st,spear320-evb",
+ NULL,
+};
- ret = pmx_register(&pmx_driver);
- if (ret)
- printk(KERN_ERR "padmux: registration failed. err no: %d\n",
- ret);
+static void __init spear320_map_io(void)
+{
+ spear3xx_map_io();
+ spear320_clk_init();
}
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+ .map_io = spear320_map_io,
+ .init_irq = spear3xx_dt_init_irq,
+ .handle_irq = vic_handle_irq,
+ .timer = &spear3xx_timer,
+ .init_machine = spear320_dt_init,
+ .restart = spear_restart,
+ .dt_compat = spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
- /* spear3xx specific devices */
- &spear3xx_pmx_i2c,
- &spear3xx_pmx_ssp,
- &spear3xx_pmx_mii,
- &spear3xx_pmx_uart0,
-
- /* spear320 specific devices */
- &spear320_pmx_fsmc,
- &spear320_pmx_sdhci,
- &spear320_pmx_i2s,
- &spear320_pmx_uart1,
- &spear320_pmx_uart2,
- &spear320_pmx_can,
- &spear320_pmx_pwm0,
- &spear320_pmx_pwm1,
- &spear320_pmx_pwm2,
- &spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
- /* spear3xx specific devices */
- &spear3xx_gpio_device,
- &spear3xx_uart_device,
-
- /* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
- /* spear3xx specific devices */
-
- /* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
- unsigned int i;
-
- /* call spear320 machine init function */
- spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
- ARRAY_SIZE(pmx_devs));
-
- /* Add Platform Devices */
- platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
- /* Add Amba Devices */
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
- amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
- .atag_offset = 0x100,
- .map_io = spear3xx_map_io,
- .init_irq = spear3xx_init_irq,
- .handle_irq = vic_handle_irq,
- .timer = &spear3xx_timer,
- .init_machine = spear320_evb_init,
- .restart = spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..bbb11efa6056 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,83 +3,25 @@
*
* SPEAr3XX machines common source file
*
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
#include <linux/io.h>
+#include <asm/hardware/pl080.h>
#include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
+#include <plat/pl080.h>
#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
- .gpio_base = 0,
- .irq_base = SPEAR3XX_GPIO_INT_BASE,
-};
-
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
- {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
- {SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
- /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
- vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
-struct map_desc spear3xx_io_desc[] __initdata = {
- {
- .virtual = VA_SPEAR3XX_ICM1_UART_BASE,
- .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
- .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
- .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
- .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
- .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- }, {
- .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
- .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE
- },
-};
-
-/* This will create static memory mapping for selected devices */
-void __init spear3xx_map_io(void)
-{
- iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
- /* This will initialize clock framework */
- spear3xx_clk_init();
-}
+#include <mach/spear.h>
/* pad multiplexing support */
/* devices */
@@ -506,6 +448,68 @@ struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
};
#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+ .bus_id = 0,
+ .enable_dma = 1,
+ .dma_filter = pl08x_filter_id,
+ .dma_tx_param = "ssp0_tx",
+ .dma_rx_param = "ssp0_rx",
+ /*
+ * This is number of spi devices that can be connected to spi. There are
+ * two type of chipselects on which slave devices can work. One is chip
+ * select provided by spi masters other is controlled through external
+ * gpio's. We can't use chipselect provided from spi master (because as
+ * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+ * this number now depends on number of gpios available for spi. each
+ * slave on each master requires a separate gpio pin.
+ */
+ .num_chipselect = 2,
+};
+
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+ .memcpy_channel = {
+ .bus_id = "memcpy",
+ .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+ PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+ PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+ PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+ PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+ PL080_CONTROL_PROT_SYS),
+ },
+ .lli_buses = PL08X_AHB1,
+ .mem_buses = PL08X_AHB1,
+ .get_signal = pl080_get_signal,
+ .put_signal = pl080_put_signal,
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL VIRTUAL
+ * 0xD0000000 0xFD000000
+ * 0xFC000000 0xFC000000
+ */
+struct map_desc spear3xx_io_desc[] __initdata = {
+ {
+ .virtual = VA_SPEAR3XX_ICM1_2_BASE,
+ .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+ .length = SZ_16M,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+ .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+ .length = SZ_16M,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear3xx_map_io(void)
+{
+ iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
+}
+
static void __init spear3xx_timer_init(void)
{
char pclk_name[] = "pll3_48m_clk";
@@ -530,9 +534,19 @@ static void __init spear3xx_timer_init(void)
clk_put(gpt_clk);
clk_put(pclk);
- spear_setup_timer();
+ spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1);
}
struct sys_timer spear3xx_timer = {
.init = spear3xx_timer_init,
};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+ { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+ { /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+ of_irq_init(vic_of_match);
+}
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-15 21:50:09 +0000