diff options
Diffstat (limited to 'arch/arm/mach-tegra/odm_kit')
4 files changed, 122 insertions, 48 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c index 285044034f97..fdd3b3eeffa1 100644 --- a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c +++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c @@ -141,7 +141,7 @@ static const NvU32 VoltageTable_VOUT_02[] = { // Specifies the time between each sequencer event. // Disable temporarily to keep the compiler happy. -//static const NvU32 SequencerPeriod[] = { 20, 40, 80, 160, 320, 640, 1280, 2560 }; +//static const NvU32 SequencerPeriod[] = {20, 40, 80, 160, 320, 640, 1280, 2560}; /*-- Voltage translation functions --*/ @@ -1055,6 +1055,25 @@ const Max8907bPmuSupplyInfo Max8907bSupplyInfoTable[] = AD5258_VMAX, MAX8907B_REQUESTVOLTAGE_LX_V1 }, + }, + + // FUSE Vcc is wired from VBAT. + { + Max8907bPmuSupply_VBAT_FUSE, + TCA6416_CONFIG_PORT_0, + TCA6416_INVALID_PORT, + TCA6416_INVALID_PORT, + TCA6416_PORT_0, + TCA6416_PIN_2, + NULL, + NULL, + { + NV_FALSE, + FAN5355_MIN_OUTPUT_VOLTAGE_x10/10, + FAN5355_OUTPUT_VOLTAGE_INCREMENT_x10/10, + FAN5355_MAX_OUTPUT_VOLTAGE_x10/10, + MAX8907B_REQUESTVOLTAGE_EXT_DCDC_3 + }, } }; @@ -1786,6 +1805,39 @@ Tca6416UsbVbusControl( return NV_TRUE; } +static NvBool +Tca6416FuseControl( + NvOdmPmuDeviceHandle hDevice, + NvU32 vddRail, + NvU32 MilliVolts) +{ + const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail]; + NvU32 PortNo; + NvU32 PinNo; + + // Get port number and pin number + PortNo = pSupplyInfo->OutputPort; + PinNo = pSupplyInfo->PmuGpio; + + // Configure port pin as output + if (!Tca6416ConfigPortPin(hDevice, PortNo, PinNo, GpioPinMode_Output)) + return NV_FALSE; + + if (MilliVolts == ODM_VOLTAGE_OFF) // to disable FUSE voltage + { + // Set Low on pin + if (!Tca6416WritePortPin(hDevice, PortNo, PinNo, GpioPinState_Low)) + return NV_FALSE; + } + else // to Enable FUSE voltage + { + // Set high on pin + if (!Tca6416WritePortPin(hDevice, PortNo, PinNo, GpioPinState_High)) + return NV_FALSE; + } + return NV_TRUE; +} + NvBool Max8907bSetVoltage( NvOdmPmuDeviceHandle hDevice, @@ -1802,6 +1854,15 @@ Max8907bSetVoltage( return NV_TRUE; } + if (vddRail == Max8907bPmuSupply_VBAT_FUSE) + { + // Enable fuse voltage + if (!Tca6416FuseControl(hDevice, vddRail, MilliVolts)) + return NV_FALSE; + + return NV_TRUE; + } + if ((MilliVolts == ODM_VOLTAGE_ENABLE_EXT_ONOFF) || (MilliVolts == ODM_VOLTAGE_DISABLE_EXT_ONOFF)) { diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h index 1b362aac43f4..77cf70bc32b5 100644 --- a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h +++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * */ - + #ifndef INCLUDED_MAX8907B_SUPPLY_INFO_HEADER #define INCLUDED_MAX8907B_SUPPLY_INFO_HEADER @@ -86,7 +86,7 @@ extern "C" // Defines common for all supplies I2C (s/w) sequencer selection #define MAX8907B_SEQSEL_I2CEN_LXX 7 /* I2CEN (s/w) */ -// Defines sequencer count default values +// Defines sequencer count default values #define MAX8907B_SEQCNT_DEFAULT_LX_V1 0x1C #define MAX8907B_SEQCNT_DEFAULT_LX_V2 0x1C @@ -156,7 +156,7 @@ typedef enum Max8907bPmuSupply_EXT_DCDC_3_USB1, //USB1 VBUS Max8907bPmuSupply_EXT_DCDC_3_USB3, // USB3 VBUS - /** Secondary PMU MIC2826 Rails **/ + /** Secondary PMU MIC2826 Rails **/ MIC2826PmuSupply_BUCK, MIC2826PmuSupply_LDO1, MIC2826PmuSupply_LDO2, @@ -166,6 +166,9 @@ typedef enum // potentiometer (DPM) AD5258 Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7, + //Temp for enabling fuse using p2 of i0 expander + Max8907bPmuSupply_VBAT_FUSE, + Max8907bPmuSupply_Num, Max8907bPmuSupply_Force32 = 0x7FFFFFFF } Max8907bPmuSupply; @@ -192,6 +195,5 @@ typedef struct Max8907bPmuSupplyInfoRec #if defined(__cplusplus) } #endif - #endif //INCLUDED_MAX8907B_SUPPLY_INFO_HEADER diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h index 2b5ca7f8bacd..7c3d38f7c04d 100644 --- a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h +++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h @@ -30,13 +30,12 @@ * */ - /** * @file * <b>NVIDIA APX ODM Kit:: * Implementation of the ODM Peripheral Discovery API</b> * - * @b Description: Specifies the peripheral connectivity + * @b Description: Specifies the peripheral connectivity * database NvOdmIoAddress entries for the E1116 * Power module. */ @@ -44,227 +43,233 @@ #include "pmu/max8907b/max8907b_supply_info_table.h" // Persistent voltage rail (ie, for RTC, Standby, etc...) -static const NvOdmIoAddress s_ffaRtcAddresses[] = +static const NvOdmIoAddress s_ffaRtcAddresses[] = { // On Maxim 8907B, the standby rail automatically follows V2 { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V2 } /* VDD_RTC -> RTC */ }; // Core voltage rail -static const NvOdmIoAddress s_ffaCoreAddresses[] = +static const NvOdmIoAddress s_ffaCoreAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V2 } /* VDD_CORE -> V2 */ }; // PMU CPU voltage rail -static const NvOdmIoAddress s_ffaCpuAddresses[] = +static const NvOdmIoAddress s_ffaCpuAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V1 } /* VDD_CPU_PMU -> V1 */ }; // External CPU DCDC voltage rail -static const NvOdmIoAddress s_ffaCpuExtSupplyAddresses[] = +static const NvOdmIoAddress s_ffaCpuExtSupplyAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7 } /* VDD_CPU_PMU -> DCDC7 */ }; // PLLA voltage rail -static const NvOdmIoAddress s_ffaPllAAddresses[] = +static const NvOdmIoAddress s_ffaPllAAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */ }; // PLLM voltage rail -static const NvOdmIoAddress s_ffaPllMAddresses[] = +static const NvOdmIoAddress s_ffaPllMAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLM -> VOUT2 */ }; // PLLP voltage rail -static const NvOdmIoAddress s_ffaPllPAddresses[] = +static const NvOdmIoAddress s_ffaPllPAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */ }; // PLLC voltage rail -static const NvOdmIoAddress s_ffaPllCAddresses[] = +static const NvOdmIoAddress s_ffaPllCAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */ }; // PLLE voltage rail -static const NvOdmIoAddress s_ffaPllEAddresses[] = +static const NvOdmIoAddress s_ffaPllEAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLL_E -> VOUT2 */ }; // PLLU1 voltage rail -static const NvOdmIoAddress s_ffaPllU1Addresses[] = +static const NvOdmIoAddress s_ffaPllU1Addresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLU -> VOUT2 */ }; // PLLS voltage rail -static const NvOdmIoAddress s_ffaPllSAddresses[] = +static const NvOdmIoAddress s_ffaPllSAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */ }; // PLLHD voltage rail -static const NvOdmIoAddress s_ffaPllHdmiAddresses[] = +static const NvOdmIoAddress s_ffaPllHdmiAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO6 } /* AVDD_HDMI_PLL -> VOUT6 */ }; // OSC voltage rail -static const NvOdmIoAddress s_ffaVddOscAddresses[] = +static const NvOdmIoAddress s_ffaVddOscAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* AVDD_OSC -> V3 */ }; // PLLX voltage rail -static const NvOdmIoAddress s_ffaPllXAddresses[] = +static const NvOdmIoAddress s_ffaPllXAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLX -> VOUT2 */ }; // PLL_USB voltage rail -static const NvOdmIoAddress s_ffaPllUsbAddresses[] = +static const NvOdmIoAddress s_ffaPllUsbAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO4 } /* AVDD_USB_PLL -> VOUT4 */ }; // SYS IO voltage rail -static const NvOdmIoAddress s_ffaVddSysAddresses[] = +static const NvOdmIoAddress s_ffaVddSysAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_SYS -> V3 */ }; // USB voltage rail -static const NvOdmIoAddress s_ffaVddUsbAddresses[] = +static const NvOdmIoAddress s_ffaVddUsbAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO4 } /* AVDD_USB -> VOUT4 */ }; // HDMI voltage rail -static const NvOdmIoAddress s_ffaVddHdmiAddresses[] = +static const NvOdmIoAddress s_ffaVddHdmiAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO11 } /* AVDD_HDMI -> VOUT11 */ }; // MIPI voltage rail -static const NvOdmIoAddress s_ffaVddMipiAddresses[] = +static const NvOdmIoAddress s_ffaVddMipiAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO17 } /* VDDIO_MIPI -> VOUT17 */ }; // LCD voltage rail -static const NvOdmIoAddress s_ffaVddLcdAddresses[] = +static const NvOdmIoAddress s_ffaVddLcdAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_LCD_PMU -> V3 */ }; // Audio voltage rail -static const NvOdmIoAddress s_ffaVddAudAddresses[] = +static const NvOdmIoAddress s_ffaVddAudAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_AUDIO -> V3 */ }; // LPDDR2 voltage rail (default) -static const NvOdmIoAddress s_ffaVddDdrAddresses[] = +static const NvOdmIoAddress s_ffaVddDdrAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO20 } /* VDDIO_DDR_1V2 -> VOUT20 */ }; // DDR2 voltage rail (on E1109 board ext 1.8V DCDC is controlled by LDO5) -static const NvOdmIoAddress s_ffaVddDdr2Addresses[] = +static const NvOdmIoAddress s_ffaVddDdr2Addresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO5 } /* VDDIO_DDR_1V8 -> VOUT05 */ }; // DDR_RX voltage rail -static const NvOdmIoAddress s_ffaVddDdrRxAddresses[] = +static const NvOdmIoAddress s_ffaVddDdrRxAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO1 } /* VDDIO_RX_DDR(2.7-3.3) -> VOUT1 */ }; // NAND voltage rail -static const NvOdmIoAddress s_ffaVddNandAddresses[] = +static const NvOdmIoAddress s_ffaVddNandAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_NAND_PMU -> V3 */ }; // UART voltage rail -static const NvOdmIoAddress s_ffaVddUartAddresses[] = +static const NvOdmIoAddress s_ffaVddUartAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_UART -> V3 */ }; // SDIO voltage rail -static const NvOdmIoAddress s_ffaVddSdioAddresses[] = +static const NvOdmIoAddress s_ffaVddSdioAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO12 } /* VDDIO_SDIO -> VOUT12 */ }; // VDAC voltage rail -static const NvOdmIoAddress s_ffaVddVdacAddresses[] = +static const NvOdmIoAddress s_ffaVddVdacAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO14 } /* AVDD_VDAC -> VOUT14 */ }; // VI voltage rail -static const NvOdmIoAddress s_ffaVddViAddresses[] = +static const NvOdmIoAddress s_ffaVddViAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO18 } /* VDDIO_VI -> VOUT18 */ }; // BB voltage rail -static const NvOdmIoAddress s_ffaVddBbAddresses[] = +static const NvOdmIoAddress s_ffaVddBbAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_BB -> V3 */ }; // HSIC voltage rail -static const NvOdmIoAddress s_ffaVddHsicAddresses[] = +static const NvOdmIoAddress s_ffaVddHsicAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO20 } /* VDDIO_HSIC -> VOUT20 */ }; // USB_IC voltage rail -static const NvOdmIoAddress s_ffaVddUsbIcAddresses[] = +static const NvOdmIoAddress s_ffaVddUsbIcAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* AVDD_USB_IC -> V3 */ }; // PEX_CLK voltage rail -static const NvOdmIoAddress s_ffaVddPexClkAddresses[] = +static const NvOdmIoAddress s_ffaVddPexClkAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO11 }, /* VDDIO_PEX_CLK -> VOUT11 */ { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO12 }, /* VDDIO_PEX_CLK -> VOUT12 */ - { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3 } + { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3 } }; // PMU0 -static const NvOdmIoAddress s_Pmu0Addresses[] = +static const NvOdmIoAddress s_Pmu0Addresses[] = { { NvOdmIoModule_I2c_Pmu, 0x00, 0x78 }, }; // I2C IO Expander -static const NvOdmIoAddress s_I2cioexpanderAddress[] = +static const NvOdmIoAddress s_I2cioexpanderAddress[] = { { NvOdmIoModule_I2c_Pmu, 0x00, 0x40 }, }; // USB1 VBus voltage rail -static const NvOdmIoAddress s_ffaVddUsb1VBusAddresses[] = +static const NvOdmIoAddress s_ffaVddUsb1VBusAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3_USB1 }, }; // USB3 VBus voltage rail -static const NvOdmIoAddress s_ffaVddUsb3VBusAddresses[] = +static const NvOdmIoAddress s_ffaVddUsb3VBusAddresses[] = { { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3_USB3 }, }; +// FUSE voltage enablel +static const NvOdmIoAddress s_ffaVddFuseAddresses[] = +{ + { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_VBAT_FUSE }, +}; + diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h index 5145bf5b0711..1fe3f615226b 100644 --- a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h +++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h @@ -35,7 +35,7 @@ * <b>NVIDIA APX ODM Kit:: * Implementation of the ODM Peripheral Discovery API</b> * - * @b Description: Specifies the peripheral connectivity + * @b Description: Specifies the peripheral connectivity * database Peripheral entries for the E1116 * power module. */ @@ -51,8 +51,7 @@ NV_ARRAY_SIZE(s_ffaPllU1Addresses), NvOdmPeripheralClass_Other }, -// -------- END WHISTLER_AP16_ONLY -------- - +// -------- END WHISTLER_AP16_ONLY -------- // RTC (NV reserved) { @@ -208,6 +207,13 @@ NvOdmPeripheralClass_Other }, +// Fuse +{ + NV_VDD_FUSE_ODM_ID, + s_ffaVddFuseAddresses, + NV_ARRAY_SIZE(s_ffaVddFuseAddresses), + NvOdmPeripheralClass_Other +}, // HDMI VDD (NV reserved) { |