diff options
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 421b21ac9342..401c0aaf061f 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -2,7 +2,7 @@ * arch/arm/mach-tegra/include/mach/pm.h * * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010-2012 NVIDIA Corporation + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross <ccross@google.com> @@ -33,6 +33,16 @@ #define PMC_SCRATCH1 0x54 #define PMC_SCRATCH4 0x60 +/* The following two constants are for setting the CPU freq + * floor when display is on. 204000Khz is for tablet and + * 102000KHz is for phones. The reason for different values + * for tablet and phone is due to phones usually have smart + * displays that requires less CPU activity for refreshing + * the screen + */ + +#define CPU_WAKE_FREQ_HIGH 204000 +#define CPU_WAKE_FREQ_LOW 102000 enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -65,20 +75,26 @@ struct tegra_suspend_platform_data { /* lp_state = 0 for LP0 state, 1 for LP1 state, 2 for LP2 state */ void (*board_resume)(int lp_state, enum resume_stage stg); unsigned int cpu_resume_boost; /* CPU frequency resume boost in kHz */ +#ifdef CONFIG_TEGRA_LP1_950 + bool lp1_lowvolt_support; + unsigned int i2c_base_addr; + unsigned int pmuslave_addr; + unsigned int core_reg_addr; + unsigned int lp1_core_volt_low; + unsigned int lp1_core_volt_high; +#endif + int cpu_wake_freq; }; -/* Tegra io dpd entry - for each supported driver */ -struct tegra_io_dpd { - const char *name; /* driver name */ - u8 io_dpd_reg_index; /* io dpd register index */ - u8 io_dpd_bit; /* bit position for driver in dpd register */ -}; +/* clears io dpd settings before kernel code */ +void tegra_bl_io_dpd_cleanup(void); unsigned long tegra_cpu_power_good_time(void); unsigned long tegra_cpu_power_off_time(void); unsigned long tegra_cpu_lp2_min_residency(void); void tegra_clear_cpu_in_lp2(int cpu); bool tegra_set_cpu_in_lp2(int cpu); +bool tegra_is_cpu_in_lp2(int cpu); int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags); @@ -226,6 +242,8 @@ extern bool tegra_all_cpus_booted __read_mostly; #ifdef CONFIG_TRUSTED_FOUNDATIONS void tegra_generic_smc(u32 type, u32 subtype, u32 arg); +void tegra_generic_smc_local(u32 type, u32 subtype, u32 arg); +void tegra_generic_smc_uncached(u32 type, u32 subtype, u32 arg); #endif /* The debug channel uart base physical address */ |