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-rwxr-xr-xarch/arm/plat-mxc/Makefile4
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c6
-rwxr-xr-xarch/arm/plat-mxc/cpufreq.c14
-rwxr-xr-xarch/arm/plat-mxc/devices/Makefile2
-rwxr-xr-xarch/arm/plat-mxc/devices/platform-imx-dma.c6
-rwxr-xr-xarch/arm/plat-mxc/devices/platform-mxc_gpu.c13
-rwxr-xr-xarch/arm/plat-mxc/dvfs_core.c72
-rw-r--r--arch/arm/plat-mxc/include/mach/check_fuse.h35
-rwxr-xr-xarch/arm/plat-mxc/include/mach/common.h5
-rwxr-xr-xarch/arm/plat-mxc/include/mach/devices-common.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/esdhc.h1
-rwxr-xr-xarch/arm/plat-mxc/include/mach/iomux-mx53.h4
-rwxr-xr-xarch/arm/plat-mxc/include/mach/ipu-v3.h2
-rwxr-xr-xarch/arm/plat-mxc/include/mach/memory.h4
-rwxr-xr-xarch/arm/plat-mxc/include/mach/mx53.h27
-rwxr-xr-xarch/arm/plat-mxc/include/mach/mxc.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_gpu.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/pcie.h1
-rw-r--r--arch/arm/plat-mxc/system.c17
19 files changed, 196 insertions, 30 deletions
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 1aa1780231d0..cf0457cb5237 100755
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,7 @@
#
# Common support
-obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o fuse.o
+obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o
# MX51 uses the TZIC interrupt controller, older platforms use AVIC
obj-$(CONFIG_MXC_TZIC) += tzic.o
@@ -28,7 +28,7 @@ endif
obj-y += devices/
obj-$(CONFIG_ARCH_MX5) += dvfs_core.o
-obj-$(CONFIG_ARCH_MX6) += dvfs_core.o
+obj-$(CONFIG_ARCH_MX6) += dvfs_core.o fuse.o
# DVFS-PER support
obj-$(CONFIG_MXC_DVFS_PER) += dvfs_per.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index c36ddb34c905..45fa1ef5a9b5 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -196,7 +196,9 @@ static int mxc_audmux_v2_init(void)
if (cpu_is_mx51()) {
audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
ret = 0;
- return ret;
+ } else if (cpu_is_mx53()) {
+ audmux_base = MX53_IO_ADDRESS(MX53_AUDMUX_BASE_ADDR);
+ ret = 0;
}
#endif
#if defined(CONFIG_ARCH_MX3)
@@ -228,7 +230,7 @@ static int mxc_audmux_v2_init(void)
#endif /* if defined(CONFIG_SOC_IMX25) */
audmux_debugfs_init();
- return 0;
+ return ret;
}
postcore_initcall(mxc_audmux_v2_init);
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 47a70d96b24c..bf34bf79ceea 100755
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -43,6 +43,9 @@ static struct cpufreq_frequency_table *imx_freq_table;
static int cpu_op_nr;
static struct cpu_op *cpu_op_tbl;
static u32 pre_suspend_rate;
+#ifdef CONFIG_ARCH_MX5
+int cpufreq_suspended;
+#endif
static bool cpufreq_suspend;
static struct mutex set_cpufreq_lock;
@@ -231,7 +234,12 @@ static int mxc_set_target(struct cpufreq_policy *policy,
num_cpus = num_possible_cpus();
if (policy->cpu > num_cpus)
return 0;
- if (dvfs_core_is_active) {
+
+ if (dvfs_core_is_active
+#ifdef CONFIG_ARCH_MX5
+ || cpufreq_suspended
+#endif
+ ) {
struct cpufreq_freqs freqs;
freqs.old = policy->cur;
@@ -506,10 +514,14 @@ Notify_finish:
static struct notifier_block imx_cpufreq_pm_notifier = {
.notifier_call = cpufreq_pm_notify,
};
+#ifdef CONFIG_ARCH_MX6
extern void mx6_cpu_regulator_init(void);
+#endif
static int __init mxc_cpufreq_driver_init(void)
{
+#ifdef CONFIG_ARCH_MX6
mx6_cpu_regulator_init();
+#endif
mutex_init(&set_cpufreq_lock);
register_pm_notifier(&imx_cpufreq_pm_notifier);
return cpufreq_register_driver(&mxc_driver);
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 102eeaaff38b..af3ace4c08cc 100755
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -67,4 +67,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2) += platform-imx-mipi_csi2.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA) += platform-imx-vdoa.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE) += platform-imx-pcie.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FSL_CSI) += platform-imx-fsl-csi.o
-obj-y += platform-imx-pmu.o
+obj-$(CONFIG_ARCH_MX6) += platform-imx-pmu.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index e7caaf4ce36f..b32375607b9c 100755
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -54,7 +54,7 @@ struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
#ifdef CONFIG_SOC_IMX53
struct imx_imx_sdma_data imx53_imx_sdma_data __initconst =
imx_imx_sdma_data_entry_single(MX53, 2, "imx53", 1);
-#endif /* ifdef CONFIG_SOC_IMX51 */
+#endif /* ifdef CONFIG_SOC_IMX53 */
#ifdef CONFIG_SOC_IMX6Q
struct imx_imx_sdma_data imx6q_imx_sdma_data __initconst =
@@ -160,6 +160,8 @@ static struct sdma_script_start_addrs addr_imx51_to3 = {
.app_2_mcu_addr = 683,
.shp_2_per_addr = 1251,
.shp_2_mcu_addr = 892,
+ .mcu_2_ssish_addr = 6600,
+ .ssish_2_mcu_addr = 6783,
};
#endif
@@ -175,6 +177,8 @@ static struct sdma_script_start_addrs addr_imx53_to1 = {
.shp_2_mcu_addr = 891,
.spdif_2_mcu_addr = 1100,
.mcu_2_spdif_addr = 1134,
+ .mcu_2_ssish_addr = 6242,
+ .ssish_2_mcu_addr = 6679,
};
#endif
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
index 06ac1560216a..526d5958c443 100755
--- a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -30,6 +30,8 @@
.iobase_2d = soc ## _GPU2D_BASE_ADDR, \
.gmem_base = soc ## _GPU_GMEM_BASE_ADDR, \
.gmem_size = soc ## _GPU_GMEM_SIZE, \
+ .gmem_reserved_base = 0, \
+ .gmem_reserved_size = SZ_128M, \
}
#define imx_mxc_gpu_entry_2d(soc) \
@@ -54,7 +56,7 @@ const struct imx_mxc_gpu_data imx51_gpu_data __initconst =
#endif
#ifdef CONFIG_SOC_IMX53
-const struct imx_mxc_gpu_data imx53_gpu_data __initconst =
+struct imx_mxc_gpu_data imx53_gpu_data =
imx_mxc_gpu_entry_3d_2d(MX53);
#endif
@@ -93,6 +95,13 @@ struct platform_device *__init imx_add_mxc_gpu(
.name = "gpu_graphics_mem",
.flags = IORESOURCE_MEM,
},
+ {
+ .start = data->gmem_reserved_base,
+ .end = data->gmem_reserved_base +
+ data->gmem_reserved_size - 1,
+ .name = "gpu_reserved_mem",
+ .flags = IORESOURCE_MEM,
+ },
};
return imx_add_platform_device_dmamask("mxc_gpu", 0,
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index b5cfba1a5047..bdf91df941f5 100755
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -47,6 +47,7 @@
#include <mach/hardware.h>
#include <mach/mxc_dvfs.h>
+#include <mach/clock.h>
#define MXC_DVFSTHRS_UPTHR_MASK 0x0FC00000
#define MXC_DVFSTHRS_UPTHR_OFFSET 22
@@ -84,7 +85,7 @@
#define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER 0x4
#define CCM_CDHIPR_ARM_PODF_BUSY 0x10000
-int cpufreq_trig_needed;
+static int cpufreq_trig_needed;
int dvfs_core_is_active;
static struct mxc_dvfs_platform_data *dvfs_data;
static struct device *dvfs_dev;
@@ -114,6 +115,9 @@ static struct delayed_work dvfs_core_handler;
*/
static struct clk *pll1_sw_clk;
static struct clk *cpu_clk;
+#ifdef CONFIG_ARCH_MX5
+static struct clk *gpu_clk;
+#endif
static struct clk *dvfs_clk;
static int cpu_op_nr;
@@ -190,6 +194,7 @@ static int mx5_set_cpu_freq(int op)
int podf;
int vinc = 0;
int ret = 0;
+ int retry_count = 0;
int org_cpu_rate;
unsigned long rate = 0;
int gp_volt = 0;
@@ -258,6 +263,7 @@ static int mx5_set_cpu_freq(int op)
udelay(10);
spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+ clk_set_rate(cpu_clk, rate);
if (rate < org_cpu_rate) {
ret = regulator_set_voltage(cpu_regulator, gp_volt,
gp_volt);
@@ -272,11 +278,19 @@ static int mx5_set_cpu_freq(int op)
reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
reg &= ~(CCM_CDCR_SW_DVFS_EN);
reg |= en_sw_dvfs;
- clk_set_rate(cpu_clk, rate);
} else {
podf = cpu_op_tbl[op].cpu_podf;
gp_volt = cpu_op_tbl[op].cpu_voltage;
+ /* Get ARM_PODF */
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
+ arm_podf = reg & 0x07;
+ if (podf == arm_podf) {
+ printk(KERN_DEBUG
+ "No need to change freq and voltage!!!!\n");
+ return 0;
+ }
+
/* Change arm_podf only */
/* set ARM_FREQ_SHIFT_DIVIDER */
reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
@@ -291,14 +305,6 @@ static int mx5_set_cpu_freq(int op)
reg |= CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER;
__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
- /* Get ARM_PODF */
- reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
- arm_podf = reg & 0x07;
- if (podf == arm_podf) {
- printk(KERN_DEBUG
- "No need to change freq and voltage!!!!\n");
- return 0;
- }
/* Check if FSVAI indicate freq up */
if (podf < arm_podf) {
ret = regulator_set_voltage(cpu_regulator, gp_volt,
@@ -356,7 +362,10 @@ static int mx5_set_cpu_freq(int op)
/* Wait for arm podf Enable */
while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) &
MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) {
- printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
+ if (retry_count)
+ printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
+
+ retry_count++;
udelay(10);
}
spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
@@ -586,7 +595,12 @@ static void dvfs_core_work_handler(struct work_struct *work)
int ret = 0;
int low_freq_bus_ready = 0;
int bus_incr = 0, cpu_dcr = 0;
+#ifdef CONFIG_ARCH_MX5
+ int disable_dvfs_irq = 0;
+#endif
+#ifdef CONFIG_CPU_FREQ
int cpu;
+#endif
low_freq_bus_ready = low_freq_bus_used();
@@ -599,6 +613,31 @@ static void dvfs_core_work_handler(struct work_struct *work)
goto END;
}
curr_cpu = clk_get_rate(cpu_clk);
+
+#ifdef CONFIG_ARCH_MX5
+ if (clk_get_usecount(gpu_clk)) {
+ maxf = 1;
+ if (curr_cpu != cpu_op_tbl[0].cpu_rate) {
+ curr_op = 0;
+ minf = 0;
+ dvfs_load_config(0);
+ if (!high_bus_freq_mode)
+ set_high_bus_freq(1);
+ set_cpu_freq(curr_op);
+ }
+ /* If we enable DVFS's irq, the irq will keep coming,
+ * and will consume about 3-40% cpu usage, we disable
+ * dvfs 's irq here, and let it check the status every
+ * 100 msecs. If gpu clk have count to 0, it will
+ * enable dvfs's irq let it do what it want.*/
+ schedule_delayed_work(&dvfs_core_handler,
+ msecs_to_jiffies(100));
+ disable_dvfs_irq = 1;
+ goto END;
+ } else
+ disable_dvfs_irq = 0;
+#endif
+
/* If FSVAI indicate freq down,
check arm-clk is not in lowest frequency*/
if (fsvai == FSVAI_FREQ_DECREASE) {
@@ -699,8 +738,11 @@ END:
/* Enable DVFS interrupt */
/* FSVAIM=0 */
- reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
- reg |= FSVAI_FREQ_NOCHANGE;
+#ifdef CONFIG_ARCH_MX5
+ if (!disable_dvfs_irq)
+#endif
+ reg = ((reg & ~MXC_DVFSCNTR_FSVAIM) | FSVAI_FREQ_NOCHANGE);
+
/* LBFL=1 */
reg = (reg & ~MXC_DVFSCNTR_LBFL);
reg |= MXC_DVFSCNTR_LBFL;
@@ -723,7 +765,7 @@ void stop_dvfs(void)
u32 curr_cpu;
int cpu;
#ifndef CONFIG_SMP
- unsigned long old_loops_per_jiffy;
+ u32 old_loops_per_jiffy;
#endif
if (dvfs_core_is_active) {
@@ -767,6 +809,8 @@ void stop_dvfs(void)
for (cpu = 0; cpu < num_online_cpus(); cpu++)
cpufreq_get(cpu);
#endif
+ if (cpufreq_trig_needed == 1)
+ cpufreq_trig_needed = 0;
}
spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
diff --git a/arch/arm/plat-mxc/include/mach/check_fuse.h b/arch/arm/plat-mxc/include/mach/check_fuse.h
new file mode 100644
index 000000000000..ca746fa44a73
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/check_fuse.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX5_FUSE_CHECK_H__
+#define __ARCH_ARM_MACH_MX5_FUSE_CHECK_H__
+
+#define MXC_IIM_MX5_DISABLERS_OFFSET 0x8
+#define MXC_IIM_MX5_DISABLERS_GPU_MASK 0x4
+#define MXC_IIM_MX5_DISABLERS_GPU_SHIFT 0x2
+#define MXC_IIM_MX5_DISABLERS_VPU_MASK 0x2
+#define MXC_IIM_MX5_DISABLERS_VPU_SHIFT 0x1
+
+#define FSL_OCOTP_MX5_CFG2_OFFSET 0x060
+#define FSL_OCOTP_MX5_DISABLERS_GPU_MASK 0x2000000
+#define FSL_OCOTP_MX5_DISABLERS_GPU_SHIFT 0x19
+
+int mxc_fuse_get_gpu_status(void);
+int mxc_fuse_get_vpu_status(void);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 3dfc6646307a..4bb096d65c32 100755
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -89,10 +89,15 @@ extern void mx51_efikamx_reset(void);
extern int mx53_revision(void);
extern int mx50_revision(void);
extern int mx53_display_revision(void);
+#ifdef CONFIG_ARCH_MX5
+extern int mxs_reset_block(void __iomem *, int);
+#else
extern int mxs_reset_block(void __iomem *);
+#endif
extern void early_console_setup(unsigned long base, struct clk *clk);
extern void mx6_cpu_regulator_init(void);
extern int mx6q_sabreauto_init_pfuze100(u32 int_gpio);
extern int mx6q_sabresd_init_pfuze100(u32 int_gpio);
+extern int mx6q_hdmidongle_init_wm8326(void);
extern void imx_print_silicon_rev(const char *cpu, int srev);
#endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index f6d616d0b98a..cc6f7781c31c 100755
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -429,6 +429,8 @@ struct imx_mxc_gpu_data {
resource_size_t iobase_3d;
resource_size_t gmem_base;
resource_size_t gmem_size;
+ resource_size_t gmem_reserved_base;
+ resource_size_t gmem_reserved_size;
};
struct platform_device *__init imx_add_mxc_gpu(
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
index bb15db1ecbc2..49c6fcf495ba 100644
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -35,6 +35,7 @@ struct esdhc_platform_data {
unsigned int support_8bit;
unsigned int keep_power_at_suspend;
unsigned int delay_line;
+ bool runtime_pm;
int (*platform_pad_change)(unsigned int index, int clock);
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 56bade10d581..106d6c526ce1 100755
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -870,7 +870,7 @@
#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0)
+#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h
index d5ee6afce838..f4f7a06e8b88 100755
--- a/arch/arm/plat-mxc/include/mach/ipu-v3.h
+++ b/arch/arm/plat-mxc/include/mach/ipu-v3.h
@@ -745,6 +745,8 @@ struct ipuv3_fb_platform_data {
* channel in bootloader.
*/
bool late_init;
+ int panel_width_mm; /* Display panel width in millimeters */
+ int panel_height_mm; /* Display panel height in millimeters */
};
struct imx_ipuv3_platform_data {
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index e0a08b7e298e..350ae0f9fce5 100755
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -64,7 +64,9 @@
#define CONSISTENT_DMA_SIZE SZ_4M
#else
-#if defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX6)
+#ifndef CONFIG_ZONE_DMA
+#define CONSISTENT_DMA_SIZE (64 * SZ_1M)
+#elif defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX6)
#define ARM_DMA_ZONE_SIZE (184 * SZ_1M)
#define CONSISTENT_DMA_SIZE ARM_DMA_ZONE_SIZE
#else
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 1bcddd633532..ca53d8b05615 100755
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -1,3 +1,21 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
#ifndef __MACH_MX53_H__
#define __MACH_MX53_H__
@@ -221,6 +239,12 @@
#define MX53_DMA_REQ_ASRC_DMA3 34
#define MX53_DMA_REQ_ASRC_DMA2 33
#define MX53_DMA_REQ_ASRC_DMA1 32
+#define MX53_DMA_REQ_ASRC_TX3 37
+#define MX53_DMA_REQ_ASRC_TX2 36
+#define MX53_DMA_REQ_ASRC_TX1 35
+#define MX53_DMA_REQ_ASRC_RX3 34
+#define MX53_DMA_REQ_ASRC_RX2 33
+#define MX53_DMA_REQ_ASRC_RX1 32
#define MX53_DMA_REQ_EMI_WR 31
#define MX53_DMA_REQ_EMI_RD 30
#define MX53_DMA_REQ_SSI1_TX0 29
@@ -323,7 +347,7 @@
#define MX53_INT_I2C2 63
#define MX53_INT_I2C3 64
#define MX53_INT_RESV65 65
-#define MX53_INT_RESV66 66
+#define MX53_INT_ASRC 66
#define MX53_INT_SPDIF 67
#define MX53_INT_SIM_DAT 68
#define MX53_INT_IIM 69
@@ -386,6 +410,7 @@
#define MXC_IIM_MX51_BANK_END_ADDR 0x147c
#define MXC_IIM_MX53_BANK_START_ADDR 0x0800
#define MXC_IIM_MX53_BANK_END_ADDR 0x183c
+#define MXC_IIM_MX53_BANK_AREA_0_OFFSET 0x800
#define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00
#define MXC_IIM_MX53_MAC_ADDR_OFFSET 0x24
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 75b99affc39b..c7fa3d20948c 100755
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -71,6 +71,7 @@
#define IMX_BOARD_REV_2 0x100
#define IMX_BOARD_REV_3 0x200
#define IMX_BOARD_REV_4 0x300
+#define IMX_BOARD_REV_5 0x400
#ifndef __ASSEMBLY__
extern unsigned int system_rev;
@@ -85,6 +86,7 @@ extern unsigned int system_rev;
#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_2))
#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_1))
#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_3))
+#define fuse_dev_is_available(int) (1)
#endif
#ifdef CONFIG_SOC_IMX6Q
@@ -242,6 +244,8 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx6q() (0)
# define cpu_is_mx6dl() (0)
# define cpu_is_mx6sl() (0)
+# define mx6q_revision(void) (0)
+# define mx6dl_revision(void) (0)
#endif
#ifndef __ASSEMBLY__
@@ -295,7 +299,9 @@ enum mxc_dev_type {
MXC_DEV_RV,
MXC_DEV_SORENSEN,
};
+#ifdef CONFIG_ARCH_MX6
extern int fuse_dev_is_available(enum mxc_dev_type dev);
+#endif
#endif
diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpu.h b/arch/arm/plat-mxc/include/mach/mxc_gpu.h
index a43d6ec99bfa..fbd87c6416db 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_gpu.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_gpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -17,8 +17,7 @@
struct mxc_gpu_platform_data {
int z160_revision;
- resource_size_t reserved_mem_base;
- resource_size_t reserved_mem_size;
+ int enable_mmu;
};
#endif /* __MACH_MXC_GPU_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/pcie.h b/arch/arm/plat-mxc/include/mach/pcie.h
index 775f65107978..2e8eb44be0c7 100644
--- a/arch/arm/plat-mxc/include/mach/pcie.h
+++ b/arch/arm/plat-mxc/include/mach/pcie.h
@@ -35,5 +35,6 @@ struct imx_pcie_platform_data {
unsigned int pcie_rst;
unsigned int pcie_wake_up;
unsigned int pcie_dis;
+ unsigned int pcie_power_always_on;
};
#endif /* __ASM_ARCH_IMX_PCIE_H */
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index e216f687cd89..650391c7d2dd 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -35,6 +35,8 @@
static void __iomem *wdog_base;
extern u32 enable_ldo_mode;
+extern int dvfs_core_is_active;
+extern void stop_dvfs(void);
static void arch_reset_special_mode(char mode, const char *cmd)
{
@@ -85,6 +87,21 @@ void arch_reset(char mode, const char *cmd)
return;
}
#endif
+#ifdef CONFIG_ARCH_MX51
+ /* Workaround to reset NFC_CONFIG3 register
+ * due to the chip warm reset does not reset it
+ */
+ if (cpu_is_mx53())
+ __raw_writel(0x20600, MX53_IO_ADDRESS(MX53_NFC_BASE_ADDR)+0x28);
+ if (cpu_is_mx51())
+ __raw_writel(0x20600, MX51_IO_ADDRESS(MX51_NFC_BASE_ADDR)+0x28);
+#endif
+
+#ifdef CONFIG_ARCH_MX5
+ /* Stop DVFS-CORE before reboot. */
+ if (dvfs_core_is_active)
+ stop_dvfs();
+#endif
if (cpu_is_mx1()) {
wcr_enable = (1 << 0);
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-02 19:47:41 +0000