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-rw-r--r--arch/arm/plat-mxc/clock.c21
-rw-r--r--arch/arm/plat-mxc/dptc.c78
-rw-r--r--arch/arm/plat-mxc/dvfs_core.c191
-rw-r--r--arch/arm/plat-mxc/dvfs_per.c126
-rw-r--r--arch/arm/plat-mxc/include/mach/arc_otg.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/fsl_usb.h11
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h50
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mmc.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx37.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx5x.h91
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h68
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_dvfs.h54
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h3
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c45
-rw-r--r--arch/arm/plat-mxc/iram.c5
-rw-r--r--arch/arm/plat-mxc/pwm.c2
-rw-r--r--arch/arm/plat-mxc/usb_common.c56
-rw-r--r--arch/arm/plat-mxc/utmixc.c2
21 files changed, 535 insertions, 289 deletions
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 911908164efb..d2b51a1357c1 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -4,7 +4,7 @@
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
@@ -173,14 +173,8 @@ int clk_enable(struct clk *clk)
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
- spin_lock_irqsave(&clockfw_lock, flags);
-
- ret = __clk_enable(clk);
-
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
- && (clk_get_usecount(clk) == 1)) {
+ && (clk_get_usecount(clk) == 0)) {
#if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37))
if (low_freq_bus_used() && !low_bus_freq_mode)
set_low_bus_freq();
@@ -200,6 +194,13 @@ int clk_enable(struct clk *clk)
#endif
}
+
+ spin_lock_irqsave(&clockfw_lock, flags);
+
+ ret = __clk_enable(clk);
+
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -228,12 +229,12 @@ void clk_disable(struct clk *clk)
set_low_bus_freq();
else {
if (!high_bus_freq_mode) {
- /* Currently at ow or medium set point,
+ /* Currently at low or medium set point,
* need to set to high setpoint
*/
set_high_bus_freq(0);
} else if (high_bus_freq_mode || low_bus_freq_mode) {
- /* Currently at ow or high set point,
+ /* Currently at low or high set point,
* need to set to medium setpoint
*/
set_high_bus_freq(0);
diff --git a/arch/arm/plat-mxc/dptc.c b/arch/arm/plat-mxc/dptc.c
index 6b7f5599909e..a26fd9b8d516 100644
--- a/arch/arm/plat-mxc/dptc.c
+++ b/arch/arm/plat-mxc/dptc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -67,6 +67,7 @@ enum {
struct device *dev_data0;
struct device *dev_data1;
+struct dptc_device *dptc_device_data;
/*!
* In case the MXC device has multiple DPTC modules, this structure is used to
@@ -89,6 +90,8 @@ struct dptc_device {
int curr_wp;
/* DPTC vai bits */
u32 ptvai;
+ /* The base address of the DPTC */
+ void __iomem *membase;
/* The interrupt number used by the DPTC device */
int irq;
/* DPTC platform data pointer */
@@ -104,13 +107,13 @@ static void update_dptc_wp(struct dptc_device *drv_data, u32 wp)
voltage_uV = dptc_data->dptc_wp_allfreq[wp].voltage * 1000;
__raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr0,
- dptc_data->dcvr0_reg_addr);
+ drv_data->membase + dptc_data->dcvr0_reg_addr);
__raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr1,
- dptc_data->dcvr0_reg_addr + 0x4);
+ drv_data->membase + dptc_data->dcvr0_reg_addr + 0x4);
__raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr2,
- dptc_data->dcvr0_reg_addr + 0x8);
+ drv_data->membase + dptc_data->dcvr0_reg_addr + 0x8);
__raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr3,
- dptc_data->dcvr0_reg_addr + 0xC);
+ drv_data->membase + dptc_data->dcvr0_reg_addr + 0xC);
/* Set the voltage */
ret = regulator_set_voltage(drv_data->dptc_reg, voltage_uV, voltage_uV);
@@ -130,7 +133,8 @@ static irqreturn_t dptc_irq(int irq, void *dev_id)
struct device *dev = dev_id;
struct dptc_device *drv_data = dev->driver_data;
struct mxc_dptc_data *dptc_data = dev->platform_data;
- u32 dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ u32 dptccr = __raw_readl(drv_data->membase
+ + dptc_data->dptccr_reg_addr);
u32 gpc_cntr = __raw_readl(dptc_data->gpc_cntr_reg_addr);
gpc_cntr = (gpc_cntr & dptc_data->dptccr);
@@ -145,7 +149,8 @@ static irqreturn_t dptc_irq(int irq, void *dev_id)
dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) |
(dptc_data->irq_mask);
dptccr = (dptccr & ~(dptc_data->dptc_nvcr_bit));
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, drv_data->membase
+ + dptc_data->dptccr_reg_addr);
if (drv_data->turbo_mode_active == 1)
schedule_delayed_work(&drv_data->dptc_work, 0);
@@ -162,7 +167,8 @@ static void dptc_workqueue_handler(struct work_struct *work1)
struct dptc_device *drv_data =
container_of(dptc_work_tmp, struct dptc_device, dptc_work);
struct mxc_dptc_data *dptc_data = drv_data->dptc_platform_data;
- u32 dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ u32 dptccr = __raw_readl(drv_data->membase
+ + dptc_data->dptccr_reg_addr);
switch (drv_data->ptvai) {
case DPTC_PTVAI_DECREASE:
@@ -193,7 +199,7 @@ static void dptc_workqueue_handler(struct work_struct *work1)
/* Enable DPTC and unmask its interrupt */
dptccr = (dptccr & ~(dptc_data->irq_mask)) |
dptc_data->dptc_nvcr_bit | dptc_data->dptc_enable_bit;
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr);
}
/* Start DPTC unconditionally */
@@ -228,12 +234,12 @@ static int start_dptc(struct device *dev)
dptc_data->gpc_cntr_reg_addr);
}
- dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr);
/* Enable DPTC and unmask its interrupt */
dptccr = ((dptccr & ~(dptc_data->irq_mask)) | dptc_data->enable_config);
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr);
spin_unlock_irqrestore(&drv_data->lock, flags);
@@ -257,13 +263,13 @@ static void stop_dptc(struct device *dev)
struct dptc_device *drv_data = dev->driver_data;
u32 dptccr;
- dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr);
/* disable DPTC and mask its interrupt */
dptccr = ((dptccr & ~(dptc_data->dptc_enable_bit)) |
dptc_data->irq_mask) & (~dptc_data->dptc_nvcr_bit);
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr);
/* Restore Turbo Mode voltage to highest wp */
update_dptc_wp(drv_data, 0);
@@ -304,12 +310,12 @@ void dptc_suspend(int id)
if (!drv_data->dptc_is_active)
return;
- dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr);
/* Disable DPTC and mask its interrupt */
dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | dptc_data->irq_mask;
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr);
}
EXPORT_SYMBOL(dptc_suspend);
@@ -344,20 +350,20 @@ void dptc_resume(int id)
return;
__raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr0,
- dptc_data->dcvr0_reg_addr);
+ drv_data->membase + dptc_data->dcvr0_reg_addr);
__raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr1,
- dptc_data->dcvr0_reg_addr + 0x4);
+ drv_data->membase + dptc_data->dcvr0_reg_addr + 0x4);
__raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr2,
- dptc_data->dcvr0_reg_addr + 0x8);
+ drv_data->membase + dptc_data->dcvr0_reg_addr + 0x8);
__raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr3,
- dptc_data->dcvr0_reg_addr + 0xC);
+ drv_data->membase + dptc_data->dcvr0_reg_addr + 0xC);
- dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr);
/* Enable DPTC and unmask its interrupt */
dptccr = (dptccr & ~(dptc_data->irq_mask)) | dptc_data->dptc_enable_bit;
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr);
}
EXPORT_SYMBOL(dptc_resume);
@@ -426,7 +432,6 @@ static DEVICE_ATTR(enable, 0644, dptc_show, dptc_store);
*/
static int __devinit mxc_dptc_probe(struct platform_device *pdev)
{
- struct dptc_device *dptc_device_data;
int ret = 0;
struct resource *res;
u32 dptccr = 0;
@@ -449,13 +454,16 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev)
goto err1;
}
+ dptc_device_data->membase = ioremap(res->start,
+ res->end - res->start + 1);
+
/*
* Request the DPTC interrupt
*/
dptc_device_data->irq = platform_get_irq(pdev, 0);
if (dptc_device_data->irq < 0) {
ret = dptc_device_data->irq;
- goto err1;
+ goto err2;
}
ret =
@@ -463,7 +471,7 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev)
pdev->name, &pdev->dev);
if (ret) {
printk(KERN_ERR "DPTC: Unable to attach to DPTC interrupt\n");
- goto err1;
+ goto err2;
}
dptc_device_data->curr_wp = 0;
@@ -471,7 +479,8 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev)
dptc_device_data->turbo_mode_active = 0;
dptc_device_data->ptvai = 0;
- dptccr = __raw_readl(dptc_data->dptccr_reg_addr);
+ dptccr = __raw_readl(dptc_device_data->membase
+ + dptc_data->dptccr_reg_addr);
printk(KERN_INFO "DPTC mxc_dptc_probe()\n");
@@ -487,32 +496,33 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev)
else
printk(KERN_ERR "DPTC: Pointer to DPTC table is NULL\
not started\n");
- goto err1;
+ goto err3;
}
dptc_device_data->dptc_reg = regulator_get(NULL, dptc_data->reg_id);
if (IS_ERR(dptc_device_data->dptc_reg)) {
clk_put(dptc_device_data->dptc_clk);
printk(KERN_ERR "%s: failed to get regulator\n", __func__);
- goto err1;
+ goto err3;
}
INIT_DELAYED_WORK(&dptc_device_data->dptc_work, dptc_workqueue_handler);
/* Enable Reference Circuits */
dptccr = (dptccr & ~(dptc_data->dcr_mask)) | dptc_data->init_config;
- __raw_writel(dptccr, dptc_data->dptccr_reg_addr);
+ __raw_writel(dptccr, dptc_device_data->membase
+ + dptc_data->dptccr_reg_addr);
ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr);
if (ret) {
printk(KERN_ERR
"DPTC: Unable to register sysdev entry for dptc");
- goto err1;
+ goto err3;
}
if (ret != 0) {
printk(KERN_ERR "DPTC: Unable to start");
- goto err1;
+ goto err3;
}
dptc_device_data->dptc_clk = clk_get(NULL, dptc_data->clk_id);
@@ -529,6 +539,10 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev)
return 0;
+err3:
+ free_irq(dptc_device_data->irq, &pdev->dev);
+err2:
+ iounmap(dptc_device_data->membase);
err1:
dev_err(&pdev->dev, "Failed to probe DPTC\n");
kfree(dptc_device_data);
@@ -607,6 +621,10 @@ static int __init dptc_init(void)
static void __exit dptc_cleanup(void)
{
+ free_irq(dptc_device_data->irq, NULL);
+ iounmap(dptc_device_data->membase);
+ kfree(dptc_device_data);
+
/* Unregister the device structure */
platform_driver_unregister(&mxc_dptc_driver);
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index 43d0a3a8adeb..143bc07834ed 100644
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -135,18 +135,19 @@ static void dvfs_load_config(int set_point)
reg |= dvfs_core_setpoint[set_point].downthr <<
MXC_DVFSTHRS_DNTHR_OFFSET;
reg |= dvfs_core_setpoint[set_point].panicthr;
- __raw_writel(reg, dvfs_data->dvfs_thrs_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_THRS);
reg = 0;
reg |= dvfs_core_setpoint[set_point].downcnt <<
MXC_DVFSCOUN_DNCNT_OFFSET;
reg |= dvfs_core_setpoint[set_point].upcnt << MXC_DVFSCOUN_UPCNT_OFFSET;
- __raw_writel(reg, dvfs_data->dvfs_coun_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_COUN);
/* Set EMAC value */
__raw_writel((dvfs_core_setpoint[set_point].emac <<
MXC_DVFSEMAC_EMAC_OFFSET),
- dvfs_data->dvfs_emac_reg_addr);
+ dvfs_data->membase
+ + MXC_DVFSCORE_EMAC);
}
@@ -187,14 +188,14 @@ static int set_cpu_freq(int wp)
}
spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
/* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */
- reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
reg &= 0xFFFFFFFB;
- __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
+ __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
setup_pll();
/* START the GPC main control FSM */
/* set VINC */
- reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
MXC_GPCVCR_VCNT_MASK);
@@ -202,18 +203,19 @@ static int set_cpu_freq(int wp)
reg |= 1 << MXC_GPCVCR_VINC_OFFSET;
reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
- (1 << MXC_GPCVCR_VCNT_OFFSET);
- __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr);
+ (1 << MXC_GPCVCR_VCNT_OFFSET);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
- reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK);
reg |= MXC_GPCCNTR_FUPD;
reg |= MXC_GPCCNTR_ADU;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
reg |= MXC_GPCCNTR_STRT;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
- while (__raw_readl(dvfs_data->gpc_cntr_reg_addr) & 0x4000)
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
+ & 0x4000)
udelay(10);
spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
@@ -234,13 +236,13 @@ static int set_cpu_freq(int wp)
/* Change arm_podf only */
/* set ARM_FREQ_SHIFT_DIVIDER */
- reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
reg &= 0xFFFFFFFB;
reg |= 1 << 2;
- __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
+ __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
/* Get ARM_PODF */
- reg = __raw_readl(dvfs_data->ccm_cacrr_reg_addr);
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
arm_podf = reg & 0x07;
if (podf == arm_podf) {
printk(KERN_DEBUG
@@ -268,37 +270,38 @@ static int set_cpu_freq(int wp)
reg &= 0xFFFFFFF8;
reg |= arm_podf;
- reg1 = __raw_readl(dvfs_data->ccm_cdhipr_reg_addr);
+ reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset);
if ((reg1 & 0x00010000) == 0)
- __raw_writel(reg, dvfs_data->ccm_cacrr_reg_addr);
+ __raw_writel(reg,
+ ccm_base + dvfs_data->ccm_cacrr_offset);
else {
printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
return 0;
}
/* START the GPC main control FSM */
- reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
reg |= MXC_GPCCNTR_FUPD;
/* ADU=1, select ARM domain */
reg |= MXC_GPCCNTR_ADU;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
/* set VINC */
- reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
reg &=
~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
MXC_GPCVCR_VCNT_MASK);
reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
(100 << MXC_GPCVCR_VCNT_OFFSET) |
(vinc << MXC_GPCVCR_VINC_OFFSET);
- __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
- reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD));
reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD | MXC_GPCCNTR_STRT;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
/* Wait for arm podf Enable */
- while ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) &
+ while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) &
MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) {
printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
udelay(10);
@@ -317,9 +320,9 @@ static int set_cpu_freq(int wp)
propagate_rate(pll1_sw_clk);
/* Clear the ARM_FREQ_SHIFT_DIVIDER */
- reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
reg &= 0xFFFFFFFB;
- __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
+ __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
}
#if defined(CONFIG_CPU_FREQ_IMX)
cpufreq_trig_needed = 1;
@@ -344,23 +347,23 @@ static int start_dvfs(void)
dvfs_load_config(0);
/* config reg GPC_CNTR */
- reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
reg &= ~MXC_GPCCNTR_GPCIRQM;
/* GPCIRQ=1, select ARM IRQ */
reg |= MXC_GPCCNTR_GPCIRQ_ARM;
/* ADU=1, select ARM domain */
reg |= MXC_GPCCNTR_ADU;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
/* Set PREDIV bits */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
reg = (reg & ~(dvfs_data->prediv_mask));
reg |= (dvfs_data->prediv_val) << (dvfs_data->prediv_offset);
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
/* Enable DVFS interrupt */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
/* FSVAIM=0 */
reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
/* Set MAXF, MINF */
@@ -376,12 +379,12 @@ static int start_dvfs(void)
/* Set DIV3CK */
reg = (reg & ~(dvfs_data->div3ck_mask));
reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset);
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
/* Enable DVFS */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
reg |= MXC_DVFSCNTR_DVFEN;
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
dvfs_core_is_active = 1;
@@ -416,20 +419,20 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id)
u32 reg;
/* Check if DVFS0 (ARM) id requesting for freqency/voltage update */
- if ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) & MXC_GPCCNTR_DVFS0CR) ==
- 0)
+ if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
+ & MXC_GPCCNTR_DVFS0CR) == 0)
return IRQ_NONE;
/* Mask DVFS irq */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
/* FSVAIM=1 */
reg |= MXC_DVFSCNTR_FSVAIM;
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
/* Mask GPC1 irq */
- reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
schedule_delayed_work(&dvfs_core_handler, 0);
return IRQ_HANDLED;
@@ -448,7 +451,7 @@ static void dvfs_core_work_handler(struct work_struct *work)
low_freq_bus_ready = low_freq_bus_used();
/* Check DVFS frequency adjustment interrupt status */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET;
/* Check FSVAI, FSVAI=0 is error */
if (fsvai == FSVAI_FREQ_NOCHANGE) {
@@ -520,7 +523,7 @@ static void dvfs_core_work_handler(struct work_struct *work)
END: /* Set MAXF, MINF */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK));
reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET;
reg |= minf << MXC_DVFSCNTR_MINF_OFFSET;
@@ -532,11 +535,11 @@ END: /* Set MAXF, MINF */
/* LBFL=1 */
reg = (reg & ~MXC_DVFSCNTR_LBFL);
reg |= MXC_DVFSCNTR_LBFL;
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
/*Unmask GPC1 IRQ */
- reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
reg &= ~MXC_GPCCNTR_GPCIRQM;
- __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
#if defined(CONFIG_CPU_FREQ_IMX)
if (cpufreq_trig_needed == 1) {
@@ -559,10 +562,12 @@ static void stop_dvfs(void)
if (dvfs_core_is_active) {
/* Mask dvfs irq, disable DVFS */
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
/* FSVAIM=1 */
reg |= MXC_DVFSCNTR_FSVAIM;
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
curr_wp = 0;
if (!high_bus_freq_mode)
@@ -580,9 +585,11 @@ static void stop_dvfs(void)
}
spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
- reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr);
+ reg = __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
reg = (reg & ~MXC_DVFSCNTR_DVFEN);
- __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr);
+ __raw_writel(reg, dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
@@ -610,39 +617,56 @@ void dump_dvfs_core_regs()
printk(KERN_DEBUG "diff = %d\n", diff);
printk(KERN_INFO "THRS = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS));
printk(KERN_INFO "COUNT = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x04));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x04));
printk(KERN_INFO "SIG1 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x08));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x08));
printk(KERN_INFO "SIG0 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x0c));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x0c));
printk(KERN_INFO "GPC0 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x10));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x10));
printk(KERN_INFO "GPC1 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x14));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x14));
printk(KERN_INFO "GPBT = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x18));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x18));
printk(KERN_INFO "EMAC = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x1c));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x1c));
printk(KERN_INFO "CNTR = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x20));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x20));
printk(KERN_INFO "LTR0_0 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x24));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x24));
printk(KERN_INFO "LTR0_1 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x28));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x28));
printk(KERN_INFO "LTR1_0 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x2c));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x2c));
printk(KERN_DEBUG "LTR1_1 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x30));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x30));
printk(KERN_INFO "PT0 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x34));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x34));
printk(KERN_INFO "PT1 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x38));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x38));
printk(KERN_INFO "PT2 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x3c));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x3c));
printk(KERN_INFO "PT3 = 0x%08x\n",
- __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x40));
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x40));
}
static ssize_t downthreshold_show(struct device *dev,
@@ -741,7 +765,6 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
{
int err = 0;
struct resource *res;
- int irq;
printk(KERN_INFO "mxc_dvfs_core_probe\n");
dvfs_dev = &pdev->dev;
@@ -780,22 +803,25 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
err = -ENODEV;
goto err1;
}
-
+ dvfs_data->membase = ioremap(res->start, res->end - res->start + 1);
/*
* Request the DVFS interrupt
*/
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- err = irq;
- goto err1;
+ dvfs_data->irq = platform_get_irq(pdev, 0);
+ if (dvfs_data->irq < 0) {
+ err = dvfs_data->irq;
+ goto err2;
}
/* request the DVFS interrupt */
- err = request_irq(irq, dvfs_irq, IRQF_SHARED, "dvfs", dvfs_dev);
- if (err)
+ err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs",
+ dvfs_dev);
+ if (err) {
printk(KERN_ERR
"DVFS: Unable to attach to DVFS interrupt,err = %d",
err);
+ goto err2;
+ }
clk_enable(dvfs_clk);
err = init_dvfs_controller();
@@ -809,14 +835,14 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
- return err;
+ goto err3;
}
err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr);
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
- return err;
+ goto err3;
}
@@ -824,14 +850,14 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
- return err;
+ goto err3;
}
err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr);
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
- return err;
+ goto err3;
}
/* Set the current working point. */
@@ -844,7 +870,10 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
#endif
return err;
-
+err3:
+ free_irq(dvfs_data->irq, dvfs_dev);
+err2:
+ iounmap(dvfs_data->membase);
err1:
dev_err(&pdev->dev, "Failed to probe DVFS CORE\n");
return err;
@@ -914,13 +943,15 @@ static void __exit dvfs_cleanup(void)
stop_dvfs();
/* release the DVFS interrupt */
- free_irq(MXC_INT_GPC1, NULL);
+ free_irq(dvfs_data->irq, dvfs_dev);
sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr);
/* Unregister the device structure */
platform_driver_unregister(&mxc_dvfs_core_driver);
+ iounmap(ccm_base);
+ iounmap(dvfs_data->membase);
clk_put(cpu_clk);
clk_put(dvfs_clk);
diff --git a/arch/arm/plat-mxc/dvfs_per.c b/arch/arm/plat-mxc/dvfs_per.c
index 43d0dfccff50..e57f8a2fefcd 100644
--- a/arch/arm/plat-mxc/dvfs_per.c
+++ b/arch/arm/plat-mxc/dvfs_per.c
@@ -51,15 +51,14 @@
#endif
/* DVFS PER */
-static void __iomem *dvfs_per_base;
-#define MXC_DVFS_PER_LTR0 (dvfs_per_base)
-#define MXC_DVFS_PER_LTR1 (dvfs_per_base + 0x04)
-#define MXC_DVFS_PER_LTR2 (dvfs_per_base + 0x08)
-#define MXC_DVFS_PER_LTR3 (dvfs_per_base + 0x0C)
-#define MXC_DVFS_PER_LTBR0 (dvfs_per_base + 0x10)
-#define MXC_DVFS_PER_LTBR1 (dvfs_per_base + 0x14)
-#define MXC_DVFS_PER_PMCR0 (dvfs_per_base + 0x18)
-#define MXC_DVFS_PER_PMCR1 (dvfs_per_base + 0x1C)
+#define MXC_DVFS_PER_LTR0 0x00
+#define MXC_DVFS_PER_LTR1 0x04
+#define MXC_DVFS_PER_LTR2 0x08
+#define MXC_DVFS_PER_LTR3 0x0C
+#define MXC_DVFS_PER_LTBR0 0x10
+#define MXC_DVFS_PER_LTBR1 0x14
+#define MXC_DVFS_PER_PMCR0 0x18
+#define MXC_DVFS_PER_PMCR1 0x1C
#define DRIVER_NAME "DVFSPER"
#define DVFS_PER_DEBUG 0
@@ -134,16 +133,16 @@ static void dvfs_per_load_config(void)
{
u32 reg;
- reg = __raw_readl(MXC_DVFS_PER_LTR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0);
reg &= ~MXC_DVFSLTR0_UPTHR_MASK;
reg &= ~MXC_DVFSLTR0_DNTHR_MASK;
reg |= dvfs_per_setpoint[cur_setpoint].upthr <<
MXC_DVFSLTR0_UPTHR_OFFSET;
reg |= dvfs_per_setpoint[cur_setpoint].downthr <<
MXC_DVFSLTR0_DNTHR_OFFSET;
- __raw_writel(reg, MXC_DVFS_PER_LTR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0);
- reg = __raw_readl(MXC_DVFS_PER_LTR1);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1);
reg &= ~MXC_DVFSLTR1_PNCTHR_MASK;
reg &= ~MXC_DVFSLTR1_DNCNT_MASK;
reg &= ~MXC_DVFSLTR1_UPCNT_MASK;
@@ -153,11 +152,11 @@ static void dvfs_per_load_config(void)
MXC_DVFSLTR1_UPCNT_OFFSET;
reg |= dvfs_per_setpoint[cur_setpoint].panicthr <<
MXC_DVFSLTR1_PNCTHR_OFFSET;
- __raw_writel(reg, MXC_DVFS_PER_LTR1);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1);
reg = dvfs_per_setpoint[cur_setpoint].emac <<
MXC_DVFSLTR2_EMAC_OFFSET;
- __raw_writel(reg, MXC_DVFS_PER_LTR2);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2);
}
/*!
@@ -175,29 +174,29 @@ static int init_dvfs_per_controller(void)
{
u32 reg;
- reg = __raw_readl(MXC_DVFS_PER_LTR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0);
/* DIV3CLK */
reg &= ~dvfsper_plt_data->div3_mask;
reg |= (dvfsper_plt_data->div3_div <<
dvfsper_plt_data->div3_offset);
- __raw_writel(reg, MXC_DVFS_PER_LTR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0);
- reg = __raw_readl(MXC_DVFS_PER_LTR1);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1);
/* Set load tracking buffer register source */
reg &= ~MXC_DVFSLTR1_LTBRSR;
reg |= MXC_DVFSLTR1_LTBRSR;
reg &= ~MXC_DVFSLTR1_LTBRSH;
- __raw_writel(reg, MXC_DVFS_PER_LTR1);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1);
/* Enable all the peripheral signals, but VPU and IPU panic*/
- __raw_writel(0x30000, MXC_DVFS_PER_PMCR1);
+ __raw_writel(0x30000, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1);
/* Disable weighted load tracking signals */
- __raw_writel(0, MXC_DVFS_PER_LTR3);
+ __raw_writel(0, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3);
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
reg &= ~MXC_DVFSPMCR0_DVFEV;
reg |= MXC_DVFSPMCR0_LBMI;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
/* DVFS loading config */
dvfs_per_load_config();
@@ -220,14 +219,22 @@ static void dump_dvfs_per_regs(void)
if (diff < 90000)
printk(KERN_INFO "diff = %d\n", diff);
- printk(KERN_INFO "LTRO = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR0));
- printk(KERN_INFO "LTR1 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR1));
- printk(KERN_INFO "LTR2 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR2));
- printk(KERN_INFO "LTR3 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR3));
- printk(KERN_INFO "LBTR0 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTBR0));
- printk(KERN_INFO "LBTR1 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTBR1));
- printk(KERN_INFO "PMCR0 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_PMCR0));
- printk(KERN_INFO "PMCR1 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_PMCR1));
+ printk(KERN_INFO "LTRO = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0));
+ printk(KERN_INFO "LTR1 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1));
+ printk(KERN_INFO "LTR2 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2));
+ printk(KERN_INFO "LTR3 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3));
+ printk(KERN_INFO "LBTR0 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR0));
+ printk(KERN_INFO "LBTR1 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR1));
+ printk(KERN_INFO "PMCR0 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0));
+ printk(KERN_INFO "PMCR1 = 0x%08x\n",
+ __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1));
}
#endif
@@ -240,21 +247,22 @@ static irqreturn_t dvfs_per_irq(int irq, void *dev_id)
MXC_GPCCNTR_DVFS1CR) == 0)
return IRQ_NONE;
/* Mask DVFS irq */
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
/* FSVAIM=1 */
reg |= MXC_DVFSPMCR0_FSVAIM;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
/* Mask GPC1 irq */
reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr);
reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000;
__raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr);
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
if (reg & MXC_DVFSPMCR0_LBFL) {
/* clear LBFL */
reg = (reg & ~MXC_DVFSPMCR0_LBFL);
reg |= MXC_DVFSPMCR0_LBFL;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
}
schedule_delayed_work(&dvfs_per_work, 0);
return IRQ_HANDLED;
@@ -269,7 +277,7 @@ static void dvfs_per_handler(struct work_struct *work)
int retry = 20;
/* Check DVFS frequency adjustment interrupt status */
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
fsvai = (reg & MXC_DVFSPMCR0_FSVAI_MASK) >> MXC_DVFSPMCR0_FSVAI_OFFSET;
/* Check FSVAI, FSVAI=0 is error */
if (fsvai == FSVAI_FREQ_NOCHANGE) {
@@ -290,9 +298,11 @@ static void dvfs_per_handler(struct work_struct *work)
#ifndef DVFS_SW_WORKAROUND
spin_lock_irqsave(&mxc_dvfs_per_lock, flags);
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
reg &= ~MXC_DVFSPMCR0_UDCS;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
/* Set the peripheral divider */
reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr);
@@ -367,9 +377,11 @@ static void dvfs_per_handler(struct work_struct *work)
#ifndef DVFS_SW_WORKAROUND
spin_lock_irqsave(&mxc_dvfs_per_lock, flags);
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
reg |= MXC_DVFSPMCR0_UDCS;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr);
reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK);
@@ -432,13 +444,15 @@ END:
dump_dvfs_per_regs(void)();
#endif
if (dvfs_per_is_active) {
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
/* Enable dVFS interrupt */
/* FSVAIM=0 */
reg &= ~MXC_DVFSPMCR0_FSVAI_MASK;
reg |= FSVAI_FREQ_NOCHANGE;
reg = (reg & ~MXC_DVFSPMCR0_FSVAIM);
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
/*Unmask GPC1 IRQ */
reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr);
reg &= ~MXC_GPCCNTR_GPCIRQM;
@@ -453,9 +467,9 @@ static void force_freq_change(void)
freq_increased = 0;
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
reg |= MXC_DVFSPMCR0_UDCS;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
if (cpu_is_mx51()) {
/*Change the DDR freq to 133Mhz. */
@@ -513,7 +527,8 @@ static int start(void)
if (bus_freq_scaling_is_active) {
dvfs_per_is_paused = 1;
- printk(KERN_INFO "Cannot start DVFS-PER since bus_freq_scaling is active\n");
+ printk(KERN_INFO "Cannot start DVFS-PER since bus_freq_scaling\
+ is active\n");
return 0;
}
@@ -539,7 +554,7 @@ static int start(void)
reg &= ~MXC_GPCCNTR_ADU;
__raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr);
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
/* Select ARM domain */
reg |= MXC_DVFSPMCR0_DVFIS;
/* Set the UDCS bit */
@@ -550,7 +565,7 @@ static int start(void)
/*Set the FSVAI to no_freq_change */
reg &= ~MXC_DVFSPMCR0_FSVAI_MASK;
reg |= FSVAI_FREQ_NOCHANGE << MXC_DVFSPMCR0_FSVAI_OFFSET;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
/* config reg GPC_CNTR */
reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr);
@@ -560,9 +575,9 @@ static int start(void)
__raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr);
/* Enable DVFS */
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
reg |= MXC_DVFSPMCR0_DVFEN;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0);
dvfs_per_is_active = 1;
spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags);
@@ -598,17 +613,21 @@ static void stop(void)
spin_lock_irqsave(&mxc_dvfs_per_lock, flags);
/* Mask dvfs irq, disable DVFS */
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
/* FSVAIM=1 */
reg |= MXC_DVFSPMCR0_FSVAIM;
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
if (cur_setpoint != 0)
force_freq_change();
- reg = __raw_readl(MXC_DVFS_PER_PMCR0);
+ reg = __raw_readl(dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
reg = (reg & ~MXC_DVFSPMCR0_DVFEN);
- __raw_writel(reg, MXC_DVFS_PER_PMCR0);
+ __raw_writel(reg, dvfsper_plt_data->membase
+ + MXC_DVFS_PER_PMCR0);
spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags);
clk_disable(dvfs_clk);
@@ -770,7 +789,8 @@ static int __devinit mxc_dvfsper_probe(struct platform_device *pdev)
ret = -ENODEV;
goto err1;
}
- dvfs_per_base = gpc_base + 0x1C4;
+ dvfsper_plt_data->membase = ioremap(res->start,
+ res->end - res->start + 1);
/*
* Request the DVFSPER interrupt
diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
index 1b2511079560..2a58492ccc70 100644
--- a/arch/arm/plat-mxc/include/mach/arc_otg.h
+++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
@@ -147,6 +147,7 @@
#define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/
#define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/
#define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/
+#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */
/*
* register bits
@@ -245,6 +246,7 @@
#define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */
#define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */
#define UCTRL_OPM (1 << 24) /* OTG power mask */
+#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */
#define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */
#define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */
#define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */
@@ -329,6 +331,7 @@
#define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */
#define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */
#define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */
+#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */
/* USB_PHY_CTRL_FUNC2*/
#define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3
#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0
@@ -355,6 +358,8 @@
#define ULPIVW_WDATA_SHIFT 0
#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */
-
+/* USB Clock on/off Control Register */
+#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */
+#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */
extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata);
#endif
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 742fb43592b7..990c3a00567c 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -34,6 +34,7 @@ extern int mx27_clocks_init(unsigned long fref);
extern int mx31_clocks_init(unsigned long fref);
extern int mx35_clocks_init(void);
extern int mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2);
+extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih);
extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2);
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2);
extern int mxc_init_devices(void);
diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h
index d1235fc337ff..71263360dc69 100644
--- a/arch/arm/plat-mxc/include/mach/fsl_usb.h
+++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -88,4 +88,13 @@ static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd)
writel((temp & (~(0x3f << 16))) | (0x20 << 16),
hcd->regs + FSL_SOC_USB_TXFILLTUNING);
}
+
+ /* Increase TX fifo threshold for USB+SD in Hostx */
+ if (cpu_is_mx53() && (strcmp("DR", pdata->name))) {
+ temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+ /* Change TX FIFO threshold to be 0x08 */
+ writel((temp & (~(0x3f << 16))) | (0x08 << 16),
+ hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+ }
+
}
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index e47a97bdfbd8..f48456869730 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -41,6 +41,7 @@
#define BOARD_REV_1 0x000
#define BOARD_REV_2 0x100
+#define BOARD_REV_3 0x200
#ifdef CONFIG_ARCH_MX3
#include <mach/mx3x.h>
@@ -85,6 +86,8 @@ extern unsigned int system_rev;
#ifdef CONFIG_ARCH_MX5
#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(BOARD_REV_2))
+#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(BOARD_REV_1))
+#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(BOARD_REV_3))
#endif
#include <mach/mxc.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 7cd84547658f..6beaf8cd69b5 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,33 +68,31 @@ struct pad_desc {
/*
* Use to set PAD control
*/
-#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0
-#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1
-#define PAD_CTL_NO_HYSTERESIS 0
-#define PAD_CTL_HYSTERESIS 1
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_HYS (1 << 8)
-#define PAD_CTL_PULL_DISABLED 0x0
-#define PAD_CTL_PULL_KEEPER 0xa
-#define PAD_CTL_PULL_DOWN_100K 0xc
-#define PAD_CTL_PULL_UP_47K 0xd
-#define PAD_CTL_PULL_UP_100K 0xe
-#define PAD_CTL_PULL_UP_22K 0xf
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4)
+#define PAD_CTL_PUS_360K_DOWN (0 << 4)
+#define PAD_CTL_PUS_47K_UP (1 << 4)
+#define PAD_CTL_PUS_75K_UP (1 << 4)
+#define PAD_CTL_PUS_100K_UP (2 << 4)
+#define PAD_CTL_PUS_22K_UP (3 << 4)
-#define PAD_CTL_OUTPUT_CMOS 0
-#define PAD_CTL_OUTPUT_OPEN_DRAIN 1
+#define PAD_CTL_ODE (1 << 3)
-#define PAD_CTL_DRIVE_STRENGTH_NORM 0
-#define PAD_CTL_DRIVE_STRENGTH_HIGH 1
-#define PAD_CTL_DRIVE_STRENGTH_MAX 2
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
-#define PAD_CTL_SLEW_RATE_SLOW 0
-#define PAD_CTL_SLEW_RATE_FAST 1
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
/*
- * setups a single pad:
- * - reserves the pad so that it is not claimed by another driver
- * - setups the iomux according to the configuration
+ * setups a single pad in the iomuxer
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
@@ -105,17 +103,9 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
/*
- * releases a single pad:
- * - make it available for a future use by another driver
- * - DOES NOT reconfigure the IOMUX in its reset state
+ * Initialise the iomux controller
*/
-void mxc_iomux_v3_release_pad(struct pad_desc *pad);
-
-/*
- * releases multiple pads
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 3861342d1be0..ff05850287af 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -32,6 +32,10 @@
#define PHYS_OFFSET UL(0x90000000)
#endif
+#ifdef CONFIG_ARCH_MX50
+#define PHYS_OFFSET UL(0x70000000)
+#endif
+
#ifdef CONFIG_ARCH_MX53
#define PHYS_OFFSET UL(0x70000000)
#endif
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index d563c157bad7..7be75bd5756e 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -40,6 +40,9 @@ struct mxc_mmc_platform_data {
unsigned int min_clk;
unsigned int max_clk;
unsigned int clk_flg; /* 1 clock enable, 0 not */
+ unsigned int clk_always_on; /* Needed by SDIO cards and etc */
+ unsigned int dll_override_en; /* Enable dll override delay line */
+ unsigned int dll_delay_cells; /* The number of delay cells (0-0x3f) */
unsigned int reserved:16;
unsigned int card_fixed:1;
unsigned int card_inserted_state:1;
diff --git a/arch/arm/plat-mxc/include/mach/mx37.h b/arch/arm/plat-mxc/include/mach/mx37.h
index 3013d197f206..d83bdfd8824b 100644
--- a/arch/arm/plat-mxc/include/mach/mx37.h
+++ b/arch/arm/plat-mxc/include/mach/mx37.h
@@ -225,6 +225,9 @@
#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
+#define DPTCLP_BASE_ADDR (GPC_BASE_ADDR + 0x80)
+#define DPTCGP_BASE_ADDR (GPC_BASE_ADDR + 0x100)
+#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180)
#define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4)
/*
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 5be0f426c7da..0e25133736d2 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -93,7 +93,7 @@
#endif
#ifdef CONFIG_MXC_VPU_IRAM
-#define VPU_IRAM_SIZE 0x11000
+#define VPU_IRAM_SIZE 0x14000
#else
#define VPU_IRAM_SIZE 0
#endif
@@ -129,6 +129,36 @@
#define MX51_TZIC_BASE_ADDR 0xE0000000
#define TZIC_SIZE SZ_16K
+/*
+ * AHCI SATA
+ */
+#define MX53_SATA_BASE_ADDR 0x10000000
+
+/*
+ * Databahn MX50
+ */
+#define MX50_DATABAHN_BASE_ADDR 0x14000000
+#define DATABAHN_CTL_REG19 0x4c
+#define DATABAHN_CTL_REG20 0x50
+#define DATABAHN_CTL_REG21 0x54
+#define DATABAHN_CTL_REG22 0x58
+#define DATABAHN_CTL_REG23 0x5c
+#define DATABAHN_CTL_REG42 0xa8
+#define DATABAHN_CTL_REG43 0xac
+#define DATABAHN_CTL_REG55 0xdc
+#define DATABAHN_CTL_REG63 0xFC
+#define LOWPOWER_CONTROL_MASK 0x1F
+#define LOWPOWER_AUTOENABLE_MASK 0x1F
+#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16)
+#define LOWPOWER_EXTERNAL_CNT_OFFSET 16
+#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8)
+#define LOWPOWER_INTERNAL_CNT_OFFSET 8
+#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16)
+#define LOWPOWER_REFRESH_ENABLE_OFFSET 16
+#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF
+#define LOWPOWER_REFRESH_HOLD_OFFSET 0
+
+
#define DEBUG_BASE_ADDR 0x40000000
/*MX53 + 0x2000000 */
#define DEBUG_SIZE SZ_1M
@@ -141,6 +171,22 @@
#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
+#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000)
+#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000)
+#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000)
+#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000)
+#define ELCDIF_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100A000)
+#define EPXP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100C000)
+#define DCP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100E000)
+#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000)
+#define QOSC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01012000)
+#define PERFMON_BASE_ADDR (DEBUG_BASE_ADDR + 0x01014000)
+#define SSP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01016000)
+#define ANATOP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01018000)
+
+#define MX50_NIC_BASE_ADDR (DEBUG_BASE_ADDR + 0x08000000)
+
/*
* SPBA global module enabled #0
*/
@@ -216,6 +262,7 @@
#define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
+#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */
#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180)
#define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4)
@@ -371,7 +418,7 @@
#define NFC_AXI_IO_ADDRESS(x) \
(((x) - NFC_BASE_ADDR_AXI) + NFC_BASE_ADDR_AXI_VIRT)
-#define MX53_BASE_ADDR(x) (cpu_is_mx53() ? (x) - 0x20000000 : (x))
+#define MX53_BASE_ADDR(x) (cpu_is_mx53() || cpu_is_mx50() ? (x) - 0x20000000 : (x))
#define IS_MEM_DEVICE_NONSHARED(x) 0
@@ -388,6 +435,8 @@
#define DMA_REQ_SLIM_B_TX 42 /* MX51 */
#define DMA_REQ_UART3_TX_MX51 44
#define DMA_REQ_UART3_RX_MX51 43
+#define DMA_REQ_UART3_TX_MX50 43
+#define DMA_REQ_UART3_RX_MX50 42
#define DMA_REQ_ESAI_TX 41
#define DMA_REQ_SDHC4_MX51 41
#define DMA_REQ_ESAI_RX 40
@@ -434,9 +483,13 @@
#define DMA_REQ_UART5_RX 16
#define DMA_REQ_SPDIF_TX 15
#define DMA_REQ_SPDIF_RX 14
+#define DMA_REQ_EXTREQ0_MX50 14
+#define DMA_REQ_EXTREQ1_MX50 15
/* UART2 is shared w/FIRI on MX53 */
#define DMA_REQ_FIRI_TX 13
#define DMA_REQ_FIRI_RX 12
+#define DMA_REQ_UART2_TX_MX50 13
+#define DMA_REQ_UART2_RX_MX50 12
#define DMA_REQ_SDHC4_MX53 11
#define DMA_REQ_HS_I2C_RX 11 /* MX51 */
@@ -453,7 +506,9 @@
#define DMA_REQ_SLIM_B 5 /* MX51 */
#define DMA_REQ_ATA_TX_END 4
#define DMA_REQ_ATA_TX 3
+#define DMA_REQ_UART4_TX_MX50 3
#define DMA_REQ_ATA_RX 2
+#define DMA_REQ_UART4_RX_MX50 2
#define DMA_REQ_GPC 1
#define DMA_REQ_VPU 0
@@ -481,16 +536,21 @@
#define MXC_INT_USB_H3 17
#define MXC_INT_USB_OTG 18
#define MXC_INT_SAHARA_H0 19
+#define MXC_INT_DATABAHN 19 /* MX50 */
#define MXC_INT_SAHARA_H1 20
+#define MXC_INT_ELCDIF 20 /* MX50 */
#define MXC_INT_SCC_SMN 21
+#define MXC_INT_EPXP 21 /* MX50 */
#define MXC_INT_SCC_STZ 22
#define MXC_INT_SCC_SCM 23
#define MXC_INT_SRTC_NTZ 24
#define MXC_INT_SRTC_TZ 25
#define MXC_INT_RTIC 26
#define MXC_INT_CSU 27
+#define MXC_INT_EPDC 27 /* MX50 */
#define MXC_INT_SATA 28
#define MXC_INT_SLIM_B 28 /* MX51 */
+#define MXC_INT_NIC 28 /* MX50 Perfmon IRQ */
#define MXC_INT_SSI1 29
#define MXC_INT_SSI2 30
#define MXC_INT_UART1 31
@@ -534,6 +594,10 @@
#define MXC_INT_SIM_IPB 67
#define MXC_INT_SIM_DAT 68
#define MXC_INT_IIM 69
+#define MXC_INT_ANATOP1 66 /* MX50 what's it? */
+#define MXC_INT_ANATOP2 67
+#define MXC_INT_ANATOP3 68
+#define MXC_INT_ANATOP4 69
#define MXC_INT_ATA 70
#define MXC_INT_CCM1 71
#define MXC_INT_CCM2 72
@@ -559,23 +623,46 @@
#define MXC_INT_CTI1_TG2 89
#define MXC_INT_SJC 90
#define MXC_INT_SPDIF_MX51 91
+#define MXC_INT_DCP_CHAN1_3 91 /* MX50 */
#define MXC_INT_TVE 92
+#define MXC_INT_DCP_CHAN0 92 /* MX50 */
#define MXC_INT_FIRI 93
+#define MXC_INT_DCP_CHAN0_3_SEC 93 /* MX50 */
#define MXC_INT_PWM2 94
#define MXC_INT_SLIM_EXP 95
#define MXC_INT_SSI3 96
#define MXC_INT_EMI_BOOT 97
+#define MXC_INT_RNGB_BLOCK 97 /* MX50 */
#define MXC_INT_CTI1_TG3 98
#define MXC_INT_SMC_RX 99
#define MXC_INT_VPU_IDLE 100
+#define MXC_INT_RAWNAND_BCH 100 /* MX50 */
#define MXC_INT_EMI_NFC 101
#define MXC_INT_GPU_IDLE 102
+#define MXC_INT_RAWNAND_GPMI 102 /* MX50 */
#define MXC_INT_GPIO5_LOW 103
#define MXC_INT_GPIO5_HIGH 104
#define MXC_INT_GPIO6_LOW 105
#define MXC_INT_GPIO6_HIGH 106
#define MXC_INT_GPIO7_LOW 107
#define MXC_INT_GPIO7_HIGH 108
+#define MXC_INT_MSHC 109 /* MX50 */
+#define MXC_INT_APBHDMA_CHAN0 110
+#define MXC_INT_APBHDMA_CHAN1 111
+#define MXC_INT_APBHDMA_CHAN2 112
+#define MXC_INT_APBHDMA_CHAN3 113
+#define MXC_INT_APBHDMA_CHAN4 114
+#define MXC_INT_APBHDMA_CHAN5 115
+#define MXC_INT_APBHDMA_CHAN6 116
+#define MXC_INT_APBHDMA_CHAN7 117
+#define MXC_INT_APBHDMA_CHAN8 118
+#define MXC_INT_APBHDMA_CHAN9 119
+#define MXC_INT_APBHDMA_CHAN10 120
+#define MXC_INT_APBHDMA_CHAN11 121
+#define MXC_INT_APBHDMA_CHAN12 122
+#define MXC_INT_APBHDMA_CHAN13 123
+#define MXC_INT_APBHDMA_CHAN14 124
+#define MXC_INT_APBHDMA_CHAN15 125
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x00
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a47e599c54d4..808adf67552d 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -34,6 +34,7 @@
#define MXC_CPU_MX37 37
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
+#define MXC_CPU_MX50 50
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
@@ -147,6 +148,18 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx53() (0)
#endif
+#ifdef CONFIG_ARCH_MX50
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX50
+# endif
+# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
+#else
+# define cpu_is_mx50() (0)
+#endif
+
#define cpu_is_mx32() (0)
/*
@@ -222,6 +235,7 @@ struct mxc_ipu_config {
int rev;
void (*reset) (void);
struct clk *di_clk[2];
+ struct clk *csi_clk[2];
};
struct mxc_ir_platform_data {
@@ -292,6 +306,7 @@ struct mxc_lightsensor_platform_data {
struct mxc_fb_platform_data {
struct fb_videomode *mode;
+ int num_modes;
char *mode_str;
u32 interface_pix_fmt;
};
@@ -306,8 +321,32 @@ struct mxc_lcd_platform_data {
struct ccwmx51_lcd_pdata {
int vif;
struct mxc_fb_platform_data fb_pdata;
- void (*reset) (void);
- void (*bl_enable) (int);
+ void (*init) (int);
+ void (*deinit) (int);
+ void (*bl_enable) (int, int);
+};
+
+struct mxc_epdc_fb_mode {
+ struct fb_videomode *vmode;
+ int vscan_holdoff;
+ int sdoed_width;
+ int sdoed_delay;
+ int sdoez_width;
+ int sdoez_delay;
+ int gdclk_hp_offs;
+ int gdsp_offs;
+ int gdoe_offs;
+ int gdclk_offs;
+ int num_ce;
+};
+
+struct mxc_epdc_fb_platform_data {
+ struct mxc_epdc_fb_mode *epdc_mode;
+ int num_modes;
+ void (*get_pins) (void);
+ void (*put_pins) (void);
+ void (*enable_pins) (void);
+ void (*disable_pins) (void);
};
struct mxc_tsc_platform_data {
@@ -346,6 +385,7 @@ struct mxc_camera_platform_data {
char *gpo_regulator;
u32 mclk;
u32 csi;
+ void (*pwdn) (int pwdn);
};
/*gpo1-3 is in fixed state by hardware design,
@@ -465,10 +505,20 @@ struct tve_platform_data {
char *dig_reg;
};
+struct ldb_platform_data {
+ char *lvds_bg_reg;
+ u32 ext_ref;
+};
+
struct mxc_vpu_platform_data {
void (*reset) (void);
};
+struct mxc_esai_platform_data {
+ void (*activate_esai_ports) (void);
+ void (*deactivate_esai_ports) (void);
+};
+
/* The name that links the i.MX NAND Flash Controller driver to its devices. */
#define IMX_NFC_DRIVER_NAME ("imx_nfc")
@@ -584,6 +634,18 @@ struct mxc_sim_platform_data {
unsigned int detect; /* 1 have detect pin, 0 not */
};
+struct fsl_otp_data {
+ char **fuse_name;
+ char *regulator_name;
+ unsigned int fuse_num;
+};
+
+struct mxs_dma_plat_data {
+ unsigned int burst8:1;
+ unsigned int burst:1;
+ unsigned int chan_base;
+ unsigned int chan_num;
+};
#endif /* __ASSEMBLY__ */
#define MUX_IO_P 29
@@ -649,7 +711,7 @@ void gpio_deactivate_esai_ports(void);
#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
#endif
-#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53())
+#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50())
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
index fd0179b4d8f9..05c6ea4bda77 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -35,6 +35,7 @@
#include <linux/device.h>
extern void __iomem *gpc_base;
+extern void __iomem *ccm_base;
#define MXC_GPCCNTR_GPCIRQ2M (1 << 25)
#define MXC_GPCCNTR_GPCIRQ2 (1 << 24)
@@ -101,6 +102,25 @@ extern void __iomem *gpc_base;
#define MXC_DVFSPMCR1_P4PM 0x00020000
#define MXC_DVFSPMCR1_P2PM 0x00010000
+/* DVFS CORE register offsets*/
+#define MXC_DVFSCORE_THRS 0x00
+#define MXC_DVFSCORE_COUN 0x04
+#define MXC_DVFSCORE_SIG1 0x08
+#define MXC_DVFSCORE_SIG0 0x0C
+#define MXC_DVFSCORE_GPC0 0x10
+#define MXC_DVFSCORE_GPC1 0x14
+#define MXC_DVFSCORE_GPBT 0x18
+#define MXC_DVFSCORE_EMAC 0x1C
+#define MXC_DVFSCORE_CNTR 0x20
+#define MXC_DVFSCORE_LTR0_0 0x24
+#define MXC_DVFSCORE_LTR0_1 0x28
+#define MXC_DVFSCORE_LTR1_0 0x2C
+#define MXC_DVFSCORE_LTR1_1 0x30
+#define MXC_DVFSCORE_PT0 0x34
+#define MXC_DVFSCORE_PT1 0x38
+#define MXC_DVFSCORE_PT2 0x3C
+#define MXC_DVFSCORE_PT3 0x40
+
/*
* DVFS structure
*/
@@ -120,24 +140,20 @@ struct mxc_dvfs_platform_data {
char *clk1_id;
/* DVFS clock name string */
char *clk2_id;
- /* GPC control reg address */
- void __iomem *gpc_cntr_reg_addr;
- /* GPC voltage counter reg address */
- void __iomem *gpc_vcr_reg_addr;
- /* CCM DVFS control reg address */
- void __iomem *ccm_cdcr_reg_addr;
- /* CCM ARM clock root reg address */
- void __iomem *ccm_cacrr_reg_addr;
- /* CCM divider handshake in-progree reg address */
- void __iomem *ccm_cdhipr_reg_addr;
- /* DVFS threshold reg address */
- void __iomem *dvfs_thrs_reg_addr;
- /* DVFS counters reg address */
- void __iomem *dvfs_coun_reg_addr;
- /* DVFS EMAC reg address */
- void __iomem *dvfs_emac_reg_addr;
- /* DVFS control reg address */
- void __iomem *dvfs_cntr_reg_addr;
+ /* The base address of the DVFS core */
+ void __iomem *membase;
+ /* The interrupt number used by the DVFS core */
+ int irq;
+ /* GPC control reg offset */
+ int gpc_cntr_offset;
+ /* GPC voltage counter reg offset */
+ int gpc_vcr_offset;
+ /* CCM DVFS control reg offset */
+ int ccm_cdcr_offset;
+ /* CCM ARM clock root reg offset */
+ int ccm_cacrr_offset;
+ /* CCM divider handshake in-progress reg offset */
+ int ccm_cdhipr_offset;
/* PREDIV mask */
u32 prediv_mask;
/* PREDIV offset */
@@ -182,6 +198,8 @@ struct mxc_dvfsper_data {
char *reg_id;
/* DVFS clock name string */
char *clk_id;
+ /* The base address of the DVFS per */
+ void __iomem *membase;
/* GPC control reg address */
void __iomem *gpc_cntr_reg_addr;
/* GPC VCR reg address */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 126bc8713159..604abbc77da0 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,5 +24,6 @@
extern void arch_idle(void);
void arch_reset(char mode, const char *cmd);
+int mxs_reset_block(void __iomem *hwreg, int just_enable);
#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 77a078f9513f..b318c6a222d5 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,30 +29,22 @@
#include <asm/mach/map.h>
#include <mach/iomux-v3.h>
-#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
-
-static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
+static void __iomem *base;
/*
- * setups a single pin:
- * - reserves the pin so that it is not claimed by another driver
- * - setups the iomux according to the configuration
+ * setups a single pad in the iomuxer
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
{
- unsigned int pad_ofs = pad->pad_ctrl_ofs;
-
- if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
- return -EBUSY;
if (pad->mux_ctrl_ofs)
- __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
+ __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
if (pad->select_input_ofs)
__raw_writel(pad->select_input,
- IOMUX_BASE + pad->select_input_ofs);
+ base + pad->select_input_ofs);
- if (!(pad->pad_ctrl & NO_PAD_CTRL))
- __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
+ if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
+ __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
return 0;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -66,33 +58,14 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
for (i = 0; i < count; i++) {
ret = mxc_iomux_v3_setup_pad(p);
if (ret)
- goto setup_error;
+ return ret;
p++;
}
return 0;
-
-setup_error:
- mxc_iomux_v3_release_multiple_pads(pad_list, i);
- return ret;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
-void mxc_iomux_v3_release_pad(struct pad_desc *pad)
-{
- unsigned int pad_ofs = pad->pad_ctrl_ofs;
-
- clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
-}
-EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
-
-void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{
- struct pad_desc *p = pad_list;
- int i;
-
- for (i = 0; i < count; i++) {
- mxc_iomux_v3_release_pad(p);
- p++;
- }
+ base = iomux_v3_base;
}
-EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
diff --git a/arch/arm/plat-mxc/iram.c b/arch/arm/plat-mxc/iram.c
index 3d2a391bd2d1..c63b0a2a9a10 100644
--- a/arch/arm/plat-mxc/iram.c
+++ b/arch/arm/plat-mxc/iram.c
@@ -36,6 +36,11 @@ void *iram_alloc(unsigned int size, unsigned long *dma_addr)
*dma_addr = gen_pool_alloc(iram_pool, size);
pr_debug("iram alloc - %dB@0x%p\n", size, (void *)*dma_addr);
+
+ WARN_ON(!*dma_addr);
+ if (!*dma_addr)
+ return NULL;
+
return iram_phys_to_virt(*dma_addr);
}
EXPORT_SYMBOL(iram_alloc);
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index f159feb01f83..77eb52ce477c 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -61,7 +61,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
return -EINVAL;
- if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx51() || cpu_is_mx53()) {
+ if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx5()) {
unsigned long long c;
unsigned long period_cycles, duty_cycles, prescale;
c = clk_get_rate(pwm->clk);
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
index 2f5f597f806e..71583e465046 100644
--- a/arch/arm/plat-mxc/usb_common.c
+++ b/arch/arm/plat-mxc/usb_common.c
@@ -275,21 +275,25 @@ static void usbh1_set_utmi_xcvr(void)
while ((UH1_USBCMD) & (UCMD_RESET))
;
- /* MX53 EVK is not using OC */
- USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS;
-
- USBCTRL &= ~UCTRL_H1PM; /* OTG Power Mask */
- USBCTRL &= ~UCTRL_H1WIE; /* OTG Wakeup Intr Disable */
-
- /* Over current disable */
- USB_PHY_CTR_FUNC |= (0x1 << 5);
-
+ /* For OC and PWR, it is board level setting
+ * The default setting is for mx53 evk
+ */
+ USBCTRL &= ~UCTRL_H1PM; /* Host1 Power Mask */
+ USBCTRL &= ~UCTRL_H1WIE; /* Host1 Wakeup Intr Disable */
+ USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* Over current disable */
+
+ if (machine_is_mx50_arm2()) {
+ USBCTRL |= UCTRL_H1PM; /* Host1 Power Mask */
+ USB_PHY_CTR_FUNC &= ~USB_UH1_OC_DIS; /* Over current enable */
+ /* Over current polarity low active */
+ USB_PHY_CTR_FUNC |= USB_UH1_OC_POL;
+ }
/* set UTMI xcvr */
tmp = UH1_PORTSC1 & ~PORTSC_PTS_MASK;
tmp |= PORTSC_PTS_UTMI;
UH1_PORTSC1 = tmp;
- /* Set the PHY clock to 19.2MHz */
+ /* Set the PHY clock to 24MHz */
USBH1_PHY_CTRL1 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK;
USBH1_PHY_CTRL1 |= 0x01;
@@ -428,14 +432,7 @@ static int usb_register_remote_wakeup(struct platform_device *pdev)
int irq;
pr_debug("%s: pdev=0x%p \n", __func__, pdev);
- if (!cpu_is_mx51() && !cpu_is_mx25())
- return -ECANCELED;
-
- /* The Host2 USB controller On mx25 platform
- * is no path available from internal USB FS
- * PHY to FS PHY wake up interrupt, So to
- * remove the function of USB Remote Wakeup on Host2 */
- if (cpu_is_mx25() && (!strcmp("Host 2", pdata->name)))
+ if (!(pdata->wake_up_enable))
return -ECANCELED;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -485,6 +482,10 @@ int fsl_usb_host_init(struct platform_device *pdev)
clk_put(usboh3_clk);
}
+ if (cpu_is_mx50())
+ /* Turn on AHB CLK for H1*/
+ USB_CLKONOFF_CTRL &= ~H1_AHBCLK_OFF;
+
/* enable board power supply for xcvr */
if (pdata->xcvr_pwr) {
if (pdata->xcvr_pwr->regu1)
@@ -704,6 +705,11 @@ static void otg_set_utmi_xcvr(void)
} else if (cpu_is_mx25()) {
USBCTRL |= UCTRL_OCPOL;
USBCTRL &= ~UCTRL_PP;
+ } else if (cpu_is_mx50()) {
+ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
+ if (machine_is_mx50_arm2())
+ /* OTG Power pin polarity low */
+ USBCTRL |= UCTRL_O_PWR_POL;
} else {
/* USBOTG_PWR low active */
USBCTRL &= ~UCTRL_PP;
@@ -715,8 +721,9 @@ static void otg_set_utmi_xcvr(void)
USBCTRL |= UCTRL_OLOCKD;
}
- if (!cpu_is_mx53())
+ if (cpu_is_mx51())
USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */
+
USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */
/* set UTMI xcvr */
@@ -793,9 +800,12 @@ int usbotg_init(struct platform_device *pdev)
pdata->xcvr_type = xops->xcvr_type;
pdata->pdev = pdev;
+ if (fsl_check_usbclk() != 0)
+ return -EINVAL;
if (!otg_used) {
- if (fsl_check_usbclk() != 0)
- return -EINVAL;
+ if (cpu_is_mx50())
+ /* Turn on AHB CLK for OTG*/
+ USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF;
pr_debug("%s: grab pins\n", __func__);
if (pdata->gpio_usb_active && pdata->gpio_usb_active())
@@ -871,8 +881,8 @@ int usb_host_wakeup_irq(struct device *wkup_dev)
wakeup_req = USBCTRL & UCTRL_H1WIR;
} else if (!strcmp("DR", pdata->name)) {
wakeup_req = USBCTRL & UCTRL_OWIR;
- /* If DR is in device mode, let udc handle it */
- if (wakeup_req && ((UOG_USBMODE & 0x3) == 0x2))
+ /* If not ID wakeup, let udc handle it */
+ if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID))
wakeup_req = 0;
}
diff --git a/arch/arm/plat-mxc/utmixc.c b/arch/arm/plat-mxc/utmixc.c
index 6a13e8fbbe70..59207ab9ff67 100644
--- a/arch/arm/plat-mxc/utmixc.c
+++ b/arch/arm/plat-mxc/utmixc.c
@@ -73,6 +73,8 @@ static void set_power(struct fsl_xcvr_ops *this,
regulator_put(usbotg_regux);
}
}
+ if (pdata && pdata->platform_driver_vbus)
+ pdata->platform_driver_vbus(on);
}
static struct fsl_xcvr_ops utmi_ops = {
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-01 17:29:50 +0000