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Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/ehci.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 4bac3d5545d3..b79c8090197c 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -115,7 +115,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
#endif /* if defined(CONFIG_SOC_IMX25) */
#if defined(CONFIG_ARCH_MX3)
if (cpu_is_mx31()) {
- v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
+ v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
@@ -153,13 +153,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
return -EINVAL;
}
- writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
+ writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}
if (cpu_is_mx35()) {
- v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+ v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
@@ -196,7 +196,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
return -EINVAL;
}
- writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+ writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}
@@ -206,7 +206,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
/* On i.MX27 we can use the i.MX31 USBCTRL bits, they
* are identical
*/
- v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
+ v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
case 0: /* OTG port */
@@ -241,7 +241,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
default:
return -EINVAL;
}
- writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
+ writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}