diff options
Diffstat (limited to 'arch/arm/plat-s3c64xx/include')
21 files changed, 1378 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h new file mode 100644 index 000000000000..9aa0e427d113 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h @@ -0,0 +1,48 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank A register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00) +#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04) +#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08) +#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c) +#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10) + +#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0) +#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0) + +#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4) +#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4) + +#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8) +#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8) + +#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12) +#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12) + +#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16) +#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16) + +#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20) +#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20) + +#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24) +#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24) + +#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28) +#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h new file mode 100644 index 000000000000..3933adb4d50a --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h @@ -0,0 +1,60 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank B register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) +#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) +#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) +#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) +#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) + +#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) +#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) +#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) +#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) +#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) + +#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) +#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) +#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) +#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) +#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) + +#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) +#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) +#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) +#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) +#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) +#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) + +#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) +#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) +#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) +#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) +#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) + +#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) +#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) +#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) +#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) + +#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) +#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) + +#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) +#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h new file mode 100644 index 000000000000..c47daf7e2723 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h @@ -0,0 +1,53 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank C register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00) +#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04) +#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08) +#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c) +#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10) + +#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0) +#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0) + +#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4) +#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4) + +#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8) +#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8) + +#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12) +#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12) + +#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) +#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) +#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) +#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) + +#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) +#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) +#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) +#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) + +#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) +#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) + +#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) +#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) +#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h new file mode 100644 index 000000000000..6fe4a49c26f0 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h @@ -0,0 +1,49 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank D register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00) +#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04) +#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08) +#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c) +#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10) + +#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0) +#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0) +#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0) +#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0) + +#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4) +#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4) +#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4) +#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4) + +#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8) +#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8) +#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8) +#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8) + +#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12) +#define S3C64XX_GPD3_I2S0_DI (0x03 << 12) +#define S3C64XX_GPD3_AC97_SDI (0x04 << 12) +#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12) + +#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16) +#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16) +#define S3C64XX_GPD4_AC97_SDO (0x04 << 16) +#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h new file mode 100644 index 000000000000..7fcf3d8e0a48 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank E register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) +#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) +#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) +#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) +#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) + +#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) +#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) +#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) + +#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) +#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) +#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) + +#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) +#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) +#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) + +#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) +#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) +#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) + +#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) +#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) +#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h new file mode 100644 index 000000000000..f3faff974a18 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h @@ -0,0 +1,71 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank F register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00) +#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04) +#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08) +#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c) +#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10) + +#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0) +#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0) + +#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2) +#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2) + +#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4) +#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4) + +#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6) +#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6) + +#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8) +#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8) + +#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10) +#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10) + +#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12) +#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12) + +#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14) +#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14) + +#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16) +#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16) + +#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18) +#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18) + +#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20) +#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20) + +#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22) +#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22) + +#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24) +#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24) + +#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26) +#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26) + +#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28) +#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28) + +#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h new file mode 100644 index 000000000000..35bbd2378e55 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h @@ -0,0 +1,42 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank G register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00) +#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04) +#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08) +#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c) +#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10) + +#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0) +#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0) + +#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4) +#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4) + +#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8) +#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8) + +#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12) +#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12) + +#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16) +#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16) + +#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20) +#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h new file mode 100644 index 000000000000..81549516572f --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h @@ -0,0 +1,74 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank H register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00) +#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04) +#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08) +#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c) +#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10) +#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14) + +#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0) +#define S3C64XX_GPH0_KP_COL0 (0x04 << 0) +#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0) + +#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4) +#define S3C64XX_GPH1_KP_COL1 (0x04 << 4) +#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4) + +#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8) +#define S3C64XX_GPH2_KP_COL2 (0x04 << 8) +#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8) + +#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12) +#define S3C64XX_GPH3_KP_COL3 (0x04 << 12) +#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12) + +#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16) +#define S3C64XX_GPH4_KP_COL4 (0x04 << 16) +#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16) + +#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20) +#define S3C64XX_GPH5_KP_COL5 (0x04 << 20) +#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20) + +#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24) +#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24) +#define S3C64XX_GPH6_KP_COL6 (0x04 << 24) +#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24) +#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24) +#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24) + +#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28) +#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28) +#define S3C64XX_GPH7_KP_COL7 (0x04 << 28) +#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28) +#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28) +#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28) + +#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32) +#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32) +#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32) +#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32) +#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32) + +#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36) +#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36) +#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36) +#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h new file mode 100644 index 000000000000..ce9ebe335566 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h @@ -0,0 +1,40 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank I register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00) +#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04) +#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08) +#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c) +#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10) + +#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPI0_VD0 (0x02 << 0) +#define S3C64XX_GPI1_VD1 (0x02 << 2) +#define S3C64XX_GPI2_VD2 (0x02 << 4) +#define S3C64XX_GPI3_VD3 (0x02 << 6) +#define S3C64XX_GPI4_VD4 (0x02 << 8) +#define S3C64XX_GPI5_VD5 (0x02 << 10) +#define S3C64XX_GPI6_VD6 (0x02 << 12) +#define S3C64XX_GPI7_VD7 (0x02 << 14) +#define S3C64XX_GPI8_VD8 (0x02 << 16) +#define S3C64XX_GPI9_VD9 (0x02 << 18) +#define S3C64XX_GPI10_VD10 (0x02 << 20) +#define S3C64XX_GPI11_VD11 (0x02 << 22) +#define S3C64XX_GPI12_VD12 (0x02 << 24) +#define S3C64XX_GPI13_VD13 (0x02 << 26) +#define S3C64XX_GPI14_VD14 (0x02 << 28) +#define S3C64XX_GPI15_VD15 (0x02 << 30) diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h new file mode 100644 index 000000000000..21a906299d30 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h @@ -0,0 +1,36 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank J register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00) +#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04) +#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08) +#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c) +#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10) + +#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPJ0_VD16 (0x02 << 0) +#define S3C64XX_GPJ1_VD17 (0x02 << 2) +#define S3C64XX_GPJ2_VD18 (0x02 << 4) +#define S3C64XX_GPJ3_VD19 (0x02 << 6) +#define S3C64XX_GPJ4_VD20 (0x02 << 8) +#define S3C64XX_GPJ5_VD21 (0x02 << 10) +#define S3C64XX_GPJ6_VD22 (0x02 << 12) +#define S3C64XX_GPJ7_VD23 (0x02 << 14) +#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16) +#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18) +#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20) +#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22) diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h new file mode 100644 index 000000000000..569e76120881 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank N register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) +#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) +#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) + +#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPN0_EINT0 (0x02 << 0) +#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) + +#define S3C64XX_GPN1_EINT1 (0x02 << 2) +#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) + +#define S3C64XX_GPN2_EINT2 (0x02 << 4) +#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) + +#define S3C64XX_GPN3_EINT3 (0x02 << 6) +#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) + +#define S3C64XX_GPN4_EINT4 (0x02 << 8) +#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) + +#define S3C64XX_GPN5_EINT5 (0x02 << 10) +#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) + +#define S3C64XX_GPN6_EINT6 (0x02 << 12) +#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) + +#define S3C64XX_GPN7_EINT7 (0x02 << 14) +#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) + +#define S3C64XX_GPN8_EINT8 (0x02 << 16) +#define S3C64XX_GPN9_EINT9 (0x02 << 18) +#define S3C64XX_GPN10_EINT10 (0x02 << 20) +#define S3C64XX_GPN11_EINT11 (0x02 << 22) +#define S3C64XX_GPN12_EINT12 (0x02 << 24) +#define S3C64XX_GPN13_EINT13 (0x02 << 26) +#define S3C64XX_GPN14_EINT14 (0x02 << 28) +#define S3C64XX_GPN15_EINT15 (0x02 << 30) diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h new file mode 100644 index 000000000000..b09e12954b57 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h @@ -0,0 +1,70 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank O register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) +#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) +#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) +#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) +#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) + +#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) +#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) + +#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) +#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) + +#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) +#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) + +#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) +#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) + +#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) + +#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) + +#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) +#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) + +#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) +#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) + +#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) +#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) + +#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) +#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) + +#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) +#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) + +#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) +#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) + +#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) +#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) + +#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) +#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) + +#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) +#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) + +#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) +#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h new file mode 100644 index 000000000000..92f00517926b --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h @@ -0,0 +1,69 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank P register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00) +#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04) +#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08) +#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c) +#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10) + +#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0) +#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0) + +#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2) +#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2) + +#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4) +#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4) + +#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6) +#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6) + +#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8) +#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8) + +#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10) +#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10) + +#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12) +#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12) + +#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14) +#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14) + +#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16) +#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16) + +#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18) +#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18) + +#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20) +#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20) + +#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22) +#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22) + +#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24) +#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24) + +#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26) +#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26) + +#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28) +#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h new file mode 100644 index 000000000000..565e60aaee47 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h @@ -0,0 +1,46 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank Q register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) +#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) +#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) +#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) +#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) + +#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) +#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) + +#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) +#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) + +#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) + +#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) + +#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) + +#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) + +#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) + +#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) +#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) + +#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) +#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h new file mode 100644 index 000000000000..02e8dd4c97d5 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -0,0 +1,201 @@ +/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Common IRQ support + */ + +#ifndef __ASM_PLAT_S3C64XX_IRQS_H +#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S3C_IRQ_OFFSET (32) + +#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) + +#define S3C_VIC0_BASE S3C_IRQ(0) +#define S3C_VIC1_BASE S3C_IRQ(32) + +/* UART interrupts, each UART has 4 intterupts per channel so + * use the space between the ISA and S3C main interrupts. Note, these + * are not in the same order as the S3C24XX series! */ + +#define IRQ_S3CUART_BASE0 (16) +#define IRQ_S3CUART_BASE1 (20) +#define IRQ_S3CUART_BASE2 (24) +#define IRQ_S3CUART_BASE3 (28) + +#define UART_IRQ_RXD (0) +#define UART_IRQ_ERR (1) +#define UART_IRQ_TXD (2) +#define UART_IRQ_MODEM (3) + +#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) + +/* VIC based IRQs */ + +#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) + +/* VIC0 */ + +#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) +#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) +#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) +#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) +#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) +#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) +#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) +#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) +#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) +#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) +#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) +#define IRQ_2D S3C64XX_IRQ_VIC0(11) +#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) +#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) +#define IRQ_BATF S3C64XX_IRQ_VIC0(14) +#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) +#define IRQ_MFC S3C64XX_IRQ_VIC0(16) +#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) +#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) +#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) +#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) +#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) +#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) +#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) +#define IRQ_WDT S3C64XX_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) +#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) +#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) +#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) +#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) +#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) +#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) +#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) +#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) +#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) +#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) +#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) +#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) +#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) +#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) +#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) +#define IRQ_NFC S3C64XX_IRQ_VIC1(13) +#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) +#define IRQ_UHOST S3C64XX_IRQ_VIC1(15) +#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) +#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) +#define IRQ_IIC S3C64XX_IRQ_VIC1(18) +#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) +#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) +#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) +#define IRQ_MSM S3C64XX_IRQ_VIC1(22) +#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) +#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) +#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S3C64XX_IRQ_VIC1(26) +#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) +#define IRQ_SEC S3C64XX_IRQ_VIC1(29) +#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S3C64XX_IRQ_VIC1(31) + +#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) + +#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) +#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) +#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) +#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) +#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) + +/* compatibility for device defines */ + +#define IRQ_IIC1 IRQ_S3C6410_IIC1 + +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE + * which we place after the pair of VICs. */ + +#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) + +#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) +#define IRQ_EINT(x) S3C_EINT(x) + +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP3_NR (5) +#define IRQ_EINT_GROUP4_NR (14) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +#define IRQ_EINT_GROUP7_NR (16) +#define IRQ_EINT_GROUP8_NR (15) +#define IRQ_EINT_GROUP9_NR (9) + +#define IRQ_EINT_GROUP_BASE S3C_EINT(28) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) + +#endif /* __ASM_PLAT_S3C64XX_IRQS_H */ + diff --git a/arch/arm/plat-s3c64xx/include/plat/pll.h b/arch/arm/plat-s3c64xx/include/plat/pll.h new file mode 100644 index 000000000000..90bbd72fdc4e --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/pll.h @@ -0,0 +1,74 @@ +/* arch/arm/plat-s3c64xx/include/plat/pll.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX PLL code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) +#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) +#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) +#define S3C6400_PLL_MDIV_SHIFT (16) +#define S3C6400_PLL_PDIV_SHIFT (8) +#define S3C6400_PLL_SDIV_SHIFT (0) + +#include <asm/div64.h> + +static inline unsigned long s3c6400_get_pll(unsigned long baseclk, + u32 pllcon) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; + pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; + sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1) +#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1) +#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1) +#define S3C6400_EPLL_MDIV_SHIFT (16) +#define S3C6400_EPLL_PDIV_SHIFT (8) +#define S3C6400_EPLL_SDIV_SHIFT (0) +#define S3C6400_EPLL_KDIV_MASK (0xffff) + +static inline unsigned long s3c6400_get_epll(unsigned long baseclk) +{ + unsigned long result; + u32 epll0 = __raw_readl(S3C_EPLL_CON0); + u32 epll1 = __raw_readl(S3C_EPLL_CON1); + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK; + pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK; + sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK; + kdiv = epll1 & S3C6400_EPLL_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h new file mode 100644 index 000000000000..b1082c163247 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -0,0 +1,224 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_CLOCK_H +#define __PLAT_REGS_CLOCK_H __FILE__ + +#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S3C_APLL_LOCK S3C_CLKREG(0x00) +#define S3C_MPLL_LOCK S3C_CLKREG(0x04) +#define S3C_EPLL_LOCK S3C_CLKREG(0x08) +#define S3C_APLL_CON S3C_CLKREG(0x0C) +#define S3C_MPLL_CON S3C_CLKREG(0x10) +#define S3C_EPLL_CON0 S3C_CLKREG(0x14) +#define S3C_EPLL_CON1 S3C_CLKREG(0x18) +#define S3C_CLK_SRC S3C_CLKREG(0x1C) +#define S3C_CLK_DIV0 S3C_CLKREG(0x20) +#define S3C_CLK_DIV1 S3C_CLKREG(0x24) +#define S3C_CLK_DIV2 S3C_CLKREG(0x28) +#define S3C_CLK_OUT S3C_CLKREG(0x2C) +#define S3C_HCLK_GATE S3C_CLKREG(0x30) +#define S3C_PCLK_GATE S3C_CLKREG(0x34) +#define S3C_SCLK_GATE S3C_CLKREG(0x38) + +/* CLKDIV0 */ +#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) +#define S3C6400_CLKDIV0_MFC_SHIFT (28) +#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24) +#define S3C6400_CLKDIV0_JPEG_SHIFT (24) +#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20) +#define S3C6400_CLKDIV0_CAM_SHIFT (20) +#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18) +#define S3C6400_CLKDIV0_SECURITY_SHIFT (18) +#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) +#define S3C6400_CLKDIV0_PCLK_SHIFT (12) +#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) +#define S3C6400_CLKDIV0_HCLK2_SHIFT (9) +#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) +#define S3C6400_CLKDIV0_HCLK_SHIFT (8) +#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) +#define S3C6400_CLKDIV0_MPLL_SHIFT (4) +#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0) +#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6400_CLKDIV0_ARM_SHIFT (0) + +/* CLKDIV1 */ +#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24) +#define S3C6410_CLKDIV1_FIMC_SHIFT (24) +#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20) +#define S3C6400_CLKDIV1_UHOST_SHIFT (20) +#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16) +#define S3C6400_CLKDIV1_SCALER_SHIFT (16) +#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12) +#define S3C6400_CLKDIV1_LCD_SHIFT (12) +#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8) +#define S3C6400_CLKDIV1_MMC2_SHIFT (8) +#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4) +#define S3C6400_CLKDIV1_MMC1_SHIFT (4) +#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0) +#define S3C6400_CLKDIV1_MMC0_SHIFT (0) + +/* CLKDIV2 */ +#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24) +#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24) +#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20) +#define S3C6400_CLKDIV2_IRDA_SHIFT (20) +#define S3C6400_CLKDIV2_UART_MASK (0xf << 16) +#define S3C6400_CLKDIV2_UART_SHIFT (16) +#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12) +#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12) +#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8) +#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8) +#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4) +#define S3C6400_CLKDIV2_SPI1_SHIFT (4) +#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0) +#define S3C6400_CLKDIV2_SPI0_SHIFT (0) + +/* HCLK GATE Registers */ +#define S3C_CLKCON_HCLK_BUS (1<<30) +#define S3C_CLKCON_HCLK_SECUR (1<<29) +#define S3C_CLKCON_HCLK_SDMA1 (1<<28) +#define S3C_CLKCON_HCLK_SDMA2 (1<<27) +#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_IROM (1<<25) +#define S3C_CLKCON_HCLK_DDR1 (1<<24) +#define S3C_CLKCON_HCLK_DDR0 (1<<23) +#define S3C_CLKCON_HCLK_MEM1 (1<<22) +#define S3C_CLKCON_HCLK_MEM0 (1<<21) +#define S3C_CLKCON_HCLK_USB (1<<20) +#define S3C_CLKCON_HCLK_HSMMC2 (1<<19) +#define S3C_CLKCON_HCLK_HSMMC1 (1<<18) +#define S3C_CLKCON_HCLK_HSMMC0 (1<<17) +#define S3C_CLKCON_HCLK_MDP (1<<16) +#define S3C_CLKCON_HCLK_DHOST (1<<15) +#define S3C_CLKCON_HCLK_IHOST (1<<14) +#define S3C_CLKCON_HCLK_DMA1 (1<<13) +#define S3C_CLKCON_HCLK_DMA0 (1<<12) +#define S3C_CLKCON_HCLK_JPEG (1<<11) +#define S3C_CLKCON_HCLK_CAMIF (1<<10) +#define S3C_CLKCON_HCLK_SCALER (1<<9) +#define S3C_CLKCON_HCLK_2D (1<<8) +#define S3C_CLKCON_HCLK_TV (1<<7) +#define S3C_CLKCON_HCLK_POST0 (1<<5) +#define S3C_CLKCON_HCLK_ROT (1<<4) +#define S3C_CLKCON_HCLK_LCD (1<<3) +#define S3C_CLKCON_HCLK_TZIC (1<<2) +#define S3C_CLKCON_HCLK_INTC (1<<1) +#define S3C_CLKCON_HCLK_MFC (1<<0) + +/* PCLK GATE Registers */ +#define S3C6410_CLKCON_PCLK_I2C1 (1<<27) +#define S3C6410_CLKCON_PCLK_IIS2 (1<<26) +#define S3C_CLKCON_PCLK_SKEY (1<<24) +#define S3C_CLKCON_PCLK_CHIPID (1<<23) +#define S3C_CLKCON_PCLK_SPI1 (1<<22) +#define S3C_CLKCON_PCLK_SPI0 (1<<21) +#define S3C_CLKCON_PCLK_HSIRX (1<<20) +#define S3C_CLKCON_PCLK_HSITX (1<<19) +#define S3C_CLKCON_PCLK_GPIO (1<<18) +#define S3C_CLKCON_PCLK_IIC (1<<17) +#define S3C_CLKCON_PCLK_IIS1 (1<<16) +#define S3C_CLKCON_PCLK_IIS0 (1<<15) +#define S3C_CLKCON_PCLK_AC97 (1<<14) +#define S3C_CLKCON_PCLK_TZPC (1<<13) +#define S3C_CLKCON_PCLK_TSADC (1<<12) +#define S3C_CLKCON_PCLK_KEYPAD (1<<11) +#define S3C_CLKCON_PCLK_IRDA (1<<10) +#define S3C_CLKCON_PCLK_PCM1 (1<<9) +#define S3C_CLKCON_PCLK_PCM0 (1<<8) +#define S3C_CLKCON_PCLK_PWM (1<<7) +#define S3C_CLKCON_PCLK_RTC (1<<6) +#define S3C_CLKCON_PCLK_WDT (1<<5) +#define S3C_CLKCON_PCLK_UART3 (1<<4) +#define S3C_CLKCON_PCLK_UART2 (1<<3) +#define S3C_CLKCON_PCLK_UART1 (1<<2) +#define S3C_CLKCON_PCLK_UART0 (1<<1) +#define S3C_CLKCON_PCLK_MFC (1<<0) + +/* SCLK GATE Registers */ +#define S3C_CLKCON_SCLK_UHOST (1<<30) +#define S3C_CLKCON_SCLK_MMC2_48 (1<<29) +#define S3C_CLKCON_SCLK_MMC1_48 (1<<28) +#define S3C_CLKCON_SCLK_MMC0_48 (1<<27) +#define S3C_CLKCON_SCLK_MMC2 (1<<26) +#define S3C_CLKCON_SCLK_MMC1 (1<<25) +#define S3C_CLKCON_SCLK_MMC0 (1<<24) +#define S3C_CLKCON_SCLK_SPI1_48 (1<<23) +#define S3C_CLKCON_SCLK_SPI0_48 (1<<22) +#define S3C_CLKCON_SCLK_SPI1 (1<<21) +#define S3C_CLKCON_SCLK_SPI0 (1<<20) +#define S3C_CLKCON_SCLK_DAC27 (1<<19) +#define S3C_CLKCON_SCLK_TV27 (1<<18) +#define S3C_CLKCON_SCLK_SCALER27 (1<<17) +#define S3C_CLKCON_SCLK_SCALER (1<<16) +#define S3C_CLKCON_SCLK_LCD27 (1<<15) +#define S3C_CLKCON_SCLK_LCD (1<<14) +#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) +#define S3C6410_CLKCON_FIMC (1<<13) +#define S3C_CLKCON_SCLK_POST0_27 (1<<12) +#define S3C6400_CLKCON_SCLK_POST1 (1<<11) +#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) +#define S3C_CLKCON_SCLK_POST0 (1<<10) +#define S3C_CLKCON_SCLK_AUDIO1 (1<<9) +#define S3C_CLKCON_SCLK_AUDIO0 (1<<8) +#define S3C_CLKCON_SCLK_SECUR (1<<7) +#define S3C_CLKCON_SCLK_IRDA (1<<6) +#define S3C_CLKCON_SCLK_UART (1<<5) +#define S3C_CLKCON_SCLK_ONENAND (1<<4) +#define S3C_CLKCON_SCLK_MFC (1<<3) +#define S3C_CLKCON_SCLK_CAM (1<<2) +#define S3C_CLKCON_SCLK_JPEG (1<<1) + +/* CLKSRC */ + +#define S3C6400_CLKSRC_APLL_MOUT (1 << 0) +#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) +#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) +#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) +#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) +#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) +#define S3C6400_CLKSRC_MFC (1 << 4) + +#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31) +#define S3C6410_CLKSRC_TV27_SHIFT (31) +#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30) +#define S3C6410_CLKSRC_DAC27_SHIFT (30) +#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28) +#define S3C6400_CLKSRC_SCALER_SHIFT (28) +#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26) +#define S3C6400_CLKSRC_LCD_SHIFT (26) +#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24) +#define S3C6400_CLKSRC_IRDA_SHIFT (24) +#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22) +#define S3C6400_CLKSRC_MMC2_SHIFT (22) +#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) +#define S3C6400_CLKSRC_MMC1_SHIFT (20) +#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) +#define S3C6400_CLKSRC_MMC0_SHIFT (18) +#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) +#define S3C6400_CLKSRC_SPI1_SHIFT (16) +#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) +#define S3C6400_CLKSRC_SPI0_SHIFT (14) +#define S3C6400_CLKSRC_UART_MASK (0x1 << 13) +#define S3C6400_CLKSRC_UART_SHIFT (13) +#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10) +#define S3C6400_CLKSRC_AUDIO1_SHIFT (10) +#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7) +#define S3C6400_CLKSRC_AUDIO0_SHIFT (7) +#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5) +#define S3C6400_CLKSRC_UHOST_SHIFT (5) + + +#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h new file mode 100644 index 000000000000..75b873d82808 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h @@ -0,0 +1,35 @@ +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - GPIO register definitions + */ + +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H +#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ + +/* Base addresses for each of the banks */ + +#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) +#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) +#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) +#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) +#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) +#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) +#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) +#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) +#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) +#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) +#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) +#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) +#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) +#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) +#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) +#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) +#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) + +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ + diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h new file mode 100644 index 000000000000..d8ed82917096 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h @@ -0,0 +1,24 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX system register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_SYS_H +#define __PLAT_REGS_SYS_H __FILE__ + +#define S3C_SYSREG(x) (S3C_VA_SYS + (x)) + +#define S3C64XX_OTHERS S3C_SYSREG(0x900) + +#define S3C64XX_OTHERS_USBMASK (1 << 16) + +#endif /* _PLAT_REGS_SYS_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h new file mode 100644 index 000000000000..571eaa2e54f1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h @@ -0,0 +1,35 @@ +/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Header file for s3c6400 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S3C6400 related SoCs */ + +extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s3c6400_register_clocks(void); +extern void s3c6400_setup_clocks(void); + +#ifdef CONFIG_CPU_S3C6400 + +extern int s3c6400_init(void); +extern void s3c6400_map_io(void); +extern void s3c6400_init_clocks(int xtal); + +#define s3c6400_init_uarts s3c6400_common_init_uarts + +#else +#define s3c6400_init_clocks NULL +#define s3c6400_init_uarts NULL +#define s3c6400_map_io NULL +#define s3c6400_init NULL +#endif + diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6410.h b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h new file mode 100644 index 000000000000..50dcdd6f6800 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h @@ -0,0 +1,29 @@ +/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Header file for s3c6410 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C6410 + +extern int s3c6410_init(void); +extern void s3c6410_init_irq(void); +extern void s3c6410_map_io(void); +extern void s3c6410_init_clocks(int xtal); + +#define s3c6410_init_uarts s3c6400_common_init_uarts + +#else +#define s3c6410_init_clocks NULL +#define s3c6410_init_uarts NULL +#define s3c6410_map_io NULL +#define s3c6410_init NULL +#endif |