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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
new file mode 100644
index 000000000000..43c67be8500f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019~2020 NXP
+ */
+
+&hsio_subsys {
+ phyx1_lpcg: clock-controller@5f090000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f090000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
+ <&hsio_per_clk>, <&hsio_per_clk>;
+ bit-offset = <0 4 8 16>;
+ clock-output-names = "hsio_phyx1_pclk",
+ "hsio_phyx1_epcs_tx_clk",
+ "hsio_phyx1_epcs_rx_clk",
+ "hsio_phyx1_apb_clk";
+ power-domains = <&pd IMX_SC_R_SERDES_1>;
+ };
+};
+
+&pcieb {
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+};