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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-evk.dts30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 291b6050c30a..507d1dfec88d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -543,6 +543,28 @@
status = "okay";
};
+&pcie{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ ext_osc = <0>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
+ <&clk IMX8MP_CLK_PCIE_AUX>,
+ <&clk IMX8MP_CLK_PCIE_PHY>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>,
+ <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ status = "okay";
+};
+
+&pcie_phy{
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -805,6 +827,14 @@
>;
};
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x61 /* open drain, pull up */
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
+ >;
+ };
+
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41