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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi')
-rwxr-xr-x[-rw-r--r--]arch/arm64/boot/dts/freescale/imx8mq.dtsi544
1 files changed, 504 insertions, 40 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 3dae8d7c7619..49c544d72173 100644..100755
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -20,6 +20,9 @@
#size-cells = <2>;
aliases {
+ csi0 = &mipi_csi_1;
+ csi1 = &mipi_csi_2;
+ ethernet0 = &fec1;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -29,6 +32,8 @@
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
@@ -103,6 +108,7 @@
#cooling-cells = <2>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_1: cpu@1 {
@@ -115,6 +121,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_2: cpu@2 {
@@ -127,6 +134,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_3: cpu@3 {
@@ -139,11 +147,27 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
};
a53_opp_table: opp-table {
@@ -228,34 +252,6 @@
};
};
};
-
- gpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
- thermal-sensors = <&tmu 1>;
-
- trips {
- gpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
-
- vpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
- thermal-sensors = <&tmu 2>;
-
- trips {
- vpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
};
timer {
@@ -268,6 +264,25 @@
arm,no-tick-in-suspend;
};
+ busfreq { /* BUSFREQ */
+ compatible = "fsl,imx_busfreq";
+ clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>,
+ <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>,
+ <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>,
+ <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>,
+ <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>,
+ <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>,
+ <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>;
+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
+ "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m",
+ "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src",
+ "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m";
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -275,12 +290,82 @@
ranges = <0x0 0x0 0x0 0x3e000000>;
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
+ caam_sm: caam-sm@100000 {
+ compatible = "fsl,imx6q-caam-sm";
+ reg = <0x100000 0x8000>;
+ };
+
bus@30000000 { /* AIPS1 */
compatible = "fsl,imx8mq-aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
+ sai1: sai@30010000 {
+ compatible = "fsl,imx8mq-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x30010000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_SAI1_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 1 0>, <&sdma2 9 1 0>;
+ dma-names = "rx", "tx";
+ fsl,dataline = <0 0xff 0xff>;
+ status = "disabled";
+ };
+
+ sai6: sai@30030000 {
+ compatible = "fsl,imx8mq-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x30030000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_SAI6_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
+ dma-names = "rx", "tx";
+ fsl,shared-interrupt;
+ status = "disabled";
+ };
+
+ sai5: sai@30040000 {
+ compatible = "fsl,imx8mq-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x30040000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_SAI5_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
+ dma-names = "rx", "tx";
+ fsl,shared-interrupt;
+ fsl,dataline = <0 0xf 0xf>;
+ status = "disabled";
+ };
+
+ sai4: sai@30050000 {
+ compatible = "fsl,imx8mq-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x30050000 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_SAI4_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
+ dma-names = "rx", "tx";
+ fsl,dataline = <0 0x0 0xf>;
+ status = "disabled";
+ };
+
gpio1: gpio@30200000 {
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
@@ -396,7 +481,7 @@
0x00030005 0x00000053
0x00030006 0x0000005f
0x00030007 0x00000071>;
- #thermal-sensor-cells = <1>;
+ #thermal-sensor-cells = <0>;
};
wdog1: watchdog@30280000 {
@@ -423,7 +508,7 @@
status = "disabled";
};
- sdma2: sdma@302c0000 {
+ sdma2: dma-controller@302c0000 {
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
@@ -434,6 +519,21 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
+ lcdif: lcdif@30320000 {
+ compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
+ reg = <0x30320000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+ clock-names = "pix";
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
+ <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_VIDEO_PLL1>,
+ <&clk IMX8MQ_CLK_27M>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
@@ -451,7 +551,7 @@
};
};
- ocotp: ocotp-ctrl@30350000 {
+ ocotp: efuse@30350000 {
compatible = "fsl,imx8mq-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
@@ -461,6 +561,10 @@
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
+
+ fec_mac_address: mac-address@640 {
+ reg = <0x90 6>;
+ };
};
anatop: syscon@30360000 {
@@ -469,6 +573,22 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
};
+ irq_sec_vio: caam_secvio {
+ compatible = "fsl,imx6q-caam-secvio";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ jtag-tamper = "disabled";
+ watchdog-tamper = "enabled";
+ internal-boot-tamper = "enabled";
+ external-pin-tamper = "disabled";
+ };
+
+ caam_snvs: caam-snvs@30370000 {
+ compatible = "fsl,imx6q-caam-snvs";
+ reg = <0x30370000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
+ clock-names = "ipg";
+ };
+
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
@@ -487,6 +607,8 @@
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
+ clock-names = "snvs";
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
@@ -505,6 +627,19 @@
clock-names = "ckil", "osc_25m", "osc_27m",
"clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
+ assigned-clocks = <&clk IMX8MQ_CLK_NOC>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MQ_CLK_AUDIO_AHB>,
+ <&clk IMX8MQ_AUDIO_PLL1>,
+ <&clk IMX8MQ_AUDIO_PLL2>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_500M>;
+ assigned-clock-rates = <800000000>,
+ <0>,
+ <0>,
+ <786432000>,
+ <722534400>;
};
src: reset-controller@30390000 {
@@ -519,6 +654,7 @@
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
+ broken-wake-request-signals;
#interrupt-cells = <3>;
pgc {
@@ -669,6 +805,30 @@
ranges = <0x30800000 0x30800000 0x400000>,
<0x08000000 0x08000000 0x10000000>;
+ spdif1: spdif@30810000 {
+ compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif";
+ reg = <0x30810000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
+ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
+ <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8MQ_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -724,6 +884,8 @@
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
<&clk IMX8MQ_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -735,6 +897,32 @@
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
<&clk IMX8MQ_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spdif2: spdif@308a0000 {
+ compatible = "fsl,imx8mm-spdif", "fsl,imx35-spdif";
+ reg = <0x308a0000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
+ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
+ <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8MQ_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -744,14 +932,30 @@
reg = <0x308b0000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
+ <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI2_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
+ sai3: sai@308c0000 {
+ compatible = "fsl,imx8mq-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x308c0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_SAI3_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
@@ -795,6 +999,47 @@
status = "disabled";
};
+ mipi_dsi: mipi_dsi@30a00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mq-nwl-dsi";
+ reg = <0x30a00000 0x300>;
+ clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
+ <&clk IMX8MQ_CLK_DSI_AHB>,
+ <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
+ <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_VIDEO_PLL1>,
+ <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+ clock-names = "core",
+ "rx_esc",
+ "tx_esc",
+ "phy_ref",
+ "video_pll",
+ "lcdif";
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_CLK_DSI_CORE>,
+ <&clk IMX8MQ_CLK_DSI_AHB>,
+ <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <27000000>,
+ <266000000>,
+ <80000000>,
+ <20000000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pgc_mipi>;
+ resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
+ <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
+ <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
+ <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
+ reset-names = "byte", "dpi", "esc", "pclk";
+ mux-controls = <&mux 0>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
@@ -843,9 +1088,49 @@
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
<&clk IMX8MQ_CLK_UART4_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ mipi_csi_1: mipi_csi1@30a70000 {
+ compatible = "fsl,mxc-mipi-csi2_yav";
+ reg = <0x30a70000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+ <&clk IMX8MQ_CLK_CSI1_ESC>,
+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
+ clock-names = "clk_core", "clk_esc", "clk_pxl";
+ assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MQ_CLK_CSI1_ESC>;
+ assigned-clock-rates = <133000000>, <100000000>, <66000000>;
+ power-domains = <&pgc_mipi_csi1>;
+ csis-phy-reset = <&src 0x4c 7>;
+ phy-gpr = <&iomuxc_gpr 0x88>;
status = "disabled";
};
+ csi1_bridge: csi1_bridge@30a90000 {
+ compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
+ reg = <0x30a90000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_CSI1_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ status = "disabled";
+ };
+
+ mu: mu@30aa0000 {
+ compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
+ reg = <0x30aa0000 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
+ clock-names = "mu";
+ #mbox-cells = <2>;
+ };
+
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mq-usdhc",
"fsl,imx7d-usdhc";
@@ -878,6 +1163,35 @@
status = "disabled";
};
+ mipi_csi_2: mipi_csi2@30b60000 {
+ compatible = "fsl,mxc-mipi-csi2_yav";
+ reg = <0x30b60000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+ <&clk IMX8MQ_CLK_CSI2_ESC>,
+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
+ clock-names = "clk_core", "clk_esc", "clk_pxl";
+ assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
+ <&clk IMX8MQ_CLK_CSI2_ESC>;
+ assigned-clock-rates = <133000000>, <100000000>, <66000000>;
+ power-domains = <&pgc_mipi_csi2>;
+ csis-phy-reset = <&src 0x50 7>;
+ phy-gpr = <&iomuxc_gpr 0xa4>;
+ status = "disabled";
+ };
+
+ csi2_bridge: csi2_bridge@30b80000 {
+ compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
+ reg = <0x30b80000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_CSI2_ROOT>,
+ <&clk IMX8MQ_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ status = "disabled";
+ };
+
qspi0: spi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -892,7 +1206,7 @@
status = "disabled";
};
- sdma1: sdma@30bd0000 {
+ sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -918,6 +1232,11 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ nvmem-cells = <&fec_mac_address>;
+ nvmem-cell-names = "mac-address";
+ nvmem_macaddr_swap;
+ stop-mode = <&iomuxc_gpr 0x10 3>;
+ fsl,wakeup_irq = <2>;
status = "disabled";
};
};
@@ -928,6 +1247,14 @@
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ hdmi: hdmi@32c00000 {
+ reg = <0x32c00000 0x100000>,
+ <0x32e40000 0x40000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ };
+
irqsteer: interrupt-controller@32e2d000 {
compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
@@ -939,6 +1266,35 @@
interrupt-controller;
#interrupt-cells = <1>;
};
+
+ dcss: display-controller@32e00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+ interrupts = <6>, <8>, <9>, <16>, <17>;
+ interrupt-names = "ctx_ld", "ctxld_kick", "vblank",
+ "dtrc_ch1", "dtrc_ch2";
+ interrupt-parent = <&irqsteer>;
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+ <&clk IMX8MQ_CLK_DISP_DTRC>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
+ <&clk IMX8MQ_CLK_PHY_27MHZ>;
+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src",
+ "pll_phy_ref";
+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_CLK_27M>;
+ assigned-clock-rates = <800000000>,
+ <400000000>;
+ status = "disabled";
+ };
};
gpu: gpu@38000000 {
@@ -963,6 +1319,7 @@
assigned-clock-rates = <800000000>, <800000000>,
<800000000>, <800000000>, <0>;
power-domains = <&pgc_gpu>;
+ status = "disabled";
};
usb_dwc3_0: usb@38100000 {
@@ -982,6 +1339,7 @@
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg1>;
usb3-resume-missing-cas;
+ snps,power-down-scale = <2>;
status = "disabled";
};
@@ -1014,6 +1372,7 @@
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg2>;
usb3-resume-missing-cas;
+ snps,power-down-scale = <2>;
status = "disabled";
};
@@ -1029,6 +1388,35 @@
status = "disabled";
};
+ dma_apbh: dma-apbh@33000000 {
+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x33000000 0x2000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+ };
+
+ gpmi: gpmi-nand@33002000{
+ compatible = "fsl,imx7d-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+ clock-names = "gpmi_io", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
pcie0: pcie@33800000 {
compatible = "fsl,imx8mq-pcie";
reg = <0x33800000 0x400000>,
@@ -1042,8 +1430,9 @@
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "msi", "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
@@ -1054,8 +1443,9 @@
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
- <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
- reset-names = "pciephy", "apps", "turnoff";
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "clkreq", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
@@ -1079,8 +1469,9 @@
0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "msi", "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
@@ -1091,7 +1482,25 @@
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
- <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "clkreq", "turnoff";
+ status = "disabled";
+ };
+
+ pcie1_ep: pcie_ep@33c00000 {
+ compatible = "fsl,imx8mq-pcie-ep";
+ reg = <0x33c00000 0x000400000>,
+ <0x20000000 0x08000000>;
+ reg-names = "regs", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
@@ -1101,6 +1510,8 @@
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
status = "disabled";
};
@@ -1123,5 +1534,58 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ vpu: vpu@38300000 {
+ compatible = "nxp,imx8mq-hantro";
+ reg = <0x38300000 0x200000>;
+ reg-names = "regs_hantro";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_hantro_g1", "irq_hantro_g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>;
+ assigned-clock-rates = <600000000>, <600000000>, <800000000>;
+ power-domains = <&pgc_vpu>;
+ status = "disabled";
+ };
+ };
+
+ gpu3d: gpu3d@38000000 {
+ compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu";
+ reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>;
+ reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_3d";
+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+ <&clk IMX8MQ_CLK_GPU_AXI>,
+ <&clk IMX8MQ_CLK_GPU_AHB>;
+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+ <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+ <&clk IMX8MQ_CLK_GPU_AXI>,
+ <&clk IMX8MQ_CLK_GPU_AHB>;
+ assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>;
+ assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>;
+ power-domains = <&pgc_gpu>;
+ status = "disabled";
+ };
+
+ rpmsg: rpmsg{
+ compatible = "fsl,imx8mq-rpmsg";
+ /* up to now, the following channels are used in imx rpmsg
+ * - tx1/rx1: messages channel.
+ * - general interrupt1: remote proc finish re-init rpmsg stack
+ * when A core is partition reset.
+ */
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu 0 1
+ &mu 1 1
+ &mu 3 1>;
+ status = "disabled";
};
};
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-08 13:25:13 +0000