summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts60
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts
new file mode 100644
index 000000000000..bc4535647fc4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-lpspi.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2019 NXP
+ */
+
+#include "imx8qxp-lpddr4-val.dts"
+
+&iomuxc {
+ pinctrl_lpspi0: lpspi0grp {
+ fsl,pins = <
+ IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x600004c
+ IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x600004c
+ IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x600004c
+ >;
+ };
+
+ pinctrl_lpspi0_cs: lpspi0cs {
+ fsl,pins = <
+ IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x21
+ >;
+ };
+
+ pinctrl_lpspi2: lpspi2grp {
+ fsl,pins = <
+ IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x600004c
+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x600004c
+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x600004c
+ IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 0x600004c
+ >;
+ };
+};
+
+&lpspi0 {
+ fsl,spi-num-chipselects = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
+ cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash: at45db041e@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <5000000>;
+ reg = <0>;
+ };
+};
+
+&lpspi2 {
+ fsl,spi-num-chipselects = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi2>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <10000000>;
+ };
+};