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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7280.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sc7280.dtsi378
1 files changed, 306 insertions, 72 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 64a2abd30100..4b04dea57ec8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -28,6 +28,7 @@
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,lpass.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/thermal/thermal.h>
@@ -620,12 +621,12 @@
cpu4_opp_2400mhz: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
- opp-peak-kBps = <8532000 48537600>;
+ opp-peak-kBps = <12787200 48537600>;
};
cpu4_opp_2611mhz: opp-2611200000 {
opp-hz = /bits/ 64 <2611200000>;
- opp-peak-kBps = <8532000 48537600>;
+ opp-peak-kBps = <12787200 48537600>;
};
};
@@ -685,22 +686,22 @@
cpu7_opp_2400mhz: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
- opp-peak-kBps = <8532000 48537600>;
+ opp-peak-kBps = <12787200 48537600>;
};
cpu7_opp_2515mhz: opp-2515200000 {
opp-hz = /bits/ 64 <2515200000>;
- opp-peak-kBps = <8532000 48537600>;
+ opp-peak-kBps = <12787200 48537600>;
};
cpu7_opp_2707mhz: opp-2707200000 {
opp-hz = /bits/ 64 <2707200000>;
- opp-peak-kBps = <8532000 48537600>;
+ opp-peak-kBps = <12787200 48537600>;
};
cpu7_opp_3014mhz: opp-3014400000 {
opp-hz = /bits/ 64 <3014400000>;
- opp-peak-kBps = <8532000 48537600>;
+ opp-peak-kBps = <12787200 48537600>;
};
};
@@ -2200,6 +2201,135 @@
qcom,smem-state-names = "wlan-smp2p-out";
};
+ pcie0: pcie@1c00000 {
+ compatible = "qcom,pcie-sc7280";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+ <&pcie0_phy>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq_n>;
+ dma-coherent;
+
+ status = "disabled";
+
+ pcie0_port: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
+ reg = <0 0x01c06000 0 0x1000>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+ };
+
pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
@@ -2240,10 +2370,10 @@
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
@@ -2644,6 +2774,66 @@
status = "disabled";
};
+ lpass_wsa_macro: codec@3240000 {
+ compatible = "qcom,sc7280-lpass-wsa-macro";
+ reg = <0x0 0x03240000 0x0 0x1000>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
+ <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_va_macro>;
+ clock-names = "mclk",
+ "npl",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>;
+ pinctrl-names = "default";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
+ swr2: soundwire@3250000 {
+ compatible = "qcom,soundwire-v1.6.0";
+ reg = <0x0 0x03250000 0x0 0x2000>;
+
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsa_macro>;
+ clock-names = "iface";
+
+ resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,din-ports = <2>;
+ qcom,dout-ports = <6>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07
+ 0x1f 0x3f 0x0f 0x0f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01
+ 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0 0x03300000 0 0x30000>,
@@ -2811,41 +3001,77 @@
lpass_dmic01_clk: dmic01-clk-state {
pins = "gpio6";
function = "dmic1_clk";
+ drive-strength = <8>;
+ bias-disable;
};
lpass_dmic01_data: dmic01-data-state {
pins = "gpio7";
function = "dmic1_data";
+ drive-strength = <8>;
+ bias-pull-down;
};
lpass_dmic23_clk: dmic23-clk-state {
pins = "gpio8";
function = "dmic2_clk";
+ drive-strength = <8>;
+ bias-disable;
};
lpass_dmic23_data: dmic23-data-state {
pins = "gpio9";
function = "dmic2_data";
+ drive-strength = <8>;
+ bias-pull-down;
};
lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
};
lpass_rx_swr_data: rx-swr-data-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
};
lpass_tx_swr_clk: tx-swr-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
};
lpass_tx_swr_data: tx-swr-data-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+
+ lpass_wsa_swr_clk: wsa-swr-clk-state {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ lpass_wsa_swr_data: wsa-swr-data-state {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
};
};
@@ -3711,14 +3937,10 @@
};
};
- usb_2: usb@8cf8800 {
- compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
- reg = <0 0x08cf8800 0 0x400>;
+ usb_2: usb@8c00000 {
+ compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x08c00000 0 0xfc100>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
@@ -3735,11 +3957,13 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "pwr_event",
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@@ -3753,24 +3977,19 @@
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_2_dwc3: usb@8c00000 {
- compatible = "snps,dwc3";
- reg = <0 0x08c00000 0 0xe000>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&apps_smmu 0xa0 0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- phys = <&usb_2_hsphy>;
- phy-names = "usb2-phy";
- maximum-speed = "high-speed";
- usb-role-switch;
+ iommus = <&apps_smmu 0xa0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+ usb-role-switch;
- port {
- usb2_role_switch: endpoint {
- remote-endpoint = <&eud_ep>;
- };
+ port {
+ usb2_role_switch: endpoint {
+ remote-endpoint = <&eud_ep>;
};
};
};
@@ -3822,7 +4041,7 @@
status = "disabled";
- glink-edge {
+ remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
@@ -3862,6 +4081,13 @@
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
+
+ q6usbdai: usbd {
+ compatible = "qcom,q6usb";
+ iommus = <&apps_smmu 0x180f 0x0>;
+ #sound-dai-cells = <1>;
+ qcom,usb-audio-intr-idx = /bits/ 16 <2>;
+ };
};
q6asm: service@7 {
@@ -4013,6 +4239,12 @@
opp-7 {
opp-peak-kBps = <8532000>;
};
+ opp-8 {
+ opp-peak-kBps = <10944000>;
+ };
+ opp-9 {
+ opp-peak-kBps = <12787200>;
+ };
};
};
@@ -4252,14 +4484,10 @@
};
};
- usb_1: usb@a6f8800 {
- compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
- reg = <0 0x0a6f8800 0 0x400>;
+ usb_1: usb@a600000 {
+ compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a600000 0 0xfc100>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -4276,12 +4504,14 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pwr_event",
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
@@ -4298,37 +4528,33 @@
wakeup-source;
- usb_1_dwc3: usb@a600000 {
- compatible = "snps,dwc3";
- reg = <0 0x0a600000 0 0xe000>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&apps_smmu 0xe0 0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_enblslpm_quirk;
- snps,parkmode-disable-ss-quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
- phy-names = "usb2-phy", "usb3-phy";
- maximum-speed = "super-speed";
+ iommus = <&apps_smmu 0xe0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ num-hc-interrupters = /bits/ 16 <3>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy", "usb3-phy";
+ maximum-speed = "super-speed";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port@0 {
+ reg = <0>;
- usb_1_dwc3_hs: endpoint {
- };
+ usb_1_dwc3_hs: endpoint {
};
+ };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- usb_1_dwc3_ss: endpoint {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
- };
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
@@ -4724,6 +4950,8 @@
iommus = <&apps_smmu 0x900 0x402>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -4916,7 +5144,8 @@
reg = <0 0x0aea0000 0 0x200>,
<0 0x0aea0200 0 0x200>,
<0 0x0aea0400 0 0xc00>,
- <0 0x0aea1000 0 0x400>;
+ <0 0x0aea1000 0 0x400>,
+ <0 0x0aea1400 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;
@@ -5285,6 +5514,11 @@
function = "mi2s1_ws";
};
+ pcie0_clkreq_n: pcie0-clkreq-n-state {
+ pins = "gpio88";
+ function = "pcie0_clkreqn";
+ };
+
pcie1_clkreq_n: pcie1-clkreq-n-state {
pins = "gpio79";
function = "pcie1_clkreqn";
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-21 17:21:11 +0000