diff options
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 23 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts | 33 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts | 33 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 34 |
4 files changed, 103 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 2a6d5b9d04f0..664a03ef5161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -3353,18 +3353,31 @@ vpu_encoder: vpu_encoder@2d000000 { compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + boot-region = <&encoder_boot>; rpc-region = <&encoder_rpc>; - fw-buf-size = <0x200000>; - rpc-buf-size = <0x80000>; - print-buf-size = <0x80000>; - reg = <0x0 0x2d000000 0x0 0x1000000>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ reg-names = "vpu_regs"; power-domains = <&pd_vpu_enc>; - reg-fw-base = <0x50000>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1080>; fps-max = <120>; status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; }; imx_rpmsg: imx_rpmsg { compatible = "fsl,rpmsg-bus", "simple-bus"; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts index e409d3b31cc0..1be5bbcf38e9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts @@ -232,18 +232,41 @@ vpu_encoder: vpu_encoder@2d000000 { compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + boot-region = <&encoder_boot>; rpc-region = <&encoder_rpc>; - fw-buf-size = <0x200000 0x200000>; - rpc-buf-size = <0x80000 0x80000>; - print-buf-size = <0x80000 0x80000>; - reg = <0x0 0x2d000000 0x0 0x1000000>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ reg-names = "vpu_regs"; power-domains = <&pd_vpu_enc>; - reg-fw-base = <0x90000 0xa0000>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1080>; fps-max = <120>; status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; }; clk: clk { diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts index b815faf38845..44e18f2125ff 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -294,18 +294,41 @@ vpu_encoder: vpu_encoder@2d000000 { compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + boot-region = <&encoder_boot>; rpc-region = <&encoder_rpc>; - fw-buf-size = <0x200000 0x200000>; - rpc-buf-size = <0x80000 0x80000>; - print-buf-size = <0x80000 0x80000>; - reg = <0x0 0x2d000000 0x0 0x1000000>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ reg-names = "vpu_regs"; power-domains = <&pd_vpu_enc>; - reg-fw-base = <0x90000 0xa0000>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1080>; fps-max = <120>; status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; }; clk: clk { diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index c9bc602a3128..94a83cc7cd66 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -167,6 +167,7 @@ fsl,vpu_ap_mu_id = <17>; status = "okay"; }; + mu2_m0: mu2_m0@2d040000 { compatible = "fsl,imx8-mu2-vpu-m0"; reg = <0x0 0x2d040000 0x0 0x20000>; @@ -188,18 +189,41 @@ vpu_encoder: vpu_encoder@2d000000 { compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + boot-region = <&encoder_boot>; rpc-region = <&encoder_rpc>; - fw-buf-size = <0x200000 0x200000>; - rpc-buf-size = <0x80000 0x80000>; - print-buf-size = <0x80000 0x80000>; - reg = <0x0 0x2d000000 0x0 0x1000000>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ reg-names = "vpu_regs"; power-domains = <&pd_vpu_enc>; - reg-fw-base = <0x90000 0xa0000>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1080>; fps-max = <120>; status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; }; clk: clk { |