diff options
Diffstat (limited to 'arch/arm64')
122 files changed, 29398 insertions, 87 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3e43874568f9..79230bef86b9 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -728,6 +728,7 @@ config FORCE_MAX_ZONEORDER int default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) + default "14" if (ARCH_FSL_IMX8QM || ARCH_FSL_IMX8QXP || ARCH_FSL_IMX8MQ || ARCH_FSL_IMX8QP) default "11" help The kernel memory allocator divides physically contiguous memory diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 3428a4ba2ccd..6f5ed9c32a40 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -231,4 +231,64 @@ config ARCH_ZYNQMP help This enables support for Xilinx ZynqMP Family +config ARCH_FSL_IMX8QM + bool "Freescale i.MX8QM SOC" + select PINCTRL + select PINCTRL_IMX + select PINCTRL_IMX8QM + select PM + select SOC_BUS + select GPIO_MXC_PAD_WAKEUP + help + This enables support for Freescale i.MX8QM SOC. + +config ARCH_FSL_IMX8QP + bool "Freescale i.MX8QP SOC" + select PINCTRL + select PINCTRL_IMX + select PINCTRL_IMX8QM + select PM + select SOC_BUS + select GPIO_MXC_PAD_WAKEUP + help + This enables support for Freescale i.MX8QP SOC. + + +config ARCH_FSL_IMX8QXP + bool "Freescale i.MX8QXP SOC" + select PINCTRL + select PINCTRL_IMX + select PINCTRL_IMX8QXP + select PM + select SOC_BUS + select GPIO_MXC_PAD_WAKEUP + help + This enables support for Freescale i.MX8QXP SOC. + +config ARCH_FSL_IMX8MQ + bool "Freescale i.MX8MQ SOC" + select ARCH_MXC + select SERIAL_IMX + select PINCTRL + select PINCTRL_IMX + select PINCTRL_IMX8MQ + select PM + select SOC_BUS + select KEYBOARD_SNVS_PWRKEY + help + This enables support for Freescale i.MX8MQ SOC. + +config ARCH_FSL_IMX8MM + bool "Freescale i.MX8MM SOC" + select ARCH_MXC + select SERIAL_IMX + select PINCTRL + select PINCTRL_IMX + select PINCTRL_IMX8MM + select PM + select SOC_BUS + select KEYBOARD_SNVS_PWRKEY + help + This enables support for Freescale i.MX8MM SOC. + endmenu diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1b7783db7de4..add632de9db8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -3,7 +3,101 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb - +dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ + fsl-imx8qm-lpddr4-arm2-dom0.dtb \ + fsl-imx8qm-lpddr4-arm2-domu.dtb \ + fsl-imx8qm-ddr4-arm2.dtb \ + fsl-imx8qm-lpddr4-arm2_ca53.dtb \ + fsl-imx8qm-lpddr4-arm2_ca72.dtb \ + fsl-imx8qm-mek.dtb \ + fsl-imx8qm-mek-mipi-ov5640.dtb \ + fsl-imx8qm-mek-mipi-two-ov5640.dtb \ + fsl-imx8qm-mek-8cam.dtb \ + fsl-imx8qm-mek_ca53.dtb \ + fsl-imx8qm-mek_ca72.dtb \ + fsl-imx8qm-mek-hdmi.dtb \ + fsl-imx8qm-mek-hdmi-in.dtb \ + fsl-imx8qm-mek-dsi-rm67191.dtb \ + fsl-imx8qm-mek-enet2-tja1100.dtb \ + fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qm-mek-dom0.dtb \ + fsl-imx8qm-mek-domu.dtb \ + fsl-imx8qm-mek-root.dtb \ + fsl-imx8qm-mek-inmate.dtb \ + fsl-imx8qm-lpddr4-arm2-dp.dtb \ + fsl-imx8qm-lpddr4-arm2-hdmi.dtb \ + fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \ + fsl-imx8qm-lpddr4-arm2-8cam.dtb \ + fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dtb \ + fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qm-lpddr4-arm2-lpspi.dtb \ + fsl-imx8qm-lpddr4-arm2-spdif.dtb \ + fsl-imx8qm-lpddr4-arm2-mqs.dtb \ + fsl-imx8qm-lpddr4-arm2-usb3.dtb \ + fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dtb \ + fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dtb \ + fsl-imx8qm-lpddr4-arm2-hsic.dtb \ + fsl-imx8dm-lpddr4-arm2.dtb \ + fsl-imx8qp-lpddr4-arm2.dtb \ + fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb +dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ + fsl-imx8qxp-mek.dtb \ + fsl-imx8qxp-mek-dom0.dtb \ + fsl-imx8qxp-mek-csi.dtb \ + fsl-imx8qxp-mek-mipi-ov5640.dtb \ + fsl-imx8qxp-mek-ov5640.dtb \ + fsl-imx8qxp-mek-enet2.dtb \ + fsl-imx8qxp-mek-enet2-tja1100.dtb \ + fsl-imx8qxp-mek-dsi-rm67191.dtb \ + fsl-imx8qxp-mek-a0.dtb \ + fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dtb \ + fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dtb \ + fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ + fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ + fsl-imx8qxp-mek-root.dtb \ + fsl-imx8qxp-mek-m4.dtb \ + fsl-imx8qxp-mek-inmate.dtb \ + fsl-imx8qxp-lpddr4-arm2-enet2.dtb \ + fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dtb \ + fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dtb \ + fsl-imx8qxp-lpddr4-arm2-lpspi.dtb \ + fsl-imx8qxp-lpddr4-arm2-spdif.dtb \ + fsl-imx8qxp-lpddr4-arm2-mlb.dtb \ + fsl-imx8qxp-lpddr4-arm2-mqs.dtb \ + fsl-imx8qxp-lpddr4-arm2-wm8962.dtb \ + fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dtb \ + fsl-imx8qxp-lpddr4-arm2-a0.dtb \ + fsl-imx8dx-lpddr4-arm2.dtb \ + fsl-imx8dxp-lpddr4-arm2.dtb +dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ + fsl-imx8mq-ddr4-arm2.dtb \ + fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \ + fsl-imx8mq-evk.dtb \ + fsl-imx8mq-evk-b3.dtb \ + fsl-imx8mq-evk-m4.dtb \ + fsl-imx8mq-evk-pcie1-m2.dtb \ + fsl-imx8mq-evk-lcdif-adv7535.dtb \ + fsl-imx8mq-evk-mipi-csi2.dtb \ + fsl-imx8mq-evk-pdm.dtb \ + fsl-imx8mq-evk-dcss-adv7535.dtb \ + fsl-imx8mq-evk-dcss-rm67191.dtb \ + fsl-imx8mq-evk-dual-display.dtb \ + fsl-imx8mq-evk-ak4497.dtb \ + fsl-imx8mq-evk-audio-tdm.dtb \ + fsl-imx8mq-evk-drm.dtb \ + fsl-imx8mq-evk-root.dtb \ + fsl-imx8mq-evk-inmate.dtb \ + fsl-imx8mq-evk-dp.dtb \ + fsl-imx8mq-evk-edp.dtb +dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \ + fsl-imx8mm-evk-ak4497.dtb \ + fsl-imx8mm-evk-m4.dtb \ + fsl-imx8mm-evk-ak5558.dtb \ + fsl-imx8mm-evk-audio-tdm.dtb \ + fsl-imx8mm-ddr4-val.dtb \ + fsl-imx8mm-evk-rm67191.dtb \ + fsl-imx8mm-evk-root.dtb \ + fsl-imx8mm-evk-inmate.dtb always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8-ca35.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8-ca35.dtsi new file mode 100644 index 000000000000..2a2f155027c6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8-ca35.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/clock/imx8qxp-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters having 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi new file mode 100644 index 000000000000..7f24d09b3ad7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 1 clusters having 4 Cortex-A53 cores */ + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8-ca72.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8-ca72.dtsi new file mode 100644 index 000000000000..944c16002cbf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8-ca72.dtsi @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 2nd clusters having 2 Cortex-A72 cores */ + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72","arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A72_0>, <&A72_1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts new file mode 100644 index 000000000000..412525fcf1b0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dm.dtsi" + +#include "fsl-imx8q-arm2.dtsi" + +/ { + model = "Freescale i.MX8DM ARM2"; + compatible = "fsl,imx8dm-arm2", "fsl,imx8dm", "fsl,imx8qm"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&display{ + ports = <&dpu1_disp0>, <&dpu1_disp1>; +}; + +&prg10 { + status = "disabled"; +}; + +&prg11 { + status = "disabled"; +}; + +&prg12 { + status = "disabled"; +}; + +&prg13 { + status = "disabled"; +}; + +&prg14 { + status = "disabled"; +}; + +&prg15 { + status = "disabled"; +}; + +&prg16 { + status = "disabled"; +}; + +&prg17 { + status = "disabled"; +}; + +&prg18 { + status = "disabled"; +}; + +&dpr3_channel1 { + status = "disabled"; +}; + +&dpr3_channel2 { + status = "disabled"; +}; + +&dpr3_channel3 { + status = "disabled"; +}; + +&dpr4_channel1 { + status = "disabled"; +}; + +&dpr4_channel2 { + status = "disabled"; +}; + +&dpr4_channel3 { + status = "disabled"; +}; + +&dpu2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi new file mode 100644 index 000000000000..eae337eb6422 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8DM"; + compatible = "fsl, imx8dm", "fsl,imx8qm"; + +}; + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; + +&A53_L2 { + compatible = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts new file mode 100644 index 000000000000..23d0714087f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx-lpddr4-arm2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dx.dtsi" + +#include "fsl-imx8x-arm2.dtsi" + +/ { + model = "Freescale i.MX8DX ARM2"; + compatible = "fsl,imx8dx-arm2", "fsl,imx8dx", "fsl,imx8qxp"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi new file mode 100644 index 000000000000..883e63e6093c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -0,0 +1,3369 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "fsl-imx8-ca35.dtsi" +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/clock/imx8qxp-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8DX"; + compatible = "fsl,imx8dx", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + pmu { + interrupt-affinity = <&A35_0>, <&A35_1>; + }; + + aliases { + csi0 = &mipi_csi_0; + dpu0 = &dpu1; + ethernet0 = &fec1; + ethernet1 = &fec2; + dsi_phy0 = &mipi_dsi_phy1; + dsi_phy1 = &mipi_dsi_phy2; + mipi_dsi0 = &mipi_dsi1; + mipi_dsi1 = &mipi_dsi2; + ldb0 = &ldb1; + ldb1 = &ldb2; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x2000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + decoder_rpc: decoder_rpc@0x90400000 { + no-map; + reg = <0 0x90400000 0 0x1000000>; + }; + encoder_rpc: encoder_rpc@0x91400000 { + no-map; + reg = <0 0x91400000 0 0x1000000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + decoder_str: str@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x1800000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + mu: mu@5d1c0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1c0000 0x0 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + mu_m4: mu_m4@37440000 { + compatible = "fsl,imx8-mu0-vpu-m4"; + reg = <0x0 0x37440000 0x0 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <15>; + status = "okay"; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x10000>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x10000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; + }; + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + imx8qx-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = <SC_R_PWM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = <SC_R_PWM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = <SC_R_PWM_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = <SC_R_PWM_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = <SC_R_PWM_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = <SC_R_PWM_5>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = <SC_R_PWM_6>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = <SC_R_PWM_7>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = <SC_R_KPP>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = <SC_R_GPIO_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = <SC_R_GPIO_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = <SC_R_GPIO_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = <SC_R_GPIO_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = <SC_R_GPIO_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = <SC_R_GPIO_5>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = <SC_R_GPIO_6>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = <SC_R_GPIO_7>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = <SC_R_GPT_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = <SC_R_GPT_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = <SC_R_GPT_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = <SC_R_GPT_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = <SC_R_GPT_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = <SC_R_FSPI_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = <SC_R_FSPI_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu5a: PD_LSIO_MU5A { + reg = <SC_R_MU_5A>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = <SC_R_USB_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <267>; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = <SC_R_USB_0_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usbotg0>; + wakeup-irq = <267>; + }; + + }; + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = <SC_R_USB_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2: PD_CONN_USB_2 { + reg = <SC_R_USB_2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <271>; + + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = <SC_R_USB_2_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usb2>; + wakeup-irq = <271>; + }; + + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = <SC_R_SDHC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = <SC_R_SDHC_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = <SC_R_SDHC_2>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = <SC_R_ENET_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <258>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = <SC_R_ENET_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + fsl,wakeup_irq = <262>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = <SC_R_NAND>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = <SC_R_MLB_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = <SC_R_DMA_4_CH0>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = <SC_R_DMA_4_CH1>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = <SC_R_DMA_4_CH2>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = <SC_R_DMA_4_CH3>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = <SC_R_DMA_4_CH4>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = <SC_R_AUDIO_PLL_0>; + power-domains =<&pd_audio>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = <SC_R_AUDIO_PLL_1>; + power-domains =<&pd_audio_pll0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = <SC_R_AUDIO_CLK_0>; + power-domains =<&pd_audio_pll1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = <SC_R_AUDIO_CLK_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_ASRC_0_RXA { + reg = <SC_R_DMA_0_CH0>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_ASRC_0_RXB { + reg = <SC_R_DMA_0_CH1>; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan2: PD_ASRC_0_RXC { + reg = <SC_R_DMA_0_CH2>; + power-domains =<&pd_dma0_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan3: PD_ASRC_0_TXA { + reg = <SC_R_DMA_0_CH3>; + power-domains =<&pd_dma0_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan4: PD_ASRC_0_TXB { + reg = <SC_R_DMA_0_CH4>; + power-domains =<&pd_dma0_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan5: PD_ASRC_0_TXC { + reg = <SC_R_DMA_0_CH5>; + power-domains =<&pd_dma0_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = <SC_R_ASRC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan5>; + }; + }; + }; + }; + }; + }; + }; + + pd_dma1_chan0: PD_ASRC_1_RXA { + reg = <SC_R_DMA_1_CH0>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan1: PD_ASRC_1_RXB { + reg = <SC_R_DMA_1_CH1>; + power-domains =<&pd_dma1_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan2: PD_ASRC_1_RXC { + reg = <SC_R_DMA_1_CH2>; + power-domains =<&pd_dma1_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan3: PD_ASRC_1_TXA { + reg = <SC_R_DMA_1_CH3>; + power-domains =<&pd_dma1_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan4: PD_ASRC_1_TXB { + reg = <SC_R_DMA_1_CH4>; + power-domains =<&pd_dma1_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan5: PD_ASRC_1_TXC { + reg = <SC_R_DMA_1_CH5>; + power-domains =<&pd_dma1_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc1: PD_AUD_ASRC_1 { + reg = <SC_R_ASRC_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dma1_chan5>; + + }; + }; + }; + }; + }; + }; + }; + pd_dma0_chan6: PD_ESAI_0_RX { + reg = <SC_R_DMA_0_CH6>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_ESAI_0_TX { + reg = <SC_R_DMA_0_CH7>; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = <SC_R_ESAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan7>; + }; + }; + }; + pd_dma0_chan8: PD_SPDIF_0_RX { + reg = <SC_R_DMA_0_CH8>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan9: PD_SPDIF_0_TX { + reg = <SC_R_DMA_0_CH9>; + power-domains =<&pd_dma0_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_spdif0: PD_AUD_SPDIF_0 { + reg = <SC_R_SPDIF_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan9>; + + }; + }; + }; + pd_dma0_chan12: PD_SAI_0_RX { + reg = <SC_R_DMA_0_CH12>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan13: PD_SAI_0_TX { + reg = <SC_R_DMA_0_CH13>; + power-domains =<&pd_dma0_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai0:PD_AUD_SAI_0 { + reg = <SC_R_SAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan13>; + }; + }; + + }; + pd_dma0_chan14: PD_SAI_1_RX { + reg = <SC_R_DMA_0_CH14>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan15: PD_SAI_1_TX { + reg = <SC_R_DMA_0_CH15>; + power-domains =<&pd_dma0_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai1: PD_AUD_SAI_1 { + reg = <SC_R_SAI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan15>; + }; + }; + }; + pd_dma0_chan16: PD_SAI_2_RX { + reg = <SC_R_DMA_0_CH16>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai2: PD_AUD_SAI_2 { + reg = <SC_R_SAI_2>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan16>; + }; + }; + pd_dma0_chan17: PD_SAI_3_RX { + reg = <SC_R_DMA_0_CH17>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai3: PD_AUD_SAI_3 { + reg = <SC_R_SAI_3>; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan17>; + }; + }; + pd_dma1_chan8: PD_SAI_4_RX { + reg = <SC_R_DMA_1_CH8>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan9: PD_SAI_4_TX { + reg = <SC_R_DMA_1_CH9>; + power-domains =<&pd_dma1_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai4: PD_AUD_SAI_4 { + reg = <SC_R_SAI_4>; + #power-domain-cells = <0>; + power-domains =<&pd_dma1_chan9>; + + }; + }; + }; + pd_dma1_chan10: PD_SAI_5_TX { + reg = <SC_R_DMA_1_CH10>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai5: PD_AUD_SAI_5 { + reg = <SC_R_SAI_5>; + #power-domain-cells = <0>; + power-domains =<&pd_dma1_chan10>; + }; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = <SC_R_GPT_5>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = <SC_R_GPT_6>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = <SC_R_GPT_7>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = <SC_R_GPT_8>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt9: PD_AUD_GPT_9 { + reg = <SC_R_GPT_9>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt10: PD_AUD_GPT_10 { + reg = <SC_R_GPT_10>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_amix: PD_AUD_AMIX { + reg = <SC_R_AMIX>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = <SC_R_MQS_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = <SC_R_MCLK_OUT_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = <SC_R_MCLK_OUT_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + }; + }; + }; + }; + + pd_dsp_mu_A: PD_DSP_MU_A { + reg = <SC_R_MU_13A>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_B: PD_DSP_MU_B { + reg = <SC_R_MU_13B>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_A>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = <SC_R_DSP_RAM>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = <SC_R_DSP>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; + }; + }; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = <SC_R_CAN_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <235>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = <SC_R_CAN_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <236>; + }; + + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = <SC_R_CAN_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <237>; + }; + }; + + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = <SC_R_FTM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = <SC_R_FTM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = <SC_R_ADC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = <SC_R_I2C_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = <SC_R_I2C_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = <SC_R_I2C_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = <SC_R_I2C_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = <SC_R_UART_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <225>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = <SC_R_UART_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <226>; + + pd_dma2_chan10: PD_UART1_RX { + reg = <SC_R_DMA_2_CH10>; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan11: PD_UART1_TX { + reg = <SC_R_DMA_2_CH11>; + power-domains =<&pd_dma2_chan10>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <227>; + + pd_dma2_chan12: PD_UART2_RX { + reg = <SC_R_DMA_2_CH12>; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = <SC_R_DMA_2_CH13>; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = <SC_R_UART_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <228>; + + pd_dma3_chan14: PD_UART3_RX { + reg = <SC_R_DMA_2_CH14>; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan15: PD_UART3_TX { + reg = <SC_R_DMA_2_CH15>; + power-domains =<&pd_dma3_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = <SC_R_SPI_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = <SC_R_SPI_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = <SC_R_SPI_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = <SC_R_SPI_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_pwm0: PD_DMA_PWM_0 { + reg = <SC_R_LCD_0_PWM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + + pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { + reg = <SC_R_ELCDIF_PLL>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = <SC_R_LCD_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma_elcdif_pll>; + }; + }; + }; + + pd_gpu: gpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu0: gpu0 { + name = "gpu0"; + reg = <SC_R_GPU_0_PID0>; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pd_vpu: vpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_VPU>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_mu_enc: VPU_ENC_MU { + reg = <SC_R_VPU_MU_1>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_enc: VPU_ENC { + reg = <SC_R_VPU_ENC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_enc>; + }; + }; + + pd_vpu_mu_dec: VPU_DEC_MU { + reg = <SC_R_VPU_MU_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_dec: VPU_DEC { + reg = <SC_R_VPU_DEC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_dec>; + }; + }; + }; + + pd_hsio: hsio-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hsio_gpio: PD_HSIO_GPIO { + reg = <SC_R_HSIO_GPIO>; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = <SC_R_SERDES_1>; + #power-domain-cells = <0>; + power-domains =<&pd_hsio_gpio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: PD_HSIO_PCIE_B { + reg = <SC_R_PCIE_B>; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = <SC_R_M4_0_I2C>; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = <SC_R_M4_0_INTMUX>; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + early_power_on; + }; + }; + + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_DC_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = <SC_R_DC_0_PLL_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = <SC_R_DC_0_PLL_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + pd_mipi_dsi0: PD_MIPI_0_DSI { + reg = <SC_R_MIPI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_0_lvds: PD_LVDS0 { + reg = <SC_R_LVDS_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + + pd_mipi_dsi_0_aux_lvds: PD_AUX_LVDS0 { + reg = <SC_R_LVDS_0>; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_1_dual_lvds: PD_DUAL_LVDS1 { + reg = <SC_R_LVDS_1>; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi_0_aux_lvds>; + }; + }; + + pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = <SC_R_MIPI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = <SC_R_MIPI_0_I2C_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { + reg = <SC_R_MIPI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + }; + + pd_mipi_dsi1: PD_MIPI_1_DSI { + reg = <SC_R_MIPI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_1_lvds: PD_LVDS1 { + reg = <SC_R_LVDS_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + + pd_mipi_dsi_1_aux_lvds: PD_AUX_LVDS1 { + reg = <SC_R_LVDS_1>; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_0_dual_lvds: PD_DUAL_LVDS0 { + reg = <SC_R_LVDS_0>; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi_1_aux_lvds>; + }; + }; + + pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = <SC_R_MIPI_1_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = <SC_R_MIPI_1_I2C_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { + reg = <SC_R_MIPI_1_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + }; + }; + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = <SC_R_ISI_CH0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_csi: PD_MIPI_CSI0 { + reg = <SC_R_CSI_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C0 { + reg = <SC_R_CSI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + + pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { + name = "mipi_csi0_pwm"; + reg = <SC_R_CSI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + }; + + pd_parallel_csi: PD_PARALLEL_CSI { + reg = <SC_R_PI_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_parallel_csi_i2c0: PD_PARALLEL_CSI_I2C { + name = "parallel_csi_i2c"; + reg = <SC_R_PI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + + pd_parallel_csi_pwm0: PD_PARALLEL_CSI_PWM { + name = "parallel_csi_pwm"; + reg = <SC_R_PI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + + pd_parallel_csi_pll: PD_PARALLEL_CSI_PLL { + name = "parallel_csi_pll"; + reg = <SC_R_PI_0_PLL>; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + }; + + pd_isi_ch1: PD_IMAGING_PDMA1 { + reg = <SC_R_ISI_CH1>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch2: PD_IMAGING_PDMA2 { + reg = <SC_R_ISI_CH2>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch3: PD_IMAGING_PDMA3 { + reg = <SC_R_ISI_CH3>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch4: PD_IMAGING_PDMA4 { + reg = <SC_R_ISI_CH4>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch5: PD_IMAGING_PDMA5 { + reg = <SC_R_ISI_CH5>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch6: PD_IMAGING_PDMA6 { + reg = <SC_R_ISI_CH6>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch7: PD_IMAGING_PDMA7 { + reg = <SC_R_ISI_CH7>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_jpeg_dec_mp: PD_JPEG_DEC_MP{ + reg = <SC_R_MJPEG_DEC_MP>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_jpgdec: PD_IMAGING_JPEG_DEC { + reg = <SC_R_MJPEG_DEC_S0>; + #power-domain-cells = <0>; + power-domains =<&pd_jpeg_dec_mp>; + }; + }; + + pd_jpeg_enc_mp: PD_JPEG_ENC_MP{ + reg = <SC_R_MJPEG_ENC_MP>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_jpgenc: PD_IMAGING_JPEG_ENC { + reg = <SC_R_MJPEG_ENC_S0>; + #power-domain-cells = <0>; + power-domains =<&pd_jpeg_enc_mp>; + }; + }; + }; + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = <SC_R_CAAM_JR1>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = <SC_R_CAAM_JR2>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = <SC_R_CAAM_JR3>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + /* number of the temp sensor on the chip */ + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + status = "disabled"; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + irqsteer_csi: irqsteer@58220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58220000 0x0 0x1000>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg"; + power-domains = <&pd_mipi_csi>; + }; + + i2c0_csi0: i2c@58226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, + <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_csi_i2c0>; + status = "disabled"; + }; + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QXP_CM40_I2C_CLK>, + <&clk IMX8QXP_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + status = "disabled"; + }; + + dpu_intsteer: dpu_intsteer@56000000 { + compatible = "fsl,imx8qxp-dpu-intsteer", "syscon"; + reg = <0x0 0x56000000 0x0 0x10000>; + }; + + prg1: prg@56040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56040000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG0_APB_CLK>, + <&clk IMX8QXP_DC0_PRG0_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg2: prg@56050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56050000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG1_APB_CLK>, + <&clk IMX8QXP_DC0_PRG1_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg3: prg@56060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56060000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG2_APB_CLK>, + <&clk IMX8QXP_DC0_PRG2_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg4: prg@56070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56070000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG3_APB_CLK>, + <&clk IMX8QXP_DC0_PRG3_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg5: prg@56080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56080000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG4_APB_CLK>, + <&clk IMX8QXP_DC0_PRG4_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg6: prg@56090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56090000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG5_APB_CLK>, + <&clk IMX8QXP_DC0_PRG5_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg7: prg@560a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x560a0000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG6_APB_CLK>, + <&clk IMX8QXP_DC0_PRG6_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg8: prg@560b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x560b0000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG7_APB_CLK>, + <&clk IMX8QXP_DC0_PRG7_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg9: prg@560c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x560c0000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG8_APB_CLK>, + <&clk IMX8QXP_DC0_PRG8_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel1: dpr-channel@560d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560d0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_BLIT0>; + fsl,prgs = <&prg1>; + clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, + <&clk IMX8QXP_DC0_DPR0_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel2: dpr-channel@560e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560e0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_BLIT1>; + fsl,prgs = <&prg2>, <&prg1>; + clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, + <&clk IMX8QXP_DC0_DPR0_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel3: dpr-channel@560f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560f0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_FRAC0>; + fsl,prgs = <&prg3>; + clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, + <&clk IMX8QXP_DC0_DPR0_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel1: dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56100000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_VIDEO0>; + fsl,prgs = <&prg4>, <&prg5>; + clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, + <&clk IMX8QXP_DC0_DPR1_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel2: dpr-channel@56110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56110000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_VIDEO1>; + fsl,prgs = <&prg6>, <&prg7>; + clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, + <&clk IMX8QXP_DC0_DPR1_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel3: dpr-channel@56120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56120000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_WARP>; + fsl,prgs = <&prg8>, <&prg9>; + clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, + <&clk IMX8QXP_DC0_DPR1_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu_intsteer>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit", + "irq_dpr0", + "irq_dpr1"; + clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, + <&clk IMX8QXP_DC0_PLL1_CLK>, + <&clk IMX8QXP_DC0_DISP0_CLK>, + <&clk IMX8QXP_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd_dc0_pll1>; + fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, + <&dpr1_channel3>, <&dpr2_channel1>, + <&dpr2_channel2>, <&dpr2_channel3>; + status = "disabled"; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_lvds0_ch0: lvds0-endpoint { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_lvds0_ch1: lvds1-endpoint { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi1_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_lvds1_ch0: lvds0-endpoint { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_lvds1_ch1: lvds1-endpoint { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi2_in>; + }; + }; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi0>; + }; + + mipi_dsi_csr1: csr@56221000 { + compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; + reg = <0x0 0x56221000 0x0 0x1000>; + }; + + mipi_dsi_phy1: dsi_phy@56228300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qxp-mipi-dsi-phy"; + reg = <0x0 0x56228300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>, + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; + assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-parents = + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>; + power-domains = <&pd_mipi_dsi0>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge1_in: endpoint { + remote-endpoint = <&mipi_dsi1_out>; + }; + }; + }; + + mipi_dsi1: mipi_dsi@56228000 { + compatible = "fsl,imx8qxp-mipi-dsi"; + clocks = + <&clk IMX8QXP_MIPI0_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_BYPASS_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi_dsi0>; + csr = <&mipi_dsi_csr1>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi1_in: endpoint { + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi1_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_in>; + }; + }; + }; + + lvds_region1: lvds_region@56220000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56220000 0x0 0x10000>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; + clock-names = "phy"; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; + power-domains = <&pd_mipi_dsi_0_lvds>; + gpr = <&lvds_region1>; + aux-gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>, <&ldb2_phy>; + phy-names = "ldb_phy", "aux_ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds0: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x56224000 0 0x1000>; + clocks = <&clk IMX8QXP_MIPI0_PWM_IPG_CLK>, + <&clk IMX8QXP_MIPI0_PWM_CLK>, + <&clk IMX8QXP_MIPI0_PWM_32K_CLK>; + clock-names = "ipg", "per", "32k"; + assigned-clocks = <&clk IMX8QXP_MIPI0_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_mipi_0_pwm0>; + status = "disabled"; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, + <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_0_i2c0>; + status = "disabled"; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi1>; + }; + + mipi_dsi_csr2: csr@56241000 { + compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; + reg = <0x0 0x56241000 0x0 0x1000>; + }; + + mipi_dsi_phy2: dsi_phy@56248300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qxp-mipi-dsi-phy"; + reg = <0x0 0x56248300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge2: mipi_dsi_bridge@56248000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56248000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = + <&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>, + <&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>, + <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; + assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-parents = + <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>; + power-domains = <&pd_mipi_dsi1>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge2_in: endpoint { + remote-endpoint = <&mipi_dsi2_out>; + }; + }; + }; + + mipi_dsi2: mipi_dsi@56248000 { + compatible = "fsl,imx8qxp-mipi-dsi"; + clocks = + <&clk IMX8QXP_MIPI1_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_BYPASS_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi_dsi1>; + csr = <&mipi_dsi_csr2>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi2_in: endpoint { + remote-endpoint = <&dpu_disp1_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi2_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_in>; + }; + }; + }; + + lvds_region2: lvds_region@56240000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; + clock-names = "phy"; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; + power-domains = <&pd_mipi_dsi_1_lvds>; + gpr = <&lvds_region2>; + aux-gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>, <&ldb1_phy>; + phy-names = "ldb_phy", "aux_ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch1>; + }; + }; + }; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58100000 0x0 0x10000>; + interrupts = <0 297 0>; + interface = <2 0 2>; /* <Input MIPI_VCx Output> + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch0>; + status = "disabled"; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58110000 0x0 0x10000>; + interrupts = <0 298 0>; + interface = <2 1 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch1>; + status = "disabled"; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58120000 0x0 0x10000>; + interrupts = <0 299 0>; + interface = <2 2 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch2>; + status = "disabled"; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58130000 0x0 0x10000>; + interrupts = <0 300 0>; + interface = <2 3 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch3>; + status = "disabled"; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58140000 0x0 0x10000>; + interrupts = <0 301 0>; + interface = <3 0 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch4>; + status = "disabled"; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58150000 0x0 0x10000>; + interrupts = <0 302 0>; + interface = <3 1 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch5>; + status = "disabled"; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58160000 0x0 0x10000>; + interrupts = <0 303 0>; + interface = <3 2 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch6>; + status = "disabled"; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58170000 0x0 0x10000>; + interrupts = <0 304 0>; + interface = <3 3 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch7>; + status = "disabled"; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ + <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CSI0_CORE_CLK>, + <&clk IMX8QXP_CSI0_ESC_CLK>, + <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>, + <&clk IMX8QXP_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_mipi_csi>; + status = "disabled"; + }; + + parallel_csi: pcsi@58261000 { + compatible = "fsl,mxc-parallel-csi"; + reg = <0x0 0x58261000 0x0 0x1000>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_PIXEL_CLK>, + <&clk IMX8QXP_PARALLEL_CSI_IPG_CLK>, + <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, + <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>, + <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; + clock-names = "pixel", "ipg", "sel", "div", "dpll"; + assigned-clocks = <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, + <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>; + assigned-clock-parents = <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; + assigned-clock-rates = <0>, <160000000>; /* 160MHz */ + power-domains = <&pd_parallel_csi>; + status = "disabled"; + }; + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x0 0x58400000 0x0 0x00040020 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_DEC_CLK >; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_DEC_CLK >; + assigned-clock-rates = <200000000>; + power-domains =<&pd_jpgdec>; + status = "okay"; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x0 0x58450000 0x0 0x00240020 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_ENC_CLK >; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_ENC_CLK >; + assigned-clock-rates = <200000000>; + power-domains =<&pd_jpgenc>; + status = "okay"; + }; + }; + + pwm_mipi_lvds1: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x56244000 0 0x1000>; + clocks = <&clk IMX8QXP_MIPI1_PWM_IPG_CLK>, + <&clk IMX8QXP_MIPI1_PWM_CLK>, + <&clk IMX8QXP_MIPI1_PWM_32K_CLK>; + clock-names = "ipg", "per", "32k"; + assigned-clocks = <&clk IMX8QXP_MIPI1_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_mipi_1_pwm0>; + status = "disabled"; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56246000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, + <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_1_i2c0>; + status = "disabled"; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_ADC0_CLK>, + <&clk IMX8QXP_ADC0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_ADC0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_adc0>; + status = "disabled"; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C1_CLK>, + <&clk IMX8QXP_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C3_CLK>, + <&clk IMX8QXP_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x200>; + clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan1>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan2>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x0 0x5b810000 0x0 0x2000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8QXP_APBHDMA_CLK>; + power-domains = <&pd_conn_nand>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, + <&clk IMX8QXP_GPMI_APB_CLK>, + <&clk IMX8QXP_GPMI_BCH_CLK>, + <&clk IMX8QXP_GPMI_APB_BCH_CLK>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd_conn_nand>; + assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QXP_USB3_PHY_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usb2_phy>; + }; + + usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>, + <0x0 0x5B120000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_USB3_LPM_CLK>, + <&clk IMX8QXP_USB3_BUS_CLK>, + <&clk IMX8QXP_USB3_ACLK>, + <&clk IMX8QXP_USB3_IPG_CLK>, + <&clk IMX8QXP_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + status = "disabled"; + }; + + wu: wu { + compatible = "fsl,imx8-wu"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x58222000 0x0 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_mipi_csi>; + }; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x53100000 0 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd_gpu0>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + depth-compression = <0>; + status = "disabled"; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI0_CLK>, + <&clk IMX8QXP_SPI0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; + assigned-clock-rates = <20000000>; + power-domains = <&pd_dma_lpspi0>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART1_CLK>, + <&clk IMX8QXP_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan11>; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan13>; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART3_CLK>, + <&clk IMX8QXP_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma3_chan15>; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; + status = "disabled"; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ + <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ + <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ + <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + status = "okay"; + }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <16>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + status = "okay"; + }; + + edma1: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ + "edma1-chan2-rx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ + "edma1-chan10-tx"; /* sai5 */ + status = "okay"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_0_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59060000 0x0 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_2_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + status = "disabled"; + power-domains = <&pd_sai2>; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59070000 0x0 0x10000>; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_3_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + status = "disabled"; + power-domains = <&pd_sai3>; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59820000 0x0 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + status = "disabled"; + power-domains = <&pd_sai4>; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59830000 0x0 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + status = "disabled"; + power-domains = <&pd_sai5>; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + status = "disabled"; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x0 0x59800000 0x0 0x10000>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, + <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc1>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_MQS_IPG>, + <&clk IMX8QXP_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, + <&clk IMX8QXP_SDHC1_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, + <&clk IMX8QXP_SDHC2_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, + <&clk IMX8QXP_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, + <&clk IMX8QXP_ENET1_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; + + mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; + }; + + dsp: dsp@586e8000 { + compatible = "fsl,imx8qxp-dsp"; + reserved-region = <&dsp_reserved>; + reg = <0x0 0x596e8000 0x0 0x88000>; + clocks = <&clk IMX8QXP_AUD_DSP_IPG>, + <&clk IMX8QXP_AUD_OCRAM_IPG>, + <&clk IMX8QXP_AUD_DSP_CORE_CLK>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd_dsp>; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x0 0x59010000 0x0 0x10000>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_esai0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QXP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clock-rates = <29000000>; + clock-names = "fspi"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + ocotp: ocotp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8qxp-ocotp", "syscon"; + }; + + pcieb: pcie@0x5f010000 { + /* + * pcieb phyx1 lane1 in default, adjust it refer to the + * exact hw design. + */ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, + <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, + <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie>; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX2PCIEBX1>; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu", "nxp,imx8qxp-vpu"; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + interrupts = <0 464 0x4>, /* encoder irq */ + <0 465 0x4>, /* encoder fiq */ + <0 466 0x4>, /* decoder irq */ + <0 467 0x4>, /* decoder fiq */ + <0 468 0x4>; /* decoder sif */ + interrupt-names = "enc_irq", "enc_fiq", "dec_irq", "dec_fiq", "dec_sif"; + clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + clock-names = "vpu_clk"; + assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + str-region = <&decoder_str>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + clock-names = "vpu_clk"; + assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reg = <0x0 0x2d000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + clocks = <&clk IMX8QXP_VPU_ENC_CLK>; + clock-names = "vpu_encoder_clk"; + assigned-clocks = <&clk IMX8QXP_VPU_ENC_CLK>; + power-domains = <&pd_vpu_enc>; + status = "disabled"; + }; + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu_rpmsg: mu_rpmsg@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x5d200000 0x0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu5a>; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + status = "disabled"; + power-domains = <&pd_lsio_mu5a>; + }; + }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x1ffff>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + + wdog: wdog { + compatible = "fsl,imx8-wdt"; + }; +}; + +&A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 1000000 0 + >; + clocks = <&clk IMX8QXP_A35_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; + +/delete-node/ &A35_2; +/delete-node/ &A35_3; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts new file mode 100644 index 000000000000..c8b9e57f10d0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dxp-lpddr4-arm2.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dxp.dtsi" + +#include "fsl-imx8x-arm2.dtsi" + +/ { + model = "Freescale i.MX8DXP ARM2"; + compatible = "fsl,imx8dxp-arm2", "fsl,imx8dxp", "fsl,imx8qxp"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dxp.dtsi new file mode 100644 index 000000000000..6e11a7b5788e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dxp.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include "fsl-imx8dx.dtsi" + +/ { + model = "Freescale i.MX8DXP"; + compatible = "fsl,imx8dxp", "fsl,imx8qxp"; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + clock-names = "vpu_clk"; + assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>, + <0x0 0x5B120000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_USB3_LPM_CLK>, + <&clk IMX8QXP_USB3_BUS_CLK>, + <&clk IMX8QXP_USB3_ACLK>, + <&clk IMX8QXP_USB3_IPG_CLK>, + <&clk IMX8QXP_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + status = "disabled"; + }; +}; + +&gpu_3d0 { + assigned-clock-rates = <700000000>, <850000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts new file mode 100644 index 000000000000..797f21d166fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-val.dts @@ -0,0 +1,541 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM DDR4 validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_typec2: typec2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x159 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu256aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + typec1_ptn5110: tcpci@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8>; + /* Only can sink 5V for safe */ + max-snk-mv = <5000>; + max-snk-ma = <3000>; + op-snk-mw = <10000>; + max-snk-mw = <15000>; + port-type = "drp"; + default-role = "sink"; + status = "okay"; + }; + + typec2_ptn5110: tcpci@52 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec2>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <12 8>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8>; + /* Only can sink 5V for safe */ + max-snk-mv = <5000>; + max-snk-ma = <3000>; + op-snk-mw = <10000>; + max-snk-mw = <15000>; + port-type = "drp"; + default-role = "sink"; + status = "disabled"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + extcon = <0>, <&typec1_ptn5110>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "otg"; + extcon = <0>, <&typec2_ptn5110>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts new file mode 100644 index 000000000000..95b09f294437 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak4497.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + imx8mm-evk { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1_SRC>, + <&clk IMX8MM_CLK_SAI1_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <0>, <22579200>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0xff 0x11>; + dmas = <&sdma2 0 26 0>, <&sdma2 1 26 0>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts new file mode 100644 index 000000000000..0268b09a2755 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-ak5558.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + sound-ak5558 { + status = "okay"; + }; + sound-micfil { + status = "disabled"; + }; +}; + +&micfil { + status = "disabled"; +}; + +&sai5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts new file mode 100644 index 000000000000..fc1826bb90cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk-ak5558.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-inmate.dts new file mode 100644 index 000000000000..a6eba06f3503 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-inmate.dts @@ -0,0 +1,224 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "Freescale i.MX8MM EVK"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + interrupt-parent = <&gic>; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clocks { + clk_dummy: clock@7 { + compatible = "fixed-clock"; + reg = <7>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_200m: clock@8 { + compatible = "fixed-clock"; + reg = <8>; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + reg = <9>; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + reg = <10>; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + }; + + display-subsystem { + /delete-property/ compatible; + }; + + pci@bfb00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0x7fb00000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; +}; + +/delete-node/ &{/memory@40000000}; +/delete-node/ &{/reserved-memory}; +/delete-node/ &{/busfreq}; +/delete-node/ &ddr_pmu0; + +&hsio_pd { + status = "disabled"; +}; + +&pcie0_pd { + status = "disabled"; +}; + +&usb_otg1_pd { + status = "disabled"; +}; + +&usb_otg2_pd { + status = "disabled"; +}; + +&gpumix_pd { + status = "disabled"; +}; + +&vpumix_pd { + status = "disabled"; +}; + +&vpu_g1_pd { + status = "disabled"; +}; + +&vpu_g2_pd { + status = "disabled"; +}; + +&vpu_h1_pd { + status = "disabled"; +}; + +&dispmix_pd { + status = "disabled"; +}; + +&mipi_pd { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; +&gpio2 { + status = "disabled"; +}; +&gpio3 { + status = "disabled"; +}; +&gpio4 { + status = "disabled"; +}; +&gpio5 { + status = "disabled"; +}; + +/delete-node/ &tmu; +/delete-node/ &{/thermal-zones}; +/delete-node/ &iomuxc; + +&gpr { + /delete-property/ compatible; +}; + +/delete-node/ &anatop; +/delete-node/ &snvs; + +&clk { + /delete-property/ compatible; +}; + +&src { + /delete-property/ compatible; +}; + +/delete-node/ &system_counter; + +/delete-node/ &imx_rpmsg; +/delete-node/ &ocotp; + +&dispmix_gpr { + /delete-property/ compatible; +}; + +&sdma1 { + status = "disabled"; +}; + +&sdma2 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +/delete-node/ &{/imx_ion}; +/delete-node/ &pcie0; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &caam_snvs; +/delete-node/ &irq_sec_vio; + +/delete-node/ &{/cpus/cpu@0}; +/delete-node/ &{/cpus/cpu@1}; +/delete-node/ &{/pmu}; + +&gic { + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_200m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts new file mode 100644 index 000000000000..1f9c6676ccfb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-m4.dts @@ -0,0 +1,82 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + }; + + sound-wm8524 { + status = "disabled"; + }; + + wm8524: wm8524 { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8mq-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + fsl,dma-buffer-size = <0x6000000>; + status = "okay"; + }; + + sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "rpmsg-audio"; + cpu-dai = <&rpmsg_i2s>; + rpmsg-out; + }; + +}; + +/* + * ATTENTION: M4 may use IPs like below + * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1 + */ + +&i2c3 { + status = "disabled"; +}; + +&sdma1{ + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&sai3 { + status = "disabled"; +}; + +&sdma3 { + status = "disabled"; +}; + +&sai1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts new file mode 100644 index 000000000000..d7c17e33ffdf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-rm67191.dts @@ -0,0 +1,35 @@ +#include "fsl-imx8mm-evk.dts" + +&adv_bridge { + status = "disabled"; +}; + +&mipi_dsi { + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + }; +}; + +&i2c2 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts new file mode 100644 index 000000000000..ff5d60766461 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts @@ -0,0 +1,109 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mm-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +/delete-node/ &gpc; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + /delete-property/ compatible; + /*arm,psci-suspend-param = <0x0>;*/ +}; + +&clk { + init-on-array = <IMX8MM_CLK_AHB_CG IMX8MM_CLK_DRAM_CORE + IMX8MM_CLK_NOC_CG IMX8MM_CLK_NOC_APB_CG + IMX8MM_CLK_USB_BUS_CG + IMX8MM_CLK_MAIN_AXI_CG IMX8MM_CLK_AUDIO_AHB_CG + IMX8MM_CLK_DRAM_APB_DIV IMX8MM_CLK_A53_DIV + IMX8MM_ARM_PLL_OUT IMX8MM_CLK_DISP_AXI_CG + IMX8MM_CLK_DISP_APB_CG + IMX8MM_CLK_NAND_USDHC_BUS_CG>; +}; + +&iomuxc { + imx8mq-evk { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&{/reserved-memory} { + jh_reserved: jh@0xbfc00000 { + no-map; + reg = <0 0xbfc00000 0x0 0x400000>; + }; + + inmate_reserved: inmate@0x80000000 { + no-map; + reg = <0 0x80000000 0x0 0x3fc00000>; + }; + + loader_reserved: loader@0x7ff00000 { + no-map; + reg = <0 0x7ff00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0x7fe00000 { + no-map; + reg = <0 0x7fe00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0x7fd00000 { + no-map; + reg = <0 0x7fd00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0x7fb00000 { + no-map; + reg = <0 0x7fb00000 0x0 0x00200000>; + }; +}; + +&uart2 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4_SRC>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; +}; + +&usdhc3 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc3 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts new file mode 100755 index 000000000000..1f2006e432aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts @@ -0,0 +1,1016 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mm.dtsi" + +/ { + model = "FSL i.MX8MM EVK board"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio3 16 0>; + default-state = "on"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio_board: regulator-audio-board { + compatible = "regulator-fixed"; + regulator-name = "EXT_PWREN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <300000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + }; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + status = "disabled"; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-micfil { + compatible = "fsl,imx-audio-micfil"; + model = "imx-audio-micfil"; + cpu-dai = <&micfil>; + }; +}; + +&clk { + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; + assigned-clock-rates = <786432000>, <722534400>; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-evk { + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; + + pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch int */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_typec2: typec2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x159 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&csi1_bridge { + fsl,mipi-mode; + status = "okay"; + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu256aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + + typec1_ptn5110: tcpci@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 8>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8>; + /* Only can sink 5V for safe */ + max-snk-mv = <5000>; + max-snk-ma = <3000>; + op-snk-mw = <10000>; + max-snk-mw = <15000>; + port-type = "drp"; + default-role = "sink"; + status = "okay"; + }; + + typec2_ptn5110: tcpci@52 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec2>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <12 8>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8>; + /* Only can sink 5V for safe */ + max-snk-mv = <5000>; + max-snk-ma = <3000>; + op-snk-mw = <10000>; + max-snk-mw = <15000>; + port-type = "drp"; + default-role = "sink"; + status = "okay"; + }; +}; + + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi1_mipi_ep: endpoint2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_audio_board>; + DVDD-supply = <®_audio_board>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MM_CLK_CLKO1_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>, + <&clk IMX8MM_CLK_CLKO1_DIV>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <0>, <24000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX8MM_CLK_SAI1_SRC>, + <&clk IMX8MM_CLK_SAI1_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <49152000>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3_SRC>, + <&clk IMX8MM_CLK_SAI3_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5_SRC>, + <&clk IMX8MM_CLK_SAI5_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1_SRC>, + <&clk IMX8MM_CLK_SPDIF1_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1_DIV>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + ext_osc = <0>; + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + extcon = <0>, <&typec1_ptn5110>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "otg"; + extcon = <0>, <&typec2_ptn5110>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + vmmc-supply = <®_sd1_vmmc>; + pm-ignore-notify; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +&gpu { + status = "okay"; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM_SRC>, <&clk IMX8MM_CLK_PDM_DIV>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <196608000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi new file mode 100755 index 000000000000..6ec6265cd6d7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -0,0 +1,1246 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8-ca53.dtsi" +#include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pins-imx8mm.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "fsl,imx8mm"; + interrupt-parent = <&gpc>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <25000>; + exit-latency-us = <10000>; + min-residency-us = <30000>; + wakeup-latency-us = <15000>; + }; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x40000000 0 0x60000000>; + linux,cma-default; + }; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT_SRC>, + <&clk IMX8MM_CLK_DRAM_APB_SRC>, <&clk IMX8MM_CLK_DRAM_APB_PRE_DIV>, + <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>, + <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC_DIV>, + <&clk IMX8MM_CLK_AHB_DIV>, <&clk IMX8MM_CLK_MAIN_AXI_SRC>, + <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + + ddr_pmu0: ddr_pmu@3d800000 { + compatible = "fsl,imx8m-ddr-pmu", "fsl,imx8-ddr-pmu"; + reg = <0x0 0x3d800000 0x0 0x400000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc_32k: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock@2 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock@3 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock@4 { + compatible = "fixed-clock"; + reg = <5>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock@5 { + compatible = "fixed-clock"; + reg = <6>; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + }; + + power-domains { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* HSIOMIX */ + hsio_pd: power-domain@0 { + compatible = "fsl,imx8mm-pm-domain"; + #address-cells = <1>; + #size-cells = <0>; + domain-id = <0>; + #power-domain-cells = <0>; + domain-name = "HSIO_PD"; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + + pcie0_pd: power-domain@1 { + domain-id = <1>; + #power-domain-cells = <0>; + domain-name = "PCIE0_PD"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; + }; + + usb_otg1_pd: power-domain@2 { + domain-id = <2>; + #power-domain-cells = <0>; + domain-name = "USB_OTG1_PD"; + }; + + usb_otg2_pd: power-domain@3 { + domain-id = <3>; + #power-domain-cells = <0>; + domain-name = "USB_OTG2_PD"; + }; + }; + + /* GPU2D&3D */ + gpumix_pd: power-domain@4 { + compatible = "fsl,imx8mm-pm-domain"; + domain-id = <4>; + #power-domain-cells = <0>; + domain-name = "GPUMIX_PD"; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB_DIV>; + }; + + vpumix_pd: power-domain@5 { + compatible = "fsl,imx8mm-pm-domain"; + #address-cells = <1>; + #size-cells = <0>; + domain-id = <5>; + #power-domain-cells = <0>; + domain-name = "VPUMIX_PD"; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + + vpu_g1_pd: power-domain@6 { + domain-id = <6>; + #power-domain-cells = <0>; + domain-name = "VPU_G1_PD"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: power-domain@7 { + domain-id = <7>; + #power-domain-cells = <0>; + domain-name = "VPU_G2_PD"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: power-domain@8 { + domain-id = <8>; + #power-domain-cells = <0>; + domain-name = "VPU_H1_PD"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; + }; + }; + + dispmix_pd: power-domain@9 { + compatible = "fsl,imx8mm-pm-domain"; + #address-cells = <1>; + #size-cells = <0>; + domain-id = <9>; + #power-domain-cells = <0>; + domain-name = "DISPMIX_PD"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>; + + mipi_pd: power-domain@10 { + domain-id = <10>; + #power-domain-cells = <0>; + domain-name = "MIPI_PD"; + }; + }; + }; + + csi1_bridge: csi1_bridge@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x0 0x32e20000 0x0 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&dispmix_pd>; + status = "disabled"; + }; + + mipi_csi_1: mipi_csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi"; + reg = <0x0 0x32e30000 0x0 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_CSI1_CORE_DIV>, + <&clk IMX8MM_CLK_CSI1_PHY_REF_DIV>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + bus-width = <4>; + power-domains = <&mipi_pd>; + status = "disabled"; + }; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30200000 0x0 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30210000 0x0 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30220000 0x0 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30230000 0x0 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30240000 0x0 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@0x30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x0 0x30260000 0x0 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x0 0x30340000 0x0 0x10000>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; + reg = <0x0 0x30360000 0x0 0x10000>; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x0 0x30370000 0x0 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x0 0x30380000 0x0 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + src: src@30390000 { + compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; + reg = <0x0 0x30390000 0x0 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc", "syscon"; + reg = <0x0 0x303a0000 0x0 0x10000>; + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */ + <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */ + <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */ + clock-frequency = <8000000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30860000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART1_ROOT>, + <&clk IMX8MM_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30880000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART3_ROOT>, + <&clk IMX8MM_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mm-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30890000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART2_ROOT>, + <&clk IMX8MM_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a20000 0x0 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a30000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a40000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; + reg = <0x0 0x30a50000 0x0 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30a60000 0x0 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART4_ROOT>, + <&clk IMX8MM_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x0 0x30aa0000 0x0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + clock-names = "mu"; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qm-rpmsg"; + status = "disabled"; + }; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon"; + reg = <0 0x30350000 0 0x10000>; + clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + }; + + dispmix_gpr: display-gpr@32e28000 { + compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; + reg = <0x0 0x32e28000 0x0 0x100>; + }; + + usbotg1: usb@32e40000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x32e40000 0x0 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>, + <&clk IMX8MM_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&usb_otg1_pd>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc1: usbmisc@32e40200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x32e40200 0x0 0x200>; + }; + + usbotg2: usb@32e50000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x32e50000 0x0 0x200>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>, + <&clk IMX8MM_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&usb_otg2_pd>; + status = "disabled"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + usbmisc2: usbmisc@32e50200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x32e50200 0x0 0x200>; + }; + + usdhc1: mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b40000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MM_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1_DIV>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@30b50000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b50000 0x0 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MM_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b60000 0x0 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MM_CLK_USDHC3_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30010000 0x0 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0xff 0xff>; + status = "disabled"; + }; + + sai2: sai@30020000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30020000 0x0 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI2_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30060000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI6_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>; + clock-names = "ipg_clk", "ipg_clk_app"; + dmas = <&sdma2 24 26 0x80000000>; + dma-names = "rx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx8mm-spdif"; + reg = <0x0 0x30090000 0x0 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1_DIV>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x30bd0000 0x0 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, + <&clk IMX8MM_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "okay"; + }; + + sdma2: dma-controller@302c0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302c0000 0x0 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, + <&clk IMX8MM_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + sdma3: dma-controller@302b0000 { + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302b0000 0x0 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, + <&clk IMX8MM_CLK_SDMA3_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30280000 0 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30290000 0 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x302a0000 0 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + + flexspi: flexspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-flexspi"; + reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi"; + status = "disabled"; + }; + + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30820000 0x0 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, + <&clk IMX8MM_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30830000 0x0 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, + <&clk IMX8MM_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30840000 0x0 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, + <&clk IMX8MM_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x0 0x30be0000 0x0 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER_DIV>, + <&clk IMX8MM_CLK_ENET_REF_DIV>, + <&clk IMX8MM_CLK_ENET_PHY_REF_DIV>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI_SRC>, + <&clk IMX8MM_CLK_ENET_TIMER_SRC>, + <&clk IMX8MM_CLK_ENET_REF_SRC>, + <&clk IMX8MM_CLK_ENET_TIMER_DIV>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + lcdif: lcdif@32E00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-lcdif"; + reg = <0x0 0x32e00000 0x0 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_DIV>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_SRC>, + <&clk IMX8MM_CLK_DISP_AXI_SRC>, + <&clk IMX8MM_CLK_DISP_APB_SRC>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + lcdif-gpr = <&dispmix_gpr>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32E10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x0 0x32e10000 0x0 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>, + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>, + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + dsi-gpr = <&dispmix_gpr>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + + pcie0: pcie@0x33800000 { + compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x32f00000 0x0 0x10000>, + <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "phy", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX_CG>, + <&clk IMX8MM_CLK_PCIE1_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <0>; + power-domains = <&pcie0_pd>; + status = "disabled"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30660000 0x0 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, + <&clk IMX8MM_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30670000 0x0 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, + <&clk IMX8MM_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30680000 0x0 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, + <&clk IMX8MM_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30690000 0x0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, + <&clk IMX8MM_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + vpu_h1: vpu_h1@38320000 { + compatible = "nxp,imx8mm-hantro-h1"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_h1"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1_SRC>,<&clk IMX8MM_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; + + gpu: gpu@38000000 { + compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, + <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB_DIV>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu3d_ahb_clk", + "gpu2d_clk", "gpu2d_axi_clk", + "gpu2d_ahb_clk"; + + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_CLK_GPU_AHB_DIV>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>, <400000000>; + + power-domains = <&gpumix_pd>; + + status = "disabled"; + }; + + crypto: caam@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0 0x30900000 0 0x40000>; + ranges = <0 0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x00100000 0 0x7fff>; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0 0x30370000 0 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1800000 1000000 + 1600000 900000 + 1200000 800000 + >; + clocks = <&clk IMX8MM_CLK_A53_DIV>, <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_ARM_PLL>, <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>; + clock-names = "a53", "arm_a53_src", "arm_pll", + "arm_pll_out", "sys1_pll_800m"; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts new file mode 100644 index 000000000000..4516c56e2dcf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts @@ -0,0 +1,369 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR3L ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_50M>; + assigned-clock-rates = <0>, <0>, <50000000>, <100000000>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "disabled"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts new file mode 100644 index 000000000000..bc6c8b7c2ce1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2-gpmi-nand.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2017 NXP + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-ddr4-arm2.dts" + +&iomuxc { + imx8mq-arm2 { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts new file mode 100644 index 000000000000..cf93e3bebc97 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts @@ -0,0 +1,363 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ DDR4 ARM2"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + busfreq { + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-arm2 { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts new file mode 100644 index 000000000000..d5b28bce186c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + sound-ak4458 { + status = "disabled"; + }; + + sound-ak4497 { + status = "okay"; + }; +}; + +&iomuxc { + + imx8mq-evk { + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd: sai1grp_dsd { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_dsd512: sai1grp_dsd512 { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + }; +}; + +&sai1 { + pinctrl-names = "default", "dsd", "dsd512"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_dsd>; + pinctrl-2 = <&pinctrl_sai1_dsd512>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>, + <&clk IMX8MQ_CLK_SAI1_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>; + assigned-clock-rates = <0>, <45158400>; + fsl,sai-multi-lane; + fsl,dataline,dsd = <0xff 0x11>; + dmas = <&sdma2 8 26 0>, <&sdma2 9 26 0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts new file mode 100644 index 000000000000..752114f6a064 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-audio-tdm.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + sound-ak4458 { + fsl,tdm; + }; + + sound-ak5558 { + fsl,tdm; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts new file mode 100644 index 000000000000..9ad6754790e6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/delete-node/ &ov5640_mipi; +/delete-node/ &ov5640_mipi2; + +&i2c1 { + ov5640_mipi: ov5640_mipi@1c { + compatible = "ovti,ov5640_mipi"; + reg = <0x1c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + + ov5640_mipi2: ov5640_mipi2@2c { + compatible = "ovti,ov5640_mipi"; + reg = <0x2c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; +}; + +&i2c2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts new file mode 100644 index 000000000000..afe92680724d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "okay"; + disp-dev = "mipi_disp"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; + clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, + <&clk IMX8MQ_CLK_DISP_AXI_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <594000000>, + <800000000>, + <400000000>, + <400000000>; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_mipi_dsi: mipi_dsi { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&i2c1 { + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_disp0_mipi_dsi>; + }; + }; + +}; + +&mipi_dsi_bridge { + status = "okay"; + + port@1 { + mipi_dsi_bridge_adv: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts new file mode 100644 index 000000000000..c64fdd39bb26 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts @@ -0,0 +1,138 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&hdmi { + status = "disabled"; +}; + +&dcss { + status = "okay"; + disp-dev = "mipi_disp"; + + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; + clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc"; + + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, + <&clk IMX8MQ_CLK_DISP_AXI_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rates = <600000000>, + <800000000>, + <400000000>, + <0>, + <400000000>, + <599999999>; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_mipi_dsi: mipi_dsi { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>, + <&clk IMX8MQ_CLK_DSI_CORE_SRC>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rates = <24000000>, + <266000000>, + <0>, + <599999999>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_disp0_mipi_dsi>; + }; + }; + +}; + +&mipi_dsi_bridge { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_out>; + }; + }; + }; + + port@1 { + mipi_dsi_bridge_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; + + pinctrl_i2c1_synaptics_dsx_io: synaptics_dsx_iogrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 + >; + }; + + }; +}; + +&i2c1 { + synaptics_dsx_ts@20 { + compatible = "synaptics_dsx"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_synaptics_dsx_io>; + interrupt-parent = <&gpio5>; + interrupts = <7 8>; + synaptics,diagonal-rotation; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts new file mode 100644 index 000000000000..057c0e645ce7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dp.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&hdmi { + compatible = "fsl,imx8mq-dp"; + lane_mapping = <0xc6>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts new file mode 100644 index 000000000000..a695afbf9469 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-drm.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&resmem { + display_region: imx_ion@1 { + compatible = "imx-ion-pool"; + reg = <0x0 0xe6000000 0 0x18000000>; + }; + + vpu_region: imx_ion@2 { + compatible = "imx-ion-pool"; + reg = <0x0 0xe4000000 0 0x02000000>; + }; +}; + +&imx_ion { + compatible = "fsl,mxc-ion", "linux,ion"; + + ion-display-region { + compatible = "fsl,display-heap", "linux,ion-heap-unmapped"; + memory-region = <&display_region>; + }; + + ion-vpu-region { + compatible = "fsl,vpu-heap", "linux,ion-heap-unmapped"; + memory-region = <&vpu_region>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts new file mode 100644 index 000000000000..2c512696c39d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dual-display.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&lcdif { + status = "okay"; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&i2c1 { + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + as_bridge; + sync-pol = <1>; + pwr-delay = <10>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; +}; + +&mipi_dsi_bridge { + status = "okay"; + + port@1 { + mipi_dsi_bridge_adv: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts new file mode 100644 index 000000000000..5f8ea76166bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-edp.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&hdmi { + compatible = "fsl,imx8mq-dp"; + lane_mapping = <0xc6>; + fsl,edp; + edp_link_rate = <0x6>; + edp_num_lanes = <0x4>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts new file mode 100644 index 000000000000..135a90498fa7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-inmate.dts @@ -0,0 +1,207 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + interrupt-parent = <&gic>; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clocks { + clk_dummy: clock@7 { + compatible = "fixed-clock"; + reg = <7>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + reg = <8>; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "400m"; + }; + clk_266m: clock@9 { + compatible = "fixed-clock"; + reg = <9>; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + clk_80m: clock@10 { + compatible = "fixed-clock"; + reg = <10>; + #clock-cells = <0>; + clock-frequency = <80000000>; + clock-output-names = "80m"; + }; + }; + + display-subsystem { + /delete-property/ compatible; + }; + + pci@bfb00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xbfb00000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; +}; + +/delete-node/ &{/memory@40000000}; + +&clk { + /delete-property/ compatible; +}; + +/delete-node/ &{/cpus/cpu@0}; +/delete-node/ &{/cpus/cpu@1}; +/delete-node/ &{/pmu}; + +/delete-node/ &{/busfreq}; + +/delete-node/ &resmem; + +&mipi_pd { + status = "disabled"; +}; + +&pcie0_pd { + status = "disabled"; +}; + +&usb_otg1_pd { + status = "disabled"; +}; + +&usb_otg2_pd { + status = "disabled"; +}; + +&gpu_pd { + status = "disabled"; +}; + +&vpu_pd { + status = "disabled"; +}; + +&mipi_csi1_pd { + status = "disabled"; +}; + +&mipi_csi2_pd { + status = "disabled"; +}; + +&pcie1_pd { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; +&gpio2 { + status = "disabled"; +}; +&gpio3 { + status = "disabled"; +}; +&gpio4 { + status = "disabled"; +}; +&gpio5 { + status = "disabled"; +}; + +/delete-node/ &tmu; +/delete-node/ &{/thermal-zones}; + +/delete-node/ &irqsteer_dcss; +/delete-node/ &ocotp; +/delete-node/ &snvs; + +&src { + /delete-property/ compatible; +}; + +&dcss { + /delete-property/ interrupt-parent; +}; + +/delete-node/ &gpc; +/delete-node/ &system_counter; +/delete-node/ &imx_ion; +/delete-node/ &pcie0; +/delete-node/ &pcie1; +/delete-node/ &vpu; +/delete-node/ &ddr_pmu0; +/delete-node/ &imx_rpmsg; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &caam_snvs; +/delete-node/ &irq_sec_vio; +/delete-node/ &dma_apbh; +/delete-node/ &gpmi; + +&gic { + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ +}; + + +/delete-node/ &iomuxc; + +&uart2 { + clocks = <&osc_25m>, + <&osc_25m>; + clock-names = "ipg", "per"; + /delete-property/ dmas; + /delete-property/ dmas-names; + status = "okay"; +}; + +&usdhc1 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + /delete-property/assigned-clocks; + /delete-property/assigned-clock-rates; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts new file mode 100644 index 000000000000..204d696e086c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts @@ -0,0 +1,87 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + display-subsystem { + status = "disabled"; + }; +}; + +&irqsteer_dcss { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&i2c1 { + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3b>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + as_bridge; + sync-pol = <1>; + pwr-delay = <10>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; +}; + +&mipi_dsi_bridge { + status = "okay"; + + port@1 { + mipi_dsi_bridge_adv: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts new file mode 100644 index 000000000000..174036de1f48 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts @@ -0,0 +1,114 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + display-subsystem { + status = "disabled"; + }; +}; + +&irqsteer_dcss { + status = "disabled"; +}; + +&dcss { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&lcdif { + status = "okay"; + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rate = <120000000>, + <0>, + <599999999>; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + as_bridge; + sync-pol = <1>; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>, + <&clk IMX8MQ_CLK_DSI_CORE_SRC>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rates = <24000000>, + <266000000>, + <0>, + <599999999>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; +}; + +&mipi_dsi_bridge { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_out>; + }; + }; + }; + + port@1 { + mipi_dsi_bridge_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts new file mode 100644 index 000000000000..e4c530e96069 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@0x80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + }; + + sound-wm8524 { + status = "disabled"; + }; +}; + +&gpt1 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&pwm4 { + status = "disabled"; +}; + +&tmu { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&wdog3{ + status = "disabled"; +}; + +&sai2 { + status = "disabled"; +}; + +&qspi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts new file mode 100644 index 000000000000..7e4a672708bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-mipi-csi2.dts @@ -0,0 +1,38 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +&ov5640_mipi { + status = "disabled"; +}; + +&ov5640_mipi2 { + status = "okay"; +}; + +&csi1_bridge { + status = "disabled"; +}; + +&csi2_bridge { + status = "okay"; +}; + +&mipi_csi_1 { + status = "disabled"; +}; +&mipi_csi_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts new file mode 100644 index 000000000000..6b0147673ec7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pcie1-m2.dts @@ -0,0 +1,82 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: + * 1. The DTS file only support i.MX8MQ EVK RevB1/B2 board PCIe M.2 Murata + * 1CQ (Qca6174) WIFI & BT. + * EVK RevB1 rework: + * WIFI rework: fly line from R1436 (near to M.2) to R1459 + * BT rework: ensure R1446,R1447,R1448,R1449 installed on board + * EVK RevB2 rework: no rework + * + * 2. If need to support i.MX8MQ EVK RevA0/A1 board PCIe M.2 Murata 1CQ + * (Qca6174) WIFI & BT, some board rework requirement: + * EVK RevA0 rework: + * WIFI rework: install R1436 for wlreg_on + * EVK RevA0 rework: + * WIFI rework: install R1436 for wlreg_on + * BT rework: fly line from M.2 pin54 to R1437 + * Also, below DTS change requirement: + * / { + * regulators { + * epdev_on: fixedregulator@100 { + * compatible = "regulator-fixed"; + * regulator-min-microvolt = <3300000>; + * regulator-max-microvolt = <3300000>; + * regulator-name = "epdev_on"; + * gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + * enable-active-high; + * }; + * }; + * }; + * + * &iomuxc { + * imx8mq-evk { + * pinctrl_epdev_on: epdevongrp { + * fsl,pins = < + * MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x16 + * >; + * }; + * }; + * }; + * + * &pcie1{ + * pinctrl-names = "default"; + * pinctrl-0 = <&pinctrl_pcie1 &pinctrl_epdev_on>; + * epdev_on-supply = <&epdev_on>; + * }; + * + * &usdhc2 { + * status = "disabled"; + * }; + * + * + * 3. When wifi driver switch to QCA CLD from ATH10K, there have two known issues: + * - QCA CLD driver only support ONE instance. + * - QCA CLD driver don't support PCIe MSI feature. + * So here it has to disable pcie0 port. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + modem_reset: modem-reset { + reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0{ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts new file mode 100644 index 000000000000..a2e84eea463b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + sound-pdm { + compatible = "fsl,imx-pdm-mic"; + model = "imx-pdm-audio"; + audio-cpu = <&sai3>; + decimation = <64>; + status = "okay"; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3_SRC>, + <&clk IMX8MQ_CLK_SAI3_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts new file mode 100644 index 000000000000..13ce6b7e1439 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts @@ -0,0 +1,109 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + interrupt-parent = <&gic>; +}; + +/delete-node/ &gpc; + +&CPU_SLEEP { + /* We are not using GPC for now, need set 0 to avoid hang */ + arm,psci-suspend-param = <0x0>; +}; + +&clk { + init-on-array = <IMX8MQ_CLK_DRAM_CORE IMX8MQ_CLK_AHB_CG + IMX8MQ_CLK_NOC_CG IMX8MQ_CLK_NOC_APB_CG + IMX8MQ_CLK_USB_BUS_CG + IMX8MQ_CLK_MAIN_AXI_CG IMX8MQ_CLK_A53_CG + IMX8MQ_CLK_AUDIO_AHB_DIV IMX8MQ_CLK_TMU_ROOT + IMX8MQ_CLK_DRAM_APB_DIV + IMX8MQ_CLK_NOC_CG IMX8MQ_CLK_NOC_APB_CG + IMX8MQ_CLK_NAND_USDHC_BUS_CG>; +}; + +&iomuxc { + imx8mq-evk { + /* + * Used for the 2nd Linux. + * TODO: M4 may use these pins. + */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + }; +}; + +&{/busfreq} { + /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */ + status = "disabled"; +}; + +&resmem { + jh_reserved: jh@0xffc00000 { + no-map; + reg = <0 0xffc00000 0x0 0x400000>; + }; + + inmate_reserved: inmate@0xc0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3fc00000>; + }; + + loader_reserved: loader@0xbff00000 { + no-map; + reg = <0 0xbff00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xbfe00000 { + no-map; + reg = <0 0xbfe00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@0xbfd00000 { + no-map; + reg = <0 0xbfd00000 0x0 0x00100000>; + }; + + pci_reserved: pci@0xbfc00000 { + no-map; + reg = <0 0xbfb00000 0x0 0x00200000>; + }; +}; + +&uart1 { + /* uart2 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>, + <&clk IMX8MQ_CLK_UART2_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_CLK_25M>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + /* sdhc1 is used by 2nd linux, configure the pin */ + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts new file mode 100644 index 000000000000..95d78a2dfbde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts @@ -0,0 +1,928 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + states = <900000 0x1 1000000 0x0>; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: wm8524 { + compatible = "wlf,wm8524"; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + clock-names = "mclk"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + sound-wm8524 { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&wm8524>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <1>; + hdmi-out; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif2>; + spdif-in; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-ak4458-mq"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4458_1>, <&ak4458_2>; + ak4458,pdn-gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + sound-ak5558 { + compatible = "fsl,imx-audio-ak5558-mq"; + model = "ak5558-audio"; + audio-cpu = <&sai5>; + audio-codec = <&ak5558>; + }; + + sound-ak4497 { + compatible = "fsl,imx-audio-ak4497-mq"; + model = "ak4497-audio"; + audio-cpu = <&sai1>; + audio-codec = <&ak4497>; + status = "disabled"; + }; +}; + +&clk { + assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; + assigned-clock-rates = <786432000>, <722534400>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8mq-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 + >; + }; + + pinctrl_csi1_pwn: csi1_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + >; + }; + pinctrl_csi2_pwn: csi2_pwn_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 /* open drain, pull up */ + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai1_pcm: sai1grp_pcm { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 + MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 + MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 + >; + }; + + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + typec_ptn5100: ptn5110@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <3 8>; + ss-sel-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8>; + snk-pdos = <0x380190c8 0x3802d0c8>; + max-snk-mv = <9000>; + max-snk-ma = <2000>; + op-snk-mw = <9000>; + max-snk-mw = <18000>; + port-type = "drp"; + default-role = "sink"; + }; + + ov5640_mipi2: ov5640_mipi2@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ak4458_1: ak4458@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + }; + + ak4458_2: ak4458@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + }; + + ak5558: ak5558@13 { + compatible = "asahi-kasei,ak5558"; + reg = <0x13>; + ak5558,pdn-gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + + ak4497: ak4497@11 { + compatible = "asahi-kasei,ak4497"; + reg = <0x11>; + ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + hard-wired = <1>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + extcon = <&typec_ptn5100>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&sai1 { + pinctrl-names = "default", "pcm_b2m"; + pinctrl-0 = <&pinctrl_sai1_pcm>; + pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>, + <&clk IMX8MQ_CLK_SAI1_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, + <&clk IMX8MQ_CLK_SAI2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>, + <&clk IMX8MQ_CLK_SAI4_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI5_SRC>, + <&clk IMX8MQ_CLK_SAI5_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <49152000>; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1_SRC>, + <&clk IMX8MQ_CLK_SPDIF1_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&spdif2 { + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2_SRC>, + <&clk IMX8MQ_CLK_SPDIF2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&gpu_pd { + power-supply = <&sw1a_reg>; +}; + +&vpu_pd { + power-supply = <&sw1c_reg>; +}; + +&gpu { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&mu { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0xb8000000 0x0 0x10000>; + status = "okay"; +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1500000 1000000 + 1300000 1000000 + 1000000 900000 + 800000 900000 + >; + dc-supply = <®_gpio_dvfs>; +}; + +&dcss { + status = "okay"; + + disp-dev = "hdmi_disp"; +}; + +&hdmi { + status = "okay"; +}; + +&csi1_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +&csi2_bridge { + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + status = "okay"; + + port { + csi2_ep: endpoint { + remote-endpoint = <&csi2_mipi_ep>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi1_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi1_ep>; + data-lanes = <1 2>; + }; + + csi1_mipi_ep: endpoint2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_csi_2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port { + mipi2_sensor_ep: endpoint1 { + remote-endpoint = <&ov5640_mipi2_ep>; + data-lanes = <1 2>; + }; + + csi2_mipi_ep: endpoint2 { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi new file mode 100755 index 000000000000..5dd2ea12a1db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi @@ -0,0 +1,1469 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8-ca53.dtsi" +#include <dt-bindings/clock/imx8mq-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pins-imx8mq.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "fsl,imx8mq"; + interrupt-parent = <&gpc>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi0 = &mipi_csi_1; + csi1 = &mipi_csi_2; + ethernet0 = &fec1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + dsi_phy0 = &mipi_dsi_phy; + mipi_dsi0 = &mipi_dsi; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x00000000 0x40000000 0 0xc0000000>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x40000000 0 0x40000000>; + linux,cma-default; + }; + + rpmsg_reserved: rpmsg@0xb8000000 { + no-map; + reg = <0 0xb8000000 0 0x400000>; + }; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>, /* GICR (RD_base + SGI_base) */ + <0x0 0x30340000 0x0 0x10000>; /* IOMUXC_GPR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + interrupt-parent = <&gic>; + arm,no-tick-in-suspend; + }; + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MQ_DRAM_PLL1>, <&clk IMX8MQ_CLK_DRAM_ALT_SRC>, + <&clk IMX8MQ_CLK_DRAM_APB_SRC>, <&clk IMX8MQ_CLK_DRAM_APB_PRE_DIV>, + <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>, + <&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_NOC_DIV>, <&clk IMX8MQ_CLK_MAIN_AXI_SRC>, + <&clk IMX8MQ_CLK_AHB_DIV>, <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m", + "sys1_pll_100m", "sys1_pll_800m", "noc_div", "main_axi_src", + "ahb_div", "osc_25m", "sys2_pll_333m", "sys1_pll_133m"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc_25m: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_25m"; + }; + + osc_27m: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "osc_27m"; + }; + + clk_ext1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock@4 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock@5 { + compatible = "fixed-clock"; + reg = <5>; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock@6 { + compatible = "fixed-clock"; + reg = <6>; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + }; + + mipi_pd: gpc_power_domain@0 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <0>; + domain-name = "MIPI_PD"; + }; + + pcie0_pd: gpc_power_domain@1 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <1>; + domain-name = "PCIE0_PD"; + }; + + usb_otg1_pd: gpc_power_domain@2 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <2>; + domain-name = "USB_OTG1_PD"; + }; + + usb_otg2_pd: gpc_power_domain@3 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <3>; + domain-name = "USB_OTG2_PD"; + }; + + gpu_pd: gpc_power_domain@4 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <4>; + domain-name = "GPU_PD"; + clocks = <&clk IMX8MQ_CLK_GPU_AXI_DIV>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, + <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_AHB_DIV>; + }; + + vpu_pd: gpc_power_domain@5 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <5>; + domain-name = "VPU_PD"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + }; + + mipi_csi1_pd: gpc_power_domain@8 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <8>; + domain-name = "MIPI_CSI1_PD"; + }; + + mipi_csi2_pd: gpc_power_domain@9 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <9>; + domain-name = "MIPI_CSI2_PD"; + }; + + pcie1_pd: gpc_power_domain@10 { + compatible = "fsl,imx8mq-pm-domain"; + #power-domain-cells = <0>; + domain-id = <10>; + domain-name = "PCIE1_PD"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30660000 0x0 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, + <&clk IMX8MQ_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30670000 0x0 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, + <&clk IMX8MQ_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30680000 0x0 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, + <&clk IMX8MQ_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x30690000 0x0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, + <&clk IMX8MQ_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@30200000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30200000 0x0 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30210000 0x0 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30220000 0x0 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30230000 0x0 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x30240000 0x0 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mq-tmu"; + reg = <0x0 0x30260000 0x0 0x10000>; + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; + fsl,tmu-calibration = <0x00000000 0x00000023 + 0x00000001 0x00000029 + 0x00000002 0x0000002f + 0x00000003 0x00000035 + 0x00000004 0x0000003d + 0x00000005 0x00000043 + 0x00000006 0x0000004b + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005f + 0x0000000a 0x00000067 + 0x0000000b 0x0000006f + + 0x00010000 0x0000001b + 0x00010001 0x00000023 + 0x00010002 0x0000002b + 0x00010003 0x00000033 + 0x00010004 0x0000003b + 0x00010005 0x00000043 + 0x00010006 0x0000004b + 0x00010007 0x00000055 + 0x00010008 0x0000005d + 0x00010009 0x00000067 + 0x0001000a 0x00000070 + + 0x00020000 0x00000017 + 0x00020001 0x00000023 + 0x00020002 0x0000002d + 0x00020003 0x00000037 + 0x00020004 0x00000041 + 0x00020005 0x0000004b + 0x00020006 0x00000057 + 0x00020007 0x00000063 + 0x00020008 0x0000006f + + 0x00030000 0x00000015 + 0x00030001 0x00000021 + 0x00030002 0x0000002d + 0x00030003 0x00000039 + 0x00030004 0x00000045 + 0x00030005 0x00000053 + 0x00030006 0x0000005f + 0x00030007 0x00000071>; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + gpt1: gpt@302d0000 { + compatible = "fsl,imx8mq-gpt", "fsl,imx7d-gpt"; + reg = <0x0 0x302d0000 0x0 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_GPT1_ROOT>, + <&clk IMX8MQ_CLK_GPT1_ROOT>, + <&clk IMX8MQ_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; + status = "disabled"; + }; + + irqsteer_dcss: irqsteer@32e2d000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x32e2d000 0x0 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + nxp,irqsteer_chans = <2>; + nxp,endian = <1>; /* MSB */ + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ipg"; + }; + + csi1_bridge: csi1_bridge@30a90000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x0 0x30a90000 0x0 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + csi2_bridge: csi2_bridge@30b80000 { + compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x0 0x30b80000 0x0 0x10000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI2_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi_1: mipi_csi1@30a70000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */ + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI1_CORE_DIV>, + <&clk IMX8MQ_CLK_CSI1_ESC_DIV>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE_DIV>, + <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>, + <&clk IMX8MQ_CLK_CSI1_ESC_DIV>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&mipi_csi1_pd>; + csis-phy-reset = <&src 0x4c 7>; + phy-gpr = <&gpr 0x88>; + status = "disabled"; + }; + + mipi_csi_2: mipi_csi2@30b60000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x0 0x30b60000 0x0 0x1000>; /* MIPI CSI2 Controller base addr */ + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_CSI2_CORE_DIV>, + <&clk IMX8MQ_CLK_CSI2_ESC_DIV>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF_DIV>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE_DIV>, + <&clk IMX8MQ_CLK_CSI2_PHY_REF_DIV>, + <&clk IMX8MQ_CLK_CSI2_ESC_DIV>; + assigned-clock-rates = <133000000>, <100000000>, <66000000>; + power-domains = <&mipi_csi2_pd>; + csis-phy-reset = <&src 0x50 7>; + phy-gpr = <&gpr 0xa4>; + status = "disabled"; + }; + + lcdif: lcdif@30320000 { + compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x30320000 0x0 0x10000>; + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>; + clock-names = "pix"; + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rate = <594000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + max-res = <1280>, <720>; + status = "disabled"; + }; + + dcss: dcss@0x32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x0 0x32e00000 0x0 0x30000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>, + <5 IRQ_TYPE_LEVEL_HIGH>, + <6 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_EDGE_RISING>, + <9 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dpr_dc_ch0", + "dpr_dc_ch1", + "dpr_dc_ch2", + "ctx_ld", + "dtg_prg1", + "ctxld_kick", + "dtrc_ch1", + "dtrc_ch2"; + interrupt-parent = <&irqsteer_dcss>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL2_DIV>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; + clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, + <&clk IMX8MQ_CLK_DISP_AXI_SRC>, + <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_VIDEO2_PLL1>, + <&clk IMX8MQ_VIDEO2_PLL1_OUT_DIV>, + <&clk IMX8MQ_VIDEO2_PLL2>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + assigned-clock-rates = <594000000>, + <800000000>, + <400000000>, + <27000000>, + <400000000>, + <297000000>, + <1728000000>, + <54000000>, + <2376000000>; + + status = "disabled"; + + dcss_disp0: port@0 { + reg = <0>; + + dcss_disp0_hdmi: hdmi-endpoint { + remote-endpoint = <&hdmi_disp>; + }; + }; + }; + + hdmi: hdmi@32c00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-hdmi"; + reg = <0x0 0x32c00000 0x0 0x100000>, /* HDP registers */ + <0x0 0x32e40000 0x0 0x40000>, /* HDP SEC register */ + <0x0 0x32e2f000 0x0 0x10>; /* RESET register */ + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + fsl,cec; + status = "disabled"; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dcss_disp0_hdmi>; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dcss_disp0>; + }; + + mipi_dsi_phy: dsi_phy@30A00300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8mq-mipi-dsi-phy"; + reg = <0x0 0x30A00300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge: mipi_dsi_bridge@30A00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x30A00000 0x0 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>, + <&clk IMX8MQ_CLK_DSI_AHB_DIV>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + clock-names = "phy_ref", "rx_esc", "tx_esc"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <80000000>; + phys = <&mipi_dsi_phy>; + phy-names = "dphy"; + no_clk_reset; + status = "disabled"; + + port@0 { + mipi_dsi_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + mipi_dsi: mipi_dsi@30A00000 { + compatible = "fsl,imx8mq-mipi-dsi_drm"; + clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>; + clock-names = "core", "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>, + <&clk IMX8MQ_CLK_DSI_CORE_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>; + assigned-clock-rates = <594000000>, <266000000>; + power-domains = <&mipi_pd>; + src = <&src>; + mux-sel = <&gpr>; + phys = <&mipi_dsi_phy>; + phy-names = "dphy"; + no_clk_reset; + status = "disabled"; + + port@0 { + mipi_dsi_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge_in>; + }; + }; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x0 0x30340000 0x0 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon"; + reg = <0 0x30350000 0 0x10000>; + clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; + /* For nvmem subnodes */ + #address-cells = <1>; + #size-cells = <1>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x0 0x30360000 0x0 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x0 0x30370000 0x0 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: ccm@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x0 0x30380000 0x0 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + src: src@30390000 { + compatible = "fsl,imx8mq-src", "fsl,imx51-src", "syscon"; + reg = <0x0 0x30390000 0x0 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon"; + reg = <0x0 0x303a0000 0x0 0x10000>; + interrupt-controller; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + system_counter: system-counter@3036a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */ + <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */ + <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */ + clock-frequency = <8333333>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + spdif1: spdif@30810000 { + compatible = "fsl,imx8mq-spdif", "fsl,imx35-spdif"; + reg = <0x0 0x30810000 0x0 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF1_DIV>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi1: ecspi@30820000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30820000 0x0 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, + <&clk IMX8MQ_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30820000 0x0 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, + <&clk IMX8MQ_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30830000 0x0 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, + <&clk IMX8MQ_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30840000 0x0 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, + <&clk IMX8MQ_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30860000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, + <&clk IMX8MQ_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30880000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, + <&clk IMX8MQ_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30890000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, + <&clk IMX8MQ_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdif2: spdif@308a0000 { + compatible = "fsl,imx8mq-spdif", "fsl,imx35-spdif"; + reg = <0x0 0x308a0000 0x0 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF2_DIV>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30a60000 0x0 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, + <&clk IMX8MQ_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + mu: mu@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x0 0x30aa0000 0x0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_MU_ROOT>; + clock-names = "mu"; + status = "disabled"; + }; + + usb3_phy0: phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + #phy-cells = <1>; + reg = <0x0 0x381f0040 0x0 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "usb_phy_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + usb3_0: usb@38100000 { + compatible = "fsl, imx8mq-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, + <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + status = "disabled"; + + usb_dwc3_0: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x38100000 0x0 0x10000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0 0>, <&usb3_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&usb_otg1_pd>; + snps,power-down-scale = <2>; + usb3-resume-missing-cas; + usb3-lpm-capable; + status = "disabled"; + }; + }; + + usb3_phy1: phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + #phy-cells = <1>; + reg = <0x0 0x382f0040 0x0 0x40>; + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; + clock-names = "usb_phy_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + usb3_1: usb@38200000 { + compatible = "fsl, imx8mq-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>, + <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + status = "disabled"; + + usb_dwc3_1: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x38200000 0x0 0x10000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy1 0>, <&usb3_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&usb_otg2_pd>; + snps,power-down-scale = <2>; + usb3-resume-missing-cas; + usb3-lpm-capable; + status = "disabled"; + }; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b40000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_USDHC1_ROOT>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>; + assigned-clock-rates = <400000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + fsl,strobe-dll-delay-target = <5>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + reg = <0x0 0x30b50000 0x0 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_USDHC2_ROOT>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + bus-width = <4>; + status = "disabled"; + }; + + sai1: sai@30010000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30010000 0x0 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI1_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0xff 0xff>; + status = "disabled"; + }; + + sai6: sai@30030000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI6_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + sai5: sai@30040000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30040000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI5_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0xf 0xf>; + status = "disabled"; + }; + + sai4: sai@30050000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI4_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; + dma-names = "rx", "tx"; + fsl,dataline = <0x0 0xf>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x308b0000 0x0 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI2_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@308c0000 { + compatible = "fsl,imx8mq-sai", + "fsl,imx6sx-sai"; + reg = <0x0 0x308c0000 0x0 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, + <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sdma1: sdma@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x30bd0000 0x0 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, + <&clk IMX8MQ_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "okay"; + }; + + sdma2: sdma@302c0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x0 0x302c0000 0x0 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, + <&clk IMX8MQ_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "okay"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x0 0x30be0000 0x0 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, + <&clk IMX8MQ_CLK_ENET1_ROOT>, + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, + <&clk IMX8MQ_CLK_ENET_REF_DIV>, + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>, + <&clk IMX8MQ_CLK_ENET_TIMER_SRC>, + <&clk IMX8MQ_CLK_ENET_REF_SRC>, + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_125M>; + assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + gpu: gpu@38000000 { + compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0 0x40000>, <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI_DIV>, <&clk IMX8MQ_CLK_GPU_AHB_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI_SRC>, <&clk IMX8MQ_CLK_GPU_AHB_SRC>; + assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>; + assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; + power-domains = <&gpu_pd>; + depth-compression = <0>; + status = "disabled"; + }; + + imx_ion: imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a20000 0x0 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a30000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a40000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx21-i2c"; + reg = <0x0 0x30a50000 0x0 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; + status = "disabled"; + }; + + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x0 0x38300000 0x0 0x200000>; + reg-names = "regs_hantro"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1_SRC>, <&clk IMX8MQ_CLK_VPU_G2_SRC>, <&clk IMX8MQ_CLK_VPU_BUS_SRC>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&vpu_pd>; + regulator-supply = <&sw1c_reg>; + status = "disabled"; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30280000 0 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x30290000 0 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx21-wdt"; + reg = <0 0x302a0000 0 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + qspi: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, + <&clk IMX8MQ_CLK_QSPI_ROOT>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + pcie0: pcie@0x33800000 { + compatible = "fsl,imx8mq-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX_CG>, + <&clk IMX8MQ_CLK_PCIE1_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <0>; + power-domains = <&pcie0_pd>; + status = "disabled"; + }; + + pcie1: pcie@0x33c00000 { + compatible = "fsl,imx8mq-pcie", "snps,dw-pcie"; + reg = <0x0 0x33c00000 0x0 0x400000>, <0x0 0x27f00000 0x0 0x80000>; + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x20000000 0x0 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX_CG>, + <&clk IMX8MQ_CLK_PCIE2_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <1>; + power-domains = <&pcie1_pd>; + status = "disabled"; + }; + + ddr_pmu0: ddr_pmu@3d800000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x3d800000 0x0 0x400000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qm-rpmsg"; + status = "disabled"; + }; + }; + + crypto: caam@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0 0x30900000 0 0x40000>; + ranges = <0 0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x00100000 0 0x7fff>; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0 0x30370000 0 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0 0x33000000 0 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1000000 900000 + 800000 900000 + >; + clocks = <&clk IMX8MQ_CLK_A53_DIV>, <&clk IMX8MQ_CLK_A53_SRC>, + <&clk IMX8MQ_ARM_PLL>, <&clk IMX8MQ_ARM_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>; + clock-names = "a53", "arm_a53_src", "arm_pll", + "arm_pll_out", "sys1_pll_800m"; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi new file mode 100644 index 000000000000..00f0bbd25ef8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi @@ -0,0 +1,1327 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <3000>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_b 3 0>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai6>, <&sai7>; + amix-controller = <&amix>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&lvds0_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&lvds1_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + imx8qm-arm2 { + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x04000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x04000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; + status = "okay"; +}; + +&gpio0_mipi_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; + status = "okay"; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + power-domains = <&pd_mclk_out0>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + pinctrl-assert-gpios = <&pca9557_d 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&lvds0_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_pwm0>; + status = "okay"; +}; + +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_pwm0>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_adv: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&i2c0_mipi_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_adv: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&i2c0_mipi_dsi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_adv>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts new file mode 100644 index 000000000000..d0744e521e83 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts @@ -0,0 +1,991 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM ARM2"; + compatible = "fsl,imx8qm-arm2", "fsl,imx8qm"; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_b 3 0>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai6>, <&sai7>; + amix-controller = <&amix>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&lvds0_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&lvds1_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + imx8qm-arm2 { + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc600004c + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc600004c + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc600004c + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc600004c + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc600004c + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc600004c + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc600004c + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc600004c + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc600004c + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc600004c + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x00000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + power-domains = <&pd_mclk_out0>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "disabled"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + pinctrl-assert-gpios = <&pca9557_d 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + * --0xb8000000~0xb800ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + * --0xb8100000~0xb810ffff: pingpong + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&lvds0_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_pwm0>; + status = "okay"; +}; + +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_pwm0>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi new file mode 100644 index 000000000000..a2e78e094c9d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -0,0 +1,4293 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + imx8qm-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_DC_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = <SC_R_DC_0_PLL_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = <SC_R_DC_0_PLL_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + + pd_mipi0: PD_MIPI_0_DSI { + reg = <SC_R_MIPI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = <SC_R_MIPI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = <SC_R_MIPI_0_I2C_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 { + reg = <SC_R_MIPI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + }; + + pd_lvds0: PD_LVDS0 { + reg = <SC_R_LVDS_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lvds0_i2c0: PD_LVDS0_I2C0 { + reg = <SC_R_LVDS_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_lvds0>; + }; + + pd_lvds0_pwm: PD_LVDS0_PWM { + reg = <SC_R_LVDS_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_lvds0>; + }; + }; + + pd_hdmi: PD_HDMI { + reg = <SC_R_HDMI>; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_pll0: PD_HDMI_PLL_0{ + reg = <SC_R_HDMI_PLL_0>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_pll1: PD_HDMI_PLL_1{ + reg = <SC_R_HDMI_PLL_1>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_i2c0: PD_HDMI_I2C_0 { + reg = <SC_R_HDMI_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll1>; + }; + + pd_hdmi_i2s: PD_HDMI_I2S { + reg = <SC_R_HDMI_I2S>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll1>; + }; + }; + }; + + }; + + }; + + pd_dc1: PD_DC_1 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_DC_1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll0: PD_DC_1_PLL_0{ + reg = <SC_R_DC_1_PLL_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll1: PD_DC_1_PLL_1{ + reg = <SC_R_DC_1_PLL_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc1_pll0>; + }; + }; + + pd_mipi1: PD_MIPI_1_DSI { + reg = <SC_R_MIPI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = <SC_R_MIPI_1_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = <SC_R_MIPI_1_I2C_1>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_pwm: PD_MIPI_1_DSI_PWM { + reg = <SC_R_MIPI_1_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + }; + + pd_lvds1: PD_LVDS1 { + reg = <SC_R_LVDS_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lvds1_i2c0: PD_LVDS1_I2C0 { + reg = <SC_R_LVDS_1_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_lvds1>; + }; + + pd_lvds1_pwm: PD_LVDS1_PWM { + reg = <SC_R_LVDS_1_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_lvds1>; + }; + }; + }; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = <SC_R_PWM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = <SC_R_PWM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = <SC_R_PWM_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = <SC_R_PWM_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = <SC_R_PWM_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = <SC_R_PWM_5>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = <SC_R_PWM_6>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = <SC_R_PWM_7>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = <SC_R_KPP>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = <SC_R_GPIO_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = <SC_R_GPIO_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = <SC_R_GPIO_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = <SC_R_GPIO_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = <SC_R_GPIO_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = <SC_R_GPIO_5>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = <SC_R_GPIO_6>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = <SC_R_GPIO_7>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = <SC_R_GPT_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = <SC_R_GPT_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = <SC_R_GPT_2>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = <SC_R_GPT_3>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = <SC_R_GPT_4>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = <SC_R_FSPI_0>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = <SC_R_FSPI_1>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu5a: PD_LSIO_MU5A { + reg = <SC_R_MU_5A>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu6a: PD_LSIO_MU6A { + reg = <SC_R_MU_6A>; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = <SC_R_USB_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <267>; + }; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = <SC_R_USB_0_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <267>; + }; + + pd_conn_usbh1: PD_CONN_USB_1 { + reg = <SC_R_USB_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <268>; + }; + + pd_conn_usb2: PD_CONN_USB_2 { + reg = <SC_R_USB_2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <271>; + + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = <SC_R_USB_2_PHY>; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usb2>; + wakeup-irq = <271>; + }; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = <SC_R_SDHC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = <SC_R_SDHC_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = <SC_R_SDHC_2>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = <SC_R_ENET_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <258>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = <SC_R_ENET_1>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + fsl,wakeup_irq = <262>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = <SC_R_NAND>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = <SC_R_MLB_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = <SC_R_DMA_4_CH0>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = <SC_R_DMA_4_CH1>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = <SC_R_DMA_4_CH2>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = <SC_R_DMA_4_CH3>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = <SC_R_DMA_4_CH4>; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_hsio: PD_HSIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hsio_gpio: PD_HSIO_GPIO { + reg = <SC_R_HSIO_GPIO>; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes0: PD_HSIO_SERDES_0 { + reg = <SC_R_SERDES_0>; + #power-domain-cells = <0>; + power-domains =<&pd_hsio_gpio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie0: PD_HSIO_PCIE_A { + reg = <SC_R_PCIE_A>; + #power-domain-cells = <0>; + power-domains =<&pd_serdes0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie1: PD_HSIO_PCIE_B { + reg = <SC_R_PCIE_B>; + #power-domain-cells = <0>; + power-domains =<&pd_pcie0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = <SC_R_SERDES_1>; + #power-domain-cells = <0>; + power-domains =<&pd_pcie1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sata0: PD_HSIO_SATA_0 { + reg = <SC_R_SATA_0>; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + }; + }; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = <SC_R_AUDIO_PLL_0>; + power-domains =<&pd_audio>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = <SC_R_AUDIO_PLL_1>; + power-domains =<&pd_audio_pll0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = <SC_R_AUDIO_CLK_0>; + power-domains =<&pd_audio_pll1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = <SC_R_AUDIO_CLK_1>; + power-domains =<&pd_audio_clk0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan0: PD_ASRC_0_RXA { + reg = <SC_R_DMA_2_CH0>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan1: PD_ASRC_0_RXB { + reg = <SC_R_DMA_2_CH1>; + power-domains =<&pd_dma2_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan2: PD_ASRC_0_RXC { + reg = <SC_R_DMA_2_CH2>; + power-domains =<&pd_dma2_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan3: PD_ASRC_0_TXA { + reg = <SC_R_DMA_2_CH3>; + power-domains =<&pd_dma2_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan4: PD_ASRC_0_TXB { + reg = <SC_R_DMA_2_CH4>; + power-domains =<&pd_dma2_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan5: PD_ASRC_0_TXC { + reg = <SC_R_DMA_2_CH5>; + power-domains =<&pd_dma2_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = <SC_R_ASRC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan5>; + }; + }; + }; + }; + }; + }; + }; + + pd_dma3_chan0: PD_ASRC_1_RXA { + reg = <SC_R_DMA_3_CH0>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan1: PD_ASRC_1_RXB { + reg = <SC_R_DMA_3_CH1>; + power-domains =<&pd_dma3_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan2: PD_ASRC_1_RXC { + reg = <SC_R_DMA_3_CH2>; + power-domains =<&pd_dma3_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan3: PD_ASRC_1_TXA { + reg = <SC_R_DMA_3_CH3>; + power-domains =<&pd_dma3_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan4: PD_ASRC_1_TXB { + reg = <SC_R_DMA_3_CH4>; + power-domains =<&pd_dma3_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan5: PD_ASRC_1_TXC { + reg = <SC_R_DMA_3_CH5>; + power-domains =<&pd_dma3_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc1: PD_AUD_ASRC_1 { + reg = <SC_R_ASRC_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dma3_chan5>; + + }; + }; + }; + }; + }; + }; + }; + pd_dma2_chan6: PD_ESAI_0_RX { + reg = <SC_R_DMA_2_CH6>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan7: PD_ESAI_0_TX { + reg = <SC_R_DMA_2_CH7>; + power-domains =<&pd_dma2_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = <SC_R_ESAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan7>; + }; + }; + }; + + pd_dma3_chan6: PD_ESAI_1_RX { + reg = <SC_R_DMA_3_CH6>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan7: PD_ESAI_1_TX { + reg = <SC_R_DMA_3_CH7>; + power-domains =<&pd_dma3_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai1: PD_AUD_ESAI_1 { + reg = <SC_R_ESAI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dma3_chan7>; + }; + }; + }; + pd_dma2_chan8: PD_SPDIF_0_RX { + reg = <SC_R_DMA_2_CH8>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan9: PD_SPDIF_0_TX { + reg = <SC_R_DMA_2_CH9>; + power-domains =<&pd_dma2_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_spdif0: PD_AUD_SPDIF_0 { + reg = <SC_R_SPDIF_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan9>; + + }; + }; + }; + pd_dma2_chan10: PD_SPDIF_1_RX { + reg = <SC_R_DMA_2_CH10>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan11: PD_SPDIF_1_TX { + reg = <SC_R_DMA_2_CH11>; + power-domains =<&pd_dma2_chan10>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_spdif1: PD_AUD_SPDIF_1 { + reg = <SC_R_SPDIF_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan11>; + + }; + }; + }; + pd_dma2_chan12: PD_SAI_0_RX { + reg = <SC_R_DMA_2_CH12>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_SAI_0_TX { + reg = <SC_R_DMA_2_CH13>; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai0:PD_AUD_SAI_0 { + reg = <SC_R_SAI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan13>; + }; + }; + + }; + pd_dma2_chan14: PD_SAI_1_RX { + reg = <SC_R_DMA_2_CH14>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan15: PD_SAI_1_TX { + reg = <SC_R_DMA_2_CH15>; + power-domains =<&pd_dma2_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai1: PD_AUD_SAI_1 { + reg = <SC_R_SAI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan15>; + }; + }; + }; + pd_dma2_chan16: PD_SAI_2_RX { + reg = <SC_R_DMA_2_CH16>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai2: PD_AUD_SAI_2 { + reg = <SC_R_SAI_2>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan16>; + }; + }; + pd_dma2_chan17: PD_SAI_3_RX { + reg = <SC_R_DMA_2_CH17>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai3: PD_AUD_SAI_3 { + reg = <SC_R_SAI_3>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan17>; + }; + }; + pd_dma2_chan18: PD_SAI_4_RX { + reg = <SC_R_DMA_2_CH18>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai4: PD_AUD_SAI_4 { + reg = <SC_R_SAI_4>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan18>; + }; + }; + pd_dma2_chan19: PD_SAI_5_RX { + reg = <SC_R_DMA_2_CH19>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai5: PD_AUD_SAI_5 { + reg = <SC_R_SAI_5>; + #power-domain-cells = <0>; + power-domains =<&pd_dma2_chan19>; + }; + }; + pd_dma3_chan8: PD_SAI_6_RX { + reg = <SC_R_DMA_3_CH8>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan9: PD_SAI_6_TX { + reg = <SC_R_DMA_3_CH9>; + power-domains =<&pd_dma3_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai6: PD_AUD_SAI_6 { + reg = <SC_R_SAI_6>; + #power-domain-cells = <0>; + power-domains =<&pd_dma3_chan9>; + + }; + }; + }; + pd_dma3_chan10: PD_SAI_7_TX { + reg = <SC_R_DMA_3_CH10>; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai7: PD_AUD_SAI_7 { + reg = <SC_R_SAI_7>; + #power-domain-cells = <0>; + power-domains =<&pd_dma3_chan10>; + }; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = <SC_R_GPT_5>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = <SC_R_GPT_6>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = <SC_R_GPT_7>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = <SC_R_GPT_8>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt9: PD_AUD_GPT_9 { + reg = <SC_R_GPT_9>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt10: PD_AUD_GPT_10 { + reg = <SC_R_GPT_10>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_amix: PD_AUD_AMIX { + reg = <SC_R_AMIX>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = <SC_R_MQS_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = <SC_R_MCLK_OUT_0>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = <SC_R_MCLK_OUT_1>; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + }; + }; + }; + }; + + pd_dsp_mu_A: PD_DSP_MU_A { + reg = <SC_R_MU_13A>; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_B: PD_DSP_MU_B { + reg = <SC_R_MU_13B>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_A>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = <SC_R_DSP_RAM>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = <SC_R_DSP>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; + }; + }; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = <SC_R_CAN_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <235>; + }; + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = <SC_R_CAN_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <236>; + }; + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = <SC_R_CAN_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <237>; + }; + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = <SC_R_FTM_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = <SC_R_FTM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = <SC_R_ADC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc1: PD_DMA_ADC_1 { + reg = <SC_R_ADC_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = <SC_R_I2C_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = <SC_R_I2C_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = <SC_R_I2C_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = <SC_R_I2C_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c4: PD_DMA_I2C_4 { + reg = <SC_R_I2C_4>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = <SC_R_UART_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <345>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = <SC_R_UART_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <346>; + + pd_dma0_chan14: PD_UART1_RX { + reg = <SC_R_DMA_0_CH14>; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan15: PD_UART1_TX { + reg = <SC_R_DMA_0_CH15>; + power-domains =<&pd_dma0_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma0_chan16: PD_UART2_RX { + reg = <SC_R_DMA_0_CH16>; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan17: PD_UART2_TX { + reg = <SC_R_DMA_0_CH17>; + power-domains =<&pd_dma0_chan16>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = <SC_R_UART_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <348>; + + pd_dma0_chan18: PD_UART3_RX { + reg = <SC_R_DMA_0_CH18>; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan19: PD_UART3_TX { + reg = <SC_R_DMA_0_CH19>; + power-domains =<&pd_dma0_chan18>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart4: PD_DMA_UART4 { + reg = <SC_R_UART_4>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <349>; + + pd_dma0_chan20: PD_UART4_RX { + reg = <SC_R_DMA_0_CH20>; + power-domains =<&pd_dma_lpuart4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan21: PD_UART4_TX { + reg = <SC_R_DMA_0_CH21>; + power-domains =<&pd_dma0_chan20>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = <SC_R_SPI_0>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = <SC_R_SPI_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = <SC_R_SPI_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = <SC_R_SPI_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_emvsim0: PD_DMA_EMVSIM_0 { + reg = <SC_R_EMVSIM_0>; + power-domains = <&pd_dma>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_ldo1_sim: LDO1_SIM { + reg = <SC_R_BOARD_R2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma_emvsim0>; + }; + }; + pd_dma_emvsim1: PD_DMA_EMVSIM_1 { + reg = <SC_R_EMVSIM_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + pd_gpu: PD_GPU { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu0: PD_GPU0 { + reg = <SC_R_GPU_0_PID0>; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + }; + pd_gpu1: PD_GPU1 { + reg = <SC_R_GPU_1_PID0>; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + }; + }; + + pd_vpu: vpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = <SC_R_VPU>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_mu_enc: VPU_ENC_MU { + reg = <SC_R_VPU_MU_1>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_enc: VPU_ENC { + reg = <SC_R_VPU_ENC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_enc>; + }; + }; + + pd_vpu_mu_dec: VPU_DEC_MU { + reg = <SC_R_VPU_MU_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_dec: VPU_DEC { + reg = <SC_R_VPU_DEC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_dec>; + }; + }; + }; + + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = <SC_R_ISI_CH0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_csi0: PD_MIPI_CSI0 { + reg = <SC_R_CSI_0>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_csi0_i2c0: PD_MIPI_CSI0_I2C0 { + reg = <SC_R_CSI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_csi0>; + }; + + pd_csi0_pwm: PD_MIPI_CSI0_PWM { + reg = <SC_R_CSI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_csi0>; + }; + }; + + pd_csi1: PD_MIPI_CSI1 { + reg = <SC_R_CSI_1>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_csi1_i2c0: PD_MIPI_CSI1_I2C0 { + reg = <SC_R_CSI_1_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_csi1>; + }; + + pd_csi1_pwm: PD_MIPI_CSI1_PWM { + reg = <SC_R_CSI_1_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_csi1>; + }; + }; + + pd_hdmi_rx: PD_HDMI_RX { + reg = <SC_R_HDMI_RX>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS { + reg = <SC_R_HDMI_RX_BYPASS>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C { + reg = <SC_R_HDMI_RX_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx_bypass>; + }; + + pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM { + reg = <SC_R_HDMI_RX_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx_bypass>; + }; + }; + }; + + pd_isi_ch1: PD_IMAGING_PDMA1 { + reg = <SC_R_ISI_CH1>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch2: PD_IMAGING_PDMA2 { + reg = <SC_R_ISI_CH2>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch3: PD_IMAGING_PDMA3 { + reg = <SC_R_ISI_CH3>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch4: PD_IMAGING_PDMA4 { + reg = <SC_R_ISI_CH4>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch5: PD_IMAGING_PDMA5 { + reg = <SC_R_ISI_CH5>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch6: PD_IMAGING_PDMA6 { + reg = <SC_R_ISI_CH6>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch7: PD_IMAGING_PDMA7 { + reg = <SC_R_ISI_CH7>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_jpeg_dec_mp: PD_JPEG_DEC_MP { + reg = <SC_R_MJPEG_DEC_MP>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_jpgdec: PD_IMAGING_JPEG_DEC { + reg = <SC_R_MJPEG_DEC_S0>; + #power-domain-cells = <0>; + power-domains =<&pd_jpeg_dec_mp>; + }; + }; + + pd_jpeg_enc_mp: PD_JPEG_ENC_MP { + reg = <SC_R_MJPEG_ENC_MP>; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_jpgenc: PD_IMAGING_JPEG_ENC { + reg = <SC_R_MJPEG_ENC_S0>; + #power-domain-cells = <0>; + power-domains =<&pd_jpeg_enc_mp>; + }; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = <SC_R_M4_0_I2C>; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = <SC_R_M4_0_INTMUX>; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + early_power_on; + }; + }; + + pd_cm41: PD_CM41 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm41_i2c: PD_CM41_I2C { + reg = <SC_R_M4_1_I2C>; + #power-domain-cells = <0>; + power-domains =<&pd_cm41>; + }; + + pd_cm41_intmux: PD_CM41_INTMUX { + reg = <SC_R_M4_1_INTMUX>; + #power-domain-cells = <0>; + power-domains =<&pd_cm41>; + early_power_on; + }; + }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = <SC_R_CAAM_JR1>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = <SC_R_CAAM_JR2>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = <SC_R_CAAM_JR3>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qm-sc-tsens"; + /* number of the temp sensor on the chip */ + tsens-num = <5>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 3>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 4>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + dpu1_intsteer: dpu_intsteer@56000000 { + compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; + reg = <0x0 0x56000000 0x0 0x10000>; + }; + + prg1: prg@56040000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56040000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG0_APB_CLK>, + <&clk IMX8QM_DC0_PRG0_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg2: prg@56050000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56050000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG1_APB_CLK>, + <&clk IMX8QM_DC0_PRG1_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg3: prg@56060000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56060000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG2_APB_CLK>, + <&clk IMX8QM_DC0_PRG2_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg4: prg@56070000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56070000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG3_APB_CLK>, + <&clk IMX8QM_DC0_PRG3_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg5: prg@56080000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56080000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG4_APB_CLK>, + <&clk IMX8QM_DC0_PRG4_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg6: prg@56090000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x56090000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG5_APB_CLK>, + <&clk IMX8QM_DC0_PRG5_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg7: prg@560a0000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x560a0000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG6_APB_CLK>, + <&clk IMX8QM_DC0_PRG6_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg8: prg@560b0000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x560b0000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG7_APB_CLK>, + <&clk IMX8QM_DC0_PRG7_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg9: prg@560c0000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x560c0000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC0_PRG8_APB_CLK>, + <&clk IMX8QM_DC0_PRG8_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel1: dpr-channel@560d0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560d0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_BLIT0>; + fsl,prgs = <&prg1>; + clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>, + <&clk IMX8QM_DC0_DPR0_B_CLK>, + <&clk IMX8QM_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel2: dpr-channel@560e0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560e0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_BLIT1>; + fsl,prgs = <&prg2>, <&prg1>; + clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>, + <&clk IMX8QM_DC0_DPR0_B_CLK>, + <&clk IMX8QM_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel3: dpr-channel@560f0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560f0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_FRAC0>; + fsl,prgs = <&prg3>; + clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>, + <&clk IMX8QM_DC0_DPR0_B_CLK>, + <&clk IMX8QM_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel1: dpr-channel@56100000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56100000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_VIDEO0>; + fsl,prgs = <&prg4>, <&prg5>; + clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>, + <&clk IMX8QM_DC0_DPR1_B_CLK>, + <&clk IMX8QM_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel2: dpr-channel@56110000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56110000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_VIDEO1>; + fsl,prgs = <&prg6>, <&prg7>; + clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>, + <&clk IMX8QM_DC0_DPR1_B_CLK>, + <&clk IMX8QM_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel3: dpr-channel@56120000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56120000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_0_WARP>; + fsl,prgs = <&prg8>, <&prg9>; + clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>, + <&clk IMX8QM_DC0_DPR1_B_CLK>, + <&clk IMX8QM_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu1_intsteer>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit", + "irq_dpr0", + "irq_dpr1"; + clocks = <&clk IMX8QM_DC0_PLL0_CLK>, + <&clk IMX8QM_DC0_PLL1_CLK>, + <&clk IMX8QM_DC0_BYPASS_0_DIV>, + <&clk IMX8QM_DC0_DISP0_SEL>, + <&clk IMX8QM_DC0_DISP1_SEL>, + <&clk IMX8QM_DC0_DISP0_CLK>, + <&clk IMX8QM_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "bypass0", + "disp0_sel", "disp1_sel", "disp0", "disp1"; + power-domains = <&pd_dc0_pll1>; + fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, + <&dpr1_channel3>, <&dpr2_channel1>, + <&dpr2_channel2>, <&dpr2_channel3>; + status = "disabled"; + + dpu1_disp0: port@0 { + reg = <0>; + + dpu1_disp0_hdmi: hdmi-endpoint { + remote-endpoint = <&hdmi_disp>; + }; + + dpu1_disp0_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi1_in>; + }; + }; + + dpu1_disp1: port@1 { + reg = <1>; + + dpu1_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb1_lvds0>; + }; + + dpu1_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb1_lvds1>; + }; + }; + }; + + hdmi:hdmi@56268000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x56268000 0x0 0x100000>, /* HDP Controller */ + <0x0 0x56261000 0x0 0x1000>; /* HDP SubSystem CSR */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + status = "disabled"; + clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_IPG_CLK>, + <&clk IMX8QM_HDMI_HDP_CORE_CLK>, + <&clk IMX8QM_HDMI_PXL_CLK>, + <&clk IMX8QM_HDMI_PXL_MUX_CLK>, + <&clk IMX8QM_HDMI_PXL_LINK_CLK>, + <&clk IMX8QM_HDMI_HDP_CLK>, + <&clk IMX8QM_HDMI_HDP_PHY_CLK>, + <&clk IMX8QM_HDMI_APB_CLK>, + <&clk IMX8QM_HDMI_LIS_IPG_CLK>, + <&clk IMX8QM_HDMI_MSI_HCLK>, + <&clk IMX8QM_HDMI_PXL_LPCG_CLK>, + <&clk IMX8QM_HDMI_PXL_EVEN_CLK>, + <&clk IMX8QM_HDMI_PXL_DBL_CLK>, + <&clk IMX8QM_HDMI_VIF_CLK>, + <&clk IMX8QM_HDMI_APB_MUX_CSR_CLK>, + <&clk IMX8QM_HDMI_APB_MUX_CTRL_CLK>, + <&clk IMX8QM_HDMI_I2S_CLK>, + <&clk IMX8QM_HDMI_I2S_BYPASS_CLK>; + clock-names = "dig_pll", "av_pll", "clk_ipg", + "clk_core", "clk_pxl", "clk_pxl_mux", + "clk_pxl_link", "clk_hdp", "clk_phy", + "clk_apb", "clk_lis","clk_msi", + "clk_lpcg", "clk_even","clk_dbl", + "clk_vif", "clk_apb_csr","clk_apb_ctrl", + "clk_i2s", "clk_i2s_bypass"; + power-domains = <&pd_hdmi_i2s>; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dpu1_disp0_hdmi>; + }; + }; + }; + + irqsteer_dsi0: irqsteer@56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_MIPI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi0>; + }; + + i2c0_mipi_dsi0: i2c@56226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi0>; + clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>, + <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi0_i2c0>; + status = "disabled"; + }; + + mipi_dsi_csr1: csr@56221000 { + compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon"; + reg = <0x0 0x56221000 0x0 0x1000>; + }; + + mipi_dsi_phy1: dsi_phy@56228300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qm-mipi-dsi-phy"; + reg = <0x0 0x56228300 0x0 0x100>; + power-domains = <&pd_mipi0>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi1: mipi_dsi@56228000 { + compatible = "fsl,imx8qm-mipi-dsi"; + clocks = + <&clk IMX8QM_MIPI0_PXL_CLK>, + <&clk IMX8QM_MIPI0_BYPASS_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi0>; + csr = <&mipi_dsi_csr1>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + pwr-delay = <100>; + status = "disabled"; + + port@0 { + mipi_dsi1_in: endpoint { + remote-endpoint = <&dpu1_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi1_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_in>; + }; + }; + }; + + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi0>; + clocks = + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>; + assigned-clock-rates = <18000000>, <72000000>; + power-domains = <&pd_mipi0>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge1_in: endpoint { + remote-endpoint = <&mipi_dsi1_out>; + }; + }; + }; + + lvds_region1: lvds_region@56240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + + ldb1_phy: ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, + <&clk IMX8QM_LVDS0_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds0>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds0: endpoint { + remote-endpoint = <&dpu1_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds1: endpoint { + remote-endpoint = <&dpu1_disp1_lvds1>; + }; + }; + }; + }; + + lvds0_pwm: pwm@56244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x56244000 0 0x1000>; + clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>, + <&clk IMX8QM_LVDS0_PWM0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lvds0_pwm>; + status = "disabled"; + }; + + dpu2_intsteer: dpu_intsteer@57000000 { + compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; + reg = <0x0 0x57000000 0x0 0x10000>; + }; + + prg10: prg@57040000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x57040000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG0_APB_CLK>, + <&clk IMX8QM_DC1_PRG0_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg11: prg@57050000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x57050000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG1_APB_CLK>, + <&clk IMX8QM_DC1_PRG1_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg12: prg@57060000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x57060000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG2_APB_CLK>, + <&clk IMX8QM_DC1_PRG2_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg13: prg@57070000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x57070000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG3_APB_CLK>, + <&clk IMX8QM_DC1_PRG3_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg14: prg@57080000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x57080000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG4_APB_CLK>, + <&clk IMX8QM_DC1_PRG4_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg15: prg@57090000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x57090000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG5_APB_CLK>, + <&clk IMX8QM_DC1_PRG5_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg16: prg@570a0000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x570a0000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG6_APB_CLK>, + <&clk IMX8QM_DC1_PRG6_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg17: prg@570b0000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x570b0000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG7_APB_CLK>, + <&clk IMX8QM_DC1_PRG7_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + prg18: prg@570c0000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x0 0x570c0000 0x0 0x10000>; + clocks = <&clk IMX8QM_DC1_PRG8_APB_CLK>, + <&clk IMX8QM_DC1_PRG8_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpr3_channel1: dpr-channel@570d0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x570d0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_1_BLIT0>; + fsl,prgs = <&prg10>; + clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>, + <&clk IMX8QM_DC1_DPR0_B_CLK>, + <&clk IMX8QM_DC1_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpr3_channel2: dpr-channel@570e0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x570e0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_1_BLIT1>; + fsl,prgs = <&prg11>, <&prg10>; + clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>, + <&clk IMX8QM_DC1_DPR0_B_CLK>, + <&clk IMX8QM_DC1_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpr3_channel3: dpr-channel@570f0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x570f0000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_1_FRAC0>; + fsl,prgs = <&prg12>; + clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>, + <&clk IMX8QM_DC1_DPR0_B_CLK>, + <&clk IMX8QM_DC1_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpr4_channel1: dpr-channel@57100000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x57100000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_1_VIDEO0>; + fsl,prgs = <&prg13>, <&prg14>; + clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>, + <&clk IMX8QM_DC1_DPR1_B_CLK>, + <&clk IMX8QM_DC1_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpr4_channel2: dpr-channel@57110000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x57110000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_1_VIDEO1>; + fsl,prgs = <&prg15>, <&prg16>; + clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>, + <&clk IMX8QM_DC1_DPR1_B_CLK>, + <&clk IMX8QM_DC1_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpr4_channel3: dpr-channel@56712000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x57120000 0x0 0x10000>; + fsl,sc-resource = <SC_R_DC_1_WARP>; + fsl,prgs = <&prg17>, <&prg18>; + clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>, + <&clk IMX8QM_DC1_DPR1_B_CLK>, + <&clk IMX8QM_DC1_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc1>; + status = "disabled"; + }; + + dpu2: dpu@57180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x57180000 0x0 0x40000>; + intsteer = <&dpu2_intsteer>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit", + "irq_dpr0", + "irq_dpr1"; + clocks = <&clk IMX8QM_DC1_PLL0_CLK>, + <&clk IMX8QM_DC1_PLL1_CLK>, + <&clk IMX8QM_DC1_BYPASS_0_DIV>, + <&clk IMX8QM_DC1_DISP0_SEL>, + <&clk IMX8QM_DC1_DISP1_SEL>, + <&clk IMX8QM_DC1_DISP0_CLK>, + <&clk IMX8QM_DC1_DISP1_CLK>; + clock-names = "pll0", "pll1", "bypass0", + "disp0_sel", "disp1_sel", "disp0", "disp1"; + power-domains = <&pd_dc1_pll1>; + fsl,dpr-channels = <&dpr3_channel1>, <&dpr3_channel2>, + <&dpr3_channel3>, <&dpr4_channel1>, + <&dpr4_channel2>, <&dpr4_channel3>; + status = "disabled"; + + dpu2_disp0: port@0 { + reg = <0>; + + dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi2_in>; + }; + }; + + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; + }; + }; + }; + + irqsteer_dsi1: irqsteer@57220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x57220000 0x0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_MIPI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi1>; + }; + + i2c0_mipi_dsi1: i2c@57226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi1>; + clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>, + <&clk IMX8QM_MIPI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi1_i2c0>; + status = "disabled"; + }; + + mipi_dsi_csr2: csr@57221000 { + compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon"; + reg = <0x0 0x57221000 0x0 0x1000>; + }; + + mipi_dsi_phy2: mipi_phy@57228300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qm-mipi-dsi-phy"; + reg = <0x0 0x57228300 0x0 0x100>; + power-domains = <&pd_mipi1>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi2: mipi_dsi@57228000 { + compatible = "fsl,imx8qm-mipi-dsi"; + clocks = + <&clk IMX8QM_MIPI1_PXL_CLK>, + <&clk IMX8QM_MIPI1_BYPASS_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi1>; + csr = <&mipi_dsi_csr2>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + pwr-delay = <100>; + status = "disabled"; + + port@0 { + mipi_dsi2_in: endpoint { + remote-endpoint = <&dpu2_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi2_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_in>; + }; + }; + }; + + mipi_dsi_bridge2: mipi_dsi_bridge@57228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x57228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi1>; + clocks = + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>, + <&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>; + assigned-clock-rates = <18000000>, <72000000>; + power-domains = <&pd_mipi1>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge2_in: endpoint { + remote-endpoint = <&mipi_dsi2_out>; + }; + }; + }; + + lvds_region2: lvds_region@57240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x57240000 0x0 0x10000>; + }; + + ldb2_phy: ldb_phy@57241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x57241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS1_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, + <&clk IMX8QM_LVDS1_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds1>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds0: endpoint { + remote-endpoint = <&dpu2_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds1: endpoint { + remote-endpoint = <&dpu2_disp1_lvds1>; + }; + }; + }; + }; + + lvds1_pwm: pwm@57244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x57244000 0 0x1000>; + clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>, + <&clk IMX8QM_LVDS1_PWM0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lvds1_pwm>; + status = "disabled"; + }; + + camera: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58100000 0x0 0x10000>; + interrupts = <0 297 0>; + interface = <2 0 2>; /* <Input MIPI_VCx Output> + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch0>; + status = "disabled"; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58110000 0x0 0x10000>; + interrupts = <0 298 0>; + interface = <2 1 2>; + clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch1>; + status = "disabled"; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58120000 0x0 0x10000>; + interrupts = <0 299 0>; + interface = <2 2 2>; + clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch2>; + status = "disabled"; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58130000 0x0 0x10000>; + interrupts = <0 300 0>; + interface = <2 3 2>; + clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch3>; + status = "disabled"; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58140000 0x0 0x10000>; + interrupts = <0 301 0>; + interface = <3 0 2>; + clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch4>; + status = "disabled"; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58150000 0x0 0x10000>; + interrupts = <0 302 0>; + interface = <3 1 2>; + clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch5>; + status = "disabled"; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58160000 0x0 0x10000>; + interrupts = <0 303 0>; + interface = <3 2 2>; + clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch6>; + status = "disabled"; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58170000 0x0 0x10000>; + interrupts = <0 304 0>; + interface = <3 3 2>; + clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch7>; + status = "disabled"; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ + <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CSI0_CORE_CLK>, + <&clk IMX8QM_CSI0_ESC_CLK>, + <&clk IMX8QM_IMG_PXL_LINK_CSI0_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QM_CSI0_CORE_CLK>, + <&clk IMX8QM_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_csi0>; + status = "disabled"; + }; + + mipi_csi_1: csi@58247000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58247000 0x0 0x1000>, /* CSI1 Controler base addr */ + <0x0 0x58241000 0x0 0x1000>; /* CSI1 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CSI1_CORE_CLK>, + <&clk IMX8QM_CSI1_ESC_CLK>, + <&clk IMX8QM_IMG_PXL_LINK_CSI1_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QM_CSI1_CORE_CLK>, + <&clk IMX8QM_CSI1_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_csi1>; + status = "disabled"; + }; + + hdmi_rx: hdmi_rx@58268000 { + compatible = "fsl,imx-hdmi-rx"; + reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */ + <0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi_rx>; + clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>, + <&clk IMX8QM_HDMI_RX_HD_CORE_CLK>, + <&clk IMX8QM_HDMI_RX_PXL_CLK>, + <&clk IMX8QM_HDMI_RX_SINK_PCLK>, + <&clk IMX8QM_HDMI_RX_SINK_SCLK>, + <&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>, + <&clk IMX8QM_HDMI_RX_I2S_CLK>, + <&clk IMX8QM_HDMI_RX_SPDIF_CLK>, + <&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>; + clock-names = "ref_clk", "core_clk", "pxl_clk", + "pclk", "sclk", "enc_clk", + "i2s_clk", "spdif_clk", + "pxl_link_clk"; + power-domains = <&pd_hdmi_rx_bypass>; + status = "disabled"; + }; + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x0 0x58400000 0x0 0x00040020 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >, + <&clk IMX8QM_IMG_JPEG_DEC_CLK >; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >, + <&clk IMX8QM_IMG_JPEG_DEC_CLK >; + assigned-clock-rates = <200000000>; + power-domains =<&pd_jpgdec>; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x0 0x58450000 0x0 0x00240020 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >, + <&clk IMX8QM_IMG_JPEG_ENC_CLK >; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >, + <&clk IMX8QM_IMG_JPEG_ENC_CLK >; + assigned-clock-rates = <200000000>; + power-domains =<&pd_jpgenc>; + }; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_ADC0_CLK>, + <&clk IMX8QM_ADC0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_ADC0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_adc0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x0 0x5a890000 0x0 0x10000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_ADC1_CLK>, + <&clk IMX8QM_ADC1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_ADC1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_adc1>; + status = "disabled"; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C0_CLK>, + <&clk IMX8QM_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C1_CLK>, + <&clk IMX8QM_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C2_CLK>, + <&clk IMX8QM_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C3_CLK>, + <&clk IMX8QM_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a840000 0x0 0x4000>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C4_CLK>, + <&clk IMX8QM_I2C4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C4_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c4>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QM_CM40_I2C_CLK>, + <&clk IMX8QM_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + status = "disabled"; + }; + + i2c0_cm41: i2c@3b230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x3b230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm41>; + clocks = <&clk IMX8QM_CM41_I2C_CLK>, + <&clk IMX8QM_CM41_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CM41_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm41_i2c>; + status = "disabled"; + }; + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56260000 0x0 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_HDMI_LIS_IPG_CLK>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_LIS_IPG_CLK>; + assigned-clock-rates = <675000000>, <84375000>; + power-domains = <&pd_hdmi>; + }; + + irqsteer_hdmi_rx: irqsteer@58260000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58260000 0x0 0x1000>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_hdmi_rx>; + }; + + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56266000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8QM_HDMI_I2C0_CLK>, + <&clk IMX8QM_HDMI_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_hdmi_i2c0>; + status = "disabled"; + }; + + irqsteer_lvds0: irqsteer@562400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lvds0>; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_CAN0_IPG_CLK>, + <&clk IMX8QM_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_CAN1_IPG_CLK>, + <&clk IMX8QM_CAN1_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_CAN1_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_CAN2_IPG_CLK>, + <&clk IMX8QM_CAN2_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_CAN2_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan2>; + status = "disabled"; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>, + <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds0_i2c0>; + status = "disabled"; + }; + + irqsteer_lvds1: irqsteer@572400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x57240000 0x0 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lvds1>; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>, + <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds1_i2c0>; + status = "disabled"; + }; + + irqsteer_csi0: irqsteer@58220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58220000 0x0 0x1000>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg"; + power-domains = <&pd_csi0>; + }; + + i2c0_mipi_csi0: i2c@58226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + clocks = <&clk IMX8QM_CSI0_I2C0_CLK>, + <&clk IMX8QM_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_csi0_i2c0>; + status = "disabled"; + }; + + irqsteer_csi1: irqsteer@582400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58240000 0x0 0x1000>; + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg"; + power-domains = <&pd_csi1>; + }; + + i2c0_mipi_csi1: i2c@58246000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58246000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + clocks = <&clk IMX8QM_CSI1_I2C0_CLK>, + <&clk IMX8QM_CSI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_CSI1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_csi1_i2c0>; + status = "disabled"; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI0_CLK>, + <&clk IMX8QM_SPI0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_SPI0_CLK>; + assigned-clock-rates = <20000000>; + power-domains = <&pd_dma_lpspi0>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART0_CLK>, + <&clk IMX8QM_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART1_CLK>, + <&clk IMX8QM_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan15>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan17>; + dma-names = "tx","rx"; + dmas = <&edma0 17 0 0>, + <&edma0 16 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART3_CLK>, + <&clk IMX8QM_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan19>; + dma-names = "tx","rx"; + dmas = <&edma0 19 0 0>, + <&edma0 18 0 1>; + status = "disabled"; + }; + + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a0a0000 0x0 0x1000>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART4_CLK>, + <&clk IMX8QM_UART4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART4_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan21>; + dma-names = "tx","rx"; + dmas = <&edma0 21 0 0>, + <&edma0 20 0 1>; + status = "disabled"; + }; + + ftmpwm0: ftmpwm@0x05a8a0000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0 0x5A8A0000 0 0x1000>; + #pwm-cells = <3>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en", "ipg"; + clocks = <&clk IMX8QM_FTM0_CLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_FTM0_CLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_FTM0_IPG_CLK>; + assigned-clocks = <&clk IMX8QM_FTM0_CLK>; + assigned-clock-rates = <8000000>; + power-domains = <&pd_dma_ftm0>; + ftm-has-pwmen-bits; + status = "disabled"; + }; + + ftmpwm1: ftmpwm@0x05a8b0000 { + compatible = "fsl,vf610-ftm-pwm"; + reg = <0 0x5A8B0000 0 0x1000>; + #pwm-cells = <3>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en", "ipg"; + clocks = <&clk IMX8QM_FTM1_CLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_FTM1_CLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_FTM0_IPG_CLK>; + assigned-clocks = <&clk IMX8QM_FTM1_CLK>; + assigned-clock-rates = <8000000>; + power-domains = <&pd_dma_ftm1>; + ftm-has-pwmen-bits; + status = "disabled"; + }; + + emvsim0: sim0@5a0d0000 { + compatible = "fsl,imx8-emvsim"; + reg = <0x0 0x5a0d0000 0x0 0x10000>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_EMVSIM0_CLK>, + <&clk IMX8QM_EMVSIM0_IPG_CLK>; + clock-names = "sim", "ipg"; + power-domains = <&pd_ldo1_sim>; + status = "disabled"; + }; + + edma0: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */ + <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */ + <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */ + <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <10>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + status = "okay"; + }; + + edma2: dma-controller@591F0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */ + <0x0 0x592B0000 0x0 0x10000>, /* spdif1 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <18>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */ + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ + "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ + status = "okay"; + }; + + edma3: dma-controller@599F0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */ + interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ + "edma3-chan2-rx", "edma3-chan3-tx", + "edma3-chan4-tx", "edma3-chan5-tx", + "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ + "edma3-chan10-tx"; /* sai7 */ + status = "okay"; + }; + + wu: wu { + compatible = "fsl,imx8-wu"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x58222000 0x0 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_csi0>; + status = "disabled"; + }; + + gpio0_mipi_csi1: gpio@58242000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x58242000 0x0 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd_csi1>; + status = "disabled"; + }; + + gpt0: gpt0@5d140000 { + compatible = "fsl,imx8qm-gpt"; + reg = <0x0 0x5d140000 0x0 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_GPT0_CLK>, <&clk IMX8QM_GPT_3M>; + clock-names = "ipg", "per"; + power-domains = <&pd_lsio_gpt0>; + }; + + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QM_PWM0_HF_CLK>, + <&clk IMX8QM_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QM_PWM1_HF_CLK>, + <&clk IMX8QM_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QM_PWM2_HF_CLK>, + <&clk IMX8QM_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QM_PWM3_HF_CLK>, + <&clk IMX8QM_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QM_PWM4_HF_CLK>, + <&clk IMX8QM_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QM_PWM5_HF_CLK>, + <&clk IMX8QM_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QM_PWM6_HF_CLK>, + <&clk IMX8QM_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QM_PWM7_HF_CLK>, + <&clk IMX8QM_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x53100000 0 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = <SC_R_GPU_0_PID0>; + power-domains = <&pd_gpu0>; + status = "disabled"; + }; + + gpu_3d1: gpu@54100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x54100000 0x0 0x40000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = <SC_R_GPU_1_PID0>; + power-domains = <&pd_gpu1>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>, <&gpu_3d1>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + depth-compression = <0>; + status = "disabled"; + }; + + mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, + <&clk IMX8QM_SDHC0_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + iommus = <&smmu 0x11 0x7f80>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, + <&clk IMX8QM_SDHC1_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + iommus = <&smmu 0x11 0x7f80>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, + <&clk IMX8QM_SDHC2_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch2>; + iommus = <&smmu 0x11 0x7f80>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>, + <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, + <&clk IMX8QM_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet0>; + iommus = <&smmu 0x12 0x7f80>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>, + <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, + <&clk IMX8QM_ENET1_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet1>; + iommus = <&smmu 0x12 0x7f80>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0e0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x200>; + clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QM_USB3_PHY_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usb2_phy>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + status = "disabled"; + }; + + usbh1: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0e0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "hsic"; + dr_mode = "host"; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbh1>; + status = "disabled"; + }; + + usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>, + <0x0 0x5B120000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_USB3_LPM_CLK>, + <&clk IMX8QM_USB3_BUS_CLK>, + <&clk IMX8QM_USB3_ACLK>, + <&clk IMX8QM_USB3_IPG_CLK>, + <&clk IMX8QM_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + status = "disabled"; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + }; + + ddr_pmu1: ddr_pmu@5c120000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c120000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu", "nxp,imx8x-vpu"; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "iobase_vpu"; + interrupts = <0 464 0x4>; + interrupt-names = "irq_vpu"; + clocks = <&clk IMX8QM_VPU_DDR_CLK>, + <&clk IMX8QM_VPU_SYS_CLK>, + <&clk IMX8QM_VPU_XUVI_CLK>, + <&clk IMX8QM_VPU_UART_CLK>; + clock-names = "clk_vpu_ddr", "clk_vpu_sys", + "clk_vpu_xuvi", "clk_vpu_uart"; + assigned-clocks = <&clk IMX8QM_VPU_DDR_CLK>, + <&clk IMX8QM_VPU_SYS_CLK>, + <&clk IMX8QM_VPU_XUVI_CLK>, + <&clk IMX8QM_VPU_UART_CLK>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <80000000>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + dsp: dsp@556e8000 { + compatible = "fsl,imx8qxp-dsp"; + reserved-region = <&dsp_reserved>; + reg = <0x0 0x556e8000 0x0 0x88000>; + clocks = <&clk IMX8QM_AUD_DSP_IPG>, + <&clk IMX8QM_AUD_OCRAM_IPG>, + <&clk IMX8QM_AUD_DSP_CORE_CLK>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + fixup-offset = <0x4000000>; + power-domains = <&pd_dsp>; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x0 0x59010000 0x0 0x10000>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QM_AUD_ESAI_0_IPG>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_esai0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&clk IMX8QM_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QM_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59030000 0x0 0x10000>; + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&clk IMX8QM_AUD_SPDIF_1_GCLKW>, /* core */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QM_AUD_SPDIF_1_TX_CLK>, /* rxtx1 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma2 10 0 5>, <&edma2 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif1>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_1_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_1_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_0_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_0_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59060000 0x0 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_2_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_2_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma2 16 0 1>; + status = "disabled"; + power-domains = <&pd_sai2>; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59070000 0x0 0x10000>; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_3_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_3_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma2 17 0 1>; + status = "disabled"; + power-domains = <&pd_sai3>; + }; + + sai_hdmi_rx: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59080000 0x0 0x10000>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_HDMIRX0_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_HDMIRX0_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma2 18 0 1>; + fsl,dataline = <0xf 0x0>; + status = "disabled"; + power-domains = <&pd_sai4>; + }; + + sai_hdmi_tx: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59090000 0x0 0x10000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_HDMITX0_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma2 19 0 0>; + fsl,dataline = <0x0 0xf>; + status = "disabled"; + power-domains = <&pd_sai5>; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x0 0x59810000 0x0 0x10000>; + interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_ESAI_1_IPG>, + <&clk IMX8QM_AUD_ESAI_1_EXTAL_IPG>, + <&clk IMX8QM_AUD_ESAI_1_IPG>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma3 6 0 1>, <&edma3 7 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + power-domains = <&pd_esai1>; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59820000 0x0 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_6_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_6_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; + status = "disabled"; + power-domains = <&pd_sai6>; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59830000 0x0 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_SAI_7_IPG>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_AUD_SAI_7_MCLK>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma3 10 0 0>; + status = "disabled"; + power-domains = <&pd_sai7>; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QM_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + status = "disabled"; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_ASRC_0_IPG>, + <&clk IMX8QM_AUD_ASRC_0_MEM>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QM_ACM_AUD_CLK0_SEL>, + <&clk IMX8QM_ACM_AUD_CLK1_SEL>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, + <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x0 0x59800000 0x0 0x10000>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_AUD_ASRC_1_IPG>, + <&clk IMX8QM_AUD_ASRC_1_MEM>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QM_ACM_AUD_CLK0_SEL>, + <&clk IMX8QM_ACM_AUD_CLK1_SEL>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, + <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc1>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QM_AUD_MQS_IPG>, + <&clk IMX8QM_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-flexspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x10000000>; + reg-names = "FlexSPI", "FlexSPI-memory"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_FSPI0_CLK>; + assigned-clock-rates = <29000000>; + clock-names = "fspi"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + display: display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + ocotp: ocotp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8qm-ocotp", "syscon"; + }; + + pciea: pcie@0x5f000000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */ + <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + power-domains = <&pd_pcie1>; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + hsio = <&hsio>; + ctrl-id = <0>; /* pciea */ + cpu-base-addr = <0x40000000>; + status = "disabled"; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie1>; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + sata: sata@5f020000 { + compatible = "fsl,imx8qm-ahci"; + reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */ + <0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */ + reg-names = "ctl", "phy"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_HSIO_SATA_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "phy_pclk0", "phy_pclk1", "phy_apbclk"; + hsio = <&hsio>; + power-domains = <&pd_sata0>; + iommus = <&smmu 0x13 0x7f80>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + intmux_cm41: intmux@3b400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x3b400000 0x0 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_CM41_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm41_intmux>; + status = "disabled"; + }; + + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu_rpmsg: mu_rpmsg@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x5d200000 0x0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_LSIO_MU5A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu5a>; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qm-rpmsg"; + power-domains = <&pd_lsio_mu5a>; + status = "disabled"; + }; + + mu_rpmsg1: mu_rpmsg1@5d210000 { + compatible = "fsl,imx-mu-rpmsg1"; + reg = <0x0 0x5d210000 0x0 0x10000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_LSIO_MU6A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu6a>; + status = "okay"; + }; + + rpmsg1: rpmsg1{ + compatible = "fsl,imx8qm-rpmsg"; + multi-core-id = <1>; + power-domains = <&pd_lsio_mu6a>; + status = "disabled"; + }; + }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x1ffff>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + + wdog: wdog { + compatible = "fsl,imx8-wdt"; + }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi new file mode 100644 index 000000000000..410954296779 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* fec1 cannot attach to ethphy0 since the PHY address + * conflict with ethphy2. So eth0 should not work. + * There still enable fec1 to share the MDIO bus for fec2 due + * to board limitation. + */ +&fec1 { + /* PHY address should rework to 2 */ + phy-handle = <ðphy2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + tja110x,refclk_in; + /delete-property/ at803x,eee-disabled; + /delete-property/ at803x,vddio-1p8v; + }; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&clk IMX8QM_ENET1_IPG_CLK>, + <&clk IMX8QM_ENET1_AHB_CLK>, + <&clk IMX8QM_ENET1_REF_50MHZ_CLK>, + <&clk IMX8QM_ENET1_PTP_CLK>, + <&clk IMX8QM_ENET1_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + /delete-property/ phy-supply; +}; + +&iomuxc { + imx8qm-mek { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts new file mode 100644 index 000000000000..64c530e4ba1f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-8cam.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * MIPI CSI-2 eight cameras dts, + * One MIPI CSI-2 controller connected four cameras + * The first four cameras have enabled in mipi_csi_0. + * Enable the last four cameras in mipi_csi_1 here. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&mipi_csi_1 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts new file mode 100644 index 000000000000..5ccd8924cc20 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dom0.dts @@ -0,0 +1,331 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" +#include "fsl-imx8qm-xen.dtsi" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_GPU_1_PID0 + SC_R_GPU_1_PID1 + SC_R_GPU_1_PID2 + SC_R_GPU_1_PID3 + SC_R_LVDS_1 + SC_R_LVDS_1_I2C_0 + SC_R_LVDS_1_PWM_0 + SC_R_DC_1 + SC_R_DC_1_BLIT0 + SC_R_DC_1_BLIT1 + SC_R_DC_1_BLIT2 + SC_R_DC_1_BLIT_OUT + SC_R_DC_1_CAPTURE0 + SC_R_DC_1_CAPTURE1 + SC_R_DC_1_WARP + SC_R_DC_1_INTEGRAL0 + SC_R_DC_1_INTEGRAL1 + SC_R_DC_1_VIDEO0 + SC_R_DC_1_VIDEO1 + SC_R_DC_1_FRAC0 + SC_R_DC_1_FRAC1 + SC_R_DC_1_PLL_0 + SC_R_DC_1_PLL_1 + SC_R_MIPI_1 + SC_R_MIPI_1_I2C_0 + SC_R_MIPI_1_I2C_1 + SC_R_MIPI_1_PWM_0 + SC_R_HDMI + SC_R_HDMI_I2C_0 + SC_R_SDHC_0 + SC_R_USB_0 + SC_R_USB_0_PHY + SC_R_UART_1 + SC_R_DMA_0_CH14 + SC_R_DMA_0_CH15 + SC_R_MU_2A + >; + pads = < + /* i2c1_lvds1 */ + SC_P_LVDS1_I2C1_SCL + SC_P_LVDS1_I2C1_SDA + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* usb otg */ + SC_P_USB_SS3_TC0 + /* uart1 */ + SC_P_UART1_RX + SC_P_UART1_TX + SC_P_UART1_CTS_B + SC_P_UART1_RTS_B + SC_P_QSPI1A_DQS + >; + }; + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0xd0000000 0 0x28000000>; + linux,cma-default; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; + + /* Passthrough to domu */ + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + xen,passthrough; + status = "disabled"; + }; + +}; + +&usbotg1_lpcg { + xen,passthrough; +}; + +&sdhc1_lpcg { + xen,passthrough; +}; + +&lpuart1 { + xen,passthrough; +}; + +&lpuart1_lpcg { + xen,passthrough; +}; + +&di_lvds1_lpcg { + xen,passthrough; +}; + +&dc_1_lpcg { + xen,passthrough; +}; + +&edma01 { + #stream-id-cells = <1>; + xen,passthrough; + fsl,sc_rsrc_id = <SC_R_DMA_0_CH14>, + <SC_R_DMA_0_CH15>; +}; + +/* SMMU */ +&smmu { + mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>, + <&usdhc1 0x12>, <&usbotg1 0x11>, + <&edma01 0x10>; +}; + +&lvds_region2 { + xen,passthrough; +}; + +&irqsteer_lvds1 { + xen,passthrough; +}; + +&i2c1_lvds1 { + xen,passthrough; +}; + +&ldb2_phy { + xen,passthrough; +}; + +&ldb2 { + xen,passthrough; +}; + +&crypto { + /* Met CAAM failure on A0, disable it first */ + status = "disabled"; +}; + +&dpu2_intsteer { + xen,passthrough; +}; + +&dpu2 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&prg10 { + xen,passthrough; +}; + +&prg11 { + xen,passthrough; +}; + +&prg12 { + xen,passthrough; +}; + +&prg13 { + xen,passthrough; +}; + +&prg14 { + xen,passthrough; +}; + +&prg15 { + xen,passthrough; +}; + +&prg16 { + xen,passthrough; +}; + +&prg17 { + xen,passthrough; +}; + +&prg18 { + xen,passthrough; +}; + +&dpr3_channel1 { + xen,passthrough; +}; + +&dpr3_channel2 { + xen,passthrough; +}; + +&dpr3_channel3 { + xen,passthrough; +}; + +&dpr4_channel1 { + xen,passthrough; +}; + +&dpr4_channel2 { + xen,passthrough; +}; + +&dpr4_channel3 { + xen,passthrough; +}; + +/* GPU */ +&pd_gpu1 { + xen,passthrough; +}; + +&gpu_3d1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d0>; + /delete-property/ reg; + /delete-property/ reg-names; +}; + +&sata { + status = "disabled"; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbotg1 { + /* Hack reg */ + reg = <0x0 0x5b0d0000 0x0 0x1000>; + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + /* Hack */ + /delete-property/ reg; + status = "disabled"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x1000>; + xen,passthrough; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts new file mode 100644 index 000000000000..ab687ff15f5c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts @@ -0,0 +1,629 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imx8qm-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-lpddr4", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + /delete-node/ aliases; + + aliases { + mmc0 = &usdhc1; + dpu1 = &dpu2; + ldb1 = &ldb2; + serial1 = &lpuart1; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.10", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + /* emmc node which used if androidboot.storage_type=emmc */ + dev_emmc = "/dev/block/platform/passthrough/15b010000.usdhc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + }; + + vbmeta { + /*we need use FirstStageMountVBootV2 if we enable avb*/ + compatible = "android,vbmeta"; + /*parts means the partition witch can be mount in first stage*/ + parts = "vbmeta,boot,system,vendor"; + }; + }; + }; + + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + fsl,lpcg_base_offset = <0x00000001 0x00000000>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + #include "fsl-imx8qm-device.dtsi" + + mu2: mu@15d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x1 0x5d1d0000 0x0 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + usb_lpcg { + reg = <0x1 0x5b270000 0x0 0x10000>; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x1 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x1 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + }; +}; + +/delete-node/ &tsens; +/delete-node/ &thermal_zones; +/delete-node/ &rtc; + +&display { + ports = <&dpu2_disp0>, <&dpu2_disp1>; +}; + +&dpu2_intsteer { + reg = <0x1 0x57000000 0x0 0x10000>; + status = "okay"; +}; + +&prg10 { + reg = <0x1 0x57040000 0x0 0x10000>; + status = "okay"; +}; + +&prg11 { + reg = <0x1 0x57050000 0x0 0x10000>; + status = "okay"; +}; + +&prg12 { + reg = <0x1 0x57060000 0x0 0x10000>; + status = "okay"; +}; + +&prg13 { + reg = <0x1 0x57070000 0x0 0x10000>; + status = "okay"; +}; + +&prg14 { + reg = <0x1 0x57080000 0x0 0x10000>; + status = "okay"; +}; + +&prg15 { + reg = <0x1 0x57090000 0x0 0x10000>; + status = "okay"; +}; + +&prg16 { + reg = <0x1 0x570a0000 0x0 0x10000>; + status = "okay"; +}; + +&prg17 { + reg = <0x1 0x570b0000 0x0 0x10000>; + status = "okay"; +}; + +&prg18 { + reg = <0x1 0x570c0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel1 { + reg = <0x1 0x570d0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel2 { + reg = <0x1 0x570e0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel3 { + reg = <0x1 0x570f0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel1 { + reg = <0x1 0x57100000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel2 { + reg = <0x1 0x57110000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel3 { + reg = <0x1 0x57120000 0x0 0x10000>; + status = "okay"; +}; + +&dpu2 { + reg = <0x1 0x57180000 0x0 0x40000>; + status = "okay"; + + dpu2_disp0: port@0 { + dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { + /delete-property/ remote-endpoint; + }; + }; + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; + }; + }; +}; + +/delete-node/ &hdmi; +/delete-node/ &irqsteer_dsi0; +/delete-node/ &i2c0_mipi_dsi0; +/delete-node/ &mipi_dsi_csr1; +/delete-node/ &mipi_dsi_phy1; +/delete-node/ &mipi_dsi1; +/delete-node/ &mipi_dsi_bridge1; + +&lvds_region2 { + reg = <0x1 0x57240000 0x0 0x10000>; + status = "okay"; +}; + +&ldb2_phy { + reg = <0x1 0x57241000 0x0 0x100>; + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +/delete-node/ &lvds0_pwm; +/delete-node/ &dpu1_intsteer; +/delete-node/ &prg1; +/delete-node/ &prg2; +/delete-node/ &prg3; +/delete-node/ &prg4; +/delete-node/ &prg5; +/delete-node/ &prg6; +/delete-node/ &prg7; +/delete-node/ &prg8; +/delete-node/ &prg9; +/delete-node/ &dpr1_channel1; +/delete-node/ &dpr1_channel2; +/delete-node/ &dpr1_channel3; +/delete-node/ &dpr2_channel1; +/delete-node/ &dpr2_channel2; +/delete-node/ &dpr2_channel3; +/delete-node/ &dpu1; +/delete-node/ &dsp; +/delete-node/ &irqsteer_dsi1; +/delete-node/ &i2c0_mipi_dsi1; +/delete-node/ &mipi_dsi_csr2; +/delete-node/ &mipi_dsi_phy2; +/delete-node/ &mipi_dsi2; +/delete-node/ &mipi_dsi_bridge2; +/delete-node/ &lvds_region1; +/delete-node/ &ldb1_phy; +/delete-node/ &ldb1; +/delete-node/ &lvds1_pwm; +/delete-node/ &camera; +/delete-node/ &adc0; +/delete-node/ &adc1; +/delete-node/ &i2c0; +/delete-node/ &i2c1; +/delete-node/ &i2c2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c0_cm41; +/delete-node/ &irqsteer_hdmi; +/delete-node/ &i2c0_hdmi; + +&irqsteer_lvds1 { + reg = <0x1 0x57240000 0x0 0x1000>; + /delete-property/ interrupt-parent; + status = "okay"; +}; + +/delete-node/ &flexcan1; +/delete-node/ &flexcan2; +/delete-node/ &flexcan3; + +&i2c1_lvds1 { + reg = <0x1 0x57247000 0x0 0x1000>; + status = "okay"; +}; + +/delete-node/ &irqsteer_lvds0; +/delete-node/ &i2c1_lvds0; +/delete-node/ &irqsteer_csi0; +/delete-node/ &i2c0_mipi_csi0; +/delete-node/ &irqsteer_csi1; +/delete-node/ &i2c0_mipi_csi1; +/delete-node/ &lpspi0; +/delete-node/ &lpuart0; + +&lpuart1 { + /delete-property/ interrupt-parent; + reg = <0x1 0x5a070000 0 0x1000>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/delete-node/ &lpuart2; +/delete-node/ &lpuart3; +/delete-node/ &lpuart4; +/delete-node/ &emvsim0; +/delete-node/ &edma0; +/delete-node/ &edma2; +/delete-node/ &edma3; +/delete-node/ &gpio0; +/delete-node/ &gpio1; +/delete-node/ &gpio2; +/delete-node/ &gpio3; +/delete-node/ &gpio4; +/delete-node/ &gpio5; +/delete-node/ &gpio6; +/delete-node/ &gpio7; +/delete-node/ &gpio0_mipi_csi0; +/delete-node/ &gpio0_mipi_csi1; +/delete-node/ &gpt0; +/delete-node/ &pwm0; +/delete-node/ &pwm1; +/delete-node/ &pwm2; +/delete-node/ &pwm3; +/delete-node/ &pwm4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; + +&gpu_3d1 { + reg = <0x0 0x24100000 0 0x40000>; + status = "okay"; +}; + +/delete-node/ &gpu_3d0; + +&imx8_gpu_ss { + /* xen guests have 3GB of low RAM @ 1GB */ + reg = <0x0 0x40000000 0x0 0xc0000000>; + reg-names = "phys_baseaddr"; + cores = <&gpu_3d1>; + status = "okay"; +}; + +/delete-node/ &mlb; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + /*interrupt-parent = <&gic>;*/ + /delete-property/ interrupt-parent; + reg = <0x1 0x5b010000 0x0 0x10000>; +}; + +/delete-node/ &usdhc2; +/delete-node/ &usdhc3; +/delete-node/ &fec1; +/delete-node/ &fec2; + +&usbmisc1 { + reg = <0x1 0x5b0d0200 0x0 0x200>; +}; + +/delete-node/ &usbmisc2; + +&usbphy1 { + reg = <0x1 0x5b100000 0x0 0x200>; +}; + +/delete-node/ &usbh1; +/delete-node/ &usbotg3; +/delete-node/ &usbphynop1; +/delete-node/ &usbphynop2; + +&usbotg1 { + reg = <0x1 0x5b0d0000 0x0 0x200>; + /delete-property/ interrupt-parent; +}; + +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &vpu; +/delete-node/ &acm; +/delete-node/ &esai0; +/delete-node/ &esai1; +/delete-node/ &spdif0; +/delete-node/ &spdif1; +/delete-node/ &sai1; +/delete-node/ &sai0; +/delete-node/ &sai2; +/delete-node/ &sai3; +/delete-node/ &sai_hdmi_rx; +/delete-node/ &sai_hdmi_tx; +/delete-node/ &sai6; +/delete-node/ &sai7; +/delete-node/ &amix; +/delete-node/ &asrc0; +/delete-node/ &asrc1; +/delete-node/ &mqs; +/delete-node/ &flexspi0; + +&dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; +}; + +/delete-node/ &hsio; +/delete-node/ &ocotp; +/delete-node/ &pciea; +/delete-node/ &pcieb; +/delete-node/ &sata; + +/delete-node/ &intmux_cm40; +/delete-node/ &intmux_cm41; +/delete-node/ &imx_rpmsg; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &sc_pwrkey; +/delete-node/ &wdog; +/delete-node/ &wu; + +&iomuxc { + imx8qm-mek { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + >; + }; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts new file mode 100644 index 000000000000..46600260dd41 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai_hdmi_tx>; + protocol = <1>; + hdmi-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&hdmi { + compatible = "fsl,imx8qm-dp"; + fsl,use_digpll_pclock; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts new file mode 100644 index 000000000000..de73e301c452 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dp.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-dp"; + audio-cpu = <&sai_hdmi_tx>; + protocol = <1>; + hdmi-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&hdmi { + compatible = "fsl,imx8qm-dp"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts new file mode 100644 index 000000000000..788ff2cff108 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts new file mode 100644 index 000000000000..42daa8aedb74 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" +#include "fsl-imx8qm-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts new file mode 100644 index 000000000000..2f60845773c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi-in.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2-hdmi.dts" + +/ { + sound-hdmi-rx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-rx"; + audio-cpu = <&sai_hdmi_rx>; + protocol = <1>; + hdmi-in; + }; +}; + +/* HDMI RX */ +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + interface = <4 0 2>; /* <Input MIPI_VCx Output> + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + status = "okay"; +}; + +&isi_2 { + status = "okay"; + fsl,chain_buf; +}; + +&isi_3 { + status = "disabled"; +}; + + +&mipi_csi_0 { + status = "disabled"; +}; + +&i2c0_mipi_csi0 { + status = "disabled"; +}; + +&hdmi_rx { + fsl,cec; + assigned-clocks = <&clk IMX8QM_HDMI_RX_HD_REF_SEL>, + <&clk IMX8QM_HDMI_RX_PXL_SEL>, + <&clk IMX8QM_HDMI_RX_HD_REF_DIV>; + assigned-clock-parents = <&clk IMX8QM_HDMI_RX_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_RX_BYPASS_CLK>; + assigned-clock-rates = <0>, <0>, <400000000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts new file mode 100644 index 000000000000..f01ac9706290 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hdmi.dts @@ -0,0 +1,103 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + protocol = <1>; + hdmi-out; + }; + + sound-amix-sai { + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&sai7 { + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts new file mode 100644 index 000000000000..d2ce4fe3b00d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-hsic.dts @@ -0,0 +1,75 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This dts is only for verify USB HSIC function at i.MX8 Debug Board */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + imx8qm-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_usbh1: PD_USBH1 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_usbh1_io: usbh1_io { + reg = <SC_R_BOARD_R2>; + #power-domain-cells = <0>; + power-domains =<&pd_usbh1>; + }; + }; + }; +}; + +&iomuxc { + imx8qm-arm2 { + pinctrl_usb_hsic_idle: usbh1_1 { + fsl,pins = < + SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0xc60000c5 + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000c5 + >; + }; + + pinctrl_usb_hsic_active: usbh1_2 { + fsl,pins = < + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000d5 + >; + }; + }; +}; + +&usbotg1 { + ci-disable-lpm; +}; + +/* + * Due to USB HSIC uses the same AHB and 480M with USBOTG1, + * the usbotg1 must be enabled for usbh1 usage. + */ +&usbh1 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usb_hsic_idle>; + pinctrl-1 = <&pinctrl_usb_hsic_active>; + power-domains = <&pd_usbh1_io>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts new file mode 100644 index 000000000000..2e9572b4d33b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&ldb1 { + fsl,dual-channel; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb2 { + fsl,dual-channel; +}; + +&i2c1_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..39bbdad2d6f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,71 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&i2c1_lvds1 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts new file mode 100644 index 000000000000..d6d7d770eaee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-lpspi.dts @@ -0,0 +1,54 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&iomuxc { + + imx8qm-arm2 { + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO3_IO05 0x21 + >; + }; + + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <500000>; + reg = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts new file mode 100644 index 000000000000..64d0bb2f77ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts @@ -0,0 +1,198 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + + leds { + status = "disabled"; + }; + + regulators { + + reg_spdif_en: regulator-spdif-en { + compatible = "regulator-fixed"; + regulator-name = "spdif-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_d 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_wm8962: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_bb2: regulator-bb2 { + compatible = "regulator-fixed"; + regulator-name = "bb2-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; + + sound-wm8962 { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&sai0>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + hp-det-gpios = <&gpio5 26 1>; + mic-det-gpios = <&gpio5 27 1>; + codec-master; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + + imx8qm-arm2 { + + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_MQS_L 0xc6000061 + SC_P_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SAI1_RXC_AUD_SAI0_TXD 0xc6000060 + SC_P_SAI1_RXFS_AUD_SAI0_RXD 0xc6000040 + SC_P_SAI1_TXC_AUD_SAI0_TXC 0xc6000040 + SC_P_SPI2_CS1_AUD_SAI0_TXFS 0xc6000040 + + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0xc6000040 + SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 0xc6000040 + SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 0xc6000040 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + }; +}; + +&i2c0 { + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + DCVDD-supply = <®_wm8962>; + DBVDD-supply = <®_wm8962>; + AVDD-supply = <®_wm8962>; + CPVDD-supply = <®_wm8962>; + MICVDD-supply = <®_wm8962>; + PLLVDD-supply = <®_wm8962>; + SPKVDD1-supply = <®_wm8962>; + SPKVDD2-supply = <®_wm8962>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + power-domains = <&pd_mclk_out0>; + }; +}; + + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + status = "disabled"; +}; + +&sai1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts new file mode 100644 index 000000000000..8125de8f0579 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts @@ -0,0 +1,205 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + + leds { + status = "disabled"; + }; + + regulators { + + reg_spdif_en: regulator-spdif-en { + compatible = "regulator-fixed"; + regulator-name = "spdif-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_d 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_wm8962: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + reg_bb2: regulator-bb2 { + compatible = "regulator-fixed"; + regulator-name = "bb2-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + sound-mqs { + compatible = "fsl,imx8qm-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&sai0>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + hp-det-gpios = <&gpio5 26 1>; + mic-det-gpios = <&gpio5 27 1>; + codec-master; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + + imx8qm-arm2 { + + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_MQS_L 0xc6000061 + SC_P_SPDIF0_RX_AUD_MQS_R 0xc6000061 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SAI1_RXC_AUD_SAI0_TXD 0xc6000060 + SC_P_SAI1_RXFS_AUD_SAI0_RXD 0xc6000040 + SC_P_SAI1_TXC_AUD_SAI0_TXC 0xc6000040 + SC_P_SPI2_CS1_AUD_SAI0_TXFS 0xc6000040 + + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0xc6000040 + SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 0xc6000040 + SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 0xc6000040 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&i2c0 { + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + DCVDD-supply = <®_wm8962>; + DBVDD-supply = <®_wm8962>; + AVDD-supply = <®_wm8962>; + CPVDD-supply = <®_wm8962>; + MICVDD-supply = <®_wm8962>; + PLLVDD-supply = <®_wm8962>; + SPKVDD1-supply = <®_wm8962>; + SPKVDD2-supply = <®_wm8962>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + power-domains = <&pd_mclk_out0>; + }; +}; + + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "disabled"; +}; + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts new file mode 100644 index 000000000000..f1f7538bb719 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-usb3.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This dts is only for verify USB3 Type-C Connector */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +/ { + imx8qm-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_ptn5150: PD_PTN5150 { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_ptn5150_io: ptn5150_io { + reg = <SC_R_BOARD_R0>; + #power-domain-cells = <0>; + power-domains =<&pd_ptn5150>; + }; + }; + }; +}; + + + +&iomuxc { + imx8qm-arm2 { + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC1_DMA_I2C1_SCL 0xc600004c + SC_P_USB_SS3_TC3_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_ptn5150: ptn5150 { + fsl,pins = < + SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 + >; + }; + }; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + power-domains = <&pd_ptn5150_io>; + connect-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + pca9557_a: gpio@18 { + status = "disabled"; + }; + + pca9557_b: gpio@19 { + status = "disabled"; + }; + + pca9557_c: gpio@1b { + status = "disabled"; + }; + + pca9557_d: gpio@1f { + status = "disabled"; + }; + + fxas2100x@20 { + status = "disabled"; + }; + + fxos8700@1d { + status = "disabled"; + }; + + isl29023@44 { + status = "disabled"; + }; + + mpl3115@60 { + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts new file mode 100644 index 000000000000..9e79cd282600 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" +#include "fsl-imx8q-arm2.dtsi" + +/ { + model = "Freescale i.MX8QM LPDDR4 ARM2"; + compatible = "fsl,imx8qm-lpddr4-arm2", "fsl,imx8qm"; +}; + +&vpu_decoder { + core_type = <2>; + status = "okay"; +}; + +&vpu_encoder { + core_type = <2>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts new file mode 100644 index 000000000000..9c42d98899b0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca53.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&A72_0 { + device_type = ""; +}; + +&A72_1 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts new file mode 100644 index 000000000000..55e2e8c51637 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2_ca72.dts @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-lpddr4-arm2.dts" + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-8cam.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-8cam.dts new file mode 100644 index 000000000000..3ae1956a3b28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-8cam.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * MIPI CSI-2 eight cameras dts, + * One MIPI CSI-2 controller connected four cameras + * The first four cameras have enabled in mipi_csi_0. + * Enable the last four cameras in mipi_csi_1 here. + */ + +#include "fsl-imx8qm-mek.dts" + +&mipi_csi_1 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts new file mode 100644 index 000000000000..d4ae5b31fe28 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts @@ -0,0 +1,331 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" +#include "fsl-imx8qm-xen.dtsi" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + + /* Could be updated by U-Boot */ + module@0 { + bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; + + domu { + /* + * There are 5 MUs, 0A is used by Dom0, 1A is used + * by ATF, so for DomU, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + compatible = "xen,domu"; + /* + * The name entry in VM configuration file + * needs to be same as here. + */ + domain_name = "DomU"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_GPU_1_PID0 + SC_R_GPU_1_PID1 + SC_R_GPU_1_PID2 + SC_R_GPU_1_PID3 + SC_R_LVDS_1 + SC_R_LVDS_1_I2C_0 + SC_R_LVDS_1_PWM_0 + SC_R_DC_1 + SC_R_DC_1_BLIT0 + SC_R_DC_1_BLIT1 + SC_R_DC_1_BLIT2 + SC_R_DC_1_BLIT_OUT + SC_R_DC_1_CAPTURE0 + SC_R_DC_1_CAPTURE1 + SC_R_DC_1_WARP + SC_R_DC_1_INTEGRAL0 + SC_R_DC_1_INTEGRAL1 + SC_R_DC_1_VIDEO0 + SC_R_DC_1_VIDEO1 + SC_R_DC_1_FRAC0 + SC_R_DC_1_FRAC1 + SC_R_DC_1_PLL_0 + SC_R_DC_1_PLL_1 + SC_R_MIPI_1 + SC_R_MIPI_1_I2C_0 + SC_R_MIPI_1_I2C_1 + SC_R_MIPI_1_PWM_0 + SC_R_HDMI + SC_R_HDMI_I2C_0 + SC_R_SDHC_0 + SC_R_USB_0 + SC_R_USB_0_PHY + SC_R_UART_1 + SC_R_DMA_0_CH14 + SC_R_DMA_0_CH15 + SC_R_MU_2A + >; + pads = < + /* i2c1_lvds1 */ + SC_P_LVDS1_I2C1_SCL + SC_P_LVDS1_I2C1_SDA + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* usb otg */ + SC_P_USB_SS3_TC0 + /* uart1 */ + SC_P_UART1_RX + SC_P_UART1_TX + SC_P_UART1_CTS_B + SC_P_UART1_RTS_B + SC_P_QSPI1A_DQS + >; + }; + }; + + reserved-memory { + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0xd0000000 0 0x28000000>; + linux,cma-default; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>; + }; + + /* Passthrough to domu */ + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + xen,passthrough; + status = "disabled"; + }; + +}; + +&usbotg1_lpcg { + xen,passthrough; +}; + +&sdhc1_lpcg { + xen,passthrough; +}; + +&lpuart1 { + xen,passthrough; +}; + +&lpuart1_lpcg { + xen,passthrough; +}; + +&di_lvds1_lpcg { + xen,passthrough; +}; + +&dc_1_lpcg { + xen,passthrough; +}; + +&edma01 { + #stream-id-cells = <1>; + xen,passthrough; + fsl,sc_rsrc_id = <SC_R_DMA_0_CH14>, + <SC_R_DMA_0_CH15>; +}; + +/* SMMU */ +&smmu { + mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>, + <&usdhc1 0x12>, <&usbotg1 0x11>, + <&edma01 0x10>; +}; + +&lvds_region2 { + xen,passthrough; +}; + +&irqsteer_lvds1 { + xen,passthrough; +}; + +&i2c1_lvds1 { + xen,passthrough; +}; + +&ldb2_phy { + xen,passthrough; +}; + +&ldb2 { + xen,passthrough; +}; + +&crypto { + /* Met CAAM failure on A0, disable it first */ + status = "disabled"; +}; + +&dpu2_intsteer { + xen,passthrough; +}; + +&dpu2 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&prg10 { + xen,passthrough; +}; + +&prg11 { + xen,passthrough; +}; + +&prg12 { + xen,passthrough; +}; + +&prg13 { + xen,passthrough; +}; + +&prg14 { + xen,passthrough; +}; + +&prg15 { + xen,passthrough; +}; + +&prg16 { + xen,passthrough; +}; + +&prg17 { + xen,passthrough; +}; + +&prg18 { + xen,passthrough; +}; + +&dpr3_channel1 { + xen,passthrough; +}; + +&dpr3_channel2 { + xen,passthrough; +}; + +&dpr3_channel3 { + xen,passthrough; +}; + +&dpr4_channel1 { + xen,passthrough; +}; + +&dpr4_channel2 { + xen,passthrough; +}; + +&dpr4_channel3 { + xen,passthrough; +}; + +/* GPU */ +&pd_gpu1 { + xen,passthrough; +}; + +&gpu_3d1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&imx8_gpu_ss { + cores = <&gpu_3d0>; + /delete-property/ reg; + /delete-property/ reg-names; +}; + +&sata { + status = "disabled"; +}; + +&usdhc1 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbotg1 { + /* Hack reg */ + reg = <0x0 0x5b0d0000 0x0 0x1000>; + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; +}; + +&usbmisc1 { + /* Hack */ + /delete-property/ reg; + status = "disabled"; +}; + +&usbphy1 { + reg = <0x0 0x5b100000 0x0 0x1000>; + xen,passthrough; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts new file mode 100644 index 000000000000..8bd72c656281 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -0,0 +1,629 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imx8qm-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QM DOMU"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + /delete-node/ aliases; + + aliases { + mmc0 = &usdhc1; + dpu1 = &dpu2; + ldb1 = &ldb2; + serial1 = &lpuart1; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "hvc"; + }; + + memory@80000000 { + device_type = "memory"; + /* Will be updated by U-Boot or XEN TOOL */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + gic: interrupt-controller@3001000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0x0>; + interrupt-controller; + redistributor-stride = <0x20000>; + #redistributor-regions = <0x1>; + reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ + <0x0 0x3020000 0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + clock-frequency = <8000000>; + }; + + hypervisor { + compatible = "xen,xen-4.10", "xen,xen"; + reg = <0x0 0x38000000 0x0 0x1000000>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + }; + + passthrough { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + /* emmc node which used if androidboot.storage_type=emmc */ + dev_emmc = "/dev/block/platform/passthrough/15b010000.usdhc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + }; + + vbmeta { + /*we need use FirstStageMountVBootV2 if we enable avb*/ + compatible = "android,vbmeta"; + /*parts means the partition witch can be mount in first stage*/ + parts = "vbmeta,boot,system,vendor"; + }; + }; + }; + + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + fsl,lpcg_base_offset = <0x00000001 0x00000000>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + #include "fsl-imx8qm-device.dtsi" + + mu2: mu@15d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x1 0x5d1d0000 0x0 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + usb_lpcg { + reg = <0x1 0x5b270000 0x0 0x10000>; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x1 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x1 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + }; +}; + +/delete-node/ &tsens; +/delete-node/ &thermal_zones; +/delete-node/ &rtc; + +&display { + ports = <&dpu2_disp0>, <&dpu2_disp1>; +}; + +&dpu2_intsteer { + reg = <0x1 0x57000000 0x0 0x10000>; + status = "okay"; +}; + +&prg10 { + reg = <0x1 0x57040000 0x0 0x10000>; + status = "okay"; +}; + +&prg11 { + reg = <0x1 0x57050000 0x0 0x10000>; + status = "okay"; +}; + +&prg12 { + reg = <0x1 0x57060000 0x0 0x10000>; + status = "okay"; +}; + +&prg13 { + reg = <0x1 0x57070000 0x0 0x10000>; + status = "okay"; +}; + +&prg14 { + reg = <0x1 0x57080000 0x0 0x10000>; + status = "okay"; +}; + +&prg15 { + reg = <0x1 0x57090000 0x0 0x10000>; + status = "okay"; +}; + +&prg16 { + reg = <0x1 0x570a0000 0x0 0x10000>; + status = "okay"; +}; + +&prg17 { + reg = <0x1 0x570b0000 0x0 0x10000>; + status = "okay"; +}; + +&prg18 { + reg = <0x1 0x570c0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel1 { + reg = <0x1 0x570d0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel2 { + reg = <0x1 0x570e0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr3_channel3 { + reg = <0x1 0x570f0000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel1 { + reg = <0x1 0x57100000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel2 { + reg = <0x1 0x57110000 0x0 0x10000>; + status = "okay"; +}; + +&dpr4_channel3 { + reg = <0x1 0x57120000 0x0 0x10000>; + status = "okay"; +}; + +&dpu2 { + reg = <0x1 0x57180000 0x0 0x40000>; + status = "okay"; + + dpu2_disp0: port@0 { + dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { + /delete-property/ remote-endpoint; + }; + }; + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: lvds0-endpoint { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: lvds1-endpoint { + remote-endpoint = <&ldb2_lvds1>; + }; + }; +}; + +/delete-node/ &hdmi; +/delete-node/ &irqsteer_dsi0; +/delete-node/ &i2c0_mipi_dsi0; +/delete-node/ &mipi_dsi_csr1; +/delete-node/ &mipi_dsi_phy1; +/delete-node/ &mipi_dsi1; +/delete-node/ &mipi_dsi_bridge1; + +&lvds_region2 { + reg = <0x1 0x57240000 0x0 0x10000>; + status = "okay"; +}; + +&ldb2_phy { + reg = <0x1 0x57241000 0x0 0x100>; + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +/delete-node/ &lvds0_pwm; +/delete-node/ &dpu1_intsteer; +/delete-node/ &prg1; +/delete-node/ &prg2; +/delete-node/ &prg3; +/delete-node/ &prg4; +/delete-node/ &prg5; +/delete-node/ &prg6; +/delete-node/ &prg7; +/delete-node/ &prg8; +/delete-node/ &prg9; +/delete-node/ &dpr1_channel1; +/delete-node/ &dpr1_channel2; +/delete-node/ &dpr1_channel3; +/delete-node/ &dpr2_channel1; +/delete-node/ &dpr2_channel2; +/delete-node/ &dpr2_channel3; +/delete-node/ &dpu1; +/delete-node/ &dsp; +/delete-node/ &irqsteer_dsi1; +/delete-node/ &i2c0_mipi_dsi1; +/delete-node/ &mipi_dsi_csr2; +/delete-node/ &mipi_dsi_phy2; +/delete-node/ &mipi_dsi2; +/delete-node/ &mipi_dsi_bridge2; +/delete-node/ &lvds_region1; +/delete-node/ &ldb1_phy; +/delete-node/ &ldb1; +/delete-node/ &lvds1_pwm; +/delete-node/ &camera; +/delete-node/ &adc0; +/delete-node/ &adc1; +/delete-node/ &i2c0; +/delete-node/ &i2c1; +/delete-node/ &i2c2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &i2c0_cm40; +/delete-node/ &i2c0_cm41; +/delete-node/ &irqsteer_hdmi; +/delete-node/ &i2c0_hdmi; + +&irqsteer_lvds1 { + reg = <0x1 0x57240000 0x0 0x1000>; + /delete-property/ interrupt-parent; + status = "okay"; +}; + +/delete-node/ &flexcan1; +/delete-node/ &flexcan2; +/delete-node/ &flexcan3; + +&i2c1_lvds1 { + reg = <0x1 0x57247000 0x0 0x1000>; + status = "okay"; +}; + +/delete-node/ &irqsteer_lvds0; +/delete-node/ &i2c1_lvds0; +/delete-node/ &irqsteer_csi0; +/delete-node/ &i2c0_mipi_csi0; +/delete-node/ &irqsteer_csi1; +/delete-node/ &i2c0_mipi_csi1; +/delete-node/ &lpspi0; +/delete-node/ &lpuart0; + +&lpuart1 { + /delete-property/ interrupt-parent; + reg = <0x1 0x5a070000 0 0x1000>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +/delete-node/ &lpuart2; +/delete-node/ &lpuart3; +/delete-node/ &lpuart4; +/delete-node/ &emvsim0; +/delete-node/ &edma0; +/delete-node/ &edma2; +/delete-node/ &edma3; +/delete-node/ &gpio0; +/delete-node/ &gpio1; +/delete-node/ &gpio2; +/delete-node/ &gpio3; +/delete-node/ &gpio4; +/delete-node/ &gpio5; +/delete-node/ &gpio6; +/delete-node/ &gpio7; +/delete-node/ &gpio0_mipi_csi0; +/delete-node/ &gpio0_mipi_csi1; +/delete-node/ &gpt0; +/delete-node/ &pwm0; +/delete-node/ &pwm1; +/delete-node/ &pwm2; +/delete-node/ &pwm3; +/delete-node/ &pwm4; +/delete-node/ &pwm5; +/delete-node/ &pwm6; +/delete-node/ &pwm7; + +&gpu_3d1 { + reg = <0x0 0x24100000 0 0x40000>; + status = "okay"; +}; + +/delete-node/ &gpu_3d0; + +&imx8_gpu_ss { + /* xen guests have 3GB of low RAM @ 1GB */ + reg = <0x0 0x40000000 0x0 0xc0000000>; + reg-names = "phys_baseaddr"; + cores = <&gpu_3d1>; + status = "okay"; +}; + +/delete-node/ &mlb; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + /*interrupt-parent = <&gic>;*/ + /delete-property/ interrupt-parent; + reg = <0x1 0x5b010000 0x0 0x10000>; +}; + +/delete-node/ &usdhc2; +/delete-node/ &usdhc3; +/delete-node/ &fec1; +/delete-node/ &fec2; + +&usbmisc1 { + reg = <0x1 0x5b0d0200 0x0 0x200>; +}; + +/delete-node/ &usbmisc2; + +&usbphy1 { + reg = <0x1 0x5b100000 0x0 0x200>; +}; + +/delete-node/ &usbh1; +/delete-node/ &usbotg3; +/delete-node/ &usbphynop1; +/delete-node/ &usbphynop2; + +&usbotg1 { + reg = <0x1 0x5b0d0000 0x0 0x200>; + /delete-property/ interrupt-parent; +}; + +/delete-node/ &ddr_pmu0; +/delete-node/ &ddr_pmu1; +/delete-node/ &vpu; +/delete-node/ &acm; +/delete-node/ &esai0; +/delete-node/ &esai1; +/delete-node/ &spdif0; +/delete-node/ &spdif1; +/delete-node/ &sai1; +/delete-node/ &sai0; +/delete-node/ &sai2; +/delete-node/ &sai3; +/delete-node/ &sai_hdmi_rx; +/delete-node/ &sai_hdmi_tx; +/delete-node/ &sai6; +/delete-node/ &sai7; +/delete-node/ &amix; +/delete-node/ &asrc0; +/delete-node/ &asrc1; +/delete-node/ &mqs; +/delete-node/ &flexspi0; + +&dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; +}; + +/delete-node/ &hsio; +/delete-node/ &ocotp; +/delete-node/ &pciea; +/delete-node/ &pcieb; +/delete-node/ &sata; + +/delete-node/ &intmux_cm40; +/delete-node/ &intmux_cm41; +/delete-node/ &imx_rpmsg; +/delete-node/ &crypto; +/delete-node/ &caam_sm; +/delete-node/ &sc_pwrkey; +/delete-node/ &wdog; +/delete-node/ &wu; + +&iomuxc { + imx8qm-mek { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + >; + }; + }; +}; + +&usdhc1 { + /delete-property/ iommus; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..4ce6121f1437 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsi-rm67191.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; + reset-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..817bb62df06a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" +#include "fsl-imx8qm-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts new file mode 100644 index 000000000000..0daadcb12e0a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi-in.dts @@ -0,0 +1,69 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI IN only dts. + */ + +#include "fsl-imx8qm-mek-hdmi.dts" + +/ { + sound-hdmi-rx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-rx"; + audio-cpu = <&sai_hdmi_rx>; + protocol = <1>; + hdmi-in; + }; +}; + +/* HDMI RX */ +&isi_0 { + status = "disabled"; +}; + +&isi_1 { + interface = <4 0 2>; /* <Input MIPI_VCx Output> + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + status = "okay"; +}; + +&isi_2 { + status = "okay"; + fsl,chain_buf; +}; + +&isi_3 { + status = "disabled"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&i2c0_mipi_csi0 { + status = "disabled"; +}; + +&hdmi_rx { + fsl,cec; + assigned-clocks = <&clk IMX8QM_HDMI_RX_HD_REF_SEL>, + <&clk IMX8QM_HDMI_RX_PXL_SEL>, + <&clk IMX8QM_HDMI_RX_HD_REF_DIV>; + assigned-clock-parents = <&clk IMX8QM_HDMI_RX_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_RX_BYPASS_CLK>; + assigned-clock-rates = <0>, <0>, <400000000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts new file mode 100644 index 000000000000..324ff44940e2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts @@ -0,0 +1,102 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * HDMI only dts, disable ldb display. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi-tx"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + protocol = <1>; + hdmi-out; + }; + + sound-amix-sai { + status = "disabled"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + fsl,cec; + status = "okay"; +}; + +&amix { + status = "disabled"; +}; + +&sai6 { + status = "disabled"; +}; + +&sai7 { + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "okay"; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts new file mode 100644 index 000000000000..87da05ecb454 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts @@ -0,0 +1,285 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "fsl-imx8-ca35.dtsi" +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/clock/imx8qm-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + imx8qx-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = <SC_R_SDHC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma0_chan16: PD_UART2_RX { + reg = <SC_R_DMA_0_CH16>; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan17: PD_UART2_TX { + reg = <SC_R_DMA_0_CH17>; + power-domains =<&pd_dma0_chan16>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + pci@ff700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xff700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, + <&clk IMX8QM_SDHC0_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + /*iommus = <&smmu 0x11 0x7f80>;*/ + status = "disabled"; + }; + + /* For early console */ + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan17>; + /* + * dma-names = "tx","rx"; + * dmas = <&edma0 17 0 0>, + * <&edma0 16 0 1>; + */ + status = "disabled"; + }; +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020 + SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..8c4d450c775a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,71 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&i2c1_lvds0 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&i2c1_lvds1 { + lvds-to-hdmi-bridge@4c { + status = "disabled"; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + fsl,dual-channel; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-mipi-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-mipi-ov5640.dts new file mode 100644 index 000000000000..9e4c8e0e77b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-mipi-ov5640.dts @@ -0,0 +1,84 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&iomuxc { + imx8qm-mek { + pinctrl_mipi_csi0: mipicsi0grp{ + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&i2c0_mipi_csi0 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-mipi-two-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-mipi-two-ov5640.dts new file mode 100644 index 000000000000..87e0a576ded7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-mipi-two-ov5640.dts @@ -0,0 +1,73 @@ + +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek-mipi-ov5640.dts" + +&iomuxc { + imx8qm-mek { + pinctrl_mipi_csi1: mipicsi1grp{ + fsl,pins = < + SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + }; +}; + +&isi_4 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <1>; + pwn-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep_1: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_1 { + /delete-property/virtual-channel; + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep_1>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts new file mode 100644 index 000000000000..e28fd5ffa399 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_SDHC_0 + SC_R_DMA_0_CH16 + SC_R_DMA_0_CH17 + SC_R_UART_2 + SC_R_MU_2A + >; + pads = < + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + SC_P_EMMC0_RESET_B + /* lpuart2 */ + SC_P_UART0_RTS_B + SC_P_UART0_CTS_B + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@0xffc00000 { + no-map; + reg = <0x0 0xffc00000 0x0 0x400000>; + }; + + loader_reserved: loader@0xffb00000 { + no-map; + reg = <0x0 0xffb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xff900000 { + no-map; + reg = <0x0 0xff900000 0x0 0x00200000>; + }; + + pci_reserved: pci@0xff700000 { + no-map; + reg = <0x0 0xff700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@0xdf7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x20000000>; + }; +}; + +&smmu { + /* Jailhouse hypervisor will initialize SMMU and use it. */ + status = "disabled"; +}; + +&usdhc1 { + /* Let U-Boot program SID */ + iommus = <&smmu 0x10 0x7f80>; + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts new file mode 100644 index 000000000000..507509a2d409 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts @@ -0,0 +1,1435 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio4 9 0>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <4800>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vref_1v8: adc_vref_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + sound: sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai6>, <&sai7>; + amix-controller = <&amix>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&lvds0_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&lvds1_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + SC_P_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + + pinctrl_cm41_i2c0: cm41i2c0grp { + fsl,pins = < + SC_P_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + SC_P_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020 + SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + SC_P_SAI1_RXC_AUD_SAI1_RXC 0x06000040 + SC_P_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040 + SC_P_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + SC_P_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x04000021 + >; + }; + + pinctrl_sim0: sim0grp { + fsl,pins = < + SC_P_SIM0_CLK_DMA_SIM0_CLK 0x21 + SC_P_SIM0_IO_DMA_SIM0_IO 0x21 + SC_P_SIM0_PD_DMA_SIM0_PD 0x21 + SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0x21 + SC_P_SIM0_RST_DMA_SIM0_RST 0x21 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_gpio1: mipi_csi_en_rst{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000021 + SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000021 + SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0x00000021 + >; + }; + + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + +&emvsim0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim0>; + pinctrl-1 = <&pinctrl_sim0>; + status = "okay"; +}; +&sai1 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_1_MCLK>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5110>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio4>; + interrupts = <11 2>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + interrupt-open-drain; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&i2c0_cm41 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c0>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&gpio4 25 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + status = "okay"; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { /* Dbg console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "disabled"; +}; + +&lpuart3 { /* MKbus */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + status = "okay"; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&sata { + pinctrl-0 = <&pinctrl_pciea>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&i2c0_mipi_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_adv: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&i2c0_mipi_dsi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_adv: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&lvds0_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_pwm0>; + status = "okay"; +}; + +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_pwm0>; + status = "okay"; +}; + +&tsens { + tsens-num = <6>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 5>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&pmic_alert0>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts new file mode 100644 index 000000000000..5c8c4f499948 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca53.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&A72_0 { + device_type = ""; +}; + +&A72_1 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts new file mode 100644 index 000000000000..fa2ff24c51ce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek_ca72.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi new file mode 100644 index 000000000000..984e40cd5ef3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi @@ -0,0 +1,226 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This dtsi is used by dom0 mainly for passthrough devices to domu. + */ +/ { + /delete-node/ thermal-zones; + + /delete-node/ wu; + + edma00: dma-controller0@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx"; + status = "okay"; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + + edma02: dma-controller2@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx"; + status = "okay"; + }; + + edma03: dma-controller3@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx"; + status = "okay"; + }; + + edma04: dma-controller4@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx"; + status = "okay"; + }; + + usbotg1_lpcg: usbotg1_lpcg@5b270000 { + compatible = "fsl,imx8qm-usbotg1-lpcg"; + reg = <0x0 0x5b270000 0x0 0x10000>; + }; + + sdhc1_lpcg: sdhc1_lpcg@5b200000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5b200000 0x0 0x10000>; + }; + + lpuart1_lpcg: lpcg@5a470000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5a470000 0x0 0x10000>; + }; + + di_lvds0_lpcg: lpcg@56243000 { + compatible = "fsl,imx8qm-di-lvds0-lpcg"; + reg = <0x0 0x56243000 0x0 0x1000>; + }; + + di_lvds1_lpcg: lpcg@57243000 { + compatible = "fsl,imx8qm-di-lvds1-lpcg"; + reg = <0x0 0x57243000 0x0 0x1000>; + }; + + dc_0_lpcg: lpcg@56010000 { + compatible = "fsl,imx8qm-dc0-lpcg"; + reg = <0x0 0x56010000 0x0 0x10000>; + }; + + dc_1_lpcg: lpcg@57010000 { + compatible = "fsl,imx8qm-dc1-lpcg"; + reg = <0x0 0x57010000 0x0 0x10000>; + }; +}; + +/delete-node/ &edma0; + +&mu { + interrupt-parent = <&gic>; +}; + +&flexcan1 { + interrupt-parent = <&gic>; +}; + +&flexcan2 { + interrupt-parent = <&gic>; +}; + +&flexcan3 { + interrupt-parent = <&gic>; +}; + +&lpuart0 { + interrupt-parent = <&gic>; +}; + +&lpuart1 { + interrupt-parent = <&gic>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; +}; + +&lpuart2 { + interrupt-parent = <&gic>; + dmas = <&edma02 17 0 0>, <&edma02 16 0 1>; +}; + +&lpuart3 { + interrupt-parent = <&gic>; + dmas = <&edma03 19 0 0>, <&edma03 18 0 1>; +}; + +&lpuart4 { + interrupt-parent = <&gic>; + dmas = <&edma04 21 0 0>, <&edma04 20 0 1>; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&fec1 { + interrupt-parent = <&gic>; + /delete-property/ iommus; +}; + +&fec2 { + interrupt-parent = <&gic>; + /delete-property/ iommus; +}; + +&sata { + /delete-property/ iommus; +}; + +&usbotg1 { + interrupt-parent = <&gic>; +}; + +&usbh1 { + interrupt-parent = <&gic>; +}; + +&usbotg3 { + interrupt-parent = <&gic>; +}; + +&smmu { + /* xen only supports legacy bindings for now */ + #iommu-cells = <0>; +}; + +&dpu1 { + fsl,sc_rsrc_id = <SC_R_DC_0_BLIT0>, + <SC_R_DC_0_BLIT1>, + <SC_R_DC_0_BLIT2>, + <SC_R_DC_0_BLIT_OUT>, + <SC_R_DC_0_WARP>, + <SC_R_DC_0_VIDEO0>, + <SC_R_DC_0_VIDEO1>, + <SC_R_DC_0_FRAC0>, + <SC_R_DC_0>; +}; + +&dpu2 { + fsl,sc_rsrc_id = <SC_R_DC_1_BLIT0>, + <SC_R_DC_1_BLIT1>, + <SC_R_DC_1_BLIT2>, + <SC_R_DC_1_BLIT_OUT>, + <SC_R_DC_1_WARP>, + <SC_R_DC_1_VIDEO0>, + <SC_R_DC_1_VIDEO1>, + <SC_R_DC_1_FRAC0>, + <SC_R_DC_1>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi new file mode 100644 index 000000000000..f22321279c17 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "fsl-imx8-ca53.dtsi" +#include "fsl-imx8-ca72.dtsi" +#include <dt-bindings/clock/imx8qm-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi0 = &mipi_csi_0; + csi1 = &mipi_csi_1; + dpu0 = &dpu1; + dpu1 = &dpu2; + ethernet0 = &fec1; + ethernet1 = &fec2; + dsi_phy0 = &mipi_dsi_phy1; + dsi_phy1 = &mipi_dsi_phy2; + mipi_dsi0 = &mipi_dsi1; + mipi_dsi1 = &mipi_dsi2; + ldb0 = &ldb1; + ldb1 = &ldb2; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + usbphy0 = &usbphy1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x2000000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + + decoder_rpc: decoder_rpc@0x90400000 { + no-map; + reg = <0 0x90400000 0 0x1000000>; + }; + encoder_rpc: encoder_rpc@0x91400000 { + no-map; + reg = <0 0x91400000 0 0x1000000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + + decoder_str: str@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x1800000>; + }; + + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x96000000 0 0x28000000>; + linux,cma-default; + }; + + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + mu: mu@5d1c0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1c0000 0x0 0x10000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x10000>; + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; + }; + mu2_m0: mu2_m0@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x0 0x2d040000 0x0 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + status = "okay"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + str-region = <&decoder_str>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reg = <0x0 0x2d000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + power-domains = <&pd_vpu_enc>; + status = "disabled"; + }; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + + cci: cci@52090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x52090000 0 0x1000>; + ranges = <0 0 0x52090000 0x10000>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1", + "arm,cci-400-pmu"; + reg = <0x9000 0x4000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + }; + + #include "fsl-imx8qm-device.dtsi" +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 1104000 0 + 900000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A53_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; + +&A72_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1596000 0 + 1296000 0 + 1056000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A72_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; + +&imx8_gpu_ss {/*<freq-kHz vol-uV>*/ + operating-points = < +/*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/ + 1000000 0 /*The second tuple is for shader clock frequency*/ +/*nominal*/ 650000 0 + 700000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts new file mode 100644 index 000000000000..969869097ed5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qp.dtsi" + +#include "fsl-imx8q-arm2.dtsi" + +/ { + model = "Freescale i.MX8QP ARM2"; + compatible = "fsl,imx8qp-arm2", "fsl,imx8qp", "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi new file mode 100644 index 000000000000..97793d66ef23 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QP"; + compatible = "fsl,imx8qp", "fsl,imx8qm"; + + pmu { + interrupt-affinity = <&A72_0>; + }; +}; + +/delete-node/ &A72_1; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&gpu_3d1 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&imx8_gpu_ss {/*<freq-kHz vol-uV>*/ + operating-points = < + /*nominal*/ 625000 0 + 625000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi new file mode 100644 index 000000000000..b664c6f8a215 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-0 = <&pinctrl_fec2_rmii>; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, + <&clk IMX8QXP_ENET1_AHB_CLK>, + <&clk IMX8QXP_ENET1_REF_50MHZ_CLK>, + <&clk IMX8QXP_ENET1_PTP_CLK>, + <&clk IMX8QXP_ENET1_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + /delete-property/ phy-supply; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + tja110x,refclk_in; + }; + }; +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_fec2_rmii: fec2rmiigrp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT 0x06000020 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x06000020 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020 + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts new file mode 100644 index 000000000000..264ae77ddbb7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-a0.dts @@ -0,0 +1,24 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts new file mode 100644 index 000000000000..414cd3231f32 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dts @@ -0,0 +1,61 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts new file mode 100644 index 000000000000..f45a85a736d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2-enet2.dts" +#include "fsl-imx8qxp-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts new file mode 100644 index 000000000000..2c9f5b188470 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-enet2.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts new file mode 100644 index 000000000000..d1165640116b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts @@ -0,0 +1,67 @@ +/* + * Copyright 2017 NXP + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&iomuxc { + imx8qxp-zebu { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + SC_P_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + SC_P_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + SC_P_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + SC_P_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts new file mode 100644 index 000000000000..2fddbdf79359 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-lpspi.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&iomuxc { + + imx8qxp-arm2 { + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_ADMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_ADMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_ADMA_SPI0_SDI 0x0600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <500000>; + reg = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts new file mode 100644 index 000000000000..14d164f21c5f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mlb.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +&esai0 { + status = "disabled"; +}; + +&mlb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts new file mode 100644 index 000000000000..17abb9bc5b67 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-mqs.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + + imx8qxp-arm2 { + pinctrl_mqs: mqsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_ADMA_MQS_L 0xc6000061 + SC_P_SPDIF0_RX_ADMA_MQS_R 0xc6000061 + >; + }; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts new file mode 100644 index 000000000000..c6622623101b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-spdif.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + + imx8qxp-arm2 { + + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; + + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts new file mode 100644 index 000000000000..8f39af831aef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-lpddr4-arm2.dts" + +/ { + regulators { + reg_wm8962: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + }; + + sound-cs42888 { + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&sai0>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "Playback", "CPU-Playback", + "CPU-Capture", "Capture"; + codec-master; + hp-det-gpios = <&gpio1 2 1>; + mic-det-gpios = <&gpio1 3 1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + imx8qxp-lpddr4-arm2 { + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SAI0_TXFS_ADMA_SAI0_TXFS 0xc6000040 + SC_P_SAI0_TXC_ADMA_SAI0_TXC 0xc6000040 + SC_P_SAI0_TXD_ADMA_SAI0_TXD 0xc6000060 + SC_P_SAI0_RXD_ADMA_SAI0_RXD 0xc6000040 + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0xc6000040 + SC_P_SPI2_SDI_LSIO_GPIO1_IO02 0xc6000040 + SC_P_SPI2_SCK_LSIO_GPIO1_IO03 0xc6000040 + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + }; +}; + +&i2c0_csi0 { + + wm8962: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + DCVDD-supply = <®_wm8962>; + DBVDD-supply = <®_wm8962>; + AVDD-supply = <®_wm8962>; + CPVDD-supply = <®_wm8962>; + MICVDD-supply = <®_wm8962>; + PLLVDD-supply = <®_wm8962>; + SPKVDD1-supply = <®_wm8962>; + SPKVDD2-supply = <®_wm8962>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + amic-mono; + power-domains = <&pd_mclk_out0>; + }; +}; + +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts new file mode 100644 index 000000000000..db6c7a40efd3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +#include "fsl-imx8x-arm2.dtsi" + +/ { + model = "Freescale i.MX8QXP LPDDR4 ARM2"; + compatible = "fsl,imx8qxp-lpddr4-arm2", "fsl,imx8qxp"; +}; + +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts new file mode 100755 index 000000000000..c64dda8215f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-a0.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&vpu_encoder { + status = "disabled"; +}; + +&vpu_decoder { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-csi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-csi.dts new file mode 100644 index 000000000000..110c29cef6e3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-csi.dts @@ -0,0 +1,128 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" +#include "fsl-imx8qxp-mek-lvds0-it6263.dtsi" + +&iomuxc { + imx8qxp-mek { + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 + SC_P_CSI_D01_CI_PI_D03 0xC0000041 + SC_P_CSI_D02_CI_PI_D04 0xC0000041 + SC_P_CSI_D03_CI_PI_D05 0xC0000041 + SC_P_CSI_D04_CI_PI_D06 0xC0000041 + SC_P_CSI_D05_CI_PI_D07 0xC0000041 + SC_P_CSI_D06_CI_PI_D08 0xC0000041 + SC_P_CSI_D07_CI_PI_D09 0xC0000041 + + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; +}; + }; +}; + +&jpegdec { + status = "disabled"; +}; + +&jpegenc { + status = "disabled"; +}; + +&i2c0_csi0 { + status = "disabled"; +}; + +&mipi_csi_0 { + status = "disabled"; +}; + +&i2c0_cm40 { + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; +}; +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&isi_0 { + interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ + parallel_csi; + status = "okay"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts new file mode 100644 index 000000000000..88942ca404aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dom0.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + /delete-property/ bootargs; + /delete-property/ stdout-path; + module@0 { + bootargs = "earlycon=xen console=hvc0 clk_ignore_unused loglevel=8 root=/dev/mmcblk1p2 rootwait rw video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off"; + compatible = "xen,linux-zimage", "xen,multiboot-module"; + /* The size will be override by uboot command */ + reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; + }; + }; +}; + +&lpuart0 { + interrupt-parent = <&gic>; +}; + +&imx8_gpu_ss { + /delete-property/ reg; + /delete-property/ reg-names; +}; + +&rtc { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts new file mode 100644 index 000000000000..a5debdc6ff7e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-dsi-rm67191.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&mipi_dsi_bridge1 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpio = <&pca9557_a 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_bridge1_out>; + }; + }; + }; + + port@2 { + mipi_bridge1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpio = <&pca9557_b 7 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel2_in: endpoint { + remote-endpoint = <&mipi_bridge2_out>; + }; + }; + }; + + port@2 { + mipi_bridge2_out: endpoint { + remote-endpoint = <&panel2_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts new file mode 100644 index 000000000000..d9b3842502f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2-tja1100.dts @@ -0,0 +1,16 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek-enet2.dts" +#include "fsl-imx8qxp-enet2-tja1100.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts new file mode 100644 index 000000000000..e0ba4d44a925 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&esai0 { + status = "disabled"; +}; + +&fec2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts new file mode 100644 index 000000000000..09f49927ecf6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-inmate.dts @@ -0,0 +1,284 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "fsl-imx8-ca35.dtsi" +#include <dt-bindings/soc/imx_rsrc.h> +#include <dt-bindings/soc/imx8_hsio.h> +#include <dt-bindings/soc/imx8_pd.h> +#include <dt-bindings/clock/imx8qxp-clock.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + imx8qx-pm { + #address-cells = <1>; + #size-cells = <0>; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = <SC_R_SDHC_0>; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = <SC_R_LAST>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + /*wakeup-irq = <227>;*/ + + pd_dma2_chan12: PD_UART2_RX { + reg = <SC_R_DMA_2_CH12>; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = <SC_R_DMA_2_CH13>; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + mu2: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + fsl,scu_ap_mu_id = <0>; + status = "okay"; + }; + + pci@ff700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xff700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-rates = <0>, <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + + /* For early console */ + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan13>; + /* + * dma-names = "tx","rx"; + * dmas = <&edma2 13 0 0>, + * <&edma2 12 0 1>; + */ + status = "disabled"; + }; + +}; + +&iomuxc { + imx8qxp-mek { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + }; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts new file mode 100755 index 000000000000..aa6d7b27cf1b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&i2c0_mipi_lvds0 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_0_dual_lvds>; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts new file mode 100755 index 000000000000..14328ef010fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +&i2c0_mipi_lvds1 { + lvds-to-hdmi-bridge@4c { + split-mode; + }; +}; + +&ldb1 { + status = "disabled"; +}; + +&ldb2 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts new file mode 100644 index 000000000000..f855f66e94e5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + lvds0_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight1>; + + port { + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb1 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_0_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&ldb2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts new file mode 100644 index 000000000000..b23fb2b6fa3d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-jdi-wuxga-lvds1-panel.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + lvds1_panel { + compatible = "jdi,tx26d202vm0bwa"; + backlight = <&lvds_backlight0>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&ldb2 { + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&ldb1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi new file mode 100644 index 000000000000..acd6a388cce0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds0-it6263.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi new file mode 100644 index 000000000000..c3088ea63fab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lvds1-it6263.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-m4.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-m4.dts new file mode 100644 index 000000000000..5372ef57e73d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-m4.dts @@ -0,0 +1,104 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + sound: sound { + status = "disabled"; + }; + + sound-cs42888 { + status = "disabled"; + }; + + rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx8qxp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 1>; + status = "okay"; + }; + + sound_rpmsg_wm8960: sound-rpmsg-wm8960 { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&rpmsg_i2s>; + codec-master; + codec-rpmsg; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&gpio1 0 0>; + mic-det-gpios = <&gpio1 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-rpmsg-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + asrc-controller = <&asrc0>; + audio-codec = <&rpmsg_i2s>; + codec-rpmsg; + status = "okay"; + }; +}; + +&i2c0_cm40 { + status = "disabled"; +}; + +&flexcan1 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-mipi-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-mipi-ov5640.dts new file mode 100644 index 000000000000..7756d686caf4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-mipi-ov5640.dts @@ -0,0 +1,87 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" +#include "fsl-imx8qxp-mek-lvds0-it6263.dtsi" + +&iomuxc { + imx8qxp-mek { + pinctrl_mipi_csi0: mipicsi0grp{ + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&i2c0_csi0 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts new file mode 100644 index 000000000000..8828be6f5b5e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-ov5640.dts @@ -0,0 +1,160 @@ +#include "fsl-imx8qxp-mek.dts" +#include "fsl-imx8qxp-mek-lvds0-it6263.dtsi" + +&iomuxc { + imx8qxp-mek { + pinctrl_mipi_csi0: mipicsi0grp{ + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 + SC_P_CSI_D01_CI_PI_D03 0xC0000041 + SC_P_CSI_D02_CI_PI_D04 0xC0000041 + SC_P_CSI_D03_CI_PI_D05 0xC0000041 + SC_P_CSI_D04_CI_PI_D06 0xC0000041 + SC_P_CSI_D05_CI_PI_D07 0xC0000041 + SC_P_CSI_D06_CI_PI_D08 0xC0000041 + SC_P_CSI_D07_CI_PI_D09 0xC0000041 + + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 + SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 + >; + }; + }; +}; + +&isi_0 { + interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ + parallel_csi; + status = "okay"; +}; + +&i2c0_cm40 { + ov5640: ov5640@3c { + compatible = "ovti,ov5640_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; + clock-names = "csi_mclk"; + pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <¶llel_csi_ep>; + }; + }; + }; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&isi_1 { + interface = <2 0 2>; + status = "okay"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&i2c0_csi0 { + clock-frequency = <100000>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + rst-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + max9286_mipi@6A { + status = "disabled"; + }; +}; + +&mipi_csi_0 { + /delete-property/virtual-channel; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +&jpegdec { + status = "disabled"; +}; + +&jpegenc { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts new file mode 100644 index 000000000000..9939b09b9d76 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-root.dts @@ -0,0 +1,111 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + SC_R_MU_2A + >; + rsrcs = < + SC_R_SDHC_0 + SC_R_DMA_2_CH12 + SC_R_DMA_2_CH13 + SC_R_UART_2 + SC_R_MU_2A + >; + pads = < + /* emmc */ + SC_P_EMMC0_CLK + SC_P_EMMC0_CMD + SC_P_EMMC0_DATA0 + SC_P_EMMC0_DATA1 + SC_P_EMMC0_DATA2 + SC_P_EMMC0_DATA3 + SC_P_EMMC0_DATA4 + SC_P_EMMC0_DATA5 + SC_P_EMMC0_DATA6 + SC_P_EMMC0_DATA7 + SC_P_EMMC0_STROBE + /* lpuart2 */ + SC_P_UART2_TX + SC_P_UART2_RX + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@0xffc00000 { + no-map; + reg = <0x0 0xffc00000 0x0 0x400000>; + }; + + loader_reserved: loader@0xffb00000 { + no-map; + reg = <0x0 0xffb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@0xff900000 { + no-map; + reg = <0x0 0xff900000 0x0 0x00200000>; + }; + + pci_reserved: pci@0xff700000 { + no-map; + reg = <0x0 0xff700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@0xdf7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x20000000>; + }; +}; + +&usdhc1 { + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts new file mode 100755 index 000000000000..a215f719dabf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts @@ -0,0 +1,1256 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + bcmdhd_wlan_0: bcmdhd_wlan@0 { + compatible = "android,bcmdhd_wlan"; + bcmdhd_fw = "/lib/firmware/bcm/1FD_BCM89359/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1FD_BCM89359/bcmdhd.cal"; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <3480>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound: sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&wm8960>; + codec-master; + /* + * hp-det = <hp-det-pin hp-det-polarity>; + * hp-det-pin: JD1 JD2 or JD3 + * hp-det-polarity = 0: hp detect high for headphone + * hp-det-polarity = 1: hp detect high for speaker + */ + hp-det = <2 0>; + hp-det-gpios = <&gpio1 0 0>; + mic-det-gpios = <&gpio1 0 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Main MIC", + "RINPUT2", "Main MIC", + "Mic Jack", "MICB", + "Main MIC", "MICB", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai4>, <&sai5>; + amix-controller = <&amix>; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds0 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm_mipi_lvds1 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_csi0_lpi2c0: csi0lpi2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 + SC_P_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + SC_P_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + SC_P_ADC_IN1_M40_I2C0_SDA 0x0600004c + SC_P_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_ioexp_rst: ioexp_rst_grp { + fsl,pins = < + SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 + >; + }; + + pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + SC_P_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + SC_P_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + SC_P_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + SC_P_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_gpio3: gpio3grp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + >; + }; + + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&i2c0_cm40 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_b 1 1>; + power-domains = <&pd_mclk_out0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + status = "okay"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + pinctrl-assert-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9646@71 { + compatible = "nxp,pca9646"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + interrupt-open-drain; + }; + + fxas2100x@21 { + compatible = "fsl,fxas2100x"; + reg = <0x21>; + interrupt-open-drain; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + interrupt-open-drain; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio1>; + interrupts = <2 2>; + }; + }; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&sai1 { + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +/* Only enable it and ptn5110 after rework U182 */ +&usbotg3 { + dr_mode = "otg"; + extcon = <&typec_ptn5110>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpio3 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_gpio3>; +}; + +&i2c0_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&vpu { + status = "disabled"; +}; + +&vpu_decoder { + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + core_type = <1>; + status = "okay"; +}; + +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + status = "okay"; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + status = "okay"; +}; + +/* DSI/LVDS port 1 */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + + port { + it6263_1_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_out: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi new file mode 100644 index 000000000000..b3c7ed38cec6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8dxp.dtsi" + +/ { + model = "Freescale i.MX8QXP"; + compatible = "fsl,imx8qxp"; + + cpus { + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + }; + + pmu { + interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; + }; +}; + +&A35_2 { + device_type = "cpu"; +}; + +&A35_3 { + device_type = "cpu"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi new file mode 100644 index 000000000000..56c735de9a06 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi @@ -0,0 +1,1008 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <2720>; + enable-active-high; + }; + + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_audio: fixedregulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_baseboard: fixedregulator@1 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "baseboard_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_adc_vref_1v8: adc_vref_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + status = "okay"; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai4>, <&sai5>; + amix-controller = <&amix>; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_adc_vref_1v8>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + compatible = "fsl,imx8qm-esai"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>, + <&clk IMX8QXP_AUD_PLL1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>; + assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + imx8qxp-lpddr4-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0xc600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 + >; + }; + + pinctrl_csi0_lpi2c0: csi0lpi2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_ptn5150: ptn5150 { + fsl,pins = < + SC_P_SPI0_CS1_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x0600002c + SC_P_UART0_TX_ADMA_UART0_TX 0x0600002c + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_TX_ADMA_UART1_TX 0x0600002c + SC_P_UART1_RX_ADMA_UART1_RX 0x0600002c + SC_P_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600002c + SC_P_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600002c + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x0600002c + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x0600002c + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_ESAI0_SCKT_CONN_MLB_SIG 0x21 + SC_P_ESAI0_FST_CONN_MLB_CLK 0x21 + SC_P_ESAI0_TX0_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&i2c0_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + power-domains = <&pd_mclk_out0>; + status = "okay"; + }; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + status = "okay"; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + reg = <0x3d>; + connect-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "disabled"; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_out: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_out>; + }; + }; +}; + }; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b4c4d823569a..f7df110b3eef 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -21,16 +21,18 @@ CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y +CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y @@ -59,17 +61,19 @@ CONFIG_ARCH_VULCAN=y CONFIG_ARCH_XGENE=y CONFIG_ARCH_ZX=y CONFIG_ARCH_ZYNQMP=y +CONFIG_ARCH_FSL_IMX8QM=y +CONFIG_ARCH_FSL_IMX8QP=y +CONFIG_ARCH_FSL_IMX8QXP=y +CONFIG_ARCH_FSL_IMX8MQ=y +CONFIG_ARCH_FSL_IMX8MM=y CONFIG_PCI=y -CONFIG_PCI_MSI=y CONFIG_PCI_IOV=y CONFIG_PCI_AARDVARK=y +CONFIG_PCI_IMX6=y CONFIG_PCIE_RCAR=y CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_XGENE=y -CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y CONFIG_ARM64_VA_BITS_48=y CONFIG_SCHED_MC=y CONFIG_PREEMPT=y @@ -77,15 +81,25 @@ CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_CMA=y CONFIG_SECCOMP=y -CONFIG_XEN=y CONFIG_KEXEC=y +CONFIG_XEN=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y -CONFIG_CPU_IDLE=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_BIG_LITTLE_CPUFREQ=y +CONFIG_ARM_IMX8_CPUFREQ=y +CONFIG_ARM_IMX8MQ_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_NET=y CONFIG_PACKET=y @@ -122,31 +136,61 @@ CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y CONFIG_BPF_JIT=y -CONFIG_BT=m -CONFIG_BT_HIDP=m -# CONFIG_BT_HS is not set -# CONFIG_BT_LE is not set +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y CONFIG_BT_LEDS=y -# CONFIG_BT_DEBUGFS is not set -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_LL=y -CONFIG_CFG80211=m -CONFIG_MAC80211=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_ARM_CCI400_PMU=y +CONFIG_ARM_CCI5xx_PMU=y CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y +CONFIG_MTD_SLRAM=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_FSL_FLEXSPI=y +CONFIG_MTD_UBI=y +CONFIG_OF_OVERLAY=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=y CONFIG_VIRTIO_BLK=y +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y CONFIG_SRAM=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -155,12 +199,13 @@ CONFIG_SCSI_HISI_SAS=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y CONFIG_AHCI_CEVA=y CONFIG_AHCI_MVEBU=y CONFIG_AHCI_XGENE=y CONFIG_AHCI_QORIQ=y -CONFIG_SATA_RCAR=y CONFIG_SATA_SIL24=y +CONFIG_SATA_RCAR=y CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_NETDEVICES=y @@ -182,8 +227,10 @@ CONFIG_RAVB=y CONFIG_SMC91X=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=m -CONFIG_REALTEK_PHY=m +CONFIG_AT803X_PHY=y CONFIG_MICREL_PHY=y +CONFIG_NXP_TJA110X_PHY=y +CONFIG_REALTEK_PHY=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m @@ -194,13 +241,25 @@ CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m +# CONFIG_WLAN_VENDOR_ATH is not set +CONFIG_BCMDHD_1363=y +CONFIG_BCMDHD_PCIE=y +CONFIG_HOSTAP=y +CONFIG_RTL_CARDS=m +# CONFIG_WLAN_VENDOR_TI is not set +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_POLLDEV=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX_SC_PWRKEY=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_HISI_POWERKEY=y +CONFIG_INPUT_MPL3115=y +CONFIG_INPUT_ISL29023=y # CONFIG_SERIO_SERPORT is not set CONFIG_SERIO_AMBAKMI=y CONFIG_LEGACY_PTY_COUNT=16 @@ -212,25 +271,28 @@ CONFIG_SERIAL_8250_UNIPHIER=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MESON=y +CONFIG_SERIAL_MESON_CONSOLE=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_SH_SCI=y CONFIG_SERIAL_SH_SCI_NR_UARTS=11 CONFIG_SERIAL_SH_SCI_CONSOLE=y -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_MVEBU_UART=y CONFIG_VIRTIO_CONSOLE=y CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_QUP=y @@ -239,12 +301,14 @@ CONFIG_I2C_UNIPHIER_F=y CONFIG_I2C_RCAR=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_LPSPI=y CONFIG_SPI_MESON_SPIFC=m CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=m CONFIG_SPI_S3C64XX=y +CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y @@ -257,52 +321,95 @@ CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y +CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_MAX77620=y CONFIG_POWER_AVS=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_POWER_RESET_MSM=y -CONFIG_BATTERY_BQ27XXX=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_THERMAL=y -CONFIG_THERMAL_EMULATION=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX8M_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_DEVICE_THERMAL=y CONFIG_EXYNOS_THERMAL=y CONFIG_WATCHDOG=y -CONFIG_RENESAS_WDT=y CONFIG_S3C2410_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX8_WDT=y CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m +CONFIG_RENESAS_WDT=y +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_HI655X_PMIC=y CONFIG_MFD_MAX77620=y CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_SEC_CORE=y -CONFIG_MFD_HI655X_PMIC=y -CONFIG_REGULATOR=y -CONFIG_MFD_CROS_EC=y -CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_BD71837=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_S2MPS11=y -CONFIG_DRM=m +CONFIG_REGULATOR_BD71837=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_GMSL_MAX9286=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_DCSS_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_DRM=y CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_VIVANTE=m +CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_NWL_DSI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_HDP=y +CONFIG_IMX_HDP_CEC=y CONFIG_DRM_HISI_KIRIN=m -CONFIG_FB=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_IMX64=y +CONFIG_FB_IMX64_DEBUG=y CONFIG_FB_ARMCLCD=y +CONFIG_FB_MXC_DISP_FRAMEWORK=y CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_LP855X=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y @@ -310,56 +417,118 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=y CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=y -CONFIG_SND_SOC_RCAR=y +CONFIG_SND_SOC_FSL_ACM=y +CONFIG_SND_SOC_FSL_DSP=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_WM8524=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_AMIX=y +CONFIG_SND_SOC_IMX_CDNHDMI=y CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_RCAR=y CONFIG_SND_SOC_AK4613=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y CONFIG_USB=y CONFIG_USB_OTG=y +CONFIG_USB_OTG_WHITELIST=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_XHCI_RCAR=y -CONFIG_USB_EHCI_EXYNOS=y CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_EXYNOS=y CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_EXYNOS=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y -CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_HSIC_USB3503=y -CONFIG_USB_MSM_OTG=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GPIO_VBUS=y +CONFIG_USB_MXS_PHY=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_FSL_UTP=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_GADGET_UAC1=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_SDHCI_IPROC is not set CONFIG_MMC_SPI=y CONFIG_MMC_SDHI=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_SUNXI=y +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y +CONFIG_MXC_MLB150=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y @@ -367,25 +536,36 @@ CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_S3C=y CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_TEGRA=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y CONFIG_RTC_DRV_XGENE=y -CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y CONFIG_PL330_DMA=y CONFIG_TEGRA20_APB_DMA=y CONFIG_QCOM_BAM_DMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y CONFIG_RCAR_DMAC=y -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y CONFIG_XEN_GNTDEV=y CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_MEDIA_CEC=y +CONFIG_ION=y +CONFIG_ION_MXC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y @@ -394,28 +574,37 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_MMCC_8996=y CONFIG_HWSPINLOCK_QCOM=y +CONFIG_CLKSRC_IMX_SYS_CNT=y CONFIG_MAILBOX=y CONFIG_ARM_MHU=y CONFIG_HI6220_MBOX=y CONFIG_ARM_SMMU=y +CONFIG_ARCH_MXC_ARM64=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD=y CONFIG_QCOM_SMD_RPM=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_PTN5150=y +CONFIG_IIO=y +CONFIG_EXYNOS_ADC=y +CONFIG_IMX8QXP_ADC=y CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX=y +CONFIG_PWM_SAMSUNG=y CONFIG_PWM_TEGRA=m -CONFIG_COMMON_RESET_HI6220=y -CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_XGENE=y CONFIG_PHY_TEGRA_XUSB=y +CONFIG_IMX8_DDR_PERF=y +CONFIG_NVMEM=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_SCU_OCOTP=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ACPI=y -CONFIG_IIO=y -CONFIG_EXYNOS_ADC=y -CONFIG_PWM_SAMSUNG=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y @@ -429,10 +618,10 @@ CONFIG_FUSE_FS=m CONFIG_CUSE=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y -CONFIG_TMPFS=y CONFIG_HUGETLBFS=y -CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y @@ -442,26 +631,49 @@ CONFIG_ROOT_NFS=y CONFIG_9P_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_VIRTUALIZATION=y CONFIG_KVM=y CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y CONFIG_LOCKUP_DETECTOR=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_MEMTEST=y CONFIG_SECURITY=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set CONFIG_CRYPTO_CRC32_ARM64=y diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index ad6bd8b26ada..6d2349df0048 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -24,6 +24,7 @@ #include <linux/sched.h> #include <asm/cputype.h> #include <asm/mmu.h> +#include <soc/imx8/soc.h> /* * Raw TLBI operations. @@ -108,8 +109,12 @@ static inline void flush_tlb_mm(struct mm_struct *mm) unsigned long asid = ASID(mm) << 48; dsb(ishst); - __tlbi(aside1is, asid); - __tlbi_user(aside1is, asid); + if (TKT340553_SW_WORKAROUND && ASID(mm) >> 11) { + __tlbi(vmalle1is); + } else { + __tlbi(aside1is, asid); + __tlbi_user(aside1is, asid); + } dsb(ish); } @@ -119,8 +124,12 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48); dsb(ishst); - __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); + if (TKT340553_SW_WORKAROUND && (uaddr >> 36 || (ASID(vma->vm_mm) >> 12))) { + __tlbi(vmalle1is); + } else { + __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); + } dsb(ish); } @@ -136,6 +145,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, { unsigned long asid = ASID(vma->vm_mm) << 48; unsigned long addr; + unsigned long mask = (1 << 20) - 1; if ((end - start) > MAX_TLB_RANGE) { flush_tlb_mm(vma->vm_mm); @@ -144,10 +154,14 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, start = asid | (start >> 12); end = asid | (end >> 12); + mask <<= 24; + dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { - if (last_level) { + if (TKT340553_SW_WORKAROUND && (addr & mask || (ASID(vma->vm_mm) >> 12))) { + __tlbi(vmalle1is); + } else if (last_level) { __tlbi(vale1is, addr); __tlbi_user(vale1is, addr); } else { @@ -177,8 +191,12 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end end >>= 12; dsb(ishst); - for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) - __tlbi(vaae1is, addr); + for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { + if (TKT340553_SW_WORKAROUND && addr >> 24) + __tlbi(vmalle1is); + else + __tlbi(vaae1is, addr); + } dsb(ish); isb(); } @@ -192,8 +210,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, { unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); - __tlbi(vae1is, addr); - __tlbi_user(vae1is, addr); + if (TKT340553_SW_WORKAROUND && (uaddr >> 36 || (ASID(mm) >> 12))) { + __tlbi(vmalle1is); + } else { + __tlbi(vae1is, addr); + __tlbi_user(vae1is, addr); + } + dsb(ish); } diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 8eedeef375d6..5346c4cc65e6 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -24,6 +24,7 @@ #include <linux/kernel.h> #include <linux/sched.h> #include <linux/mm.h> +#include <linux/nospec.h> #include <linux/smp.h> #include <linux/ptrace.h> #include <linux/user.h> @@ -266,19 +267,22 @@ static int ptrace_hbp_set_event(unsigned int note_type, switch (note_type) { case NT_ARM_HW_BREAK: - if (idx < ARM_MAX_BRP) { - tsk->thread.debug.hbp_break[idx] = bp; - err = 0; - } + if (idx >= ARM_MAX_BRP) + goto out; + idx = array_index_nospec(idx, ARM_MAX_BRP); + tsk->thread.debug.hbp_break[idx] = bp; + err = 0; break; case NT_ARM_HW_WATCH: - if (idx < ARM_MAX_WRP) { - tsk->thread.debug.hbp_watch[idx] = bp; - err = 0; - } + if (idx >= ARM_MAX_WRP) + goto out; + idx = array_index_nospec(idx, ARM_MAX_WRP); + tsk->thread.debug.hbp_watch[idx] = bp; + err = 0; break; } +out: return err; } diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index cab3574ab7d9..28d9199aaf8f 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -28,9 +28,14 @@ #include <linux/dma-contiguous.h> #include <linux/vmalloc.h> #include <linux/swiotlb.h> +#include <linux/of.h> #include <asm/cacheflush.h> +EXPORT_SYMBOL(__dma_map_area); +EXPORT_SYMBOL(__dma_unmap_area); +EXPORT_SYMBOL(__dma_flush_area); + static int swiotlb __ro_after_init; static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot, @@ -359,6 +364,22 @@ static int __swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t addr) return 0; } +/* + * Some 64bit SoCs only support up to 32bit dma capability. + * Do quirk set here. + */ +static int __swiotlb_dma_supported_quirk(struct device *hwdev, u64 mask) +{ + if (mask > DMA_BIT_MASK(32)) { + pr_err("Can't support > 32 bit dma.\n"); + return 0; + } + + if (swiotlb) + return swiotlb_dma_supported(hwdev, mask); + return 1; +} + static struct dma_map_ops swiotlb_dma_ops = { .alloc = __dma_alloc, .free = __dma_free, @@ -961,6 +982,15 @@ void arch_teardown_dma_ops(struct device *dev) dev->archdata.dma_ops = NULL; } +static int iommu_dma_supported_quirk(struct device *dev, u64 mask) +{ + if (mask > DMA_BIT_MASK(32)) { + pr_err("Can't support > 32 bit dma.\n"); + return 0; + } + + return iommu_dma_supported(dev, mask); +} #else static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, @@ -972,9 +1002,24 @@ static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, const struct iommu_ops *iommu, bool coherent) { + u32 mask32; + struct device_node *np; + if (!dev->archdata.dma_ops) dev->archdata.dma_ops = &swiotlb_dma_ops; dev->archdata.dma_coherent = coherent; __iommu_setup_dma_ops(dev, dma_base, size, iommu); + + np = of_find_compatible_node(NULL, NULL, "dma-capability"); + if (np == NULL) + return; + if (of_property_read_u32(np, "only-dma-mask32", &mask32)) + mask32 = 0; + if (mask32) { + swiotlb_dma_ops.dma_supported = __swiotlb_dma_supported_quirk; +#ifdef CONFIG_IOMMU_DMA + iommu_dma_ops.dma_supported = iommu_dma_supported_quirk; +#endif + } } |