diff options
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts | 109 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi | 42 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi | 1216 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 1209 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts | 30 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi | 43 |
7 files changed, 1425 insertions, 1229 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b7cfae888878..89e37018b255 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -40,8 +40,9 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-lpddr4-arm2-usb3.dtb \ fsl-imx8qm-lpddr4-arm2-dsi-rm67191.dtb \ fsl-imx8qm-lpddr4-arm2-enet2-tja1100.dtb \ - fsl-imx8qm-lpddr4-arm2-hsic.dtb -dtb-$(CONFIG_ARCH_FSL_IMX8QP) += fsl-imx8qp-lpddr4-arm2.dtb + fsl-imx8qm-lpddr4-arm2-hsic.dtb \ + fsl-imx8dm-lpddr4-arm2.dtb \ + fsl-imx8qp-lpddr4-arm2.dtb dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-mek.dtb \ fsl-imx8qxp-mek-dom0.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts new file mode 100644 index 000000000000..412525fcf1b0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dm-lpddr4-arm2.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8dm.dtsi" + +#include "fsl-imx8q-arm2.dtsi" + +/ { + model = "Freescale i.MX8DM ARM2"; + compatible = "fsl,imx8dm-arm2", "fsl,imx8dm", "fsl,imx8qm"; +}; + +&gpu_3d1 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&display{ + ports = <&dpu1_disp0>, <&dpu1_disp1>; +}; + +&prg10 { + status = "disabled"; +}; + +&prg11 { + status = "disabled"; +}; + +&prg12 { + status = "disabled"; +}; + +&prg13 { + status = "disabled"; +}; + +&prg14 { + status = "disabled"; +}; + +&prg15 { + status = "disabled"; +}; + +&prg16 { + status = "disabled"; +}; + +&prg17 { + status = "disabled"; +}; + +&prg18 { + status = "disabled"; +}; + +&dpr3_channel1 { + status = "disabled"; +}; + +&dpr3_channel2 { + status = "disabled"; +}; + +&dpr3_channel3 { + status = "disabled"; +}; + +&dpr4_channel1 { + status = "disabled"; +}; + +&dpr4_channel2 { + status = "disabled"; +}; + +&dpr4_channel3 { + status = "disabled"; +}; + +&dpu2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi new file mode 100644 index 000000000000..eae337eb6422 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dm.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8DM"; + compatible = "fsl, imx8dm", "fsl,imx8qm"; + +}; + +&A53_0 { + device_type = ""; +}; + +&A53_1 { + device_type = ""; +}; + +&A53_2 { + device_type = ""; +}; + +&A53_3 { + device_type = ""; +}; + +&A53_L2 { + compatible = ""; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi new file mode 100644 index 000000000000..b647e4019b3a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi @@ -0,0 +1,1216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_audio: regulator@0 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <3000>; + enable-active-high; + }; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&codec>; + asrc-controller = <&asrc0>; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + model = "amix-audio-sai"; + dais = <&sai6>, <&sai7>; + amix-controller = <&amix>; + }; + + lvds_backlight0: lvds_backlight@0 { + compatible = "pwm-backlight"; + pwms = <&lvds0_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; + + lvds_backlight1: lvds_backlight@1 { + compatible = "pwm-backlight"; + pwms = <&lvds1_pwm 0 100000 0>; + + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <80>; + }; +}; + +&acm { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&iomuxc { + imx8qm-arm2 { + + pinctrl_esai0: esai0grp { + fsl,pins = < + SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + >; + }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x04000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x04000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_lvds0_pwm0: lvds0pwm0grp { + fsl,pins = < + SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_lvds1_pwm0: lvds1pwm0grp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 + >; + }; + + pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ + fsl,pins = < + SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 + SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&gpio0_mipi_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; + status = "okay"; +}; + +&gpio0_mipi_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; + status = "okay"; +}; + +&i2c0_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "disabled"; + + max9286_mipi@6A { + compatible = "maxim,max9286_mipi"; + reg = <0x6A>; + clocks = <&clk IMX8QM_CLK_DUMMY>; + clock-names = "capture_mclk"; + mclk = <27000000>; + mclk_source = <0>; + pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; + virtual-channel; + port { + max9286_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c0_hdmi { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + codec: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 1>; + power-domains = <&pd_mclk_out0>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1d { + compatible = "fsl,fxos8700"; + reg = <0x1d>; + }; + + isl29023@44 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isl29023>; + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <20 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + resets = <&modem_reset>; + status = "okay"; +}; + +&lpuart3 { /* GPS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "okay"; + + /* Camera 0 MIPI CSI-2 (CSIS0) */ + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&max9286_0_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + virtual-channel; + status = "disabled"; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&max9286_1_ep>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + pinctrl-assert-gpios = <&pca9557_d 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90000000 0x0 0x10000>; + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&rpmsg1{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <1>; + reg = <0x0 0x90100000 0x0 0x10000>; + status = "okay"; +}; + +&lvds0_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_pwm0>; + status = "okay"; +}; + +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_pwm0>; + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&it6263_1_in>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_1_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_adv: endpoint { + remote-endpoint = <&adv7535_1_in>; + }; + }; +}; + +&i2c0_mipi_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge1: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_adv>; + }; + }; + }; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; + + port@1 { + mipi_dsi_bridge2_adv: endpoint { + remote-endpoint = <&adv7535_2_in>; + }; + }; +}; + +&i2c0_mipi_dsi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + adv_bridge2: adv7535@3d { + compatible = "adi,adv7535", "adi,adv7533"; + reg = <0x3d>; + adi,dsi-lanes = <4>; + adi,dsi-channel = <1>; + status = "okay"; + + port { + adv7535_2_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_adv>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 20eff2e69062..43a4e8904054 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -1,6 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017~2018 NXP * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -16,1208 +16,9 @@ /dts-v1/; #include "fsl-imx8qm.dtsi" +#include "fsl-imx8q-arm2.dtsi" / { - model = "Freescale i.MX8QM ARM2"; - compatible = "fsl,imx8qm-arm2", "fsl,imx8qm"; - - chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; - stdout-path = &lpuart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - user { - label = "heartbeat"; - gpios = <&gpio2 15 0>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - modem_reset: modem-reset { - compatible = "gpio-reset"; - reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; - reset-delay-us = <2000>; - reset-post-delay-ms = <40>; - #reset-cells = <0>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_audio: regulator@0 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usdhc2_vmmc: usdhc2_vmmc { - compatible = "regulator-fixed"; - regulator-name = "sw-3p3-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - off-on-delay = <3000>; - enable-active-high; - }; - }; - - sound-cs42888 { - compatible = "fsl,imx8qm-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; - model = "imx-cs42888"; - esai-controller = <&esai0>; - audio-codec = <&codec>; - asrc-controller = <&asrc0>; - }; - - sound-amix-sai { - compatible = "fsl,imx-audio-amix"; - model = "amix-audio-sai"; - dais = <&sai6>, <&sai7>; - amix-controller = <&amix>; - }; - - lvds_backlight0: lvds_backlight@0 { - compatible = "pwm-backlight"; - pwms = <&lvds0_pwm 0 100000 0>; - - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <80>; - }; - - lvds_backlight1: lvds_backlight@1 { - compatible = "pwm-backlight"; - pwms = <&lvds1_pwm 0 100000 0>; - - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <80>; - }; -}; - -&acm { - status = "okay"; -}; - -&amix { - status = "okay"; -}; - -&asrc0 { - assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; - assigned-clock-rates = <786432000>, <49152000>, <24576000>; - fsl,asrc-rate = <48000>; - status = "okay"; -}; - -&asrc1 { - fsl,asrc-rate = <48000>; - assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; - assigned-clock-rates = <786432000>, <49152000>, <24576000>; - status = "okay"; -}; - -&esai0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esai0>; - assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, - <&clk IMX8QM_AUD_PLL0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; - assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; - status = "okay"; -}; - -&sai_hdmi_tx { - assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, - <&clk IMX8QM_AUD_PLL0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, - <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; - assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; - fsl,sai-asynchronous; - status = "okay"; -}; - -&sai6 { - assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, - <&clk IMX8QM_AUD_PLL1_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, - <&clk IMX8QM_AUD_SAI_6_MCLK>; - assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; - assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; - fsl,sai-asynchronous; - fsl,txm-rxs; - status = "okay"; -}; - -&sai7 { - assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, - <&clk IMX8QM_AUD_PLL1_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, - <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, - <&clk IMX8QM_AUD_SAI_7_MCLK>; - assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; - assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; - fsl,sai-asynchronous; - fsl,txm-rxs; - status = "okay"; -}; - -&iomuxc { - imx8qm-arm2 { - - pinctrl_esai0: esai0grp { - fsl,pins = < - SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 - SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 - SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 - SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 - SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 - SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 - SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 - SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 - SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 - SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 - SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc6000040 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_fec2: fec2grp { - fsl,pins = < - SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 - SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 - SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020 - SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020 - SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020 - SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020 - SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020 - SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020 - SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020 - SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020 - SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020 - SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020 - SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020 - SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { - fsl,pins = < - SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c - SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c - >; - }; - - pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { - fsl,pins = < - SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c - SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c - >; - }; - - pinctrl_hdmi_lpi2c0: hdmilpi2c0grp { - fsl,pins = < - SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL 0xc600004c - SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA 0xc600004c - >; - }; - - pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { - fsl,pins = < - SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c - SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c - >; - }; - - pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { - fsl,pins = < - SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c - SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c - >; - }; - - pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { - fsl,pins = < - SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 - >; - }; - - pinctrl_lpi2c0: lpi2c0grp { - fsl,pins = < - SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c - SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c - SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - SC_P_UART0_RX_DMA_UART0_RX 0x06000020 - SC_P_UART0_TX_DMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - SC_P_UART1_RX_DMA_UART1_RX 0x06000020 - SC_P_UART1_TX_DMA_UART1_TX 0x06000020 - SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 - SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 - >; - }; - - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 - SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 - >; - }; - - pinctrl_mlb: mlbgrp { - fsl,pins = < - SC_P_MLB_SIG_CONN_MLB_SIG 0x21 - SC_P_MLB_CLK_CONN_MLB_CLK 0x21 - SC_P_MLB_DATA_CONN_MLB_DATA 0x21 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 - SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 - SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c - SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c - SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c - SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c - SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c - SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c - SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c - SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c - SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c - SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c - SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c - SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c - SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c - SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c - SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c - SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 - >; - }; - - pinctrl_pciea: pcieagrp{ - fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 - SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 - >; - }; - - pinctrl_pcieb: pciebgrp{ - fsl,pins = < - SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x04000021 - SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 - SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x04000021 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 - >; - }; - - pinctrl_lvds0_pwm0: lvds0pwm0grp { - fsl,pins = < - SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020 - >; - }; - - pinctrl_lvds1_pwm0: lvds1pwm0grp { - fsl,pins = < - SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 - >; - }; - - pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ - fsl,pins = < - SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 - SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 - >; - }; - - pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{ - fsl,pins = < - SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021 - SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021 - >; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - srp-disable; - hnp-disable; - adp-disable; - power-polarity-active-high; - disable-over-current; - status = "okay"; -}; - -&usbotg3 { - dr_mode = "host"; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - fsl,rgmii_txc_dly; - fsl,rgmii_rxc_dly; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - at803x,eee-disabled; - at803x,vddio-1p8v; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - at803x,eee-disabled; - at803x,vddio-1p8v; - status = "disabled"; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; -}; - -&flexspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - flash0: mt35xu512aba@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt35xu512aba"; - spi-max-frequency = <29000000>; - spi-nor,ddr-quad-read-dummy = <8>; - }; -}; - -&gpio0_mipi_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_csi0_gpio>; - status = "okay"; -}; - -&gpio0_mipi_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_csi1_gpio>; - status = "okay"; -}; - -&i2c0_mipi_csi0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - - max9286_mipi@6A { - compatible = "maxim,max9286_mipi"; - reg = <0x6A>; - clocks = <&clk IMX8QM_CLK_DUMMY>; - clock-names = "capture_mclk"; - mclk = <27000000>; - mclk_source = <0>; - pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>; - virtual-channel; - port { - max9286_0_ep: endpoint { - remote-endpoint = <&mipi_csi0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c0_mipi_csi1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "disabled"; - - max9286_mipi@6A { - compatible = "maxim,max9286_mipi"; - reg = <0x6A>; - clocks = <&clk IMX8QM_CLK_DUMMY>; - clock-names = "capture_mclk"; - mclk = <27000000>; - mclk_source = <0>; - pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>; - virtual-channel; - port { - max9286_1_ep: endpoint { - remote-endpoint = <&mipi_csi1_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c0_hdmi { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_lpi2c0>; - clock-frequency = <100000>; - status = "disabled"; -}; - -&i2c0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c0>; - clock-frequency = <100000>; - status = "okay"; - - codec: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&clk IMX8QM_AUD_MCLKOUT0>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; - reset-gpio = <&pca9557_a 2 1>; - power-domains = <&pd_mclk_out0>; - }; -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1>; - status = "okay"; - - pca9557_a: gpio@18 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@19 { - compatible = "nxp,pca9557"; - reg = <0x19>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_c: gpio@1b { - compatible = "nxp,pca9557"; - reg = <0x1b>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_d: gpio@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - }; - - fxas2100x@20 { - compatible = "fsl,fxas2100x"; - reg = <0x20>; - }; - - fxos8700@1d { - compatible = "fsl,fxos8700"; - reg = <0x1d>; - }; - - isl29023@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "fsl,isl29023"; - reg = <0x44>; - rext = <499>; - interrupt-parent = <&gpio3>; - interrupts = <20 2>; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&pd_dma_lpuart0 { - debug_console; -}; - -&lpuart0 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&lpuart1 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - resets = <&modem_reset>; - status = "okay"; -}; - -&lpuart3 { /* GPS */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>; - status = "okay"; -}; - -&mipi_csi_0 { - #address-cells = <1>; - #size-cells = <0>; - virtual-channel; - status = "okay"; - - /* Camera 0 MIPI CSI-2 (CSIS0) */ - port@0 { - reg = <0>; - mipi_csi0_ep: endpoint { - remote-endpoint = <&max9286_0_ep>; - data-lanes = <1 2 3 4>; - }; - }; -}; - -&mipi_csi_1 { - #address-cells = <1>; - #size-cells = <0>; - virtual-channel; - status = "disabled"; - - /* Camera 0 MIPI CSI-2 (CSIS1) */ - port@1 { - reg = <1>; - mipi_csi1_ep: endpoint { - remote-endpoint = <&max9286_1_ep>; - data-lanes = <1 2 3 4>; - }; - }; -}; - -&mlb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mlb>; - pinctrl-assert-gpios = <&pca9557_d 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&isi_0 { - status = "okay"; -}; - -&isi_1 { - status = "okay"; -}; - -&isi_2 { - status = "okay"; -}; - -&isi_3 { - status = "okay"; -}; - -&gpu_3d0 { - status = "okay"; -}; - -&gpu_3d1 { - status = "okay"; -}; - -&imx8_gpu_ss { - status = "okay"; -}; - -&prg1 { - status = "okay"; -}; - -&prg2 { - status = "okay"; -}; - -&prg3 { - status = "okay"; -}; - -&prg4 { - status = "okay"; -}; - -&prg5 { - status = "okay"; -}; - -&prg6 { - status = "okay"; -}; - -&prg7 { - status = "okay"; -}; - -&prg8 { - status = "okay"; -}; - -&prg9 { - status = "okay"; -}; - -&dpr1_channel1 { - status = "okay"; -}; - -&dpr1_channel2 { - status = "okay"; -}; - -&dpr1_channel3 { - status = "okay"; -}; - -&dpr2_channel1 { - status = "okay"; -}; - -&dpr2_channel2 { - status = "okay"; -}; - -&dpr2_channel3 { - status = "okay"; -}; - -&dpu1 { - status = "okay"; -}; - -&prg10 { - status = "okay"; -}; - -&prg11 { - status = "okay"; -}; - -&prg12 { - status = "okay"; -}; - -&prg13 { - status = "okay"; -}; - -&prg14 { - status = "okay"; -}; - -&prg15 { - status = "okay"; -}; - -&prg16 { - status = "okay"; -}; - -&prg17 { - status = "okay"; -}; - -&prg18 { - status = "okay"; -}; - -&dpr3_channel1 { - status = "okay"; -}; - -&dpr3_channel2 { - status = "okay"; -}; - -&dpr3_channel3 { - status = "okay"; -}; - -&dpr4_channel1 { - status = "okay"; -}; - -&dpr4_channel2 { - status = "okay"; -}; - -&dpr4_channel3 { - status = "okay"; -}; - -&dpu2 { - status = "okay"; -}; - -&pciea{ - ext_osc = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pciea>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcieb{ - ext_osc = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb>; - reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; - clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&intmux_cm40 { - status = "okay"; -}; - -&rpmsg{ - /* - * 64K for one rpmsg instance: - */ - vdev-nums = <1>; - reg = <0x0 0x90000000 0x0 0x10000>; - status = "okay"; -}; - -&intmux_cm41 { - status = "okay"; -}; - -&rpmsg1{ - /* - * 64K for one rpmsg instance: - */ - vdev-nums = <1>; - reg = <0x0 0x90100000 0x0 0x10000>; - status = "okay"; -}; - -&lvds0_pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0_pwm0>; - status = "okay"; -}; - -&lvds1_pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds1_pwm0>; - status = "okay"; -}; - -&ldb1_phy { - status = "okay"; -}; - -&ldb1 { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - status = "okay"; - - port@1 { - reg = <1>; - - lvds0_out: endpoint { - remote-endpoint = <&it6263_0_in>; - }; - }; - }; -}; - -&i2c1_lvds0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; - clock-frequency = <100000>; - status = "okay"; - - lvds-to-hdmi-bridge@4c { - compatible = "ite,it6263"; - reg = <0x4c>; - - port { - it6263_0_in: endpoint { - clock-lanes = <3>; - data-lanes = <0 1 2 4>; - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ldb2_phy { - status = "okay"; -}; - -&ldb2 { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - status = "okay"; - - port@1 { - reg = <1>; - - lvds1_out: endpoint { - remote-endpoint = <&it6263_1_in>; - }; - }; - }; -}; - -&i2c1_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; - clock-frequency = <100000>; - status = "okay"; - - lvds-to-hdmi-bridge@4c { - compatible = "ite,it6263"; - reg = <0x4c>; - - port { - it6263_1_in: endpoint { - clock-lanes = <3>; - data-lanes = <0 1 2 4>; - remote-endpoint = <&lvds1_out>; - }; - }; - }; -}; - -&mipi_dsi_phy1 { - status = "okay"; -}; - -&mipi_dsi1 { - status = "okay"; -}; - -&mipi_dsi_bridge1 { - status = "okay"; - - port@1 { - mipi_dsi_bridge1_adv: endpoint { - remote-endpoint = <&adv7535_1_in>; - }; - }; -}; - -&i2c0_mipi_dsi0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi0_lpi2c0>; - clock-frequency = <100000>; - status = "okay"; - - adv_bridge1: adv7535@3d { - compatible = "adi,adv7535", "adi,adv7533"; - reg = <0x3d>; - adi,dsi-lanes = <4>; - adi,dsi-channel = <1>; - status = "okay"; - - port { - adv7535_1_in: endpoint { - remote-endpoint = <&mipi_dsi_bridge1_adv>; - }; - }; - }; -}; - -&mipi_dsi_phy2 { - status = "okay"; -}; - -&mipi_dsi2 { - status = "okay"; -}; - -&mipi_dsi_bridge2 { - status = "okay"; - - port@1 { - mipi_dsi_bridge2_adv: endpoint { - remote-endpoint = <&adv7535_2_in>; - }; - }; -}; - -&i2c0_mipi_dsi1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi1_lpi2c0>; - clock-frequency = <100000>; - status = "okay"; - - adv_bridge2: adv7535@3d { - compatible = "adi,adv7535", "adi,adv7533"; - reg = <0x3d>; - adi,dsi-lanes = <4>; - adi,dsi-channel = <1>; - status = "okay"; - - port { - adv7535_2_in: endpoint { - remote-endpoint = <&mipi_dsi_bridge2_adv>; - }; - }; - }; + model = "Freescale i.MX8QM LPDDR4 ARM2"; + compatible = "fsl,imx8qm-lpddr4-arm2", "fsl,imx8qm"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts index 00446b80bf44..969869097ed5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qp-lpddr4-arm2.dts @@ -1,5 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2018 NXP * * This program is free software; you can redistribute it and/or @@ -13,29 +13,13 @@ * GNU General Public License for more details. */ -#include "fsl-imx8qm-lpddr4-arm2.dts" +/dts-v1/; -/ { - model = "Freescale i.MX8QP ARM2"; - compatible = "fsl,imx8qm-arm2", "fsl,imx8qm"; -}; - -&gpu_3d0 { - assigned-clock-rates = <625000000>, <625000000>; -}; +#include "fsl-imx8qp.dtsi" -&gpu_3d1 { - assigned-clock-rates = <625000000>, <625000000>; -}; - -&A72_1 { - device_type = ""; -}; +#include "fsl-imx8q-arm2.dtsi" -&imx8_gpu_ss {/*<freq-kHz vol-uV>*/ - operating-points = < -/*nominal*/ 625000 0 - 625000 0 -/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ - >; +/ { + model = "Freescale i.MX8QP ARM2"; + compatible = "fsl,imx8qp-arm2", "fsl,imx8qp", "fsl,imx8qm"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi new file mode 100644 index 000000000000..97793d66ef23 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qp.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QP"; + compatible = "fsl,imx8qp", "fsl,imx8qm"; + + pmu { + interrupt-affinity = <&A72_0>; + }; +}; + +/delete-node/ &A72_1; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&gpu_3d1 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&imx8_gpu_ss {/*<freq-kHz vol-uV>*/ + operating-points = < + /*nominal*/ 625000 0 + 625000 0 +/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/ + >; +}; |