diff options
Diffstat (limited to 'arch/arm')
72 files changed, 1324 insertions, 708 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 28e6a29e95c6..25fa0ede0d1b 100755 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1192,7 +1192,7 @@ config ARM_ERRATA_743622 depends on CPU_V7 help This option enables the workaround for the 743622 Cortex-A9 - (r2p0..r2p2) erratum. Under very rare conditions, a faulty + (r2p*) erratum. Under very rare conditions, a faulty optimisation in the Cortex-A9 Store Buffer may lead to data corruption. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which disables the Store Buffer diff --git a/arch/arm/configs/imx6_android_defconfig b/arch/arm/configs/imx6_android_defconfig index d8d1b11202aa..5439d9c922d2 100644 --- a/arch/arm/configs/imx6_android_defconfig +++ b/arch/arm/configs/imx6_android_defconfig @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux/arm 3.0.15 Kernel Configuration +# Linux/arm 3.0.35 Kernel Configuration # CONFIG_ARM=y CONFIG_HAVE_PWM=y @@ -2594,6 +2594,11 @@ CONFIG_ANATOP_THERMAL=y CONFIG_MXC_MIPI_CSI2=y # +# MXC HDMI CEC (Consumer Electronics Control) support +# +# CONFIG_MXC_HDMI_CEC is not set + +# # File systems # CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig index 5cae7c249854..e032e6cc3de3 100644 --- a/arch/arm/configs/imx6_defconfig +++ b/arch/arm/configs/imx6_defconfig @@ -1126,7 +1126,7 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y @@ -1832,7 +1832,6 @@ CONFIG_SND_SOC_IMX_CS42888=y # CONFIG_SND_SOC_IMX_SI4763 is not set CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_HDMI=y -CONFIG_SND_SOC_IMX_WM8958=y CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_WM_HUBS=y @@ -2316,6 +2315,11 @@ CONFIG_ANATOP_THERMAL=y CONFIG_MXC_MIPI_CSI2=y # +# MXC HDMI CEC (Consumer Electronics Control) support +# +# CONFIG_MXC_HDMI_CEC is not set + +# # File systems # CONFIG_EXT2_FS=y @@ -2664,6 +2668,9 @@ CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048 CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set # CONFIG_BINARY_PRINTF is not set # diff --git a/arch/arm/configs/imx6_updater_defconfig b/arch/arm/configs/imx6_updater_defconfig index 56406344b130..5fad815940e8 100644 --- a/arch/arm/configs/imx6_updater_defconfig +++ b/arch/arm/configs/imx6_updater_defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_FIQ=y CONFIG_VECTORS_BASE=0xffff0000 @@ -92,7 +93,6 @@ CONFIG_RD_GZIP=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y -CONFIG_PANIC_TIMEOUT=0 CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y @@ -108,7 +108,6 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y -# CONFIG_ASHMEM is not set CONFIG_AIO=y CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y @@ -383,7 +382,6 @@ CONFIG_ARM_ERRATA_751472=y CONFIG_ARM_ERRATA_754322=y # CONFIG_ARM_ERRATA_754327 is not set CONFIG_ARM_GIC=y -# CONFIG_FIQ_DEBUGGER is not set # # Bus support @@ -433,7 +431,7 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_COMPACTION is not set # CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 +CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set @@ -444,7 +442,6 @@ CONFIG_ALIGNMENT_TRAP=y # CONFIG_SECCOMP is not set # CONFIG_CC_STACKPROTECTOR is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set -# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set # # Boot options @@ -514,7 +511,6 @@ CONFIG_SUSPEND=y # CONFIG_PM_TEST_SUSPEND is not set CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y CONFIG_SUSPEND_FREEZER=y -# CONFIG_WAKELOCK is not set CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_RUNTIME=y @@ -524,7 +520,6 @@ CONFIG_PM_DEBUG=y CONFIG_CAN_PM_TRACE=y CONFIG_APM_EMULATION=y CONFIG_PM_RUNTIME_CLK=y -# CONFIG_SUSPEND_TIME is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -567,8 +562,6 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -CONFIG_ANDROID_PARANOID_NETWORK=y -CONFIG_NET_ACTIVITY_STATS=y # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set # CONFIG_NETFILTER is not set @@ -648,7 +641,6 @@ CONFIG_WIRELESS=y # # CONFIG_WIMAX is not set CONFIG_RFKILL=y -CONFIG_RFKILL_PM=y CONFIG_RFKILL_INPUT=y # CONFIG_RFKILL_REGULATOR is not set # CONFIG_RFKILL_GPIO is not set @@ -739,7 +731,6 @@ CONFIG_M25PXX_USE_FAST_READ=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_ECC=y # CONFIG_MTD_NAND_ECC_SMC is not set CONFIG_MTD_NAND=y @@ -748,6 +739,7 @@ CONFIG_MTD_NAND=y # CONFIG_MTD_SM_COMMON is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set # CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set # CONFIG_MTD_NAND_GPMI_NAND is not set @@ -919,9 +911,6 @@ CONFIG_FEC=y # CONFIG_NETDEV_10000 is not set CONFIG_WLAN=y # CONFIG_USB_ZD1201 is not set -# CONFIG_WIFI_CONTROL_FUNC is not set -# CONFIG_BCM4329 is not set -# CONFIG_BCMDHD is not set # CONFIG_HOSTAP is not set # @@ -970,7 +959,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # CONFIG_INPUT_APMPOWER is not set -# CONFIG_INPUT_KEYRESET is not set # # Input Device Drivers @@ -1001,7 +989,6 @@ CONFIG_TOUCHSCREEN_EGALAX=y # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set # CONFIG_TOUCHSCREEN_WM97XX is not set @@ -1017,13 +1004,11 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYCHORD is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set @@ -1052,7 +1037,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_N_GSM is not set # CONFIG_TRACE_SINK is not set -CONFIG_DEVMEM=y CONFIG_DEVKMEM=y # @@ -1083,7 +1067,6 @@ CONFIG_HW_RANDOM=y # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set -# CONFIG_DCC_TTY is not set # CONFIG_RAMOOPS is not set CONFIG_MXS_VIIM=y CONFIG_I2C=y @@ -1449,7 +1432,6 @@ CONFIG_VIDEO_MXC_IPU_OUTPUT=y # Graphics support # # CONFIG_DRM is not set -# CONFIG_ION is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y @@ -1787,8 +1769,6 @@ CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y # CONFIG_MMC_CLKGATE is not set -# CONFIG_MMC_EMBEDDED_SDIO is not set -# CONFIG_MMC_PARANOID_SD_INIT is not set # # MMC/SD/SDIO Card Drivers @@ -1796,7 +1776,6 @@ CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=8 CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set # CONFIG_SDIO_UART is not set # CONFIG_MMC_TEST is not set @@ -1813,7 +1792,6 @@ CONFIG_MMC_SDHCI_ESDHC_IMX=y # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_NFC_DEVICES is not set -# CONFIG_SWITCH is not set # CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y @@ -1828,8 +1806,6 @@ CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y -CONFIG_RTC_INTF_ALARM=y -CONFIG_RTC_INTF_ALARM_DEV=y # CONFIG_RTC_DRV_TEST is not set # @@ -1901,6 +1877,7 @@ CONFIG_DMADEVICES=y # CONFIG_MXC_PXP_V2 is not set # CONFIG_TIMB_DMA is not set CONFIG_IMX_SDMA=y +# CONFIG_MXS_DMA is not set CONFIG_DMA_ENGINE=y # @@ -1918,11 +1895,6 @@ CONFIG_STAGING=y # CONFIG_ASUS_OLED is not set # CONFIG_R8712U is not set # CONFIG_TRANZPORT is not set - -# -# Android -# -# CONFIG_ANDROID is not set # CONFIG_POHMELFS is not set # CONFIG_LINE6_USB is not set # CONFIG_VT6656 is not set @@ -2115,7 +2087,6 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_YAFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y @@ -2243,7 +2214,6 @@ CONFIG_DEBUG_FS=y # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_SPARSE_RCU_POINTER is not set -CONFIG_STACKTRACE=y CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig index 01f9bed4d721..78efc6b7563e 100644 --- a/arch/arm/configs/imx6s_defconfig +++ b/arch/arm/configs/imx6s_defconfig @@ -274,6 +274,8 @@ CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y CONFIG_IMX_HAVE_PLATFORM_AHCI=y CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y +CONFIG_IMX_HAVE_PLATFORM_IMX_DCP=y +CONFIG_IMX_HAVE_PLATFORM_RANDOM_RNGC=y CONFIG_IMX_HAVE_PLATFORM_PERFMON=y CONFIG_IMX_HAVE_PLATFORM_LDB=y CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y @@ -317,13 +319,14 @@ CONFIG_MACH_MX6Q_SABRESD=y # MX6 Options: # # CONFIG_IMX_PCIE is not set -# CONFIG_MX6_INTER_LDO_BYPASS is not set +CONFIG_MX6_INTER_LDO_BYPASS=y CONFIG_ISP1504_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set CONFIG_MXC_PWM=y # CONFIG_MXC_DEBUG_BOARD is not set # CONFIG_MXC_REBOOT_MFGMODE is not set # CONFIG_MXC_REBOOT_ANDROID_CMD is not set +CONFIG_ARCH_HAS_RNGC=y CONFIG_ARCH_MXC_IOMUX_V3=y CONFIG_ARCH_MXC_AUDMUX_V2=y CONFIG_IRAM_ALLOC=y @@ -1147,6 +1150,7 @@ CONFIG_FSL_OTP=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_HW_RANDOM_FSL_RNGC=y # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set @@ -2287,6 +2291,11 @@ CONFIG_ANATOP_THERMAL=y CONFIG_MXC_MIPI_CSI2=y # +# MXC HDMI CEC (Consumer Electronics Control) support +# +# CONFIG_MXC_HDMI_CEC is not set + +# # File systems # CONFIG_EXT2_FS=y @@ -2628,6 +2637,7 @@ CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_USER_API_SKCIPHER is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_FSL_CAAM is not set +CONFIG_CRYPTO_DEV_DCP=y # CONFIG_BINARY_PRINTF is not set # diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index d5070022a407..a9098ca89a33 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -211,6 +211,22 @@ extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t); */ extern void *dma_alloc_writethrough(struct device *, size_t, dma_addr_t *, gfp_t); + +#ifdef CONFIG_FSL_UTP +/** + * dma_alloc_noncacheable - allocate consistent memory for DMA + * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices + * @size: required memory size + * @handle: bus-specific DMA address + * + * Allocate some noncacheable memory, for a device for + * performing DMA. This function allocates pages, and will + * return the CPU-viewed address, and sets @handle to be the + * device-viewed address. + */ +extern void *dma_alloc_noncacheable(struct device *, size_t, dma_addr_t *, gfp_t); +#endif + /** * dma_free_coherent - free memory allocated by dma_alloc_coherent * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index 60843eb0f61c..73409e6c0251 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -7,6 +7,8 @@ .macro set_tls_v6k, tp, tmp1, tmp2 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register + mov \tmp1, #0 + mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register .endm .macro set_tls_v6, tp, tmp1, tmp2 @@ -15,6 +17,8 @@ mov \tmp2, #0xffff0fff tst \tmp1, #HWCAP_TLS @ hardware TLS available? mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register + movne \tmp1, #0 + mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 .endm diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 97260060bf26..172ae01c26e0 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -719,10 +719,13 @@ static int vfp_set(struct task_struct *target, { int ret; struct thread_info *thread = task_thread_info(target); - struct vfp_hard_struct new_vfp = thread->vfpstate.hard; + struct vfp_hard_struct new_vfp; const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); + vfp_sync_hwstate(thread); + new_vfp = thread->vfpstate.hard; + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &new_vfp.fpregs, user_fpregs_offset, @@ -743,9 +746,8 @@ static int vfp_set(struct task_struct *target, if (ret) return ret; - vfp_sync_hwstate(thread); - thread->vfpstate.hard = new_vfp; vfp_flush_hwstate(thread); + thread->vfpstate.hard = new_vfp; return 0; } diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 0340224cf73c..9e617bd4a146 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -227,6 +227,8 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) return -EINVAL; + vfp_flush_hwstate(thread); + /* * Copy the floating point registers. There can be unused * registers see asm/hwcap.h for details. @@ -251,9 +253,6 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); - if (!err) - vfp_flush_hwstate(thread); - return err ? -EFAULT : 0; } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 1d43ba28ebb5..24cdba4e9614 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -274,8 +274,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) struct mm_struct *mm = &init_mm; unsigned int cpu = smp_processor_id(); - printk("CPU%u: Booted secondary processor\n", cpu); - /* * All kernel threads share the same mm context; grab a * reference and switch to it. @@ -287,6 +285,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) enter_lazy_tlb(mm, current); local_flush_tlb_all(); + printk("CPU%u: Booted secondary processor\n", cpu); + cpu_init(); preempt_disable(); trace_hardirqs_off(); @@ -449,7 +449,9 @@ asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs) if (local_timer_ack()) { __inc_irq_stat(cpu, local_timer_irqs); + irq_enter(); ipi_timer(); + irq_exit(); } set_irq_regs(old_regs); diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 62e7c61d0342..0264ab433e9e 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -115,7 +115,7 @@ int kernel_execve(const char *filename, "Ir" (THREAD_START_SP - sizeof(regs)), "r" (®s), "Ir" (sizeof(regs)) - : "r0", "r1", "r2", "r3", "ip", "lr", "memory"); + : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory"); out: return ret; diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index cf7e5985eebf..46c044986294 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -31,6 +31,7 @@ #include <asm/mach/arch.h> #include <linux/irq.h> #include <plat/time.h> +#include <plat/ehci-orion.h> #include <plat/common.h> #include "common.h" @@ -74,7 +75,7 @@ void __init dove_map_io(void) void __init dove_ehci0_init(void) { orion_ehci_init(&dove_mbus_dram_info, - DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); + DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); } /***************************************************************************** diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 74ac88978ddd..a37fe021d69f 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -32,7 +32,7 @@ * Memory-mapped I/O on MX21ADS base board */ #define MX21ADS_MMIO_BASE_ADDR 0xf5000000 -#define MX21ADS_MMIO_SIZE SZ_16M +#define MX21ADS_MMIO_SIZE 0xc00000 #define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ (MX21ADS_MMIO_BASE_ADDR + (offset)) diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3248cfbe51d..c5dbbb35e0b1 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -28,6 +28,7 @@ #include <plat/cache-feroceon-l2.h> #include <plat/mvsdio.h> #include <plat/orion_nand.h> +#include <plat/ehci-orion.h> #include <plat/common.h> #include <plat/time.h> #include "common.h" @@ -74,7 +75,7 @@ void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; orion_ehci_init(&kirkwood_mbus_dram_info, - USB_PHYS_BASE, IRQ_KIRKWOOD_USB); + USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); } diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index ac787957e2d9..7afccf472205 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -31,313 +31,313 @@ #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 ) #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 ) #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 ) #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 ) #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 ) #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 ) #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 ) #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 ) #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 ) #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 ) #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 ) #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 ) #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) -#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 ) #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 ) #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 ) #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 ) #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 ) #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 ) #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 ) #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 ) #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 ) #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 ) #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 ) #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 ) #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 ) #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 ) #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 ) #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 ) #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 ) #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 ) #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 ) #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) -#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) -#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) -#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 ) #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 ) #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 ) #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 ) #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 ) #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 ) #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 ) #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) -#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 ) +#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 ) #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP_MAX 49 diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h index 2667f52e3b04..9e3b90df32e1 100644 --- a/arch/arm/mach-lpc32xx/include/mach/irqs.h +++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h @@ -61,7 +61,7 @@ */ #define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) #define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) -#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) +#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4) #define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) #define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) #define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 4eae566dfdc7..c74de01ab5b6 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { .event_group = &lpc32xx_event_pin_regs, .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, }, + [IRQ_LPC32XX_GPI_28] = { + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT, + }, [IRQ_LPC32XX_GPIO_00] = { .event_group = &lpc32xx_event_int_regs, .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, @@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) if (state) eventreg |= lpc32xx_events[d->irq].mask; - else + else { eventreg &= ~lpc32xx_events[d->irq].mask; + /* + * When disabling the wakeup, clear the latched + * event + */ + __raw_writel(lpc32xx_events[d->irq].mask, + lpc32xx_events[d->irq]. + event_group->rawstat_reg); + } + __raw_writel(eventreg, lpc32xx_events[d->irq].event_group->enab_reg); @@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void) /* Setup SIC1 */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); + __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); + __raw_writel(SIC1_ATR_DEFAULT, + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); /* Setup SIC2 */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); + __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); + __raw_writel(SIC2_ATR_DEFAULT, + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); /* Configure supported IRQ's */ for (i = 0; i < NR_IRQS; i++) { diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index 429cfdbb2b3d..f2735281616a 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -88,6 +88,7 @@ struct uartinit { char *uart_ck_name; u32 ck_mode_mask; void __iomem *pdiv_clk_reg; + resource_size_t mapbase; }; static struct uartinit uartinit_data[] __initdata = { @@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = { .ck_mode_mask = LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, + .mapbase = LPC32XX_UART5_BASE, }, #endif #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT @@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = { .ck_mode_mask = LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, + .mapbase = LPC32XX_UART3_BASE, }, #endif #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT @@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = { .ck_mode_mask = LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, + .mapbase = LPC32XX_UART4_BASE, }, #endif #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT @@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = { .ck_mode_mask = LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, + .mapbase = LPC32XX_UART6_BASE, }, #endif }; @@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void) /* pre-UART clock divider set to 1 */ __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); + + /* + * Force a flush of the RX FIFOs to work around a + * HW bug + */ + puart = uartinit_data[i].mapbase; + __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); + __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); + j = LPC32XX_SUART_FIFO_SIZE; + while (j--) + tmp = __raw_readl( + LPC32XX_UART_DLL_FIFO(puart)); + __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); } /* This needs to be done after all UART clocks are setup */ __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); - for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { + for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { /* Force a flush of the RX FIFOs to work around a HW bug */ puart = serial_std_platform_data[i].mapbase; __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 23d3980ef59d..d90e244e05e7 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -20,6 +20,7 @@ #include <mach/mv78xx0.h> #include <mach/bridge-regs.h> #include <plat/cache-feroceon-l2.h> +#include <plat/ehci-orion.h> #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> @@ -170,7 +171,7 @@ void __init mv78xx0_map_io(void) void __init mv78xx0_ehci0_init(void) { orion_ehci_init(&mv78xx0_mbus_dram_info, - USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); + USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); } diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h index b61b50927123..3752302ae2ee 100644 --- a/arch/arm/mach-mv78xx0/mpp.h +++ b/arch/arm/mach-mv78xx0/mpp.h @@ -24,296 +24,296 @@ #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) -#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) -#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) +#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) -#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) -#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) +#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) -#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) -#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) +#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) +#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) -#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) -#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) +#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) -#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) -#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) -#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) -#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) -#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) -#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) -#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) -#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) -#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) -#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) +#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) +#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) -#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) -#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) +#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) +#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) -#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) -#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) +#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) +#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) -#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) -#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) +#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) +#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) -#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) -#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) -#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) -#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) +#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) +#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) -#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) -#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) -#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) -#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) -#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) -#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) -#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) -#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) +#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) -#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) -#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) -#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) -#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) +#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) -#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) -#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) -#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) -#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) +#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) -#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) -#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) -#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) -#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) +#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) -#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) -#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) +#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) -#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) -#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) -#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) -#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) +#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) +#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) -#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) -#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) +#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) -#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) -#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) -#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) +#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) -#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) -#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) -#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) +#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) -#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) -#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) +#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) -#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) -#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) +#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) -#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) -#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) +#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) +#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) -#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) -#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) +#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) -#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) -#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) +#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) -#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) -#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) -#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) +#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) -#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) +#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) -#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) -#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) -#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) -#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) -#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) -#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) -#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) +#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) -#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) -#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) -#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) -#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) +#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) -#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) -#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) -#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) +#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) -#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) -#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) -#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) -#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) +#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) -#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) -#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) -#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) -#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) +#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) -#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) -#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) -#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) -#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) +#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) +#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) -#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) +#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) -#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) -#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) +#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) -#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) +#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) -#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) +#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) -#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) -#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) -#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) @@ -323,14 +323,14 @@ #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) -#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) -#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) -#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) +#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig index a96597d2d599..5c60c560f03a 100644 --- a/arch/arm/mach-mx6/Kconfig +++ b/arch/arm/mach-mx6/Kconfig @@ -65,6 +65,7 @@ config MACH_MX6Q_ARM2 select IMX_HAVE_PLATFORM_IMX_ELCDIF select IMX_HAVE_PLATFORM_IMX_PXP select IMX_HAVE_PLATFORM_IMX_PCIE + select IMX_HAVE_PLATFORM_IMX_CAAM help Include support for i.MX 6Quad Armadillo2 platform. This includes specific configurations for the board and its peripherals. @@ -99,6 +100,9 @@ config MACH_MX6SL_ARM2 select IMX_HAVE_PLATFORM_IMX_SPDC select IMX_HAVE_PLATFORM_IMX_PXP select IMX_HAVE_PLATFORM_IMX_KEYPAD + select IMX_HAVE_PLATFORM_IMX_DCP + select IMX_HAVE_PLATFORM_RANDOM_RNGC + select ARCH_HAS_RNGC help Include support for i.MX 6Sololite Armadillo2 platform. This includes specific configurations for the board and its peripherals. @@ -131,6 +135,7 @@ config MACH_MX6Q_SABRELITE select IMX_HAVE_PLATFORM_MXC_HDMI select IMX_HAVE_PLATFORM_IMX_ASRC select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_IMX_CAAM help Include support for i.MX 6Quad SABRE Lite platform. This includes specific configurations for the board and its peripherals. @@ -164,6 +169,7 @@ config MACH_MX6Q_SABRESD select IMX_HAVE_PLATFORM_IMX_ASRC select IMX_HAVE_PLATFORM_FLEXCAN select IMX_HAVE_PLATFORM_IMX_PCIE + select IMX_HAVE_PLATFORM_IMX_CAAM help Include support for i.MX 6Quad SABRE SD platform. This includes specific configurations for the board and its peripherals. @@ -200,6 +206,8 @@ config MACH_MX6Q_SABREAUTO select IMX_HAVE_PLATFORM_IMX_MIPI_DSI select IMX_HAVE_PLATFORM_FLEXCAN select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2 + select IMX_HAVE_PLATFORM_IMX_PCIE + select IMX_HAVE_PLATFORM_IMX_CAAM help Include support for i.MX 6Quad SABRE Auto platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx6/board-mx6dl_arm2.h b/arch/arm/mach-mx6/board-mx6dl_arm2.h index 4528da53694a..6ed3e65e68ee 100644 --- a/arch/arm/mach-mx6/board-mx6dl_arm2.h +++ b/arch/arm/mach-mx6/board-mx6dl_arm2.h @@ -319,3 +319,13 @@ static iomux_v3_cfg_t mx6dl_gpmi_nand[] __initdata = { MX6DL_PAD_SD4_CLK__RAWNAND_WRN, MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN, }; + +static iomux_v3_cfg_t mx6dl_arm2_hdmi_ddc_pads[] = { + MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6dl_arm2_i2c2_pads[] = { + MX6DL_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6DL_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; diff --git a/arch/arm/mach-mx6/board-mx6dl_sabresd.h b/arch/arm/mach-mx6/board-mx6dl_sabresd.h index 35701a4979d4..7e6a26143a49 100644 --- a/arch/arm/mach-mx6/board-mx6dl_sabresd.h +++ b/arch/arm/mach-mx6/board-mx6dl_sabresd.h @@ -390,4 +390,13 @@ static iomux_v3_cfg_t mx6dl_arm2_elan_pads[] = { MX6DL_PAD_EIM_D28__GPIO_3_28, }; +static iomux_v3_cfg_t mx6dl_sabresd_hdmi_ddc_pads[] = { + MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6dl_sabresd_i2c2_pads[] = { + MX6DL_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6DL_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; #endif diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c index 2bfd23e6085b..c335e5e451c0 100644 --- a/arch/arm/mach-mx6/board-mx6q_arm2.c +++ b/arch/arm/mach-mx6/board-mx6q_arm2.c @@ -77,7 +77,6 @@ #include "devices-imx6q.h" #include "crm_regs.h" #include "cpu_op-mx6.h" - #include "board-mx6q_arm2.h" #include "board-mx6dl_arm2.h" @@ -1413,8 +1412,34 @@ static void hdmi_init(int ipu_id, int disp_id) mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting); } +/* On mx6x arm2 board i2c2 iomux with hdmi ddc, + * the pins default work at i2c2 function, + when hdcp enable, the pins should work at ddc function */ + +static void hdmi_enable_ddc_pin(void) +{ + if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_hdmi_ddc_pads, + ARRAY_SIZE(mx6dl_arm2_hdmi_ddc_pads)); + else + mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_hdmi_ddc_pads, + ARRAY_SIZE(mx6q_arm2_hdmi_ddc_pads)); +} + +static void hdmi_disable_ddc_pin(void) +{ + if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_i2c2_pads, + ARRAY_SIZE(mx6dl_arm2_i2c2_pads)); + else + mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_i2c2_pads, + ARRAY_SIZE(mx6q_arm2_i2c2_pads)); +} + static struct fsl_mxc_hdmi_platform_data hdmi_data = { - .init = hdmi_init, + .init = hdmi_init, + .enable_pins = hdmi_enable_ddc_pin, + .disable_pins = hdmi_disable_ddc_pin, }; static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = { @@ -2184,6 +2209,7 @@ static void __init mx6_arm2_init(void) mxc_register_device(&max17135_sensor_device, NULL); imx6dl_add_imx_epdc(&epdc_data); } + /* Add PCIe RC interface support */ imx6q_add_pcie(&mx6_arm2_pcie_data); imx6q_add_busfreq(); } diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.h b/arch/arm/mach-mx6/board-mx6q_arm2.h index 8c3277d869e1..eb06ef89bdd8 100644 --- a/arch/arm/mach-mx6/board-mx6q_arm2.h +++ b/arch/arm/mach-mx6/board-mx6q_arm2.h @@ -315,3 +315,13 @@ static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = { MX6Q_PAD_SD4_CLK__RAWNAND_WRN, MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN, }; + +static iomux_v3_cfg_t mx6q_arm2_hdmi_ddc_pads[] = { + MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6q_arm2_i2c2_pads[] = { + MX6Q_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c index 2e5cf702a23b..7d2eab2c89f2 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c @@ -104,6 +104,7 @@ #define SABREAUTO_CSI0_RST IMX_GPIO_NR(4, 5) #define SABREAUTO_DISP0_RESET IMX_GPIO_NR(5, 0) #define SABREAUTO_I2C3_STEER IMX_GPIO_NR(5, 4) +#define SABREAUTO_WEIM_NOR_WDOG1 IMX_GPIO_NR(4, 29) #define SABREAUTO_ANDROID_VOLDOWN IMX_GPIO_NR(5, 14) #define SABREAUTO_PMIC_INT IMX_GPIO_NR(5, 16) #define SABREAUTO_ALS_INT IMX_GPIO_NR(5, 17) @@ -120,6 +121,7 @@ #define SABREAUTO_IO_EXP_GPIO2(x) (SABREAUTO_MAX7310_2_BASE_ADDR + (x)) #define SABREAUTO_IO_EXP_GPIO3(x) (SABREAUTO_MAX7310_3_BASE_ADDR + (x)) +#define SABREAUTO_PCIE_RST_B_REVB (SABREAUTO_MAX7310_1_BASE_ADDR + 2) /* * CAN2 STBY and EN lines are the same as the CAN1. These lines are not * independent. @@ -140,6 +142,7 @@ static int can0_enable; static int uart3_en; static int tuner_en; static int spinor_en; +static int weimnor_en; static int __init spinor_enable(char *p) { @@ -148,6 +151,13 @@ static int __init spinor_enable(char *p) } early_param("spi-nor", spinor_enable); +static int __init weimnor_enable(char *p) +{ + weimnor_en = 1; + return 0; +} +early_param("weim-nor", weimnor_enable); + static int __init uart3_enable(char *p) { uart3_en = 1; @@ -903,8 +913,34 @@ static void hdmi_init(int ipu_id, int disp_id) mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting); } +/* On mx6x sabreauto board i2c2 iomux with hdmi ddc, + * the pins default work at i2c2 function, + when hdcp enable, the pins should work at ddc function */ + +static void hdmi_enable_ddc_pin(void) +{ + if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_multiple_pads(mx6dl_sabreauto_hdmi_ddc_pads, + ARRAY_SIZE(mx6dl_sabreauto_hdmi_ddc_pads)); + else + mxc_iomux_v3_setup_multiple_pads(mx6q_sabreauto_hdmi_ddc_pads, + ARRAY_SIZE(mx6q_sabreauto_hdmi_ddc_pads)); +} + +static void hdmi_disable_ddc_pin(void) +{ + if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_multiple_pads(mx6dl_sabreauto_i2c2_pads, + ARRAY_SIZE(mx6dl_sabreauto_i2c2_pads)); + else + mxc_iomux_v3_setup_multiple_pads(mx6q_sabreauto_i2c2_pads, + ARRAY_SIZE(mx6q_sabreauto_i2c2_pads)); +} + static struct fsl_mxc_hdmi_platform_data hdmi_data = { .init = hdmi_init, + .enable_pins = hdmi_enable_ddc_pin, + .disable_pins = hdmi_disable_ddc_pin, }; static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = { @@ -1300,6 +1336,12 @@ static struct fsl_mxc_capture_platform_data capture_data[] = { }, }; +static const struct imx_pcie_platform_data mx6_sabreauto_pcie_data __initconst = { + .pcie_pwr_en = -EINVAL, + .pcie_rst = SABREAUTO_PCIE_RST_B_REVB, + .pcie_wake_up = -EINVAL, + .pcie_dis = -EINVAL, +}; /*! * Board specific initialization. @@ -1314,6 +1356,8 @@ static void __init mx6_board_init(void) iomux_v3_cfg_t *mipi_sensor_pads = NULL; iomux_v3_cfg_t *i2c3_pads = NULL; iomux_v3_cfg_t *tuner_pads = NULL; + iomux_v3_cfg_t *spinor_pads = NULL; + iomux_v3_cfg_t *weimnor_pads = NULL; int common_pads_cnt; int can0_pads_cnt; @@ -1321,6 +1365,8 @@ static void __init mx6_board_init(void) int mipi_sensor_pads_cnt; int i2c3_pads_cnt; int tuner_pads_cnt; + int spinor_pads_cnt; + int weimnor_pads_cnt; if (cpu_is_mx6q()) { common_pads = mx6q_sabreauto_pads; @@ -1328,12 +1374,16 @@ static void __init mx6_board_init(void) can1_pads = mx6q_sabreauto_can1_pads; mipi_sensor_pads = mx6q_sabreauto_mipi_sensor_pads; tuner_pads = mx6q_tuner_pads; + spinor_pads = mx6q_spinor_pads; + weimnor_pads = mx6q_weimnor_pads; common_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_pads); can0_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can0_pads); can1_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can1_pads); mipi_sensor_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_mipi_sensor_pads); tuner_pads_cnt = ARRAY_SIZE(mx6q_tuner_pads); + spinor_pads_cnt = ARRAY_SIZE(mx6q_spinor_pads); + weimnor_pads_cnt = ARRAY_SIZE(mx6q_weimnor_pads); if (board_is_mx6_reva()) { i2c3_pads = mx6q_i2c3_pads_rev_a; i2c3_pads_cnt = ARRAY_SIZE(mx6q_i2c3_pads_rev_a); @@ -1347,12 +1397,17 @@ static void __init mx6_board_init(void) can1_pads = mx6dl_sabreauto_can1_pads; mipi_sensor_pads = mx6dl_sabreauto_mipi_sensor_pads; tuner_pads = mx6dl_tuner_pads; + spinor_pads = mx6dl_spinor_pads; + weimnor_pads = mx6dl_weimnor_pads; common_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_pads); can0_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can0_pads); can1_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can1_pads); mipi_sensor_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_mipi_sensor_pads); tuner_pads_cnt = ARRAY_SIZE(mx6dl_tuner_pads); + spinor_pads_cnt = ARRAY_SIZE(mx6dl_spinor_pads); + weimnor_pads_cnt = ARRAY_SIZE(mx6dl_weimnor_pads); + if (board_is_mx6_reva()) { i2c3_pads = mx6dl_i2c3_pads_rev_a; i2c3_pads_cnt = ARRAY_SIZE(mx6dl_i2c3_pads_rev_a); @@ -1364,11 +1419,19 @@ static void __init mx6_board_init(void) BUG_ON(!common_pads); mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt); - if (!spinor_en) { + + /*If at least one NOR memory is selected we don't configure IC23 PADS*/ + if (spinor_en) { + BUG_ON(!spinor_pads); + mxc_iomux_v3_setup_multiple_pads(spinor_pads, spinor_pads_cnt); + } else if (weimnor_en) { + BUG_ON(!weimnor_pads); + mxc_iomux_v3_setup_multiple_pads(weimnor_pads, + weimnor_pads_cnt); + } else { BUG_ON(!i2c3_pads); mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt); } - if (can0_enable) { BUG_ON(!can0_pads); mxc_iomux_v3_setup_multiple_pads(can0_pads, @@ -1388,12 +1451,19 @@ static void __init mx6_board_init(void) gpio_direction_output(SABREAUTO_I2C_EXP_RST, 1); if (!board_is_mx6_reva()) { - /* enable i2c3_sda route path */ + /* enable either EIM_D18 or i2c3_sda route path */ gpio_request(SABREAUTO_I2C3_STEER, "i2c3-steer"); if (spinor_en) gpio_direction_output(SABREAUTO_I2C3_STEER, 0); - else - gpio_direction_output(SABREAUTO_I2C3_STEER, 1); + else if (weimnor_en) { + /*Put DISP0_DAT8 in ALT5 mode to prevent WDOG1 of + resetting WEIM NOR*/ + gpio_direction_output(SABREAUTO_I2C3_STEER, 0); + + gpio_request(SABREAUTO_WEIM_NOR_WDOG1, "nor-reset"); + gpio_direction_output(SABREAUTO_WEIM_NOR_WDOG1, 1); + } else + gpio_direction_output(SABREAUTO_I2C3_STEER, 1); /* Set GPIO_16 input for IEEE-1588 ts_clk and * RMII reference clk * For MX6 GPR1 bit21 meaning: @@ -1443,6 +1513,8 @@ static void __init mx6_board_init(void) imx6q_add_imx_snvs_rtc(); + imx6q_add_imx_caam(); + imx6q_add_imx_i2c(1, &mx6q_sabreauto_i2c1_data); i2c_register_board_info(1, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); @@ -1461,10 +1533,10 @@ static void __init mx6_board_init(void) /* SPI */ imx6q_add_ecspi(0, &mx6q_sabreauto_spi_data); #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - spi_device_init(); + spi_device_init(); #else - mx6q_setup_weimcs(); - platform_device_register(&physmap_flash_device); + mx6q_setup_weimcs(); + platform_device_register(&physmap_flash_device); #endif imx6q_add_mxc_hdmi(&hdmi_data); @@ -1547,6 +1619,13 @@ static void __init mx6_board_init(void) mxc_register_device(&mxc_si4763_audio_device, &si4763_audio_data); imx6q_add_busfreq(); + + /* Add PCIe RC interface support */ + imx6q_add_pcie(&mx6_sabreauto_pcie_data); + + imx6q_add_perfmon(0); + imx6q_add_perfmon(1); + imx6q_add_perfmon(2); } extern void __iomem *twd_base; diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h index bffd109115c2..da6e4387d781 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h @@ -215,69 +215,6 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = { MX6Q_PAD_ENET_TXD1__MLB_MLBCLK, MX6Q_PAD_GPIO_6__MLB_MLBSIG, MX6Q_PAD_GPIO_2__MLB_MLBDAT, - -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - /* eCSPI1 */ - MX6Q_PAD_EIM_D16__ECSPI1_SCLK, - MX6Q_PAD_EIM_D17__ECSPI1_MISO, - MX6Q_PAD_EIM_D18__ECSPI1_MOSI, - MX6Q_PAD_EIM_D19__ECSPI1_SS1, - MX6Q_PAD_EIM_D19__GPIO_3_19, /*SS1*/ -#else - /* Parallel NOR */ - MX6Q_PAD_EIM_OE__WEIM_WEIM_OE, - MX6Q_PAD_EIM_RW__WEIM_WEIM_RW, - MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT, - MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0, - - MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA, - MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK, - /* Parallel Nor Data Bus */ - MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16, - MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17, - MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18, - MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19, - MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20, - MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21, - MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22, - MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23, - MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24, - MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25, - MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26, - MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27, - MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28, - MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29, - MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30, - MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31, - - /* Parallel Nor 25 bit Address Bus */ - MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24, - MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23, - MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22, - MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21, - MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20, - MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19, - MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18, - MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17, - MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16, - - MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, - MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, - MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, - MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, - MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, - MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, - MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, - MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, - MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, - MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, - MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, - MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, - MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, - MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, - MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, - MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, -#endif }; static iomux_v3_cfg_t mx6q_sabreauto_can0_pads[] = { @@ -355,3 +292,80 @@ static iomux_v3_cfg_t mx6q_tuner_pads[] __initdata = { }; +static iomux_v3_cfg_t mx6q_spinor_pads[] __initdata = { + /* eCSPI1 */ + MX6Q_PAD_EIM_D16__ECSPI1_SCLK, + MX6Q_PAD_EIM_D17__ECSPI1_MISO, + MX6Q_PAD_EIM_D18__ECSPI1_MOSI, + MX6Q_PAD_EIM_D19__ECSPI1_SS1, + + MX6Q_PAD_EIM_D19__GPIO_3_19, +}; + +static iomux_v3_cfg_t mx6q_weimnor_pads[] __initdata = { + /* Parallel NOR */ + MX6Q_PAD_EIM_OE__WEIM_WEIM_OE, + MX6Q_PAD_EIM_RW__WEIM_WEIM_RW, + MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT, + MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0, + /*Control NOR reset using gpio mode*/ + MX6Q_PAD_DISP0_DAT8__GPIO_4_29, + + MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA, + MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK, + /* Parallel Nor Data Bus */ + MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16, + MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17, + MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18, + MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19, + MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20, + MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21, + MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22, + MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23, + MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24, + MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25, + MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26, + MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27, + MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28, + MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29, + MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30, + MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31, + + /* Parallel Nor 25 bit Address Bus */ + MX6Q_PAD_EIM_A24__GPIO_5_4, + MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23, + MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22, + MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21, + MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20, + MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19, + MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18, + MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17, + MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16, + + MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, + MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, + MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, + MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, + MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, + MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, + MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, + MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, + MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, + MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, + MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, + MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, + MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, + MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, + MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, + MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, +}; + +static iomux_v3_cfg_t mx6q_sabreauto_hdmi_ddc_pads[] = { + MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6q_sabreauto_i2c2_pads[] = { + MX6Q_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c index 3f00ae563492..925dfb71ea0e 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c +++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c @@ -327,6 +327,16 @@ static iomux_v3_cfg_t mx6q_sabrelite_csi0_sensor_pads[] = { MX6Q_PAD_NANDF_WP_B__GPIO_6_9, /* J16 - MIPI GP */ }; +static iomux_v3_cfg_t mx6q_sabrelite_hdmi_ddc_pads[] = { + MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6q_sabrelite_i2c2_pads[] = { + MX6Q_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; + #define MX6Q_USDHC_PAD_SETTING(id, speed) \ mx6q_sd##id##_##speed##mhz[] = { \ MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ, \ @@ -804,8 +814,26 @@ static void hdmi_init(int ipu_id, int disp_id) mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting); } +/* On mx6x sbarelite board i2c2 iomux with hdmi ddc, + * the pins default work at i2c2 function, + when hdcp enable, the pins should work at ddc function */ + +static void hdmi_enable_ddc_pin(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_hdmi_ddc_pads, + ARRAY_SIZE(mx6q_sabrelite_hdmi_ddc_pads)); +} + +static void hdmi_disable_ddc_pin(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_i2c2_pads, + ARRAY_SIZE(mx6q_sabrelite_i2c2_pads)); +} + static struct fsl_mxc_hdmi_platform_data hdmi_data = { .init = hdmi_init, + .enable_pins = hdmi_enable_ddc_pin, + .disable_pins = hdmi_disable_ddc_pin, }; static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = { @@ -1145,6 +1173,8 @@ static void __init mx6_sabrelite_board_init(void) imx6q_add_mipi_csi2(&mipi_csi2_pdata); imx6q_add_imx_snvs_rtc(); + imx6q_add_imx_caam(); + imx6q_add_imx_i2c(0, &mx6q_sabrelite_i2c_data); imx6q_add_imx_i2c(1, &mx6q_sabrelite_i2c_data); imx6q_add_imx_i2c(2, &mx6q_sabrelite_i2c_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c index 955f47e7ab8c..e03777884aa3 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabresd.c +++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c @@ -1277,8 +1277,34 @@ static void hdmi_init(int ipu_id, int disp_id) mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting); } +/* On mx6x sabresd board i2c2 iomux with hdmi ddc, + * the pins default work at i2c2 function, + when hdcp enable, the pins should work at ddc function */ + +static void hdmi_enable_ddc_pin(void) +{ + if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_hdmi_ddc_pads, + ARRAY_SIZE(mx6dl_sabresd_hdmi_ddc_pads)); + else + mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_hdmi_ddc_pads, + ARRAY_SIZE(mx6q_sabresd_hdmi_ddc_pads)); +} + +static void hdmi_disable_ddc_pin(void) +{ + if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_i2c2_pads, + ARRAY_SIZE(mx6dl_sabresd_i2c2_pads)); + else + mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_i2c2_pads, + ARRAY_SIZE(mx6q_sabresd_i2c2_pads)); +} + static struct fsl_mxc_hdmi_platform_data hdmi_data = { .init = hdmi_init, + .enable_pins = hdmi_enable_ddc_pin, + .disable_pins = hdmi_disable_ddc_pin, }; static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = { @@ -1702,6 +1728,8 @@ static void __init mx6_sabresd_board_init(void) imx6q_add_mipi_csi2(&mipi_csi2_pdata); imx6q_add_imx_snvs_rtc(); + imx6q_add_imx_caam(); + if (board_is_mx6_reva()) { strcpy(mxc_i2c0_board_info[0].type, "wm8958"); mxc_i2c0_board_info[0].platform_data = &wm8958_config_data; @@ -1737,6 +1765,7 @@ static void __init mx6_sabresd_board_init(void) imx6q_add_anatop_thermal_imx(1, &mx6q_sabresd_anatop_thermal_data); imx6_init_fec(fec_data); imx6q_add_pm_imx(0, &mx6q_sabresd_pm_data); + /* Move sd4 to first because sd4 connect to emmc. Mfgtools want emmc is mmcblk0 and other sd card is mmcblk1. */ @@ -1842,6 +1871,7 @@ static void __init mx6_sabresd_board_init(void) pm_power_off = mx6_snvs_poweroff; imx6q_add_busfreq(); + /* Add PCIe RC interface support */ imx6q_add_pcie(&mx6_sabresd_pcie_data); if (cpu_is_mx6dl()) { mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_elan_pads, @@ -1872,6 +1902,10 @@ static void __init mx6_sabresd_board_init(void) sdio_clk->flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; clk_put(sdio_clk); } + imx6_add_armpmu(); + imx6q_add_perfmon(0); + imx6q_add_perfmon(1); + imx6q_add_perfmon(2); } extern void __iomem *twd_base; diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.h b/arch/arm/mach-mx6/board-mx6q_sabresd.h index af3df8b01092..54ad3ac416b6 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabresd.h +++ b/arch/arm/mach-mx6/board-mx6q_sabresd.h @@ -28,7 +28,7 @@ static iomux_v3_cfg_t mx6q_sabresd_pads[] = { MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD, /* CAN1 */ - MX6Q_PAD_KEY_ROW2__CAN1_RXCAN, + MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE, /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN, */ MX6Q_PAD_GPIO_1__GPIO_1_1, /* user defiend green led */ MX6Q_PAD_GPIO_2__GPIO_1_2, /* user defined red led */ @@ -128,9 +128,9 @@ static iomux_v3_cfg_t mx6q_sabresd_pads[] = { MX6Q_PAD_CSI0_DAT8__I2C1_SDA, MX6Q_PAD_CSI0_DAT9__I2C1_SCL, - /* I2C2 Camera, MIPI */ - MX6Q_PAD_KEY_COL3__I2C2_SCL, /* GPIO4[12] */ - MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* GPIO4[13] */ + /* I2C2, Camera, MIPI */ + MX6Q_PAD_KEY_COL3__I2C2_SCL, + MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* I2C3 */ MX6Q_PAD_GPIO_3__I2C3_SCL, /* GPIO1[3] */ @@ -288,4 +288,14 @@ static iomux_v3_cfg_t mx6q_sabresd_mipi_sensor_pads[] = { MX6Q_PAD_SD1_DAT2__GPIO_1_19, /* camera PWDN */ MX6Q_PAD_SD1_CLK__GPIO_1_20, /* camera RESET */ }; + +static iomux_v3_cfg_t mx6q_sabresd_hdmi_ddc_pads[] = { + MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6q_sabresd_i2c2_pads[] = { + MX6Q_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6Q_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; #endif diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c index 2507970133eb..2efca1ba5d93 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.c +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c @@ -129,6 +129,7 @@ #define MX6SL_ARM2_ELAN_INT IMX_GPIO_NR(2, 10) #define MX6SL_ARM2_ELAN_RST IMX_GPIO_NR(4, 4) +static int spdc_sel; static int max17135_regulator_init(struct max17135 *max17135); struct clk *extern_audio_root; @@ -670,23 +671,17 @@ static int mx6sl_arm2_fec_phy_init(struct phy_device *phydev) /* power on FEC phy and reset phy */ gpio_request(MX6_ARM2_FEC_PWR_EN, "fec-pwr"); - gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 1); + gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 0); /* wait RC ms for hw reset */ - udelay(50); + msleep(1); + gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 1); /* check phy power */ val = phy_read(phydev, 0x0); if (val & BMCR_PDOWN) { phy_write(phydev, 0x0, (val & ~BMCR_PDOWN)); - udelay(50); } - /* sw reset phy */ - val = phy_read(phydev, 0x0); - val |= BMCR_RESET; - phy_write(phydev, 0x0, val); - udelay(50); - return 0; } @@ -1084,13 +1079,19 @@ static struct imx_spdc_fb_platform_data spdc_data = { .disable_pins = spdc_disable_pins, }; -#if defined(CONFIG_FB_MXC_SIPIX_PANEL) +static int __init early_use_spdc_sel(char *p) +{ + spdc_sel = 1; + return 0; +} +early_param("spdc", early_use_spdc_sel); + static void setup_spdc(void) { /* GPR0[8]: 0:EPDC, 1:SPDC */ - mxc_iomux_set_gpr_register(0, 8, 1, 1); + if (spdc_sel) + mxc_iomux_set_gpr_register(0, 8, 1, 1); } -#endif static void imx6_arm2_usbotg_vbus(bool on) { @@ -1207,6 +1208,17 @@ static void __init elan_ts_init(void) gpio_direction_output(MX6SL_ARM2_ELAN_CE, 1); } +#define SNVS_LPCR 0x38 +static void mx6_snvs_poweroff(void) +{ + u32 value; + void __iomem *mx6_snvs_base = MX6_IO_ADDRESS(MX6Q_SNVS_BASE_ADDR); + + value = readl(mx6_snvs_base + SNVS_LPCR); + /* set TOP and DP_EN bit */ + writel(value | 0x60, mx6_snvs_base + SNVS_LPCR); +} + /*! * Board specific initialization. */ @@ -1270,14 +1282,14 @@ static void __init mx6_arm2_init(void) imx6dl_add_imx_pxp(); imx6dl_add_imx_pxp_client(); mxc_register_device(&max17135_sensor_device, NULL); - imx6dl_add_imx_epdc(&epdc_data); -#if defined(CONFIG_FB_MXC_SIPIX_PANEL) setup_spdc(); -#endif - imx6sl_add_imx_spdc(&spdc_data); + if (!spdc_sel) + imx6dl_add_imx_epdc(&epdc_data); + else + imx6sl_add_imx_spdc(&spdc_data); imx6q_add_dvfs_core(&mx6sl_arm2_dvfscore_data); - imx6q_init_audio(); + imx6q_init_audio(); imx6q_add_viim(); imx6q_add_imx2_wdt(0, NULL); @@ -1285,6 +1297,10 @@ static void __init mx6_arm2_init(void) imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata); imx6sl_add_imx_keypad(&mx6sl_arm2_map_data); imx6q_add_busfreq(); + imx6sl_add_dcp(); + imx6sl_add_rngb(); + + pm_power_off = mx6_snvs_poweroff; } extern void __iomem *twd_base; diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_arm2.h index d720ab3465b6..09a211690029 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.h +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.h @@ -153,6 +153,9 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = { MX6SL_PAD_KEY_ROW1__KPP_ROW_1, MX6SL_PAD_KEY_ROW2__KPP_ROW_2, MX6SL_PAD_KEY_ROW3__KPP_ROW_3, + + /* WDOG */ + MX6SL_PAD_WDOG_B__WDOG1_WDOG_B, }; static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = { diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h index dd113bab749b..f51925bee9fa 100644 --- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h @@ -215,70 +215,6 @@ static iomux_v3_cfg_t mx6dl_sabreauto_pads[] = { MX6DL_PAD_ENET_TXD1__MLB_MLBCLK, MX6DL_PAD_GPIO_6__MLB_MLBSIG, MX6DL_PAD_GPIO_2__MLB_MLBDAT, - -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - /* eCSPI1 */ - MX6DL_PAD_EIM_D16__ECSPI1_SCLK, - MX6DL_PAD_EIM_D17__ECSPI1_MISO, - MX6DL_PAD_EIM_D18__ECSPI1_MOSI, - MX6DL_PAD_EIM_D19__ECSPI1_SS1, - - MX6DL_PAD_EIM_D19__GPIO_3_19, -#else - /* Parallel NOR */ - MX6DL_PAD_EIM_OE__WEIM_WEIM_OE, - MX6DL_PAD_EIM_RW__WEIM_WEIM_RW, - MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT, - MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0, - - MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA, - MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK, - /* Parallel Nor Data Bus */ - MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16, - MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17, - MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18, - MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19, - MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20, - MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21, - MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22, - MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23, - MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24, - MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25, - MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26, - MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27, - MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28, - MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29, - MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30, - MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31, - - /* Parallel Nor 25 bit Address Bus */ - MX6DL_PAD_EIM_A24__WEIM_WEIM_A_24, - MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23, - MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22, - MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21, - MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20, - MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19, - MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18, - MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17, - MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16, - - MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, - MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, - MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, - MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, - MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, - MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, - MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, - MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, - MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, - MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, - MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, - MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, - MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, - MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, - MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, - MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, -#endif }; static iomux_v3_cfg_t mx6dl_sabreauto_can0_pads[] = { @@ -355,3 +291,81 @@ static iomux_v3_cfg_t mx6dl_tuner_pads[] __initdata = { MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS, MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD, }; + +static iomux_v3_cfg_t mx6dl_spinor_pads[] __initdata = { + /* eCSPI1 */ + MX6DL_PAD_EIM_D16__ECSPI1_SCLK, + MX6DL_PAD_EIM_D17__ECSPI1_MISO, + MX6DL_PAD_EIM_D18__ECSPI1_MOSI, + MX6DL_PAD_EIM_D19__ECSPI1_SS1, + + MX6DL_PAD_EIM_D19__GPIO_3_19, +}; + +static iomux_v3_cfg_t mx6dl_weimnor_pads[] __initdata = { + /* Parallel NOR */ + MX6DL_PAD_EIM_OE__WEIM_WEIM_OE, + MX6DL_PAD_EIM_RW__WEIM_WEIM_RW, + MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT, + MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0, + /*Control NOR reset using gpio mode*/ + MX6DL_PAD_DISP0_DAT8__GPIO_4_29, + + MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA, + MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK, + /* Parallel Nor Data Bus */ + MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16, + MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17, + MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18, + MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19, + MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20, + MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21, + MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22, + MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23, + MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24, + MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25, + MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26, + MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27, + MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28, + MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29, + MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30, + MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31, + + /* Parallel Nor 25 bit Address Bus */ + MX6DL_PAD_EIM_A24__GPIO_5_4, + MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23, + MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22, + MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21, + MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20, + MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19, + MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18, + MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17, + MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16, + + MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, + MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, + MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, + MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, + MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, + MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, + MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, + MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, + MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, + MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, + MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, + MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, + MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, + MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, + MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, + MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, +}; + +static iomux_v3_cfg_t mx6dl_sabreauto_hdmi_ddc_pads[] = { + MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */ + MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */ +}; + +static iomux_v3_cfg_t mx6dl_sabreauto_i2c2_pads[] = { + MX6DL_PAD_KEY_COL3__I2C2_SCL, /* I2C2 SCL */ + MX6DL_PAD_KEY_ROW3__I2C2_SDA, /* I2C2 SDA */ +}; diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c index cb4d6eaf880f..b1a0af0f3d35 100644 --- a/arch/arm/mach-mx6/bus_freq.c +++ b/arch/arm/mach-mx6/bus_freq.c @@ -78,7 +78,6 @@ void set_ddr_freq(int ddr_freq); extern int init_mmdc_settings(void); extern struct cpu_op *(*get_cpu_op)(int *op); extern int update_ddr_freq(int ddr_rate); -extern void __iomem *gpc_base; struct mutex bus_freq_mutex; @@ -93,18 +92,18 @@ static struct clk *ahb_clk; static struct clk *periph_clk; static struct clk *osc_clk; static struct clk *cpu_clk; -static unsigned int org_ldo; static struct clk *pll3; static struct clk *pll2; static struct clk *pll3_sw_clk; static struct clk *pll2_200; static struct clk *mmdc_ch0_axi; +struct regulator *vddsoc_cap_regulator; static struct delayed_work low_bus_freq_handler; static void reduce_bus_freq_handler(struct work_struct *work) { - unsigned long reg; + int ret = 0; if (low_bus_freq_mode || !low_freq_bus_used()) return; @@ -152,6 +151,17 @@ static void reduce_bus_freq_handler(struct work_struct *work) clk_disable(pll2_400); clk_disable(pll3); } else { + /* Set VDDSOC_CAP to 1.1V */ + ret = regulator_set_voltage(vddsoc_cap_regulator, 1100000, + 1100000); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT DECREASE VDDSOC_CAP VOLTAGE!!!!\n"); + return; + } + + udelay(150); + /* Set periph_clk to be sourced from OSC_CLK */ /* Set MMDC clk to 25MHz. */ /* First need to set the divider before changing the parent */ @@ -175,48 +185,8 @@ static void reduce_bus_freq_handler(struct work_struct *work) high_bus_freq_mode = 0; med_bus_freq_mode = 0; - /* Do not disable PU LDO if it is not enabled */ - reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET); - if ((low_bus_freq_mode || audio_bus_freq_mode) && reg != 0) { - /* Disable the brown out detection since we are going to be - * disabling the LDO. - */ - reg = __raw_readl(ANA_MISC2_BASE_ADDR); - reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; - __raw_writel(reg, ANA_MISC2_BASE_ADDR); - - /* Power gate the PU LDO. */ - /* Power gate the PU domain first. */ - /* enable power down request */ - reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); - __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); - /* power down request */ - reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); - __raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET); - /* Wait for power down to complete. */ - while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1) - ; - - /* Mask the ANATOP brown out interrupt in the GPC. */ - reg = __raw_readl(gpc_base + 0x14); - reg |= 0x80000000; - __raw_writel(reg, gpc_base + 0x14); - - /* PU power gating. */ - reg = __raw_readl(ANADIG_REG_CORE); - org_ldo = reg & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET); - reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET); - __raw_writel(reg, ANADIG_REG_CORE); - - /* Clear the BO interrupt in the ANATOP. */ - reg = __raw_readl(ANADIG_MISC1_REG); - reg |= 0x80000000; - __raw_writel(reg, ANADIG_MISC1_REG); - } - mutex_unlock(&bus_freq_mutex); } - /* Set the DDR, AHB to 24MHz. * This mode will be activated only when none of the modules that * need a higher DDR or AHB frequency are active. @@ -241,7 +211,7 @@ int set_low_bus_freq(void) */ int set_high_bus_freq(int high_bus_freq) { - unsigned long reg; + int ret = 0; if (busfreq_suspended) return 0; @@ -255,6 +225,12 @@ int set_high_bus_freq(int high_bus_freq) if (med_bus_freq_mode && !high_bus_freq) return 0; + if (cpu_is_mx6dl() && high_bus_freq) + high_bus_freq = 0; + + if (cpu_is_mx6dl() && med_bus_freq_mode) + return 0; + while (!mutex_trylock(&bus_freq_mutex)) msleep(1); @@ -265,11 +241,15 @@ int set_high_bus_freq(int high_bus_freq) return 0; } - /* Enable the PU LDO */ - if (low_bus_freq_mode || audio_bus_freq_mode) { - /* Set the voltage of VDDPU as in normal mode. */ - __raw_writel(org_ldo | (__raw_readl(ANADIG_REG_CORE) & - (~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET))), ANADIG_REG_CORE); + if (cpu_is_mx6sl()) { + /* Set the voltage of VDDSOC to 1.2V as in normal mode. */ + ret = regulator_set_voltage(vddsoc_cap_regulator, 1200000, + 1200000); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT INCREASE VDDSOC_CAP VOLTAGE!!!!\n"); + return ret; + } /* Need to wait for the regulator to come back up */ /* @@ -279,52 +259,27 @@ int set_high_bus_freq(int high_bus_freq) */ udelay(150); - /* enable power up request */ - reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); - __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); - /* power up request */ - reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); - __raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET); - /* Wait for the power up bit to clear */ - while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2) - ; - - /* Enable the Brown Out detection. */ - reg = __raw_readl(ANA_MISC2_BASE_ADDR); - reg |= ANADIG_ANA_MISC2_REG1_BO_EN; - __raw_writel(reg, ANA_MISC2_BASE_ADDR); - - /* Unmask the ANATOP brown out interrupt in the GPC. */ - reg = __raw_readl(gpc_base + 0x14); - reg &= ~0x80000000; - __raw_writel(reg, gpc_base + 0x14); - - if (cpu_is_mx6sl()) { - /* Set periph_clk to be sourced from pll2_pfd2_400M */ - /* First need to set the divider before changing the */ - /* parent if parent clock is larger than previous one */ - clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, - LPAPM_CLK / 3)); - clk_set_rate(axi_clk, - clk_round_rate(axi_clk, LPAPM_CLK / 2)); - clk_set_parent(periph_clk, pll2_400); - - /* Set mmdc_clk_root to be sourced */ - /* from pll2_pfd2_400M */ - clk_set_rate(mmdc_ch0_axi, - clk_round_rate(mmdc_ch0_axi, - LPAPM_CLK / 2)); - clk_set_parent(mmdc_ch0_axi, pll3_sw_clk); - clk_set_parent(mmdc_ch0_axi, pll2_400); - clk_set_rate(mmdc_ch0_axi, - clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK)); - - high_bus_freq_mode = 1; - med_bus_freq_mode = 0; - } - } + /* Set periph_clk to be sourced from pll2_pfd2_400M */ + /* First need to set the divider before changing the */ + /* parent if parent clock is larger than previous one */ + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, + LPAPM_CLK / 3)); + clk_set_rate(axi_clk, + clk_round_rate(axi_clk, LPAPM_CLK / 2)); + clk_set_parent(periph_clk, pll2_400); + + /* Set mmdc_clk_root to be sourced */ + /* from pll2_pfd2_400M */ + clk_set_rate(mmdc_ch0_axi, + clk_round_rate(mmdc_ch0_axi, LPAPM_CLK / 2)); + clk_set_parent(mmdc_ch0_axi, pll3_sw_clk); + clk_set_parent(mmdc_ch0_axi, pll2_400); + clk_set_rate(mmdc_ch0_axi, + clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK)); - if (!cpu_is_mx6sl()) { + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + } else { clk_enable(pll3); if (high_bus_freq) { update_ddr_freq(ddr_normal_rate); @@ -355,7 +310,6 @@ int set_high_bus_freq(int high_bus_freq) return 0; } - int low_freq_bus_used(void) { if (!bus_freq_scaling_initialized) @@ -411,8 +365,7 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev, static int busfreq_suspend(struct platform_device *pdev, pm_message_t message) { - if (low_bus_freq_mode || audio_bus_freq_mode) - set_high_bus_freq(1); + set_high_bus_freq(1); busfreq_suspended = 1; return 0; } @@ -517,6 +470,13 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(mmdc_ch0_axi); } + vddsoc_cap_regulator = regulator_get(NULL, "cpu_vddsoc"); + if (IS_ERR(vddsoc_cap_regulator)) { + printk(KERN_ERR "%s: failed to get vddsoc_cap regulator\n", + __func__); + return PTR_ERR(vddsoc_cap_regulator); + } + err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); if (err) { printk(KERN_ERR @@ -526,8 +486,16 @@ static int __devinit busfreq_probe(struct platform_device *pdev) cpu_op_tbl = get_cpu_op(&cpu_op_nr); low_bus_freq_mode = 0; - high_bus_freq_mode = 1; - med_bus_freq_mode = 0; + if (cpu_is_mx6dl()) { + high_bus_freq_mode = 0; + med_bus_freq_mode = 1; + /* To make pll2_400 use count right, as when + system enter 24M, it will disable pll2_400 */ + clk_enable(pll2_400); + } else { + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + } bus_freq_scaling_is_active = 0; bus_freq_scaling_initialized = 1; @@ -575,18 +543,20 @@ static int __init busfreq_init(void) printk(KERN_INFO "Bus freq driver module loaded\n"); - if (cpu_is_mx6sl()) { - /* Enable busfreq by default. */ - bus_freq_scaling_is_active = 1; + /* Enable busfreq by default. */ + bus_freq_scaling_is_active = 1; + + if (cpu_is_mx6q()) + set_high_bus_freq(1); + else set_high_bus_freq(0); - /* Make sure system can enter low bus mode if it should be in - low bus mode */ - if (low_freq_bus_used() && !low_bus_freq_mode) - set_low_bus_freq(); - printk(KERN_INFO "Bus freq driver Enabled\n"); - } + /* Make sure system can enter low bus mode if it should be in + low bus mode */ + if (low_freq_bus_used() && !low_bus_freq_mode) + set_low_bus_freq(); + printk(KERN_INFO "Bus freq driver Enabled\n"); return 0; } diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 3efb6b3e6378..600cd8b23414 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -1989,15 +1989,26 @@ static struct clk vdo_axi_clk = { .set_parent = _clk_vdo_axi_set_parent, }; -static struct clk vdoa_clk = { +static struct clk vdoa_clk[] = { + { __INIT_CLK_DEBUG(vdoa_clk) .id = 0, .parent = &vdo_axi_clk, - .secondary = &ipg_clk, .enable_reg = MXC_CCM_CCGR2, .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, .enable = _clk_enable, .disable = _clk_disable, + .secondary = &vdoa_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &mmdc_ch0_axi_clk[0], + .secondary = &vdoa_clk[2], + }, + { + .parent = &mx6fast1_clk, + .secondary = &ocram_clk, + }, }; static unsigned long _clk_gpt_get_rate(struct clk *clk) @@ -4165,7 +4176,6 @@ static struct clk hdmi_clk[] = { .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, .enable = _clk_enable, .disable = _clk_disable, - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { __INIT_CLK_DEBUG(hdmi_iahb_clk) @@ -4187,7 +4197,6 @@ static struct clk caam_clk[] = { .enable = _clk_enable, .disable = _clk_disable, .secondary = &caam_clk[1], - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { __INIT_CLK_DEBUG(caam_aclk_clk) @@ -5247,7 +5256,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]), _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]), _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk), - _REGISTER_CLOCK(NULL, "vdoa", vdoa_clk), + _REGISTER_CLOCK(NULL, "vdoa", vdoa_clk[0]), _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk), _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk), _REGISTER_CLOCK(NULL, "clko_clk", clko_clk), diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index 42621f73dbbc..577a52277d68 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -3910,6 +3910,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk), _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk), _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk), + _REGISTER_CLOCK(NULL, "rng_clk", dummy_clk), + _REGISTER_CLOCK(NULL, "dcp_clk", dummy_clk), }; static void clk_tree_init(void) diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index 651b1ffd4344..5d9749653988 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -60,6 +60,8 @@ static int mx6_get_srev(void) return IMX_CHIP_REVISION_1_0; else if (rev == 1) return IMX_CHIP_REVISION_1_1; + else if (rev == 2) + return IMX_CHIP_REVISION_1_2; return IMX_CHIP_REVISION_UNKNOWN; } diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h index c99caad1e776..2e1f3e4a32c4 100644 --- a/arch/arm/mach-mx6/crm_regs.h +++ b/arch/arm/mach-mx6/crm_regs.h @@ -121,6 +121,7 @@ #define ANADIG_PLL_ENET_POWER_DOWN (1 << 12) #define ANADIG_PLL_ENET_DIV_SELECT_MASK (0x3) #define ANADIG_PLL_ENET_DIV_SELECT_OFFSET (0) +#define ANATOP_BYPASS_SRC_LVDS1 0x00004000 /* PFD register defines. */ #define ANADIG_PFD_FRAC_MASK 0x3F diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h index 3255cf79decf..105e1f6d0a0e 100644 --- a/arch/arm/mach-mx6/devices-imx6q.h +++ b/arch/arm/mach-mx6/devices-imx6q.h @@ -246,3 +246,13 @@ extern const struct imx_pcie_data imx6q_pcie_data __initconst; extern const struct imx_imx_keypad_data imx6sl_imx_keypad_data; #define imx6sl_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx6sl_imx_keypad_data, pdata) + +extern const struct imx_dcp_data imx6sl_dcp_data __initconst; +#define imx6sl_add_dcp() \ + imx_add_dcp(&imx6sl_dcp_data); + +extern const struct imx_rngb_data imx6sl_rngb_data __initconst; +#define imx6sl_add_rngb() \ + imx_add_rngb(&imx6sl_rngb_data); + +#define imx6_add_armpmu() imx_add_imx_armpmu() diff --git a/arch/arm/mach-mx6/mx6_anatop_regulator.c b/arch/arm/mach-mx6/mx6_anatop_regulator.c index fd7e0c3fbdee..06755dc7a4ee 100644 --- a/arch/arm/mach-mx6/mx6_anatop_regulator.c +++ b/arch/arm/mach-mx6/mx6_anatop_regulator.c @@ -34,9 +34,15 @@ #include "crm_regs.h" #include "regs-anadig.h" +#define GPC_PGC_GPU_PGCR_OFFSET 0x260 +#define GPC_CNTR_OFFSET 0x0 + extern struct platform_device sgtl5000_vdda_reg_devices; extern struct platform_device sgtl5000_vddio_reg_devices; extern struct platform_device sgtl5000_vddd_reg_devices; +extern void __iomem *gpc_base; +/* Default PU voltage value set to 1.1V */ +static unsigned int org_ldo = 0x2000; static int get_voltage(struct anatop_regulator *sreg) { @@ -82,6 +88,108 @@ static int set_voltage(struct anatop_regulator *sreg, int uv) } } +static int pu_enable(struct anatop_regulator *sreg) +{ + unsigned int reg; + + /* Do not enable PU LDO if it is already enabled */ + reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK + << ANADIG_REG1_PU_TARGET_OFFSET); + if (reg != 0) + return 0; + + /* Set the voltage of VDDPU as in normal mode. */ + __raw_writel(org_ldo | (__raw_readl(ANADIG_REG_CORE) & + (~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET))), ANADIG_REG_CORE); + + /* Need to wait for the regulator to come back up */ + /* + * Delay time is based on the number of 24MHz clock cycles + * programmed in the ANA_MISC2_BASE_ADDR for each + * 25mV step. + */ + udelay(150); + + /* enable power up request */ + reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + /* power up request */ + reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + __raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET); + /* Wait for the power up bit to clear */ + while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2) + ; + + /* Enable the Brown Out detection. */ + reg = __raw_readl(ANA_MISC2_BASE_ADDR); + reg |= ANADIG_ANA_MISC2_REG1_BO_EN; + __raw_writel(reg, ANA_MISC2_BASE_ADDR); + + /* Unmask the ANATOP brown out interrupt in the GPC. */ + reg = __raw_readl(gpc_base + 0x14); + reg &= ~0x80000000; + __raw_writel(reg, gpc_base + 0x14); + + return 0; +} + +static int pu_disable(struct anatop_regulator *sreg) +{ + unsigned int reg; + + /* Do not disable PU LDO if it is not enabled */ + reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK + << ANADIG_REG1_PU_TARGET_OFFSET); + if (reg == 0) + return 0; + + /* Disable the brown out detection since we are going to be + * disabling the LDO. + */ + reg = __raw_readl(ANA_MISC2_BASE_ADDR); + reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; + __raw_writel(reg, ANA_MISC2_BASE_ADDR); + + /* Power gate the PU LDO. */ + /* Power gate the PU domain first. */ + /* enable power down request */ + reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + /* power down request */ + reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET); + /* Wait for power down to complete. */ + while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1) + ; + + /* Mask the ANATOP brown out interrupt in the GPC. */ + reg = __raw_readl(gpc_base + 0x14); + reg |= 0x80000000; + __raw_writel(reg, gpc_base + 0x14); + + /* PU power gating. */ + reg = __raw_readl(ANADIG_REG_CORE); + org_ldo = reg & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET); + reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET); + __raw_writel(reg, ANADIG_REG_CORE); + + /* Clear the BO interrupt in the ANATOP. */ + reg = __raw_readl(ANADIG_MISC1_REG); + reg |= 0x80000000; + __raw_writel(reg, ANADIG_MISC1_REG); + return 0; +} +static int is_pu_enabled(struct anatop_regulator *sreg) +{ + unsigned int reg; + + reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK + << ANADIG_REG1_PU_TARGET_OFFSET); + if (reg == 0) + return 0; + else + return 1; +} static int enable(struct anatop_regulator *sreg) { return 0; @@ -101,9 +209,9 @@ static struct anatop_regulator_data vddpu_data = { .name = "vddpu", .set_voltage = set_voltage, .get_voltage = get_voltage, - .enable = enable, - .disable = disable, - .is_enabled = is_enabled, + .enable = pu_enable, + .disable = pu_disable, + .is_enabled = is_pu_enabled, .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_CORE), .vol_bit_shift = 9, .vol_bit_mask = 0x1F, @@ -193,6 +301,21 @@ static struct regulator_consumer_supply vddcore_consumers[] = { .supply = "cpu_vddgp", } }; +/* PU */ +static struct regulator_consumer_supply vddpu_consumers[] = { + { + .supply = "cpu_vddvpu", + }, + { + .supply = "cpu_vddgpu", + } +}; +/* SOC */ +static struct regulator_consumer_supply vddsoc_consumers[] = { + { + .supply = "cpu_vddsoc", + }, +}; static struct regulator_init_data vddpu_init = { .constraints = { @@ -202,11 +325,11 @@ static struct regulator_init_data vddpu_init = { .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, - .always_on = 1, }, - .num_consumer_supplies = 0, - .consumer_supplies = NULL, + .num_consumer_supplies = ARRAY_SIZE(vddpu_consumers), + .consumer_supplies = vddpu_consumers, }; static struct regulator_init_data vddcore_init = { @@ -235,8 +358,8 @@ static struct regulator_init_data vddsoc_init = { REGULATOR_CHANGE_MODE, .always_on = 1, }, - .num_consumer_supplies = 0, - .consumer_supplies = NULL, + .num_consumer_supplies = ARRAY_SIZE(vddsoc_consumers), + .consumer_supplies = &vddsoc_consumers[0], }; static struct regulator_init_data vdd2p5_init = { diff --git a/arch/arm/mach-mx6/pcie.c b/arch/arm/mach-mx6/pcie.c index 38e9abcd29cc..f39dd3d4314b 100644 --- a/arch/arm/mach-mx6/pcie.c +++ b/arch/arm/mach-mx6/pcie.c @@ -606,6 +606,7 @@ static void imx_pcie_enable_controller(struct device *dev) pr_err("can't enable pcie clock.\n"); clk_put(pcie_clk); } + imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 1 << 16, IOMUXC_GPR1); } static void card_reset(struct device *dev) @@ -652,6 +653,9 @@ static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base, clk_disable(pcie_clk); clk_put(pcie_clk); + imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 0 << 16, + IOMUXC_GPR1); + /* Disable PCIE power */ gpio_request(pdata->pcie_pwr_en, "PCIE POWER_EN"); @@ -669,7 +673,6 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct imx_pcie_platform_data *pdata = dev->platform_data; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(dev, "no mmio space\n"); @@ -698,15 +701,13 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev) imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen1, 0 << 0, IOMUXC_GPR8); imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_3p5db, 0 << 6, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 0 << 12, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 20 << 12, IOMUXC_GPR8); imx_pcie_clrset(iomuxc_gpr8_tx_swing_full, 127 << 18, IOMUXC_GPR8); imx_pcie_clrset(iomuxc_gpr8_tx_swing_low, 127 << 25, IOMUXC_GPR8); /* Enable the pwr, clks and so on */ imx_pcie_enable_controller(dev); - imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 1 << 16, IOMUXC_GPR1); - /* togle the external card's reset */ card_reset(dev) ; @@ -714,13 +715,6 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev) imx_pcie_regions_setup(dbi_base); usleep_range(3000, 4000); - /* - * Force to GEN1 because of PCIE2USB storage stress tests - * would be failed when GEN2 is enabled - */ - writel(((readl(dbi_base + LNK_CAP) & 0xfffffff0) | 0x1), - dbi_base + LNK_CAP); - /* start link up */ imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 1 << 10, IOMUXC_GPR12); @@ -749,6 +743,8 @@ static int __devexit imx_pcie_pltfm_remove(struct platform_device *pdev) clk_put(pcie_clk); } + imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 0 << 16, IOMUXC_GPR1); + /* Disable PCIE power */ gpio_request(pdata->pcie_pwr_en, "PCIE POWER_EN"); diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index d16b1eff6cbe..b9efbb64c8f9 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -49,8 +49,6 @@ extern unsigned int gpc_wake_irq[4]; -static unsigned int cpu_idle_mask; - static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR); int wait_mode_arm_podf; diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 63de2d396e2d..14a5971d0d48 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -49,8 +49,9 @@ #define ETH_KS8851_QUART 138 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 -#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ +#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ +#define HDMI_GPIO_HPD 63 /* Hotplug detect */ static const int sdp4430_keymap[] = { KEY(0, 0, KEY_E), @@ -578,12 +579,8 @@ static void __init omap_sfh7741prox_init(void) static void sdp4430_hdmi_mux_init(void) { - /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ - omap_mux_init_signal("hdmi_hpd", - OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hdmi_cec", OMAP_PIN_INPUT_PULLUP); - /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ omap_mux_init_signal("hdmi_ddc_scl", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hdmi_ddc_sda", @@ -591,8 +588,9 @@ static void sdp4430_hdmi_mux_init(void) } static struct gpio sdp4430_hdmi_gpios[] = { - { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, + { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, + { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, }; static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) @@ -609,26 +607,21 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) { - gpio_free(HDMI_GPIO_LS_OE); - gpio_free(HDMI_GPIO_HPD); + gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios)); } +static struct omap_dss_hdmi_data sdp4430_hdmi_data = { + .hpd_gpio = HDMI_GPIO_HPD, +}; + static struct omap_dss_device sdp4430_hdmi_device = { .name = "hdmi", .driver_name = "hdmi_panel", .type = OMAP_DISPLAY_TYPE_HDMI, - .clocks = { - .dispc = { - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - .hdmi = { - .regn = 15, - .regm2 = 1, - }, - }, .platform_enable = sdp4430_panel_enable_hdmi, .platform_disable = sdp4430_panel_disable_hdmi, .channel = OMAP_DSS_CHANNEL_DIGIT, + .data = &sdp4430_hdmi_data, }; static struct omap_dss_device *sdp4430_dss_devices[] = { @@ -645,6 +638,10 @@ void omap_4430sdp_display_init(void) { sdp4430_hdmi_mux_init(); omap_display_init(&sdp4430_dss_data); + + omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); } #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 0cfe2005cb50..107dfc377a8a 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -52,8 +52,9 @@ #define GPIO_HUB_NRESET 62 #define GPIO_WIFI_PMENA 43 #define GPIO_WIFI_IRQ 53 -#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ +#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */ #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ +#define HDMI_GPIO_HPD 63 /* Hotplug detect */ /* wl127x BT, FM, GPS connectivity chip */ static int wl1271_gpios[] = {46, -1, -1}; @@ -614,12 +615,8 @@ int __init omap4_panda_dvi_init(void) static void omap4_panda_hdmi_mux_init(void) { - /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ - omap_mux_init_signal("hdmi_hpd", - OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hdmi_cec", OMAP_PIN_INPUT_PULLUP); - /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ omap_mux_init_signal("hdmi_ddc_scl", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hdmi_ddc_sda", @@ -627,8 +624,9 @@ static void omap4_panda_hdmi_mux_init(void) } static struct gpio panda_hdmi_gpios[] = { - { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" }, + { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, + { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" }, }; static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) @@ -645,10 +643,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev) static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev) { - gpio_free(HDMI_GPIO_LS_OE); - gpio_free(HDMI_GPIO_HPD); + gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios)); } +static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { + .hpd_gpio = HDMI_GPIO_HPD, +}; + static struct omap_dss_device omap4_panda_hdmi_device = { .name = "hdmi", .driver_name = "hdmi_panel", @@ -656,6 +657,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = { .platform_enable = omap4_panda_panel_enable_hdmi, .platform_disable = omap4_panda_panel_disable_hdmi, .channel = OMAP_DSS_CHANNEL_DIGIT, + .data = &omap4_panda_hdmi_data, }; static struct omap_dss_device *omap4_panda_dss_devices[] = { @@ -679,6 +681,10 @@ void omap4_panda_display_init(void) omap4_panda_hdmi_mux_init(); omap_display_init(&omap4_panda_dss_data); + + omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); } static void __init omap4_panda_init(void) diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 88bd6f7705f0..c56597172bfc 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -133,7 +133,7 @@ static struct platform_device rx51_charger_device = { static void __init rx51_charger_init(void) { WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO, - GPIOF_OUT_INIT_LOW, "isp1704_reset")); + GPIOF_OUT_INIT_HIGH, "isp1704_reset")); platform_device_register(&rx51_charger_device); } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 130034bf01d5..dfffbbf4c009 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -528,7 +528,13 @@ int gpmc_cs_configure(int cs, int cmd, int wval) case GPMC_CONFIG_DEV_SIZE: regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + + /* clear 2 target bits */ + regval &= ~GPMC_CONFIG1_DEVICESIZE(3); + + /* set the proper value */ regval |= GPMC_CONFIG1_DEVICESIZE(wval); + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); break; diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 0ab531d047fc..8a98da0b3f8e 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -29,6 +29,7 @@ #include <mach/hardware.h> #include <mach/orion5x.h> #include <plat/orion_nand.h> +#include <plat/ehci-orion.h> #include <plat/time.h> #include <plat/common.h> #include "common.h" @@ -72,7 +73,8 @@ void __init orion5x_map_io(void) void __init orion5x_ehci0_init(void) { orion_ehci_init(&orion5x_mbus_dram_info, - ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); + ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, + EHCI_PHY_ORION); } diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h index eac68978a2c2..db70e79a1198 100644 --- a/arch/arm/mach-orion5x/mpp.h +++ b/arch/arm/mach-orion5x/mpp.h @@ -65,8 +65,8 @@ #define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1) #define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1) +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1, 1) +#define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1) #define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1) diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 9a9706cf1496..6ebdb0d03828 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -7,6 +7,7 @@ config UX500_SOC_COMMON select HAS_MTU select ARM_ERRATA_753970 select ARM_ERRATA_754322 + select ARM_ERRATA_764369 menu "Ux500 SoC" diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 03da5fba8656..e830a9cfaa91 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -386,6 +386,22 @@ dma_alloc_writethrough(struct device *dev, size_t size, dma_addr_t *handle, gfp_ } EXPORT_SYMBOL(dma_alloc_writethrough); + +#ifdef CONFIG_FSL_UTP +/* + * Allocate noncacheable memory space and return both the kernel remapped + * virtual and bus address for that space. + */ +void * +dma_alloc_noncacheable(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) +{ + return __dma_alloc(dev, size, handle, gfp, + /*pgprot_writethrough(pgprot_kernel));*/ + pgprot_noncached(pgprot_kernel)); +} +EXPORT_SYMBOL(dma_alloc_noncacheable); +#endif + static int dma_mmap(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, dma_addr_t dma_addr, size_t size) { diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index bc0e1d88fd3b..8799eae5da9b 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -266,7 +266,9 @@ good_area: return fault; check_stack: - if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) + /* Don't allow expansion below FIRST_USER_ADDRESS */ + if (vma->vm_flags & VM_GROWSDOWN && + addr >= FIRST_USER_ADDRESS && !expand_stack(vma, addr)) goto good_area; out: return fault; diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b6ba1032a988..21cd29834076 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -344,9 +344,7 @@ __v7_setup: mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif #ifdef CONFIG_ARM_ERRATA_743622 - teq r6, #0x20 @ present in r2p0 - teqne r6, #0x21 @ present in r2p1 - teqne r6, #0x22 @ present in r2p2 + teq r5, #0x00200000 @ only present in r2p* mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register orreq r10, r10, #1 << 6 @ set bit #6 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register @@ -374,6 +372,18 @@ __v7_setup: mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR #endif +#ifndef CONFIG_ARM_THUMBEE + mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE + and r0, r0, #(0xf << 12) @ ThumbEE enabled field + teq r0, #(1 << 12) @ check if ThumbEE is present + bne 1f + mov r5, #0 + mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 + mrc p14, 6, r0, c0, c0, 0 @ load TEECR + orr r0, r0, #1 @ set the 1st bit in order to + mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access +1: +#endif adr r5, v7_crval ldmia r5, {r5, r6} #ifdef CONFIG_CPU_ENDIAN_BE8 diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index c074e66ad224..4e0a371630b3 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -116,7 +116,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) return oprofile_perf_init(ops); } -void __exit oprofile_arch_exit(void) +void oprofile_arch_exit(void) { oprofile_perf_exit(); } diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 386b9cb4e29c..41287783cb80 100755 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -66,3 +66,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI) += platform-imx-mipi_dsi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2) += platform-imx-mipi_csi2.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA) += platform-imx-vdoa.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE) += platform-imx-pcie.o +obj-y += platform-imx-pmu.o diff --git a/arch/arm/plat-mxc/devices/platform-imx-dcp.c b/arch/arm/plat-mxc/devices/platform-imx-dcp.c index 3a36de55254b..a77840b93fe9 100755 --- a/arch/arm/plat-mxc/devices/platform-imx-dcp.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dcp.c @@ -1,28 +1,50 @@ /* * Copyright (C) 2010 Pengutronix * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #include <asm/sizes.h> #include <mach/hardware.h> #include <mach/devices-common.h> -#define imx_ocp_data_entry_single(soc) \ +#ifdef CONFIG_SOC_IMX50 +#define imx_dcp_data_entry_single(soc) \ { \ .iobase = soc ## _DCP_BASE_ADDR, \ .irq1 = soc ## _INT_DCP_CHAN0, \ .irq2 = soc ## _INT_DCP_CHAN1_3, \ } -#ifdef CONFIG_SOC_IMX50 const struct imx_dcp_data imx50_dcp_data __initconst = - imx_ocp_data_entry_single(MX50); + imx_dcp_data_entry_single(MX50); #endif /* ifdef CONFIG_SOC_IMX50 */ +#ifdef CONFIG_SOC_IMX6SL +#define imx_dcp_data_entry_single(soc) \ +{ \ + .iobase = soc ## _DCP_BASE_ADDR, \ + .irq1 = soc ## _INT_DCP_CH0, \ + .irq2 = soc ## _INT_DCP_GEN, \ +} + +const struct imx_dcp_data imx6sl_dcp_data __initconst = + imx_dcp_data_entry_single(MX6SL); +#endif /* ifdef CONFIG_SOC_IMX6SL */ + struct platform_device *__init imx_add_dcp( const struct imx_dcp_data *data) { @@ -31,17 +53,19 @@ struct platform_device *__init imx_add_dcp( .start = data->iobase, .end = data->iobase + SZ_8K - 1, .flags = IORESOURCE_MEM, - }, { + }, + { .start = data->irq1, .end = data->irq1, .flags = IORESOURCE_IRQ, - }, { + }, + { .start = data->irq2, .end = data->irq2, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("dcp", 0, - res, ARRAY_SIZE(res), NULL, 0); + return imx_add_platform_device_dmamask("dcp", 0, + res, ARRAY_SIZE(res), NULL, 0, DMA_BIT_MASK(32)); } diff --git a/arch/arm/plat-mxc/devices/platform-imx-ocotp.c b/arch/arm/plat-mxc/devices/platform-imx-ocotp.c index 2279aa7b8f91..055fe337e143 100755 --- a/arch/arm/plat-mxc/devices/platform-imx-ocotp.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ocotp.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License version 2 as published by the @@ -53,7 +53,7 @@ const struct imx_otp_data imx50_otp_data = { static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), BANK(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2), - BANK(OTPMK0, SOTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), + BANK(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7), BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), BANK(RESP0, HSJC_RESP1, MAC0, MAC1, HDCP_KSV0, HDCP_KSV1, GP1, GP2), BANK(DTCP_KEY0, DTCP_KEY1, DTCP_KEY2, DTCP_KEY3, DTCP_KEY4, MISC_CONF, FIELD_RETURN, SRK_REVOKE), diff --git a/arch/arm/plat-mxc/devices/platform-imx-pmu.c b/arch/arm/plat-mxc/devices/platform-imx-pmu.c new file mode 100644 index 000000000000..cf29415d679e --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-pmu.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <asm/pmu.h> + +static struct resource mx6_pmu_resources[] = { + [0] = { + .start = MXC_INT_CHEETAH_PERFORM, + .end = MXC_INT_CHEETAH_PERFORM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx6_pmu_device = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(mx6_pmu_resources), + .resource = mx6_pmu_resources, +}; + +void __init imx_add_imx_armpmu() +{ + platform_device_register(&mx6_pmu_device); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-rngb.c b/arch/arm/plat-mxc/devices/platform-imx-rngb.c index 3407ea04ea53..9a0a652de82e 100755 --- a/arch/arm/plat-mxc/devices/platform-imx-rngb.c +++ b/arch/arm/plat-mxc/devices/platform-imx-rngb.c @@ -1,8 +1,6 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -33,6 +31,11 @@ const struct imx_rngb_data imx50_rngb_data __initconst = imx_rngb_data_entry_single(MX50); #endif /* ifdef CONFIG_SOC_IMX50 */ +#ifdef CONFIG_SOC_IMX6SL +const struct imx_rngb_data imx6sl_rngb_data __initconst = + imx_rngb_data_entry_single(MX6SL); +#endif /* ifdef CONFIG_SOC_IMX6SL */ + struct platform_device *__init imx_add_rngb( const struct imx_rngb_data *data) { diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c index 872515a04099..53cfb8dde927 100644 --- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -15,6 +15,7 @@ .id = _id, \ .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ .iosize = _size, \ + .irq = soc ## _INT_WDOG ## _hwid, \ } #define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) @@ -79,6 +80,10 @@ struct platform_device *__init imx_add_imx2_wdt( .start = data->iobase, .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, }, }; return imx_add_platform_device("imx2-wdt", data->id, diff --git a/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c b/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c index c0545705e8c0..d4952620e223 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_hdmi.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -43,7 +43,8 @@ struct platform_device *__init imx_add_mxc_hdmi( .flags = IORESOURCE_IRQ, }, }; - + imx_add_platform_device("mxc_hdmi_cec", 0, + res, ARRAY_SIZE(res), NULL, 0); return imx_add_platform_device_dmamask("mxc_hdmi", -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 369ec0f6bd4a..4b6110712d1b 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -80,6 +80,7 @@ struct imx_imx2_wdt_data { int id; resource_size_t iobase; resource_size_t iosize; + resource_size_t irq; }; struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data); @@ -685,3 +686,5 @@ struct imx_pcie_data { struct platform_device *__init imx_add_pcie( const struct imx_pcie_data *data, const struct imx_pcie_platform_data *pdata); + +void __init imx_add_imx_armpmu(void); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h index 1fa0e82b6a7e..4d0fa922c742 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h @@ -2665,11 +2665,13 @@ #define MX6DL_PAD_KEY_COL3__ENET_CRS \ IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, NO_PAD_CTRL) #define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ - IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, NO_PAD_CTRL) + IOMUX_PAD(0x0638, 0x0250, 2 | IOMUX_CONFIG_SION, 0x0860, 1, \ + MX6DL_I2C_PAD_CTRL) #define MX6DL_PAD_KEY_COL3__KPP_COL_3 \ IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, NO_PAD_CTRL) #define MX6DL_PAD_KEY_COL3__I2C2_SCL \ - IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, MX6DL_I2C_PAD_CTRL) + IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, \ + MX6DL_I2C_PAD_CTRL) #define MX6DL_PAD_KEY_COL3__GPIO_4_12 \ IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, NO_PAD_CTRL) #define MX6DL_PAD_KEY_COL3__SPDIF_IN1 \ @@ -2756,11 +2758,13 @@ #define MX6DL_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, NO_PAD_CTRL) #define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ - IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, NO_PAD_CTRL) + IOMUX_PAD(0x064C, 0x0264, 2 | IOMUX_CONFIG_SION, 0x0864, 1, \ + MX6DL_I2C_PAD_CTRL) #define MX6DL_PAD_KEY_ROW3__KPP_ROW_3 \ IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, NO_PAD_CTRL) #define MX6DL_PAD_KEY_ROW3__I2C2_SDA \ - IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, MX6DL_I2C_PAD_CTRL) + IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, \ + MX6DL_I2C_PAD_CTRL) #define MX6DL_PAD_KEY_ROW3__GPIO_4_13 \ IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, NO_PAD_CTRL) #define MX6DL_PAD_KEY_ROW3__USDHC1_VSELECT \ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h index b56f2fe1ff1b..7618975d38a3 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h @@ -80,9 +80,10 @@ #define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define MX6Q_I2S_OUT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_HYS | PAD_CTL_SPEED_MED) +#define MX6Q_HDMICEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW) #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0) @@ -2183,7 +2184,7 @@ #define _MX6Q_PAD_KEY_COL3__ENET_CRS \ IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ - IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0) + IOMUX_PAD(0x05E0, 0x0210, 2 | IOMUX_CONFIG_SION, 0x0890, 1, 0) #define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_COL3__I2C2_SCL \ @@ -2200,7 +2201,7 @@ #define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0) #define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ - IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0) + IOMUX_PAD(0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x0894, 1, 0) #define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0) #define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \ @@ -3871,7 +3872,7 @@ #define MX6Q_PAD_EIM_A25__GPIO_5_2 \ (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \ - (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(MX6Q_HDMICEC_PAD_CTRL)) #define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \ (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -5781,7 +5782,7 @@ #define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \ (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \ - (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(MX6Q_HDMICEC_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \ (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -5790,7 +5791,7 @@ #define MX6Q_PAD_KEY_COL3__ENET_CRS \ (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \ - (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__KPP_COL_3 \ (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_COL3__I2C2_SCL \ @@ -5807,7 +5808,7 @@ #define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \ (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \ - (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \ (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_KEY_ROW3__I2C2_SDA \ @@ -6176,7 +6177,7 @@ #define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \ (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \ - (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(MX6Q_I2S_OUT_PAD_CTRL)) + (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \ (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV)) #define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \ diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index bb4423e20063..aaf8b998ca63 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -308,7 +308,7 @@ (((((x) >= (unsigned long)AIPS1_ARB_BASE_ADDR) && \ ((x) <= (unsigned long)AIPS2_ARB_END_ADDR)) || \ ((x) >= (unsigned long)ARM_PERIPHBASE && \ - ((x) <= (unsigned long)(ARM_PERIPHBASE + ARM_PERIPHBASE)))) ? \ + ((x) <= (unsigned long)(ARM_PERIPHBASE + ARM_PERIPHBASE_SIZE)))) ? \ MX6_IO_ADDRESS(x) : (void __force __iomem *)0xDEADBEEF) /* @@ -322,7 +322,7 @@ #define MX6DL_INT_MSHC 35 #define MXC_INT_INTERRUPT_36_NUM 36 #define MX6Q_INT_IPU1_ERR 37 -#define MX6DL_INT_RNGB 37 +#define MX6SL_INT_RNGB 37 #define MX6Q_INT_IPU1_SYN 38 #define MX6SL_INT_SPDC 38 #define MX6Q_INT_IPU2_ERR 39 @@ -415,8 +415,8 @@ #define MXC_INT_GPIO6_INT31_16_NUM 109 #define MXC_INT_GPIO7_INT15_0_NUM 110 #define MXC_INT_GPIO7_INT31_16_NUM 111 -#define MXC_INT_WDOG1 112 -#define MXC_INT_WDOG2 113 +#define MX6Q_INT_WDOG1 112 +#define MX6Q_INT_WDOG2 113 #define MXC_INT_KPP 114 #define MX6SL_INT_KPP 114 #define MX6Q_INT_PWM1 115 @@ -436,9 +436,9 @@ #define MX6DL_INT_EPDC 129 #define MX6DL_INT_EPXP 130 #define MXC_INT_INTERRUPT_131_NUM 131 -#define MX6DL_INT_DCP_GEN 131 -#define MX6DL_INT_DCP_CH0 132 -#define MX6DL_INT_DCP_SEC 133 +#define MX6SL_INT_DCP_GEN 131 +#define MX6SL_INT_DCP_CH0 132 +#define MX6SL_INT_DCP_SEC 133 #define MXC_INT_CSI_INTR1 132 #define MXC_INT_CSI_INTR2 133 #define MXC_INT_DSI 134 diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h index 7385c2710db8..38bad6b7a67e 100755 --- a/arch/arm/plat-mxc/include/mach/mxc_edid.h +++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h @@ -51,6 +51,13 @@ enum cea_audio_coding_types { AUDIO_CODING_TYPE_RESERVED = 15, }; +struct mxc_hdmi_3d_format { + unsigned char vic_order_2d; + unsigned char struct_3d; + unsigned char detail_3d; + unsigned char reserved; +}; + struct mxc_edid_cfg { bool cea_underscan; bool cea_basicaudio; @@ -59,12 +66,30 @@ struct mxc_edid_cfg { bool hdmi_cap; /*VSD*/ + bool vsd_support_ai; bool vsd_dc_48bit; bool vsd_dc_36bit; bool vsd_dc_30bit; bool vsd_dc_y444; bool vsd_dvi_dual; + bool vsd_cnc0; + bool vsd_cnc1; + bool vsd_cnc2; + bool vsd_cnc3; + + u8 vsd_video_latency; + u8 vsd_audio_latency; + u8 vsd_I_video_latency; + u8 vsd_I_audio_latency; + + u8 physical_address[4]; + u8 hdmi_vic[64]; + struct mxc_hdmi_3d_format hdmi_3d_format[64]; + u16 hdmi_3d_mask_all; + u16 hdmi_3d_struct_all; + u32 vsd_max_tmdsclk_rate; + u8 max_channels; u8 sample_sizes; u8 sample_rates; @@ -75,5 +100,6 @@ int mxc_edid_var_to_vic(struct fb_var_screeninfo *var); int mxc_edid_mode_to_vic(const struct fb_videomode *mode); int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr, unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi); - +int mxc_edid_parse_ext_blk(unsigned char *edid, struct mxc_edid_cfg *cfg, + struct fb_monspecs *specs); #endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h index bc1ed6c48ecd..60946cadc441 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h +++ b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h @@ -538,7 +538,7 @@ /* I2C Master Registers (E-DDC) */ #define HDMI_I2CM_SLAVE 0x7E00 -#define HDMI_I2CMESS 0x7E01 +#define HDMI_I2CM_ADDRESS 0x7E01 #define HDMI_I2CM_DATAO 0x7E02 #define HDMI_I2CM_DATAI 0x7E03 #define HDMI_I2CM_OPERATION 0x7E04 @@ -583,6 +583,16 @@ enum { HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, HDMI_IH_PHY_STAT0_HPD = 0x1, +/* IH_CEC_STAT0 field values */ + HDMI_IH_CEC_STAT0_WAKEUP = 0x40, + HDMI_IH_CEC_STAT0_ERROR_FOLL = 0x20, + HDMI_IH_CEC_STAT0_ERROR_INIT = 0x10, + HDMI_IH_CEC_STAT0_ARB_LOST = 0x8, + HDMI_IH_CEC_STAT0_NACK = 0x4, + HDMI_IH_CEC_STAT0_EOM = 0x2, + HDMI_IH_CEC_STAT0_DONE = 0x1, + + /* IH_MUTE_I2CMPHY_STAT0 field values */ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, @@ -1056,6 +1066,23 @@ enum { HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, + + +/* I2CM_OPERATION field values */ + HDMI_I2CM_OPERATION_WRITE = 0x10, + HDMI_I2CM_OPERATION_READ_EXT = 0x2, + HDMI_I2CM_OPERATION_READ = 0x1, + +/* HDMI_I2CM_INT */ + HDMI_I2CM_INT_DONE_POL = 0x08, + HDMI_I2CM_INT_DONE_MASK = 0x04, + +/* HDMI_I2CM_CTLINT */ + HDMI_I2CM_CTLINT_NAC_POL = 0x80, + HDMI_I2CM_CTLINT_NAC_MASK = 0x40, + HDMI_I2CM_CTLINT_ARBITRATION_POL = 0x08, + HDMI_I2CM_CTLINT_ARBITRATION_MASK = 0x04, + }; #endif /* __MXC_HDMI_H__ */ diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 4a67f4de0e4d..c663acf65c3f 100755 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -34,6 +34,9 @@ #define MX3_PWMSAR 0x0C /* PWM Sample Register */ #define MX3_PWMPR 0x10 /* PWM Period Register */ #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define MX3_PWMCR_DOZEEN (1 << 24) +#define MX3_PWMCR_WAITEN (1 << 23) +#define MX3_PWMCR_DBGEN (1 << 22) #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) #define MX3_PWMCR_CLKSRC_IPG (1 << 16) #define MX3_PWMCR_EN (1 << 0) @@ -91,6 +94,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) do_div(c, period_ns); duty_cycles = c; + /* + * according to imx pwm RM, the real period value should be + * PERIOD value in PWMPR plus 2. + */ + if (period_cycles > 2) + period_cycles -= 2; + else + period_cycles = 0; + writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); writel(period_cycles, pwm->mmio_base + MX3_PWMPR); diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 5a022321802f..d2a999bdcf5b 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -34,6 +34,7 @@ static void __iomem *wdog_base; + static void arch_reset_special_mode(char mode, const char *cmd) { if (strcmp(cmd, "download") == 0) diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 9e5451b3c8e3..11dce87c2487 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -806,10 +806,7 @@ void __init orion_xor1_init(unsigned long mapbase_low, /***************************************************************************** * EHCI ****************************************************************************/ -static struct orion_ehci_data orion_ehci_data = { - .phy_version = EHCI_PHY_NA, -}; - +static struct orion_ehci_data orion_ehci_data; static u64 ehci_dmamask = DMA_BIT_MASK(32); @@ -830,9 +827,11 @@ static struct platform_device orion_ehci = { void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, - unsigned long irq) + unsigned long irq, + enum orion_ehci_phy_ver phy_version) { orion_ehci_data.dram = mbus_dram_info; + orion_ehci_data.phy_version = phy_version; fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, irq); diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index a63c357e2ab1..a2c0e31ce0dc 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -95,7 +95,8 @@ void __init orion_xor1_init(unsigned long mapbase_low, void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, - unsigned long irq); + unsigned long irq, + enum orion_ehci_phy_ver phy_version); void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 91553432711d..3b1e17bd3d17 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, gpio_mode |= GPIO_INPUT_OK; if (*mpp_list & MPP_OUTPUT_MASK) gpio_mode |= GPIO_OUTPUT_OK; - if (sel != 0) - gpio_mode = 0; + orion_gpio_set_valid(num, gpio_mode); } diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 539bd0e3defd..0719f49defb2 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void) struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1; int channel; - for (channel = dma_channels - 1; channel >= 0; cp++, channel--) + for (channel = dma_channels - 1; channel >= 0; cp--, channel--) s3c2410_dma_resume_chan(cp); } |