diff options
Diffstat (limited to 'arch/arm')
50 files changed, 16812 insertions, 2 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 9d9d0b195618..e713f9d75168 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -158,6 +158,7 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MX1) := imx machine-$(CONFIG_ARCH_MX2) := imx machine-$(CONFIG_ARCH_MX6) := mx6 +machine-$(CONFIG_ARCH_MVF) := mvf machine-$(CONFIG_ARCH_MX25) := imx machine-$(CONFIG_ARCH_MX3) := imx machine-$(CONFIG_ARCH_MX5) := mx5 diff --git a/arch/arm/mach-mvf/Kconfig b/arch/arm/mach-mvf/Kconfig new file mode 100644 index 000000000000..44757909765e --- /dev/null +++ b/arch/arm/mach-mvf/Kconfig @@ -0,0 +1,68 @@ +if ARCH_MVF + +config ARCH_VF6XX + bool + #select USB_ARCH_HAS_EHCI + select ARCH_MXC_IOMUX_VMVF + #select ARCH_MXC_AUDMUX_V2 + select ARM_GIC + #select ARCH_HAS_CPUFREQ + #select IMX_HAVE_PLATFORM_IMX_UART + #select IMX_HAVE_PLATFORM_FEC + #select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL + #select IMX_HAVE_PLATFORM_IMX_IPUV3 + #select IMX_HAVE_PLATFORM_MXC_PWM + #select IMX_HAVE_PLATFORM_LDB + #select IMX_HAVE_PLATFORM_IMX_SPDIF + +config SOC_VF6XX + bool + +config MACH_TWR_VF600 + bool "Support MVF TWR-VF600 platform" + select ARCH_VF6XX + select SOC_VF6XX + #select IMX_HAVE_PLATFORM_IMX_UART + #select IMX_HAVE_PLATFORM_DMA + #select IMX_HAVE_PLATFORM_FEC + #select IMX_HAVE_PLATFORM_GPMI_NFC + #select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + #select IMX_HAVE_PLATFORM_SPI_IMX + #select IMX_HAVE_PLATFORM_IMX_I2C + #select IMX_HAVE_PLATFORM_VIV_GPU + #select IMX_HAVE_PLATFORM_IMX_VPU + #select IMX_HAVE_PLATFORM_IMX_DVFS + #select IMX_HAVE_PLATFORM_IMX_ESAI + #select IMX_HAVE_PLATFORM_IMX_SSI + #select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL + #select IMX_HAVE_PLATFORM_FSL_USB2_UDC + #select IMX_HAVE_PLATFORM_MXC_EHCI + #select IMX_HAVE_PLATFORM_FSL_OTG + #select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP + #select IMX_HAVE_PLATFORM_AHCI + #select IMX_HAVE_PLATFORM_IMX_OCOTP + #select IMX_HAVE_PLATFORM_IMX_VIIM + #select IMX_HAVE_PLATFORM_IMX2_WDT + #select IMX_HAVE_PLATFORM_IMX_SNVS_RTC + #select IMX_HAVE_PLATFORM_IMX_PM + #select IMX_HAVE_PLATFORM_MXC_HDMI + #select IMX_HAVE_PLATFORM_IMX_ASRC + #select IMX_HAVE_PLATFORM_IMX_SPDIF + #select IMX_HAVE_PLATFORM_IMX_MIPI_DSI + #select IMX_HAVE_PLATFORM_FLEXCAN + #select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2 + #select IMX_HAVE_PLATFORM_PERFMON + #select IMX_HAVE_PLATFORM_MXC_MLB + #select IMX_HAVE_PLATFORM_IMX_EPDC + #select IMX_HAVE_PLATFORM_IMX_PXP + help + Include support for i.MX Faraday platform. This includes specific + configurations for the board and its peripherals. + +comment "MVF Options:" + +config IMX_PCIE + bool "PCI Express support" + select PCI + +endif diff --git a/arch/arm/mach-mvf/Makefile b/arch/arm/mach-mvf/Makefile new file mode 100644 index 000000000000..03813026847a --- /dev/null +++ b/arch/arm/mach-mvf/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. +obj-y := mm.o devices.o irq.o clock.o + +#obj-$(MACH_TWR_VF600) += board-twr_vf600.o diff --git a/arch/arm/mach-mvf/Makefile.boot b/arch/arm/mach-mvf/Makefile.boot new file mode 100644 index 000000000000..dc006a84c32c --- /dev/null +++ b/arch/arm/mach-mvf/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-$(CONFIG_ARCH_MX6Q) := 0x10008000 +params_phys-$(CONFIG_ARCH_MX6Q) := 0x10000100 +initrd_phys-$(CONFIG_ARCH_MX6Q) := 0x10800000 diff --git a/arch/arm/mach-mvf/] b/arch/arm/mach-mvf/] new file mode 100644 index 000000000000..faac24672e4c --- /dev/null +++ b/arch/arm/mach-mvf/] @@ -0,0 +1,83 @@ +/* + * based on arch/arm/mach-mx6/irq.c + * + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <asm/hardware/gic.h> +#include <mach/hardware.h> +#ifdef CONFIG_CPU_FREQ_GOV_INTERACTIVE +#include <linux/cpufreq.h> +#endif + +int mvf_register_gpios(void); +unsigned int gpc_wake_irq[4]; +extern bool enable_wait_mode; + +static int mvf_gic_irq_set_wake(struct irq_data *d, unsigned int enable) +{ + if ((d->irq < MXC_INT_START) || (d->irq > MXC_INT_END)) { + printk(KERN_ERR "Invalid irq number!\n"); + return -EINVAL; + } + + if (enable) { + gpc_wake_irq[d->irq / 32 - 1] |= 1 << (d->irq % 32); + printk(KERN_INFO "add wake up source irq %d\n", d->irq); + } else { + printk(KERN_INFO "remove wake up source irq %d\n", d->irq); + gpc_wake_irq[d->irq / 32 - 1] &= ~(1 << (d->irq % 32)); + } + return 0; +} + +void mvf_init_irq(void) +{ + void __iomem *gpc_base = MVF_IO_ADDRESS(GPC_BASE_ADDR); + struct irq_desc *desc; + unsigned int i; + + /* start offset if private timer irq id, which is 29. + * ID table: + * Global timer, PPI -> ID27 + * A legacy nFIQ, PPI -> ID28 + * Private timer, PPI -> ID29 + * Watchdog timers, PPI -> ID30 + * A legacy nIRQ, PPI -> ID31 + */ + gic_init(0, 29, MVF_IO_ADDRESS(IC_DISTRIBUTOR_BASE_ADDR), + MVF_IO_ADDRESS(IC_INTERFACES_BASE_ADDR)); + +#if 0 + if (enable_wait_mode) { + /* Mask the always pending interrupts - HW bug. */ + __raw_writel(0x00400000, gpc_base + 0x0c); + __raw_writel(0x20000000, gpc_base + 0x10); + } +#endif + + for (i = MXC_INT_START; i <= MXC_INT_END; i++) { + desc = irq_to_desc(i); + desc->irq_data.chip->irq_set_wake = mvf_gic_irq_set_wake; + } + mvf_register_gpios(); +} diff --git a/arch/arm/mach-mvf/board-twr_vf600.c b/arch/arm/mach-mvf/board-twr_vf600.c new file mode 100644 index 000000000000..dc4218ab8fca --- /dev/null +++ b/arch/arm/mach-mvf/board-twr_vf600.c @@ -0,0 +1,2198 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/nodemask.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/smsc911x.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/i2c.h> +#include <linux/i2c/pca953x.h> +#include <linux/ata.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/partitions.h> +#include <linux/pmic_external.h> +#include <linux/pmic_status.h> +#include <linux/ipu.h> +#include <linux/mxcfb.h> +#include <linux/pwm_backlight.h> +#include <linux/fec.h> +#include <linux/memblock.h> +#include <linux/gpio.h> +#include <linux/etherdevice.h> +#include <linux/regulator/anatop-regulator.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/mfd/max17135.h> +#include <sound/pcm.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> +#include <mach/memory.h> +#include <mach/imx-uart.h> +#include <mach/viv_gpu.h> +#include <mach/ahci_sata.h> +#include <mach/ipu-v3.h> +#include <mach/mxc_hdmi.h> +#include <mach/mxc_asrc.h> +#include <mach/mipi_dsi.h> +#include <mach/mipi_csi2.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "usb.h" +#include "devices-imx6q.h" +#include "crm_regs.h" +#include "cpu_op-mx6.h" +#include "board-mx6q_arm2.h" +#include "board-mx6dl_arm2.h" + +/* GPIO PIN, sort by PORT/BIT */ +#define MX6_ARM2_LDB_BACKLIGHT IMX_GPIO_NR(1, 9) +#define MX6_ARM2_ECSPI1_CS0 IMX_GPIO_NR(2, 30) +#define MX6_ARM2_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define MX6_ARM2_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define MX6_ARM2_DISP0_PWR IMX_GPIO_NR(3, 24) +#define MX6_ARM2_DISP0_I2C_EN IMX_GPIO_NR(3, 28) +#define MX6_ARM2_CAP_TCH_INT IMX_GPIO_NR(3, 31) +#define MX6_ARM2_DISP0_DET_INT IMX_GPIO_NR(3, 31) +#define MX6_ARM2_CSI0_RST IMX_GPIO_NR(4, 5) +#define MX6_ARM2_DISP0_RESET IMX_GPIO_NR(5, 0) +#define MX6_ARM2_CSI0_PWN IMX_GPIO_NR(5, 23) +#define MX6_ARM2_CAN2_EN IMX_GPIO_NR(5, 24) +#define MX6_ARM2_CSI0_RST_TVIN IMX_GPIO_NR(5, 25) +#define MX6_ARM2_SD3_CD IMX_GPIO_NR(6, 11) +#define MX6_ARM2_SD3_WP IMX_GPIO_NR(6, 14) +#define MX6_ARM2_CAN1_STBY IMX_GPIO_NR(7, 12) +#define MX6_ARM2_CAN1_EN IMX_GPIO_NR(7, 13) +#define MX6_ARM2_MAX7310_1_BASE_ADDR IMX_GPIO_NR(8, 0) +#define MX6_ARM2_MAX7310_2_BASE_ADDR IMX_GPIO_NR(8, 8) +#define MX6DL_ARM2_EPDC_SDDO_0 IMX_GPIO_NR(2, 22) +#define MX6DL_ARM2_EPDC_SDDO_1 IMX_GPIO_NR(3, 10) +#define MX6DL_ARM2_EPDC_SDDO_2 IMX_GPIO_NR(3, 12) +#define MX6DL_ARM2_EPDC_SDDO_3 IMX_GPIO_NR(3, 11) +#define MX6DL_ARM2_EPDC_SDDO_4 IMX_GPIO_NR(2, 27) +#define MX6DL_ARM2_EPDC_SDDO_5 IMX_GPIO_NR(2, 30) +#define MX6DL_ARM2_EPDC_SDDO_6 IMX_GPIO_NR(2, 23) +#define MX6DL_ARM2_EPDC_SDDO_7 IMX_GPIO_NR(2, 26) +#define MX6DL_ARM2_EPDC_SDDO_8 IMX_GPIO_NR(2, 24) +#define MX6DL_ARM2_EPDC_SDDO_9 IMX_GPIO_NR(3, 15) +#define MX6DL_ARM2_EPDC_SDDO_10 IMX_GPIO_NR(3, 16) +#define MX6DL_ARM2_EPDC_SDDO_11 IMX_GPIO_NR(3, 23) +#define MX6DL_ARM2_EPDC_SDDO_12 IMX_GPIO_NR(3, 19) +#define MX6DL_ARM2_EPDC_SDDO_13 IMX_GPIO_NR(3, 13) +#define MX6DL_ARM2_EPDC_SDDO_14 IMX_GPIO_NR(3, 14) +#define MX6DL_ARM2_EPDC_SDDO_15 IMX_GPIO_NR(5, 2) +#define MX6DL_ARM2_EPDC_GDCLK IMX_GPIO_NR(2, 17) +#define MX6DL_ARM2_EPDC_GDSP IMX_GPIO_NR(2, 16) +#define MX6DL_ARM2_EPDC_GDOE IMX_GPIO_NR(6, 6) +#define MX6DL_ARM2_EPDC_GDRL IMX_GPIO_NR(5, 4) +#define MX6DL_ARM2_EPDC_SDCLK IMX_GPIO_NR(3, 31) +#define MX6DL_ARM2_EPDC_SDOEZ IMX_GPIO_NR(3, 30) +#define MX6DL_ARM2_EPDC_SDOED IMX_GPIO_NR(3, 26) +#define MX6DL_ARM2_EPDC_SDOE IMX_GPIO_NR(3, 27) +#define MX6DL_ARM2_EPDC_SDLE IMX_GPIO_NR(3, 1) +#define MX6DL_ARM2_EPDC_SDCLKN IMX_GPIO_NR(3, 0) +#define MX6DL_ARM2_EPDC_SDSHR IMX_GPIO_NR(2, 29) +#define MX6DL_ARM2_EPDC_PWRCOM IMX_GPIO_NR(2, 28) +#define MX6DL_ARM2_EPDC_PWRSTAT IMX_GPIO_NR(2, 21) +#define MX6DL_ARM2_EPDC_PWRCTRL0 IMX_GPIO_NR(2, 20) +#define MX6DL_ARM2_EPDC_PWRCTRL1 IMX_GPIO_NR(2, 19) +#define MX6DL_ARM2_EPDC_PWRCTRL2 IMX_GPIO_NR(2, 18) +#define MX6DL_ARM2_EPDC_PWRCTRL3 IMX_GPIO_NR(3, 28) +#define MX6DL_ARM2_EPDC_BDR0 IMX_GPIO_NR(3, 2) +#define MX6DL_ARM2_EPDC_BDR1 IMX_GPIO_NR(3, 3) +#define MX6DL_ARM2_EPDC_SDCE0 IMX_GPIO_NR(3, 4) +#define MX6DL_ARM2_EPDC_SDCE1 IMX_GPIO_NR(3, 5) +#define MX6DL_ARM2_EPDC_SDCE2 IMX_GPIO_NR(3, 6) +#define MX6DL_ARM2_EPDC_SDCE3 IMX_GPIO_NR(3, 7) +#define MX6DL_ARM2_EPDC_SDCE4 IMX_GPIO_NR(3, 8) +#define MX6DL_ARM2_EPDC_SDCE5 IMX_GPIO_NR(3, 9) +#define MX6DL_ARM2_EPDC_PMIC_WAKE IMX_GPIO_NR(2, 31) +#define MX6DL_ARM2_EPDC_PMIC_INT IMX_GPIO_NR(2, 25) +#define MX6DL_ARM2_EPDC_VCOM IMX_GPIO_NR(3, 17) + +#define MX6_ARM2_IO_EXP_GPIO1(x) (MX6_ARM2_MAX7310_1_BASE_ADDR + (x)) +#define MX6_ARM2_IO_EXP_GPIO2(x) (MX6_ARM2_MAX7310_2_BASE_ADDR + (x)) + +#define MX6_ARM2_CAN2_STBY MX6_ARM2_IO_EXP_GPIO2(1) + + +#define BMCR_PDOWN 0x0800 /* PHY Powerdown */ + +void __init early_console_setup(unsigned long base, struct clk *clk); +static struct clk *sata_clk; +static int esai_record; +static int sgtl5000_en; +static int spdif_en; +static int flexcan_en; +static int disable_mipi_dsi; + +extern struct regulator *(*get_cpu_regulator)(void); +extern void (*put_cpu_regulator)(void); +extern char *gp_reg_id; +extern int epdc_enabled; +extern void mx6_cpu_regulator_init(void); +static int max17135_regulator_init(struct max17135 *max17135); + +enum sd_pad_mode { + SD_PAD_MODE_LOW_SPEED, + SD_PAD_MODE_MED_SPEED, + SD_PAD_MODE_HIGH_SPEED, +}; + +static int plt_sd3_pad_change(int clock) +{ + static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED; + + iomux_v3_cfg_t *sd3_pads_200mhz = NULL; + iomux_v3_cfg_t *sd3_pads_100mhz = NULL; + iomux_v3_cfg_t *sd3_pads_50mhz = NULL; + + u32 sd3_pads_200mhz_cnt; + u32 sd3_pads_100mhz_cnt; + u32 sd3_pads_50mhz_cnt; + + if (cpu_is_mx6q()) { + sd3_pads_200mhz = mx6q_sd3_200mhz; + sd3_pads_100mhz = mx6q_sd3_100mhz; + sd3_pads_50mhz = mx6q_sd3_50mhz; + + sd3_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd3_200mhz); + sd3_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd3_100mhz); + sd3_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd3_50mhz); + } else if (cpu_is_mx6dl()) { + sd3_pads_200mhz = mx6dl_sd3_200mhz; + sd3_pads_100mhz = mx6dl_sd3_100mhz; + sd3_pads_50mhz = mx6dl_sd3_50mhz; + + sd3_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd3_200mhz); + sd3_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd3_100mhz); + sd3_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd3_50mhz); + } + + if (clock > 100000000) { + if (pad_mode == SD_PAD_MODE_HIGH_SPEED) + return 0; + BUG_ON(!sd3_pads_200mhz); + pad_mode = SD_PAD_MODE_HIGH_SPEED; + return mxc_iomux_v3_setup_multiple_pads(sd3_pads_200mhz, + sd3_pads_200mhz_cnt); + } else if (clock > 52000000) { + if (pad_mode == SD_PAD_MODE_MED_SPEED) + return 0; + BUG_ON(!sd3_pads_100mhz); + pad_mode = SD_PAD_MODE_MED_SPEED; + return mxc_iomux_v3_setup_multiple_pads(sd3_pads_100mhz, + sd3_pads_100mhz_cnt); + } else { + if (pad_mode == SD_PAD_MODE_LOW_SPEED) + return 0; + BUG_ON(!sd3_pads_50mhz); + pad_mode = SD_PAD_MODE_LOW_SPEED; + return mxc_iomux_v3_setup_multiple_pads(sd3_pads_50mhz, + sd3_pads_50mhz_cnt); + } +} + +static int plt_sd4_pad_change(int clock) +{ + static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED; + + iomux_v3_cfg_t *sd4_pads_200mhz = NULL; + iomux_v3_cfg_t *sd4_pads_100mhz = NULL; + iomux_v3_cfg_t *sd4_pads_50mhz = NULL; + + u32 sd4_pads_200mhz_cnt; + u32 sd4_pads_100mhz_cnt; + u32 sd4_pads_50mhz_cnt; + + if (cpu_is_mx6q()) { + sd4_pads_200mhz = mx6q_sd4_200mhz; + sd4_pads_100mhz = mx6q_sd4_100mhz; + sd4_pads_50mhz = mx6q_sd4_50mhz; + + sd4_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd4_200mhz); + sd4_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd4_100mhz); + sd4_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd4_50mhz); + } else if (cpu_is_mx6dl()) { + sd4_pads_200mhz = mx6dl_sd4_200mhz; + sd4_pads_100mhz = mx6dl_sd4_100mhz; + sd4_pads_50mhz = mx6dl_sd4_50mhz; + + sd4_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd4_200mhz); + sd4_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd4_100mhz); + sd4_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd4_50mhz); + } + + if (clock > 100000000) { + if (pad_mode == SD_PAD_MODE_HIGH_SPEED) + return 0; + + pad_mode = SD_PAD_MODE_HIGH_SPEED; + return mxc_iomux_v3_setup_multiple_pads(sd4_pads_200mhz, + sd4_pads_200mhz_cnt); + } else if (clock > 52000000) { + if (pad_mode == SD_PAD_MODE_MED_SPEED) + return 0; + + pad_mode = SD_PAD_MODE_MED_SPEED; + return mxc_iomux_v3_setup_multiple_pads(sd4_pads_100mhz, + sd4_pads_100mhz_cnt); + } else { + if (pad_mode == SD_PAD_MODE_LOW_SPEED) + return 0; + + pad_mode = SD_PAD_MODE_LOW_SPEED; + return mxc_iomux_v3_setup_multiple_pads(sd4_pads_50mhz, + sd4_pads_50mhz_cnt); + } +} + +static const struct esdhc_platform_data mx6_arm2_sd3_data __initconst = { + .cd_gpio = MX6_ARM2_SD3_CD, + .wp_gpio = MX6_ARM2_SD3_WP, + .support_18v = 1, + .support_8bit = 1, + .keep_power_at_suspend = 1, + .delay_line = 0, + .platform_pad_change = plt_sd3_pad_change, +}; + +/* No card detect signal for SD4 on ARM2 board*/ +static const struct esdhc_platform_data mx6_arm2_sd4_data __initconst = { + .always_present = 1, + .support_8bit = 1, + .keep_power_at_suspend = 1, + .platform_pad_change = plt_sd4_pad_change, +}; + +static int __init gpmi_nand_platform_init(void) +{ + iomux_v3_cfg_t *nand_pads = NULL; + u32 nand_pads_cnt; + + if (cpu_is_mx6q()) { + nand_pads = mx6q_gpmi_nand; + nand_pads_cnt = ARRAY_SIZE(mx6dl_gpmi_nand); + } else if (cpu_is_mx6dl()) { + nand_pads = mx6dl_gpmi_nand; + nand_pads_cnt = ARRAY_SIZE(mx6dl_gpmi_nand); + + } + BUG_ON(!nand_pads); + return mxc_iomux_v3_setup_multiple_pads(nand_pads, nand_pads_cnt); +} + +static const struct gpmi_nand_platform_data +mx6_gpmi_nand_platform_data __initconst = { + .platform_init = gpmi_nand_platform_init, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 1, + .enable_bbt = 1, +}; + +static const struct anatop_thermal_platform_data + mx6_arm2_anatop_thermal_data __initconst = { + .name = "anatop_thermal", +}; + +static const struct imxuart_platform_data mx6_arm2_uart1_data __initconst = { + .flags = IMXUART_HAVE_RTSCTS | IMXUART_USE_DCEDTE | IMXUART_SDMA, + .dma_req_rx = MX6Q_DMA_REQ_UART2_RX, + .dma_req_tx = MX6Q_DMA_REQ_UART2_TX, +}; + +static inline void mx6_arm2_init_uart(void) +{ + imx6q_add_imx_uart(3, NULL); + imx6q_add_imx_uart(1, &mx6_arm2_uart1_data); +} + +static int mx6_arm2_fec_phy_init(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, 0xd, 0x7); + phy_write(phydev, 0xe, 0x8016); + phy_write(phydev, 0xd, 0x4007); + val = phy_read(phydev, 0xe); + + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, 0x1d, 0x5); + val = phy_read(phydev, 0x1e); + val |= 0x0100; + phy_write(phydev, 0x1e, val); + + /*check phy power*/ + val = phy_read(phydev, 0x0); + if (val & BMCR_PDOWN) + phy_write(phydev, 0x0, (val & ~BMCR_PDOWN)); + return 0; +} + +static int mx6_arm2_fec_power_hibernate(struct phy_device *phydev) +{ + unsigned short val; + + /*set AR8031 debug reg 0xb to hibernate power*/ + phy_write(phydev, 0x1d, 0xb); + val = phy_read(phydev, 0x1e); + + val |= 0x8000; + phy_write(phydev, 0x1e, val); + + return 0; +} + +static struct fec_platform_data fec_data __initdata = { + .init = mx6_arm2_fec_phy_init, + .power_hibernate = mx6_arm2_fec_power_hibernate, + .phy = PHY_INTERFACE_MODE_RGMII, +}; + +static int mx6_arm2_spi_cs[] = { + MX6_ARM2_ECSPI1_CS0, + MX6_ARM2_ECSPI1_CS1, +}; + +static const struct spi_imx_master mx6_arm2_spi_data __initconst = { + .chipselect = mx6_arm2_spi_cs, + .num_chipselect = ARRAY_SIZE(mx6_arm2_spi_cs), +}; + +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +static struct mtd_partition m25p32_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x00040000, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data m25p32_spi_flash_data = { + .name = "m25p32", + .parts = m25p32_partitions, + .nr_parts = ARRAY_SIZE(m25p32_partitions), + .type = "m25p32", +}; +#endif + +static struct spi_board_info m25p32_spi0_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) + { + /* The modalias must be the same as spi device driver name */ + .modalias = "m25p80", + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &m25p32_spi_flash_data, + }, +#endif +}; + +static void spi_device_init(void) +{ + spi_register_board_info(m25p32_spi0_board_info, + ARRAY_SIZE(m25p32_spi0_board_info)); +} + +static int max7310_1_setup(struct i2c_client *client, + unsigned gpio_base, unsigned ngpio, + void *context) +{ + int max7310_gpio_value[] = { 0, 1, 0, 1, 0, 0, 0, 0 }; + + int n; + + for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) { + gpio_request(gpio_base + n, "MAX7310 1 GPIO Expander"); + if (max7310_gpio_value[n] < 0) + gpio_direction_input(gpio_base + n); + else + gpio_direction_output(gpio_base + n, + max7310_gpio_value[n]); + gpio_export(gpio_base + n, 0); + } + + return 0; +} + +static struct pca953x_platform_data max7310_platdata = { + .gpio_base = MX6_ARM2_MAX7310_1_BASE_ADDR, + .invert = 0, + .setup = max7310_1_setup, +}; + +static int max7310_u48_setup(struct i2c_client *client, + unsigned gpio_base, unsigned ngpio, + void *context) +{ + int max7310_gpio_value[] = { 1, 1, 1, 1, 0, 1, 0, 0 }; + + int n; + + for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) { + gpio_request(gpio_base + n, "MAX7310 U48 GPIO Expander"); + if (max7310_gpio_value[n] < 0) + gpio_direction_input(gpio_base + n); + else + gpio_direction_output(gpio_base + n, + max7310_gpio_value[n]); + gpio_export(gpio_base + n, 0); + } + + return 0; +} + +static struct pca953x_platform_data max7310_u48_platdata = { + .gpio_base = MX6_ARM2_MAX7310_2_BASE_ADDR, + .invert = 0, + .setup = max7310_u48_setup, +}; + +static void ddc_dvi_init(void) +{ + /* enable DVI I2C */ + gpio_set_value(MX6_ARM2_DISP0_I2C_EN, 1); + + /* DISP0 Detect */ + gpio_request(MX6_ARM2_DISP0_DET_INT, "disp0-detect"); + gpio_direction_input(MX6_ARM2_DISP0_DET_INT); +} + +static int ddc_dvi_update(void) +{ + /* DVI cable state */ + if (gpio_get_value(MX6_ARM2_DISP0_DET_INT) == 1) + return 1; + return 0; +} + +static struct fsl_mxc_dvi_platform_data sabr_ddc_dvi_data = { + .ipu_id = 0, + .disp_id = 0, + .init = ddc_dvi_init, + .update = ddc_dvi_update, +}; + +static void mx6_csi0_io_init(void) +{ + if (0 == sgtl5000_en) { + iomux_v3_cfg_t *sensor_pads = NULL; + u32 sensor_pads_cnt; + + if (cpu_is_mx6q()) { + sensor_pads = mx6q_arm2_csi0_sensor_pads; + sensor_pads_cnt = \ + ARRAY_SIZE(mx6q_arm2_csi0_sensor_pads); + } else if (cpu_is_mx6dl()) { + sensor_pads = mx6dl_arm2_csi0_sensor_pads; + sensor_pads_cnt = \ + ARRAY_SIZE(mx6dl_arm2_csi0_sensor_pads); + } + + BUG_ON(!sensor_pads); + mxc_iomux_v3_setup_multiple_pads(sensor_pads, sensor_pads_cnt); + } + /* Camera reset */ + gpio_request(MX6_ARM2_CSI0_RST, "cam-reset"); + gpio_direction_output(MX6_ARM2_CSI0_RST, 1); + + /* Camera power down */ + gpio_request(MX6_ARM2_CSI0_PWN, "cam-pwdn"); + gpio_direction_output(MX6_ARM2_CSI0_PWN, 1); + msleep(1); + gpio_set_value(MX6_ARM2_CSI0_PWN, 0); + + /* For MX6Q: + * GPR1 bit19 and bit20 meaning: + * Bit19: 0 - Enable mipi to IPU1 CSI0 + * virtual channel is fixed to 0 + * 1 - Enable parallel interface to IPU1 CSI0 + * Bit20: 0 - Enable mipi to IPU2 CSI1 + * virtual channel is fixed to 3 + * 1 - Enable parallel interface to IPU2 CSI1 + * IPU1 CSI1 directly connect to mipi csi2, + * virtual channel is fixed to 1 + * IPU2 CSI0 directly connect to mipi csi2, + * virtual channel is fixed to 2 + * + * For MX6DL: + * GPR1 bit 21 and GPR13 bit 0-5, RM has detail information + */ + if (cpu_is_mx6q()) + mxc_iomux_set_gpr_register(1, 19, 1, 1); + else if (cpu_is_mx6dl()) + mxc_iomux_set_gpr_register(13, 0, 3, 4); +} + +static struct fsl_mxc_camera_platform_data camera_data = { + .analog_regulator = "DA9052_LDO7", + .core_regulator = "DA9052_LDO9", + .mclk = 24000000, + .csi = 0, + .io_init = mx6_csi0_io_init, +}; + +static void mx6_csi0_tvin_io_init(void) +{ + if (0 == sgtl5000_en) { + iomux_v3_cfg_t *tvin_pads = NULL; + u32 tvin_pads_cnt; + + if (cpu_is_mx6q()) { + tvin_pads = mx6q_arm2_csi0_tvin_pads; + tvin_pads_cnt = \ + ARRAY_SIZE(mx6q_arm2_csi0_tvin_pads); + } else if (cpu_is_mx6dl()) { + tvin_pads = mx6dl_arm2_csi0_tvin_pads; + tvin_pads_cnt = \ + ARRAY_SIZE(mx6dl_arm2_csi0_tvin_pads); + } + + BUG_ON(!tvin_pads); + mxc_iomux_v3_setup_multiple_pads(tvin_pads, tvin_pads_cnt); + } + /* Tvin reset */ + gpio_request(MX6_ARM2_CSI0_RST_TVIN, "tvin-reset"); + gpio_direction_output(MX6_ARM2_CSI0_RST_TVIN, 1); + + /* Tvin power down */ + gpio_request(MX6_ARM2_CSI0_PWN, "cam-pwdn"); + gpio_direction_output(MX6_ARM2_CSI0_PWN, 0); + msleep(1); + gpio_set_value(MX6_ARM2_CSI0_PWN, 1); + + if (cpu_is_mx6q()) + mxc_iomux_set_gpr_register(1, 19, 1, 1); + else if (cpu_is_mx6dl()) + mxc_iomux_set_gpr_register(13, 0, 3, 4); +} + +static struct fsl_mxc_tvin_platform_data tvin_data = { + .io_init = mx6_csi0_tvin_io_init, + .cvbs = false, +}; + +static void mx6_mipi_sensor_io_init(void) +{ + iomux_v3_cfg_t *mipi_sensor_pads = NULL; + u32 mipi_sensor_pads_cnt; + + if (cpu_is_mx6q()) { + mipi_sensor_pads = mx6q_arm2_mipi_sensor_pads; + mipi_sensor_pads_cnt = ARRAY_SIZE(mx6q_arm2_mipi_sensor_pads); + } else if (cpu_is_mx6dl()) { + mipi_sensor_pads = mx6dl_arm2_mipi_sensor_pads; + mipi_sensor_pads_cnt = ARRAY_SIZE(mx6dl_arm2_mipi_sensor_pads); + + } + BUG_ON(!mipi_sensor_pads); + mxc_iomux_v3_setup_multiple_pads(mipi_sensor_pads, + mipi_sensor_pads_cnt); + + if (cpu_is_mx6q()) + mxc_iomux_set_gpr_register(1, 19, 1, 0); + if (cpu_is_mx6dl()) + mxc_iomux_set_gpr_register(13, 0, 3, 0); +} + +static struct fsl_mxc_camera_platform_data ov5640_mipi_data = { + .mclk = 24000000, + .csi = 0, + .io_init = mx6_mipi_sensor_io_init, +}; + +static struct mxc_audio_codec_platform_data cs42888_data = { + .rates = (SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_176400), +}; + +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_consumer_supply display_consumers[] = { + { + /* MAX17135 */ + .supply = "DISPLAY", + }, +}; + +static struct regulator_consumer_supply vcom_consumers[] = { + { + /* MAX17135 */ + .supply = "VCOM", + }, +}; + +static struct regulator_consumer_supply v3p3_consumers[] = { + { + /* MAX17135 */ + .supply = "V3P3", + }, +}; + +static struct regulator_init_data max17135_init_data[] = { + { + .constraints = { + .name = "DISPLAY", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(display_consumers), + .consumer_supplies = display_consumers, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcom_consumers), + .consumer_supplies = vcom_consumers, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, { + .constraints = { + .name = "V3P3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(v3p3_consumers), + .consumer_supplies = v3p3_consumers, + }, +}; + +static struct platform_device max17135_sensor_device = { + .name = "max17135_sensor", + .id = 0, +}; + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = MX6DL_ARM2_EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = MX6DL_ARM2_EPDC_VCOM, + .gpio_pmic_wakeup = MX6DL_ARM2_EPDC_PMIC_WAKE, + .gpio_pmic_v3p3 = MX6DL_ARM2_EPDC_PWRCTRL0, + .gpio_pmic_intr = MX6DL_ARM2_EPDC_PMIC_INT, + .regulator_init = max17135_init_data, + .init = max17135_regulator_init, +}; + +static int __init max17135_regulator_init(struct max17135 *max17135) +{ + struct max17135_platform_data *pdata = &max17135_pdata; + int i, ret; + + if (!epdc_enabled) { + printk(KERN_DEBUG + "max17135_regulator_init abort: EPDC not enabled\n"); + return 0; + } + + max17135->gvee_pwrup = pdata->gvee_pwrup; + max17135->vneg_pwrup = pdata->vneg_pwrup; + max17135->vpos_pwrup = pdata->vpos_pwrup; + max17135->gvdd_pwrup = pdata->gvdd_pwrup; + max17135->gvdd_pwrdn = pdata->gvdd_pwrdn; + max17135->vpos_pwrdn = pdata->vpos_pwrdn; + max17135->vneg_pwrdn = pdata->vneg_pwrdn; + max17135->gvee_pwrdn = pdata->gvee_pwrdn; + + max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup + + pdata->gvdd_pwrup + pdata->gvee_pwrup; + + max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood; + max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl; + max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup; + max17135->gpio_pmic_v3p3 = pdata->gpio_pmic_v3p3; + max17135->gpio_pmic_intr = pdata->gpio_pmic_intr; + + gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake"); + gpio_direction_output(max17135->gpio_pmic_wakeup, 0); + + gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom"); + gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0); + + gpio_request(max17135->gpio_pmic_v3p3, "epdc-v3p3"); + gpio_direction_output(max17135->gpio_pmic_v3p3, 0); + + gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int"); + gpio_direction_input(max17135->gpio_pmic_intr); + + gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat"); + gpio_direction_input(max17135->gpio_pmic_pwrgood); + + max17135->vcom_setup = false; + max17135->init_done = false; + + for (i = 0; i < MAX17135_NUM_REGULATORS; i++) { + ret = max17135_register_regulator(max17135, i, + &pdata->regulator_init[i]); + if (ret != 0) { + printk(KERN_ERR"max17135 regulator init failed: %d\n", + ret); + return ret; + } + } + + regulator_has_full_constraints(); + + return 0; +} + +static int sii902x_get_pins(void) +{ + /* Sii902x HDMI controller */ + gpio_request(MX6_ARM2_DISP0_RESET, "disp0-reset"); + gpio_direction_output(MX6_ARM2_DISP0_RESET, 0); + gpio_request(MX6_ARM2_DISP0_DET_INT, "disp0-detect"); + gpio_direction_input(MX6_ARM2_DISP0_DET_INT); + return 1; +} + +static void sii902x_put_pins(void) +{ + gpio_free(MX6_ARM2_DISP0_RESET); + gpio_free(MX6_ARM2_DISP0_DET_INT); +} + +static void sii902x_hdmi_reset(void) +{ + gpio_set_value(MX6_ARM2_DISP0_RESET, 0); + msleep(10); + gpio_set_value(MX6_ARM2_DISP0_RESET, 1); + msleep(10); +} + +static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = { + .ipu_id = 0, + .disp_id = 0, + .reset = sii902x_hdmi_reset, + .get_pins = sii902x_get_pins, + .put_pins = sii902x_put_pins, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + I2C_BOARD_INFO("cs42888", 0x48), + .platform_data = (void *)&cs42888_data, + }, { + I2C_BOARD_INFO("ov5640", 0x3c), + .platform_data = (void *)&camera_data, + }, { + I2C_BOARD_INFO("adv7180", 0x21), + .platform_data = (void *)&tvin_data, + }, +}; + +static struct imxi2c_platform_data mx6_arm2_i2c0_data = { + .bitrate = 100000, +}; + +static struct imxi2c_platform_data mx6_arm2_i2c1_data = { + .bitrate = 100000, +}; + +static struct imxi2c_platform_data mx6_arm2_i2c2_data = { + .bitrate = 400000, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + I2C_BOARD_INFO("max17135", 0x48), + .platform_data = &max17135_pdata, + }, { + I2C_BOARD_INFO("max7310", 0x1F), + .platform_data = &max7310_platdata, + }, { + I2C_BOARD_INFO("max7310", 0x1B), + .platform_data = &max7310_u48_platdata, + }, { + I2C_BOARD_INFO("mxc_dvi", 0x50), + .platform_data = &sabr_ddc_dvi_data, + .irq = gpio_to_irq(MX6_ARM2_DISP0_DET_INT), + }, { + I2C_BOARD_INFO("egalax_ts", 0x4), + .irq = gpio_to_irq(MX6_ARM2_CAP_TCH_INT), + }, { + I2C_BOARD_INFO("sii902x", 0x39), + .platform_data = &sii902x_hdmi_data, + .irq = gpio_to_irq(MX6_ARM2_DISP0_DET_INT), + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + I2C_BOARD_INFO("egalax_ts", 0x4), + .irq = gpio_to_irq(MX6_ARM2_CAP_TCH_INT), + }, { + I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50), + }, { + I2C_BOARD_INFO("ov5640_mipi", 0x3c), + .platform_data = (void *)&ov5640_mipi_data, + }, { + I2C_BOARD_INFO("sgtl5000", 0x0a), + }, +}; + +static int epdc_get_pins(void) +{ + int ret = 0; + + /* Claim GPIOs for EPDC pins - used during power up/down */ + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_0, "epdc_d0"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_1, "epdc_d1"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_2, "epdc_d2"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_3, "epdc_d3"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_4, "epdc_d4"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_5, "epdc_d5"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_6, "epdc_d6"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_7, "epdc_d7"); + ret |= gpio_request(MX6DL_ARM2_EPDC_GDCLK, "epdc_gdclk"); + ret |= gpio_request(MX6DL_ARM2_EPDC_GDSP, "epdc_gdsp"); + ret |= gpio_request(MX6DL_ARM2_EPDC_GDOE, "epdc_gdoe"); + ret |= gpio_request(MX6DL_ARM2_EPDC_GDRL, "epdc_gdrl"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDCLK, "epdc_sdclk"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDOE, "epdc_sdoe"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDLE, "epdc_sdle"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDSHR, "epdc_sdshr"); + ret |= gpio_request(MX6DL_ARM2_EPDC_BDR0, "epdc_bdr0"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDCE0, "epdc_sdce0"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDCE1, "epdc_sdce1"); + ret |= gpio_request(MX6DL_ARM2_EPDC_SDCE2, "epdc_sdce2"); + + return ret; +} + +static void epdc_put_pins(void) +{ + gpio_free(MX6DL_ARM2_EPDC_SDDO_0); + gpio_free(MX6DL_ARM2_EPDC_SDDO_1); + gpio_free(MX6DL_ARM2_EPDC_SDDO_2); + gpio_free(MX6DL_ARM2_EPDC_SDDO_3); + gpio_free(MX6DL_ARM2_EPDC_SDDO_4); + gpio_free(MX6DL_ARM2_EPDC_SDDO_5); + gpio_free(MX6DL_ARM2_EPDC_SDDO_6); + gpio_free(MX6DL_ARM2_EPDC_SDDO_7); + gpio_free(MX6DL_ARM2_EPDC_GDCLK); + gpio_free(MX6DL_ARM2_EPDC_GDSP); + gpio_free(MX6DL_ARM2_EPDC_GDOE); + gpio_free(MX6DL_ARM2_EPDC_GDRL); + gpio_free(MX6DL_ARM2_EPDC_SDCLK); + gpio_free(MX6DL_ARM2_EPDC_SDOE); + gpio_free(MX6DL_ARM2_EPDC_SDLE); + gpio_free(MX6DL_ARM2_EPDC_SDSHR); + gpio_free(MX6DL_ARM2_EPDC_BDR0); + gpio_free(MX6DL_ARM2_EPDC_SDCE0); + gpio_free(MX6DL_ARM2_EPDC_SDCE1); + gpio_free(MX6DL_ARM2_EPDC_SDCE2); +} + +static iomux_v3_cfg_t mx6dl_epdc_pads_enabled[] = { + MX6DL_PAD_EIM_A16__EPDC_SDDO_0, + MX6DL_PAD_EIM_DA10__EPDC_SDDO_1, + MX6DL_PAD_EIM_DA12__EPDC_SDDO_2, + MX6DL_PAD_EIM_DA11__EPDC_SDDO_3, + MX6DL_PAD_EIM_LBA__EPDC_SDDO_4, + MX6DL_PAD_EIM_EB2__EPDC_SDDO_5, + MX6DL_PAD_EIM_CS0__EPDC_SDDO_6, + MX6DL_PAD_EIM_RW__EPDC_SDDO_7, + MX6DL_PAD_EIM_CS1__EPDC_SDDO_8, + MX6DL_PAD_EIM_DA15__EPDC_SDDO_9, + MX6DL_PAD_EIM_D16__EPDC_SDDO_10, + MX6DL_PAD_EIM_D23__EPDC_SDDO_11, + MX6DL_PAD_EIM_D19__EPDC_SDDO_12, + MX6DL_PAD_EIM_DA13__EPDC_SDDO_13, + MX6DL_PAD_EIM_DA14__EPDC_SDDO_14, + MX6DL_PAD_EIM_A25__EPDC_SDDO_15, + MX6DL_PAD_EIM_A21__EPDC_GDCLK, + MX6DL_PAD_EIM_A22__EPDC_GDSP, + MX6DL_PAD_EIM_A23__EPDC_GDOE, + MX6DL_PAD_EIM_A24__EPDC_GDRL, + MX6DL_PAD_EIM_D31__EPDC_SDCLK, + MX6DL_PAD_EIM_D27__EPDC_SDOE, + MX6DL_PAD_EIM_DA1__EPDC_SDLE, + MX6DL_PAD_EIM_EB1__EPDC_SDSHR, + MX6DL_PAD_EIM_DA2__EPDC_BDR_0, + MX6DL_PAD_EIM_DA4__EPDC_SDCE_0, + MX6DL_PAD_EIM_DA5__EPDC_SDCE_1, + MX6DL_PAD_EIM_DA6__EPDC_SDCE_2, +}; + +static iomux_v3_cfg_t mx6dl_epdc_pads_disabled[] = { + MX6DL_PAD_EIM_A16__GPIO_2_22, + MX6DL_PAD_EIM_DA10__GPIO_3_10, + MX6DL_PAD_EIM_DA12__GPIO_3_12, + MX6DL_PAD_EIM_DA11__GPIO_3_11, + MX6DL_PAD_EIM_LBA__GPIO_2_27, + MX6DL_PAD_EIM_EB2__GPIO_2_30, + MX6DL_PAD_EIM_CS0__GPIO_2_23, + MX6DL_PAD_EIM_RW__GPIO_2_26, + MX6DL_PAD_EIM_CS1__GPIO_2_24, + MX6DL_PAD_EIM_DA15__GPIO_3_15, + MX6DL_PAD_EIM_D16__GPIO_3_16, + MX6DL_PAD_EIM_D23__GPIO_3_23, + MX6DL_PAD_EIM_D19__GPIO_3_19, + MX6DL_PAD_EIM_DA13__GPIO_3_13, + MX6DL_PAD_EIM_DA14__GPIO_3_14, + MX6DL_PAD_EIM_A25__GPIO_5_2, + MX6DL_PAD_EIM_A21__GPIO_2_17, + MX6DL_PAD_EIM_A22__GPIO_2_16, + MX6DL_PAD_EIM_A23__GPIO_6_6, + MX6DL_PAD_EIM_A24__GPIO_5_4, + MX6DL_PAD_EIM_D31__GPIO_3_31, + MX6DL_PAD_EIM_D27__GPIO_3_27, + MX6DL_PAD_EIM_DA1__GPIO_3_1, + MX6DL_PAD_EIM_EB1__GPIO_2_29, + MX6DL_PAD_EIM_DA2__GPIO_3_2, + MX6DL_PAD_EIM_DA4__GPIO_3_4, + MX6DL_PAD_EIM_DA5__GPIO_3_5, + MX6DL_PAD_EIM_DA6__GPIO_3_6, +}; +static void epdc_enable_pins(void) +{ + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_multiple_pads(mx6dl_epdc_pads_enabled, \ + ARRAY_SIZE(mx6dl_epdc_pads_enabled)); + + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_0); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_1); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_2); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_3); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_4); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_5); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_6); + gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_7); + gpio_direction_input(MX6DL_ARM2_EPDC_GDCLK); + gpio_direction_input(MX6DL_ARM2_EPDC_GDSP); + gpio_direction_input(MX6DL_ARM2_EPDC_GDOE); + gpio_direction_input(MX6DL_ARM2_EPDC_GDRL); + gpio_direction_input(MX6DL_ARM2_EPDC_SDCLK); + gpio_direction_input(MX6DL_ARM2_EPDC_SDOE); + gpio_direction_input(MX6DL_ARM2_EPDC_SDLE); + gpio_direction_input(MX6DL_ARM2_EPDC_SDSHR); + gpio_direction_input(MX6DL_ARM2_EPDC_BDR0); + gpio_direction_input(MX6DL_ARM2_EPDC_SDCE0); + gpio_direction_input(MX6DL_ARM2_EPDC_SDCE1); + gpio_direction_input(MX6DL_ARM2_EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_multiple_pads(mx6dl_epdc_pads_disabled, \ + ARRAY_SIZE(mx6dl_epdc_pads_disabled)); + + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_0, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_1, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_2, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_3, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_4, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_5, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_6, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_7, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_GDCLK, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_GDSP, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_GDOE, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_GDRL, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDCLK, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDOE, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDLE, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDSHR, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_BDR0, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDCE0, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDCE1, 0); + gpio_direction_output(MX6DL_ARM2_EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_v110_mode = { + .name = "E60_V110", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 18604700, + .left_margin = 8, + .right_margin = 178, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +static struct fb_videomode e60_v220_mode = { + .name = "E60_V220", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 30000000, + .left_margin = 8, + .right_margin = 164, + .upper_margin = 4, + .lower_margin = 8, + .hsync_len = 4, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + .refresh = 85, + .xres = 800, + .yres = 600, +}; +static struct fb_videomode e060scm_mode = { + .name = "E060SCM", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 26666667, + .left_margin = 8, + .right_margin = 100, + .upper_margin = 4, + .lower_margin = 8, + .hsync_len = 4, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +static struct fb_videomode e97_v110_mode = { + .name = "E97_V110", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 12, + .right_margin = 128, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_epdc_fb_mode panel_modes[] = { + { + &e60_v110_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e60_v220_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 465, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 9, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e060scm_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 419, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 5, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e97_v110_mode, + 8, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 632, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 3, /* num_ce */ + } +}; + +static struct imx_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + +static void imx6_arm2_usbotg_vbus(bool on) +{ + if (on) + gpio_set_value(MX6_ARM2_USB_OTG_PWR, 1); + else + gpio_set_value(MX6_ARM2_USB_OTG_PWR, 0); +} + +static void __init mx6_arm2_init_usb(void) +{ + int ret = 0; + + imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR); + + /* disable external charger detect, + * or it will affect signal quality at dp. + */ + + ret = gpio_request(MX6_ARM2_USB_OTG_PWR, "usb-pwr"); + if (ret) { + pr_err("failed to get GPIO MX6_ARM2_USB_OTG_PWR:%d\n", ret); + return; + } + gpio_direction_output(MX6_ARM2_USB_OTG_PWR, 0); + mxc_iomux_set_gpr_register(1, 13, 1, 1); + + mx6_set_otghost_vbus_func(imx6_arm2_usbotg_vbus); + mx6_usb_dr_init(); + mx6_usb_h1_init(); +#ifdef CONFIG_USB_EHCI_ARC_HSIC + mx6_usb_h2_init(); + mx6_usb_h3_init(); +#endif +} + +static struct viv_gpu_platform_data imx6_gpu_pdata __initdata = { + .reserved_mem_size = SZ_128M, +}; + +/* HW Initialization, if return 0, initialization is successful. */ +static int mx6_arm2_sata_init(struct device *dev, void __iomem *addr) +{ + u32 tmpdata; + int ret = 0; + struct clk *clk; + + /* Enable SATA PWR CTRL_0 of MAX7310 */ + gpio_request(MX6_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN"); + gpio_direction_output(MX6_ARM2_MAX7310_1_BASE_ADDR, 1); + + sata_clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(sata_clk)) { + dev_err(dev, "no sata clock.\n"); + return PTR_ERR(sata_clk); + } + ret = clk_enable(sata_clk); + if (ret) { + dev_err(dev, "can't enable sata clock.\n"); + goto put_sata_clk; + } + + /* Set PHY Paremeters, two steps to configure the GPR13, + * one write for rest of parameters, mask of first write is 0x07FFFFFD, + * and the other one write for setting the mpll_clk_off_b + *.rx_eq_val_0(iomuxc_gpr13[26:24]), + *.los_lvl(iomuxc_gpr13[23:19]), + *.rx_dpll_mode_0(iomuxc_gpr13[18:16]), + *.sata_speed(iomuxc_gpr13[15]), + *.mpll_ss_en(iomuxc_gpr13[14]), + *.tx_atten_0(iomuxc_gpr13[13:11]), + *.tx_boost_0(iomuxc_gpr13[10:7]), + *.tx_lvl(iomuxc_gpr13[6:2]), + *.mpll_ck_off(iomuxc_gpr13[1]), + *.tx_edgerate_0(iomuxc_gpr13[0]), + */ + tmpdata = readl(IOMUXC_GPR13); + writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13); + + /* enable SATA_PHY PLL */ + tmpdata = readl(IOMUXC_GPR13); + writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13); + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(NULL, "ahb"); + if (IS_ERR(clk)) { + dev_err(dev, "no ahb clock.\n"); + ret = PTR_ERR(clk); + goto release_sata_clk; + } + tmpdata = clk_get_rate(clk) / 1000; + clk_put(clk); + + ret = sata_init(addr, tmpdata); + if (ret == 0) + return ret; + +release_sata_clk: + clk_disable(sata_clk); +put_sata_clk: + clk_put(sata_clk); + /* Disable SATA PWR CTRL_0 of MAX7310 */ + gpio_request(MX6_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN"); + gpio_direction_output(MX6_ARM2_MAX7310_1_BASE_ADDR, 0); + + return ret; +} + +static void mx6_arm2_sata_exit(struct device *dev) +{ + clk_disable(sata_clk); + clk_put(sata_clk); + + /* Disable SATA PWR CTRL_0 of MAX7310 */ + gpio_request(MX6_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN"); + gpio_direction_output(MX6_ARM2_MAX7310_1_BASE_ADDR, 0); + +} + +static struct ahci_platform_data mx6_arm2_sata_data = { + .init = mx6_arm2_sata_init, + .exit = mx6_arm2_sata_exit, +}; + +static struct imx_asrc_platform_data imx_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + +static void mx6_arm2_reset_mipi_dsi(void) +{ + gpio_set_value(MX6_ARM2_DISP0_PWR, 1); + gpio_set_value(MX6_ARM2_DISP0_RESET, 1); + udelay(10); + gpio_set_value(MX6_ARM2_DISP0_RESET, 0); + udelay(50); + gpio_set_value(MX6_ARM2_DISP0_RESET, 1); + + /* + * it needs to delay 120ms minimum for reset complete + */ + msleep(120); +} + +static struct mipi_dsi_platform_data mipi_dsi_pdata = { + .ipu_id = 1, + .disp_id = 1, + .lcd_panel = "TRULY-WVGA", + .reset = mx6_arm2_reset_mipi_dsi, +}; + +static struct ipuv3_fb_platform_data sabr_fb_data[] = { + { /*fb0*/ + .disp_dev = "ldb", + .interface_pix_fmt = IPU_PIX_FMT_RGB666, + .mode_str = "LDB-XGA", + .default_bpp = 16, + .int_clk = false, + }, { + .disp_dev = "mipi_dsi", + .interface_pix_fmt = IPU_PIX_FMT_RGB24, + .mode_str = "TRULY-WVGA", + .default_bpp = 24, + .int_clk = false, + }, { + .disp_dev = "ldb", + .interface_pix_fmt = IPU_PIX_FMT_RGB666, + .mode_str = "LDB-XGA", + .default_bpp = 16, + .int_clk = false, + }, { + .disp_dev = "lcd", + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .default_bpp = 16, + .int_clk = false, + } +}; + +static void hdmi_init(int ipu_id, int disp_id) +{ + int hdmi_mux_setting; + int max_ipu_id = cpu_is_mx6q() ? 1 : 0; + + if ((ipu_id > max_ipu_id) || (ipu_id < 0)) { + pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id); + ipu_id = 0; + } + + if ((disp_id > 1) || (disp_id < 0)) { + pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id); + disp_id = 0; + } + + /* Configure the connection between IPU1/2 and HDMI */ + hdmi_mux_setting = 2 * ipu_id + disp_id; + + /* GPR3, bits 2-3 = HDMI_MUX_CTL */ + mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting); +} + +static struct fsl_mxc_hdmi_platform_data hdmi_data = { + .init = hdmi_init, +}; + +static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = { + .ipu_id = 0, + .disp_id = 0, +}; + +static struct fsl_mxc_lcd_platform_data lcdif_data = { + .ipu_id = 0, + .disp_id = 0, + .default_ifmt = IPU_PIX_FMT_RGB565, +}; + +static struct fsl_mxc_ldb_platform_data ldb_data = { + .ipu_id = 1, + .disp_id = 0, + .ext_ref = 1, + .mode = LDB_SEP0, + .sec_ipu_id = 0, + .sec_disp_id = 1, +}; + +static struct imx_ipuv3_platform_data ipu_data[] = { + { + .rev = 4, + .csi_clk[0] = "clko_clk", + }, { + .rev = 4, + .csi_clk[0] = "clko_clk", + }, +}; + +static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +static struct gpio mx6_flexcan_gpios[] = { + { MX6_ARM2_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" }, + { MX6_ARM2_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" }, + { MX6_ARM2_CAN2_EN, GPIOF_OUT_INIT_LOW, "flexcan2-en" }, +}; + +static void mx6_flexcan0_switch(int enable) +{ + if (enable) { + gpio_set_value(MX6_ARM2_CAN1_EN, 1); + gpio_set_value(MX6_ARM2_CAN1_STBY, 1); + } else { + gpio_set_value(MX6_ARM2_CAN1_EN, 0); + gpio_set_value(MX6_ARM2_CAN1_STBY, 0); + } +} + +static void mx6_flexcan1_switch(int enable) +{ + if (enable) { + gpio_set_value(MX6_ARM2_CAN2_EN, 1); + gpio_set_value_cansleep(MX6_ARM2_CAN2_STBY, 1); + } else { + gpio_set_value(MX6_ARM2_CAN2_EN, 0); + gpio_set_value_cansleep(MX6_ARM2_CAN2_STBY, 0); + } +} + +static const struct flexcan_platform_data + mx6_arm2_flexcan_pdata[] __initconst = { + { + .transceiver_switch = mx6_flexcan0_switch, + }, { + .transceiver_switch = mx6_flexcan1_switch, + } +}; + +static struct mipi_csi2_platform_data mipi_csi2_pdata = { + .ipu_id = 0, + .csi_id = 0, + .v_channel = 0, + .lanes = 2, + .dphy_clk = "mipi_pllref_clk", + .pixel_clk = "emi_clk", +}; + +static void arm2_suspend_enter(void) +{ + /* suspend preparation */ +} + +static void arm2_suspend_exit(void) +{ + /* resmue resore */ +} +static const struct pm_platform_data mx6_arm2_pm_data __initconst = { + .name = "imx_pm", + .suspend_enter = arm2_suspend_enter, + .suspend_exit = arm2_suspend_exit, +}; + +static struct mxc_audio_platform_data sab_audio_data = { + .sysclk = 16934400, +}; + +static struct platform_device sab_audio_device = { + .name = "imx-cs42888", +}; + +static struct imx_esai_platform_data sab_esai_pdata = { + .flags = IMX_ESAI_NET, +}; + +static struct regulator_consumer_supply arm2_vmmc_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"), +}; + +static struct regulator_init_data arm2_vmmc_init = { + .num_consumer_supplies = ARRAY_SIZE(arm2_vmmc_consumers), + .consumer_supplies = arm2_vmmc_consumers, +}; + +static struct fixed_voltage_config arm2_vmmc_reg_config = { + .supply_name = "vmmc", + .microvolts = 3300000, + .gpio = -1, + .init_data = &arm2_vmmc_init, +}; + +static struct platform_device arm2_vmmc_reg_devices = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &arm2_vmmc_reg_config, + }, +}; + +#ifdef CONFIG_SND_SOC_CS42888 + +static struct regulator_consumer_supply cs42888_arm2_consumer_va = { + .supply = "VA", + .dev_name = "0-0048", +}; + +static struct regulator_consumer_supply cs42888_arm2_consumer_vd = { + .supply = "VD", + .dev_name = "0-0048", +}; + +static struct regulator_consumer_supply cs42888_arm2_consumer_vls = { + .supply = "VLS", + .dev_name = "0-0048", +}; + +static struct regulator_consumer_supply cs42888_arm2_consumer_vlc = { + .supply = "VLC", + .dev_name = "0-0048", +}; + +static struct regulator_init_data cs42888_arm2_va_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &cs42888_arm2_consumer_va, +}; + +static struct regulator_init_data cs42888_arm2_vd_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &cs42888_arm2_consumer_vd, +}; + +static struct regulator_init_data cs42888_arm2_vls_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &cs42888_arm2_consumer_vls, +}; + +static struct regulator_init_data cs42888_arm2_vlc_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &cs42888_arm2_consumer_vlc, +}; + +static struct fixed_voltage_config cs42888_arm2_va_reg_config = { + .supply_name = "VA", + .microvolts = 2800000, + .gpio = -1, + .init_data = &cs42888_arm2_va_reg_initdata, +}; + +static struct fixed_voltage_config cs42888_arm2_vd_reg_config = { + .supply_name = "VD", + .microvolts = 2800000, + .gpio = -1, + .init_data = &cs42888_arm2_vd_reg_initdata, +}; + +static struct fixed_voltage_config cs42888_arm2_vls_reg_config = { + .supply_name = "VLS", + .microvolts = 2800000, + .gpio = -1, + .init_data = &cs42888_arm2_vls_reg_initdata, +}; + +static struct fixed_voltage_config cs42888_arm2_vlc_reg_config = { + .supply_name = "VLC", + .microvolts = 2800000, + .gpio = -1, + .init_data = &cs42888_arm2_vlc_reg_initdata, +}; + +static struct platform_device cs42888_arm2_va_reg_devices = { + .name = "reg-fixed-voltage", + .id = 3, + .dev = { + .platform_data = &cs42888_arm2_va_reg_config, + }, +}; + +static struct platform_device cs42888_arm2_vd_reg_devices = { + .name = "reg-fixed-voltage", + .id = 4, + .dev = { + .platform_data = &cs42888_arm2_vd_reg_config, + }, +}; + +static struct platform_device cs42888_arm2_vls_reg_devices = { + .name = "reg-fixed-voltage", + .id = 5, + .dev = { + .platform_data = &cs42888_arm2_vls_reg_config, + }, +}; + +static struct platform_device cs42888_arm2_vlc_reg_devices = { + .name = "reg-fixed-voltage", + .id = 6, + .dev = { + .platform_data = &cs42888_arm2_vlc_reg_config, + }, +}; + +#endif /* CONFIG_SND_SOC_CS42888 */ + +#ifdef CONFIG_SND_SOC_SGTL5000 + +static struct regulator_consumer_supply sgtl5000_arm2_consumer_vdda = { + .supply = "VDDA", + .dev_name = "1-000a", +}; + +static struct regulator_consumer_supply sgtl5000_arm2_consumer_vddio = { + .supply = "VDDIO", + .dev_name = "1-000a", +}; + +static struct regulator_consumer_supply sgtl5000_arm2_consumer_vddd = { + .supply = "VDDD", + .dev_name = "1-000a", +}; + +static struct regulator_init_data sgtl5000_arm2_vdda_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &sgtl5000_arm2_consumer_vdda, +}; + +static struct regulator_init_data sgtl5000_arm2_vddio_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &sgtl5000_arm2_consumer_vddio, +}; + +static struct regulator_init_data sgtl5000_arm2_vddd_reg_initdata = { + .num_consumer_supplies = 1, + .consumer_supplies = &sgtl5000_arm2_consumer_vddd, +}; + +static struct fixed_voltage_config sgtl5000_arm2_vdda_reg_config = { + .supply_name = "VDDA", + .microvolts = 1800000, + .gpio = -1, + .init_data = &sgtl5000_arm2_vdda_reg_initdata, +}; + +static struct fixed_voltage_config sgtl5000_arm2_vddio_reg_config = { + .supply_name = "VDDIO", + .microvolts = 3300000, + .gpio = -1, + .init_data = &sgtl5000_arm2_vddio_reg_initdata, +}; + +static struct fixed_voltage_config sgtl5000_arm2_vddd_reg_config = { + .supply_name = "VDDD", + .microvolts = 0, + .gpio = -1, + .init_data = &sgtl5000_arm2_vddd_reg_initdata, +}; + +static struct platform_device sgtl5000_arm2_vdda_reg_devices = { + .name = "reg-fixed-voltage", + .id = 7, + .dev = { + .platform_data = &sgtl5000_arm2_vdda_reg_config, + }, +}; + +static struct platform_device sgtl5000_arm2_vddio_reg_devices = { + .name = "reg-fixed-voltage", + .id = 8, + .dev = { + .platform_data = &sgtl5000_arm2_vddio_reg_config, + }, +}; + +static struct platform_device sgtl5000_arm2_vddd_reg_devices = { + .name = "reg-fixed-voltage", + .id = 9, + .dev = { + .platform_data = &sgtl5000_arm2_vddd_reg_config, + }, +}; + +#endif /* CONFIG_SND_SOC_SGTL5000 */ + +static struct mxc_audio_platform_data mx6_arm2_audio_data; + +static int mx6_arm2_sgtl5000_init(void) +{ + + mx6_arm2_audio_data.sysclk = 12000000; + + return 0; +} + +static struct imx_ssi_platform_data mx6_arm2_ssi_pdata = { + .flags = IMX_SSI_DMA | IMX_SSI_SYN, +}; + +static struct mxc_audio_platform_data mx6_arm2_audio_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .init = mx6_arm2_sgtl5000_init, + .hp_gpio = -1, +}; + +static struct platform_device mx6_arm2_audio_device = { + .name = "imx-sgtl5000", +}; + +static int __init mx6_arm2_init_audio(void) +{ + struct clk *pll3_pfd, *esai_clk; + mxc_register_device(&sab_audio_device, &sab_audio_data); + imx6q_add_imx_esai(0, &sab_esai_pdata); + + esai_clk = clk_get(NULL, "esai_clk"); + if (IS_ERR(esai_clk)) + return PTR_ERR(esai_clk); + + pll3_pfd = clk_get(NULL, "pll3_pfd_508M"); + if (IS_ERR(pll3_pfd)) + return PTR_ERR(pll3_pfd); + + clk_set_parent(esai_clk, pll3_pfd); + clk_set_rate(esai_clk, 101647058); + +#ifdef CONFIG_SND_SOC_CS42888 + platform_device_register(&cs42888_arm2_va_reg_devices); + platform_device_register(&cs42888_arm2_vd_reg_devices); + platform_device_register(&cs42888_arm2_vls_reg_devices); + platform_device_register(&cs42888_arm2_vlc_reg_devices); +#endif + + if (sgtl5000_en) { + /* SSI audio init part */ + mxc_register_device(&mx6_arm2_audio_device, + &mx6_arm2_audio_data); + imx6q_add_imx_ssi(1, &mx6_arm2_ssi_pdata); + + /* + * AUDMUX3 and CSI0_Camera use the same pin + * MX6x_PAD_CSI0_DAT5 + */ + if (cpu_is_mx6q()) { + mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_audmux_pads, + ARRAY_SIZE(mx6q_arm2_audmux_pads)); + } else if (cpu_is_mx6dl()) { + mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_audmux_pads, + ARRAY_SIZE(mx6dl_arm2_audmux_pads)); + } + +#ifdef CONFIG_SND_SOC_SGTL5000 + platform_device_register(&sgtl5000_arm2_vdda_reg_devices); + platform_device_register(&sgtl5000_arm2_vddio_reg_devices); + platform_device_register(&sgtl5000_arm2_vddd_reg_devices); +#endif + } + + return 0; +} + +static int __init early_use_esai_record(char *p) +{ + esai_record = 1; + return 0; +} + +early_param("esai_record", early_use_esai_record); + +static struct mxc_mlb_platform_data mx6_arm2_mlb150_data = { + .reg_nvcc = NULL, + .mlb_clk = "mlb150_clk", + .mlb_pll_clk = "pll6", +}; + +static struct mxc_dvfs_platform_data arm2_dvfscore_data = { + .reg_id = "cpu_vddgp", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 80, +}; + +static void __init mx6_arm2_fixup(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ +} + +static int __init early_enable_sgtl5000(char *p) +{ + sgtl5000_en = 1; + return 0; +} + +early_param("sgtl5000", early_enable_sgtl5000); + +static int __init early_enable_spdif(char *p) +{ + spdif_en = 1; + return 0; +} + +early_param("spdif", early_enable_spdif); + +static int __init early_enable_can(char *p) +{ + flexcan_en = 1; + return 0; +} + +early_param("flexcan", early_enable_can); + +static int spdif_clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long rate_actual; + rate_actual = clk_round_rate(clk, rate); + clk_set_rate(clk, rate_actual); + return 0; +} + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, /* enable tx */ + .spdif_rx = 1, /* enable rx */ + /* + * spdif0_clk will be 454.7MHz divided by ccm dividers. + * + * 44.1KHz: 454.7MHz / 7 (ccm) / 23 (spdif) = 44,128 Hz ~ 0.06% error + * 48KHz: 454.7MHz / 4 (ccm) / 37 (spdif) = 48,004 Hz ~ 0.01% error + * 32KHz: 454.7MHz / 6 (ccm) / 37 (spdif) = 32,003 Hz ~ 0.01% error + */ + .spdif_clk_44100 = 1, /* tx clk from spdif0_clk_root */ + .spdif_clk_48000 = 1, /* tx clk from spdif0_clk_root */ + .spdif_div_44100 = 23, + .spdif_div_48000 = 37, + .spdif_div_32000 = 37, + .spdif_rx_clk = 0, /* rx clk from spdif stream */ + .spdif_clk_set_rate = spdif_clk_set_rate, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static int __init early_disable_mipi_dsi(char *p) +{ + /*enable on board HDMI*/ + /*mulplex pin with mipi disp0_reset we should disable mipi reset*/ + disable_mipi_dsi = 1; + return 0; +} + +early_param("disable_mipi_dsi", early_disable_mipi_dsi); + +/*! + * Board specific initialization. + */ +static void __init mx6_arm2_init(void) +{ + int i; + int ret; + + iomux_v3_cfg_t *common_pads = NULL; + iomux_v3_cfg_t *esai_rec_pads = NULL; + iomux_v3_cfg_t *spdif_pads = NULL; + iomux_v3_cfg_t *flexcan_pads = NULL; + iomux_v3_cfg_t *i2c3_pads = NULL; + + int common_pads_cnt; + int esai_rec_pads_cnt; + int spdif_pads_cnt; + int flexcan_pads_cnt; + int i2c3_pads_cnt; + + + /* + * common pads: pads are non-shared with others on this board + * feature_pds: pads are shared with others on this board + */ + + if (cpu_is_mx6q()) { + common_pads = mx6q_arm2_pads; + esai_rec_pads = mx6q_arm2_esai_record_pads; + spdif_pads = mx6q_arm2_spdif_pads; + flexcan_pads = mx6q_arm2_can_pads; + i2c3_pads = mx6q_arm2_i2c3_pads; + + common_pads_cnt = ARRAY_SIZE(mx6q_arm2_pads); + esai_rec_pads_cnt = ARRAY_SIZE(mx6q_arm2_esai_record_pads); + spdif_pads_cnt = ARRAY_SIZE(mx6q_arm2_spdif_pads); + flexcan_pads_cnt = ARRAY_SIZE(mx6q_arm2_can_pads); + i2c3_pads_cnt = ARRAY_SIZE(mx6q_arm2_i2c3_pads); + } else if (cpu_is_mx6dl()) { + common_pads = mx6dl_arm2_pads; + esai_rec_pads = mx6dl_arm2_esai_record_pads; + spdif_pads = mx6dl_arm2_spdif_pads; + flexcan_pads = mx6dl_arm2_can_pads; + i2c3_pads = mx6dl_arm2_i2c3_pads; + + common_pads_cnt = ARRAY_SIZE(mx6dl_arm2_pads); + esai_rec_pads_cnt = ARRAY_SIZE(mx6dl_arm2_esai_record_pads); + spdif_pads_cnt = ARRAY_SIZE(mx6dl_arm2_spdif_pads); + flexcan_pads_cnt = ARRAY_SIZE(mx6dl_arm2_can_pads); + i2c3_pads_cnt = ARRAY_SIZE(mx6dl_arm2_i2c3_pads); + } + + BUG_ON(!common_pads); + mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt); + + if (esai_record) { + BUG_ON(!esai_rec_pads); + mxc_iomux_v3_setup_multiple_pads(esai_rec_pads, + esai_rec_pads_cnt); + } + + /* + * IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive + * because all of them use GPIO_16. + * S/PDIF out and can1 stby are mutually exclusive because both + * use GPIO_17. + */ +#ifndef CONFIG_FEC_1588 + if (spdif_en) { + BUG_ON(!spdif_pads); + mxc_iomux_v3_setup_multiple_pads(spdif_pads, spdif_pads_cnt); + } else { + BUG_ON(!i2c3_pads); + mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt); + } +#else + /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock + * For MX6 GPR1 bit21 meaning: + * Bit21: 0 - GPIO_16 pad output + * 1 - GPIO_16 pad input + */ + mxc_iomux_set_gpr_register(1, 21, 1, 1); +#endif + + if (!spdif_en && flexcan_en) { + BUG_ON(!flexcan_pads); + mxc_iomux_v3_setup_multiple_pads(flexcan_pads, + flexcan_pads_cnt); + } + + /* + * the following is the common devices support on the shared ARM2 boards + * Since i.MX6DQ/DL share the same memory/Register layout, we don't + * need to diff the i.MX6DQ or i.MX6DL here. We can simply use the + * mx6q_add_features() for the shared devices. For which only exist + * on each indivual SOC, we can use cpu_is_mx6q/6dl() to diff it. + */ + + gp_reg_id = arm2_dvfscore_data.reg_id; + mx6_arm2_init_uart(); + imx6q_add_mipi_csi2(&mipi_csi2_pdata); + imx6q_add_mxc_hdmi_core(&hdmi_core_data); + + imx6q_add_ipuv3(0, &ipu_data[0]); + if (cpu_is_mx6q()) + imx6q_add_ipuv3(1, &ipu_data[1]); + + if (cpu_is_mx6dl()) { + mipi_dsi_pdata.ipu_id = 0; + mipi_dsi_pdata.disp_id = 1; + ldb_data.ipu_id = 0; + ldb_data.disp_id = 0; + for (i = 0; i < ARRAY_SIZE(sabr_fb_data) / 2; i++) + imx6q_add_ipuv3fb(i, &sabr_fb_data[i]); + } else { + for (i = 0; i < ARRAY_SIZE(sabr_fb_data); i++) + imx6q_add_ipuv3fb(i, &sabr_fb_data[i]); + } + + if (!disable_mipi_dsi) + imx6q_add_mipi_dsi(&mipi_dsi_pdata); + imx6q_add_lcdif(&lcdif_data); + imx6q_add_ldb(&ldb_data); + imx6q_add_v4l2_output(0); + imx6q_add_v4l2_capture(0); + + imx6q_add_imx_snvs_rtc(); + + imx6q_add_imx_i2c(0, &mx6_arm2_i2c0_data); + imx6q_add_imx_i2c(1, &mx6_arm2_i2c1_data); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + if (!spdif_en) { + if (disable_mipi_dsi) + mx6_arm2_i2c2_data.bitrate = 100000; + imx6q_add_imx_i2c(2, &mx6_arm2_i2c2_data); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + } + + /* SPI */ + imx6q_add_ecspi(0, &mx6_arm2_spi_data); + spi_device_init(); + + imx6q_add_mxc_hdmi(&hdmi_data); + + imx6q_add_anatop_thermal_imx(1, &mx6_arm2_anatop_thermal_data); + + if (!esai_record) + imx6_init_fec(fec_data); + + imx6q_add_pm_imx(0, &mx6_arm2_pm_data); + imx6q_add_sdhci_usdhc_imx(3, &mx6_arm2_sd4_data); + imx6q_add_sdhci_usdhc_imx(2, &mx6_arm2_sd3_data); + imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata); + if (cpu_is_mx6q()) + imx6q_add_ahci(0, &mx6_arm2_sata_data); + imx6q_add_vpu(); + mx6_arm2_init_usb(); + mx6_arm2_init_audio(); + platform_device_register(&arm2_vmmc_reg_devices); + mx6_cpu_regulator_init(); + + imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + imx6q_add_asrc(&imx_asrc_data); + + /* DISP0 Reset - Assert for i2c disabled mode */ + gpio_request(MX6_ARM2_DISP0_RESET, "disp0-reset"); + gpio_direction_output(MX6_ARM2_DISP0_RESET, 0); + + /* DISP0 I2C enable */ + if (!disable_mipi_dsi) { + gpio_request(MX6_ARM2_DISP0_I2C_EN, "disp0-i2c"); + gpio_direction_output(MX6_ARM2_DISP0_I2C_EN, 0); + } + gpio_request(MX6_ARM2_DISP0_PWR, "disp0-pwr"); + gpio_direction_output(MX6_ARM2_DISP0_PWR, 1); + + gpio_request(MX6_ARM2_LDB_BACKLIGHT, "ldb-backlight"); + gpio_direction_output(MX6_ARM2_LDB_BACKLIGHT, 1); + imx6q_add_otp(); + imx6q_add_viim(); + imx6q_add_imx2_wdt(0, NULL); + imx6q_add_dma(); + imx6q_add_gpmi(&mx6_gpmi_nand_platform_data); + + imx6q_add_dvfs_core(&arm2_dvfscore_data); + + imx6q_add_mxc_pwm(0); + imx6q_add_mxc_pwm_backlight(0, &mx6_arm2_pwm_backlight_data); + + if (spdif_en) { + mxc_spdif_data.spdif_core_clk = clk_get_sys("mxc_spdif.0", NULL); + clk_put(mxc_spdif_data.spdif_core_clk); + imx6q_add_spdif(&mxc_spdif_data); + imx6q_add_spdif_dai(); + imx6q_add_spdif_audio_device(); + } else if (flexcan_en) { + ret = gpio_request_array(mx6_flexcan_gpios, + ARRAY_SIZE(mx6_flexcan_gpios)); + if (ret) { + pr_err("failed to request flexcan-gpios: %d\n", ret); + } else { + imx6q_add_flexcan0(&mx6_arm2_flexcan_pdata[0]); + imx6q_add_flexcan1(&mx6_arm2_flexcan_pdata[1]); + } + } + + imx6q_add_hdmi_soc(); + imx6q_add_hdmi_soc_dai(); + imx6q_add_perfmon(0); + imx6q_add_perfmon(1); + imx6q_add_perfmon(2); + imx6q_add_mlb150(&mx6_arm2_mlb150_data); + + if (cpu_is_mx6dl() && epdc_enabled) { + imx6dl_add_imx_pxp(); + imx6dl_add_imx_pxp_client(); + mxc_register_device(&max17135_sensor_device, NULL); + imx6dl_add_imx_epdc(&epdc_data); + } +} + +extern void __iomem *twd_base; +static void __init mx6_timer_init(void) +{ + struct clk *uart_clk; +#ifdef CONFIG_LOCAL_TIMERS + twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256); + BUG_ON(!twd_base); +#endif + mx6_clocks_init(32768, 24000000, 0, 0); + + uart_clk = clk_get_sys("imx-uart.0", NULL); + early_console_setup(UART4_BASE_ADDR, uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx6_timer_init, +}; + +static void __init mx6_arm2_reserve(void) +{ + phys_addr_t phys; + + if (imx6_gpu_pdata.reserved_mem_size) { + phys = memblock_alloc_base( + imx6_gpu_pdata.reserved_mem_size, SZ_4K, SZ_2G); + memblock_free(phys, imx6_gpu_pdata.reserved_mem_size); + memblock_remove(phys, imx6_gpu_pdata.reserved_mem_size); + imx6_gpu_pdata.reserved_mem_base = phys; + } +} + +MACHINE_START(MX6Q_ARM2, "Freescale i.MX 6Quad/Solo/DualLite Armadillo2 Board") + .boot_params = MX6_PHYS_OFFSET + 0x100, + .fixup = mx6_arm2_fixup, + .map_io = mx6_map_io, + .init_irq = mx6_init_irq, + .init_machine = mx6_arm2_init, + .timer = &mxc_timer, + .reserve = mx6_arm2_reserve, +MACHINE_END diff --git a/arch/arm/mach-mvf/board-twr_vf600.h b/arch/arm/mach-mvf/board-twr_vf600.h new file mode 100644 index 000000000000..21c050baf4b1 --- /dev/null +++ b/arch/arm/mach-mvf/board-twr_vf600.h @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/iomux-vfxx.h> + +static iomux_v3_cfg_t vf6xx_arm2_pads[] = { + /* primary function */ + VF6XX_PAD_PAD_0__CCM_RMII_CLKIN, + VF6XX_PAD_PAD_1__DEBUG_TCLK, + VF6XX_PAD_PAD_2__DEBUG_TDI, + VF6XX_PAD_PAD_3__DEBUG_TDO, + VF6XX_PAD_PAD_4__DEBUG_TMS, + VF6XX_PAD_PAD_5__PLATFORM_TRACECK, + VF6XX_PAD_PAD_6__SAI2_TX_BCLK, + VF6XX_PAD_PAD_7__PLATFORM_TRACED1, + VF6XX_PAD_PAD_8__SAI2_TX_DATA, + VF6XX_PAD_PAD_9__SAI2_TX_SYNC, + VF6XX_PAD_PAD_10__RGPIOC_GPIO10, + VF6XX_PAD_PAD_11__SAI2_RX_BCLK, + VF6XX_PAD_PAD_12__SAI2_RX_DATA, + VF6XX_PAD_PAD_13__SAI2_RX_SYNC, + VF6XX_PAD_PAD_14__ESDHC1_CLK, + VF6XX_PAD_PAD_15__ESDHC1_CMD, + VF6XX_PAD_PAD_16__ESDHC1_DAT0, + VF6XX_PAD_PAD_17__ESDHC1_DAT1, + VF6XX_PAD_PAD_18__ESDHC1_DAT2, + VF6XX_PAD_PAD_19__ESDHC1_DAT3, + VF6XX_PAD_PAD_20__RGPIOC_GPIO20, + VF6XX_PAD_PAD_21__RGPIOC_GPIO21, + VF6XX_PAD_PAD_22__FLEXTIMER0_CH0, + VF6XX_PAD_PAD_23__FLEXTIMER0_CH1, + VF6XX_PAD_PAD_24__FLEXTIMER0_CH2, + VF6XX_PAD_PAD_25__FLEXTIMER0_CH3, + VF6XX_PAD_PAD_26__SCI_FLX1_TX, + VF6XX_PAD_PAD_27__SCI_FLX1_RX, + VF6XX_PAD_PAD_28__SCI_FLX1_RTS, + VF6XX_PAD_PAD_29__SCI_FLX1_CTS, + VF6XX_PAD_PAD_30__FLEXTIMER1_CH0, + VF6XX_PAD_PAD_31__FLEXTIMER1_CH1, + VF6XX_PAD_PAD_32__RGPIOC_GPIO32, + VF6XX_PAD_PAD_33__RGPIOC_GPIO33, + VF6XX_PAD_PAD_34__RGPIOC_GPIO34, + VF6XX_PAD_PAD_35__PLATFORM_TRACETL, + VF6XX_PAD_PAD_36__I2C0_SCL, + VF6XX_PAD_PAD_37__I2C0_SDA, + VF6XX_PAD_PAD_38__RGPIOC_GPIO38, + VF6XX_PAD_PAD_39__RGPIOC_GPIO39, + VF6XX_PAD_PAD_40__CCM_EXT_AUDIO_MCLK, + VF6XX_PAD_PAD_41__DSPI0_CS0, + VF6XX_PAD_PAD_42__DSPI0_SIN, + VF6XX_PAD_PAD_43__DSPI0_SOUT, + VF6XX_PAD_PAD_44__DSPI0_SCK, + VF6XX_PAD_PAD_45__ENET_SWIAHB_RMII0_MDC, + VF6XX_PAD_PAD_46__ENET_SWIAHB_RMII0_MDIO, + VF6XX_PAD_PAD_47__ENET_SWIAHB_RMII0_CRS_DV, + VF6XX_PAD_PAD_48__ENET_SWIAHB_RMII0_RXD1, + VF6XX_PAD_PAD_49__ENET_SWIAHB_RMII0_RXD0, + VF6XX_PAD_PAD_50__ENET_SWIAHB_RMII0_RXER, + VF6XX_PAD_PAD_51__ENET_SWIAHB_RMII0_TXD1, + VF6XX_PAD_PAD_52__ENET_SWIAHB_RMII0_TXD0, + VF6XX_PAD_PAD_53__ENET_SWIAHB_RMII0_TXEN, + VF6XX_PAD_PAD_54__ENET_SWIAHB_RMII1_MDC, + VF6XX_PAD_PAD_55__ENET_SWIAHB_RMII1_MDIO, + VF6XX_PAD_PAD_56__ENET_SWIAHB_RMII1_CRS_DV, + VF6XX_PAD_PAD_57__ENET_SWIAHB_RMII1_RXD1, + VF6XX_PAD_PAD_58__ENET_SWIAHB_RMII1_RXD0, + VF6XX_PAD_PAD_59__ENET_SWIAHB_RMII1_RXER, + VF6XX_PAD_PAD_60__ENET_SWIAHB_RMII1_TXD1, + VF6XX_PAD_PAD_61__ENET_SWIAHB_RMII1_TXD0, + VF6XX_PAD_PAD_62__ENET_SWIAHB_RMII1_TXEN, + VF6XX_PAD_PAD_63__NFC_MLC_NF_IO15, + VF6XX_PAD_PAD_64__NFC_MLC_NF_IO14, + VF6XX_PAD_PAD_65__NFC_MLC_NF_IO13, + VF6XX_PAD_PAD_66__NFC_MLC_NF_IO12, + VF6XX_PAD_PAD_67__NFC_MLC_NF_IO11, + VF6XX_PAD_PAD_68__NFC_MLC_NF_IO10, + VF6XX_PAD_PAD_69__NFC_MLC_NF_IO9, + VF6XX_PAD_PAD_70__NFC_MLC_NF_IO8, + VF6XX_PAD_PAD_71__NFC_MLC_NF_IO7, + VF6XX_PAD_PAD_72__NFC_MLC_NF_IO6, + VF6XX_PAD_PAD_73__NFC_MLC_NF_IO5, + VF6XX_PAD_PAD_74__NFC_MLC_NF_IO4, + VF6XX_PAD_PAD_75__NFC_MLC_NF_IO3, + VF6XX_PAD_PAD_76__NFC_MLC_NF_IO2, + VF6XX_PAD_PAD_77__NFC_MLC_NF_IO1, + VF6XX_PAD_PAD_78__NFC_MLC_NF_IO0, + VF6XX_PAD_PAD_79__QUADSPI0_QSCK_A, + VF6XX_PAD_PAD_80__QUADSPI0_QPCS0_A, + VF6XX_PAD_PAD_81__QUADSPI0_QSPI_IO3_A, + VF6XX_PAD_PAD_82__QUADSPI0_QSPI_IO2_A, + VF6XX_PAD_PAD_83__QUADSPI0_QSPI_IO1_A, + VF6XX_PAD_PAD_84__QUADSPI0_QSPI_IO0_A, + VF6XX_PAD_PAD_85__RGPIOC_GPIO85, + VF6XX_PAD_PAD_86__QUADSPI0_QSCK_B, + VF6XX_PAD_PAD_87__QUADSPI0_QPCS0_B, + VF6XX_PAD_PAD_88__QUADSPI0_QSPI_IO3_B, + VF6XX_PAD_PAD_89__QUADSPI0_QSPI_IO2_B, + VF6XX_PAD_PAD_90__QUADSPI0_QSPI_IO1_B, + VF6XX_PAD_PAD_91__QUADSPI0_QSPI_IO0_B, + VF6XX_PAD_PAD_92__RGPIOC_GPIO92, + VF6XX_PAD_PAD_93__RGPIOC_GPIO93, + VF6XX_PAD_PAD_94__NFC_MLC_NF_WE_B, + VF6XX_PAD_PAD_95__NFC_MLC_NF_CE0_B, + VF6XX_PAD_PAD_96__RGPIOC_GPIO96, + VF6XX_PAD_PAD_97__NFC_MLC_NF_RE_B, + VF6XX_PAD_PAD_98__RGPIOC_GPIO98, + VF6XX_PAD_PAD_99__NFC_MLC_NF_RB_B, + VF6XX_PAD_PAD_100__NFC_MLC_NF_ALE, + VF6XX_PAD_PAD_101__NFC_MLC_NF_CLE, +, + VF6XX_PAD_PAD_103__ADC0_DA_ADC0SE5, + VF6XX_PAD_PAD_104__ADC1_DA_ADC1SE5, + VF6XX_PAD_PAD_105__TCON0_TCON1, + VF6XX_PAD_PAD_106__TCON0_TCON2, + VF6XX_PAD_PAD_107__TCON0_DATA_OUT1, + VF6XX_PAD_PAD_108__RGPIOC_GPIO108, + VF6XX_PAD_PAD_109__TCON0_TCON3, + VF6XX_PAD_PAD_110__TCON0_DATA_OUT18, + VF6XX_PAD_PAD_111__TCON0_DATA_OUT19, + VF6XX_PAD_PAD_112__TCON0_DATA_OUT20, + VF6XX_PAD_PAD_113__TCON0_DATA_OUT21, + VF6XX_PAD_PAD_114__TCON0_DATA_OUT22, + VF6XX_PAD_PAD_115__TCON0_DATA_OUT23, + VF6XX_PAD_PAD_116__TCON0_DATA_OUT24, + VF6XX_PAD_PAD_117__TCON0_DATA_OUT25, + VF6XX_PAD_PAD_118__TCON0_DATA_OUT10, + VF6XX_PAD_PAD_119__TCON0_DATA_OUT11, + VF6XX_PAD_PAD_120__TCON0_DATA_OUT12, + VF6XX_PAD_PAD_121__TCON0_DATA_OUT13, + VF6XX_PAD_PAD_122__TCON0_DATA_OUT14, + VF6XX_PAD_PAD_123__TCON0_DATA_OUT15, + VF6XX_PAD_PAD_124__TCON0_DATA_OUT16, + VF6XX_PAD_PAD_125__TCON0_DATA_OUT17, + VF6XX_PAD_PAD_126__TCON0_DATA_OUT2, + VF6XX_PAD_PAD_127__TCON0_DATA_OUT3, + VF6XX_PAD_PAD_128__TCON0_DATA_OUT4, + VF6XX_PAD_PAD_129__TCON0_DATA_OUT5, + VF6XX_PAD_PAD_130__TCON0_DATA_OUT6, + VF6XX_PAD_PAD_131__TCON0_DATA_OUT7, + VF6XX_PAD_PAD_132__TCON0_DATA_OUT8, + VF6XX_PAD_PAD_133__TCON0_DATA_OUT9, + VF6XX_PAD_PAD_134__RGPIOC_GPIO134 + +}; + diff --git a/arch/arm/mach-mvf/bus_freq.c b/arch/arm/mach-mvf/bus_freq.c new file mode 100644 index 000000000000..36308c14c8f2 --- /dev/null +++ b/arch/arm/mach-mvf/bus_freq.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file bus_freq.c + * + * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module + * and DVFS CORE module. + * + * The APIs are for setting bus frequency to low or high. + * + * @ingroup PM + */ +#include <asm/io.h> +#include <linux/sched.h> +#include <linux/proc_fs.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/mutex.h> +#include <mach/iram.h> +#include <mach/hardware.h> +#include <mach/clock.h> +#include <mach/mxc_dvfs.h> +#include <mach/sdram_autogating.h> +#include <asm/mach/map.h> +#include <asm/mach-types.h> +#include <asm/cacheflush.h> +#include <asm/tlb.h> + +#define LP_LOW_VOLTAGE 1050000 +#define LP_NORMAL_VOLTAGE 1250000 +#define LP_APM_CLK 24000000 +#define NAND_LP_APM_CLK 12000000 +#define AXI_A_NORMAL_CLK 166250000 +#define AXI_A_CLK_NORMAL_DIV 4 +#define AXI_B_CLK_NORMAL_DIV 5 +#define AHB_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV +#define EMI_SLOW_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV +#define NFC_CLK_NORMAL_DIV 4 +#define SPIN_DELAY 1000000 /* in nanoseconds */ +#define DDR_TYPE_DDR3 0x0 +#define DDR_TYPE_DDR2 0x1 + +DEFINE_SPINLOCK(ddr_freq_lock); + +unsigned long lp_normal_rate; +unsigned long lp_med_rate; +unsigned long ddr_normal_rate; +unsigned long ddr_med_rate; +unsigned long ddr_low_rate; + +struct regulator *pll_regulator; + +struct regulator *lp_regulator; +int low_bus_freq_mode; +int high_bus_freq_mode; +int med_bus_freq_mode; + +int bus_freq_scaling_initialized; +char *lp_reg_id; + +static struct device *busfreq_dev; +static int busfreq_suspended; + +/* True if bus_frequency is scaled not using DVFS-PER */ +int bus_freq_scaling_is_active; + +int cpu_op_nr; +int lp_high_freq; +int lp_med_freq; + +struct workqueue_struct *voltage_wq; +struct completion voltage_change_cmpl; + +int low_freq_bus_used(void); +void set_ddr_freq(int ddr_freq); + +extern struct cpu_op *(*get_cpu_op)(int *op); +extern void __iomem *ccm_base; +extern void __iomem *databahn_base; +extern int update_ddr_freq(int ddr_rate); + + +struct mutex bus_freq_mutex; + +struct timeval start_time; +struct timeval end_time; + +int set_low_bus_freq(void) +{ + return 0; +} + +int set_high_bus_freq(int high_bus_freq) +{ + return 0; +} + +void exit_lpapm_mode_mx6q(int high_bus_freq) +{ + +} + + +void set_ddr_freq(int ddr_rate) +{ + +} + +int low_freq_bus_used(void) +{ + if ((lp_high_freq == 0) + && (lp_med_freq == 0)) + return 1; + else + return 0; +} + +void setup_pll(void) +{ +} + +static ssize_t bus_freq_scaling_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (bus_freq_scaling_is_active) + return sprintf(buf, "Bus frequency scaling is enabled\n"); + else + return sprintf(buf, "Bus frequency scaling is disabled\n"); +} + +static ssize_t bus_freq_scaling_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return size; +} + +static int busfreq_suspend(struct platform_device *pdev, pm_message_t message) +{ + if (low_bus_freq_mode) + set_high_bus_freq(1); + busfreq_suspended = 1; + return 0; +} + +static int busfreq_resume(struct platform_device *pdev) +{ + busfreq_suspended = 0; + return 0; +} + +static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, + bus_freq_scaling_enable_store); + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit busfreq_probe(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "imx_busfreq", + }, + .probe = busfreq_probe, + .suspend = busfreq_suspend, + .resume = busfreq_resume, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ + if (platform_driver_register(&busfreq_driver) != 0) { + printk(KERN_ERR "busfreq_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "Bus freq driver module loaded\n"); + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); + bus_freq_scaling_initialized = 0; +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c new file mode 100644 index 000000000000..ad7b159d097d --- /dev/null +++ b/arch/arm/mach-mvf/clock.c @@ -0,0 +1,3584 @@ +/* + * based on arch/arm/mach-mx6/clock.c + */ + +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/time.h> +#include <linux/hrtimer.h> +#include <linux/mm.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/regulator/consumer.h> +#include <asm/div64.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/clock.h> +#include <mach/mxc_dvfs.h> +#include "crm_regs.h" +#include "cpu_op-mvf.h" +#include "regs-anadig.h" + +#ifdef CONFIG_CLK_DEBUG +#define __INIT_CLK_DEBUG(n) .name = #n, +#else +#define __INIT_CLK_DEBUG(n) +#endif + +extern u32 arm_max_freq; +extern int mxc_jtag_enabled; +extern struct regulator *cpu_regulator; +extern struct cpu_op *(*get_cpu_op)(int *op); +extern int lp_high_freq; +extern int lp_med_freq; +#if 0 +extern int vf6xx_revision(void); +#endif + +void __iomem *apll_base; +static struct clk pll1_sys_main_clk; +static struct clk pll1_pfd1; +static struct clk pll1_pfd2; +static struct clk pll1_pfd3; +static struct clk pll1_pfd4; +static struct clk pll2_528_main_clk; +static struct clk pll2_pfd1; +static struct clk pll2_pfd2; +static struct clk pll2_pfd3; +static struct clk pll2_pfd4; +static struct clk pll3_480_usb1_main_clk; +static struct clk pll3_pfd1; +static struct clk pll3_pfd2; +static struct clk pll3_pfd3; +static struct clk pll3_pfd4; +static struct clk pll4_audio_main_clk; +static struct clk pll5_enet_main_clk; +static struct clk pll6_video_main_clk; +static struct clk pll_480_usb2_main_clk; + +static struct cpu_op *cpu_op_tbl; +#if 0 +static int cpu_op_nr; +#endif + +#define SPIN_DELAY 1200000 /* in nanoseconds */ //FIXME + +#define AUDIO_VIDEO_MIN_CLK_FREQ 650000000 +#define AUDIO_VIDEO_MAX_CLK_FREQ 1300000000 + +/* We need to check the exp status again after timer expiration, + * as there might be interrupt coming between the first time exp + * and the time reading, then the time reading may be several ms + * after the exp checking due to the irq handle, so we need to + * check it to make sure the exp return the right value after + * timer expiration. */ +#define WAIT(exp, timeout) \ +({ \ + struct timespec nstimeofday; \ + struct timespec curtime; \ + int result = 1; \ + getnstimeofday(&nstimeofday); \ + while (!(exp)) { \ + getnstimeofday(&curtime); \ + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \ + if (!(exp)) \ + result = 0; \ + break; \ + } \ + } \ + result; \ +}) + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_high_reference, oscillator_low_reference; +static unsigned long anaclk_1_reference, audio_ext_clk_reference; +static unsigned long enet_ext_clk_reference, enet_ts_clk_reference; +static unsigned long usb_clk_reference; + +/* For MX 6DL/S, Video PLL may be used by synchronous display devices, + * such as HDMI or LVDS, and also by the EPDC. If EPDC is in use, + * it must use the Video PLL to achieve the clock frequencies it needs. + * So if EPDC is in use, the "epdc" string should be added to kernel + * parameters, in order to set the EPDC parent clock to the Video PLL. + * This will have an impact on the behavior of HDMI and LVDS. + */ +int epdc_enabled; +static int __init epdc_setup(char *__unused) +{ + epdc_enabled = 1; + return 1; +} +__setup("epdc", epdc_setup); + +static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post) +{ + //FIXME + u32 min_pre, temp_pre, old_err, err; + + /* Some of the podfs are 3 bits while others are 6 bits. + * Handle both cases here. + */ + if (div >= 512 && (max_podf == 64)) { + /* For pre = 3bits and podf = 6 bits, max divider is 512. */ + *pre = 8; + *post = 64; + } else if (div >= 64 && (max_podf == 8)) { + /* For pre = 3bits and podf = 3 bits, max divider is 64. */ + *pre = 8; + *post = 8; + } else if (div >= 8) { + /* Find the minimum pre-divider for a max podf */ + if (max_podf == 64) + min_pre = (div - 1) / (1 << 6) + 1; + else + min_pre = (div - 1) / (1 << 3) + 1; + old_err = 8; + /* Now loop through to find the max pre-divider. */ + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div < 8) { + *pre = div; + *post = 1; + } +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + return 0; +} + +static int _clk_force_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= MXC_CCM_CCGRx_MOD_FORCE_ON << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return 0; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_sys_main_clk) + return PLL1_SYS_BASE_ADDR; + else if (pll == &pll2_528_main_clk) + return PLL2_528_BASE_ADDR; + else if (pll == &pll3_480_usb1_main_clk) + return PLL3_480_USB1_BASE_ADDR; + else if (pll == &pll4_audio_main_clk) + return PLL4_AUDIO_BASE_ADDR; + else if (pll == &pll5_enet_main_clk) + return PLL5_ENET_BASE_ADDR; + else if (pll == &pll6_video_main_clk) + return PLL6_VIDEO_BASE_ADDR; + else if (pll == &pll_480_usb2_main_clk) + return ANADIG_USB2_PLL_CTRL; + else + BUG(); + return NULL; +} + + +/* + * For the 6-to-1 muxed input clock + */ +static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1, + struct clk *m2, struct clk *m3, struct clk *m4, + struct clk *m5) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else if (parent == m5) + return 5; + else + BUG(); + + return 0; +} + +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_high_reference_clock_rate(struct clk *clk) +{ + return oscillator_high_reference; +} + +static unsigned long get_oscillator_low_reference_clock_rate(struct clk *clk) +{ + return oscillator_low_reference; +} + +static unsigned long _clk_anaclk_1_get_rate(struct clk *clk) +{ + return anaclk_1_reference; +} + +static int _clk_anaclk_1_set_rate(struct clk *clk, unsigned long rate) +{ + anaclk_1_reference = rate; + return 0; +} + +static unsigned long _clk_audio_ext_get_rate(struct clk *clk) +{ + return audio_ext_clk_reference; +} + +static int _clk_audio_ext_set_rate(struct clk *clk, unsigned long rate) +{ + audio_ext_clk_reference = rate; + return 0; +} + +static unsigned long _clk_enet_ext_get_rate(struct clk *clk) +{ + return enet_ext_clk_reference; +} + +static int _clk_enet_ext_set_rate(struct clk *clk, unsigned long rate) +{ + enet_ext_clk_reference = rate; + return 0; +} + +static unsigned long _clk_enet_ts_get_rate(struct clk *clk) +{ + return enet_ts_clk_reference; +} + +static int _clk_enet_ts_set_rate(struct clk *clk, unsigned long rate) +{ + enet_ts_clk_reference = rate; + return 0; +} + +static unsigned long _clk_usb_clk_get_rate(struct clk *clk) +{ + return 60000000; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + __INIT_CLK_DEBUG(ckih_clk) + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk osch_clk = { + __INIT_CLK_DEBUG(osch_clk) + .get_rate = get_oscillator_high_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + __INIT_CLK_DEBUG(ckil_clk) + .get_rate = get_low_reference_clock_rate, +}; + +static struct clk oscl_clk = { + __INIT_CLK_DEBUG(oscl_clk) + .get_rate = get_oscillator_low_reference_clock_rate, +}; + +static struct clk anaclk_1 = { + __INIT_CLK_DEBUG(anaclk_1) + .get_rate = _clk_anaclk_1_get_rate, + .set_rate = _clk_anaclk_1_set_rate, +}; + +static struct clk audio_ext = { + __INIT_CLK_DEBUG(audio_ext) + .get_rate = _clk_audio_ext_get_rate, + .set_rate = _clk_audio_ext_set_rate, +}; + +static struct clk enet_ext = { + __INIT_CLK_DEBUG(enet_ext) + .get_rate = _clk_enet_ext_get_rate, + .set_rate = _clk_enet_ext_set_rate, +}; + +static struct clk enet_ts = { + __INIT_CLK_DEBUG(enet_ts) + .get_rate = _clk_enet_ts_get_rate, + .set_rate = _clk_enet_ts_set_rate, +}; + +static struct clk usb_clk = { + __INIT_CLK_DEBUG(usb_clk) + .get_rate = _clk_usb_clk_get_rate, +}; + +static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + + tmp = (u64)clk_get_rate(clk->parent) * 18; + tmp += rate/2; + do_div(tmp, rate); + frac = tmp; + frac = frac < 12 ? 12 : frac; + frac = frac > 35 ? 35 : frac; + tmp = (u64)clk_get_rate(clk->parent) * 18; + do_div(tmp, frac); + return tmp; +} + +static unsigned long pfd_get_rate(struct clk *clk) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) & + ANADIG_PFD_FRAC_MASK; + + do_div(tmp, frac); + + return tmp; +} + +static int pfd_set_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + /* Round up the divider so that we don't set a rate + * higher than what is requested. */ + tmp += rate/2; + do_div(tmp, rate); + frac = tmp; + frac = frac < 12 ? 12 : frac; + frac = frac > 35 ? 35 : frac; + /* set clk frac bits */ + __raw_writel(frac << clk->enable_shift, + (int)clk->enable_reg); + + return 0; +} + +static int _clk_pfd_enable(struct clk *clk) +{ + u32 reg; + + /* clear clk gate bit */ + reg = __raw_readl((int)clk->enable_reg); + __raw_writel(reg & ~(1 << (clk->enable_shift + ANADIG_PFD_CLKGATE)), + (int)clk->enable_reg); + + /* enable PLLm_PFDn */ + reg = __raw_readl(MXC_CCM_CCSR); + if (clk == &pll1_pfd1) { + reg |= MXC_CCM_CCSR_PLL1_PFD1_EN; + } else if (clk == &pll1_pfd2) { + reg |= MXC_CCM_CCSR_PLL1_PFD2_EN; + } else if (clk == &pll1_pfd3) { + reg |= MXC_CCM_CCSR_PLL1_PFD3_EN; + } else if (clk == &pll1_pfd4) { + reg |= MXC_CCM_CCSR_PLL1_PFD4_EN; + } else if (clk == &pll2_pfd1) { + reg |= MXC_CCM_CCSR_PLL2_PFD1_EN; + } else if (clk == &pll2_pfd2) { + reg |= MXC_CCM_CCSR_PLL2_PFD2_EN; + } else if (clk == &pll2_pfd3) { + reg |= MXC_CCM_CCSR_PLL2_PFD3_EN; + } else if (clk == &pll2_pfd4) { + reg |= MXC_CCM_CCSR_PLL2_PFD4_EN; + } else if (clk == &pll3_pfd1) { + reg |= MXC_CCM_CCSR_PLL3_PFD1_EN; + } else if (clk == &pll3_pfd2) { + reg |= MXC_CCM_CCSR_PLL3_PFD2_EN; + } else if (clk == &pll3_pfd3) { + reg |= MXC_CCM_CCSR_PLL3_PFD3_EN; + } else if (clk == &pll3_pfd4) { + reg |= MXC_CCM_CCSR_PLL3_PFD4_EN; + } else { + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static void _clk_pfd_disable(struct clk *clk) +{ + u32 reg; + + /* disable PLLm_PFDn */ + reg = __raw_readl(MXC_CCM_CCSR); + if (clk == &pll1_pfd1) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD1_EN; + } else if (clk == &pll1_pfd2) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD2_EN; + } else if (clk == &pll1_pfd3) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD3_EN; + } else if (clk == &pll1_pfd4) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD4_EN; + } else if (clk == &pll2_pfd1) { + reg &= ~MXC_CCM_CCSR_PLL2_PFD1_EN; + } else if (clk == &pll2_pfd2) { + reg &= ~MXC_CCM_CCSR_PLL2_PFD2_EN; + } else if (clk == &pll2_pfd3) { + reg &= ~MXC_CCM_CCSR_PLL2_PFD3_EN; + } else if (clk == &pll2_pfd4) { + reg &= ~MXC_CCM_CCSR_PLL2_PFD4_EN; + } else if (clk == &pll3_pfd1) { + reg &= ~MXC_CCM_CCSR_PLL3_PFD1_EN; + } else if (clk == &pll3_pfd2) { + reg &= ~MXC_CCM_CCSR_PLL3_PFD2_EN; + } else if (clk == &pll3_pfd3) { + reg &= ~MXC_CCM_CCSR_PLL3_PFD3_EN; + } else if (clk == &pll3_pfd4) { + reg &= ~MXC_CCM_CCSR_PLL3_PFD4_EN; + } else { + return; + } + __raw_writel(reg, MXC_CCM_CCSR); + + /* set clk gate bit */ + reg = __raw_readl((int)clk->enable_reg); + __raw_writel(reg | (1 << (clk->enable_shift + ANADIG_PFD_CLKGATE)), + (int)clk->enable_reg); +} + +static int _clk_pll_enable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg &= ~ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_POWER_DOWN; + + /* The 480MHz PLLs have the opposite definition for power bit. */ + if (clk == &pll3_480_usb1_main_clk || clk == &pll_480_usb2_main_clk) + reg |= ANADIG_PLL_POWER_DOWN; + + __raw_writel(reg, pllbase); + +#if 0 //FIXME + /* It will power on pll3 */ + if (clk == &pll3_480_usb1_main_clk) + __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_CLR); +#endif + + /* Wait for PLL to lock */ + if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK, + SPIN_DELAY)) + panic("pll enable failed\n"); + + /* Enable the PLL output now*/ + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, pllbase); + + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_ENABLE; + + __raw_writel(reg, pllbase); + +#if 0 //FIXME + /* + * It will power off PLL3's power, it is the TO1.1 fix + * Please see TKT064178 for detail. + */ + if (clk == &pll3_480_usb1_main_clk) + __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET); +#endif +} + +static unsigned long _clk_pll1_main_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + + else + val = clk_get_rate(clk->parent) * 20; + + return val; +} + +static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + switch (rate) { + case 528000000: + div = 1; + break; + case 480000000: + div = 0; + break; + default: + return -EINVAL; + } + + /* Update div */ + reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT; + reg |= div; + __raw_writel(reg, PLL1_SYS_BASE_ADDR); + + // FIXME: need wait? + /* Wait for PLL1 to lock */ + if (!WAIT(__raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_LOCK, + SPIN_DELAY)) + panic("pll1 enable failed\n"); + + return 0; +} + +static struct clk pll1_sys_main_clk = { + __INIT_CLK_DEBUG(pll1_sys_main_clk) + .parent = &osch_clk, + .get_rate = _clk_pll1_main_get_rate, +#if 0 //we do not support to change PLL1 + .set_rate = _clk_pll1_main_set_rate, +#endif + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static struct clk pll1_pfd1 = { + __INIT_CLK_DEBUG(pll1_pfd1_pll) + .id = 0, + .parent = &pll1_sys_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528_SYS, + .enable_shift = ANADIG_PFD1_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, +#if 0 //we do not support to change PLL1 + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, +#endif +}; + +static struct clk pll1_pfd2 = { + __INIT_CLK_DEBUG(pll1_pfd2) + .parent = &pll1_sys_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528_SYS, + .enable_shift = ANADIG_PFD2_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, +#if 0 //we do not support to change PLL1 + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, +#endif +}; + +static struct clk pll1_pfd3 = { + __INIT_CLK_DEBUG(pll1_pfd3) + .parent = &pll1_sys_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528_SYS, + .enable_shift = ANADIG_PFD3_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, +#if 0 //we do not support to change PLL1 + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, +#endif +}; + +static struct clk pll1_pfd4 = { + __INIT_CLK_DEBUG(pll1_pfd4) + .parent = &pll1_sys_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528_SYS, + .enable_shift = ANADIG_PFD4_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, +#if 0 //we do not support to change PLL1 + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, +#endif +}; + +static int _pll1_pfd_out_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + int mux; + + mux = _get_mux6(parent, &pll1_sys_main_clk, &pll1_pfd1, &pll1_pfd2, + &pll1_pfd3, &pll1_pfd4, NULL); + reg |= mux; + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk pll1_pfd_out = { + __INIT_CLK_DEBUG(pll1_pfd_out) + .parent = &pll1_pfd2, +#if 0 //we do not support to change PLL1 + .set_parent = _pll1_pfd_out_set_parent, +#endif +}; + +static unsigned long _clk_pll1_pfd_out_div_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_PLL1_PFD_CLK_DIV_MASK) >> + MXC_CCM_CACRR_PLL1_PFD_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +#if 0 +static int _clk_pll1_pfd_out_div_set_rate(struct clk *clk, unsigned long rate) +{ + int i; + u32 cacrr, div; + u32 parent_rate; + + + for (i = 0; i < cpu_op_nr; i++) { + if (rate == cpu_op_tbl[i].cpu_rate) + break; + } + if (i >= cpu_op_nr) + return -EINVAL; + + if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk) || + cpu_op_tbl[i].cpu_rate != clk_get_rate(&pll1_pfd_out)) { + /* Change the PLL1 rate. */ + pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate); + pll1_pfd_out.set_parent(&pll1_pfd_out, &pll1_pfd2); + pll1_pfd2.set_rate(&pll1_pfd2, cpu_op_tbl[i].cpu_rate); + } + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + + if ((parent_rate / div) > rate) + div++; + + if (div > 4) + return -1; + + cacrr = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_PLL1_PFD_CLK_DIV_MASK; + cacrr |= (div -1) << MXC_CCM_CACRR_PLL1_PFD_CLK_DIV_OFFSET; + __raw_writel(cacrr, MXC_CCM_CACRR); + + return 0; +} +#endif + +static struct clk pll1_pfd_out_div = { + __INIT_CLK_DEBUG(pll1_pfd_out_div) + .parent = &pll1_pfd_out, + .get_rate = _clk_pll1_pfd_out_div_get_rate, +#if 0 //we do not support to change PLL1 + .set_rate = _clk_pll1_pfd_out_div_set_rate, +#endif +}; + +static unsigned long _clk_pll2_main_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + + else + val = clk_get_rate(clk->parent) * 20; + + return val; +} + +static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL2_528_BASE_ADDR); + reg &= ~ANADIG_PLL_528_DIV_SELECT; + reg |= div; + __raw_writel(reg, PLL2_528_BASE_ADDR); + + return 0; +} + +static struct clk pll2_528_main_clk = { + __INIT_CLK_DEBUG(pll2_528_main_clk) + .parent = &osch_clk, + .get_rate = _clk_pll2_main_get_rate, + .set_rate = _clk_pll2_main_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static struct clk pll2_pfd1 = { + __INIT_CLK_DEBUG(pll2_pfd1) + .parent = &pll2_528_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528, + .enable_shift = ANADIG_PFD1_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd2 = { + __INIT_CLK_DEBUG(pll2_pfd2) + .parent = &pll2_528_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528, + .enable_shift = ANADIG_PFD2_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd3 = { + __INIT_CLK_DEBUG(pll2_pfd3) + .parent = &pll2_528_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528, + .enable_shift = ANADIG_PFD3_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd4 = { + __INIT_CLK_DEBUG(pll2_pfd4) + .parent = &pll2_528_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_528, + .enable_shift = ANADIG_PFD4_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static int _pll2_pfd_out_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_MASK; + + if (parent == &pll2_528_main_clk) { + reg |= 0x0; + } else if (parent == &pll2_pfd1) { + reg |= 0x1; + } else if (parent == &pll2_pfd2) { + reg |= 0x2; + } else if (parent == &pll2_pfd3) { + reg |= 0x3; + } else if (parent == &pll2_pfd4) { + reg |= 0x4; + } else { + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk pll2_pfd_out = { + __INIT_CLK_DEBUG(pll2_pfd_out) + .parent = &pll2_pfd1, + .set_parent = _pll2_pfd_out_set_parent, +}; + +static unsigned long _clk_pll3_480_usb1_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL3_480_USB1_BASE_ADDR) + & ANADIG_PLL_480_DIV_SELECT_MASK; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + else + val = clk_get_rate(clk->parent) * 20; + return val; +} + +static int _clk_pll3_480_usb1_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL3_480_USB1_BASE_ADDR); + reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK; + reg |= div; + __raw_writel(reg, PLL3_480_USB1_BASE_ADDR); + + return 0; +} + + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_480_usb1_main_clk = { + __INIT_CLK_DEBUG(pll3_480_usb1_main_clk) + .parent = &osch_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll3_480_usb1_set_rate, + .get_rate = _clk_pll3_480_usb1_get_rate, +}; + +static unsigned long _clk_pll3_div_get_rate(struct clk *clk) +{ + unsigned int div; + + div = (__raw_readl(MXC_CCM_CACRR) &~MXC_CCM_CACRR_PLL3_CLK_DIV) >> + MXC_CCM_CACRR_PLL3_CLK_DIV_OFFSET; + div += 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_pll3_div_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + if (((parent_rate / div) != rate) || div > 2) + return -1; + + reg = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_PLL3_CLK_DIV; + reg |= div << MXC_CCM_CACRR_PLL3_CLK_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + + return 0; +} + +static struct clk pll3_div_clk = { + __INIT_CLK_DEBUG(pll3_div_clk) + .parent = &pll3_480_usb1_main_clk, + .set_rate = _clk_pll3_div_set_rate, + .get_rate = _clk_pll3_div_get_rate, +}; + +static struct clk pll3_pfd1 = { + __INIT_CLK_DEBUG(pll3_pfd1) + .parent = &pll3_480_usb1_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_480_USB1, + .enable_shift = ANADIG_PFD1_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd2 = { + __INIT_CLK_DEBUG(pll3_pfd2) + .parent = &pll3_480_usb1_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_480_USB1, + .enable_shift = ANADIG_PFD2_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd3 = { + __INIT_CLK_DEBUG(pll3_pfd3) + .parent = &pll3_480_usb1_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_480_USB1, + .enable_shift = ANADIG_PFD3_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd4 = { + __INIT_CLK_DEBUG(pll3_pfd4) + .parent = &pll3_480_usb1_main_clk, + .enable_reg = (void *)ANADIG_PLL_PFD_480_USB1, + .enable_shift = ANADIG_PFD4_FRAC_SHIFT, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static unsigned long _clk_audio_video_get_rate(struct clk *clk) +{ + //FIXME: need TEST_DIV_SEL support? + unsigned int div, mfn, mfd; + unsigned long rate; + unsigned int parent_rate = clk_get_rate(clk->parent); + void __iomem *pllbase; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL6_VIDEO_BASE_ADDR; + + div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT; + mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET); + mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET); + + rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); + + return rate; +} + +static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate) +{ + //FIXME: need TEST_DIV_SEL support? + unsigned int reg, div; + unsigned int mfn, mfd = 1000000; + s64 temp64; + unsigned int parent_rate = clk_get_rate(clk->parent); + void __iomem *pllbase; + unsigned long pre_div_rate; + + if ((rate < AUDIO_VIDEO_MIN_CLK_FREQ) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ)) + return -EINVAL; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL6_VIDEO_BASE_ADDR; + + pre_div_rate = rate; + div = pre_div_rate / parent_rate; + temp64 = (u64) (pre_div_rate - (div * parent_rate)); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + reg = __raw_readl(pllbase) + & ~ANADIG_PLL_SYS_DIV_SELECT; + reg |= div; + __raw_writel(reg, pllbase); + __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET); + __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET); + + return 0; +} + +static unsigned long _clk_audio_video_round_rate(struct clk *clk, + unsigned long rate) +{ + //FIXME: need TEST_DIV_SEL support? + unsigned int div, post_div = 1; + unsigned int mfn, mfd = 1000000; + s64 temp64; + unsigned int parent_rate = clk_get_rate(clk->parent); + unsigned long pre_div_rate; + u32 test_div_sel = 2; + u32 control3 = 0; + unsigned long final_rate; + + if (rate < AUDIO_VIDEO_MIN_CLK_FREQ) + return AUDIO_VIDEO_MIN_CLK_FREQ; + + if (rate > AUDIO_VIDEO_MAX_CLK_FREQ) + return AUDIO_VIDEO_MAX_CLK_FREQ; + + pre_div_rate = rate; + div = pre_div_rate / parent_rate; + temp64 = (u64) (pre_div_rate - (div * parent_rate)); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); + + return final_rate; +} + +static int _clk_audio_video_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + void __iomem *pllbase; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL6_VIDEO_BASE_ADDR; + + reg = __raw_readl(pllbase) & ~ANADIG_PLL_BYPASS_CLK_SRC; + mux = _get_mux(parent, &osch_clk, &anaclk_1, NULL, NULL); + reg |= mux << ANADIG_PLL_BYPASS_CLK_SRC; + __raw_writel(reg, pllbase); + + /* Set anaclk_x as input */ + if (parent == &anaclk_1) { + reg = __raw_readl(ANADIG_ANA_MISC1); + reg |= (ANADIG_ANA_MISC1_LVDSCLK1_IBEN & + ~ANADIG_ANA_MISC1_LVDSCLK1_OBEN); + __raw_writel(reg, ANADIG_ANA_MISC1); + } + + return 0; +} + +static struct clk pll4_audio_main_clk = { + __INIT_CLK_DEBUG(pll4_audio_main_clk) + .parent = &osch_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_audio_video_set_rate, + .get_rate = _clk_audio_video_get_rate, + .round_rate = _clk_audio_video_round_rate, + .set_parent = _clk_audio_video_set_parent, +}; + +static struct clk pll6_video_main_clk = { + __INIT_CLK_DEBUG(pll6_video_main_clk) + .parent = &osch_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_audio_video_set_rate, + .get_rate = _clk_audio_video_get_rate, + .round_rate = _clk_audio_video_round_rate, + .set_parent = _clk_audio_video_set_parent, +}; + +static unsigned long _clk_pll6_div_get_rate(struct clk *clk) +{ + unsigned int div; + u32 reg; + + div = (__raw_readl(MXC_CCM_CACRR) &~MXC_CCM_CACRR_PLL6_CLK_DIV) >> + MXC_CCM_CACRR_PLL6_CLK_DIV_OFFSET; + div += 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_pll6_div_set_rate(struct clk *clk) +{ + u32 reg, div; + u32 parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div == 1; + if (((parent_rate / div) != rate) || div > 2) + return -1; + + reg = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_PLL6_CLK_DIV; + reg |= div << MXC_CCM_CACRR_PLL6_CLK_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + + return 0; +} + +static struct clk pll6_div_clk = { + __INIT_CLK_DEBUG(pll6_div_clk) + .parent = &pll6_video_main_clk, + .set_rate = _clk_pll6_div_set_rate, + .get_rate = _clk_pll6_div_get_rate, +}; + +static unsigned long _clk_pll_480_usb2_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(ANADIG_USB2_PLL_CTRL) + & ANADIG_PLL_480_DIV_SELECT_MASK; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + else + val = clk_get_rate(clk->parent) * 20; + return val; +} + +static int _clk_pll_480_usb2_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(ANADIG_USB2_PLL_CTRL); + reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK; + reg |= div; + __raw_writel(reg, ANADIG_USB2_PLL_CTRL); + + return 0; +} + +static struct clk pll_480_usb2_main_clk = { + __INIT_CLK_DEBUG(pll_480_usb2_main_clk) + .parent = &osch_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll_480_usb2_set_rate, + .get_rate = _clk_pll_480_usb2_get_rate, + +}; + +static struct clk pll5_enet_main_clk = { + __INIT_CLK_DEBUG(pll5_enet_main_clk) + .parent = &osch_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static int _clk_enet_enable(struct clk *clk) +{ + unsigned int reg; + + /* Enable ENET ref clock */ + reg = __raw_readl(PLL5_ENET_BASE_ADDR); + reg &= ~ANADIG_PLL_BYPASS; + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL5_ENET_BASE_ADDR); + + _clk_enable(clk); + return 0; +} + +static void _clk_enet_disable(struct clk *clk) +{ + unsigned int reg; + + _clk_disable(clk); + + /* Enable ENET ref clock */ + reg = __raw_readl(PLL5_ENET_BASE_ADDR); + reg |= ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL5_ENET_BASE_ADDR); +} + +static int _clk_enet_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div = 1; + + switch (rate) { + case 25000000: + div = 0; + break; + case 50000000: + div = 1; + break; + case 100000000: + div = 2; + break; + case 125000000: + div = 3; + break; + default: + return -EINVAL; + } + reg = __raw_readl(PLL5_ENET_BASE_ADDR); + reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK; + reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET); + __raw_writel(reg, PLL5_ENET_BASE_ADDR); + + return 0; +} + +static unsigned long _clk_enet_get_rate(struct clk *clk) +{ + unsigned int div; + + div = (__raw_readl(PLL5_ENET_BASE_ADDR)) + & ANADIG_PLL_ENET_DIV_SELECT_MASK; + + switch (div) { + case 0: + div = 20; + break; + case 1: + div = 10; + break; + case 2: + div = 5; + break; + case 3: + div = 4; + break; + } + + return 500000000 / div; +} + +static struct clk enet_clk = { + __INIT_CLK_DEBUG(enet_clk) + .id = 0, + .parent = &pll5_enet_main_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enet_enable, + .disable = _clk_enet_disable, +#if 0 //we do not support enet freq + .set_rate = _clk_enet_set_rate, +#endif + .get_rate = _clk_enet_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +unsigned long _clk_enet_div2_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static struct clk enet_div2_clk = { + __INIT_CLK_DEBUG(enet_div2_clk) + .parent = &enet_clk, + .get_rate = _clk_enet_div2_get_rate, +}; + +static unsigned long _clk_sys_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_ARM_CLK_DIV_MASK) >> + MXC_CCM_CACRR_ARM_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +#if 0 +static int _clk_sys_set_rate(struct clk *clk, unsigned long rate) +{ + int i; + u32 cacrr, div; + u32 parent_rate; + + + for (i = 0; i < cpu_op_nr; i++) { + if (rate == cpu_op_tbl[i].cpu_rate) + break; + } + if (i >= cpu_op_nr) + return -EINVAL; + + if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk) || + cpu_op_tbl[i].cpu_rate != clk_get_rate(&pll1_pfd_out)) { + /* Change the PLL1 rate. */ + pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate); + pll1_pfd_out.set_parent(&pll1_pfd_out, &pll1_pfd2); + pll1_pfd2.set_rate(&pll1_pfd2, cpu_op_tbl[i].cpu_rate); + } + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + + if ((parent_rate / div) > rate) + div++; + + if (div > 8) + return -1; + + cacrr = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_ARM_CLK_DIV_MASK; + cacrr |= (div -1) << MXC_CCM_CACRR_ARM_CLK_DIV_OFFSET; + __raw_writel(cacrr, MXC_CCM_CACRR); + + return 0; +} + +static int _clk_sys_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux6(parent, &osch_clk, &oscl_clk, &pll2_pfd_out, + &pll2_528_main_clk, &pll1_pfd_out, &pll3_480_usb1_main_clk); + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_SYS_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CCSR_SYS_CLK_SE_OFFSET; + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} +#endif + +static struct clk sys_clk = { + __INIT_CLK_DEBUG(sys_clk) + .parent = &pll1_pfd_out, +#if 0 /* we do not support to change sys_clk */ + .set_rate = _clk_sys_set_rate, +#endif + .get_rate = _clk_sys_get_rate, +#if 0 /* we do not support to change sys_clk */ + .set_parent = _clk_sys_set_parent, +#endif +}; + +static int _clk_ca5_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux(parent, &sys_clk, &pll1_pfd_out_div, NULL, NULL); + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_CA5_CLK_SEL; + reg |= mux << MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk cpu_clk = { + __INIT_CLK_DEBUG(cpu_clk) + .parent = &sys_clk, + //FIXME: need enable/disable CA5-XXX on AIPS? +#if 0 //we do not support to change ca5_clk + .set_parent = _clk_ca5_set_parent, +#endif +}; + +static int _clk_ddrc_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux(parent, &pll2_pfd2, &sys_clk, NULL, NULL); + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_DDRC_CLK_SEL; + reg |= mux << MXC_CCM_CCSR_DDRC_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk ddrc_clk = { + __INIT_CLK_DEBUG(ddrc_clk) + .parent = &pll2_pfd2, +#if 0 //we do not support to change dram_clk + .set_parent = _clk_ddrc_set_parent, +#endif +}; + +static unsigned long _clk_plat_bus_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_BUS_CLK_DIV_MASK) >> + MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_plat_bus_set_rate(struct clk *clk, unsigned long rate) +{ + u32 cacrr, div; + u32 parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + if (((parent_rate / div) != rate) || div > 8) + return -1; + + cacrr = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_BUS_CLK_DIV_MASK; + cacrr |= (div -1) << MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET; + __raw_writel(cacrr, MXC_CCM_CACRR); + + return 0; +} + +static struct clk plat_bus_clk = { + __INIT_CLK_DEBUG(plat_bus_clk) + .parent = &sys_clk, + .get_rate = _clk_plat_bus_get_rate, +#if 0 //we do not support to change plat_bus_clk + .set_rate = _clk_plat_bus_set_rate, +#endif +}; + +static struct clk cm4_clk = { + __INIT_CLK_DEBUG(cm4_clk) + .parent = &plat_bus_clk, +}; + +static unsigned long _clk_flex_bus_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_FLEX_CLK_DIV_MASK) >> + MXC_CCM_CACRR_FLEX_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_flex_bus_set_rate(struct clk *clk, unsigned long rate) +{ + u32 cacrr, div; + u32 parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + if (((parent_rate / div) != rate) || div > 8) + return -EINVAL; + + cacrr = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_FLEX_CLK_DIV_MASK; + cacrr |= (div -1) << MXC_CCM_CACRR_FLEX_CLK_DIV_OFFSET; + __raw_writel(cacrr, MXC_CCM_CACRR); + + return 0; +} + +static struct clk flex_bus_clk = { + __INIT_CLK_DEBUG(flex_bus_clk) + .parent = &plat_bus_clk, + .get_rate = _clk_flex_bus_get_rate, + .set_rate = _clk_flex_bus_set_rate, +}; + +static unsigned long _clk_ips_bus_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_IPG_CLK_DIV_MASK) >> + MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ips_bus_set_rate(struct clk *clk, unsigned long rate) +{ + u32 cacrr, div; + u32 parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + if (((parent_rate / div) != rate) || div > 4) + return -EINVAL; + + cacrr = __raw_readl(MXC_CCM_CACRR) & ~MXC_CCM_CACRR_IPG_CLK_DIV_MASK; + cacrr |= (div -1) << MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET; + __raw_writel(cacrr, MXC_CCM_CACRR); + + return 0; +} + +static struct clk ips_bus_clk = { + __INIT_CLK_DEBUG(ips_bus_clk) + .parent = &plat_bus_clk, + .get_rate = _clk_ips_bus_get_rate, +#if 0 //we do not support to change ips_bus_clk + .set_rate = _clk_ips_bus_set_rate, +#endif +}; + +static struct clk gpc_core_clk = { + __INIT_CLK_DEBUG(gpc_core_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static unsigned long _clk_snvs_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR4); + div = ((reg & MXC_CCM_CSCDR4_SNVS_CLK_DIV_MASK) >> + MXC_CCM_CSCDR4_SNVS_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_snvs_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (div == 0) + div = 1; + if (((parent_rate / div) != rate) || div > 4) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR4) & ~MXC_CCM_CSCDR4_SNVS_CLK_DIV_MASK; + reg |= (div -1) << MXC_CCM_CSCDR4_SNVS_CLK_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + + return 0; +} + +static struct clk snvs_clk = { + __INIT_CLK_DEBUG(snvs_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .get_rate = _clk_snvs_get_rate, + .set_rate = _clk_snvs_set_rate, +}; + +static struct clk wdog_snvs_clk = { + __INIT_CLK_DEBUG(wdog_snvs_clk) + //FIXME: which is parent? + .parent = &ips_bus_clk, + //.parent = &snvs_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_can0_root_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR2) | MXC_CCM_CSCDR2_CAN0_EN; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static void _clk_can0_root_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR2) & ~MXC_CCM_CSCDR2_CAN0_EN; + __raw_writel(reg, MXC_CCM_CSCDR2); +} + +static int _clk_can0_root_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux(parent, &osch_clk, &ips_bus_clk, NULL, NULL); + reg = __raw_readl(CAN0_CTRL1) & ~CAN_CTRL_CLKSRC; + reg |= mux << CAN_CTRL_CLKSRC_OFFSET; + __raw_writel(reg, CAN0_CTRL1); + + return 0; +} + +static struct clk can0_clk_root = { + __INIT_CLK_DEBUG(can0_clk_root) + .id = 0, + .parent = &ips_bus_clk, + .enable = _clk_can0_root_enable, + .disable = _clk_can0_root_disable, + .set_parent = _clk_can0_root_set_parent, +}; + +static struct clk can0_clk[] = { + { + __INIT_CLK_DEBUG(can0_clk_0) + .id = 0, + .parent = &can0_clk_root, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &can0_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, //FIXME + }, + { + __INIT_CLK_DEBUG(can0_clk_1) + .id = 1, + .parent = &can0_clk_root, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &can0_clk[2], + }, + { + __INIT_CLK_DEBUG(can0_clk_2) + .id = 2, + .parent = &can0_clk_root, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &can0_clk[3], + }, + { + __INIT_CLK_DEBUG(can0_clk_3) + .id = 4, + .parent = &can0_clk_root, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static int _clk_can1_root_enable(struct clk *clk) +{ + u32 req; + + reg = __raw_readl(MXC_CCM_CSCDR2) | MXC_CCM_CSCDR2_CAN1_EN; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static void _clk_can1_root_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR2) & ~MXC_CCM_CSCDR2_CAN1_EN; + __raw_writel(reg, MXC_CCM_CSCDR2); +} + +static int _clk_can1_root_set_parent(struct clk *clk, struct clk *parent) +{ + + u32 reg; + int mux; + + mux = _get_mux(parent, &osch_clk, &ips_bus_clk, NULL, NULL); + reg = __raw_readl(CAN1_CTRL1) & ~CAN_CTRL_CLKSRC; + reg |= mux << CAN_CTRL_CLKSRC_OFFSET; + __raw_writel(reg, CAN1_CTRL1); + + return 0; +} + +static struct clk can1_root_clk = { + __INIT_CLK_DEBUG(can1_root_clk) + .parent = &ips_bus_clk, + .enable = _clk_can1_root_enable, + .disable = _clk_can1_root_disable, + .set_parent = _clk_can1_root_set_parent, +}; + +static struct clk can1_clk[] = { + { + __INIT_CLK_DEBUG(can1_clk_0) + .id = 0, + .parent = &can1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &can1_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, //FIXME + }, + { + __INIT_CLK_DEBUG(can1_clk_1) + .id = 1, + .parent = &can1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &can1_clk[2], + }, + { + __INIT_CLK_DEBUG(can1_clk_2) + .id = 2, + .parent = &can1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &can1_clk[3], + }, + { + __INIT_CLK_DEBUG(can1_clk_3) + .id = 3, + .parent = &can1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk ftm0_ext_clk; +static struct clk ftm1_ext_clk; +static struct clk ftm2_ext_clk; +static struct clk ftm3_ext_clk; +static struct clk ftm0_fix_clk; +static struct clk ftm1_fix_clk; +static struct clk ftm2_fix_clk; +static struct clk ftm3_fix_clk; + +static int _clk_ftm_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) | (1 << clk->enable_shif); + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static void _clk_ftm_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) & ~(1 << clk->enable_shif); + __raw_writel(reg, MXC_CCM_CSCDR1); +} + +static unsigned long _clk_ftm_ext_get_rate(struct clk *clk) +{ + if (clk->parent == &osch_clk) + return clk_get_rate(clk->parent) / 2; + else + return clk_get_rate(clk->parent); +} + +static int _clk_ftm_ext_set_parent(struct clk *clk, struct clk *parent) +{ + u8 shift; + u32 reg; + int mux; + + if (clk == &ftm0_ext_clk) + shift = MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_OFFSET; + else if (clk == &ftm1_ext_clk) + shift = MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_OFFSET; + else if (clk == &ftm2_ext_clk) + shift = MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_OFFSET; + else if (clk == &ftm3_ext_clk) + shift = MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_OFFSET; + else + return -EINVAL; + + mux = _get_mux(parent, &ckil_clk, &oscl_clk, &osch_clk, &audio_ext_clk); + reg = __raw_readl(MXC_CCM_CSCMR2) & ~(0x3 << shift); + reg |= mux << shift; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static int _clk_ftm_fix_set_parent(struct clk *clk, struct clk *parent) +{ + u8 shift; + u32 reg; + int mux; + + if (clk == &ftm0_fix_clk) + shift = MXC_CCM_CSCMR2_FTM0_FIX_CLK_SEL_OFFSET; + else if (clk == &ftm1_fix_clk) + shift = MXC_CCM_CSCMR2_FTM1_FIX_CLK_SEL_OFFSET; + else if (clk == &ftm2_fix_clk) + shift = MXC_CCM_CSCMR2_FTM2_FIX_CLK_SEL_OFFSET; + else if (clk == &ftm3_fix_clk) + shift = MXC_CCM_CSCMR2_FTM3_FIX_CLK_SEL_OFFSET; + else + return -EINVAL; + + if (parent == &oscl_clk) + mux = 0; + else if (parent == &ckil_clk) + mux = 1; + else + return -EINVAL + + reg = __raw_readl(MXC_CCM_CSCMR2) & ~(1 << shift); + reg |= mux << shift; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static struct clk ftm0_ext_clk = { + __INIT_CLK_DEBUG(ftm0_ext_clk) + .parent = &ckil_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .get_rate = _clk_ftm_ext_get_rate, + .set_parent = _clk_ftm_ext_set_parent, +}; + +static struct clk ftm1_ext_clk = { + __INIT_CLK_DEBUG(ftm1_ext_clk) + .parent = &ckil_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .get_rate = _clk_ftm_ext_get_rate, + .set_parent = _clk_ftm_ext_set_parent, +}; + +static struct clk ftm2_ext_clk = { + __INIT_CLK_DEBUG(ftm2_ext_clk) + .parent = &ckil_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .get_rate = _clk_ftm_ext_get_rate, + .set_parent = _clk_ftm_ext_set_parent, +}; + +static struct clk ftm3_ext_clk = { + __INIT_CLK_DEBUG(ftm3_ext_clk) + .parent = &ckil_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .get_rate = _clk_ftm_ext_get_rate, + .set_parent = _clk_ftm_ext_set_parent, +}; + +static struct clk ftm0_fix_clk = { + __INIT_CLK_DEBUG(ftm0_fix_clk) + .parent = &oscl_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .set_parent = _clk_ftm0_fix_set_parent, +}; + +static struct clk ftm1_fix_clk = { + __INIT_CLK_DEBUG(ftm1_fix_clk) + .parent = &oscl_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .set_parent = _clk_ftm1_fix_set_parent, +}; + +static struct clk ftm2_fix_clk = { + __INIT_CLK_DEBUG(ftm2_fix_clk) + .parent = &oscl_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .set_parent = _clk_ftm2_fix_set_parent, +}; + +static struct clk ftm3_fix_clk = { + __INIT_CLK_DEBUG(ftm3_fix_clk) + .parent = &oscl_clk, + .enable_shift = MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET; + .enable = _clk_ftm_enable, + .disable = _clk_ftm_disable, + .set_parent = _clk_ftm3_fix_set_parent, +}; + +static int _clk_ftm0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + if (parent == NULL) + mux = 0x0; + else if (parent == &sys_clk) + mux = 0x1; + else if (parent == &ftm0_fix_clk) + mux = 0x2; + else if (parent == &ftm0_ext_clk) + mux = 0x3; + else + return -EINVAL; + + reg = __raw_readl(FTM0_SC) & ~FTM_SC_CLKS_MASK; + reg |= mux << FTM_SC_CLKS_OFFSET; + __raw_writel(reg, FTM0_SC); + + return 0; +} + +static struct clk ftm0_clk = { + __INIT_CLK_DEBUG(ftm0_clk), + .parent = &ftm0_fix_clk, //FIXME + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ftm0_set_parent, +}; + +static int _clk_ftm1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + if (parent == NULL) + mux = 0x0; + else if (parent == &sys_clk) + mux = 0x1; + else if (parent == &ftm1_fix_clk) + mux = 0x2; + else if (parent == &ftm1_ext_clk) + mux = 0x3; + else + return -EINVAL; + + reg = __raw_readl(FTM1_SC) & ~FTM_SC_CLKS_MASK; + reg |= mux << FTM_SC_CLKS_OFFSET; + __raw_writel(reg, FTM1_SC); + + return 0; +} + +static struct clk ftm1_clk = { + __INIT_CLK_DEBUG(ftm1_clk), + .parent = &ftm1_fix_clk, //FIXME + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ftm1_set_parent, +}; + +static int _clk_ftm2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + if (parent == NULL) + mux = 0x0; + else if (parent == &sys_clk) + mux = 0x1; + else if (parent == &ftm2_fix_clk) + mux = 0x2; + else if (parent == &ftm2_ext_clk) + mux = 0x3; + else + return -EINVAL; + + reg = __raw_readl(FTM2_SC) & ~FTM_SC_CLKS_MASK; + reg |= mux << FTM_SC_CLKS_OFFSET; + __raw_writel(reg, FTM2_SC); + + return 0; +} + +static struct clk ftm2_clk = { + __INIT_CLK_DEBUG(ftm2_clk), + .parent = &ftm2_fix_clk, //FIXME + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ftm2_set_parent, +}; + +static int _clk_ftm3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + if (parent == NULL) + mux = 0x0; + else if (parent == &sys_clk) + mux = 0x1; + else if (parent == &ftm3_fix_clk) + mux = 0x2; + else if (parent == &ftm3_ext_clk) + mux = 0x3; + else + return -EINVAL; + + reg = __raw_readl(FTM3_SC) & ~FTM_SC_CLKS_MASK; + reg |= mux << FTM_SC_CLKS_OFFSET; + __raw_writel(reg, FTM3_SC); + + return 0; +} + +static struct clk ftm3_clk = { + __INIT_CLK_DEBUG(ftm3_clk), + .parent = &ftm3_fix_clk, //FIXME + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ftm3_set_parent, +}; + +static int _clk_enet_rmii_enable(truct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) | MXC_CCM_CSCDR1_RMII_CLK_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static void _clk_enet_rmii_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_RMII_CLK_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); +} + +static int _clk_enet_rmii_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_RMII_CLK_SEL_MASK; + mux = _get_mux(parent, &enet_ext, &audio_ext, &enet_clk, &enet_div2_clk); + reg |= mux << MXC_CCM_CSCMR2_RMII_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static struct clk enet_rmii_clk = { + __INIT_CLK_DEBUG(enet_rmii_clk), + .parent = &enet_ext, + .enable = _clk_enet_rmii_enable, + .disable = _clk_enet_rmii_disable, +#if 0 //we do not support to change enet freq + .set_parent = _clk_enet_rmii_set_parent, +#endif +}; + +static int _clk_enet_ts_enable(truct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) | MXC_CCM_CSCDR1_TS_CLK_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static void _clk_enet_ts_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_TS_CLK_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); +} + +static int _clk_enet_ts_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + if (parent == &enet_ext) + mux = 0x0; + else if (parent == &osch_clk) + mux = 0x1; + else if (parent == &audio_ext) + mux = 0x2; + else if (parent == &usb_clk) + mux = 0x3; + else if (parent == &enet_ts) + mux = 0x4; + else if (parent == &enet_div2_clk) + mux = 0x5; + else if (parent == &enet_clk) + mux = 0x6; + else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static struct clk enet_ts_clk = { + __INIT_CLK_DEBUG(enet_ts_clk), + .parent = &enet_ext, + .enable = _clk_enet_ts_enable, + .disable = _clk_enet_ts_disable, +#if 0 //we do not support to change enet freq + .set_parent = _clk_enet_ts_set_parent, +#endif +}; + +static struct clk dcu0_clk_root; +static struct clk dcu1_clk_root; + +static int _clk_dcu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static int _clk_dcu_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, MXC_CCM_CSCDR3); +} + +static unsigned long _clk_dcu_get_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR3); + if (clk == &dcu0_clk_root) + div = ((reg & ~MXC_CCM_CSCDR3_DCU0_DIV_MASK) >> + MXC_CCM_CSCDR3_DCU0_DIV_OFFSET) + 1; + else if (clk == &dcu1_clk_root) + div = ((reg & ~MXC_CCM_CSCDR3_DCU1_DIV_MASK) >> + MXC_CCM_CSCDR3_DCU1_DIV_OFFSET) + 1; + else + return -EINVAL; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_dcu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR3); + if (clk == &dcu0_clk_root) { + reg &= ~MXC_CCM_CSCDR3_DCU0_DIV_MASK; + reg |= (div -1) << MXC_CCM_CSCDR3_DCU0_DIV_OFFSET; + } else if (clk == &dcu1_clk_root) { + reg &= ~MXC_CCM_CSCDR3_DCU1_DIV_MASK; + reg |= (div -1) << MXC_CCM_CSCDR3_DCU1_DIV_OFFSET; + } else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static int _clk_dcu_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux(parent, &pll1_pfd2, &pll3_480_usb1_main_clk, NULL, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1); + if (clk == &dcu0_clk_root) { + reg &= ~MXC_CCM_CSCMR1_DCU0_CLK_SEL; + reg |= mux << MXC_CCM_CSCMR1_DCU0_CLK_SEL_OFFSET; + } else if (clk == &dcu1_clk_root) { + reg &= ~MXC_CCM_CSCMR1_DCU1_CLK_SEL; + reg |= mux << MXC_CCM_CSCMR1_DCU1_CLK_SEL_OFFSET; + } else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk dcu0_clk_root = { + __INIT_CLK_DEBUG(dcu0_clk_root), + .parent = &pll1_pfd2, //FIXME + .enable_shift = MXC_CCM_CSCDR3_DCU0_EN_OFFSET, + .enable = _clk_dcu_enable, + .disable = _clk_dcu_disable, + .set_rate = _clk_dcu_set_rate, + .get_rate = _clk_dcu_get_rate, + .set_parent = _clk_dcu_set_parent, +}; + +static struct dcu0_clk[] = { + { + __INIT_CLK_DEBUG(dcu0_clk_0), + .id = 0, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[1], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_1), + .id = 1, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[2], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_2), + .id = 2, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[3], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_3), + .id = 3, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[4], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_4), + .id = 4, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[5], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_5), + .id = 5, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[6], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_6), + .id = 6, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu0_clk[7], + }, + { + __INIT_CLK_DEBUG(dcu0_clk_7), + .id = 7, + .parent = &dcu0_clk_root, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +} + +static struct clk dcu1_clk_root = { + __INIT_CLK_DEBUG(dcu1_clk_root), + .parent = &pll1_pfd2, //FIXME + .enable_shift = MXC_CCM_CSCDR3_DCU1_EN_OFFSET, + .enable = _clk_dcu_enable, + .disable = _clk_dcu_disable, + .set_rate = _clk_dcu_set_rate, + .get_rate = _clk_dcu_get_rate, + .set_parent = _clk_dcu_set_parent, +}; + +static struct clk dcu1_clk[] = { + { + __INIT_CLK_DEBUG(dcu1_clk_0), + .id = 0, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[1], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_1), + .id = 1, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[2], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_2), + .id = 2, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[3], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_3), + .id = 3, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[4], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_4), + .id = 4, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[5], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_5), + .id = 5, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[6], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_6), + .id = 6, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &dcu1_clk[7], + }, + { + __INIT_CLK_DEBUG(dcu1_clk_7), + .id = 7, + .parent = &dcu1_clk_root, + .enable_reg = MXC_CCM_CCGR9, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static int _clk_video_adc_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1) | MXC_CCM_CSCDR1_VADC_EN; + _raw_writel(reg, MXC_CCM_CSCDR1); + + _clk_enable(clk); + return 0; +} + +static void _clk_video_adc__disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + + reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_VADC_EN; + _raw_writel(reg, MXC_CCM_CSCDR1); +} + +static unsigned long _clk_video_adc_get_rate(struct clk *clk) +{ + unsigned int div; + + div = (__raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_VADC_DIV_MASK) >> + MXC_CCM_CSCDR1_VADC_DIV_OFFSET; + + return clk_get_rate(clk->parent) / (div + 1); +} + +tatic int _clk_video_adc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 4)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_VADC_DIV_MASK; + reg |= div << MXC_CCM_CSCDR1_VADC_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static int _clk_video_adc_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg; + + mux = _get_mux(parent, &pll6_div_clk, &pll3_div_clk, + &pll3_480_usb1_main_clk, NULL); + + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_VADC_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_VADC_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk video_adc_clk = { + __INIT_CLK_DEBUG(video_adc_clk), + .parent = &pll6_div_clk, //FIXME + .enable_reg = MXC_CCM_CCGR8, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_video_adc_enable, + .disable = _clk_video_adc_disable, + .get_rate = _clk_video_adc_get_rate, + .set_rate = _clk_video_adc_set_rate, + .set_parent = _clk_video_adc_set_parent, +}; + +static unsigned long _clk_video_adc_div2_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static struct clk video_adc_div2_clk = { + __INIT_CLK_DEBUG(video_adc_div2_clk), + .parent = &video_adc_clk, + .get_rate = _clk_video_adc_div2_get_rate, +}; + +static int _clk_gpu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR2) | MXC_CCM_CSCDR2_GPU_EN; + _raw_writel(reg, MXC_CCM_CSCDR2); + + _clk_enable(clk); + return 0; +} + +static void _clk_gpu_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + + reg = __raw_readl(MXC_CCM_CSCDR2) & ~MXC_CCM_CSCDR2_GPU_EN; + _raw_writel(reg, MXC_CCM_CSCDR2); +} + +static int _clk_gpu_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg; + + mux = _get_mux(parent, &pll2_pfd2, &pll3_pfd2, &NULL, NULL); + + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_GPU_CLK_SEL; + reg |= mux << MXC_CCM_CSCMR1_GPU_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk gpu_clk = { + __INIT_CLK_DEBUG(gpu_clk), + .parent = &pll2_pfd2, //FIXME + .enable_reg = MXC_CCM_CCGR8, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_gpu_enable, + .disable = _clk_gpu_disable, + .get_rate = _clk_gpu_get_rate, + .set_rate = _clk_gpu_set_rate, + .set_parent = _clk_gpu_set_parent, +}; + +static struct clk dma_mux0_clk = { + __INIT_CLK_DEBUG(dma_mux0_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk dma_mux1_clk = { + __INIT_CLK_DEBUG(dma_mux1_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk uart0_clk = { + __INIT_CLK_DEBUG(uart0_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk uart1_clk = { + __INIT_CLK_DEBUG(uart1_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk uart2_clk = { + __INIT_CLK_DEBUG(uart2_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk uart3_clk = { + __INIT_CLK_DEBUG(uart3_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk spi0_clk = { + __INIT_CLK_DEBUG(spi0_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk spi1_clk = { + __INIT_CLK_DEBUG(spi1_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: SAI0 - USBC0 */ + +static struct clk pdb_clk = { + __INIT_CLK_DEBUG(pdb_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk pit_clk = { + __INIT_CLK_DEBUG(pit_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: ADC0 */ + +static struct clk tcon0_clk = { + __INIT_CLK_DEBUG(tcon0_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk wdog_a5_clk = { + __INIT_CLK_DEBUG(wdog_a5_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk wdog_m4_clk = { + __INIT_CLK_DEBUG(wdog_m4_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk lptmr_clk = { + __INIT_CLK_DEBUG(lptmr_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: RLE - QSPI0 */ + +static struct clk iomux_clk = { + __INIT_CLK_DEBUG(iomux_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk port_a_mux_clk = { + __INIT_CLK_DEBUG(port_a_mux_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk port_b_mux_clk = { + __INIT_CLK_DEBUG(port_b_mux_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk port_c_mux_clk = { + __INIT_CLK_DEBUG(port_c_mux_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk port_d_mux_clk = { + __INIT_CLK_DEBUG(port_d_mux_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk port_e_mux_clk = { + __INIT_CLK_DEBUG(port_e_mux_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk anadig_clk = { + __INIT_CLK_DEBUG(anadig_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk scsc_clk = { + __INIT_CLK_DEBUG(scsc_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: ASRC - ESAI */ + +static struct clk ewm_clk = { + __INIT_CLK_DEBUG(ewm_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk i2c0_clk = { + __INIT_CLK_DEBUG(i2c0_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk i2c1_clk = { + __INIT_CLK_DEBUG(i2c1_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: WKUP */ + +static struct clk ccm_clk = { + __INIT_CLK_DEBUG(ccm_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: VREG_DIG */ + +static struct clk src_clk = { + __INIT_CLK_DEBUG(src_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: CMU */ + +static struct clk dma_mux2_clk = { + __INIT_CLK_DEBUG(dma_mux2_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk dma_mux3_clk = { + __INIT_CLK_DEBUG(dma_mux3_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: OTP CTRL */ + +static struct clk uart4_clk = { + __INIT_CLK_DEBUG(uart4_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk uart5_clk = { + __INIT_CLK_DEBUG(uart5_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: SPI2,SPI3? - USB OTG1 */ +/* FIXME: ADC1 */ + +static struct clk tcon1_clk = { + __INIT_CLK_DEBUG(tcon1_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk seg_lcd_clk = { + __INIT_CLK_DEBUG(seg_lcd_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: QSPI1 */ + +static struct clk video_dec_clk = { + __INIT_CLK_DEBUG(video_dec_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR8, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk viu3_clk = { + __INIT_CLK_DEBUG(viu3_clk) + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR8, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +/* FIXME: NFC */ + +static struct clk eth_l2_sw_clk[] = { + { + __INIT_CLK_DEBUG(eth_l2_sw_0_clk) + .id = 0, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[1], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_1_clk) + .id = 1, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[2], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_2_clk) + .id = 2, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[3], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_3_clk) + .id = 3, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[4], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_4_clk) + .id = 4, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[5], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_5_clk) + .id = 5, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[6], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_6_clk) + .id = 6, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = eth_l2_sw_clk[7], + }, + { + __INIT_CLK_DEBUG(eth_l2_sw_7_clk) + .id = 7, + .parent = &ips_bus_clk, + .enable_reg = MXC_CCM_CCGR10, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +/* FIXME: CAAM */ + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + } + + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "osch", osch_clk), + _REGISTER_CLOCK(NULL, "ckih", ckih_clk), + _REGISTER_CLOCK(NULL, "oscl", oscl_clk), + _REGISTER_CLOCK(NULL, "ckil", ckil_clk), + _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk), + _REGISTER_CLOCK(NULL, "pll1_pfd1", pll1_pfd1), + _REGISTER_CLOCK(NULL, "pll1_pfd2", pll1_pfd2), + _REGISTER_CLOCK(NULL, "pll1_pfd3", pll1_pfd3), + _REGISTER_CLOCK(NULL, "pll1_pfd4", pll1_pfd4), + _REGISTER_CLOCK(NULL, "pll1_pfd_out", pll1_pfd_out), + _REGISTER_CLOCK(NULL, "pll1_pfd_out_div", pll1_pfd_out_div), + _REGISTER_CLOCK(NULL, "pll2", pll2_528_main_clk), + _REGISTER_CLOCK(NULL, "pll2_pfd1", pll2_pfd1), + _REGISTER_CLOCK(NULL, "pll2_pfd2", pll2_pfd2), + _REGISTER_CLOCK(NULL, "pll2_pfd3", pll2_pfd3), + _REGISTER_CLOCK(NULL, "pll2_pfd4", pll2_pfd4), + _REGISTER_CLOCK(NULL, "pll1_pfd_out", pll1_pfd_out), + _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_480_usb1_main_clk), + _REGISTER_CLOCK(NULL, "pll3_div_clk", pll3_div_clk), + _REGISTER_CLOCK(NULL, "pll3_pfd1", pll2_pfd1), + _REGISTER_CLOCK(NULL, "pll3_pfd2", pll2_pfd2), + _REGISTER_CLOCK(NULL, "pll3_pfd3", pll2_pfd3), + _REGISTER_CLOCK(NULL, "pll3_pfd4", pll2_pfd4), + _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk), + _REGISTER_CLOCK(NULL, "pll5", pll5_enet_main_clk), + _REGISTER_CLOCK(NULL, "pll6", pll6_video_main_clk), + _REGISTER_CLOCK(NULL, "pll6_div_clk", pll6_div_clk), + _REGISTER_CLOCK(NULL, "pll_usb2", pll_480_usb2_main_clk), + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), + _REGISTER_CLOCK(NULL, "ddrc_clk", ddrc_clk), + _REGISTER_CLOCK(NULL, "plat_bus_clk", plat_bus_clk), + _REGISTER_CLOCK(NULL, "cm4_clk", cm4_clk), + _REGISTER_CLOCK(NULL, "flex_bus_clk", flex_bus_clk), + _REGISTER_CLOCK(NULL, "ips_bus_clk", ips_bus_clk), + _REGISTER_CLOCK(NULL, "gpc_core_clk", gpc_core_clk), + _REGISTER_CLOCK(NULL, "snvs_clk", snvs_clk), + _REGISTER_CLOCK(NULL, "wdog_snvs_clk", wdog_snvs_clk), + _REGISTER_CLOCK(NULL, "can0_root_clk", can0_clk_root), + _REGISTER_CLOCK(NULL, "can1_root_clk", can1_clk_root), + _REGISTER_CLOCK("mvf-flexcan.0", NULL, can0_clk[0]), + _REGISTER_CLOCK("mvf-flexcan.1", NULL, can1_clk[0]), + _REGISTER_CLOCK(NULL, "ftm0_ext_clk", ftm0_ext_clk), + _REGISTER_CLOCK(NULL, "ftm1_ext_clk", ftm1_ext_clk), + _REGISTER_CLOCK(NULL, "ftm2_ext_clk", ftm2_ext_clk), + _REGISTER_CLOCK(NULL, "ftm3_ext_clk", ftm3_ext_clk), + _REGISTER_CLOCK(NULL, "ftm0_fix_clk", ftm0_fix_clk), + _REGISTER_CLOCK(NULL, "ftm1_fix_clk", ftm1_fix_clk), + _REGISTER_CLOCK(NULL, "ftm2_fix_clk", ftm2_fix_clk), + _REGISTER_CLOCK(NULL, "ftm3_fix_clk", ftm3_fix_clk), + _REGISTER_CLOCK(NULL, "ftm0_clk", ftm0_clk), + _REGISTER_CLOCK(NULL, "ftm1_clk", ftm1_clk), + _REGISTER_CLOCK(NULL, "ftm2_clk", ftm2_clk), + _REGISTER_CLOCK(NULL, "ftm3_clk", ftm3_clk), +#if 0 + _REGISTER_CLOCK(NULL, "fec_clk", enet_clk), //FIXME +#else + _REGISTER_CLOCK("fec.0", NULL, enet_clk), //FIXME +#endif + _REGISTER_CLOCK(NULL, "enet_div2_clk", enet_div2_clk), + _REGISTER_CLOCK(NULL, "enet_rmii_clk", enet_rmii_clk), + _REGISTER_CLOCK(NULL, "enet_ts_clk", enet_ts_clk), + _REGISTER_CLOCK(NULL, "dcu0_clk_root", dcu0_clk_root), + _REGISTER_CLOCK(NULL, "dcu1_clk_root", dcu1_clk_root), + _REGISTER_CLOCK(NULL, "dcu0_clk", dcu0_clk[0]), + _REGISTER_CLOCK(NULL, "dcu1_clk", dcu1_clk[0]), + _REGISTER_CLOCK(NULL, "video_adc_clk", video_adc_clk), + _REGISTER_CLOCK(NULL, "video_adc_div2_clk", video_adc_div2_clk), + _REGISTER_CLOCK(NULL, "gpu_clk", gpu_clk), + _REGISTER_CLOCK(NULL, "dma_mix0_clk", dma_mux0_clk), + _REGISTER_CLOCK(NULL, "dma_mix1_clk", dma_mux1_clk), + _REGISTER_CLOCK("imx-uart.0", NULL, uart0_clk), + _REGISTER_CLOCK("imx-uart.1", NULL, uart1_clk), + _REGISTER_CLOCK("imx-uart.2", NULL, uart2_clk), + _REGISTER_CLOCK("imx-uart.3", NULL, uart3_clk), + _REGISTER_CLOCK(NULL, "spi0_clk", spi0_clk), + _REGISTER_CLOCK(NULL, "spi1_clk", spi1_clk), + _REGISTER_CLOCK(NULL, "pdb_clk", pdb_clk), + _REGISTER_CLOCK(NULL, "pit_clk", pit_clk), + _REGISTER_CLOCK(NULL, "tcon0_clk", tcon0_clk), + _REGISTER_CLOCK(NULL, "wdog_a5_clk", wdog_a5_clk), + _REGISTER_CLOCK(NULL, "wdog_m4_clk", wdog_m4_clk), + _REGISTER_CLOCK(NULL, "lptmr_clk", lptmr_clk), + _REGISTER_CLOCK(NULL, "iomux_clk", iomux_clk), + _REGISTER_CLOCK(NULL, "port_a_mux_clk", port_a_mux_clk), + _REGISTER_CLOCK(NULL, "port_b_mux_clk", port_b_mux_clk), + _REGISTER_CLOCK(NULL, "port_c_mux_clk", port_c_mux_clk), + _REGISTER_CLOCK(NULL, "port_d_mux_clk", port_d_mux_clk), + _REGISTER_CLOCK(NULL, "port_e_mux_clk", port_e_mux_clk), + _REGISTER_CLOCK(NULL, "anadig_clk", anadig_clk), + _REGISTER_CLOCK(NULL, "scsc_clk", scsc_clk), + _REGISTER_CLOCK(NULL, "ewm_clk", ewm_clk), + _REGISTER_CLOCK(NULL, "i2c0_clk", i2c0_clk), + _REGISTER_CLOCK(NULL, "i2c1_clk", i2c1_clk), + _REGISTER_CLOCK(NULL, "ccm_clk", ccm_clk), + _REGISTER_CLOCK(NULL, "src_clk", src_clk), + _REGISTER_CLOCK(NULL, "dma_mix2_clk", dma_mux2_clk), + _REGISTER_CLOCK(NULL, "dma_mix3_clk", dma_mux3_clk), + _REGISTER_CLOCK("imx-uart.4", NULL, uart4_clk), + _REGISTER_CLOCK("imx-uart.5", NULL, uart5_clk), + _REGISTER_CLOCK(NULL, "tcon1_clk", tcon1_clk), + _REGISTER_CLOCK(NULL, "seg_lcd_clk", seg_lcd_clk), + _REGISTER_CLOCK(NULL, "video_dec_clk", video_dec_clk), + _REGISTER_CLOCK(NULL, "viu3_clk", viu3_clk), + _REGISTER_CLOCK(NULL, "eth_l2_sw_clk", eth_l2_sw_clk[0]), + _REGISTER_CLOCK(NULL, "anaclk_1", anaclk_1), + _REGISTER_CLOCK(NULL, "audio_ext", audio_ext), + _REGISTER_CLOCK(NULL, "enet_ext", enet_ext), + _REGISTER_CLOCK(NULL, "enet_ts", enet_ts), + _REGISTER_CLOCK(NULL, "usb_clk", usb_clk), +}; + +static void clk_tree_init(void) + +{ + u32 mux; + + mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK) + >> MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET; + switch (mux) { + case 0: + pll1_pfd_out.parent = &pll1_sys_main_clk; + break; + case 1: + pll1_pfd_out.parent = &pll1_pfd1; + break; + case 2: + pll1_pfd_out.parent = &pll1_pfd2; + break; + case 3: + pll1_pfd_out.parent = &pll1_pfd3; + break; + case 4: + pll1_pfd_out.parent = &pll1_pfd4; + break; + } + + mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_MASK) + >> MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET; + switch (mux) { + case 0: + pll2_pfd_out.parent = &pll2_528_main_clk; + break; + case 1: + pll2_pfd_out.parent = &pll2_pfd1; + break; + case 2: + pll2_pfd_out.parent = &pll2_pfd2; + break; + case 3: + pll2_pfd_out.parent = &pll2_pfd3; + break; + case 4: + pll2_pfd_out.parent = &pll2_pfd4; + break; + } + + mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_SYS_CLK_SEL_MASK) + >> MXC_CCM_CCSR_SYS_CLK_SEL_OFFSET; + switch (mux) { + case 0: + sys_clk.parent = &osch_clk; + break; + case 1: + sys_clk.parent = &oscl_clk; + break; + case 2: + sys_clk.parent = &pll2_pfd_out; + break; + case 3: + sys_clk.parent = &pll2_528_main_clk; + break; + case 4: + sys_clk.parent = &pll1_pfd_out; + break; + case 5: + sys_clk.parent = &pll3_480_usb1_main_clk; + break; + } + + mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_CA5_CLK_SEL_MASK) + >> MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET; + switch (mux) { + case 0: + cpu_clk.parent = &sys_clk; + break; + case 1: + cpu_clk.parent = &pll1_pfd_out_div; + break; + } + + mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_DDRC_CLK_SEL) + >> MXC_CCM_CCSR_DDRC_CLK_SEL_OFFSET; + switch (mux) { + case 0: + ddrc_clk.parent = &pll2_pfd2; + break; + case 1: + ddrc_clk.parent = &sys_clk; + break; + } + + mux = (__raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_RMII_CLK_SEL_MASK) + >> MXC_CCM_CSCMR2_RMII_CLK_SEL_OFFSET; + switch (mux) { + case 0: + enet_rmii_clk.parent = &enet_ext; + break; + case 1: + enet_rmii_clk.parent = &audio_ext; + break; + case 2: + enet_rmii_clk.parent = &enet_clk; + break; + case 3: + enet_rmii_clk.parent = &enet_div2_clk; + break; + } + + mux = (__raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_MASK) + >> MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_OFFSET; + switch (mux) { + case 0: + enet_ts_clk.parent = &enet_ext; + break; + case 1: + enet_ts_clk.parent = &osch_clk; + break; + case 2: + enet_ts_clk.parent = &audio_ext; + break; + case 3: + enet_ts_clk.parent = &usb_clk; + break; + case 4: + enet_ts_clk.parent = &enet_ts; + break; + case 5: + enet_ts_clk.parent = &enet_div2_clk; + break; + case 6: + enet_ts_clk.parent = &enet_clk; + break; + } +} + + +int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih, + unsigned long oscl, unsigned long osch) +{ + __iomem void *base; + int i; + + external_low_reference = ckil; + external_high_reference = ckih; + oscillator_low_reference = oscl; + oscillator_high_reference = osch; + + apll_base = ioremap(MVF_ANADIG_BASE_ADDR, SZ_4K); + + clk_tree_init(); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + clk_debug_register(lookups[i].clk); + } + + /* keep correct count. */ + clk_enable(&cpu_clk); + + /* Disable un-necessary PFDs & PLLs */ + if (pll2_pfd1.usecount == 0) + pll2_pfd1.disable(&pll2_pfd1); + if (pll2_pfd2.usecount == 0) + pll2_pfd2.disable(&pll2_pfd2); + if (pll2_pfd3.usecount == 0) + pll2_pfd3.disable(&pll2_pfd3); + if (pll2_pfd4.usecount == 0) + pll2_pfd4.disable(&pll2_pfd4); + +#if !defined(CONFIG_FEC_1588) + pll3_pfd1.disable(&pll3_pfd1); + pll3_pfd2.disable(&pll3_pfd2); + pll3_pfd3.disable(&pll3_pfd3); + pll3_pfd4.disable(&pll3_pfd4); + + pll3_480_usb1_main_clk.disable(&pll3_480_usb1_main_clk); +#endif + pll4_audio_main_clk.disable(&pll4_audio_main_clk); + pll6_video_main_clk.disable(&pll6_video_main_clk); + pll_480_usb2_main_clk.disable(&pll_480_usb2_main_clk); + pll5_enet_main_clk.disable(&pll5_enet_main_clk); + + sata_clk[0].disable(&sata_clk[0]); + pcie_clk[0].disable(&pcie_clk[0]); + + /* Initialize Audio and Video PLLs to valid frequency (650MHz). */ + clk_set_rate(&pll4_audio_main_clk, 650000000); + clk_set_rate(&pll6_video_main_clk, 650000000); + +#if 0 + mvf_cpu_op_init(); + cpu_op_tbl = get_cpu_op(&cpu_op_nr); +#endif + + /* Gate off all possible clocks */ + __raw_writel(3 << MXC_CCM_CCPGRx_PPCG0_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG1_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG2_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG3_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG6_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG9_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG10_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG11_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG12_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG13_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG14_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG15_OFFSET, + MXC_CCM_CCPGR0); + __raw_writel(3 << MXC_CCM_CCPGRx_PPCG0_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG1_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG2_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG3_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG4_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG5_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG7_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG8_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG9_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG13_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG14_OFFSET, + MXC_CCM_CCPGR1); + __raw_writel(3 << MXC_CCM_CCPGRx_PPCG0_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG7_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG8_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG9_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG10_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG12_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG14_OFFSET, + MXC_CCM_CCPGR2); + __raw_writel(3 << MXC_CCM_CCPGRx_PPCG0_OFFSET, + 3 << MXC_CCM_CCPGRx_PPCG1_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG2_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG3_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG4_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG5_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG6_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG8_OFFSET | + 3 << MXC_CCM_CCPGRx_PPCG9_OFFSET, + MXC_CCM_CCPGR3); + + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG5_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR0); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG6_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR1); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET, + MXC_CCM_CCGR2); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR3); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG5_OFFSET | + 3 << MXC_CCM_CCGRx_CG6_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR4); + __raw_writel(3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG5_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET, + MXC_CCM_CCGR6); + __raw_writel(3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET, + MXC_CCM_CCGR7); + __raw_writel(3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR8); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG5_OFFSET | + 3 << MXC_CCM_CCGRx_CG6_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR9); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG6_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, + MXC_CCM_CCGR10); + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG5_OFFSET | + 3 << MXC_CCM_CCGRx_CG6_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET, + MXC_CCM_CCGR11); + + base = ioremap(MVF_PIT_BASE_ADDR, SZ_4K); + mxc_timer_init(&pit_clk, base, MXC_INT_PIT); + + lp_high_freq = 0; + lp_med_freq = 0; + + return 0; + +} diff --git a/arch/arm/mach-mvf/cpu.c b/arch/arm/mach-mvf/cpu.c new file mode 100644 index 000000000000..d4850657f60c --- /dev/null +++ b/arch/arm/mach-mvf/cpu.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/iram_alloc.h> +#include <linux/delay.h> + +#include <mach/hardware.h> +#include <asm/io.h> +#include <asm/mach/map.h> + +#include "crm_regs.h" +#include "cpu_op-mx6.h" + + +void *mx6_wait_in_iram_base; +void (*mx6_wait_in_iram)(void); +extern void mx6_wait(void); + + +struct cpu_op *(*get_cpu_op)(int *op); +bool enable_wait_mode; +u32 arm_max_freq = CPU_AT_1GHz; + +void __iomem *gpc_base; +void __iomem *ccm_base; + +static int cpu_silicon_rev = -1; +#define SI_REV_OFFSET 0x48 + +static int get_mx6q_srev(void) +{ + void __iomem *romcp = ioremap(BOOT_ROM_BASE_ADDR, SZ_8K); + u32 rev; + + if (!romcp) { + cpu_silicon_rev = -EINVAL; + return 0; + } + + rev = __raw_readl(romcp + SI_REV_OFFSET); + rev &= 0xff; + + iounmap(romcp); + if (rev == 0x10) + return IMX_CHIP_REVISION_1_0; + else if (rev == 0x11) + return IMX_CHIP_REVISION_1_1; + else if (rev == 0x20) + return IMX_CHIP_REVISION_2_0; + return 0; +} + +/* + * Returns: + * the silicon revision of the cpu + * -EINVAL - not a mx50 + */ +int mx6q_revision(void) +{ + if (!cpu_is_mx6q()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = get_mx6q_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx6q_revision); + +static int __init post_cpu_init(void) +{ + unsigned int reg; + void __iomem *base; + unsigned long iram_paddr, cpaddr; + + + iram_init(MX6Q_IRAM_BASE_ADDR, MX6Q_IRAM_SIZE); + + base = ioremap(AIPS1_ON_BASE_ADDR, PAGE_SIZE); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + iounmap(base); + + base = ioremap(AIPS2_ON_BASE_ADDR, PAGE_SIZE); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + iounmap(base); + + if (enable_wait_mode) { + /* Allow SCU_CLK to be disabled when all cores are in WFI*/ + base = IO_ADDRESS(SCU_BASE_ADDR); + reg = __raw_readl(base); + reg |= 0x20; + __raw_writel(reg, base); + } + + /* Disable SRC warm reset to work aound system reboot issue */ + base = IO_ADDRESS(SRC_BASE_ADDR); + reg = __raw_readl(base); + reg &= ~0x1; + __raw_writel(reg, base); + + /* Allocate IRAM for WAIT code. */ + /* Move wait routine into iRAM */ + cpaddr = (unsigned long)iram_alloc(SZ_4K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + mx6_wait_in_iram_base = __arm_ioremap(iram_paddr, SZ_4K, + MT_MEMORY_NONCACHED); + pr_info("cpaddr = %x wait_iram_base=%x\n", + (unsigned int)cpaddr, (unsigned int)mx6_wait_in_iram_base); + + /* + * Need to run the suspend code from IRAM as the DDR needs + * to be put into low power mode manually. + */ + memcpy((void *)cpaddr, mx6_wait, SZ_4K); + mx6_wait_in_iram = (void *)mx6_wait_in_iram_base; + + gpc_base = MX6_IO_ADDRESS(GPC_BASE_ADDR); + ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR); + + return 0; +} +postcore_initcall(post_cpu_init); + +static int __init enable_wait(char *p) +{ + if (memcmp(p, "on", 2) == 0) { + enable_wait_mode = true; + p += 2; + } else if (memcmp(p, "off", 3) == 0) { + enable_wait_mode = false; + p += 3; + } + return 0; +} +early_param("enable_wait_mode", enable_wait); + +static int __init arm_core_max(char *p) +{ + if (memcmp(p, "1200", 4) == 0) { + arm_max_freq = CPU_AT_1_2GHz; + p += 4; + } else if (memcmp(p, "1000", 4) == 0) { + arm_max_freq = CPU_AT_1GHz; + p += 4; + } else if (memcmp(p, "800", 3) == 0) { + arm_max_freq = CPU_AT_800MHz; + p += 3; + } + return 0; +} + +early_param("arm_freq", arm_core_max); + + diff --git a/arch/arm/mach-mvf/cpu_op-mvf.c b/arch/arm/mach-mvf/cpu_op-mvf.c new file mode 100644 index 000000000000..8c5dd3e0b556 --- /dev/null +++ b/arch/arm/mach-mvf/cpu_op-mvf.c @@ -0,0 +1,76 @@ +/* + * based on arch/arm/mach-mx6/cpu_op-mx6.c + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> +#include "cpu_op-day.h" + +extern struct cpu_op *(*get_cpu_op)(int *op); +//extern struct dvfs_op *(*get_dvfs_core_op)(int *wp); +extern void (*set_num_cpu_op)(int num); +extern u32 arm_max_freq; +static int num_cpu_op; + +static struct cpu_op mvf_cpu_op[] = { //FIXME + { + .pll_rate = 528000000, + .cpu_rate = 452000000, + .cpu_podf = 0, + .cpu_voltage = 1100000,}, +#if 0 + { + .pll_rate = 792000000, + .cpu_rate = 396000000, + .cpu_podf = 1, + .cpu_voltage = 950000,}, + { + .pll_rate = 792000000, + .cpu_rate = 198000000, + .cpu_podf = 3, + .cpu_voltage = 850000,}, +#endif +}; + +#if 0 //FIXME: need dvfs support ? +static struct dvfs_op dvfs_core_setpoint[] = { + {33, 14, 33, 10, 128, 0x08}, /* 800MHz */ + {26, 8, 33, 100, 200, 0x08}, /* 400MHz */ + {20, 0, 33, 20, 10, 0x08} }; /* 200MHz*/ + +static struct dvfs_op *mvf_get_dvfs_core_table(int *wp) +{ + *wp = ARRAY_SIZE(dvfs_core_setpoint); + return dvfs_core_setpoint; +} +#endif + +struct cpu_op *mvf_get_cpu_op(int *op) +{ + *op = num_cpu_op = ARRAY_SIZE(mvf_cpu_op); + return mvf_cpu_op; +} + +void mvf_set_num_cpu_op(int num) +{ + num_cpu_op = num; + return; +} + +void mvf_cpu_op_init(void) +{ + get_cpu_op = mvf_get_cpu_op; + set_num_cpu_op = mvf_set_num_cpu_op; + + //get_dvfs_core_op = mvf_get_dvfs_core_table; +} + diff --git a/arch/arm/mach-mvf/cpu_op-mvf.h b/arch/arm/mach-mvf/cpu_op-mvf.h new file mode 100644 index 000000000000..7fa20d5ba532 --- /dev/null +++ b/arch/arm/mach-mvf/cpu_op-mvf.h @@ -0,0 +1,14 @@ +/* + * based on arch/arm/mach-mx6/cpu_op-mx6.h + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define CPU_AT_450MHz 0 + +void mvf_cpu_op_init(void); diff --git a/arch/arm/mach-mvf/cpu_regulator-mx6.c b/arch/arm/mach-mvf/cpu_regulator-mx6.c new file mode 100644 index 000000000000..779ed62eea53 --- /dev/null +++ b/arch/arm/mach-mvf/cpu_regulator-mx6.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/jiffies.h> +#include <linux/regulator/consumer.h> +#include <linux/clk.h> +#if defined(CONFIG_CPU_FREQ) +#include <linux/cpufreq.h> +#endif +#include <asm/cpu.h> + +#include <mach/clock.h> +#include <mach/hardware.h> + +struct regulator *cpu_regulator; +char *gp_reg_id; +static struct clk *cpu_clk; +static int cpu_op_nr; +static struct cpu_op *cpu_op_tbl; +extern struct cpu_op *(*get_cpu_op)(int *op); + +extern unsigned long loops_per_jiffy; + +static inline unsigned long mx6_cpu_jiffies(unsigned long old, u_int div, + u_int mult) +{ +#if BITS_PER_LONG == 32 + + u64 result = ((u64) old) * ((u64) mult); + do_div(result, div); + return (unsigned long) result; + +#elif BITS_PER_LONG == 64 + + unsigned long result = old * ((u64) mult); + result /= div; + return result; + +#endif +} + + +void mx6_cpu_regulator_init(void) +{ + int cpu; + u32 curr_cpu = 0; + + cpu_regulator = regulator_get(NULL, gp_reg_id); + if (IS_ERR(cpu_regulator)) + printk(KERN_ERR "%s: failed to get cpu regulator\n", __func__); + else { + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", + __func__); + } else { + curr_cpu = clk_get_rate(cpu_clk); + cpu_op_tbl = get_cpu_op(&cpu_op_nr); + /* Set the core to max frequency requested. */ + regulator_set_voltage(cpu_regulator, + cpu_op_tbl[0].cpu_voltage, + cpu_op_tbl[0].cpu_voltage); + clk_set_rate(cpu_clk, cpu_op_tbl[0].cpu_rate); + + /*Fix loops-per-jiffy */ +#ifdef CONFIG_SMP + for_each_online_cpu(cpu) + per_cpu(cpu_data, cpu).loops_per_jiffy = + mx6_cpu_jiffies( + per_cpu(cpu_data, cpu).loops_per_jiffy, + curr_cpu / 1000, + clk_get_rate(cpu_clk) / 1000); +#else + u32 old_loops_per_jiffy = loops_per_jiffy; + + loops_per_jiffy = + mx6_cpu_jiffies(old_loops_per_jiffy, + curr_cpu/1000, + clk_get_rate(cpu_clk) / 1000); +#endif +#if defined(CONFIG_CPU_FREQ) + /* Fix CPU frequency for CPUFREQ. */ + for (cpu = 0; cpu < num_online_cpus(); cpu++) + cpufreq_get(cpu); +#endif + } + } +} + diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h new file mode 100644 index 000000000000..bf923f355174 --- /dev/null +++ b/arch/arm/mach-mvf/crm_regs.h @@ -0,0 +1,549 @@ +/* + * based on arch/arm/mach-mx6/crm_regs.h + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MVF_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MVF_CRM_REGS_H__ + +/* PLLs */ +#define MXC_PLL_BASE MVF_IO_ADDRESS(MVF_ANADIG_BASE_ADDR) +#define PLL3_480_USB1_BASE_ADDR (MXC_PLL_BASE + 0x10) +#define ANADIG_USB2_PLL_CTRL (MXC_PLL_BASE + 0x20) +#define PLL2_528_BASE_ADDR (MXC_PLL_BASE + 0x30) +#define PLL4_AUDIO_BASE_ADDR (MXC_PLL_BASE + 0x70) +#define PLL6_VIDEO_BASE_ADDR (MXC_PLL_BASE + 0xA0) +#define PLL5_ENET_BASE_ADDR (MXC_PLL_BASE + 0xE0) +#define ANADIG_PLL_PFD_480_USB1 (MXC_PLL_BASE + 0xF0) +#define ANADIG_PLL_PFD_528 (MXC_PLL_BASE + 0x100) +#define ANADIG_REG_1P1 (MXC_PLL_BASE + 0x110) +#define ANADIG_REG_3P0 (MXC_PLL_BASE + 0x120) +#define ANADIG_REG_2P5 (MXC_PLL_BASE + 0x130) +#define ANADIG_ANA_MISC0 (MXC_PLL_BASE + 0x150) +#define ANADIG_ANA_MISC1 (MXC_PLL_BASE + 0x160) +#define ANADIG_TEMPSENS0 (MXC_PLL_BASE + 0x180) +#define ANADIG_TEMPSENS1 (MXC_PLL_BASE + 0x190) +#define ANADIG_USB1_VBUS_DETECT (MXC_PLL_BASE + 0x1A0) +#define ANADIG_USB1_CHRG_DETECT (MXC_PLL_BASE + 0x1B0) +#define ANADIG_USB1_VBUS_DETECT_STAT (MXC_PLL_BASE + 0x1C0) +#define ANADIG_USB1_CHRG_DETECT_STAT (MXC_PLL_BASE + 0x1D0) +#define ANADIG_USB1_LOOPBACK (MXC_PLL_BASE + 0x1E0) +#define ANADIG_USB1_MISC (MXC_PLL_BASE + 0x1F0) +#define ANADIG_USB2_VBUS_DETECT (MXC_PLL_BASE + 0x200) +#define ANADIG_USB2_CHRG_DETECT (MXC_PLL_BASE + 0x210) +#define ANADIG_USB2_VBUS_DETECT_STAT (MXC_PLL_BASE + 0x220) +#define ANADIG_USB2_CHRG_DETECT_STAT (MXC_PLL_BASE + 0x230) +#define ANADIG_USB2_LOOPBACK (MXC_PLL_BASE + 0x240) +#define ANADIG_USB2_MISC (MXC_PLL_BASE + 0x250) +#define ANADIG_DEGPROG (MXC_PLL_BASE + 0x260) +#define PLL1_SYS_BASE_ADDR (MXC_PLL_BASE + 0x270) +#define ANADIG_PLL_PFD_528_SYS (MXC_PLL_BASE + 0x2B0) +#define ANADIG_PLL_LOCK_REG (MXC_PLL_BASE + 0x2C0) + +#define PLL_NUM_DIV_OFFSET 0x10 +#define PLL_DENOM_DIV_OFFSET 0x20 +#define PLL_528_SS_OFFSET 0x10 +#define PLL_528_NUM_DIV_OFFSET 0x20 +#define PLL_528_DENOM_DIV_OFFSET 0x30 + +/* Common PLL register bit defines. */ +#define ANADIG_PLL_LOCK (1 << 31) +#define ANADIG_PLL_PFD_OFFSET_EN (1 << 18) +#define ANADIG_PLL_DITHER_ENABLE (1 << 17) +#define ANADIG_PLL_BYPASS (1 << 16) +#define ANADIG_PLL_BYPASS_CLK_SRC (14) +#define ANADIG_PLL_ENABLE (1 << 13) +#define ANADIG_PLL_POWER_DOWN (1 << 12) +#define ANADIG_PLL_HOLD_RING_OFF (1 << 11) +#define ANADIG_PLL_DOUBLE_CP (1 << 10) +#define ANADIG_PLL_HALF_CP (1 << 9) +#define ANADIG_PLL_DOUBLE_LF (1 << 8) +#define ANADIG_PLL_HALF_LF (1 << 7) + +/* PLL1_SYS defines */ +#define ANADIG_PLL_SYS_DIV_SELECT (1) + +/* PLL2_528 defines */ +#define ANADIG_PLL_528_DIV_SELECT (1) + +/* PLL3_480 defines. */ +#define ANADIG_PLL_480_EN_USB_CLKS (1 << 6) +#define ANADIG_PLL_480_DIV_SELECT_MASK (0x3) +#define ANADIG_PLL_480_DIV_SELECT_OFFSET (0) + +/* PLL4_AUDIO PLL6_VIDEO defines. */ +#define ANADIG_PLL_AV_DIV_SELECT_MASK (0x7F) +#define ANADIG_PLL_AV_DIV_SELECT_OFFSET (0) +#define ANADIG_PLL_AV_TEST_DIV_SEL_MASK (0x180000) +#define ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET (19) + +/* PLL5_ENET defines. */ +#define ANADIG_PLL_ENET_DIV_SELECT_MASK (0x3) +#define ANADIG_PLL_ENET_DIV_SELECT_OFFSET (0) + +/* PFD register defines. */ +#define ANADIG_PFD_CLKGATE (1 << 7) +#define ANADIG_PFD_STABLE (1 << 6) +#define ANADIG_PFD_FRAC_MASK 0x3F +#define ANADIG_PFD4_FRAC_SHIFT 24 +#define ANADIG_PFD3_FRAC_SHIFT 16 +#define ANADIG_PFD2_FRAC_SHIFT 8 +#define ANADIG_PFD1_FRAC_SHIFT 0 + +/* ANATOP Regulator/LDO defines */ +#define ANADIG_REG_OK (1 << 17) +#define ANADIG_REG_BO (1 << 16) +#define ANADIG_REG_3P0_VBUS_SEL (1 << 7) +#define ANADIG_REG_1P1_2P5_ENABLE_PULL_DOWN (1 << 3) +#define ANADIG_REG_ENABLE_LIMIT (1 << 2) +#define ANADIG_REG_ENABLE_BO (1 << 1) +#define ANADIG_REG_ENABLE_LINREG (1) + +/* ANA MISC0 register defines */ +#define ANADIG_ANA_MISC0_CLKGATE_DELAY_MASK 0x1C000000 +#define ANADIG_ANA_MISC0_CLKGATE_DELAY_OFFSET 26 +#define ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25) +#define ANADIG_ANA_MISC0_ANAMUX_MASK 0x01E00000 +#define ANADIG_ANA_MISC0_ANAMUX_OFFSET 21 +#define ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20) +#define ANADIG_ANA_MISC0_WBCP_VPN_THRESH_MASK 0x000C0000 +#define ANADIG_ANA_MISC0_WBCP_VPN_THRESH_OFFSET 18 +#define ANADIG_ANA_MISC0_OSC_XTALOC_EN (1 << 17) +#define ANADIG_ANA_MISC0_OSC_XTALOC (1 << 16) +#define ANADIG_ANA_MISC0_OSC_I_MASK 0x0000C000 +#define ANADIG_ANA_MISC0_OSC_I_OFFSET 14 +#define ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13) +#define ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) +#define ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) +#define ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) +#define ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) +#define ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) +#define ANADIG_ANA_MISC0_REFTOP_PWD (1) + +/* ANA MISC1 register defines */ +#define ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30) +#define ANADIG_ANA_MISC1_IRQ_TEMPSENSE (1 << 29) +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_OFFSET 0 + +#define MXC_CCM_BASE MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR) +/* CCM Register Offsets. */ +//#define MXC_CCM_CDCR_OFFSET 0x4C +#define MXC_CCM_CACRR_OFFSET 0x0c +//#define MXC_CCM_CDHIPR_OFFSET 0x48 + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x0c) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x1c) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x2c) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x4c) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x5c) +#define MXC_CCM_CCGR8 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CCGR9 (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR10 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR11 (MXC_CCM_BASE + 0x6c) +#define MXC_CCM_CMEOR0 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CMEOR1 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CMEOR2 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CMEOR3 (MXC_CCM_BASE + 0x7c) +#define MXC_CCM_CMEOR4 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR5 (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CPPDSR (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CCOWR (MXC_CCM_BASE + 0x8c) +#define MXC_CCM_CCPGR0 (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CCPGR1 (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CCPGR2 (MXC_CCM_BASE + 0x98) +#define MXC_CCM_CCPGR3 (MXC_CCM_BASE + 0x9c) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_FIRC_EN (1 << 16) +#define MXC_CCM_CCR_FXOSC_EN (1 << 12) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_FXOSC_RDY (1 << 5) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_PLL3_PFD4_EN (1 << 31) +#define MXC_CCM_CCSR_PLL3_PFD3_EN (1 << 30) +#define MXC_CCM_CCSR_PLL3_PFD2_EN (1 << 29) +#define MXC_CCM_CCSR_PLL3_PFD1_EN (1 << 28) +#define MXC_CCM_CCSR_DAP_EN (1 << 24) +#define MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) +#define MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET (19) +#define MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET (16) +#define MXC_CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define MXC_CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define MXC_CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define MXC_CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define MXC_CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define MXC_CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define MXC_CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define MXC_CCM_CCSR_PLL1_PFD1_EN (1 << 8) +#define MXC_CCM_CCSR_DDRC_CLK_SEL (1 << 6) +#define MXC_CCM_CCSR_DDRC_CLK_SEL_OFFSET (6) +#define MXC_CCM_CCSR_FAST_CLK_SEL (1 << 5) +#define MXC_CCM_CCSR_SLOW_CLK_SEL (1 << 4) +#define MXC_CCM_CCSR_CA5_CLK_SEL (1 << 3) +#define MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET (3) +#define MXC_CCM_CCSR_SYS_CLK_SEL_MASK (0x7) +#define MXC_CCM_CCSR_SYS_CLK_SE_OFFSET (0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_FLEX_CLK_DIV_MASK (0x7 << 22) +#define MXC_CCM_CACRR_FLEX_CLK_DIV_OFFSET (22) +#define MXC_CCM_CACRR_PLL6_CLK_DIV (1 << 21) +#define MXC_CCM_CACRR_PLL6_CLK_DIV_OFFSET (21) +#define MXC_CCM_CACRR_PLL3_CLK_DIV (1 << 20) +#define MXC_CCM_CACRR_PLL3_CLK_DIV_OFFSET (20) +#define MXC_CCM_CACRR_PLL1_PFD_CLK_DIV_MASK (0x3 << 16) +#define MXC_CCM_CACRR_PLL1_PFD_CLK_DIV_OFFSET (16) +#define MXC_CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET (11) +#define MXC_CCM_CACRR_PLL4_CLK_DIV_MASK (0x7 << 6) +#define MXC_CCM_CACRR_PLL4_CLK_DIV_OFFSET (6) +#define MXC_CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET (3) +#define MXC_CCM_CACRR_ARM_CLK_DIV_MASK (0x7) +#define MXC_CCM_CACRR_ARM_CLK_DIV_OFFSET (0) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_DCU1_CLK_SEL (1 << 29) +#define MXC_CCM_CSCMR1_DCU1_CLK_SEL_OFFSET (29) +#define MXC_CCM_CSCMR1_DCU0_CLK_SEL (1 << 28) +#define MXC_CCM_CSCMR1_DCU0_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_ESAI_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESAI_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR1_ESDHC0_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_ESDHC0_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_GPU_CLK_SEL (1 << 14) +#define MXC_CCM_CSCMR1_GPU_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_NFC_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR1_VADC_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_VADC_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR1_SAI3_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_MASK (0x3) +#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_OFFSET (0) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_FTM3_CLK_EN (1 << 28) +#define MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET (28) +#define MXC_CCM_CSCDR1_FTM2_CLK_EN (1 << 27) +#define MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET (27) +#define MXC_CCM_CSCDR1_FTM1_CLK_EN (1 << 26) +#define MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET (26) +#define MXC_CCM_CSCDR1_FTM0_CLK_EN (1 << 25) +#define MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET (25) +#define MXC_CCM_CSCDR1_RMII_CLK_EN (1 << 24) +#define MXC_CCM_CSCDR1_ENET_ST_EN (1 << 23) +#define MXC_CCM_CSCDR1_VADC_EN (1 << 22) +#define MXC_CCM_CSCDR1_VADC_DIV_MASK (0x3 << 20) +#define MXC_CCM_CSCDR1_VADC_DIV_OFFSET (20) +#define MXC_CCM_CSCDR1_SAI3_EN (1 << 19) +#define MXC_CCM_CSCDR1_SAI2_EN (1 << 18) +#define MXC_CCM_CSCDR1_SAI1_EN (1 << 17) +#define MXC_CCM_CSCDR1_SAI0_EN (1 << 16) +#define MXC_CCM_CSCDR1_SAI3_DIV_MASK (0xF << 12) +#define MXC_CCM_CSCDR1_SAI3_DIV_OFFSET (12) +#define MXC_CCM_CSCDR1_SAI2_DIV_MASK (0xF << 8) +#define MXC_CCM_CSCDR1_SAI2_DIV_OFFSET (8) +#define MXC_CCM_CSCDR1_SAI1_DIV_MASK (0xF << 4) +#define MXC_CCM_CSCDR1_SAI1_DIV_OFFSET (4) +#define MXC_CCM_CSCDR1_SAI0_DIV_MASK (0xF) +#define MXC_CCM_CSCDR1_SAI0_DIV_OFFSET (0) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ESAI_EN (1 << 30) +#define MXC_CCM_CSCDR2_ESDHC1_EN (1 << 29) +#define MXC_CCM_CSCDR2_ESDHC0_EN (1 << 28) +#define MXC_CCM_CSCDR2_ESAI_DIV_MASK (0xF << 24) +#define MXC_CCM_CSCDR2_ESAI_DIV_OFFSET (24) +#define MXC_CCM_CSCDR2_ESDHC1_DIV_MASK (0xF << 20) +#define MXC_CCM_CSCDR2_ESDHC1_DIV_OFFSET (20) +#define MXC_CCM_CSCDR2_ESDHC0_DIV_MASK (0xF << 16) +#define MXC_CCM_CSCDR2_ESDHC0_DIV_OFFSET (16) +#define MXC_CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define MXC_CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) +#define MXC_CCM_CSCDR2_CAN1_EN (1 << 12) +#define MXC_CCM_CSCDR2_CAN0_EN (1 << 11) +#define MXC_CCM_CSCDR2_GPU_EN (1 << 10) +#define MXC_CCM_CSCDR2_NFC_EN (1 << 9) +#define MXC_CCM_CSCDR2_SPDIF_EN (1 << 8) +#define MXC_CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xF << 4) +#define MXC_CCM_CSCDR2_NFC_FRAC_DIV_OFFSET (4) +#define MXC_CCM_CSCDR2_SPDIF_DIV_MASK (0xF) +#define MXC_CCM_CSCDR2_SPDIF_DIV_OFFSET (0) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_SWO_EN (1 << 28) +#define MXC_CCM_CSCDR3_SWO_DIV (1 << 27) +#define MXC_CCM_CSCDR3_TRACE_EN (1 << 26) +#define MXC_CCM_CSCDR3_TRACE_DIV_MASK (0x3 << 24) +#define MXC_CCM_CSCDR3_TRACE_DIV_OFFSET (24) +#define MXC_CCM_CSCDR3_DCU1_EN (1 << 23) +#define MXC_CCM_CSCDR3_DCU1_EN_OFFSET (23) +#define MXC_CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20) +#define MXC_CCM_CSCDR3_DCU1_DIV_OFFSET (20) +#define MXC_CCM_CSCDR3_DCU0_EN (1 << 19) +#define MXC_CCM_CSCDR3_DCU0_EN_OFFSET (19) +#define MXC_CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_DCU0_DIV_OFFSET (16) +#define MXC_CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define MXC_CCM_CSCDR3_NFC_PRE_DIV_OFFSET (13) +#define MXC_CCM_CSCDR3_QSPI1_EN (1 << 12) +#define MXC_CCM_CSCDR3_QSPI1_DIV (1 << 11) +#define MXC_CCM_CSCDR3_QSPI1_X2_DIV (1 << 10) +#define MXC_CCM_CSCDR3_QSPI1_X4_DIV_MASK (0x3 << 8) +#define MXC_CCM_CSCDR3_QSPI1_X4_DIV_OFFSET (8) +#define MXC_CCM_CSCDR3_QSPI0_EN (1 << 4) +#define MXC_CCM_CSCDR3_QSPI0_DIV (1 << 3) +#define MXC_CCM_CSCDR3_QSPI0_X2_DIV (1 << 2) +#define MXC_CCM_CSCDR3_QSPI0_X4_DIV_MASK (0x3) +#define MXC_CCM_CSCDR3_QSPI0_X4_DIV_OFFSET (0) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_SWO_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR2_TRACE_CLK_SEL (1 << 18) +#define MXC_CCM_CSCMR2_FTM3_FIX_CLK_SEL (1 << 17) +#define MXC_CCM_CSCMR2_FTM2_FIX_CLK_SEL (1 << 16) +#define MXC_CCM_CSCMR2_FTM1_FIX_CLK_SEL (1 << 15) +#define MXC_CCM_CSCMR2_FTM0_FIX_CLK_SEL (1 << 14) +#define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR2_RMII_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_MASK (0x7) +#define MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_OFFSET (0) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_SNVS_CLK_DIV_MASK (0x7F) +#define MXC_CCM_CSCDR4_SNVS_CLK_DIV_OFFSET (0) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_M_L2CC_IDLE (1 << 25) +#define MXC_CCM_CLPCR_M_SCU_IDLE (1 << 24) +#define MXC_CCM_CLPCR_M_CORE1_WFI (1 << 23) +#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) +#define MXC_CCM_CLPCR_XOSC_PWRDOWN (1 << 11) +#define MXC_CCM_CLPCR_ANATOP_STOP_MODE (1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) +#define MXC_CCM_CLPCR_SBYOS (1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_LPM (1 << 5) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_XOSC_READY (1 << 6) +#define MXC_CCM_CISR_LRF_PLL4 (1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_M_XOSC_READY (1 << 6) +#define MXC_CCM_CIMR_M_LRF_PLL4 (1 << 3) +#define MXC_CCM_CIMR_M_LRF_PLL3 (1 << 2) +#define MXC_CCM_CIMR_M_LRF_PLL2 (1 << 1) +#define MXC_CCM_CIMR_M_LRF_PLL1 (1) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGRx_CG_MASK 0x3 +#define MXC_CCM_CCGRx_MOD_OFF 0x0 +#define MXC_CCM_CCGRx_MOD_IDLE 0x1 +#define MXC_CCM_CCGRx_MOD_FORCE_ON 0x2 +#define MXC_CCM_CCGRx_MOD_ON 0x3 + +#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGRx_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) + +#define MXC_CCM_CCGRx_CG15_OFFSET 30 +#define MXC_CCM_CCGRx_CG14_OFFSET 28 +#define MXC_CCM_CCGRx_CG13_OFFSET 26 +#define MXC_CCM_CCGRx_CG12_OFFSET 24 +#define MXC_CCM_CCGRx_CG11_OFFSET 22 +#define MXC_CCM_CCGRx_CG10_OFFSET 20 +#define MXC_CCM_CCGRx_CG9_OFFSET 18 +#define MXC_CCM_CCGRx_CG8_OFFSET 16 +#define MXC_CCM_CCGRx_CG7_OFFSET 14 +#define MXC_CCM_CCGRx_CG6_OFFSET 12 +#define MXC_CCM_CCGRx_CG5_OFFSET 10 +#define MXC_CCM_CCGRx_CG4_OFFSET 8 +#define MXC_CCM_CCGRx_CG3_OFFSET 6 +#define MXC_CCM_CCGRx_CG2_OFFSET 4 +#define MXC_CCM_CCGRx_CG1_OFFSET 2 +#define MXC_CCM_CCGRx_CG0_OFFSET 0 + +/* Define the bits in registers CMEORx */ +#define MXC_CCM_CMEORx_MO31 (1 << 31) +#define MXC_CCM_CMEORx_MO30 (1 << 30) +#define MXC_CCM_CMEORx_MO29 (1 << 29) +#define MXC_CCM_CMEORx_MO28 (1 << 28) +#define MXC_CCM_CMEORx_MO27 (1 << 27) +#define MXC_CCM_CMEORx_MO26 (1 << 26) +#define MXC_CCM_CMEORx_MO25 (1 << 25) +#define MXC_CCM_CMEORx_MO24 (1 << 24) +#define MXC_CCM_CMEORx_MO23 (1 << 23) +#define MXC_CCM_CMEORx_MO22 (1 << 22) +#define MXC_CCM_CMEORx_MO21 (1 << 21) +#define MXC_CCM_CMEORx_MO20 (1 << 20) +#define MXC_CCM_CMEORx_MO19 (1 << 19) +#define MXC_CCM_CMEORx_MO18 (1 << 18) +#define MXC_CCM_CMEORx_MO17 (1 << 17) +#define MXC_CCM_CMEORx_MO16 (1 << 16) +#define MXC_CCM_CMEORx_MO15 (1 << 15) +#define MXC_CCM_CMEORx_MO14 (1 << 14) +#define MXC_CCM_CMEORx_MO13 (1 << 13) +#define MXC_CCM_CMEORx_MO12 (1 << 12) +#define MXC_CCM_CMEORx_MO11 (1 << 11) +#define MXC_CCM_CMEORx_MO10 (1 << 10) +#define MXC_CCM_CMEORx_MO9 (1 << 9) +#define MXC_CCM_CMEORx_MO8 (1 << 8) +#define MXC_CCM_CMEORx_MO7 (1 << 7) +#define MXC_CCM_CMEORx_MO6 (1 << 6) +#define MXC_CCM_CMEORx_MO5 (1 << 5) +#define MXC_CCM_CMEORx_MO4 (1 << 4) +#define MXC_CCM_CMEORx_MO3 (1 << 3) +#define MXC_CCM_CMEORx_MO2 (1 << 2) +#define MXC_CCM_CMEORx_MO1 (1 << 1) +#define MXC_CCM_CMEORx_MO0 (1) + +/* Define the bits in registers CPPDSR */ +#define MXC_CCM_CPPDSR_PLL3_PFD4 (1 << 11) +#define MXC_CCM_CPPDSR_PLL3_PFD3 (1 << 10) +#define MXC_CCM_CPPDSR_PLL3_PFD2 (1 << 9) +#define MXC_CCM_CPPDSR_PLL3_PFD1 (1 << 8) +#define MXC_CCM_CPPDSR_PLL2_PFD4 (1 << 7) +#define MXC_CCM_CPPDSR_PLL2_PFD3 (1 << 6) +#define MXC_CCM_CPPDSR_PLL2_PFD2 (1 << 5) +#define MXC_CCM_CPPDSR_PLL2_PFD1 (1 << 4) +#define MXC_CCM_CPPDSR_PLL1_PFD4 (1 << 3) +#define MXC_CCM_CPPDSR_PLL1_PFD3 (1 << 2) +#define MXC_CCM_CPPDSR_PLL1_PFD2 (1 << 1) +#define MXC_CCM_CPPDSR_PLL1_PFD1 (1) + +/* Define the bits in registers CCOWR */ +#define MXC_CCM_CCOWR_AUX_CORE_WKUP (1) + +/* Define the bits in registers CCPGRn */ +#define MXC_CCM_CCPGRx_CG_MASK 0x3 +#define MXC_CCM_CCPGRx_MOD_OFF 0x0 +#define MXC_CCM_CCPGRx_MOD_IDLE 0x1 +#define MXC_CCM_CCPGRx_MOD_FORCE_ON 0x2 +#define MXC_CCM_CCPGRx_MOD_ON 0x3 + +#define MXC_CCM_CCPGRx_PPCG15_MASK (0x3 << 30) +#define MXC_CCM_CCPGRx_PPCG14_MASK (0x3 << 28) +#define MXC_CCM_CCPGRx_PPCG13_MASK (0x3 << 26) +#define MXC_CCM_CCPGRx_PPCG12_MASK (0x3 << 24) +#define MXC_CCM_CCPGRx_PPCG11_MASK (0x3 << 22) +#define MXC_CCM_CCPGRx_PPCG10_MASK (0x3 << 20) +#define MXC_CCM_CCPGRx_PPCG9_MASK (0x3 << 18) +#define MXC_CCM_CCPGRx_PPCG8_MASK (0x3 << 16) +#define MXC_CCM_CCPGRx_PPCG7_MASK (0x3 << 14) +#define MXC_CCM_CCPGRx_PPCG5_MASK (0x3 << 10) +#define MXC_CCM_CCPGRx_PPCG4_MASK (0x3 << 8) +#define MXC_CCM_CCPGRx_PPCG3_MASK (0x3 << 6) +#define MXC_CCM_CCPGRx_PPCG2_MASK (0x3 << 4) +#define MXC_CCM_CCPGRx_PPCG1_MASK (0x3 << 2) +#define MXC_CCM_CCPGRx_PPCG0_MASK (0x3 << 0) + +#define MXC_CCM_CCPGRx_PPCG15_OFFSET 30 +#define MXC_CCM_CCPGRx_PPCG14_OFFSET 28 +#define MXC_CCM_CCPGRx_PPCG13_OFFSET 26 +#define MXC_CCM_CCPGRx_PPCG12_OFFSET 24 +#define MXC_CCM_CCPGRx_PPCG11_OFFSET 22 +#define MXC_CCM_CCPGRx_PPCG10_OFFSET 20 +#define MXC_CCM_CCPGRx_PPCG9_OFFSET 18 +#define MXC_CCM_CCPGRx_PPCG8_OFFSET 16 +#define MXC_CCM_CCPGRx_PPCG7_OFFSET 14 +#define MXC_CCM_CCPGRx_PPCG6_OFFSET 12 +#define MXC_CCM_CCPGRx_PPCG5_OFFSET 10 +#define MXC_CCM_CCPGRx_PPCG4_OFFSET 8 +#define MXC_CCM_CCPGRx_PPCG3_OFFSET 6 +#define MXC_CCM_CCPGRx_PPCG2_OFFSET 4 +#define MXC_CCM_CCPGRx_PPCG1_OFFSET 2 +#define MXC_CCM_CCPGRx_PPCG0_OFFSET 0 + +/* CAN */ +#define MXC_CAN0_BASE MVF_IO_ADDRESS(MVF_FLEX_CAN0_BASE_ADDR) +#define CAN0_CTRL1 (MXC_CAN0_BASE + 0x4) + +#define MXC_CAN1_BASE MVF_IO_ADDRESS(MVF_FLEX_CAN1_BASE_ADDR) +#define CAN1_CTRL1 (MXC_CAN1_BASE + 0x4) + +#define CAN_CTRL_CLKSRC (1 << 13) +#define CAN_CTRL_CLKSRC_OFFSET (13) + +/* FTM */ +#define MXC_FTM0_BASE MVF_IO_ADDRESS(MVF_FTM0_BASE_ADDR) +#define FTM0_SC (MXC_FTM0_BASE + 0x0) + +#define MXC_FTM1_BASE MVF_IO_ADDRESS(MVF_FTM1_BASE_ADDR) +#define FTM1_SC (MXC_FTM1_BASE + 0x0) + +#define MXC_FTM2_BASE MVF_IO_ADDRESS(MVF_FTM2_BASE_ADDR) +#define FTM2_SC (MXC_FTM2_BASE + 0x0) + +#define MXC_FTM3_BASE MVF_IO_ADDRESS(MVF_FTM3_BASE_ADDR) +#define FTM3_SC (MXC_FTM3_BASE + 0x0) + +#define FTM_SC_CLKS_MASK (0x3 << 3) +#define FTM_SC_CLKS_OFFSET (3) + +#endif /* __ARCH_ARM_MACH_MVF_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mvf/devices-imx6q.h b/arch/arm/mach-mvf/devices-imx6q.h new file mode 100644 index 000000000000..ab245158cfb7 --- /dev/null +++ b/arch/arm/mach-mvf/devices-imx6q.h @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/mx6.h> +#include <mach/devices-common.h> + +extern const struct imx_imx_uart_1irq_data imx6q_imx_uart_data[] __initconst; +#define imx6q_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx6q_imx_uart_data[id], pdata) + +extern const struct imx_snvs_rtc_data imx6q_imx_snvs_rtc_data __initconst; +#define imx6q_add_imx_snvs_rtc() \ + imx_add_snvs_rtc(&imx6q_imx_snvs_rtc_data) + +extern const struct imx_anatop_thermal_imx_data +imx6q_anatop_thermal_imx_data __initconst; +#define imx6q_add_anatop_thermal_imx(id, pdata) \ + imx_add_anatop_thermal_imx(&imx6q_anatop_thermal_imx_data, pdata) + +extern const struct imx_dma_data imx6q_dma_data __initconst; +#define imx6q_add_dma() imx_add_dma(&imx6q_dma_data); + +#define imx6q_add_gpmi(platform_data) imx_add_gpmi(platform_data); + +extern const struct imx_fec_data imx6q_fec_data __initconst; +#define imx6q_add_fec(pdata) \ + imx_add_fec(&imx6q_fec_data, pdata) + +extern const struct imx_sdhci_esdhc_imx_data +imx6q_sdhci_usdhc_imx_data[] __initconst; +#define imx6q_add_sdhci_usdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx6q_sdhci_usdhc_imx_data[id], pdata) + +extern const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst; +#define imx6q_add_ecspi(id, pdata) \ + imx_add_spi_imx(&imx6q_ecspi_data[id], pdata) + +extern const struct imx_imx_i2c_data imx6q_imx_i2c_data[] __initconst; +#define imx6q_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx6q_imx_i2c_data[id], pdata) + +extern const struct imx_fsl_usb2_udc_data imx6q_fsl_usb2_udc_data __initconst; +#define imx6q_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx6q_fsl_usb2_udc_data, pdata) + +extern const struct imx_mxc_ehci_data imx6q_mxc_ehci_otg_data __initconst; +#define imx6q_add_fsl_ehci_otg(pdata) \ + imx_add_fsl_ehci(&imx6q_mxc_ehci_otg_data, pdata) + +extern const struct imx_mxc_ehci_data imx6q_mxc_ehci_hs_data[] __initconst; +#define imx6q_add_fsl_ehci_hs(id, pdata) \ + imx_add_fsl_ehci(&imx6q_mxc_ehci_hs_data[id - 1], pdata) + +extern const struct imx_fsl_usb2_otg_data imx6q_fsl_usb2_otg_data __initconst; +#define imx6q_add_fsl_usb2_otg(pdata) \ + imx_add_fsl_usb2_otg(&imx6q_fsl_usb2_otg_data, pdata) + +extern const struct imx_fsl_usb2_wakeup_data imx6q_fsl_otg_wakeup_data __initconst; +#define imx6q_add_fsl_usb2_otg_wakeup(pdata) \ + imx_add_fsl_usb2_wakeup(&imx6q_fsl_otg_wakeup_data, pdata) + +extern const struct imx_fsl_usb2_wakeup_data imx6q_fsl_hs_wakeup_data[] __initconst; +#define imx6q_add_fsl_usb2_hs_wakeup(id, pdata) \ + imx_add_fsl_usb2_wakeup(&imx6q_fsl_hs_wakeup_data[id - 1], pdata) + +extern const struct imx_imx_esai_data imx6q_imx_esai_data[] __initconst; +#define imx6q_add_imx_esai(id, pdata) \ + imx_add_imx_esai(&imx6q_imx_esai_data[id], pdata) + +extern const struct imx_viv_gpu_data imx6_gpu_data __initconst; + +extern const struct imx_ahci_data imx6q_ahci_data __initconst; +#define imx6q_add_ahci(id, pdata) \ + imx_add_ahci(&imx6q_ahci_data, pdata) + +extern const struct imx_imx_ssi_data imx6_imx_ssi_data[] __initconst; +#define imx6q_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx6_imx_ssi_data[id], pdata) + +extern const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst; +#define imx6q_add_ipuv3(id, pdata) imx_add_ipuv3(id, &imx6q_ipuv3_data[id], pdata) +#define imx6q_add_ipuv3fb(id, pdata) imx_add_ipuv3_fb(id, pdata) + +#define imx6q_add_lcdif(pdata) \ + platform_device_register_resndata(NULL, "mxc_lcdif",\ + 0, NULL, 0, pdata, sizeof(*pdata)); + +extern const struct imx_ldb_data imx6q_ldb_data __initconst; +#define imx6q_add_ldb(pdata) \ + imx_add_ldb(&imx6q_ldb_data, pdata); + +#define imx6q_add_v4l2_output(id) \ + platform_device_register_resndata(NULL, "mxc_v4l2_output",\ + id, NULL, 0, NULL, 0); + +#define imx6q_add_v4l2_capture(id) \ + platform_device_register_resndata(NULL, "mxc_v4l2_capture",\ + id, NULL, 0, NULL, 0); + +extern const struct imx_mxc_hdmi_data imx6q_mxc_hdmi_data __initconst; +#define imx6q_add_mxc_hdmi(pdata) \ + imx_add_mxc_hdmi(&imx6q_mxc_hdmi_data, pdata) + +extern const struct imx_mxc_hdmi_core_data imx6q_mxc_hdmi_core_data __initconst; +#define imx6q_add_mxc_hdmi_core(pdata) \ + imx_add_mxc_hdmi_core(&imx6q_mxc_hdmi_core_data, pdata) + +extern const struct imx_vpu_data imx6q_vpu_data __initconst; +#define imx6q_add_vpu() imx_add_vpu(&imx6q_vpu_data) + +extern const struct imx_otp_data imx6q_otp_data __initconst; +#define imx6q_add_otp() \ + imx_add_otp(&imx6q_otp_data) + +extern const struct imx_viim_data imx6q_viim_data __initconst; +#define imx6q_add_viim() \ + imx_add_viim(&imx6q_viim_data) + +extern const struct imx_imx2_wdt_data imx6q_imx2_wdt_data[] __initconst; +#define imx6q_add_imx2_wdt(id, pdata) \ + imx_add_imx2_wdt(&imx6q_imx2_wdt_data[id]) + +extern const struct imx_pm_imx_data imx6q_pm_imx_data __initconst; +#define imx6q_add_pm_imx(id, pdata) \ + imx_add_pm_imx(&imx6q_pm_imx_data, pdata) + +extern const struct imx_imx_asrc_data imx6q_imx_asrc_data[] __initconst; +#define imx6q_add_asrc(pdata) \ + imx_add_imx_asrc(imx6q_imx_asrc_data, pdata) + +extern const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst; +#define imx6q_add_ecspi(id, pdata) \ + imx_add_spi_imx(&imx6q_ecspi_data[id], pdata) + +extern const struct imx_dvfs_core_data imx6q_dvfs_core_data __initconst; +#define imx6q_add_dvfs_core(pdata) \ + imx_add_dvfs_core(&imx6q_dvfs_core_data, pdata) + +extern const struct imx_viv_gpu_data imx6_gc2000_data __initconst; +extern const struct imx_viv_gpu_data imx6_gc320_data __initconst; +extern const struct imx_viv_gpu_data imx6_gc355_data __initconst; + +extern const struct imx_mxc_pwm_data imx6q_mxc_pwm_data[] __initconst; +#define imx6q_add_mxc_pwm(id) \ + imx_add_mxc_pwm(&imx6q_mxc_pwm_data[id]) + +#define imx6q_add_mxc_pwm_backlight(id, pdata) \ + platform_device_register_resndata(NULL, "pwm-backlight",\ + id, NULL, 0, pdata, sizeof(*pdata)); + +extern const struct imx_spdif_data imx6q_imx_spdif_data __initconst; +#define imx6q_add_spdif(pdata) imx_add_spdif(&imx6q_imx_spdif_data, pdata) + +extern const struct imx_spdif_dai_data imx6q_spdif_dai_data __initconst; +#define imx6q_add_spdif_dai() imx_add_spdif_dai(&imx6q_spdif_dai_data) + +#define imx6q_add_spdif_audio_device(pdata) imx_add_spdif_audio_device() + +#define imx6q_add_hdmi_soc() imx_add_hdmi_soc() +extern const struct imx_hdmi_soc_data imx6q_imx_hdmi_soc_dai_data __initconst; +#define imx6q_add_hdmi_soc_dai() \ + imx_add_hdmi_soc_dai(&imx6q_imx_hdmi_soc_dai_data) + +extern const struct imx_mipi_dsi_data imx6q_mipi_dsi_data __initconst; +#define imx6q_add_mipi_dsi(pdata) \ + imx_add_mipi_dsi(&imx6q_mipi_dsi_data, pdata) + +extern const struct imx_flexcan_data imx6q_flexcan_data[] __initconst; +#define imx6q_add_flexcan(id, pdata) \ + imx_add_flexcan(&imx6q_flexcan_data[id], pdata) +#define imx6q_add_flexcan0(pdata) imx6q_add_flexcan(0, pdata) +#define imx6q_add_flexcan1(pdata) imx6q_add_flexcan(1, pdata) + +extern const struct imx_mipi_csi2_data imx6q_mipi_csi2_data __initconst; +#define imx6q_add_mipi_csi2(pdata) \ + imx_add_mipi_csi2(&imx6q_mipi_csi2_data, pdata) + +extern const struct imx_perfmon_data imx6q_perfmon_data[] __initconst; +#define imx6q_add_perfmon(id) \ + imx_add_perfmon(&imx6q_perfmon_data[id]) + +extern const struct imx_mxc_mlb_data imx6q_mxc_mlb150_data __initconst; +#define imx6q_add_mlb150(pdata) \ + imx_add_mlb(pdata) + +extern const struct imx_pxp_data imx6dl_pxp_data __initconst; +#define imx6dl_add_imx_pxp() \ + imx_add_imx_pxp(&imx6dl_pxp_data) + +#define imx6dl_add_imx_pxp_client() \ + imx_add_imx_pxp_client() + +extern const struct imx_epdc_data imx6dl_epdc_data __initconst; +#define imx6dl_add_imx_epdc(pdata) \ + imx_add_imx_epdc(&imx6dl_epdc_data, pdata) diff --git a/arch/arm/mach-mvf/devices.c b/arch/arm/mach-mvf/devices.c new file mode 100644 index 000000000000..dcb41aba7110 --- /dev/null +++ b/arch/arm/mach-mvf/devices.c @@ -0,0 +1,85 @@ +/* + * based on arch/arm/mach-mx6/devices.c + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/ipu.h> +#include <linux/fb.h> +#include <linux/delay.h> +#include <linux/uio_driver.h> +#include <linux/iram_alloc.h> +#include <linux/fsl_devices.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/gpio.h> + +static struct mvf_gpio_port mvf_gpio_ports[] = { + { + .chip.label = "gpio-a", + .gbase = MVF_IO_ADDRESS(GPIOA_BASE_ADDR), + .pbase = MVF_IO_ADDRESS(MVF_PORT_A_BASE_ADDR), + .ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR), + .irq =MXC_INT_GPIOA, + .virtual_irq_start = MXC_GPIO_IRQ_START + }, + { + .chip.label = "gpio-b", + .gbase = MVF_IO_ADDRESS(GPIOB_BASE_ADDR), + .pbase = MVF_IO_ADDRESS(MVF_PORT_B_BASE_ADDR), + .ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR), + .irq = MXC_INT_GPIOB, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 + }, + { + .chip.label = "gpio-c", + .gbase = MVF_IO_ADDRESS(GPIOC_BASE_ADDR), + .pbase = MVF_IO_ADDRESS(MVF_PORT_C_BASE_ADDR), + .ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR), + .irq = MXC_INT_GPIOC, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 + }, + { + .chip.label = "gpio-d", + .gbase = MVF_IO_ADDRESS(GPIOD_BASE_ADDR), + .pbase = MVF_IO_ADDRESS(MVF_PORT_D_BASE_ADDR), + .ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR), + .irq = MXC_INT_GPIOD, + //.irq_high = MXC_INT_GPIO4_INT31_16_NUM, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 + }, + { + .chip.label = "gpio-e", + .gbase = MVF_IO_ADDRESS(GPIOE_BASE_ADDR), + .pbase = MVF_IO_ADDRESS(MVF_PORT_E_BASE_ADDR), + .ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR), + .irq = MXC_INT_GPIOE, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, +}; + +int mvf_register_gpios(void) +{ + /* 5 ports for MVF */ + return mvf_gpio_init(mvf_gpio_ports, 7); +} diff --git a/arch/arm/mach-mvf/dummy_gpio.c b/arch/arm/mach-mvf/dummy_gpio.c new file mode 100644 index 000000000000..006397bc96f6 --- /dev/null +++ b/arch/arm/mach-mvf/dummy_gpio.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/errno.h> +#include <linux/module.h> + +void gpio_uart_active(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_active); + +void gpio_uart_inactive(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_inactive); + +void gpio_gps_active(void) {} +EXPORT_SYMBOL(gpio_gps_active); + +void gpio_gps_inactive(void) {} +EXPORT_SYMBOL(gpio_gps_inactive); + +void config_uartdma_event(int port) {} +EXPORT_SYMBOL(config_uartdma_event); + +void gpio_spi_active(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_active); + +void gpio_spi_inactive(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_inactive); + +void gpio_owire_active(void) {} +EXPORT_SYMBOL(gpio_owire_active); + +void gpio_owire_inactive(void) {} +EXPORT_SYMBOL(gpio_owire_inactive); + +void gpio_i2c_active(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_active); + +void gpio_i2c_inactive(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_inactive); + +void gpio_i2c_hs_active(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_active); + +void gpio_i2c_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_inactive); + +void gpio_pmic_active(void) {} +EXPORT_SYMBOL(gpio_pmic_active); + +void gpio_activate_audio_ports(void) {} +EXPORT_SYMBOL(gpio_activate_audio_ports); + +void gpio_sdhc_active(int module) {} +EXPORT_SYMBOL(gpio_sdhc_active); + +void gpio_sdhc_inactive(int module) {} +EXPORT_SYMBOL(gpio_sdhc_inactive); + +void gpio_sensor_select(int sensor) {} + +void gpio_sensor_active(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_inactive(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_inactive); + +void gpio_ata_active(void) {} +EXPORT_SYMBOL(gpio_ata_active); + +void gpio_ata_inactive(void) {} +EXPORT_SYMBOL(gpio_ata_inactive); + +void gpio_nand_active(void) {} +EXPORT_SYMBOL(gpio_nand_active); + +void gpio_nand_inactive(void) {} +EXPORT_SYMBOL(gpio_nand_inactive); + +void gpio_keypad_active(void) {} +EXPORT_SYMBOL(gpio_keypad_active); + +void gpio_keypad_inactive(void) {} +EXPORT_SYMBOL(gpio_keypad_inactive); + +int gpio_usbotg_hs_active(void) +{ + return 0; +} +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +void gpio_fec_active(void) {} +EXPORT_SYMBOL(gpio_fec_active); + +void gpio_fec_inactive(void) {} +EXPORT_SYMBOL(gpio_fec_inactive); + +void gpio_spdif_active(void) {} +EXPORT_SYMBOL(gpio_spdif_active); + +void gpio_spdif_inactive(void) {} +EXPORT_SYMBOL(gpio_spdif_inactive); + +void gpio_mlb_active(void) {} +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) {} +EXPORT_SYMBOL(gpio_mlb_inactive); diff --git a/arch/arm/mach-mvf/headsmp.S b/arch/arm/mach-mvf/headsmp.S new file mode 100644 index 000000000000..9492d8dc1765 --- /dev/null +++ b/arch/arm/mach-mvf/headsmp.S @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + + __CPUINIT +ENTRY(mx6_secondary_startup) + + /* Invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 @ Invalidate I-Cache + /* Invalidate L1 D-cache */ + bl v7_invalidate_l1 + /* Set ARM working mode */ + msr cpsr_fsxc, #0xd3 + + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + ldr r1, = 0x020d8020 + add r1, r0, LSL#3 + + /*Clear SRC_GPR register */ + mov r0, #0 + str r0, [r1] + str r0, [r1, #0x4] + + /* Jump to secondary_startup */ + b secondary_startup + +ENDPROC(mx6_secondary_startup) diff --git a/arch/arm/mach-mvf/irq.c b/arch/arm/mach-mvf/irq.c new file mode 100644 index 000000000000..a9cdb4f916bb --- /dev/null +++ b/arch/arm/mach-mvf/irq.c @@ -0,0 +1,83 @@ +/* + * based on arch/arm/mach-mx6/irq.c + * + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <asm/hardware/gic.h> +#include <mach/hardware.h> +#ifdef CONFIG_CPU_FREQ_GOV_INTERACTIVE +#include <linux/cpufreq.h> +#endif + +int mvf_register_gpios(void); +unsigned int gpc_wake_irq[4]; +extern bool enable_wait_mode; + +static int mvf_gic_irq_set_wake(struct irq_data *d, unsigned int enable) +{ + if ((d->irq < MXC_INT_START) || (d->irq > MXC_INT_END)) { + printk(KERN_ERR "Invalid irq number!\n"); + return -EINVAL; + } + + if (enable) { + gpc_wake_irq[d->irq / 32 - 1] |= 1 << (d->irq % 32); + printk(KERN_INFO "add wake up source irq %d\n", d->irq); + } else { + printk(KERN_INFO "remove wake up source irq %d\n", d->irq); + gpc_wake_irq[d->irq / 32 - 1] &= ~(1 << (d->irq % 32)); + } + return 0; +} + +void mvf_init_irq(void) +{ + void __iomem *gpc_base = MVF_IO_ADDRESS(MVF_GPC_BASE_ADDR); + struct irq_desc *desc; + unsigned int i; + + /* start offset if private timer irq id, which is 29. + * ID table: + * Global timer, PPI -> ID27 + * A legacy nFIQ, PPI -> ID28 + * Private timer, PPI -> ID29 + * Watchdog timers, PPI -> ID30 + * A legacy nIRQ, PPI -> ID31 + */ + gic_init(0, 29, MVF_IO_ADDRESS(MVF_CA5_INTD_BASE_ADDR), + MVF_IO_ADDRESS(MVF_CA5_SCU_GIC_BASE_ADDR + 0x100)); //FIXME + +#if 0 + if (enable_wait_mode) { + /* Mask the always pending interrupts - HW bug. */ + __raw_writel(0x00400000, gpc_base + 0x0c); + __raw_writel(0x20000000, gpc_base + 0x10); + } +#endif + + for (i = MXC_INT_START; i <= MXC_INT_END; i++) { + desc = irq_to_desc(i); + desc->irq_data.chip->irq_set_wake = mvf_gic_irq_set_wake; + } + mvf_register_gpios(); +} diff --git a/arch/arm/mach-mvf/localtimer.c b/arch/arm/mach-mvf/localtimer.c new file mode 100644 index 000000000000..b8bfdaba0de1 --- /dev/null +++ b/arch/arm/mach-mvf/localtimer.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/clockchips.h> +#include <asm/smp_twd.h> +#include <asm/localtimer.h> +#include <mach/irqs.h> +#include <mach/hardware.h> + + +extern bool enable_wait_mode; +/* + * Setup the local clock events for a CPU. + */ +int __cpuinit local_timer_setup(struct clock_event_device *evt) +{ +#ifdef CONFIG_LOCAL_TIMERS + if (!enable_wait_mode) { + evt->irq = IRQ_LOCALTIMER; + twd_timer_setup(evt); + return 0; + } +#endif + return -1; +} diff --git a/arch/arm/mach-mvf/mm.c b/arch/arm/mach-mvf/mm.c new file mode 100644 index 000000000000..5c3f4cfdfc43 --- /dev/null +++ b/arch/arm/mach-mvf/mm.c @@ -0,0 +1,86 @@ +/* + * based on arch/arm/mach-mx6/mm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * Create static mapping between physical to virtual memory. + */ + +#include <linux/mm.h> +#include <linux/init.h> + +#include <asm/mach/map.h> +#include <mach/iomux-vmvf.h> + +#include <mach/hardware.h> +#include <mach/common.h> +//#include <mach/iomux-vf.h> +//#include <asm/hardware/cache-l2x0.h> + +/*! + * This structure defines the Faraday memory map. + */ +static struct map_desc mvf_io_desc[] __initdata = { + imx_map_entry(MVF, AIPS0, MT_DEVICE), + imx_map_entry(MVF, AIPS1, MT_DEVICE), +}; + +static void mvf_set_cpu_type(void) +{ + //FIXME +#ifdef CONFIG_SOC_VF6XX + mxc_set_cpu_type(MXC_CPU_VF6XX); +#endif +} + +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init mvf_map_io(void) +{ + iotable_init(mvf_io_desc, ARRAY_SIZE(mvf_io_desc)); + mxc_iomux_vmvf_init(MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MVF_IO_ADDRESS(MVF_WDOC_A5_BASE_ADDR)); + mvf_set_cpu_type(); + mxc_cpu_lp_set(WAIT_CLOCKED); +} + +#ifdef CONFIG_CACHE_L2X0 +int mxc_init_l2x0(void) +{ + unsigned int val; + + writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); + writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); + + val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val |= 0x40800000; + writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); + + l2x0_init(IO_ADDRESS(L2_BASE_ADDR), 0x0, ~0x00000000); + return 0; +} + + +arch_initcall(mxc_init_l2x0); +#endif diff --git a/arch/arm/mach-mvf/mx6_anatop_regulator.c b/arch/arm/mach-mvf/mx6_anatop_regulator.c new file mode 100644 index 000000000000..fd7e0c3fbdee --- /dev/null +++ b/arch/arm/mach-mvf/mx6_anatop_regulator.c @@ -0,0 +1,325 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * mx6_anatop_regulator.c -- i.MX6 Driver for Anatop regulators + */ +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/regulator/anatop-regulator.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/gpio.h> + +#include "crm_regs.h" +#include "regs-anadig.h" + +extern struct platform_device sgtl5000_vdda_reg_devices; +extern struct platform_device sgtl5000_vddio_reg_devices; +extern struct platform_device sgtl5000_vddd_reg_devices; + +static int get_voltage(struct anatop_regulator *sreg) +{ + int uv; + struct anatop_regulator_data *rdata = sreg->rdata; + + if (sreg->rdata->control_reg) { + u32 val = (__raw_readl(rdata->control_reg) >> + rdata->vol_bit_shift) & rdata->vol_bit_mask; + uv = rdata->min_voltage + (val - rdata->min_bit_val) * 25000; + pr_debug("vddio = %d, val=%u\n", uv, val); + return uv; + } else { + pr_debug("Regulator not supported.\n"); + return -ENOTSUPP; + } +} + +static int set_voltage(struct anatop_regulator *sreg, int uv) +{ + u32 val, reg; + + pr_debug("%s: uv %d, min %d, max %d\n", __func__, + uv, sreg->rdata->min_voltage, sreg->rdata->max_voltage); + + if (uv < sreg->rdata->min_voltage || uv > sreg->rdata->max_voltage) + return -EINVAL; + + if (sreg->rdata->control_reg) { + val = sreg->rdata->min_bit_val + + (uv - sreg->rdata->min_voltage) / 25000; + + reg = (__raw_readl(sreg->rdata->control_reg) & + ~(sreg->rdata->vol_bit_mask << + sreg->rdata->vol_bit_shift)); + pr_debug("%s: calculated val %d\n", __func__, val); + __raw_writel((val << sreg->rdata->vol_bit_shift) | reg, + sreg->rdata->control_reg); + return 0; + } else { + pr_debug("Regulator not supported.\n"); + return -ENOTSUPP; + } +} + +static int enable(struct anatop_regulator *sreg) +{ + return 0; +} + +static int disable(struct anatop_regulator *sreg) +{ + return 0; +} + +static int is_enabled(struct anatop_regulator *sreg) +{ + return 1; +} + +static struct anatop_regulator_data vddpu_data = { + .name = "vddpu", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_CORE), + .vol_bit_shift = 9, + .vol_bit_mask = 0x1F, + .min_bit_val = 1, + .min_voltage = 725000, + .max_voltage = 1300000, +}; + +static struct anatop_regulator_data vddcore_data = { + .name = "vddcore", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_CORE), + .vol_bit_shift = 0, + .vol_bit_mask = 0x1F, + .min_bit_val = 1, + .min_voltage = 725000, + .max_voltage = 1300000, +}; + +static struct anatop_regulator_data vddsoc_data = { + .name = "vddsoc", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_CORE), + .vol_bit_shift = 18, + .vol_bit_mask = 0x1F, + .min_bit_val = 1, + .min_voltage = 725000, + .max_voltage = 1300000, +}; + +static struct anatop_regulator_data vdd2p5_data = { + .name = "vdd2p5", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_2P5), + .vol_bit_shift = 8, + .vol_bit_mask = 0x1F, + .min_bit_val = 0, + .min_voltage = 2000000, + .max_voltage = 2775000, +}; + +static struct anatop_regulator_data vdd1p1_data = { + .name = "vdd1p1", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_1P1), + .vol_bit_shift = 8, + .vol_bit_mask = 0x1F, + .min_bit_val = 4, + .min_voltage = 800000, + .max_voltage = 1400000, +}; + +static struct anatop_regulator_data vdd3p0_data = { + .name = "vdd3p0", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_3P0), + .vol_bit_shift = 8, + .vol_bit_mask = 0x1F, + .min_bit_val = 7, + .min_voltage = 2800000, + .max_voltage = 3150000, +}; + +/* CPU */ +static struct regulator_consumer_supply vddcore_consumers[] = { + { + .supply = "cpu_vddgp", + } +}; + +static struct regulator_init_data vddpu_init = { + .constraints = { + .name = "vddpu", + .min_uV = 725000, + .max_uV = 1300000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .always_on = 1, + }, + .num_consumer_supplies = 0, + .consumer_supplies = NULL, +}; + +static struct regulator_init_data vddcore_init = { + .constraints = { + .name = "vddcore", + .min_uV = 725000, + .max_uV = 1300000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vddcore_consumers), + .consumer_supplies = &vddcore_consumers[0], +}; + +static struct regulator_init_data vddsoc_init = { + .constraints = { + .name = "vddsoc", + .min_uV = 725000, + .max_uV = 1300000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .always_on = 1, + }, + .num_consumer_supplies = 0, + .consumer_supplies = NULL, +}; + +static struct regulator_init_data vdd2p5_init = { + .constraints = { + .name = "vdd2p5", + .min_uV = 2000000, + .max_uV = 2775000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .always_on = 1, + }, + .num_consumer_supplies = 0, + .consumer_supplies = NULL, +}; + + +static struct regulator_init_data vdd1p1_init = { + .constraints = { + .name = "vdd1p1", + .min_uV = 800000, + .max_uV = 1400000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + }, + .num_consumer_supplies = 0, + .consumer_supplies = NULL, +}; + + +static struct regulator_init_data vdd3p0_init = { + .constraints = { + .name = "vdd3p0", + .min_uV = 2800000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .always_on = 1, + }, + .num_consumer_supplies = 0, + .consumer_supplies = NULL, +}; + +static struct anatop_regulator vddpu_reg = { + .rdata = &vddpu_data, +}; + +static struct anatop_regulator vddcore_reg = { + .rdata = &vddcore_data, +}; + +static struct anatop_regulator vddsoc_reg = { + .rdata = &vddsoc_data, +}; + +static struct anatop_regulator vdd2p5_reg = { + .rdata = &vdd2p5_data, +}; + +static struct anatop_regulator vdd1p1_reg = { + .rdata = &vdd1p1_data, +}; + +static struct anatop_regulator vdd3p0_reg = { + .rdata = &vdd3p0_data, +}; + +static int __init regulators_init(void) +{ + anatop_register_regulator(&vddpu_reg, ANATOP_VDDPU, &vddpu_init); + anatop_register_regulator(&vddcore_reg, ANATOP_VDDCORE, &vddcore_init); + anatop_register_regulator(&vddsoc_reg, ANATOP_VDDSOC, &vddsoc_init); + anatop_register_regulator(&vdd2p5_reg, ANATOP_VDD2P5, &vdd2p5_init); + anatop_register_regulator(&vdd1p1_reg, ANATOP_VDD1P1, &vdd1p1_init); + anatop_register_regulator(&vdd3p0_reg, ANATOP_VDD3P0, &vdd3p0_init); + + return 0; +} +postcore_initcall(regulators_init); diff --git a/arch/arm/mach-mvf/mx6_fec.c b/arch/arm/mach-mvf/mx6_fec.c new file mode 100644 index 000000000000..b2aa45b3c510 --- /dev/null +++ b/arch/arm/mach-mvf/mx6_fec.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include <linux/fec.h> +#include <linux/etherdevice.h> + +#include <mach/common.h> +#include <mach/hardware.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include "devices-imx6q.h" + +#define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10) + +static int fec_get_mac_addr(unsigned char *mac) +{ + unsigned int value; + + value = readl(MX6_IO_ADDRESS(OCOTP_BASE_ADDR) + HW_OCOTP_MACn(0)); + mac[5] = value & 0xff; + mac[4] = (value >> 8) & 0xff; + mac[3] = (value >> 16) & 0xff; + mac[2] = (value >> 24) & 0xff; + value = readl(MX6_IO_ADDRESS(OCOTP_BASE_ADDR) + HW_OCOTP_MACn(1)); + mac[1] = value & 0xff; + mac[0] = (value >> 8) & 0xff; + + return 0; +} + +void __init imx6_init_fec(struct fec_platform_data fec_data) +{ + fec_get_mac_addr(fec_data.mac); + if (!is_valid_ether_addr(fec_data.mac)) + random_ether_addr(fec_data.mac); + + imx6q_add_fec(&fec_data); +} diff --git a/arch/arm/mach-mvf/mx6_wfi.S b/arch/arm/mach-mvf/mx6_wfi.S new file mode 100644 index 000000000000..3c6310263b38 --- /dev/null +++ b/arch/arm/mach-mvf/mx6_wfi.S @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/linkage.h> + +/* + * mx6_wait + * + * Idle the processor (eg, wait for interrupt). + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx6_wait) + + dsb + + wfi + + isb + isb + + mov pc, lr + + .type mx6_do_wait, #object +ENTRY(mx6_do_wait) + .word mx6_wait + .size mx6_wait, . - mx6_wait diff --git a/arch/arm/mach-mvf/mx6q_suspend.S b/arch/arm/mach-mvf/mx6q_suspend.S new file mode 100644 index 000000000000..29d5a76e86ce --- /dev/null +++ b/arch/arm/mach-mvf/mx6q_suspend.S @@ -0,0 +1,663 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/linkage.h> +#include <mach/hardware.h> +#include <asm/memory.h> +#include <asm/hardware/cache-l2x0.h> +#include "src-reg.h" + +#define ARM_CTRL_DCACHE (1 << 2) +#define ARM_CTRL_ICACHE (1 << 12) +#define ARM_AUXCR_L2EN (1 << 1) +#define TTRBIT_MASK 0xffffc000 +#define TABLE_INDEX_MASK 0xfff00000 +#define TABLE_ENTRY 0x00000c02 +#define CACHE_DISABLE_MASK 0xffffe7fb +#define MMDC_MAPSR_OFFSET 0x404 +#define MMDC_MAPSR_PSS (1 << 4) +#define MMDC_MAPSR_PSD (1 << 0) +#define IRAM_SUSPEND_SIZE (1 << 12) + +/************************************************************* +mx6q_suspend: + +Suspend the processor (eg, wait for interrupt). +Set the DDR into Self Refresh +IRQs are already disabled. + +The following code contain both standby and +dormant mode for MX6, decided by the parameter +passed in r0: +see define in include/linux/suspend.h +1 -> cpu enter stop mode; +3 -> cpu enter dormant mode. +r1: iram_paddr +r2: suspend_iram_base +*************************************************************/ + .macro ddr_io_save + + ldr r4, [r1, #0x5ac] /* DRAM_DQM0 */ + ldr r5, [r1, #0x5b4] /* DRAM_DQM1 */ + ldr r6, [r1, #0x528] /* DRAM_DQM2 */ + ldr r7, [r1, #0x520] /* DRAM_DQM3 */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x514] /* DRAM_DQM4 */ + ldr r5, [r1, #0x510] /* DRAM_DQM5 */ + ldr r6, [r1, #0x5bc] /* DRAM_DQM6 */ + ldr r7, [r1, #0x5c4] /* DRAM_DQM7 */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x56c] /* DRAM_CAS */ + ldr r5, [r1, #0x578] /* DRAM_RAS */ + ldr r6, [r1, #0x588] /* DRAM_SDCLK_0 */ + ldr r7, [r1, #0x594] /* DRAM_SDCLK_1 */ + stmfd r0!, {r4-r7} + + ldr r5, [r1, #0x750] /* DDRMODE_CTL */ + ldr r6, [r1, #0x774] /* DDRMODE */ + stmfd r0!, {r5-r6} + + ldr r4, [r1, #0x5a8] /* DRAM_SDQS0 */ + ldr r5, [r1, #0x5b0] /* DRAM_SDQS1 */ + ldr r6, [r1, #0x524] /* DRAM_SDQS2 */ + ldr r7, [r1, #0x51c] /* DRAM_SDQS3 */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x518] /* DRAM_SDQS4 */ + ldr r5, [r1, #0x50c] /* DRAM_SDQS5 */ + ldr r6, [r1, #0x5b8] /* DRAM_SDQS6 */ + ldr r7, [r1, #0x5c0] /* DRAM_SDQS7 */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x784] /* GPR_B0DS */ + ldr r5, [r1, #0x788] /* GPR_B1DS */ + ldr r6, [r1, #0x794] /* GPR_B2DS */ + ldr r7, [r1, #0x79c] /* GPR_B3DS */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x7a0] /* GPR_B4DS */ + ldr r5, [r1, #0x7a4] /* GPR_B5DS */ + ldr r6, [r1, #0x7a8] /* GPR_B6DS */ + ldr r7, [r1, #0x748] /* GPR_B7DS */ + stmfd r0!, {r4-r7} + + ldr r5, [r1, #0x74c] /* GPR_ADDS*/ + ldr r6, [r1, #0x59c] /* DRAM_SODT0*/ + ldr r7, [r1, #0x5a0] /* DRAM_SODT1*/ + stmfd r0!, {r5-r7} + + .endm + + .macro ddr_io_restore + + ldmea r0!, {r4-r7} + str r4, [r1, #0x5ac] /* DRAM_DQM0 */ + str r5, [r1, #0x5b4] /* DRAM_DQM1 */ + str r6, [r1, #0x528] /* DRAM_DQM2 */ + str r7, [r1, #0x520] /* DRAM_DQM3 */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x514] /* DRAM_DQM4 */ + str r5, [r1, #0x510] /* DRAM_DQM5 */ + str r6, [r1, #0x5bc] /* DRAM_DQM6 */ + str r7, [r1, #0x5c4] /* DRAM_DQM7 */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x56c] /* DRAM_CAS */ + str r5, [r1, #0x578] /* DRAM_RAS */ + str r6, [r1, #0x588] /* DRAM_SDCLK_0 */ + str r7, [r1, #0x594] /* DRAM_SDCLK_1 */ + + ldmea r0!, {r5-r6} + str r5, [r1, #0x750] /* DDRMODE_CTL */ + str r6, [r1, #0x774] /* DDRMODE */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x5a8] /* DRAM_SDQS0 */ + str r5, [r1, #0x5b0] /* DRAM_SDQS1 */ + str r6, [r1, #0x524] /* DRAM_SDQS2 */ + str r7, [r1, #0x51c] /* DRAM_SDQS3 */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x518] /* DRAM_SDQS4 */ + str r5, [r1, #0x50c] /* DRAM_SDQS5 */ + str r6, [r1, #0x5b8] /* DRAM_SDQS6 */ + str r7, [r1, #0x5c0] /* DRAM_SDQS7 */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x784] /* GPR_B0DS */ + str r5, [r1, #0x788] /* GPR_B1DS */ + str r6, [r1, #0x794] /* GPR_B2DS */ + str r7, [r1, #0x79c] /* GPR_B3DS */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x7a0] /* GPR_B4DS */ + str r5, [r1, #0x7a4] /* GPR_B5DS */ + str r6, [r1, #0x7a8] /* GPR_B6DS */ + str r7, [r1, #0x748] /* GPR_B7DS */ + + ldmea r0!, {r5-r7} + str r5, [r1, #0x74c] /* GPR_ADDS*/ + str r6, [r1, #0x59c] /* DRAM_SODT0*/ + str r7, [r1, #0x5a0] /* DRAM_SODT1*/ + + .endm + + .macro ddr_io_set_lpm + + mov r0, #0 + str r0, [r1, #0x5ac] /* DRAM_DQM0 */ + str r0, [r1, #0x5b4] /* DRAM_DQM1 */ + str r0, [r1, #0x528] /* DRAM_DQM2 */ + str r0, [r1, #0x520] /* DRAM_DQM3 */ + + str r0, [r1, #0x514] /* DRAM_DQM4 */ + str r0, [r1, #0x510] /* DRAM_DQM5 */ + str r0, [r1, #0x5bc] /* DRAM_DQM6 */ + str r0, [r1, #0x5c4] /* DRAM_DQM7 */ + + str r0, [r1, #0x56c] /* DRAM_CAS */ + str r0, [r1, #0x578] /* DRAM_RAS */ + str r0, [r1, #0x588] /* DRAM_SDCLK_0 */ + str r0, [r1, #0x594] /* DRAM_SDCLK_1 */ + + str r0, [r1, #0x750] /* DDRMODE_CTL */ + str r0, [r1, #0x774] /* DDRMODE */ + + str r0, [r1, #0x5a8] /* DRAM_SDQS0 */ + str r0, [r1, #0x5b0] /* DRAM_SDQS1 */ + str r0, [r1, #0x524] /* DRAM_SDQS2 */ + str r0, [r1, #0x51c] /* DRAM_SDQS3 */ + + str r0, [r1, #0x518] /* DRAM_SDQS4 */ + str r0, [r1, #0x50c] /* DRAM_SDQS5 */ + str r0, [r1, #0x5b8] /* DRAM_SDQS6 */ + str r0, [r1, #0x5c0] /* DRAM_SDQS7 */ + + str r0, [r1, #0x784] /* GPR_B0DS */ + str r0, [r1, #0x788] /* GPR_B1DS */ + str r0, [r1, #0x794] /* GPR_B2DS */ + str r0, [r1, #0x79c] /* GPR_B3DS */ + + str r0, [r1, #0x7a0] /* GPR_B4DS */ + str r0, [r1, #0x7a4] /* GPR_B5DS */ + str r0, [r1, #0x7a8] /* GPR_B6DS */ + str r0, [r1, #0x748] /* GPR_B7DS */ + + str r0, [r1, #0x74c] /* GPR_ADDS*/ + str r0, [r1, #0x59c] /* DRAM_SODT0*/ + str r0, [r1, #0x5a0] /* DRAM_SODT1*/ + + .endm + +ENTRY(mx6q_suspend) + stmfd sp!, {r0-r12} @ Save registers +/************************************************************* +suspend mode entry +*************************************************************/ + + cmp r0, #0x1 + bne dormant /* dormant mode */ + + dsb + wfi + + nop + nop + nop + nop + /* Due to the L2 cache errata(TKT065875) + , need to wait at least 170ns, each IO read + takes about 76ns, but the actual wait time + to make system more stable is about 380ns */ + ldr r0, =SRC_BASE_ADDR + add r0, r0, #PERIPBASE_VIRT + ldr r1, [r0] + ldr r1, [r0, #0x4] + ldr r1, [r0, #0x8] + ldr r1, [r0, #0xc] + ldr r1, [r0, #0x10] +/*********************************************************** +never run to here +************************************************************/ + b out /* exit standby */ + +/************************************************************ +dormant entry, data save in stack, save sp in the src_gpr2 +************************************************************/ +dormant: + mov r3, r1 + mov r0, r1 + add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */ + ldr r4, =SRC_BASE_ADDR + add r4, r4, #PERIPBASE_VIRT + str r0, [r4, #SRC_GPR2_OFFSET] /* set src_gpr2 */ +/************************************************************ +saved register and context as below: + ddr_iomux set + sp + spsr + lr + CPACR + TTBR0 + TTBR1 + TTBCR + DACR + PRRR + NMRR + ACTLR + Context ID + User r/w thread ID + Secure or NS VBAR + CPSR + SCTLR +************************************************************/ +ddr_iomux_save: + /* save mmdc iomux setting, stack is from the tail of + iram_suspend base */ + + mov r0, r2 /* get suspend_iram_base */ + add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */ + ldr r1, =MX6Q_IOMUXC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + + ddr_io_save + + mov r4, sp @ Store sp + mrs r5, spsr @ Store spsr + mov r6, lr @ Store lr + stmfd r0!, {r4-r6} + + /* c1 and c2 registers */ + mrc p15, 0, r4, c1, c0, 2 @ CPACR + mrc p15, 0, r5, c2, c0, 0 @ TTBR0 + mrc p15, 0, r6, c2, c0, 1 @ TTBR1 + mrc p15, 0, r7, c2, c0, 2 @ TTBCR + stmfd r0!, {r4-r7} + + /* c3 and c10 registers */ + mrc p15, 0, r4, c3, c0, 0 @ DACR + mrc p15, 0, r5, c10, c2, 0 @ PRRR + mrc p15, 0, r6, c10, c2, 1 @ NMRR + mrc p15, 0, r7, c1, c0, 1 @ ACTLR + stmfd r0!,{r4-r7} + + /* c12, c13 and CPSR registers */ + mrc p15, 0, r4, c13, c0, 1 @ Context ID + mrc p15, 0, r5, c13, c0, 2 @ User r/w thread ID + mrc p15, 0, r6, c12, c0, 0 @ Secure or NS VBAR + mrs r7, cpsr @ Store CPSR + stmfd r0!, {r4-r7} + + /* c1 control register */ + mrc p15, 0, r4, c1, c0, 0 @ SCTLR + stmfd r0!, {r4} + +#ifdef CONFIG_CACHE_L2X0 + ldr r2, =L2_BASE_ADDR + add r2, r2, #PERIPBASE_VIRT + + ldr r4, [r2, #L2X0_CTRL] + ldr r5, [r2, #L2X0_AUX_CTRL] + ldr r6, [r2, #L2X0_TAG_LATENCY_CTRL] + ldr r7, [r2, #L2X0_DATA_LATENCY_CTRL] + stmfd r0!, {r4-r7} + + ldr r4, [r2, #L2X0_PREFETCH_CTRL] + ldr r5, [r2, #L2X0_POWER_CTRL] + stmfd r0!, {r4-r5} +#endif + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + push {r0-r12, lr} + ldr r0, =v7_flush_dcache_all + mov lr, pc + mov pc, r0 + pop {r0-r12, lr} + + /* + * Clear the SCTLR.C bit to prevent further data cache + * allocation. Clearing SCTLR.C would make all the data accesses + * strongly ordered and would not hit the cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(1 << 2) @ Disable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + /* + * Invalidate L1 data cache. Even though only invalidate is + * necessary exported flush API is used here. Doing clean + * on already clean cache would be almost NOP. + */ + push {r0-r12, lr} + ldr r0, =v7_flush_dcache_all + mov lr, pc + mov pc, r0 + pop {r0-r12, lr} + + /* + * Execute an ISB instruction to ensure that all of the + * CP15 register changes have been committed. + */ + isb + + /* + * Execute a barrier instruction to ensure that all cache, + * TLB and branch predictor maintenance operations issued + * by any CPU in the cluster have completed. + */ + dsb + dmb + + /* Clean L2 cache to write the dirty data into DRAM to make + sure the data alignment between DRAM and L2 cache. + */ +#ifdef CONFIG_CACHE_L2X0 + /* Clean L2 cache here */ + ldr r1, =L2_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + /* Make way to 0xFFFF 16 ways */ + mov r0, #0x10000 + sub r0, r0, #0x1 + /* 0x7BC is L2X0_CLEAN_WAY */ + mov r4, #0x700 + orr r4, #0xBC + str r0, [r1, r4] +wait: + ldr r2, [r1, r4] + ands r2, r2, r0 + bne wait +l2x0_sync: + mov r2, #0x0 + /* 0x730 is L2X0_CACHE_SYNC */ + mov r4, #0x700 + orr r4, #0x30 + str r2, [r1, r4] +sync: + ldr r2, [r1, r4] + ands r2, r2, #0x1 + bne sync +#endif +/**************************************************************** +set ddr iomux to low power mode +****************************************************************/ + ldr r1, =MMDC_P0_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1, #MMDC_MAPSR_OFFSET] + bic r0, #MMDC_MAPSR_PSD /* enable lpm */ + str r0, [r1, #MMDC_MAPSR_OFFSET] +refresh: + ldr r0, [r1, #MMDC_MAPSR_OFFSET] /* MMDC_MAPSR */ + and r0, r0, #MMDC_MAPSR_PSS /* PSS bit */ + cmp r0, #0 + beq refresh + + /* set mmdc iomux to low power mode */ + ldr r1, =MX6Q_IOMUXC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + + ddr_io_set_lpm +/**************************************************************** +save resume pointer into SRC_GPR1 +****************************************************************/ + ldr r0, =mx6q_suspend + ldr r1, =resume + sub r1, r1, r0 + add r3, r3, r1 + ldr r1, =SRC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + str r3, [r1, #SRC_GPR1_OFFSET] +/**************************************************************** +execute a wfi instruction to let SOC go into stop mode. +****************************************************************/ + wfi + + nop + nop + nop + nop + +/**************************************************************** +if go here, means there is a wakeup irq pending, we should resume +system immediately. +****************************************************************/ + mov r0, r2 /* get suspend_iram_base */ + add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */ + + ldr r1, =MX6Q_IOMUXC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + + ddr_io_restore + + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #(1 << 2) @ Enable the C bit + mcr p15, 0, r1, c1, c0, 0 + + b out /* exit standby */ + +/**************************************************************** +when SOC exit stop mode, arm core restart from here, currently +are running with MMU off. +****************************************************************/ +resume: + /* Invalidate L1 I-cache first */ + mov r1, #0x0 + mcr p15, 0, r1, c7, c5, 0 @ Invalidate I-Cache + ldr r0, =SRC_BASE_ADDR + str r1, [r0, #SRC_GPR1_OFFSET] /* clear SRC_GPR1 */ + ldr r0, [r0, #SRC_GPR2_OFFSET] + + ldr r1, =MX6Q_IOMUXC_BASE_ADDR + ddr_io_restore + + /* Restore cp15 registers */ + ldmea r0!, {r4-r6} + mov sp, r4 + msr spsr_cxsf, r5 @ Restore spsr + mov lr, r6 @ Restore lr + + /* c1 and c2 registers */ + ldmea r0!, {r4-r7} + mcr p15, 0, r4, c1, c0, 2 @ CPACR + mcr p15, 0, r5, c2, c0, 0 @ TTBR0 + mcr p15, 0, r6, c2, c0, 1 @ TTBR1 + mcr p15, 0, r7, c2, c0, 2 @ TTBCR + + /* c3 and c10 registers */ + ldmea r0!,{r4-r7} + mcr p15, 0, r4, c3, c0, 0 @ DACR + mcr p15, 0, r5, c10, c2, 0 @ PRRR + mcr p15, 0, r6, c10, c2, 1 @ NMRR + mcr p15, 0, r7, c1, c0, 1 @ ACTLR + + /* c12, c13 and CPSR registers */ + ldmea r0!,{r4-r7} + mcr p15, 0, r4, c13, c0, 1 @ Context ID + mcr p15, 0, r5, c13, c0, 2 @ User r/w thread ID + mrc p15, 0, r6, c12, c0, 0 @ Secure or NS VBAR + msr cpsr, r7 @ store cpsr + + /* + * Enabling MMU here. Page entry needs to be altered + * to create temporary 1:1 map and then resore the entry + * ones MMU is enabled + */ + mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl + and r7, #0x7 @ Extract N (0:2) to decide + cmp r7, #0x0 @ TTBR0/TTBR1 + beq use_ttbr0 +ttbr_error: + b ttbr_error @ Only N = 0 supported +use_ttbr0: + mrc p15, 0, r2, c2, c0, 0 @ Read TTBR0 + ldr r5, =TTRBIT_MASK + and r2, r5 + mov r4, pc + ldr r5, =TABLE_INDEX_MASK + and r4, r5 @ r4 = 31 to 20 bits of pc + ldr r1, =TABLE_ENTRY + add r1, r1, r4 @ r1 has value of table entry + lsr r4, #18 @ Address of table entry + add r2, r4 @ r2 - location to be modified + + /* Storing previous entry of location being modified */ + ldr r4, [r2] + mov r9, r4 + str r1, [r2] + + /* + * Storing address of entry being modified + * It will be restored after enabling MMU + */ + mov r10, r2 + + mov r1, #0 + mcr p15, 0, r1, c7, c5, 4 @ Flush prefetch buffer + mcr p15, 0, r1, c7, c5, 6 @ Invalidate BTB + mcr p15, 0, r1, c8, c5, 0 @ Invalidate ITLB + mcr p15, 0, r1, c8, c6, 0 @ Invalidate DTLB + + /* + * Restore control register but don't enable Data caches here. + * Caches will be enabled after restoring MMU table entry. + */ + ldmea r0!, {r4} + mov r11, r4 + ldr r2, =CACHE_DISABLE_MASK + and r4, r4, r2 + mcr p15, 0, r4, c1, c0, 0 + isb + dsb + ldr r1, =mmu_on_label + bx r1 +mmu_on_label: + mov r8, lr + push {r0} + + /* Set up the per-CPU stacks */ + bl cpu_init + pop {r0} + +#ifdef CONFIG_CACHE_L2X0 + ldr r2, =L2_BASE_ADDR + add r2, r2, #PERIPBASE_VIRT + + ldmea r0!, {r4-r7} + /* L2 will be enabled after L1 is enabled */ + mov r4, #0x0 + str r4, [r2, #L2X0_CTRL] + str r5, [r2, #L2X0_AUX_CTRL] + str r6, [r2, #L2X0_TAG_LATENCY_CTRL] + str r7, [r2, #L2X0_DATA_LATENCY_CTRL] + + ldmea r0!, {r4-r5} + str r4, [r2, #L2X0_PREFETCH_CTRL] + str r5, [r2, #L2X0_POWER_CTRL] +#endif + /* + * Restore the MMU table entry that was modified for + * enabling MMU. + */ + ldr r4, =PAGE_OFFSET + ldr r5, =MX6_PHYS_OFFSET + sub r4, r4, r5 + add r4, r4, r10 + str r9, [r4] + + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 @ flush TLB and issue barriers + mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB + mcr p15, 0, r0, c8, c5, 0 @ Invalidate ITLB + mcr p15, 0, r0, c8, c6, 0 @ Invalidate DTLB + dsb + isb + +/****************************************************************** +invalidate l1 dcache, r0-r4, r6, r7 used +******************************************************************/ + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: + sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: + subs r3, r3, #1 @ Temp-- + mov r7, r3, lsl r1 + mov r6, r2, lsl r0 + orr r7, r7, r6 + mcr p15, 0, r7, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + +/************************************************************ +restore control register to enable cache +************************************************************/ + mov r0, r11 + mcr p15, 0, r0, c1, c0, 0 @ with caches enabled. + dsb + isb + +#ifdef CONFIG_CACHE_L2X0 + /* Enable L2 cache here */ + ldr r2, =L2_BASE_ADDR + add r2, r2, #PERIPBASE_VIRT + mov r4, #0x1 + str r4, [r2, #L2X0_CTRL] +#endif +/*********************************************************** +return back to mx6_suspend_enter for dormant +***********************************************************/ + mov lr, r8 + ldmfd sp!, {r0-r12} + mov pc, lr +/************************************************ +return back to mx6_suspend_enter for suspend +*************************************************/ +out: + ldmfd sp!, {r0-r12} + mov pc, lr + + .equ va2pa_offset, (PAGE_OFFSET - MX6_PHYS_OFFSET) + .type mx6q_do_suspend, #object +ENTRY(mx6q_do_suspend) + .word mx6q_suspend + .size mx6q_suspend, . - mx6q_suspend diff --git a/arch/arm/mach-mvf/pcie.c b/arch/arm/mach-mvf/pcie.c new file mode 100644 index 000000000000..9959bbceaa4d --- /dev/null +++ b/arch/arm/mach-mvf/pcie.c @@ -0,0 +1,484 @@ +/* + * arch/arm/mach-mx6/pcie.c + * + * PCIe host controller driver for IMX6 SOCs + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Bits taken from arch/arm/mach-dove/pcie.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <asm/sizes.h> + +#include "crm_regs.h" + +/* Register Definitions */ +#define PRT_LOG_R_BaseAddress 0x700 + +/* Register DB_R0 */ +/* Debug Register 0 */ +#define DB_R0 (PRT_LOG_R_BaseAddress + 0x28) +#define DB_R0_RegisterSize 32 +#define DB_R0_RegisterResetValue 0x0 +#define DB_R0_RegisterResetMask 0xFFFFFFFF +/* End of Register Definition for DB_R0 */ + +/* Register DB_R1 */ +/* Debug Register 1 */ +#define DB_R1 (PRT_LOG_R_BaseAddress + 0x2c) +#define DB_R1_RegisterSize 32 +#define DB_R1_RegisterResetValue 0x0 +#define DB_R1_RegisterResetMask 0xFFFFFFFF +/* End of Register Definition for DB_R1 */ + +#define ATU_R_BaseAddress 0x900 +#define ATU_VIEWPORT_R (ATU_R_BaseAddress + 0x0) +#define ATU_REGION_CTRL1_R (ATU_R_BaseAddress + 0x4) +#define ATU_REGION_CTRL2_R (ATU_R_BaseAddress + 0x8) +#define ATU_REGION_LOWBASE_R (ATU_R_BaseAddress + 0xC) +#define ATU_REGION_UPBASE_R (ATU_R_BaseAddress + 0x10) +#define ATU_REGION_LIMIT_ADDR_R (ATU_R_BaseAddress + 0x14) +#define ATU_REGION_LOW_TRGT_ADDR_R (ATU_R_BaseAddress + 0x18) +#define ATU_REGION_UP_TRGT_ADDR_R (ATU_R_BaseAddress + 0x1C) + +/* GPR1: iomuxc_gpr1_pcie_ref_clk_en(iomuxc_gpr1[16]) */ +#define iomuxc_gpr1_pcie_ref_clk_en (1 << 16) +/* GPR1: iomuxc_gpr1_test_powerdown(iomuxc_gpr1_18) */ +#define iomuxc_gpr1_test_powerdown (1 << 18) + +/* GPR12: iomuxc_gpr12_los_level(iomuxc_gpr12[8:4]) */ +#define iomuxc_gpr12_los_level (0x1F << 4) +/* GPR12: iomuxc_gpr12_app_ltssm_enable(iomuxc_gpr12[10]) */ +#define iomuxc_gpr12_app_ltssm_enable (1 << 10) +/* GPR12: iomuxc_gpr12_device_type(iomuxc_gpr12[15:12]) */ +#define iomuxc_gpr12_device_type (0xF << 12) + +/* GPR8: iomuxc_gpr8_tx_deemph_gen1(iomuxc_gpr8[5:0]) */ +#define iomuxc_gpr8_tx_deemph_gen1 (0x3F << 0) +/* GPR8: iomuxc_gpr8_tx_deemph_gen2_3p5db(iomuxc_gpr8[11:6]) */ +#define iomuxc_gpr8_tx_deemph_gen2_3p5db (0x3F << 6) +/* GPR8: iomuxc_gpr8_tx_deemph_gen2_6db(iomuxc_gpr8[17:12]) */ +#define iomuxc_gpr8_tx_deemph_gen2_6db (0x3F << 12) +/* GPR8: iomuxc_gpr8_tx_swing_full(iomuxc_gpr8[24:18]) */ +#define iomuxc_gpr8_tx_swing_full (0x7F << 18) +/* GPR8: iomuxc_gpr8_tx_swing_low(iomuxc_gpr8[31:25]) */ +#define iomuxc_gpr8_tx_swing_low (0x7F << 25) + +/* End of Register Definitions */ + +#define PCIE_DBI_BASE_ADDR (PCIE_ARB_END_ADDR - SZ_16K + 1) + +#define PCIE_CONF_BUS(b) (((b) & 0xFF) << 16) +#define PCIE_CONF_DEV(d) (((d) & 0x1F) << 11) +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) + +enum { + MemRdWr = 0, + MemRdLk = 1, + IORdWr = 2, + CfgRdWr0 = 4, + CfgRdWr1 = 5 +}; + +struct imx_pcie_port { + u8 index; + u8 root_bus_nr; + void __iomem *base; + void __iomem *dbi_base; + spinlock_t conf_lock; + + char io_space_name[16]; + char mem_space_name[16]; + + struct resource res[2]; +}; + +static struct imx_pcie_port imx_pcie_port[1]; +static int num_pcie_ports; + +/* IMX PCIE GPR configure routines */ +static inline void imx_pcie_clrset(u32 mask, u32 val, void __iomem *addr) +{ + writel(((readl(addr) & ~mask) | (val & mask)), addr); +} + +static struct imx_pcie_port *bus_to_port(int bus) +{ + int i; + + for (i = num_pcie_ports - 1; i >= 0; i--) { + int rbus = imx_pcie_port[i].root_bus_nr; + if (rbus != -1 && rbus <= bus) + break; + } + + return i >= 0 ? imx_pcie_port + i : NULL; +} + +static int __init imx_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct imx_pcie_port *pp; + + if (nr >= num_pcie_ports) + return 0; + + pp = &imx_pcie_port[nr]; + pp->root_bus_nr = sys->busnr; + + /* + * IORESOURCE_IO + */ + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d I/O", pp->index); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + if (pp->index == 0) { + pp->res[0].start = PCIE_ARB_BASE_ADDR; + pp->res[0].end = pp->res[0].start + SZ_64K - 1; + } + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &pp->res[0]; + + /* + * IORESOURCE_MEM + */ + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), + "PCIe %d MEM", pp->index); + pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; + pp->res[1].name = pp->mem_space_name; + if (pp->index == 0) { + pp->res[1].start = PCIE_ARB_BASE_ADDR + SZ_64K; + pp->res[1].end = pp->res[1].start + SZ_16M - SZ_128K - 1; + } + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &pp->res[1]; + + sys->resource[2] = NULL; + + return 1; +} + +static void __init imx_pcie_preinit(void) +{ + pcibios_setup("debug"); +} + +static int imx_pcie_link_up(void __iomem *dbi_base) +{ + /* Check the pcie link up or link down */ + u32 rc, iterations = 0x100000; + + do { + /* link is debug bit 36 debug 1 start in bit 32 */ + rc = readl(dbi_base + DB_R1) & (0x1 << (36-32)) ; + iterations--; + if ((iterations % 0x100000) == 0) + pr_info("link up failed!\n"); + } while (!rc && iterations); + + if (!rc) + return 0; + return 1; +} + +static int pcie_valid_config(struct imx_pcie_port *pp, int bus_num, int dev) +{ + /*If there is no link, then there is no device*/ + if (bus_num != pp->root_bus_nr) { + if (!imx_pcie_link_up(pp->dbi_base)) + return 0; + } + + /* + * Don't go out when trying to access nonexisting devices + * on the local bus. + * We have only one slot on the root port. + */ + if (bus_num == pp->root_bus_nr && dev > 0) + return 0; + + return 1; +} + +static void imx_pcie_regions_setup(void __iomem *dbi_base) +{ + /* + * i.MX6 defines 16MB in the AXI address map for PCIe. + * + * That address space excepted the pcie registers is + * split and defined into different regions by iATU, + * with sizes and offsets as follows: + * + * 0x0100_0000 --- 0x0100_FFFF 64KB IORESOURCE_IO + * 0x0101_0000 --- 0x01FE_FFFF 16MB - 128KB IORESOURCE_MEM + * 0x01FF_0000 --- 0x01FF_FFFF 64KB Cfg + Registers + */ + + /* CMD reg:I/O space, MEM space, and Bus Master Enable */ + writel(readl(dbi_base + PCI_COMMAND) + | PCI_COMMAND_IO + | PCI_COMMAND_MEMORY + | PCI_COMMAND_MASTER, + dbi_base + PCI_COMMAND); + /* + * region0 outbound used to access target cfg + */ + writel(0, dbi_base + ATU_VIEWPORT_R); + writel(PCIE_ARB_END_ADDR - SZ_64K + 1, dbi_base + ATU_REGION_LOWBASE_R); + writel(0, dbi_base + ATU_REGION_UPBASE_R); + writel(PCIE_ARB_END_ADDR, dbi_base + ATU_REGION_LIMIT_ADDR_R); + writel(0, dbi_base + ATU_REGION_LOW_TRGT_ADDR_R); + writel(0, dbi_base + ATU_REGION_UP_TRGT_ADDR_R); + writel(CfgRdWr0, dbi_base + ATU_REGION_CTRL1_R); + writel((1<<31), dbi_base + ATU_REGION_CTRL2_R); + + /* + * region1 outbound used to as IORESOURCE_IO + */ + writel(1, dbi_base + ATU_VIEWPORT_R); + writel(0, dbi_base + ATU_REGION_LOWBASE_R); + writel(0, dbi_base + ATU_REGION_UPBASE_R); + writel(SZ_64K - 1, dbi_base + ATU_REGION_LIMIT_ADDR_R); + writel(0, dbi_base + ATU_REGION_LOW_TRGT_ADDR_R); + writel(0, dbi_base + ATU_REGION_UP_TRGT_ADDR_R); + writel(IORdWr, dbi_base + ATU_REGION_CTRL1_R); + writel((1<<31), dbi_base + ATU_REGION_CTRL2_R); + + /* + * region2 outbound used to as IORESOURCE_MEM + */ + writel(2, dbi_base + ATU_VIEWPORT_R); + writel(0, dbi_base + ATU_REGION_LOWBASE_R); + writel(0, dbi_base + ATU_REGION_UPBASE_R); + writel(SZ_16M - SZ_128K - 1, dbi_base + ATU_REGION_LIMIT_ADDR_R); + writel(0, dbi_base + ATU_REGION_LOW_TRGT_ADDR_R); + writel(0, dbi_base + ATU_REGION_UP_TRGT_ADDR_R); + writel(MemRdWr, dbi_base + ATU_REGION_CTRL1_R); + writel((1<<31), dbi_base + ATU_REGION_CTRL2_R); +} + +static int imx_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct imx_pcie_port *pp = bus_to_port(bus->number); + unsigned long flags; + u32 va_address; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + + spin_lock_irqsave(&pp->conf_lock, flags); + + va_address = (u32)pp->base + + PCIE_CONF_BUS(bus->number) + + PCIE_CONF_DEV(PCI_SLOT(devfn)) + + PCIE_CONF_FUNC(PCI_FUNC(devfn)) + + (where & ~0x3); + + *val = readl(va_address); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xFF; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xFFFF; + + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static int imx_pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + struct imx_pcie_port *pp = bus_to_port(bus->number); + unsigned long flags; + u32 va_address = 0, mask = 0, tmp = 0; + int ret = PCIBIOS_SUCCESSFUL; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&pp->conf_lock, flags); + + va_address = (u32)pp->base + + PCIE_CONF_BUS(bus->number) + + PCIE_CONF_DEV(PCI_SLOT(devfn)) + + PCIE_CONF_FUNC(PCI_FUNC(devfn)) + + (where & ~0x3); + + if (size == 4) { + writel(val, va_address); + goto exit; + } + + if (size == 2) + mask = ~(0xFFFF << ((where & 0x3) * 8)); + else if (size == 1) + mask = ~(0xFF << ((where & 0x3) * 8)); + else + ret = PCIBIOS_BAD_REGISTER_NUMBER; + + tmp = readl(va_address) & mask; + tmp |= val << ((where & 0x3) * 8); + writel(tmp, va_address); +exit: + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static struct pci_ops imx_pcie_ops = { + .read = imx_pcie_rd_conf, + .write = imx_pcie_wr_conf, +}; + +static struct pci_bus __init * +imx_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_bus *bus; + + if (nr < num_pcie_ports) { + bus = pci_scan_bus(sys->busnr, &imx_pcie_ops, sys); + } else { + bus = NULL; + BUG(); + } + + return bus; +} + +static int __init imx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return MXC_INT_PCIE_0; +} + +static struct hw_pci imx_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = imx_pcie_setup, + .preinit = imx_pcie_preinit, + .scan = imx_pcie_scan_bus, + .map_irq = imx_pcie_map_irq, +}; + +static void imx_pcie_enable_controller(void) +{ + struct clk *pcie_clk; + + imx_pcie_clrset(iomuxc_gpr1_test_powerdown, 0 << 18, IOMUXC_GPR1); + + /* enable the clks */ + pcie_clk = clk_get(NULL, "pcie_clk"); + if (IS_ERR(pcie_clk)) + pr_err("no pcie clock.\n"); + + if (clk_enable(pcie_clk)) { + pr_err("can't enable pcie clock.\n"); + clk_put(pcie_clk); + } +} + +static void card_reset(void) +{ + /* Add one reset to the pcie external device */ +} + +static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base) +{ + if (imx_pcie_link_up(dbi_base)) { + struct imx_pcie_port *pp = &imx_pcie_port[num_pcie_ports++]; + + pr_info("IMX PCIe port: link up.\n"); + + pp->index = 0; + pp->root_bus_nr = -1; + pp->base = base; + pp->dbi_base = dbi_base; + spin_lock_init(&pp->conf_lock); + memset(pp->res, 0, sizeof(pp->res)); + } else + pr_info("IMX PCIe port: link down!\n"); +} + +static int __init imx_pcie_init(void) +{ + void __iomem *base, *dbi_base; + + base = ioremap_nocache(PCIE_ARB_END_ADDR - SZ_64K + 1, SZ_32K); + if (!base) { + pr_err("error with ioremap in function %s\n", __func__); + return -EIO; + } + + dbi_base = ioremap_nocache(PCIE_DBI_BASE_ADDR, SZ_16K); + if (!dbi_base) { + pr_err("error with ioremap in function %s\n", __func__); + iounmap(base); + return -EIO; + } + + /* FIXME the field name should be aligned to RM */ + imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 0 << 10, IOMUXC_GPR12); + + /* configure constant input signal to the pcie ctrl and phy */ + imx_pcie_clrset(iomuxc_gpr12_device_type, PCI_EXP_TYPE_ROOT_PORT << 12, + IOMUXC_GPR12); + imx_pcie_clrset(iomuxc_gpr12_los_level, 9 << 4, IOMUXC_GPR12); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen1, 21 << 0, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_3p5db, 21 << 6, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 32 << 12, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_swing_full, 115 << 18, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_swing_low, 115 << 25, IOMUXC_GPR8); + + /* Enable the pwr, clks and so on */ + imx_pcie_enable_controller(); + + imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 1 << 16, IOMUXC_GPR1); + + /* togle the external card's reset */ + card_reset() ; + + usleep_range(3000, 4000); + imx_pcie_regions_setup(dbi_base); + usleep_range(3000, 4000); + + /* start link up */ + imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 1 << 10, IOMUXC_GPR12); + + /* add the pcie port */ + add_pcie_port(base, dbi_base); + + pci_common_init(&imx_pci); + pr_info("pcie init successful\n"); + return 0; +} +subsys_initcall(imx_pcie_init); diff --git a/arch/arm/mach-mvf/plat_hotplug.c b/arch/arm/mach-mvf/plat_hotplug.c new file mode 100644 index 000000000000..4ae4676f962e --- /dev/null +++ b/arch/arm/mach-mvf/plat_hotplug.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <linux/io.h> +#include "src-reg.h" +#include <linux/sched.h> +#include <asm/cacheflush.h> + +static atomic_t cpu_die_done = ATOMIC_INIT(0); +int platform_cpu_kill(unsigned int cpu) +{ + void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR); + unsigned int val; + + val = jiffies; + /* wait secondary cpu to die, timeout is 50ms */ + while (atomic_read(&cpu_die_done) == 0) { + if (time_after(jiffies, (unsigned long)(val + HZ / 20))) { + printk(KERN_WARNING "cpu %d: cpu could not die\n", cpu); + break; + } + } + + /* + * we're ready for shutdown now, so do it + */ + val = __raw_readl(src_base + SRC_SCR_OFFSET); + val &= ~(1 << (BP_SRC_SCR_CORES_DBG_RST + cpu)); + val |= (1 << (BP_SRC_SCR_CORE0_RST + cpu)); + __raw_writel(val, src_base + SRC_SCR_OFFSET); + + val = jiffies; + /* wait secondary cpu reset done, timeout is 10ms */ + while ((__raw_readl(src_base + SRC_SCR_OFFSET) & + (1 << (BP_SRC_SCR_CORE0_RST + cpu))) != 0) { + if (time_after(jiffies, (unsigned long)(val + HZ / 100))) { + printk(KERN_WARNING "cpu %d: cpu reset fail\n", cpu); + break; + } + } + + atomic_set(&cpu_die_done, 0); + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + if (cpu == 0) { + printk(KERN_ERR "CPU0 can't be disabled!\n"); + return; + } + + flush_cache_all(); + dsb(); + + /* tell cpu0 to kill me */ + atomic_set(&cpu_die_done, 1); + for (;;) { + /* + * Execute WFI + */ + cpu_do_idle(); + } +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-mvf/platsmp.c b/arch/arm/mach-mvf/platsmp.c new file mode 100644 index 000000000000..a21f0231f131 --- /dev/null +++ b/arch/arm/mach-mvf/platsmp.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> +#include <asm/cacheflush.h> +#include <asm/mach-types.h> +#include <asm/localtimer.h> +#include <asm/smp_scu.h> +#include <asm/io.h> +#include <mach/hardware.h> +#include <mach/mx6.h> +#include <mach/smp.h> +#include "src-reg.h" + +static DEFINE_SPINLOCK(boot_lock); + +static void __iomem *scu_base_addr(void) +{ + return IO_ADDRESS(SCU_BASE_ADDR); +} + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + + spin_lock(&boot_lock); + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * Synchronise with the boot thread. + */ + + spin_unlock(&boot_lock); + +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long boot_entry; + void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR); + unsigned int val; + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* set entry point for cpu1-cpu3*/ + boot_entry = virt_to_phys(mx6_secondary_startup); + + writel(boot_entry, src_base + SRC_GPR1_OFFSET + 4 * 2 * cpu); + writel(0, src_base + SRC_GPR1_OFFSET + 4 * 2 * cpu + 4); + + smp_wmb(); + dsb(); + flush_cache_all(); + + /* reset cpu<n> */ + val = readl(src_base + SRC_SCR_OFFSET); + val |= 1 << (BP_SRC_SCR_CORE0_RST + cpu); + val |= 1 << (BP_SRC_SCR_CORES_DBG_RST + cpu); + writel(val, src_base + SRC_SCR_OFFSET); + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return 0; + +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + void __iomem *scu_base = scu_base_addr(); + unsigned int i, ncores; + + ncores = scu_base ? scu_get_core_count(scu_base) : 1; + + /* sanity check */ + if (ncores == 0) { + pr_err("mx6: strange CM count of 0? Default to 1\n"); + ncores = 1; + } + if (ncores > NR_CPUS) { + pr_warning("mx6: no. of cores (%d) greater than configured " + "maximum of %d - clipping\n", + ncores, NR_CPUS); + ncores = NR_CPUS; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); +} +static void __init wakeup_secondary(void) +{ + +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; + void __iomem *scu_base = scu_base_addr(); + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + /* + * Initialise the SCU and wake up the secondary core using + * wakeup_secondary(). + */ + scu_enable(scu_base); + wakeup_secondary(); +} diff --git a/arch/arm/mach-mvf/pm.c b/arch/arm/mach-mvf/pm.c new file mode 100644 index 000000000000..76a2c8dca50e --- /dev/null +++ b/arch/arm/mach-mvf/pm.c @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/suspend.h> +#include <linux/regulator/machine.h> +#include <linux/proc_fs.h> +#include <linux/iram_alloc.h> +#include <linux/fsl_devices.h> +#include <asm/mach-types.h> +#include <asm/cacheflush.h> +#include <asm/tlb.h> +#include <asm/delay.h> +#include <asm/mach/map.h> +#include <mach/hardware.h> +#include <mach/imx-pm.h> +#include <mach/arc_otg.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/hardware/gic.h> +#ifdef CONFIG_ARCH_MX6Q +#include <mach/iomux-mx6q.h> +#endif +#include "crm_regs.h" +#include "src-reg.h" + +#define SCU_CTRL_OFFSET 0x00 +#define GPC_IMR1_OFFSET 0x08 +#define GPC_IMR2_OFFSET 0x0c +#define GPC_IMR3_OFFSET 0x10 +#define GPC_IMR4_OFFSET 0x14 +#define GPC_ISR1_OFFSET 0x18 +#define GPC_ISR2_OFFSET 0x1c +#define GPC_ISR3_OFFSET 0x20 +#define GPC_ISR4_OFFSET 0x24 +#define GPC_CNTR_OFFSET 0x0 +#define GPC_PGC_GPU_PGCR_OFFSET 0x260 +#define GPC_PGC_CPU_PDN_OFFSET 0x2a0 +#define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 +#define GPC_PGC_CPU_PDNSCR_OFFSET 0x2a8 +#define UART_UCR3_OFFSET 0x88 +#define UART_USR1_OFFSET 0x94 +#define UART_UCR3_AWAKEN (1 << 4) +#define UART_USR1_AWAKE (1 << 4) +#define LOCAL_TWD_LOAD_OFFSET 0x0 +#define LOCAL_TWD_COUNT_OFFSET 0x4 +#define LOCAL_TWD_CONTROL_OFFSET 0x8 +#define LOCAL_TWD_INT_OFFSET 0xc +#define ANATOP_REG_2P5_OFFSET 0x130 +#define ANATOP_REG_CORE_OFFSET 0x140 + +static struct clk *cpu_clk; +static struct pm_platform_data *pm_data; + +#if defined(CONFIG_CPU_FREQ) +extern int set_cpu_freq(int wp); +#endif +extern void mx6q_suspend(suspend_state_t state); +extern void mx6_init_irq(void); +extern unsigned int gpc_wake_irq[4]; + +static struct device *pm_dev; +struct clk *gpc_dvfs_clk; +static void __iomem *scu_base; +static void __iomem *gpc_base; +static void __iomem *src_base; +static void __iomem *local_twd_base; +static void __iomem *gic_dist_base; +static void __iomem *gic_cpu_base; +static void __iomem *anatop_base; + +static void *suspend_iram_base; +static void (*suspend_in_iram)(suspend_state_t state, + unsigned long iram_paddr, unsigned long suspend_iram_base) = NULL; +static unsigned long iram_paddr, cpaddr; + +static u32 ccm_ccr, ccm_clpcr, scu_ctrl; +static u32 gpc_imr[4], gpc_cpu_pup, gpc_cpu_pdn, gpc_cpu, gpc_ctr; +static u32 anatop[2], ccgr1, ccgr2, ccgr3, ccgr6; +static u32 ccm_analog_pfd528; +static bool usb_vbus_wakeup_enabled; + + +/* + * The USB VBUS wakeup should be disabled to avoid vbus wake system + * up due to vbus comparator is closed at weak 2p5 mode. + */ +static void usb_power_down_handler(void) +{ + u32 temp; + bool usb_oh3_clk_already_on; + /* enable usb oh3 clock if needed*/ + temp = __raw_readl(MXC_CCM_CCGR6); + usb_oh3_clk_already_on = \ + ((temp & (MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET)) \ + == (MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET)); + if (!usb_oh3_clk_already_on) { + temp |= MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET; + __raw_writel(temp, MXC_CCM_CCGR6); + } + /* disable vbus wakeup */ + usb_vbus_wakeup_enabled = !!(USB_OTG_CTRL & UCTRL_WKUP_VBUS_EN); + if (usb_vbus_wakeup_enabled) { + USB_OTG_CTRL &= ~UCTRL_WKUP_VBUS_EN; + } + /* disable usb oh3 clock */ + if (!usb_oh3_clk_already_on) { + temp = __raw_readl(MXC_CCM_CCGR6); + temp &= ~(MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET); + __raw_writel(temp, MXC_CCM_CCGR6); + } +} + +static void usb_power_up_handler(void) +{ + /* enable vbus wakeup at runtime if needed */ + if (usb_vbus_wakeup_enabled) { + u32 temp; + bool usb_oh3_clk_already_on; + /* enable usb oh3 clock if needed*/ + temp = __raw_readl(MXC_CCM_CCGR6); + usb_oh3_clk_already_on = \ + ((temp & (MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET)) \ + == (MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET)); + if (!usb_oh3_clk_already_on) { + temp |= MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET; + __raw_writel(temp, MXC_CCM_CCGR6); + } + + /* restore usb wakeup enable setting */ + USB_OTG_CTRL |= UCTRL_WKUP_VBUS_EN; + + /* disable usb oh3 clock */ + if (!usb_oh3_clk_already_on) { + temp = __raw_readl(MXC_CCM_CCGR6); + temp &= ~(MXC_CCM_CCGRx_CG_MASK << MXC_CCM_CCGRx_CG0_OFFSET); + __raw_writel(temp, MXC_CCM_CCGR6); + } + } +} + +static void gpu_power_down(void) +{ + int reg; + + /* enable power down request */ + reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + /* power down request */ + reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET); + /* disable clocks */ + __raw_writel(ccgr1 & + ~MXC_CCM_CCGRx_CG12_MASK & + ~MXC_CCM_CCGRx_CG13_MASK, MXC_CCM_CCGR1); + __raw_writel(ccgr3 & ~MXC_CCM_CCGRx_CG15_MASK, MXC_CCM_CCGR3); + __raw_writel(ccgr6 & ~MXC_CCM_CCGRx_CG7_MASK, MXC_CCM_CCGR6); + /* power off pu */ + reg = __raw_readl(anatop_base + ANATOP_REG_CORE_OFFSET); + reg &= ~0x0003fe00; + __raw_writel(reg, anatop_base + ANATOP_REG_CORE_OFFSET); +} + +static void gpu_power_up(void) +{ + int reg; + /* power on pu */ + reg = __raw_readl(anatop_base + ANATOP_REG_CORE_OFFSET); + reg &= ~0x0003fe00; + reg |= 0x10 << 9; /* 1.1v */ + __raw_writel(reg, anatop_base + ANATOP_REG_CORE_OFFSET); + mdelay(10); + + /* enable clocks */ + /* PLL2 PFD0 and PFD1 clock enable */ + __raw_writel(ccm_analog_pfd528 & + ~ANADIG_PFD0_CLKGATE & + ~ANADIG_PFD1_CLKGATE, PFD_528_BASE_ADDR); + /* gpu3d and gpu2d clock enable */ + __raw_writel(ccgr1 | + MXC_CCM_CCGRx_CG12_MASK | + MXC_CCM_CCGRx_CG13_MASK, MXC_CCM_CCGR1); + /* tzasrc1 clock enable for gpu3d core clock */ + __raw_writel(ccgr2 | MXC_CCM_CCGRx_CG11_MASK, MXC_CCM_CCGR2); + /* openvgaxi clock enable, mmdc_core_ipg_clk_p0 clock and + mmdc_core_aclk_fast_core_p0 clock enable for gpu3d core clock */ + __raw_writel(ccgr3 | + MXC_CCM_CCGRx_CG15_MASK | + MXC_CCM_CCGRx_CG12_MASK | + MXC_CCM_CCGRx_CG10_MASK, MXC_CCM_CCGR3); + /* vpu clock enable */ + __raw_writel(ccgr6 | MXC_CCM_CCGRx_CG7_MASK, MXC_CCM_CCGR6); + + /* enable power up request */ + reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + /* power up request */ + reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + __raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET); + udelay(10); +} + + + +static void mx6_suspend_store(void) +{ + /* save some settings before suspend */ + ccm_ccr = __raw_readl(MXC_CCM_CCR); + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR); + ccm_analog_pfd528 = __raw_readl(PFD_528_BASE_ADDR); + ccgr1 = __raw_readl(MXC_CCM_CCGR1); + ccgr2 = __raw_readl(MXC_CCM_CCGR2); + ccgr3 = __raw_readl(MXC_CCM_CCGR3); + ccgr6 = __raw_readl(MXC_CCM_CCGR6); + scu_ctrl = __raw_readl(scu_base + SCU_CTRL_OFFSET); + gpc_imr[0] = __raw_readl(gpc_base + GPC_IMR1_OFFSET); + gpc_imr[1] = __raw_readl(gpc_base + GPC_IMR2_OFFSET); + gpc_imr[2] = __raw_readl(gpc_base + GPC_IMR3_OFFSET); + gpc_imr[3] = __raw_readl(gpc_base + GPC_IMR4_OFFSET); + gpc_cpu_pup = __raw_readl(gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); + gpc_cpu_pdn = __raw_readl(gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); + gpc_cpu = __raw_readl(gpc_base + GPC_PGC_CPU_PDN_OFFSET); + gpc_ctr = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + anatop[0] = __raw_readl(anatop_base + ANATOP_REG_2P5_OFFSET); + anatop[1] = __raw_readl(anatop_base + ANATOP_REG_CORE_OFFSET); +} + +static void mx6_suspend_restore(void) +{ + /* restore settings after suspend */ + __raw_writel(anatop[0], anatop_base + ANATOP_REG_2P5_OFFSET); + __raw_writel(anatop[1], anatop_base + ANATOP_REG_CORE_OFFSET); + /* Per spec, the count needs to be zeroed and reconfigured on exit from + * low power mode + */ + __raw_writel(ccm_ccr & ~MXC_CCM_CCR_REG_BYPASS_CNT_MASK & + ~MXC_CCM_CCR_WB_COUNT_MASK, MXC_CCM_CCR); + udelay(50); + __raw_writel(ccm_ccr, MXC_CCM_CCR); + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + __raw_writel(scu_ctrl, scu_base + SCU_CTRL_OFFSET); + __raw_writel(gpc_imr[0], gpc_base + GPC_IMR1_OFFSET); + __raw_writel(gpc_imr[1], gpc_base + GPC_IMR2_OFFSET); + __raw_writel(gpc_imr[2], gpc_base + GPC_IMR3_OFFSET); + __raw_writel(gpc_imr[3], gpc_base + GPC_IMR4_OFFSET); + __raw_writel(gpc_cpu_pup, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); + __raw_writel(gpc_cpu_pdn, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); + __raw_writel(gpc_cpu, gpc_base + GPC_PGC_CPU_PDN_OFFSET); + + __raw_writel(ccgr1, MXC_CCM_CCGR1); + __raw_writel(ccgr2, MXC_CCM_CCGR2); + __raw_writel(ccgr3, MXC_CCM_CCGR3); + __raw_writel(ccgr6, MXC_CCM_CCGR6); + __raw_writel(ccm_analog_pfd528, PFD_528_BASE_ADDR); +} + +static int mx6_suspend_enter(suspend_state_t state) +{ + unsigned int wake_irq_isr[4]; + struct gic_dist_state gds; + struct gic_cpu_state gcs; + + wake_irq_isr[0] = __raw_readl(gpc_base + + GPC_ISR1_OFFSET) & gpc_wake_irq[0]; + wake_irq_isr[1] = __raw_readl(gpc_base + + GPC_ISR2_OFFSET) & gpc_wake_irq[1]; + wake_irq_isr[2] = __raw_readl(gpc_base + + GPC_ISR3_OFFSET) & gpc_wake_irq[2]; + wake_irq_isr[3] = __raw_readl(gpc_base + + GPC_ISR4_OFFSET) & gpc_wake_irq[3]; + if (wake_irq_isr[0] | wake_irq_isr[1] | + wake_irq_isr[2] | wake_irq_isr[3]) { + printk(KERN_INFO "There are wakeup irq pending,system resume!\n"); + printk(KERN_INFO "wake_irq_isr[0-3]: 0x%x, 0x%x, 0x%x, 0x%x\n", + wake_irq_isr[0], wake_irq_isr[1], + wake_irq_isr[2], wake_irq_isr[3]); + return 0; + } + mx6_suspend_store(); + + switch (state) { + case PM_SUSPEND_MEM: + gpu_power_down(); + usb_power_down_handler(); + mxc_cpu_lp_set(ARM_POWER_OFF); + break; + case PM_SUSPEND_STANDBY: + mxc_cpu_lp_set(STOP_POWER_OFF); + break; + default: + return -EINVAL; + } + + if (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY) { + if (pm_data && pm_data->suspend_enter) + pm_data->suspend_enter(); + + local_flush_tlb_all(); + flush_cache_all(); + + if (state == PM_SUSPEND_MEM) { + /* preserve gic state */ + save_gic_dist_state(0, &gds); + save_gic_cpu_state(0, &gcs); + } + + suspend_in_iram(state, (unsigned long)iram_paddr, + (unsigned long)suspend_iram_base); + + if (state == PM_SUSPEND_MEM) { + /* restore gic registers */ + restore_gic_dist_state(0, &gds); + restore_gic_cpu_state(0, &gcs); + usb_power_up_handler(); + gpu_power_up(); + } + mx6_suspend_restore(); + + if (pm_data && pm_data->suspend_exit) + pm_data->suspend_exit(); + } else { + cpu_do_idle(); + } + + return 0; +} + + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx6_suspend_prepare(void) +{ + return 0; +} + +/* + * Called before devices are re-setup. + */ +static void mx6_suspend_finish(void) +{ +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx6_suspend_end(void) +{ +} + +static int mx6_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx6_suspend_ops = { + .valid = mx6_pm_valid, + .prepare = mx6_suspend_prepare, + .enter = mx6_suspend_enter, + .finish = mx6_suspend_finish, + .end = mx6_suspend_end, +}; + +static int __devinit mx6_pm_probe(struct platform_device *pdev) +{ + pm_dev = &pdev->dev; + pm_data = pdev->dev.platform_data; + + return 0; +} + +static struct platform_driver mx6_pm_driver = { + .driver = { + .name = "imx_pm", + }, + .probe = mx6_pm_probe, +}; + +static int __init pm_init(void) +{ + scu_base = IO_ADDRESS(SCU_BASE_ADDR); + gpc_base = IO_ADDRESS(GPC_BASE_ADDR); + src_base = IO_ADDRESS(SRC_BASE_ADDR); + gic_dist_base = IO_ADDRESS(IC_DISTRIBUTOR_BASE_ADDR); + gic_cpu_base = IO_ADDRESS(IC_INTERFACES_BASE_ADDR); + local_twd_base = IO_ADDRESS(LOCAL_TWD_ADDR); + anatop_base = IO_ADDRESS(ANATOP_BASE_ADDR); + + pr_info("Static Power Management for Freescale i.MX6\n"); + + if (platform_driver_register(&mx6_pm_driver) != 0) { + printk(KERN_ERR "mx6_pm_driver register failed\n"); + return -ENODEV; + } + + suspend_set_ops(&mx6_suspend_ops); + /* Move suspend routine into iRAM */ + cpaddr = (unsigned long)iram_alloc(SZ_4K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K, + MT_MEMORY_NONCACHED); + pr_info("cpaddr = %x suspend_iram_base=%x\n", + (unsigned int)cpaddr, (unsigned int)suspend_iram_base); + + /* + * Need to run the suspend code from IRAM as the DDR needs + * to be put into low power mode manually. + */ + memcpy((void *)cpaddr, mx6q_suspend, SZ_4K); + + suspend_in_iram = (void *)suspend_iram_base; + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__); + return PTR_ERR(cpu_clk); + } + printk(KERN_INFO "PM driver module loaded\n"); + + return 0; +} + +static void __exit pm_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mx6_pm_driver); +} + +module_init(pm_init); +module_exit(pm_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("PM driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/arm/mach-mvf/regs-anadig.h b/arch/arm/mach-mvf/regs-anadig.h new file mode 100644 index 000000000000..6fcf9b549148 --- /dev/null +++ b/arch/arm/mach-mvf/regs-anadig.h @@ -0,0 +1,790 @@ +/* + * based on arch/arm/mach-mx6/regs-anadig.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * Freescale ANADIG Register Definitions + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___ANADIG_H +#define __ARCH_ARM___ANADIG_H + + +#define HW_ANADIG_USB1_PLL_480_CTRL (0x00000000) + +#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 +#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD2 17 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD2 0x7FFE0000 +#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD2(v) \ + (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD2) +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x00008000 +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 +#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 +#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 +#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD0 2 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x0000003C +#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD0) +#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 +#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) + +#define HW_ANADIG_USB2_PLL_480_CTRL (0x00000020) + +#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK 0x80000000 +#define BP_ANADIG_USB2_PLL_480_CTRL_RSVD2 17 +#define BM_ANADIG_USB2_PLL_480_CTRL_RSVD2 0x7FFE0000 +#define BF_ANADIG_USB2_PLL_480_CTRL_RSVD2(v) \ + (((v) << 17) & BM_ANADIG_USB2_PLL_480_CTRL_RSVD2) +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_USB2_PLL_480_CTRL_RSVD1 0x00008000 +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 +#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF 0x00000080 +#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 +#define BP_ANADIG_USB2_PLL_480_CTRL_RSVD0 2 +#define BM_ANADIG_USB2_PLL_480_CTRL_RSVD0 0x0000003C +#define BF_ANADIG_USB2_PLL_480_CTRL_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB2_PLL_480_CTRL_RSVD0) +#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0x00000003 +#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) + +#define HW_ANADIG_PLL_528_CTRL (0x00000030) + +#define BM_ANADIG_PLL_528_CTRL_LOCK 0x80000000 +#define BP_ANADIG_PLL_528_CTRL_RSVD2 19 +#define BM_ANADIG_PLL_528_CTRL_RSVD2 0x7FF80000 +#define BF_ANADIG_PLL_528_CTRL_RSVD2(v) \ + (((v) << 19) & BM_ANADIG_PLL_528_CTRL_RSVD2) +#define BM_ANADIG_PLL_528_CTRL_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_528_CTRL_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_528_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_PLL_528_CTRL_RSVD1 0x00008000 +#define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_PLL_528_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_PLL_528_CTRL_POWERDOWN 0x00001000 +#define BP_ANADIG_PLL_528_CTRL_RSVD0 1 +#define BM_ANADIG_PLL_528_CTRL_RSVD0 0x00000FFE +#define BF_ANADIG_PLL_528_CTRL_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_PLL_528_CTRL_RSVD0) +#define BM_ANADIG_PLL_528_CTRL_DIV_SELECT 0x00000001 + +#define HW_ANADIG_PLL_528_SS (0x00000040) + +#define BP_ANADIG_PLL_528_SS_STOP 16 +#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 +#define BF_ANADIG_PLL_528_SS_STOP(v) \ + (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) +#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 +#define BP_ANADIG_PLL_528_SS_STEP 0 +#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF +#define BF_ANADIG_PLL_528_SS_STEP(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) + +#define HW_ANADIG_PLL_528_NUM (0x00000050) + +#define BP_ANADIG_PLL_528_NUM_RSVD0 30 +#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) +#define BP_ANADIG_PLL_528_NUM_A 0 +#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_528_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) + +#define HW_ANADIG_PLL_528_DENOM (0x00000060) + +#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) +#define BP_ANADIG_PLL_528_DENOM_B 0 +#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_528_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) + +#define HW_ANADIG_PLL_AUDIO_CTRL (0x00000070) + +#define BM_ANADIG_PLL_AUDIO_CTRL_LOCK 0x80000000 +#define BP_ANADIG_PLL_AUDIO_CTRL_RSVD1 22 +#define BM_ANADIG_PLL_AUDIO_CTRL_RSVD1 0x7FC00000 +#define BF_ANADIG_PLL_AUDIO_CTRL_RSVD1(v) \ + (((v) << 22) & BM_ANADIG_PLL_AUDIO_CTRL_RSVD1) +#define BM_ANADIG_PLL_AUDIO_CTRL_SSC_EN 0x00200000 +#define BP_ANADIG_PLL_AUDIO_CTRL_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_AUDIO_CTRL_TEST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_AUDIO_CTRL_TEST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_AUDIO_CTRL_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_AUDIO_CTRL_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_AUDIO_CTRL_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_AUDIO_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_PLL_AUDIO_CTRL_RSVD0 0x00008000 +#define BM_ANADIG_PLL_AUDIO_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_PLL_AUDIO_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_AUDIO_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_PLL_AUDIO_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_PLL_AUDIO_CTRL_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_AUDIO_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_AUDIO_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_AUDIO_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_AUDIO_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_AUDIO_CTRL_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_AUDIO_CTRL_DIV_SELECT 0 +#define BM_ANADIG_PLL_AUDIO_CTRL_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_AUDIO_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_CTRL_DIV_SELECT) + +#define HW_ANADIG_PLL_AUDIO_NUM (0x00000080) + +#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 +#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) +#define BP_ANADIG_PLL_AUDIO_NUM_A 0 +#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) + +#define HW_ANADIG_PLL_AUDIO_DENOM (0x00000090) + +#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) +#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 +#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) + +#define HW_ANADIG_PLL_VIDEO_CTRL (0x000000A0) + +#define BM_ANADIG_PLL_VIDEO_CTRL_LOCK 0x80000000 +#define BP_ANADIG_PLL_VIDEO_CTRL_RSVD1 22 +#define BM_ANADIG_PLL_VIDEO_CTRL_RSVD1 0x7FC00000 +#define BF_ANADIG_PLL_VIDEO_CTRL_RSVD1(v) \ + (((v) << 22) & BM_ANADIG_PLL_VIDEO_CTRL_RSVD1) +#define BM_ANADIG_PLL_VIDEO_CTRL_SSC_EN 0x00200000 +#define BP_ANADIG_PLL_VIDEO_CTRL_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_CTRL_TEST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_VIDEO_CTRL_TEST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_VIDEO_CTRL_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_VIDEO_CTRL_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_VIDEO_CTRL_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_VIDEO_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_PLL_VIDEO_CTRL_RSVD0 0x00008000 +#define BM_ANADIG_PLL_VIDEO_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_PLL_VIDEO_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_VIDEO_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_PLL_VIDEO_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_PLL_VIDEO_CTRL_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_VIDEO_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_VIDEO_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_VIDEO_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_VIDEO_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_VIDEO_CTRL_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_VIDEO_CTRL_DIV_SELECT 0 +#define BM_ANADIG_PLL_VIDEO_CTRL_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_VIDEO_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_CTRL_DIV_SELECT) + +#define HW_ANADIG_PLL_VIDEO_NUM (0x000000B0) + +#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 +#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) +#define BP_ANADIG_PLL_VIDEO_NUM_A 0 +#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) + +#define HW_ANADIG_PLL_VIDEO_DENOM (0x000000C0) + +#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) +#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 +#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) + +#define HW_ANADIG_PLL_ENET_CTRL (0x000000E0) + +#define BM_ANADIG_PLL_ENET_CTRL_LOCK 0x80000000 +#define BP_ANADIG_PLL_ENET_CTRL_RSVD2 19 +#define BM_ANADIG_PLL_ENET_CTRL_RSVD2 0x7FF80000 +#define BF_ANADIG_PLL_ENET_CTRL_RSVD2(v) \ + (((v) << 19) & BM_ANADIG_PLL_ENET_CTRL_RSVD2) +#define BM_ANADIG_PLL_ENET_CTRL_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_ENET_CTRL_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_ENET_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_PLL_ENET_CTRL_RSVD1 0x00008000 +#define BM_ANADIG_PLL_ENET_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_PLL_ENET_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_ENET_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_PLL_ENET_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_PLL_ENET_CTRL_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_ENET_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_ENET_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_ENET_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_ENET_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_ENET_CTRL_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_ENET_CTRL_RSVD0 2 +#define BM_ANADIG_PLL_ENET_CTRL_RSVD0 0x0000007C +#define BF_ANADIG_PLL_ENET_CTRL_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET_CTRL_RSVD0) +#define BP_ANADIG_PLL_ENET_CTRL_DIV_SELECT 0 +#define BM_ANADIG_PLL_ENET_CTRL_DIV_SELECT 0x00000003 +#define BF_ANADIG_PLL_ENET_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_ENET_CTRL_DIV_SELECT) + +#define HW_ANADIG_PFD_480_USB1 (0x000000F0) + +#define BM_ANADIG_PFD_480_PFD4_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_480_PFD4_STABLE 0x40000000 +#define BP_ANADIG_PFD_480_PFD4_FRAC 24 +#define BM_ANADIG_PFD_480_PFD4_FRAC 0x3F000000 +#define BF_ANADIG_PFD_480_PFD4_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_480_PFD4_FRAC) +#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_480_PFD3_STABLE 0x00400000 +#define BP_ANADIG_PFD_480_PFD3_FRAC 16 +#define BM_ANADIG_PFD_480_PFD3_FRAC 0x003F0000 +#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_480_PFD3_FRAC) +#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00004000 +#define BP_ANADIG_PFD_480_PFD2_FRAC 8 +#define BM_ANADIG_PFD_480_PFD2_FRAC 0x00003F00 +#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_480_PFD2_FRAC) +#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00000040 +#define BP_ANADIG_PFD_480_PFD1_FRAC 0 +#define BM_ANADIG_PFD_480_PFD1_FRAC 0x0000003F +#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_480_PFD1_FRAC) + +#define HW_ANADIG_PFD_528 (0x00000100) + +#define BM_ANADIG_PFD_528_PFD4_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_528_PFD4_STABLE 0x40000000 +#define BP_ANADIG_PFD_528_PFD4_FRAC 24 +#define BM_ANADIG_PFD_528_PFD4_FRAC 0x3F000000 +#define BF_ANADIG_PFD_528_PFD4_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_528_PFD4_FRAC) +#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_528_PFD3_STABLE 0x00400000 +#define BP_ANADIG_PFD_528_PFD3_FRAC 16 +#define BM_ANADIG_PFD_528_PFD3_FRAC 0x003F0000 +#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_528_PFD3_FRAC) +#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00004000 +#define BP_ANADIG_PFD_528_PFD2_FRAC 8 +#define BM_ANADIG_PFD_528_PFD2_FRAC 0x00003F00 +#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_528_PFD2_FRAC) +#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00000040 +#define BP_ANADIG_PFD_528_PFD1_FRAC 0 +#define BM_ANADIG_PFD_528_PFD1_FRAC 0x0000003F +#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_528_PFD1_FRAC) + +#define HW_ANADIG_REG_1P1 (0x00000110) + +#define BP_ANADIG_REG_1P1_RSVD1 18 +#define BM_ANADIG_REG_1P1_RSVD1 0xFFFC0000 +#define BF_ANADIG_REG_1P1_RSVD1(v) \ + (((v) << 18) & BM_ANADIG_REG_1P1_RSVD1) +#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000 +#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000 +#define BP_ANADIG_REG_1P1_RSVD0 4 +#define BM_ANADIG_REG_1P1_RSVD0 0x0000EFF0 +#define BF_ANADIG_REG_1P1_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_REG_1P1_RSVD0) +#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008 +#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_3P0 (0x00000120) + +#define BP_ANADIG_REG_3P0_RSVD2 18 +#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC0000 +#define BF_ANADIG_REG_3P0_RSVD2(v) \ + (((v) << 18) & BM_ANADIG_REG_3P0_RSVD2) +#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000 +#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000 +#define BP_ANADIG_REG_3P0_RSVD1 8 +#define BM_ANADIG_REG_3P0_RSVD1 0x0000FF00 +#define BF_ANADIG_REG_3P0_RSVD1(v) \ + (((v) << 8) & BM_ANADIG_REG_3P0_RSVD1) +#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080 +#define BP_ANADIG_REG_3P0_RSVD0 3 +#define BM_ANADIG_REG_3P0_RSVD0 0x00000078 +#define BF_ANADIG_REG_3P0_RSVD0(v) \ + (((v) << 3) & BM_ANADIG_REG_3P0_RSVD0) +#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_2P5 (0x00000130) + +#define BP_ANADIG_REG_2P5_RSVD1 19 +#define BM_ANADIG_REG_2P5_RSVD1 0xFFF80000 +#define BF_ANADIG_REG_2P5_RSVD1(v) \ + (((v) << 19) & BM_ANADIG_REG_2P5_RSVD1) +#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000 +#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000 +#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000 +#define BP_ANADIG_REG_2P5_RSVD0 4 +#define BM_ANADIG_REG_2P5_RSVD0 0x0000FFF0 +#define BF_ANADIG_REG_2P5_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_REG_2P5_RSVD0) +#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008 +#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_ANA_MISC0 (0x00000150) + +#define BP_ANADIG_ANA_MISC0_RSVD2 29 +#define BM_ANADIG_ANA_MISC0_RSVD2 0xE0000000 +#define BF_ANADIG_ANA_MISC0_RSVD2(v) \ + (((v) << 29) & BM_ANADIG_ANA_MISC0_RSVD2) +#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 +#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000 +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ + (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) +#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000 +#define BP_ANADIG_ANA_MISC0_ANAMUX 21 +#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000 +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ + (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX) +#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000 +#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 +#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000 +#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ + (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000 +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000 +#define BP_ANADIG_ANA_MISC0_OSC_I 14 +#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ + (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I) +#define BM_ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL 0x00002000 +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000 +#define BP_ANADIG_ANA_MISC0_RSVD1 8 +#define BM_ANADIG_ANA_MISC0_RSVD1 0x00000F00 +#define BF_ANADIG_ANA_MISC0_RSVD1(v) \ + (((v) << 8) & BM_ANADIG_ANA_MISC0_RSVD1) +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080 +#define BP_ANADIG_ANA_MISC0_RSVD0 4 +#define BM_ANADIG_ANA_MISC0_RSVD0 0x00000070 +#define BF_ANADIG_ANA_MISC0_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_ANA_MISC0_RSVD0) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004 +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002 +#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001 + +#define HW_ANADIG_ANA_MISC1 (0x00000160) + +#define BM_ANADIG_ANA_MISC1_RSVD3 0x80000000 +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE 0x20000000 +#define BP_ANADIG_ANA_MISC1_RSVD2 13 +#define BM_ANADIG_ANA_MISC1_RSVD2 0x1FFFE000 +#define BF_ANADIG_ANA_MISC1_RSVD2(v) \ + (((v) << 13) & BM_ANADIG_ANA_MISC1_RSVD2) +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000 +#define BM_ANADIG_ANA_MISC1_RSVD1 0x00000800 +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400 +#define BP_ANADIG_ANA_MISC1_RSVD0 5 +#define BM_ANADIG_ANA_MISC1_RSVD0 0x000003E0 +#define BF_ANADIG_ANA_MISC1_RSVD0(v) \ + (((v) << 5) & BM_ANADIG_ANA_MISC1_RSVD0) +#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ + (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) + +#define HW_ANADIG_TEMPSENSE0 (0x00000180) + +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000 +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ + (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00 +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ + (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BM_ANADIG_TEMPSENSE0_RSVD0 0x00000080 +#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040 +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 +#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038 +#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ + (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ) +#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004 +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002 +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001 + +#define HW_ANADIG_TEMPSENSE1 (0x00000190) + +#define BP_ANADIG_TEMPSENSE1_RSVD0 16 +#define BM_ANADIG_TEMPSENSE1_RSVD0 0xFFFF0000 +#define BF_ANADIG_TEMPSENSE1_RSVD0(v) \ + (((v) << 16) & BM_ANADIG_TEMPSENSE1_RSVD0) +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ + (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) + +#define HW_ANADIG_USB1_VBUS_DETECT (0x000001A0) + +#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD3 28 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD3 0x70000000 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD3(v) \ + (((v) << 28) & BM_ANADIG_USB1_VBUS_DETECT_RSVD3) +#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000 +#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD2 21 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD2 0x03E00000 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD2(v) \ + (((v) << 21) & BM_ANADIG_USB1_VBUS_DETECT_RSVD2) +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD1 0x00080000 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD0 8 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD0 0x0003FF00 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD0(v) \ + (((v) << 8) & BM_ANADIG_USB1_VBUS_DETECT_RSVD0) +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080 +#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040 +#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020 +#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008 +#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 +#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) \ + (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH) + +#define HW_ANADIG_USB1_CHRG_DETECT (0x000001B0) + +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD1 23 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD1 0xFF800000 +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD1(v) \ + (((v) << 23) & BM_ANADIG_USB1_CHRG_DETECT_RSVD1) +#define BM_ANADIG_USB1_CHRG_DETECT_CHRG_DET_CTRL 0x00400000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHRG_DET_STAT 0x00200000 +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000 +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD0 1 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD0 0x0003FFFE +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_USB1_CHRG_DETECT_RSVD0) +#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001 + +#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001C0) + +#define BP_ANADIG_USB1_VBUS_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB1_VBUS_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0) +#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008 +#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004 +#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002 +#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001 + +#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001D0) + +#define BP_ANADIG_USB1_CHRG_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB1_CHRG_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0) +#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008 +#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004 +#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 +#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 + +#define HW_ANADIG_USB1_LOOPBACK (0x000001E0) + +#define BP_ANADIG_USB1_LOOPBACK_RSVD0 9 +#define BM_ANADIG_USB1_LOOPBACK_RSVD0 0xFFFFFE00 +#define BF_ANADIG_USB1_LOOPBACK_RSVD0(v) \ + (((v) << 9) & BM_ANADIG_USB1_LOOPBACK_RSVD0) +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100 +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001 + +#define HW_ANADIG_USB1_MISC (0x000001F0) + +#define BM_ANADIG_USB1_MISC_RSVD1 0x80000000 +#define BM_ANADIG_USB1_MISC_EN_CLK_TO_UTMI 0x40000000 +#define BP_ANADIG_USB1_MISC_RSVD0 2 +#define BM_ANADIG_USB1_MISC_RSVD0 0x3FFFFFFC +#define BF_ANADIG_USB1_MISC_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB1_MISC_RSVD0) +#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002 +#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001 + +#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200) + +#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD3 28 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD3 0x70000000 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD3(v) \ + (((v) << 28) & BM_ANADIG_USB2_VBUS_DETECT_RSVD3) +#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000 +#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD2 21 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD2 0x03E00000 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD2(v) \ + (((v) << 21) & BM_ANADIG_USB2_VBUS_DETECT_RSVD2) +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD1 0x00080000 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD0 3 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD0 0x0003FFF8 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD0(v) \ + (((v) << 3) & BM_ANADIG_USB2_VBUS_DETECT_RSVD0) +#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 +#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) \ + (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH) + +#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) + +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD1 23 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD1 0xFF800000 +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD1(v) \ + (((v) << 23) & BM_ANADIG_USB2_CHRG_DETECT_RSVD1) +#define BM_ANADIG_USB2_CHRG_DETECT_CHRG_DET_CTRL 0x00400000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHRG_DET_STAT 0x00200000 +#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000 +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD0 1 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD0 0x0003FFFE +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_USB2_CHRG_DETECT_RSVD0) +#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001 + +#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220) + +#define BP_ANADIG_USB2_VBUS_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB2_VBUS_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0) +#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008 +#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004 +#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002 +#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001 + +#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230) + +#define BP_ANADIG_USB2_CHRG_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB2_CHRG_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0) +#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008 +#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004 +#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 +#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 + +#define HW_ANADIG_USB2_LOOPBACK (0x00000240) + +#define BP_ANADIG_USB2_LOOPBACK_RSVD0 9 +#define BM_ANADIG_USB2_LOOPBACK_RSVD0 0xFFFFFE00 +#define BF_ANADIG_USB2_LOOPBACK_RSVD0(v) \ + (((v) << 9) & BM_ANADIG_USB2_LOOPBACK_RSVD0) +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100 +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001 + +#define HW_ANADIG_USB2_MISC (0x00000250) + +#define BM_ANADIG_USB2_MISC_RSVD1 0x80000000 +#define BM_ANADIG_USB2_MISC_EN_CLK_TO_UTMI 0x40000000 +#define BP_ANADIG_USB2_MISC_RSVD0 2 +#define BM_ANADIG_USB2_MISC_RSVD0 0x3FFFFFFC +#define BF_ANADIG_USB2_MISC_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB2_MISC_RSVD0) +#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002 +#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001 + +#define HW_ANADIG_DIGPROG (0x00000260) + +#define BP_ANADIG_DIGPROG_RSVD 24 +#define BM_ANADIG_DIGPROG_RSVD 0xFF000000 +#define BF_ANADIG_DIGPROG_RSVD(v) \ + (((v) << 24) & BM_ANADIG_DIGPROG_RSVD) +#define BP_ANADIG_DIGPROG_MAJOR 8 +#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00 +#define BF_ANADIG_DIGPROG_MAJOR(v) \ + (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR) +#define BP_ANADIG_DIGPROG_MINOR 0 +#define BM_ANADIG_DIGPROG_MINOR 0x000000FF +#define BF_ANADIG_DIGPROG_MINOR(v) \ + (((v) << 0) & BM_ANADIG_DIGPROG_MINOR) + +#define HW_ANADIG_PLL_SYS_CTRL (0x00000270) + +#define BM_ANADIG_PLL_SYS_CTRL_LOCK 0x80000000 +#define BP_ANADIG_PLL_SYS_CTRL_RSVD2 19 +#define BM_ANADIG_PLL_SYS_CTRL_RSVD2 0x7FF80000 +#define BF_ANADIG_PLL_SYS_CTRL_RSVD2(v) \ + (((v) << 19) & BM_ANADIG_PLL_SYS_CTRL_RSVD2) +#define BM_ANADIG_PLL_SYS_CTRL_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_SYS_CTRL_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_SYS_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_PLL_SYS_CTRL_RSVD1 0x00008000 +#define BM_ANADIG_PLL_SYS_CTRL_BYPASS_CLK_SRC 0x00004000 +#define BV_ANADIG_PLL_SYS_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_SYS_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BM_ANADIG_PLL_SYS_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_PLL_SYS_CTRL_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_SYS_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_SYS_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_SYS_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_SYS_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_SYS_CTRL_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_SYS_CTRL_RSVD0 1 +#define BM_ANADIG_PLL_SYS_CTRL_RSVD0 0x0000007E +#define BF_ANADIG_PLL_SYS_CTRL_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_PLL_SYS_CTRL_RSVD0) +#define BM_ANADIG_PLL_SYS_CTRL_DIV_SELECT 0x00000001 + +#define HW_ANADIG_PLL_SYS_SS (0x00000280) + +#define BP_ANADIG_PLL_SYS_SS_STOP 16 +#define BM_ANADIG_PLL_SYS_SS_STOP 0xFFFF0000 +#define BF_ANADIG_PLL_SYS_SS_STOP(v) \ + (((v) << 16) & BM_ANADIG_PLL_SYS_SS_STOP) +#define BM_ANADIG_PLL_SYS_SS_ENABLE 0x00008000 +#define BP_ANADIG_PLL_SYS_SS_STEP 0 +#define BM_ANADIG_PLL_SYS_SS_STEP 0x00007FFF +#define BF_ANADIG_PLL_SYS_SS_STEP(v) \ + (((v) << 0) & BM_ANADIG_PLL_SYS_SS_STEP) + +#define HW_ANADIG_PLL_SYS_NUM (0x00000290) + +#define BP_ANADIG_PLL_SYS_NUM_RSVD0 30 +#define BM_ANADIG_PLL_SYS_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_SYS_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_SYS_NUM_RSVD0) +#define BP_ANADIG_PLL_SYS_NUM_A 0 +#define BM_ANADIG_PLL_SYS_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_SYS_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_SYS_NUM_A) + +#define HW_ANADIG_PLL_SYS_DENOM (0x000002A0) + +#define BP_ANADIG_PLL_SYS_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_SYS_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_SYS_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_SYS_DENOM_RSVD0) +#define BP_ANADIG_PLL_SYS_DENOM_B 0 +#define BM_ANADIG_PLL_SYS_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_SYS_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_SYS_DENOM_B) + +#define HW_ANADIG_PFD_528_SYS (0x000002B0) + +#define BM_ANADIG_PFD_528_SYS_PFD4_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_528_SYS_PFD4_STABLE 0x40000000 +#define BP_ANADIG_PFD_528_SYS_PFD4_FRAC 24 +#define BM_ANADIG_PFD_528_SYS_PFD4_FRAC 0x3F000000 +#define BF_ANADIG_PFD_528_SYS_PFD4_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_528_SYS_PFD4_FRAC) +#define BM_ANADIG_PFD_528_SYS_PFD3_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_528_SYS_PFD3_STABLE 0x00400000 +#define BP_ANADIG_PFD_528_SYS_PFD3_FRAC 16 +#define BM_ANADIG_PFD_528_SYS_PFD3_FRAC 0x003F0000 +#define BF_ANADIG_PFD_528_SYS_PFD3_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_528_SYS_PFD3_FRAC) +#define BM_ANADIG_PFD_528_SYS_PFD2_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_528_SYS_PFD2_STABLE 0x00004000 +#define BP_ANADIG_PFD_528_SYS_PFD2_FRAC 8 +#define BM_ANADIG_PFD_528_SYS_PFD2_FRAC 0x00003F00 +#define BF_ANADIG_PFD_528_SYS_PFD2_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_528_SYS_PFD2_FRAC) +#define BM_ANADIG_PFD_528_SYS_PFD1_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_528_SYS_PFD1_STABLE 0x00000040 +#define BP_ANADIG_PFD_528_SYS_PFD1_FRAC 0 +#define BM_ANADIG_PFD_528_SYS_PFD1_FRAC 0x0000003F +#define BF_ANADIG_PFD_528_SYS_PFD1_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_528_SYS_PFD1_FRAC) + +#define HW_ANADIG_PLL_LOCK (0x000002C0) + +#define BP_ANADIG_PLL_LOCK_RSVD0 7 +#define BM_ANADIG_PLL_LOCK_RSVD0 0xFFFFFF80 +#define BF_ANADIG_PLL_LOCK_RSVD0(v) \ + (((v) << 7) & BM_ANADIG_PLL_LOCK_RSVD0) +#define BM_ANADIG_PLL_LOCK_PLL_528_SYS_LOCK 0x00000040 +#define BM_ANADIG_PLL_LOCK_PLL_528_LOCK 0x00000020 +#define BM_ANADIG_PLL_LOCK_PLL_AUDIO_LOCK 0x00000010 +#define BM_ANADIG_PLL_LOCK_PLL_VIDEO_LOCK 0x00000008 +#define BM_ANADIG_PLL_LOCK_PLL_ENET_LOCK 0x00000004 +#define BM_ANADIG_PLL_LOCK_PLL_USB1_LOCK 0x00000002 +#define BM_ANADIG_PLL_LOCK_PLL_USB2_LOCK 0x00000001 + +#endif /* __ARCH_ARM___ANADIG_H */ diff --git a/arch/arm/mach-mvf/serial.h b/arch/arm/mach-mvf/serial.h new file mode 100644 index 000000000000..c510b59b6b7d --- /dev/null +++ b/arch/arm/mach-mvf/serial.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM_MACH_MX51_SERIAL_H__ +#define __ARCH_ARM_MACH_MX51_SERIAL_H__ + +/* UART 1 configuration */ +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +#define UART1_DMA_ENABLE 0 +/* UART 2 configuration */ +#define UART2_UCR4_CTSTL -1 +#define UART2_DMA_ENABLE 1 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 0 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_UCR4_CTSTL -1 +#define UART4_DMA_ENABLE 0 +#define UART4_DMA_RXBUFSIZE 512 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* UART 5 configuration */ +#define UART5_UCR4_CTSTL -1 +#define UART5_DMA_ENABLE 0 +#define UART5_DMA_RXBUFSIZE 512 +#define UART5_UFCR_RXTL 16 +#define UART5_UFCR_TXTL 16 + +#endif /* __ARCH_ARM_MACH_MX51_SERIAL_H__ */ diff --git a/arch/arm/mach-mvf/src-reg.h b/arch/arm/mach-mvf/src-reg.h new file mode 100644 index 000000000000..e1217f3b04cb --- /dev/null +++ b/arch/arm/mach-mvf/src-reg.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 1.3 + */ +#ifndef _SRC_REGISTER_HEADER_ +#define _SRC_REGISTER_HEADER_ + +#define SRC_SCR_OFFSET 0x000 +#define SRC_SBMR1_OFFSET 0x004 +#define SRC_SRSR_OFFSET 0x008 +#define SRC_SECR_OFFSET 0x00c +#define SRC_GPSR_OFFSET 0x010 +#define SRC_SISR_OFFSET 0x014 +#define SRC_SIMR_OFFSET 0x018 +#define SRC_SBMR2_OFFSET 0x01c +#define SRC_GPR0_OFFSET 0x020 +#define SRC_GPR1_OFFSET 0x024 +#define SRC_GPR2_OFFSET 0x028 +#define SRC_GPR3_OFFSET 0x02c +#define SRC_GPR4_OFFSET 0x030 +#define SRC_HAB0_OFFSET 0x034 +#define SRC_HAB1_OFFSET 0x038 +#define SRC_HAB2_OFFSET 0x03c +#define SRC_HAB3_OFFSET 0x040 +#define SRC_HAB4_OFFSET 0x044 +#define SRC_HAB5_OFFSET 0x048 +#define SRC_MISC0_OFFSET 0x04c +#define SRC_MISC1_OFFSET 0x050 +#define SRC_MISC2_OFFSET 0x054 +#define SRC_MISC3_OFFSET 0x058 + +#endif diff --git a/arch/arm/mach-mvf/system.c b/arch/arm/mach-mvf/system.c new file mode 100644 index 000000000000..0eb6592969dd --- /dev/null +++ b/arch/arm/mach-mvf/system.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/pmic_external.h> +#include <asm/io.h> +#include <mach/hardware.h> +#include <mach/clock.h> +#include <asm/proc-fns.h> +#include <asm/system.h> +#include "crm_regs.h" +#include "regs-anadig.h" + +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 +#define GPC_CNTR_OFFSET 0x0 +#define GPC_PGC_GPU_PGCR_OFFSET 0x260 +#define GPC_PGC_CPU_PDN_OFFSET 0x2a0 +#define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 +#define GPC_PGC_CPU_PDNSCR_OFFSET 0x2a8 + +#define MODULE_CLKGATE (1 << 30) +#define MODULE_SFTRST (1 << 31) + +extern unsigned int gpc_wake_irq[4]; +extern int mx6q_revision(void); + +static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR); + +extern void (*mx6_wait_in_iram)(void); +extern void mx6_wait(void); +extern void *mx6_wait_in_iram_base; +extern bool enable_wait_mode; + +void gpc_set_wakeup(unsigned int irq[4]) +{ + /* Mask all wake up source */ + __raw_writel(~irq[0], gpc_base + 0x8); + __raw_writel(~irq[1], gpc_base + 0xc); + __raw_writel(~irq[2], gpc_base + 0x10); + __raw_writel(~irq[3], gpc_base + 0x14); + + return; +} +/* set cpu low power mode before WFI instruction */ +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + + int stop_mode = 0; + void __iomem *anatop_base = IO_ADDRESS(ANATOP_BASE_ADDR); + u32 ccm_clpcr, anatop_val; + + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; + break; + case WAIT_UNCLOCKED_POWER_OFF: + case STOP_POWER_OFF: + case ARM_POWER_OFF: + if (mode == WAIT_UNCLOCKED_POWER_OFF) { + ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; + ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; + ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + stop_mode = 0; + } else if (mode == STOP_POWER_OFF) { + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + stop_mode = 1; + } else { + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + stop_mode = 2; + } + break; + case STOP_POWER_ON: + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + + break; + default: + printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); + return; + } + + if (stop_mode > 0) { + gpc_set_wakeup(gpc_wake_irq); + /* Power down and power up sequence */ + __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); + __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); + + /* dormant mode, need to power off the arm core */ + if (stop_mode == 2) { + __raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET); + __raw_writel(0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(0x1, gpc_base + GPC_CNTR_OFFSET); + if (cpu_is_mx6q()) { + /* Enable weak 2P5 linear regulator */ + anatop_val = __raw_readl(anatop_base + + HW_ANADIG_REG_2P5); + anatop_val |= BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG; + __raw_writel(anatop_val, anatop_base + + HW_ANADIG_REG_2P5); + if (mx6q_revision() != IMX_CHIP_REVISION_1_0) { + /* Enable fet_odrive */ + anatop_val = __raw_readl(anatop_base + + HW_ANADIG_REG_CORE); + anatop_val |= BM_ANADIG_REG_CORE_FET_ODRIVE; + __raw_writel(anatop_val, anatop_base + + HW_ANADIG_REG_CORE); + } + } + if (cpu_is_mx6q()) + __raw_writel(__raw_readl(MXC_CCM_CCR) | + MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR); + /* Make sure we clear WB_COUNT and re-config it */ + __raw_writel(__raw_readl(MXC_CCM_CCR) & + (~MXC_CCM_CCR_WB_COUNT_MASK), MXC_CCM_CCR); + udelay(50); + __raw_writel(__raw_readl(MXC_CCM_CCR) | (0x1 << + MXC_CCM_CCR_WB_COUNT_OFFSET), MXC_CCM_CCR); + ccm_clpcr |= MXC_CCM_CLPCR_WB_PER_AT_LPM; + } + } + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); +} + + void arch_idle(void) +{ + if (enable_wait_mode) { + if ((num_online_cpus() == num_present_cpus()) + && mx6_wait_in_iram != NULL) { + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + if (smp_processor_id() == 0) + mx6_wait_in_iram(); + else + cpu_do_idle(); + } + } else + cpu_do_idle(); +} + +static int __mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + u32 c; + int timeout; + + /* the process of software reset of IP block is done + in several steps: + + - clear SFTRST and wait for block is enabled; + - clear clock gating (CLKGATE bit); + - set the SFTRST again and wait for block is in reset; + - clear SFTRST and wait for reset completion. + */ + c = __raw_readl(hwreg); + c &= ~MODULE_SFTRST; /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & MODULE_SFTRST) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~MODULE_CLKGATE; /* clear CLKGATE */ + __raw_writel(c, hwreg); + + if (!just_enable) { + c = __raw_readl(hwreg); + c |= MODULE_SFTRST; /* now again set SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* poll until CLKGATE set */ + if (__raw_readl(hwreg) & MODULE_CLKGATE) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when resetting\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~MODULE_SFTRST; /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & MODULE_SFTRST) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling " + "after reset\n", __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~MODULE_CLKGATE; /* clear CLKGATE */ + __raw_writel(c, hwreg); + } + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & MODULE_CLKGATE) == 0) + break; + + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when unclockgating\n", + __func__, hwreg); + return -ETIME; + } + + return 0; +} + +static int _mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + int try = 10; + int r; + + while (try--) { + r = __mxs_reset_block(hwreg, just_enable); + if (!r) + break; + pr_debug("%s: try %d failed\n", __func__, 10 - try); + } + return r; +} + +int mxs_reset_block(void __iomem *hwreg) +{ + return _mxs_reset_block(hwreg, false); +} +EXPORT_SYMBOL(mxs_reset_block); diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index e708ed448585..d1b89e1ec4f1 100755 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -54,11 +54,18 @@ config ARCH_MX6 help This enable support for systems based on the Freescale i.MX 6 Series family +config ARCH_MVF + bool "MVF-based" + select CPU_V7 + help + This enable support for systems based on the Freescale MVF Series family + endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx5/Kconfig" source "arch/arm/mach-mx6/Kconfig" +source "arch/arm/mach-mvf/Kconfig" endmenu ## Freescale private USB driver support @@ -133,6 +140,9 @@ config IMX_HAVE_IOMUX_V1 config ARCH_MXC_IOMUX_V3 bool +config ARCH_MXC_IOMUX_VMVF + bool + config ARCH_MXC_AUDMUX_V1 bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 6ff1c9072104..08bdb2eb7fb1 100755 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,7 +3,15 @@ # # Common support -obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o +obj-y := clock.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o + +ifdef CONFIG_ARCH_MVF +obj-y += mvf_gpio.o +obj-y += mvf_time.o +else +obj-y += gpio.o +obj-y += time.o +endif # MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o @@ -11,6 +19,7 @@ obj-$(CONFIG_MXC_AVIC) += avic.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o +obj-$(CONFIG_ARCH_MXC_IOMUX_VMVF) += iomux-vmvf.o obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_MXC_ULPI) += ulpi.o diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index a2747f12813e..57735a00e8e4 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -19,6 +19,9 @@ #ifndef __ASM_ARCH_MXC_GPIO_H__ #define __ASM_ARCH_MXC_GPIO_H__ +#ifdef CONFIG_ARCH_MVF +#include <mach/mvf_gpio.h> +#else #include <linux/spinlock.h> #include <mach/hardware.h> #include <asm-generic/gpio.h> @@ -64,3 +67,4 @@ struct mxc_gpio_port { int mxc_gpio_init(struct mxc_gpio_port*, int); #endif +#endif diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index e1c523443ca8..482cd49e2b20 100755 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -131,6 +131,10 @@ # include <mach/mx25.h> #endif +#ifdef CONFIG_ARCH_MVF +# include <mach/mvf.h> +#endif + #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h b/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h new file mode 100644 index 000000000000..ac59b9e6082a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h @@ -0,0 +1,3692 @@ +/* + * based on arch/arm/plat-mxc/include/mach/iomux-mx6q.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Auto Generate file, please don't edit it + * + */ + +#ifndef __MACH_IOMUX_VF6XX_H__ +#define __MACH_IOMUX_VF6XX_H__ + +#include <mach/iomux-vmvf.h> + +#if 0 +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + } iomux_pin_cfg_t; + +#define VF6XX_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VF6XX_HIGH_DRV (PAD_CTL_DSE_120ohm) + +#define VF6XX_MLB150_PAD_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) \ + +#define VF6XX_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VF6XX_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VF6XX_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VF6XX_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VF6XX_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define VF6XX_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define VF6XX_GPIO_16_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define VF6XX_DISP_PAD_CLT VF6XX_HIGH_DRV + +#define VF6XX_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED) + +#define VF6XX_ESAI_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define VF6XX_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define VF6XX_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) +#define VF6XX_GPMI_PAD_CTRL2 (VF6XX_GPMI_PAD_CTRL0 | VF6XX_GPMI_PAD_CTRL1) + +#define VF6XX_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) +#define VF6XX_USB_HSIC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm) + +#define VF6XX_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#endif + +#define _VF6XX_PAD_PAD_0__RGPIOC_GPIO0 \ + IOMUX_PAD(0x0000, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_0__CCM_RMII_CLKOUT \ + IOMUX_PAD(0x0000, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_0__CCM_RMII_CLKIN \ + IOMUX_PAD(0x0000, MUX_CTL_PAD_MUX_MODE_ALT2, 0x2F0, 0) +#define _VF6XX_PAD_PAD_0__TCON1_TCON11 \ + IOMUX_PAD(0x0000, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_0__TCON1_DATA_OUT20 \ + IOMUX_PAD(0x0000, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_1__RGPIOC_GPIO1 \ + IOMUX_PAD(0x0004, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_1__DEBUG_TCLK \ + IOMUX_PAD(0x0004, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_1__TCON0_DATA_OUT18 \ + IOMUX_PAD(0x0004, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_1__MLB_TOP_MLBCLK \ + IOMUX_PAD(0x0004, MUX_CTL_PAD_MUX_MODE_ALT7, 0x354, 0) + +#define _VF6XX_PAD_PAD_2__RGPIOC_GPIO2 \ + IOMUX_PAD(0x0008, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_2__DEBUG_TDI \ + IOMUX_PAD(0x0008, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_2__CCM_RMII_CLKOUT \ + IOMUX_PAD(0x0008, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_2__CCM_RMII_CLKIN \ + IOMUX_PAD(0x0008, MUX_CTL_PAD_MUX_MODE_ALT3, 0x2F0, 1) +#define _VF6XX_PAD_PAD_2__TCON0_DATA_OUT19 \ + IOMUX_PAD(0x0008, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_2__IPP_WDOG_CA5_CM4 \ + IOMUX_PAD(0x0008, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_3__RGPIOC_GPIO3 \ + IOMUX_PAD(0x000C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_3__DEBUG_TDO \ + IOMUX_PAD(0x000C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_3__CCM_EXT_AUDIO_MCLK \ + IOMUX_PAD(0x000C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x2EC, 0) +#define _VF6XX_PAD_PAD_3__TCON0_DATA_OUT10 \ + IOMUX_PAD(0x000C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_3__CCM_ENET_TS_CLKIN \ + IOMUX_PAD(0x000C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x2F4, 0) +#define _VF6XX_PAD_PAD_3__MLB_TOP_MLBSIGNAL \ + IOMUX_PAD(0x000C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x35C, 0) + +#define _VF6XX_PAD_PAD_4__RGPIOC_GPIO4 \ + IOMUX_PAD(0x0010, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_4__DEBUG_TMS \ + IOMUX_PAD(0x0010, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_4__TCON0_DATA_OUT11 \ + IOMUX_PAD(0x0010, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_4__MLB_TOP_MLB_DATA \ + IOMUX_PAD(0x0010, MUX_CTL_PAD_MUX_MODE_ALT7, 0x358, 0) + +#define _VF6XX_PAD_PAD_5__RGPIOC_GPIO5 \ + IOMUX_PAD(0x0014, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_5__PLATFORM_TRACECK \ + IOMUX_PAD(0x0014, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_5__CCM_EXT_AUDIO_MCLK \ + IOMUX_PAD(0x0014, MUX_CTL_PAD_MUX_MODE_ALT2, 0x2EC, 1) +#define _VF6XX_PAD_PAD_5__VIDEO_IN0_DATA13 \ + IOMUX_PAD(0x0014, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_5__I2C0_SCL \ + IOMUX_PAD(0x0014, MUX_CTL_PAD_MUX_MODE_ALT7, 0x33C, 0) + +#define _VF6XX_PAD_PAD_6__RGPIOC_GPIO6 \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_6__PLATFORM_TRACED0 \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_6__USB_VBUS_EN_OTG \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_6__ADC1_DA_ADC1SE0 \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_6__LCD_64F6B_LCD29 \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_6__SAI2_TX_BCLK \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT5, 0x370, 0) +#define _VF6XX_PAD_PAD_6__VIDEO_IN0_DATA14 \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_6__I2C0_SDA \ + IOMUX_PAD(0x0018, MUX_CTL_PAD_MUX_MODE_ALT7, 0x340, 0) + +#define _VF6XX_PAD_PAD_7__RGPIOC_GPIO7 \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_7__PLATFORM_TRACED1 \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_7__USB_VBUS_OC_OTG \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_7__ADC1_DA_ADC1SE1 \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_7__LCD_64F6B_LCD30 \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_7__USB_USB0_SOF_PULSE \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_7__VIDEO_IN0_DATA15 \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_7__I2C1_SCL \ + IOMUX_PAD(0x001C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x344, 0) + +#define _VF6XX_PAD_PAD_8__RGPIOC_GPIO8 \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_8__PLATFORM_TRACED2 \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_8__ADC0_DA_ADC0SE0 \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_8__FLEXTIMER1_QD_PHA \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT3, 0x334, 0) +#define _VF6XX_PAD_PAD_8__LCD_64F6B_LCD31 \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_8__SAI2_TX_DATA \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_8__VIDEO_IN0_DATA16 \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_8__I2C1_SDA \ + IOMUX_PAD(0x0020, MUX_CTL_PAD_MUX_MODE_ALT7, 0x348, 0) + +#define _VF6XX_PAD_PAD_9__RGPIOC_GPIO9 \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_9__PLATFORM_TRACED3 \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_9__ADC0_DA_ADC0SE1 \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_9__FLEXTIMER1_QD_PHB \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT3, 0x338, 0) +#define _VF6XX_PAD_PAD_9__LCD_64F6B_LCD32 \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_9__SAI2_TX_SYNC \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT5, 0x374, 0) +#define _VF6XX_PAD_PAD_9__VIDEO_IN0_DATA17 \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_9__QUADSPI1_QSCK_A \ + IOMUX_PAD(0x0024, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_10__RGPIOC_GPIO10 \ + IOMUX_PAD(0x0028, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_10__PLATFORM_TRACED4 \ + IOMUX_PAD(0x0028, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_10__LCD_64F6B_LCD33 \ + IOMUX_PAD(0x0028, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_10__SCI_FLX3_TX \ + IOMUX_PAD(0x0028, MUX_CTL_PAD_MUX_MODE_ALT6, 0x394, 0) +#define _VF6XX_PAD_PAD_10__TCON1_TCON1 \ + IOMUX_PAD(0x0028, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_11__RGPIOC_GPIO11 \ + IOMUX_PAD(0x002C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_11__PLATFORM_TRACED5 \ + IOMUX_PAD(0x002C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_11__SAI2_RX_BCLK \ + IOMUX_PAD(0x002C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x364, 0) +#define _VF6XX_PAD_PAD_11__SCI_FLX3_RX \ + IOMUX_PAD(0x002C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x390, 0) +#define _VF6XX_PAD_PAD_11__TCON1_TCON2 \ + IOMUX_PAD(0x002C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_12__RGPIOC_GPIO12 \ + IOMUX_PAD(0x0030, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_12__PLATFORM_TRACED6 \ + IOMUX_PAD(0x0030, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_12__SAI2_RX_DATA \ + IOMUX_PAD(0x0030, MUX_CTL_PAD_MUX_MODE_ALT5, 0x368, 0) +#define _VF6XX_PAD_PAD_12__I2C2_SCL \ + IOMUX_PAD(0x0030, MUX_CTL_PAD_MUX_MODE_ALT6, 0x34C, 0) +#define _VF6XX_PAD_PAD_12__TCON1_TCON0 \ + IOMUX_PAD(0x0030, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_13__RGPIOC_GPIO13 \ + IOMUX_PAD(0x0034, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_13__PLATFORM_TRACED7 \ + IOMUX_PAD(0x0034, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_13__SAI2_RX_SYNC \ + IOMUX_PAD(0x0034, MUX_CTL_PAD_MUX_MODE_ALT5, 0x36C, 0) +#define _VF6XX_PAD_PAD_13__I2C2_SDA \ + IOMUX_PAD(0x0034, MUX_CTL_PAD_MUX_MODE_ALT6, 0x350, 0) +#define _VF6XX_PAD_PAD_13__TCON1_TCON3 \ + IOMUX_PAD(0x0034, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_14__RGPIOC_GPIO14 \ + IOMUX_PAD(0x0038, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_14__PLATFORM_TRACED8 \ + IOMUX_PAD(0x0038, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_14__USB_VBUS_EN \ + IOMUX_PAD(0x0038, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_14__ESDHC1_CLK \ + IOMUX_PAD(0x0038, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_14__TCON1_TCON4 \ + IOMUX_PAD(0x0038, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_14__DDR_TEST_LOGIC_PAD_CTRL \ + IOMUX_PAD(0x0038, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_15__RGPIOC_GPIO15 \ + IOMUX_PAD(0x003C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_15__PLATFORM_TRACED9 \ + IOMUX_PAD(0x003C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_15__USB_VBUS_OC \ + IOMUX_PAD(0x003C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_15__ESDHC1_CMD \ + IOMUX_PAD(0x003C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_15__TCON1_TCON5 \ + IOMUX_PAD(0x003C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_16__RGPIOC_GPIO16 \ + IOMUX_PAD(0x0040, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_16__PLATFORM_TRACED10 \ + IOMUX_PAD(0x0040, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_16__SAI3_TX_BCLK \ + IOMUX_PAD(0x0040, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_16__ESDHC1_DAT0 \ + IOMUX_PAD(0x0040, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_16__TCON1_TCON6 \ + IOMUX_PAD(0x0040, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_17__RGPIOC_GPIO17 \ + IOMUX_PAD(0x0044, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_17__PLATFORM_TRACED11 \ + IOMUX_PAD(0x0044, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_17__SAI3_RX_BCLK \ + IOMUX_PAD(0x0044, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_17__ESDHC1_DAT1 \ + IOMUX_PAD(0x0044, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_17__TCON1_TCON7 \ + IOMUX_PAD(0x0044, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_18__RGPIOC_GPIO18 \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_18__PLATFORM_TRACED12 \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_18__SAI3_RX_DATA \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_18__ENET_SWIAHB_MAC1_TMR0 \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_18__SCI_FLX4_TX \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_18__ESDHC1_DAT2 \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_18__TCON1_TCON8 \ + IOMUX_PAD(0x0048, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_19__RGPIOC_GPIO19 \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_19__PLATFORM_TRACED13 \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_19__SAI3_TX_DATA \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_19__ENET_SWIAHB_MAC1_TMR1 \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_19__SCI_FLX4_RX \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_19__ESDHC1_DAT3 \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_19__TCON1_TCON9 \ + IOMUX_PAD(0x004C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_20__RGPIOC_GPIO20 \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_20__PLATFORM_TRACED14 \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_20__SAI3_RX_SYNC \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_20__ENET_SWIAHB_MAC1_TMR2 \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_20__SCI_FLX4_RTS \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_20__I2C3_SCL \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_20__SCI_FLX3_RTS \ + IOMUX_PAD(0x0050, MUX_CTL_PAD_MUX_MODE_ALT7, 0x394, 1) + +#define _VF6XX_PAD_PAD_21__RGPIOC_GPIO21 \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_21__PLATFORM_TRACED15 \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_21__SAI3_TX_SYNC \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_21__ENET_SWIAHB_MAC1_TMR3 \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_21__SCI_FLX4_CTS \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_21__I2C3_SDA \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_21__SCI_FLX3_TX_SYNC \ + IOMUX_PAD(0x0054, MUX_CTL_PAD_MUX_MODE_ALT7, 0x390, 1) + +#define _VF6XX_PAD_PAD_22__RGPIOC_GPIO22 \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_22__FLEXTIMER0_CH0 \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_22__ADC0_DA_ADC0SE2 \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_22__PLATFORM_TRACECTL \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_22__LCD_64F6B_LCD34 \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_22__SAI2_RX_BCLK \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT5, 0x364, 1) +#define _VF6XX_PAD_PAD_22__VIDEO_IN0_DATA18 \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_22__QUADSPI1_QPCS0_A \ + IOMUX_PAD(0x0058, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_23__RGPIOC_GPIO23 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_23__FLEXTIMER0_CH1 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_23__ADC0_DA_ADC0SE3 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_23__SRC_RCON30 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_23__LCD_64F6B_LCD35 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_23__SAI2_RX_DATA \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x368, 1) +#define _VF6XX_PAD_PAD_23__VIDEO_IN0_DATA19 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_23__QUADSPI1_QSPI_IO3 \ + IOMUX_PAD(0x005C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_24__RGPIOC_GPIO24 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_24__FLEXTIMER0_CH2 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_24__ADC1_DA_ADC1SE2 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_24__SRC_RCON31 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_24__LCD_64F6B_LCD36 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_24__SAI2_RX_SYNC \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT5, 0x36C, 1) +#define _VF6XX_PAD_PAD_24__VIDEO_IN0_DATA20 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_24__QUADSPI1_QSPI_IO2 \ + IOMUX_PAD(0x0060, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_25__RGPIOC_GPIO25 \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_25__FLEXTIMER0_CH3 \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_25__ADC1_DA_ADC1SE3 \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_25__PDB_EXTRING \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_25__LCD_64F6B_LCD37 \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_25__VIDEO_IN0_DATA21 \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_25__QUADSPI1_QSPI_IO1 \ + IOMUX_PAD(0x0064, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_26__RGPIOC_GPIO26 \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_26__FLEXTIMER0_CH4 \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_26__SCI_FLX1_TX \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT2, 0x380, 0) +#define _VF6XX_PAD_PAD_26__ADC0_DA_ADC0SE4 \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_26__LCD_64F6B_LCD38 \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_26__VIDEO_IN0_VIU_FID \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT5, 0x3A8, 0) +#define _VF6XX_PAD_PAD_26__VIDEO_IN0_DATA22 \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_26__QUADSPI1_QSPI_IO0 \ + IOMUX_PAD(0x0068, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_27__RGPIOC_GPIO27 \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_27__FLEXTIMER0_CH5 \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_27__SCI_FLX1_RX \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x37C, 0) +#define _VF6XX_PAD_PAD_27__ADC1_DA_ADC1SE4 \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_27__LCD_64F6B_LCD39 \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_27__VIDEO_IN0_VIU_DE \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x3A4, 0) +#define _VF6XX_PAD_PAD_27__VIDEO_IN0_DATA23 \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_27__QUADSPI1_DQS_A \ + IOMUX_PAD(0x006C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + + +#define _VF6XX_PAD_PAD_28__RGPIOC_GPIO28 \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_28__FLEXTIMER0_CH6 \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_28__SCI_FLX1_RTS \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_28__QUADSPI0_QPCS1_A \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_28__LCD_64F6B_LCD40 \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_28__LPCG0_FB_CLKOUT \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_28__VIDEO_IN0_HSYNC \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_28__SCI_FLX2_TX \ + IOMUX_PAD(0x0070, MUX_CTL_PAD_MUX_MODE_ALT7, 0x38C, 0) + +#define _VF6XX_PAD_PAD_29__RGPIOC_GPIO29 \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_29__FLEXTIMER0_CH7 \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_29__SCI_FLX1_CTS \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT2, 0x378, 0) +#define _VF6XX_PAD_PAD_29__QUADSPI0_QPCS1_B \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_29__LCD_64F6B_LCD41 \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_29__VIDEO_IN0_VSYNC \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_29__SCI_FLX2_RX \ + IOMUX_PAD(0x0074, MUX_CTL_PAD_MUX_MODE_ALT7, 0x388, 0) + +#define _VF6XX_PAD_PAD_30__RGPIOC_GPIO30 \ + IOMUX_PAD(0x0078, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_30__FLEXTIMER1_CH0 \ + IOMUX_PAD(0x0078, MUX_CTL_PAD_MUX_MODE_ALT1, 0x32C, 0) +#define _VF6XX_PAD_PAD_30__FLEXTIMER0_QD_PHA \ + IOMUX_PAD(0x0078, MUX_CTL_PAD_MUX_MODE_ALT3, 0x334, 1) +#define _VF6XX_PAD_PAD_30__VIDEO_IN0_VIU_DE \ + IOMUX_PAD(0x0078, MUX_CTL_PAD_MUX_MODE_ALT5, 0x3A4, 1) +#define _VF6XX_PAD_PAD_30__TCON1_DATA_OUT24 \ + IOMUX_PAD(0x0078, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_31__RGPIOC_GPIO31 \ + IOMUX_PAD(0x007C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_31__FLEXTIMER1_CH1 \ + IOMUX_PAD(0x007C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x330, 0) +#define _VF6XX_PAD_PAD_31__FLEXTIMER1_QD_PHB \ + IOMUX_PAD(0x007C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x338, 1) +#define _VF6XX_PAD_PAD_31__TCON1_DATA_OUT25 \ + IOMUX_PAD(0x007C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_32__RGPIOC_GPIO32 \ + IOMUX_PAD(0x0080, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_32__SCI_FLX0_TX \ + IOMUX_PAD(0x0080, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_32__TCON0_TCON4 \ + IOMUX_PAD(0x0080, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_32__VIDEO_IN0_VIU_DE \ + IOMUX_PAD(0x0080, MUX_CTL_PAD_MUX_MODE_ALT5, 0x3A4, 2) +#define _VF6XX_PAD_PAD_32__CCM_CKO1 \ + IOMUX_PAD(0x0080, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_32__CCM_ENET_TS_CLKIN \ + IOMUX_PAD(0x0080, MUX_CTL_PAD_MUX_MODE_ALT7, 0x2F4, 1) + +#define _VF6XX_PAD_PAD_33__RGPIOC_GPIO33 \ + IOMUX_PAD(0x0084, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_33__SCI_FLX0_RX \ + IOMUX_PAD(0x0084, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_33__TCON0_TCON5 \ + IOMUX_PAD(0x0084, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_33__SNVS_LP_WRAPPER_SNVS_ALARM_OUT \ + IOMUX_PAD(0x0084, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_33__CCM_CKO2 \ + IOMUX_PAD(0x0084, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_33__ENET_SWIAHB_MAC0_TMR0 \ + IOMUX_PAD(0x0084, MUX_CTL_PAD_MUX_MODE_ALT7, 0x304, 0) + +#define _VF6XX_PAD_PAD_34__RGPIOC_GPIO34 \ + IOMUX_PAD(0x0088, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_34__SCI_FLX0_RTS \ + IOMUX_PAD(0x0088, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_34__DSPI0_CS5 \ + IOMUX_PAD(0x0088, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_34__TCON0_TCON6 \ + IOMUX_PAD(0x0088, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_34__PLATFORM_FB_AD1 \ + IOMUX_PAD(0x0088, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_34__ENET_SWIAHB_MAC0_TMR1 \ + IOMUX_PAD(0x0088, MUX_CTL_PAD_MUX_MODE_ALT7, 0x308, 0) + +#define _VF6XX_PAD_PAD_35__RGPIOC_GPIO35 \ + IOMUX_PAD(0x008C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_35__SCI_FLX0_CTS \ + IOMUX_PAD(0x008C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_35__DSPI0_CS4 \ + IOMUX_PAD(0x008C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_35__TCON0_TCON7 \ + IOMUX_PAD(0x008C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_35__PLATFORM_FB_AD0 \ + IOMUX_PAD(0x008C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_35__PLATFORM_TRACETL \ + IOMUX_PAD(0x008C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) + +#define _VF6XX_PAD_PAD_36__RGPIOC_GPIO36 \ + IOMUX_PAD(0x0090, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_36__CAN0_RXD \ + IOMUX_PAD(0x0090, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_36__I2C0_SCL \ + IOMUX_PAD(0x0090, MUX_CTL_PAD_MUX_MODE_ALT2, 0x33C, 1) +#define _VF6XX_PAD_PAD_36__TCON0_TCON8 \ + IOMUX_PAD(0x0090, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_36__TCON1_DATA_OUT1 \ + IOMUX_PAD(0x0090, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_37__RGPIOC_GPIO37 \ + IOMUX_PAD(0x0094, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_37__CAN0_TXD \ + IOMUX_PAD(0x0094, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_37__I2C0_SDA \ + IOMUX_PAD(0x0094, MUX_CTL_PAD_MUX_MODE_ALT2, 0x340, 1) +#define _VF6XX_PAD_PAD_37__TCON0_TCON9 \ + IOMUX_PAD(0x0094, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_37__VIDEO_IN0_PIX_CLK \ + IOMUX_PAD(0x0094, MUX_CTL_PAD_MUX_MODE_ALT7, 0x3AC, 0) + +#define _VF6XX_PAD_PAD_38__RGPIOC_GPIO38 \ + IOMUX_PAD(0x0098, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_38__CAN1_RXD \ + IOMUX_PAD(0x0098, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_38__I2C1_SCL \ + IOMUX_PAD(0x0098, MUX_CTL_PAD_MUX_MODE_ALT2, 0x344, 1) +#define _VF6XX_PAD_PAD_38__TCON0_TCON10 \ + IOMUX_PAD(0x0098, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_39__RGPIOC_GPIO39 \ + IOMUX_PAD(0x009C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_39__CAN1_TXD \ + IOMUX_PAD(0x009C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_39__I2C1_SDA \ + IOMUX_PAD(0x009C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x348, 1) +#define _VF6XX_PAD_PAD_39__TCON0_TCON11 \ + IOMUX_PAD(0x009C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_40__RGPIOC_GPIO40 \ + IOMUX_PAD(0x00A0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_40__DSPI0_CS1 \ + IOMUX_PAD(0x00A0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_40__CCM_EXT_AUDIO_MCLK \ + IOMUX_PAD(0x00A0, MUX_CTL_PAD_MUX_MODE_ALT2, 0x2EC, 2) +#define _VF6XX_PAD_PAD_40__VIDEO_IN0_DATA9 \ + IOMUX_PAD(0x00A0, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_40__CCM_CCMOBS0 \ + IOMUX_PAD(0x00A0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_41__RGPIOC_GPIO41 \ + IOMUX_PAD(0x00A4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_41__DSPI0_CS0 \ + IOMUX_PAD(0x00A4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_41__VIDEO_IN0_DATA10 \ + IOMUX_PAD(0x00A4, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_41__CCM_CCMOBS1 \ + IOMUX_PAD(0x00A4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_42__RGPIOC_GPIO42 \ + IOMUX_PAD(0x00A8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_42__DSPI0_SIN \ + IOMUX_PAD(0x00A8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_42__LCD_64F6B_LCD42 \ + IOMUX_PAD(0x00A8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_42__VIDEO_IN0_DATA11 \ + IOMUX_PAD(0x00A8, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_42__CCM_CCMOBS2 \ + IOMUX_PAD(0x00A8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_43__RGPIOC_GPIO43 \ + IOMUX_PAD(0x00AC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_43__DSPI0_SOUT \ + IOMUX_PAD(0x00AC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_43__LCD_64F6B_LCD43 \ + IOMUX_PAD(0x00AC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_43__VIDEO_IN0_DATA2 \ + IOMUX_PAD(0x00AC, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_43__TCON1_DATA_OUT1 \ + IOMUX_PAD(0x00AC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_44__RGPIOC_GPIO44 \ + IOMUX_PAD(0x00B0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_44__DSPI0_SCK \ + IOMUX_PAD(0x00B0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_44__VIDEO_IN0_VIU_FID \ + IOMUX_PAD(0x00B0, MUX_CTL_PAD_MUX_MODE_ALT5, 0x3A8, 1) + +#define _VF6XX_PAD_PAD_45__RGPIOC_GPIO45 \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_45__ENET_SWIAHB_RMII0_MDC \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_45__FLEXTIMER1_CH0 \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT2, 0x32C, 1) +#define _VF6XX_PAD_PAD_45__DSPI0_CS3 \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_45__ESABI_SCKT \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x310, 0) +#define _VF6XX_PAD_PAD_45__ESDHC0_CLK \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_45__VIDEO_IN0_DATA0 \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_45__SRC_RCON18 \ + IOMUX_PAD(0x00B4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x398, 0) + +#define _VF6XX_PAD_PAD_46__RGPIOC_GPIO46 \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_46__ENET_SWIAHB_RMII0_MDIO \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_46__FLEXTIMER1_CH1 \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT2, 0x330, 1) +#define _VF6XX_PAD_PAD_46__DSPI0_CS2 \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_46__ESAI_FST \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x30C, 0) +#define _VF6XX_PAD_PAD_46__ESDHC0_CMD \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_46__VIDEO_IN0_DATA1 \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_46__SRC_RCON19 \ + IOMUX_PAD(0x00B8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x39C, 0) + +#define _VF6XX_PAD_PAD_47__RGPIOC_GPIO47 \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_47__ENET_SWIAHB_RMII0_CRS_DV \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_47__SCI_FLX1_TX \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT2, 0x380, 1) +#define _VF6XX_PAD_PAD_47__ESAI_SDO0 \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x314, 0) +#define _VF6XX_PAD_PAD_47__ESDHC0_DAT0 \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_47__VIDEO_IN0_DATA2 \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_47__SRC_RCON20 \ + IOMUX_PAD(0x00BC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x3A0, 0) + +#define _VF6XX_PAD_PAD_48__RGPIOC_GPIO48 \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_48__ENET_SWIAHB_RMII0_RXD1 \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_48__SCI_FLX1_RX \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT2, 0x37C, 1) +#define _VF6XX_PAD_PAD_48__ESAI_SDO1 \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x318, 0) +#define _VF6XX_PAD_PAD_48__ESDHC0_DAT1 \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_48__VIDEO_IN0_DATA3 \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_48__TCON0_DATA_OUT18 \ + IOMUX_PAD(0x00C0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_49__RGPIOC_GPIO49 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_49__ENET_SWIAHB_RMII0_RXD0 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_49__SCI_FLX1_RTS \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_49__DSPI1_CS1 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_49__ESAI_SDO2 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x31C, 0) +#define _VF6XX_PAD_PAD_49__ESDHC0_DAT2 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_49__VIDEO_IN0_DATA4 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_49__TCON0_DATA_OUT19 \ + IOMUX_PAD(0x00C4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_50__RGPIOC_GPIO50 \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_50__ENET_SWIAHB_RMII0_RXER \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_50__SCI_FLX1_CTS \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT2, 0x378, 1) +#define _VF6XX_PAD_PAD_50__DSPI1_CS0 \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x300, 0) +#define _VF6XX_PAD_PAD_50__ESAI_SDO3 \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x320, 0) +#define _VF6XX_PAD_PAD_50__ESDHC0_DAT3 \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_50__VIDEO_IN0_DATA5 \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_50__TCON0_DATA_OUT10 \ + IOMUX_PAD(0x00C8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_51__RGPIOC_GPIO51 \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_51__ENET_SWIAHB_RMII0_TXD1 \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_51__DSPI1_SIN \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT3, 0x2FC, 0) +#define _VF6XX_PAD_PAD_51__ESAI_SDI0 \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x328, 0) +#define _VF6XX_PAD_PAD_51__ESDHC0_WP \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_51__VIDEO_IN0_DATA6 \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_51__TCON0_DATA_OUT11 \ + IOMUX_PAD(0x00CC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_52__RGPIOC_GPIO52 \ + IOMUX_PAD(0x00D0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_52__ENET_SWIAHB_RMII0_TXD0 \ + IOMUX_PAD(0x00D0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_52__DSPI1_SOUT \ + IOMUX_PAD(0x00D0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_52__ESAI_SDI1 \ + IOMUX_PAD(0x00D0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x324, 0) +#define _VF6XX_PAD_PAD_52__VIDEO_IN0_DATA7 \ + IOMUX_PAD(0x00D0, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_52__TCON0_DATA_OUT2 \ + IOMUX_PAD(0x00D0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_53__RGPIOC_GPIO53 \ + IOMUX_PAD(0x00D4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_53__ENET_SWIAHB_RMII0_TXEN \ + IOMUX_PAD(0x00D4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_53__DSPI1_SCK \ + IOMUX_PAD(0x00D4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x2F8, 0) +#define _VF6XX_PAD_PAD_53__VIDEO_IN0_DATA8 \ + IOMUX_PAD(0x00D4, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_53__TCON0_DATA_OUT3 \ + IOMUX_PAD(0x00D4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_54__RGPIOC_GPIO54 \ + IOMUX_PAD(0x00D8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_54__ENET_SWIAHB_RMII1_MDC \ + IOMUX_PAD(0x00D8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_54__ESAI_SCKT \ + IOMUX_PAD(0x00D8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x310, 1) +#define _VF6XX_PAD_PAD_54__MLB_TOP_MLBCLK \ + IOMUX_PAD(0x00D8, MUX_CTL_PAD_MUX_MODE_ALT6, 0x354, 1) +#define _VF6XX_PAD_PAD_54__VIU_MUX_DEBUG_OUT0 \ + IOMUX_PAD(0x00D8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_55__RGPIOC_GPIO55 \ + IOMUX_PAD(0x00DC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_55__ENET_SWIAHB_RMII1_MDIO \ + IOMUX_PAD(0x00DC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_55__ESAI_FST \ + IOMUX_PAD(0x00DC, MUX_CTL_PAD_MUX_MODE_ALT3, 0x30C, 1) +#define _VF6XX_PAD_PAD_55__MLB_TOP_MLBSIGNAL \ + IOMUX_PAD(0x00DC, MUX_CTL_PAD_MUX_MODE_ALT6, 0x35C, 1) +#define _VF6XX_PAD_PAD_55__VIU_MUX_DEBUG_OUT1 \ + IOMUX_PAD(0x00DC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_56__RGPIOC_GPIO56 \ + IOMUX_PAD(0x00E0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_56__ENET_SWIAHB_RMII1_CRS_DV \ + IOMUX_PAD(0x00E0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_56__ESAI_SDO0 \ + IOMUX_PAD(0x00E0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x314, 1) +#define _VF6XX_PAD_PAD_56__MLB_TOP_MLBDATA \ + IOMUX_PAD(0x00E0, MUX_CTL_PAD_MUX_MODE_ALT6, 0x358, 1) +#define _VF6XX_PAD_PAD_56__VIU_MUX_DEBUG_OUT2 \ + IOMUX_PAD(0x00E0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_57__RGPIOC_GPIO57 \ + IOMUX_PAD(0x00E4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_57__ENET_SWIAHB_RMII1_RXD1 \ + IOMUX_PAD(0x00E4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_57__ESAI_SDO1 \ + IOMUX_PAD(0x00E4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x318, 1) +#define _VF6XX_PAD_PAD_57__SAI2_TX_BCLK \ + IOMUX_PAD(0x00E4, MUX_CTL_PAD_MUX_MODE_ALT5, 0x370, 1) +#define _VF6XX_PAD_PAD_57__VIU_MUX_DEBUG_OUT3 \ + IOMUX_PAD(0x00E4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_58__RGPIOC_GPIO58 \ + IOMUX_PAD(0x00E8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_58__ENET_SWIAHB_RMII1_RXD0 \ + IOMUX_PAD(0x00E8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_58__ESAI_SDO2 \ + IOMUX_PAD(0x00E8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x31C, 1) +#define _VF6XX_PAD_PAD_58__SAI2_RX_BCLK \ + IOMUX_PAD(0x00E8, MUX_CTL_PAD_MUX_MODE_ALT5, 0x364, 2) +#define _VF6XX_PAD_PAD_58__VIU_MUX_DEBUG_OUT4 \ + IOMUX_PAD(0x00E8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_59__RGPIOC_GPIO59 \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_59__ENET_SWIAHB_RMII1_RXER \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_59__ESAI_SDO3 \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT3, 0x320, 1) +#define _VF6XX_PAD_PAD_59__SCI_FLX5_TX \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_59__SAI2_RX_DATA \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT5, 0x368, 2) +#define _VF6XX_PAD_PAD_59__ADC0_DA_ADC0SE6 \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_59__VIU_MUX_DEBUG_OUT5 \ + IOMUX_PAD(0x00EC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_60__RGPIOC_GPIO60 \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_60__ENET_SWIAHB_RMII1_TXD1 \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_60__ESAI_SDI0 \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x328, 1) +#define _VF6XX_PAD_PAD_60__SCI_FLX5_RX \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_60__SAI2_TX_DATA \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_60__ADC0_DA_ADC0SE7 \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_60__VIU_MUX_DEBUG_OUT6 \ + IOMUX_PAD(0x00F0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_61__RGPIOC_GPIO61 \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_61__ENET_SWIAHB_RMII1_TXD0 \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_61__ESAI_SDI1 \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x324, 1) +#define _VF6XX_PAD_PAD_61__SCI_FLX5_RTS \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_61__SAI2_RX_SYNC \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT5, 0x36C, 2) +#define _VF6XX_PAD_PAD_61__ADC1_DA_ADC1SE6 \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_61__VIU_MUX_DEBUG_OUT7 \ + IOMUX_PAD(0x00F4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_62__RGPIOC_GPIO62 \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_62__ENET_SWIAHB_RMII1_TXEN \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_62__ADC1_DA_ADC1SE7 \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_62__SCI_FLX5_CTS \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_62__SAI2_TX_SYNC \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT5, 0x374, 1) +#define _VF6XX_PAD_PAD_62__USB_VF6XX_USB1_SOF_PULSE \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_62__VIU_MUX_DEBUG_OUT8 \ + IOMUX_PAD(0x00F8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_63__RGPIOC_GPIO63 \ + IOMUX_PAD(0x00FC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_63__PLATFORM_FB_AD3 \ + IOMUX_PAD(0x00FC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_63__NFC_MLC_NF_IO15 \ + IOMUX_PAD(0x00FC, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_63__FLEXTIMER3_CH0 \ + IOMUX_PAD(0x00FC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_63__DSPI2_CS1 \ + IOMUX_PAD(0x00FC, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_63__VIU_MUX_DEBUG_OUT9 \ + IOMUX_PAD(0x00FC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_64__RGPIOC_GPIO64 \ + IOMUX_PAD(0x0100, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_64__PLATFORM_FB_AD30 \ + IOMUX_PAD(0x0100, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_64__NFC_MLC_NF_IO14 \ + IOMUX_PAD(0x0100, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_64__FLEXTIMER3_CH1 \ + IOMUX_PAD(0x0100, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_64__DSPI2_CS0 \ + IOMUX_PAD(0x0100, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_64__VIU_MUX_DEBUG_OUT10 \ + IOMUX_PAD(0x0100, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_65__RGPIOC_GPIO65 \ + IOMUX_PAD(0x0104, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_65__PLATFORM_FB_AD29 \ + IOMUX_PAD(0x0104, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_65__NFC_MLC_NF_IO13 \ + IOMUX_PAD(0x0104, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_65__FLEXTIMER3_CH2 \ + IOMUX_PAD(0x0104, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_65__DSPI2_SIN \ + IOMUX_PAD(0x0104, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_65__VIU_MUX_DEBUG_OUT11 \ + IOMUX_PAD(0x0104, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_66__RGPIOC_GPIO66 \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_66__PLATFORM_FB_AD28 \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_66__NFC_MLC_NF_IO12 \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_66__I2C2_SCL \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT3, 0x34C, 1) +#define _VF6XX_PAD_PAD_66__FLEXTIMER3_CH3 \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_66__DSPI2_SOUT \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_66__VIU_MUX_DEBUG_OUT12 \ + IOMUX_PAD(0x0108, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_67__RGPIOC_GPIO67 \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_67__PLATFORM_FB_AD27 \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_67__NFC_MLC_NF_IO11 \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_67__I2C2_SDA \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x350, 1) +#define _VF6XX_PAD_PAD_67__FLEXTIMER3_CH4 \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_67__DSPI2_SCK \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_67__VIU_MUX_DEBUG_OUT13 \ + IOMUX_PAD(0x010C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_68__RGPIOC_GPIO68 \ + IOMUX_PAD(0x0110, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_68__PLATFORM_FB_AD26 \ + IOMUX_PAD(0x0110, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_68__NFC_MLC_NF_IO10 \ + IOMUX_PAD(0x0110, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_68__FLEXTIMER3_CH5 \ + IOMUX_PAD(0x0110, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_68__ESDHC1_WP \ + IOMUX_PAD(0x0110, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_68__VIU_MUX_DEBUG_OUT14 \ + IOMUX_PAD(0x0110, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_69__RGPIOC_GPIO69 \ + IOMUX_PAD(0x0114, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_69__PLATFORM_FB_AD25 \ + IOMUX_PAD(0x0114, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_69__NFC_MLC_NF_IO9 \ + IOMUX_PAD(0x0114, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_69__FLEXTIMER3_CH6 \ + IOMUX_PAD(0x0114, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_69__VIU_MUX_DEBUG_OUT15 \ + IOMUX_PAD(0x0114, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_70__RGPIOC_GPIO70 \ + IOMUX_PAD(0x0118, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_70__PLATFORM_FB_AD24 \ + IOMUX_PAD(0x0118, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_70__NFC_MLC_NF_IO8 \ + IOMUX_PAD(0x0118, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_70__FLEXTIMER3_CH7 \ + IOMUX_PAD(0x0118, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_70__VIU_MUX_DEBUG_OUT16 \ + IOMUX_PAD(0x0118, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_71__RGPIOC_GPIO71 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_71__PLATFORM_FB_AD23 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_71__NFC_MLC_NF_IO7 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_71__FLEXTIMER2_CH0 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_71__ENET_SWIAHB_MAC0_TMR0 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x304, 1) +#define _VF6XX_PAD_PAD_71__ESDHC0_DAT4 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_71__SCI_FLX2_TX \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x38C, 1) +#define _VF6XX_PAD_PAD_71__TCON1_DATA_OUT21 \ + IOMUX_PAD(0x011C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_72__RGPIOC_GPIO72 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_72__PLATFORM_FB_AD22 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_72__NFC_MLC_NF_IO6 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_72__FLEXTIMER2_CH1 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_72__ENET_SWIAHB_MAC0_TMR1 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT4, 0x308, 1) +#define _VF6XX_PAD_PAD_72__ESDHC0_DAT5 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_72__SCI_FLX2_RX \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT6, 0x388, 1) +#define _VF6XX_PAD_PAD_72__TCON1_DATA_OUT22 \ + IOMUX_PAD(0x0120, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_73__RGPIOC_GPIO73 \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_73__PLATFORM_FB_AD21 \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_73__NFC_MLC_NF_IO5 \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_73__ENET_SWIAHB_MAC0_TMR2 \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_73__ESDHC0_DAT6 \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_73__SCI_FLX2_RTS \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_73__TCON1_DATA_OUT23 \ + IOMUX_PAD(0x0124, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_74__RGPIOC_GPIO74 \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_74__PLATFORM_FB_AD20 \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_74__NFC_MLC_NF_IO4 \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_74__ENET_SWIAHB_MAC0_TMR3 \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_74__ESDHC0_DAT7 \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_74__SCI_FLX2_CTS \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT6, 0x384, 0) +#define _VF6XX_PAD_PAD_74__TCON1_DATA_OUT18 \ + IOMUX_PAD(0x0128, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_75__RGPIOC_GPIO75 \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_75__PLATFORM_FB_AD19 \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_75__NFC_MLC_NF_IO3 \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_75__ESAI_SCKR \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_75__I2C0_SCL \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x33C, 2) +#define _VF6XX_PAD_PAD_75__FLEXTIMER2_QD_PHA \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_75__TCON1_DATA_OUT19 \ + IOMUX_PAD(0x012C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_76__RGPIOC_GPIO76 \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_76__PLATFORM_FB_AD18 \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_76__NFC_MLC_NF_IO2 \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_76__ESAI_FSR \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_76__I2C0_SDA \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT4, 0x340, 2) +#define _VF6XX_PAD_PAD_76__FLEXTIMER2_QD_PHB \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_76__TCON1_DATA_OUT10 \ + IOMUX_PAD(0x0130, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_77__RGPIOC_GPIO77 \ + IOMUX_PAD(0x0134, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_77__PLATFORM_FB_AD17 \ + IOMUX_PAD(0x0134, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_77__NFC_MLC_NF_IO1 \ + IOMUX_PAD(0x0134, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_77__ESAI_HCKR \ + IOMUX_PAD(0x0134, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_77__I2C1_SCL \ + IOMUX_PAD(0x0134, MUX_CTL_PAD_MUX_MODE_ALT4, 0x344, 2) +#define _VF6XX_PAD_PAD_77__TCON1_DATA_OUT11 \ + IOMUX_PAD(0x0134, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_78__RGPIOC_GPIO78 \ + IOMUX_PAD(0x0138, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_78__PLATFORM_FB_AD16 \ + IOMUX_PAD(0x0138, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_78__NFC_MLC_NF_IO0 \ + IOMUX_PAD(0x0138, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_78__ESAI_HCKT \ + IOMUX_PAD(0x0138, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_78__I2C1_SDA \ + IOMUX_PAD(0x0138, MUX_CTL_PAD_MUX_MODE_ALT4, 0x348, 2) +#define _VF6XX_PAD_PAD_78__TCON1_DATA_OUT12 \ + IOMUX_PAD(0x0138, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_79__RGPIOC_GPIO79 \ + IOMUX_PAD(0x013C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_79__QUADSPI0_QSCK_A \ + IOMUX_PAD(0x013C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_79__SCI_FLX2_TX \ + IOMUX_PAD(0x013C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x38C, 2) +#define _VF6XX_PAD_PAD_79__PLATFORM_FB_AD15 \ + IOMUX_PAD(0x013C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_79__SPDIF_EXTCLK \ + IOMUX_PAD(0x013C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_79__VIU_MUX_DEBUG_OUT17 \ + IOMUX_PAD(0x013C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_80__RGPIOC_GPIO80 \ + IOMUX_PAD(0x0140, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_80__QUADSPI0_QPCS0_A \ + IOMUX_PAD(0x0140, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_80__SCI_FLX2_RX \ + IOMUX_PAD(0x0140, MUX_CTL_PAD_MUX_MODE_ALT2, 0x388, 2) +#define _VF6XX_PAD_PAD_80__PLATFORM_FB_AD14 \ + IOMUX_PAD(0x0140, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_80__SPDIF_IN1 \ + IOMUX_PAD(0x0140, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_80__VIU_MUX_DEBUG_OUT18 \ + IOMUX_PAD(0x0140, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_81__RGPIOC_GPIO81 \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_81__QUADSPI0_QSPI_IO3_A \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_81__SCI_FLX2_RTS \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_81__DSPI1_CS3 \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_81__PLATFORM_FB_AD13 \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_81__SPDIF_OUT1 \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_81__VIU_MUX_DEBUG_OUT19 \ + IOMUX_PAD(0x0144, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_82__RGPIOC_GPIO82 \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_82__QUADSPI0_QSPI_IO2_A \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_82__SCI_FLX2_CTS \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT2, 0x384, 1) +#define _VF6XX_PAD_PAD_82__DSPI1_CS2 \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_82__PLATFORM_FB_AD12 \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_82__SPDIF_PLOCK \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_82__VIU_MUX_DEBUG_OUT20 \ + IOMUX_PAD(0x0148, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_83__RGPIOC_GPIO83 \ + IOMUX_PAD(0x014C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_83__QUADSPI0_QSPI_IO1_A \ + IOMUX_PAD(0x014C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_83__DSPI1_CS1 \ + IOMUX_PAD(0x014C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_83__PLATFORM_FB_AD11 \ + IOMUX_PAD(0x014C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_83__SPDIF_SRCLK \ + IOMUX_PAD(0x014C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_83__VIU_MUX_DEBUG_OUT21 \ + IOMUX_PAD(0x014C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_84__RGPIOC_GPIO84 \ + IOMUX_PAD(0x0150, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_84__QUADSPI0_QSPI_IO0_A \ + IOMUX_PAD(0x0150, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_84__DSPI1_CS0 \ + IOMUX_PAD(0x0150, MUX_CTL_PAD_MUX_MODE_ALT3, 0x300, 1) +#define _VF6XX_PAD_PAD_84__PLATFORM_FB_AD10 \ + IOMUX_PAD(0x0150, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_84__VIU_MUX_DEBUG_OUT22 \ + IOMUX_PAD(0x0150, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_85__RGPIOC_GPIO85 \ + IOMUX_PAD(0x0154, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_85__QUADSPI0_DQS_A \ + IOMUX_PAD(0x0154, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_85__DSPI1_SIN \ + IOMUX_PAD(0x0154, MUX_CTL_PAD_MUX_MODE_ALT3, 0x2FC, 1) +#define _VF6XX_PAD_PAD_85__PLATFORM_FB_AD9 \ + IOMUX_PAD(0x0154, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_85__VIU_MUX_DEBUG_OUT23 \ + IOMUX_PAD(0x0154, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_86__RGPIOC_GPIO86 \ + IOMUX_PAD(0x0158, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_86__QUADSPI0_QSCK_B \ + IOMUX_PAD(0x0158, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_86__DSPI1_SOUT \ + IOMUX_PAD(0x0158, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_86__PLATFORM_FB_AD8 \ + IOMUX_PAD(0x0158, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_86__VIU_MUX_DEBUG_OUT24 \ + IOMUX_PAD(0x0158, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_87__RGPIOC_GPIO87 \ + IOMUX_PAD(0x015C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_87__QUADSPI0_QPCS0_B \ + IOMUX_PAD(0x015C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_87__LPCG0_FB_CLKOUT \ + IOMUX_PAD(0x015C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_87__DSPI1_SCK \ + IOMUX_PAD(0x015C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x2F8, 1) +#define _VF6XX_PAD_PAD_87__PLATFORM_FB_AD7 \ + IOMUX_PAD(0x015C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_87__VIU_MUX_DEBUG_OUT25 \ + IOMUX_PAD(0x015C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_88__RGPIOC_GPIO88 \ + IOMUX_PAD(0x0160, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_88__QUADSPI0_QSPI_IO3_B \ + IOMUX_PAD(0x0160, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_88__DSPI3_CS1 \ + IOMUX_PAD(0x0160, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_88__PLATFORM_FB_AD6 \ + IOMUX_PAD(0x0160, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_88__SAI1_TX_SYNC \ + IOMUX_PAD(0x0160, MUX_CTL_PAD_MUX_MODE_ALT6, 0x360, 0) +#define _VF6XX_PAD_PAD_88__TCON1_DATA_OUT2 \ + IOMUX_PAD(0x0160, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_89__RGPIOC_GPIO89 \ + IOMUX_PAD(0x0164, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_89__QUADSPI0_QSPI_IO2_B \ + IOMUX_PAD(0x0164, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_89__DSPI3_CS0 \ + IOMUX_PAD(0x0164, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_89__PLATFORM_FB_AD5 \ + IOMUX_PAD(0x0164, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_89__TCON1_DATA_OUT3 \ + IOMUX_PAD(0x0164, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_90__RGPIOC_GPIO90 \ + IOMUX_PAD(0x0168, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_90__QUADSPI0_QSPI_IO1_B \ + IOMUX_PAD(0x0168, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_90__DSPI3_SIN \ + IOMUX_PAD(0x0168, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_90__PLATFORM_FB_AD4 \ + IOMUX_PAD(0x0168, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_90__VIU_MUX_DEBUG_OUT26 \ + IOMUX_PAD(0x0168, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_91__RGPIOC_GPIO91 \ + IOMUX_PAD(0x016C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_91__QUADSPI0_QSPI_IO0_B \ + IOMUX_PAD(0x016C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_91__DSPI3_SOUT \ + IOMUX_PAD(0x016C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_91__PLATFORM_FB_AD3 \ + IOMUX_PAD(0x016C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_91__VIU_MUX_DEBUG_OUT27 \ + IOMUX_PAD(0x016C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_92__RGPIOC_GPIO92 \ + IOMUX_PAD(0x0170, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_92__QUADSPI0_DQS_B \ + IOMUX_PAD(0x0170, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_92__DSPI3_SCK \ + IOMUX_PAD(0x0170, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_92__PLATFORM_FB_AD2 \ + IOMUX_PAD(0x0170, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_92__VIU_MUX_DEBUG_OUT28 \ + IOMUX_PAD(0x0170, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_93__RGPIOC_GPIO93 \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_93__SAI0_TX_BCLK \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_93__SCI_FLX1_TX \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT2, 0x380, 2) +#define _VF6XX_PAD_PAD_93__SRC_RCON18 \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT3, 0x398, 1) +#define _VF6XX_PAD_PAD_93__PLATFORM_FB_ALE \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_93__PLATFORM_FB_TS_B \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_93__SCI_FLX3_RTS \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_93__TCON1_DATA_OUT13 \ + IOMUX_PAD(0x0174, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_94__RGPIOC_GPIO94 \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_94__SAI0_RX_BCLK \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_94__SCI_FLX1_RX \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT2, 0x37C, 2) +#define _VF6XX_PAD_PAD_94__SRC_RCON19 \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT3, 0x39C, 1) +#define _VF6XX_PAD_PAD_94__PLATFORM_FB_CS4_B \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_94__NFC_MLC_NF_WE_B \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_94__SCI_FLX3_CTS \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_94__TCON1_DATA_OUT14 \ + IOMUX_PAD(0x0178, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_95__RGPIOC_GPIO95 \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_95__SAI0_RX_DATA \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_95__SCI_FLX1_RTS \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_95__SRC_RCON20 \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x3A0, 1) +#define _VF6XX_PAD_PAD_95__PLATFORM_FB_CS1_B \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_95__NFC_MLC_NF_CE0_B \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_95__TCON1_DATA_OUT15 \ + IOMUX_PAD(0x017C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_96__RGPIOC_GPIO96 \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_96__SAI0_TX_DATA \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_96__SCI_FLX1_CTS \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT2, 0x378, 2) +#define _VF6XX_PAD_PAD_96__SRC_RCON21 \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_96__PLATFORM_FB_CS0_B \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_96__NFC_MLC_NF_CE1_B \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_96__TCON1_DATA_OUT16 \ + IOMUX_PAD(0x0180, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_97__RGPIOC_GPIO97 \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_97__SAI0_RX_SYNC \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_97__SRC_RCON22 \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_97__PLATFORM_FB_OE_B \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_97__PLATFORM_FB_TBST_B \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_97__NFC_MLC_NF_RE_B \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_97__TCON1_DATA_OUT17 \ + IOMUX_PAD(0x0184, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_98__RGPIOC_GPIO98 \ + IOMUX_PAD(0x0188, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_98__SAI0_TX_SYNC \ + IOMUX_PAD(0x0188, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_98__SRC_RCON23 \ + IOMUX_PAD(0x0188, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_98__PLATFORM_FB_RW_B \ + IOMUX_PAD(0x0188, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_98__TCON1_DATA_OUT8 \ + IOMUX_PAD(0x0188, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_99__RGPIOC_GPIO99 \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_99__SAI1_TX_BCLK \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_99__DSPI0_CS5 \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_99__SRC_RCON24 \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_99__PLATFORM_FB_TA_B \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_99__NFC_MLC_NF_RB_B \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_99__TCON1_DATA_OUT9 \ + IOMUX_PAD(0x018C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_100__RGPIOC_GPIO100 \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_100__SAI1_RX_BCLK \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_100__DSPI0_CS4 \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_100__SRC_RCON25 \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_100__PLATFORM_FB_BE3_B \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_100__PLATFORM_FB_CS3_B \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_100__NFC_MLC_NF_ALE \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_100__TCON1_DATA_OUT4 \ + IOMUX_PAD(0x0190, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_101__RGPIOC_GPIO101 \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_101__SAI1_RX_DATA \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_101__DSPI0_CS3 \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_101__SRC_RCON26 \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_101__PLATFORM_FB_BE2_B \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_101__PLATFORM_FB_CS2_B \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_101__NFC_MLC_NF_CLE \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_101__TCON1_DATA_OUT5 \ + IOMUX_PAD(0x0194, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_102__RGPIOC_GPIO102 \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_102__SAI1_TX_DATA \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_102__DSPI0_CS2 \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_102__SRC_RCON27 \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_102__PLATFORM_FB_BE1_B \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_102__PLATFORM_FB_TSIZ1 \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_102__TCON1_DATA_OUT6 \ + IOMUX_PAD(0x0198, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_103__RGPIOC_GPIO103 \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_103__SAI1_RX_SYNC \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_103__DSPI1_CS2 \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_103__SRC_RCON28 \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_103__PLATFORM_FB_BE0_B \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_103__PLATFORM_FB_TSIZ0 \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT5, 0x000, 0) +#define _VF6XX_PAD_PAD_103__ADC0_DA_ADC0SE5 \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_103__TCON1_DATA_OUT7 \ + IOMUX_PAD(0x019C, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_104__RGPIOC_GPIO104 \ + IOMUX_PAD(0x01A0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_104__SAI1_TX_SYNC \ + IOMUX_PAD(0x01A0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x360, 1) +#define _VF6XX_PAD_PAD_104__SRC_RCON29 \ + IOMUX_PAD(0x01A0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_104__ADC1_DA_ADC1SE5 \ + IOMUX_PAD(0x01A0, MUX_CTL_PAD_MUX_MODE_ALT6, 0x000, 0) +#define _VF6XX_PAD_PAD_104__TCON1_DATA_OUT8 \ + IOMUX_PAD(0x01A0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_105__RGPIOC_GPIO105 \ + IOMUX_PAD(0x01A4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_105__TCON0_TCON1 \ + IOMUX_PAD(0x01A4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_105__SRC_BMODE1 \ + IOMUX_PAD(0x01A4, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_105__LCD_64F6B_LCD0 \ + IOMUX_PAD(0x01A4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_105__VIU_MUX_DEBUG_OUT29 \ + IOMUX_PAD(0x01A4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_106__RGPIOC_GPIO106 \ + IOMUX_PAD(0x01A8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_106__TCON0_TCON2 \ + IOMUX_PAD(0x01A8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_106__SRC_BMODE0 \ + IOMUX_PAD(0x01A8, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_106__LCD_64F6B_LCD1 \ + IOMUX_PAD(0x01A8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_106__VIU_MUX_DEBUG_OUT30 \ + IOMUX_PAD(0x01A8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_107__RGPIOC_GPIO107 \ + IOMUX_PAD(0x01AC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_107__TCON0_DATA_OUT1 \ + IOMUX_PAD(0x01AC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_107__LCD_64F6B_LCD2 \ + IOMUX_PAD(0x01AC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_107__VIU_MUX_DEBUG_OUT31 \ + IOMUX_PAD(0x01AC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_108__RGPIOC_GPIO108 \ + IOMUX_PAD(0x01B0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_108__TCON0_TCON0 \ + IOMUX_PAD(0x01B0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_108__LCD_64F6B_LCD3 \ + IOMUX_PAD(0x01B0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_108__VIU_MUX_DEBUG_OUT32 \ + IOMUX_PAD(0x01B0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_109__RGPIOC_GPIO109 \ + IOMUX_PAD(0x01B4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_109__TCON0_TCON3 \ + IOMUX_PAD(0x01B4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_109__LCD_64F6B_LCD4 \ + IOMUX_PAD(0x01B4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_109__VIU_MUX_DEBUG_OUT33 \ + IOMUX_PAD(0x01B4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_110__RGPIOC_GPIO110 \ + IOMUX_PAD(0x01B8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_110__TCON0_DATA_OUT18 \ + IOMUX_PAD(0x01B8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_110__LCD_64F6B_LCD5 \ + IOMUX_PAD(0x01B8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_110__VIU_MUX_DEBUG_OUT34 \ + IOMUX_PAD(0x01B8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_111__RGPIOC_GPIO111 \ + IOMUX_PAD(0x01BC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_111__TCON0_DATA_OUT19 \ + IOMUX_PAD(0x01BC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_111__LCD_64F6B_LCD6 \ + IOMUX_PAD(0x01BC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_111__VIU_MUX_DEBUG_OUT35 \ + IOMUX_PAD(0x01BC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_112__RGPIOC_GPIO112 \ + IOMUX_PAD(0x01C0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_112__TCON0_DATA_OUT20 \ + IOMUX_PAD(0x01C0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_112__SRC_RCON0 \ + IOMUX_PAD(0x01C0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_112__LCD_64F6B_LCD7 \ + IOMUX_PAD(0x01C0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_112__VIU_MUX_DEBUG_OUT36 \ + IOMUX_PAD(0x01C0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_113__RGPIOC_GPIO113 \ + IOMUX_PAD(0x01C4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_113__TCON0_DATA_OUT21 \ + IOMUX_PAD(0x01C4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_113__SRC_RCON1 \ + IOMUX_PAD(0x01C4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_113__LCD_64F6B_LCD8 \ + IOMUX_PAD(0x01C4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_113__VIU_MUX_DEBUG_OUT37 \ + IOMUX_PAD(0x01C4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_114__RGPIOC_GPIO114 \ + IOMUX_PAD(0x01C8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_114__TCON0_DATA_OUT22 \ + IOMUX_PAD(0x01C8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_114__SRC_RCON2 \ + IOMUX_PAD(0x01C8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_114__LCD_64F6B_LCD9 \ + IOMUX_PAD(0x01C8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_114__VIU_MUX_DEBUG_OUT38 \ + IOMUX_PAD(0x01C8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_115__RGPIOC_GPIO115 \ + IOMUX_PAD(0x01CC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_115__TCON0_DATA_OUT23 \ + IOMUX_PAD(0x01CC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_115__SRC_RCON3 \ + IOMUX_PAD(0x01CC, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_115__LCD_64F6B_LCD10 \ + IOMUX_PAD(0x01CC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_115__VIU_MUX_DEBUG_OUT39 \ + IOMUX_PAD(0x01CC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_116__RGPIOC_GPIO116 \ + IOMUX_PAD(0x01D0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_116__TCON0_DATA_OUT24 \ + IOMUX_PAD(0x01D0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_116__SRC_RCON4 \ + IOMUX_PAD(0x01D0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_116__LCD_64F6B_LCD11 \ + IOMUX_PAD(0x01D0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_116__VIU_MUX_DEBUG_OUT40 \ + IOMUX_PAD(0x01D0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_117__RGPIOC_GPIO117 \ + IOMUX_PAD(0x01D4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_117__TCON0_DATA_OUT25 \ + IOMUX_PAD(0x01D4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_117__DSPI1_CS3 \ + IOMUX_PAD(0x01D4, MUX_CTL_PAD_MUX_MODE_ALT2, 0x000, 0) +#define _VF6XX_PAD_PAD_117__SRC_RCON5 \ + IOMUX_PAD(0x01D4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_117__LCD_64F6B_LCD12 \ + IOMUX_PAD(0x01D4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_117__LPTIMER_LP_IN \ + IOMUX_PAD(0x01D4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_118__RGPIOC_GPIO118 \ + IOMUX_PAD(0x01D8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_118__TCON0_DATA_OUT10 \ + IOMUX_PAD(0x01D8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_118__LCD_64F6B_LCD13 \ + IOMUX_PAD(0x01D8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_118__VIU_MUX_DEBUG_OUT41 \ + IOMUX_PAD(0x01D8, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_119__RGPIOC_GPIO119 \ + IOMUX_PAD(0x01DC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_119__TCON0_DATA_OUT11 \ + IOMUX_PAD(0x01DC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_119__LCD_64F6B_LCD14 \ + IOMUX_PAD(0x01DC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_119__VIU_MUX_DEBUG_OUT42 \ + IOMUX_PAD(0x01DC, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_120__RGPIOC_GPIO120 \ + IOMUX_PAD(0x01E0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_120__TCON0_DATA_OUT12 \ + IOMUX_PAD(0x01E0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_120__SRC_RCON6 \ + IOMUX_PAD(0x01E0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_120__LCD_64F6B_LCD15 \ + IOMUX_PAD(0x01E0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_120__VIU_MUX_DEBUG_OUT43 \ + IOMUX_PAD(0x01E0, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_121__RGPIOC_GPIO121 \ + IOMUX_PAD(0x01E4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_121__TCON0_DATA_OUT13 \ + IOMUX_PAD(0x01E4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_121__SRC_RCON7 \ + IOMUX_PAD(0x01E4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_121__LCD_64F6B_LCD16 \ + IOMUX_PAD(0x01E4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_122__RGPIOC_GPIO122 \ + IOMUX_PAD(0x01E8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_122__TCON0_DATA_OUT14 \ + IOMUX_PAD(0x01E8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_122__SRC_RCON8 \ + IOMUX_PAD(0x01E8, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_122__LCD_64F6B_LCD17 \ + IOMUX_PAD(0x01E8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_123__RGPIOC_GPIO123 \ + IOMUX_PAD(0x01EC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_123__TCON0_DATA_OUT15 \ + IOMUX_PAD(0x01EC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_123__SRC_RCON9 \ + IOMUX_PAD(0x01EC, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_123__LCD_64F6B_LCD18 \ + IOMUX_PAD(0x01EC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_124__RGPIOC_GPIO124 \ + IOMUX_PAD(0x01F0, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_124__TCON0_DATA_OUT16 \ + IOMUX_PAD(0x01F0, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_124__SRC_RCON10 \ + IOMUX_PAD(0x01F0, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_124__LCD_64F6B_LCD19 \ + IOMUX_PAD(0x01F0, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_124__I2C0_SCL \ + IOMUX_PAD(0x01F0, MUX_CTL_PAD_MUX_MODE_ALT5, 0x33C, 3) + +#define _VF6XX_PAD_PAD_125__RGPIOC_GPIO125 \ + IOMUX_PAD(0x01F4, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_125__TCON0_DATA_OUT17 \ + IOMUX_PAD(0x01F4, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_125__SRC_RCON11 \ + IOMUX_PAD(0x01F4, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_125__LCD_64F6B_LCD20 \ + IOMUX_PAD(0x01F4, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_125__I2C0_SDA \ + IOMUX_PAD(0x01F4, MUX_CTL_PAD_MUX_MODE_ALT5, 0x340, 3) +#define _VF6XX_PAD_PAD_125__EWM_IN \ + IOMUX_PAD(0x01F4, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_126__RGPIOC_GPIO126 \ + IOMUX_PAD(0x01F8, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_126__TCON0_DATA_OUT2 \ + IOMUX_PAD(0x01F8, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_126__LCD_64F6B_LCD21 \ + IOMUX_PAD(0x01F8, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_127__RGPIOC_GPIO127 \ + IOMUX_PAD(0x01FC, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_127__TCON0_DATA_OUT3 \ + IOMUX_PAD(0x01FC, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_127__LCD_64F6B_LCD22 \ + IOMUX_PAD(0x01FC, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_128__RGPIOC_GPIO128 \ + IOMUX_PAD(0x0200, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_128__TCON0_DATA_OUT4 \ + IOMUX_PAD(0x0200, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_128__SRC_RCON12 \ + IOMUX_PAD(0x0200, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_128__LCD_64F6B_LCD23 \ + IOMUX_PAD(0x0200, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_129__RGPIOC_GPIO129 \ + IOMUX_PAD(0x0204, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_129__TCON0_DATA_OUT5 \ + IOMUX_PAD(0x0204, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_129__SRC_RCON13 \ + IOMUX_PAD(0x0204, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_129__LCD_64F6B_LCD24 \ + IOMUX_PAD(0x0204, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_130__RGPIOC_GPIO130 \ + IOMUX_PAD(0x0208, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_130__TCON0_DATA_OUT6 \ + IOMUX_PAD(0x0208, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_130__SRC_RCON14 \ + IOMUX_PAD(0x0208, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_130__LCD_64F6B_LCD25 \ + IOMUX_PAD(0x0208, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_131__RGPIOC_GPIO131 \ + IOMUX_PAD(0x020C, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_131__TCON0_DATA_OUT7 \ + IOMUX_PAD(0x020C, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_131__SRC_RCON15 \ + IOMUX_PAD(0x020C, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_131__LCD_64F6B_LCD26 \ + IOMUX_PAD(0x020C, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) + +#define _VF6XX_PAD_PAD_132__RGPIOC_GPIO132 \ + IOMUX_PAD(0x0210, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_132__TCON0_DATA_OUT8 \ + IOMUX_PAD(0x0210, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_132__SRC_RCON16 \ + IOMUX_PAD(0x0210, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_132__LCD_64F6B_LCD27 \ + IOMUX_PAD(0x0210, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_132__I2C1_SCL \ + IOMUX_PAD(0x0210, MUX_CTL_PAD_MUX_MODE_ALT5, 0x344, 3) + +#define _VF6XX_PAD_PAD_133__RGPIOC_GPIO133 \ + IOMUX_PAD(0x0214, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_133__TCON0_DATA_OUT9 \ + IOMUX_PAD(0x0214, MUX_CTL_PAD_MUX_MODE_ALT1, 0x000, 0) +#define _VF6XX_PAD_PAD_133__SRC_RCON17 \ + IOMUX_PAD(0x0214, MUX_CTL_PAD_MUX_MODE_ALT3, 0x000, 0) +#define _VF6XX_PAD_PAD_133__LCD_64F6B_LCD28 \ + IOMUX_PAD(0x0214, MUX_CTL_PAD_MUX_MODE_ALT4, 0x000, 0) +#define _VF6XX_PAD_PAD_133__I2C1_SDA \ + IOMUX_PAD(0x0214, MUX_CTL_PAD_MUX_MODE_ALT5, 0x348, 3) +#define _VF6XX_PAD_PAD_133__EWM_OUT \ + IOMUX_PAD(0x0214, MUX_CTL_PAD_MUX_MODE_ALT7, 0x000, 0) + +#define _VF6XX_PAD_PAD_134__RGPIOC_GPIO134 \ + IOMUX_PAD(0x0218, MUX_CTL_PAD_MUX_MODE_ALT0, 0x000, 0) +#define _VF6XX_PAD_PAD_134__VIDEO_IN0_PIX_CLK \ + IOMUX_PAD(0x0218, MUX_CTL_PAD_MUX_MODE_ALT1, 0x3AC, 1) + +#define _VF6XX_PAD_DDR_RESETB IOMUX_PAD(0x21C,0,0x000,0) +#define _VF6XX_PAD_DDR_A_15 IOMUX_PAD(0x220,0,0x000,0) +#define _VF6XX_PAD_DDR_A_14 IOMUX_PAD(0x224,0,0x000,0) +#define _VF6XX_PAD_DDR_A_13 IOMUX_PAD(0x228,0,0x000,0) +#define _VF6XX_PAD_DDR_A_12 IOMUX_PAD(0x22C,0,0x000,0) +#define _VF6XX_PAD_DDR_A_11 IOMUX_PAD(0x230,0,0x000,0) +#define _VF6XX_PAD_DR_A_10 IOMUX_PAD(0x234,0,0x000,0) +#define _VF6XX_PAD_DDR_A_9 IOMUX_PAD(0x238,0,0x000,0) +#define _VF6XX_PAD_DDR_A_8 IOMUX_PAD(0x23C,0,0x000,0) +#define _VF6XX_PAD_DDR_A_7 IOMUX_PAD(0x240,0,0x000,0) +#define _VF6XX_PAD_DDR_A_6 IOMUX_PAD(0x244,0,0x000,0) +#define _VF6XX_PAD_DDR_A_5 IOMUX_PAD(0x248,0,0x000,0) +#define _VF6XX_PAD_DDR_A_4 IOMUX_PAD(0x24C,0,0x000,0) +#define _VF6XX_PAD_DDR_A_3 IOMUX_PAD(0x250,0,0x000,0) +#define _VF6XX_PAD_DDR_A_2 IOMUX_PAD(0x254,0,0x000,0) +#define _VF6XX_PAD_DDR_A_1 IOMUX_PAD(0x258,0,0x000,0) +#define _VF6XX_PAD_DDR_A_0 IOMUX_PAD(0x25C,0,0x000,0) +#define _VF6XX_PAD_DDR_BA_2 IOMUX_PAD(0x260,0,0x000,0) +#define _VF6XX_PAD_DDR_BA_1 IOMUX_PAD(0x264,0,0x000,0) +#define _VF6XX_PAD_DDR_BA_0 IOMUX_PAD(0x268,0,0x000,0) +#define _VF6XX_PAD_DDR_CAS_B IOMUX_PAD(0x26C,0,0x000,0) +#define _VF6XX_PAD_DDR_CKE_0 IOMUX_PAD(0x270,0,0x000,0) +#define _VF6XX_PAD_DDR_CLK_0 IOMUX_PAD(0x274,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_B_0 IOMUX_PAD(0x278,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_15 IOMUX_PAD(0x27C,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_14 IOMUX_PAD(0x280,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_13 IOMUX_PAD(0x284,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_12 IOMUX_PAD(0x288,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_11 IOMUX_PAD(0x28C,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_10 IOMUX_PAD(0x290,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_9 IOMUX_PAD(0x294,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_8 IOMUX_PAD(0x298,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_7 IOMUX_PAD(0x29C,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_6 IOMUX_PAD(0x2A0,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_5 IOMUX_PAD(0x2A4,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_4 IOMUX_PAD(0x2A8,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_3 IOMUX_PAD(0x2AC,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_2 IOMUX_PAD(0x2B0,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_1 IOMUX_PAD(0x2B4,0,0x000,0) +#define _VF6XX_PAD_DDR_CS_D_0 IOMUX_PAD(0x2B8,0,0x000,0) +#define _VF6XX_PAD_DDR_DQM_1 IOMUX_PAD(0x2BC,0,0x000,0) +#define _VF6XX_PAD_DDR_DQM_0 IOMUX_PAD(0x2C0,0,0x000,0) +#define _VF6XX_PAD_DDR_DQS_1 IOMUX_PAD(0x2C4,0,0x000,0) +#define _VF6XX_PAD_DDR_DQS_0 IOMUX_PAD(0x2C8,0,0x000,0) +#define _VF6XX_PAD_DDR_RAS_B IOMUX_PAD(0x2CC,0,0x000,0) +#define _VF6XX_PAD_DDR_WE_B IOMUX_PAD(0x2D0,0,0x000,0) +#define _VF6XX_PAD_DDR_ODT_0 IOMUX_PAD(0x2D4,0,0x000,0) +#define _VF6XX_PAD_DDR_ODT_1 IOMUX_PAD(0x2D8,0,0x000,0) +#define _VF6XX_PAD_DUMMY_DDRBYTE1 IOMUX_PAD(0x2DC,0,0x000,0) +#define _VF6XX_PAD_DUMMY_DDRBYTE2 IOMUX_PAD(0x2E0,0,0x000,0) +#define _VF6XX_PAD_DUMMY_SDHC1 IOMUX_PAD(0x2E4,0,0x000,0) +#define _VF6XX_PAD_DUMMY_SDHC2 IOMUX_PAD(0x2E8,0,0x000,0) + + +#define VF6XX_PAD_PAD_0__RGPIOC_GPIO0 \ + (_VF6XX_PAD_PAD_0__RGPIOC_GPIO0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_0__CCM_RMII_CLKOUT \ + (_VF6XX_PAD_PAD_0__CCM_RMII_CLKOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_0__CCM_RMII_CLKIN \ + (_VF6XX_PAD_PAD_0__CCM_RMII_CLKIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_0__TCON1_TCON11 \ + (_VF6XX_PAD_PAD_0__TCON1_TCON11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_0__TCON1_DATA_OUT20 \ + (_VF6XX_PAD_PAD_0__TCON1_DATA_OUT20 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_1__RGPIOC_GPIO1 \ + (_VF6XX_PAD_PAD_1__RGPIOC_GPIO1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_1__DEBUG_TCLK \ + (_VF6XX_PAD_PAD_1__DEBUG_TCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_1__TCON_DATA_OUT18 \ + (_VF6XX_PAD_PAD_1__TCON0_DATA_OUT18 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_1__MLB_TOP_MLBCLK \ + (_VF6XX_PAD_PAD_1__MLB_TOP_MLBCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_2__RGPIOC_GPIO2 \ + (_VF6XX_PAD_PAD_2__RGPIOC_GPIO2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_2__DEBUG_TDI \ + (_VF6XX_PAD_PAD_2__DEBUG_TDI | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_2__CCM_RMII_CLKOUT \ + (_VF6XX_PAD_PAD_2__CCM_RMII_CLKOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_2__CCM_RMII_CLKIN \ + (_VF6XX_PAD_PAD_2__CCM_RMII_CLKIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_2__TCON0_DATA_OUT19 \ + (_VF6XX_PAD_PAD_2__TCON0_DATA_OUT19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_2__IPP_WDOG_CA5_CM4 \ + (_VF6XX_PAD_PAD_2__IPP_WDOG_CA5_CM4 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_3__RGPIOC_GPIO3 \ + (_VF6XX_PAD_PAD_3__RGPIOC_GPIO3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_3__DEBUG_TDO \ + (_VF6XX_PAD_PAD_3__DEBUG_TDO | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_3__CCM_EXT_AUDIO_MCLK \ + (_VF6XX_PAD_PAD_3__CCM_EXT_AUDIO_MCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_3__TCON0_DATA_OUT10 \ + (_VF6XX_PAD_PAD_3__TCON0_DATA_OUT10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_3__CCM_ENET_TS_CLKIN \ + (_VF6XX_PAD_PAD_3__CCM_ENET_TS_CLKIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_3__MLB_TOP_MLBSIGNAL \ + (_VF6XX_PAD_PAD_3__MLB_TOP_MLBSIGNAL | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_4__RGPIOC_GPIO4 \ + (_VF6XX_PAD_PAD_4__RGPIOC_GPIO4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_4__DEBUG_TMS \ + (_VF6XX_PAD_PAD_4__DEBUG_TMS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_4__TCON0_DATA_OUT11 \ + (_VF6XX_PAD_PAD_4__TCON0_DATA_OUT11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_4__MLB_TOP_MLB_DATA \ + (_VF6XX_PAD_PAD_4__MLB_TOP_MLB_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_5__RGPIOC_GPIO5 \ + (_VF6XX_PAD_PAD_5__RGPIOC_GPIO5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_5__PLATFORM_TRACECK \ + (_VF6XX_PAD_PAD_5__PLATFORM_TRACECK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_5__CCM_EXT_AUDIO_MCLK \ + (_VF6XX_PAD_PAD_5__CCM_EXT_AUDIO_MCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_5__VIDEO_IN0_DATA13 \ + (_VF6XX_PAD_PAD_5__VIDEO_IN0_DATA13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_5__I2C0_SCL \ + (_VF6XX_PAD_PAD_5__I2C0_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_6__RGPIOC_GPIO6 \ + (_VF6XX_PAD_PAD_6__RGPIOC_GPIO6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__PLATFORM_TRACED0 \ + (_VF6XX_PAD_PAD_6__PLATFORM_TRACED0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__USB_VBUS_EN_OTG \ + (_VF6XX_PAD_PAD_6__USB_VBUS_EN_OTG | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__ADC1_DA_ADC1SE0 \ + (_VF6XX_PAD_PAD_6__ADC1_DA_ADC1SE0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__LCD_64F6B_LCD29 \ + (_VF6XX_PAD_PAD_6__LCD_64F6B_LCD29 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__SAI2_TX_BCLK \ + (_VF6XX_PAD_PAD_6__SAI2_TX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__VIDEO_IN0_DATA14 \ + (_VF6XX_PAD_PAD_6__VIDEO_IN0_DATA14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_6__I2C0_SDA \ + (_VF6XX_PAD_PAD_6__I2C0_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_7__RGPIOC_GPIO7 \ + (_VF6XX_PAD_PAD_7__RGPIOC_GPIO7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__PLATFORM_TRACED1 \ + (_VF6XX_PAD_PAD_7__PLATFORM_TRACED1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__USB_VBUS_OC_OTG \ + (_VF6XX_PAD_PAD_7__USB_VBUS_OC_OTG | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__ADC1_DA_ADC1SE1 \ + (_VF6XX_PAD_PAD_7__ADC1_DA_ADC1SE1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__LCD_64F6B_LCD30 \ + (_VF6XX_PAD_PAD_7__LCD_64F6B_LCD30 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__USB_USB0_SOF_PULSE \ + (_VF6XX_PAD_PAD_7__USB_USB0_SOF_PULSE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__VIDEO_IN0_DATA15 \ + (_VF6XX_PAD_PAD_7__VIDEO_IN0_DATA15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_7__I2C1_SCL \ + (_VF6XX_PAD_PAD_7__I2C1_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_8__RGPIOC_GPIO7 \ + (_VF6XX_PAD_PAD_8__RGPIOC_GPIO7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__PLATFORM_TRACED2 \ + (_VF6XX_PAD_PAD_8__PLATFORM_TRACED2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__ADC0_DA_ADC0SE0 \ + (_VF6XX_PAD_PAD_8__ADC0_DA_ADC0SE0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__FLEXTIMER1_QD_PHA \ + (_VF6XX_PAD_PAD_8__FLEXTIMER1_QD_PHA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__LCD_64F6B_LCD31 \ + (_VF6XX_PAD_PAD_8__LCD_64F6B_LCD31 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__SAI2_TX_DATA \ + (_VF6XX_PAD_PAD_8__SAI2_TX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__VIDEO_IN0_DATA16 \ + (_VF6XX_PAD_PAD_8__VIDEO_IN0_DATA16 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_8__I2C1_SDA \ + (_VF6XX_PAD_PAD_8__I2C1_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_9__RGPIOC_GPIO9 \ + (_VF6XX_PAD_PAD_9__RGPIOC_GPIO9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__PLATFORM_TRACED3 \ + (_VF6XX_PAD_PAD_9__PLATFORM_TRACED3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__ADC0_DA_ADC0SE1 \ + (_VF6XX_PAD_PAD_9__ADC0_DA_ADC0SE1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__FLEXTIMER1_QD_PHB \ + (_VF6XX_PAD_PAD_9__FLEXTIMER1_QD_PHB | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__LCD_64F6B_LCD32 \ + (_VF6XX_PAD_PAD_9__LCD_64F6B_LCD32 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__SAI2_TX_SYNC \ + (_VF6XX_PAD_PAD_9__SAI2_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__VIDEO_IN0_DATA17 \ + (_VF6XX_PAD_PAD_9__VIDEO_IN0_DATA17 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__QUADSPI1_QSCK_A \ + (_VF6XX_PAD_PAD_9__QUADSPI1_QSCK_A | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_10__RGPIOC_GPIO10 \ + (_VF6XX_PAD_PAD_10__RGPIOC_GPIO10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_10__PLATFORM_TRACED4 \ + (_VF6XX_PAD_PAD_10__PLATFORM_TRACED4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_10__LCD_64F6B_LCD33 \ + (_VF6XX_PAD_PAD_10__LCD_64F6B_LCD33 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_10__SCI_FLX3_TX \ + (_VF6XX_PAD_PAD_10__SCI_FLX3_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_10__TCON1_TCON1 \ + (_VF6XX_PAD_PAD_10__TCON1_TCON1 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_11__RGPIOC_GPIO11 \ + (_VF6XX_PAD_PAD_11__RGPIOC_GPIO11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_11__PLATFORM_TRACED5 \ + (_VF6XX_PAD_PAD_11__PLATFORM_TRACED5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_11__SAI2_RX_BCLK \ + (_VF6XX_PAD_PAD_11__SAI2_RX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_11__SCI_FLX3_RX \ + (_VF6XX_PAD_PAD_11__SCI_FLX3_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_11__TCON1_TCON2 \ + (_VF6XX_PAD_PAD_11__TCON1_TCON2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_12__RGPIOC_GPIO12 \ + (_VF6XX_PAD_PAD_12__RGPIOC_GPIO12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_12__PLATFORM_TRACED6 \ + (_VF6XX_PAD_PAD_12__PLATFORM_TRACED6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_12__SAI2_RX_DATA \ + (_VF6XX_PAD_PAD_12__SAI2_RX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_12__I2C2_SCL \ + (_VF6XX_PAD_PAD_12__I2C2_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_12__TCON1_TCON0 \ + (_VF6XX_PAD_PAD_12__TCON1_TCON0 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_13__RGPIOC_GPIO13 \ + (_VF6XX_PAD_PAD_13__RGPIOC_GPIO13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_13__PLATFORM_TRACED7 \ + (_VF6XX_PAD_PAD_13__PLATFORM_TRACED7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_13__SAI2_RX_SYNC \ + (_VF6XX_PAD_PAD_13__SAI2_RX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_13__I2C2_SDA \ + (_VF6XX_PAD_PAD_13__I2C2_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_13__TCON1_TCON3 \ + +#define VF6XX_PAD_PAD_14__RGPIOC_GPIO14 \ + (_VF6XX_PAD_PAD_14__RGPIOC_GPIO14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_14__PLATFORM_TRACED8 \ + (_VF6XX_PAD_PAD_14__PLATFORM_TRACED8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_14__USB_VBUS_EN \ + (_VF6XX_PAD_PAD_14__USB_VBUS_EN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_14__ESDHC1_CLK \ + (_VF6XX_PAD_PAD_14__ESDHC1_CLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_14__TCON1_TCON4 \ + (_VF6XX_PAD_PAD_14__TCON1_TCON4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_14__DDR_TEST_LOGIC_PAD_CTRL \ + (_VF6XX_PAD_PAD_14__DDR_TEST_LOGIC_PAD_CTRL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_15__RGPIOC_GPIO15 \ + (_VF6XX_PAD_PAD_15__RGPIOC_GPIO15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_15__PLATFORM_TRACED9 \ + (_VF6XX_PAD_PAD_15__PLATFORM_TRACED9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_15__USB_VBUS_OC \ + (_VF6XX_PAD_PAD_15__USB_VBUS_OC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_15__ESDHC1_CMD \ + (_VF6XX_PAD_PAD_15__ESDHC1_CMD | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_15__TCON1_TCON5 \ + (_VF6XX_PAD_PAD_15__TCON1_TCON5 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_16__RGPIOC_GPIO16 \ + (_VF6XX_PAD_PAD_16__RGPIOC_GPIO16 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_16__PLATFORM_TRACED10 \ + (_VF6XX_PAD_PAD_16__PLATFORM_TRACED10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_16__SAI3_TX_BCLK \ + (_VF6XX_PAD_PAD_16__SAI3_TX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_16__ESDHC1_DAT0 \ + (_VF6XX_PAD_PAD_16__ESDHC1_DAT0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_16__TCON1_TCON6 \ + (_VF6XX_PAD_PAD_16__TCON1_TCON6 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_17__RGPIOC_GPIO17 \ + (_VF6XX_PAD_PAD_17__RGPIOC_GPIO17 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_17__PLATFORM_TRACED11 \ + (_VF6XX_PAD_PAD_17__PLATFORM_TRACED11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_17__SAI3_RX_BCLK \ + (_VF6XX_PAD_PAD_17__SAI3_RX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_17__ESDHC1_DAT1 \ + (_VF6XX_PAD_PAD_17__ESDHC1_DAT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_17__TCON1_TCON7 \ + (_VF6XX_PAD_PAD_17__TCON1_TCON7 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_18__RGPIOC_GPIO18 \ + (_VF6XX_PAD_PAD_18__RGPIOC_GPIO18 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_18__PLATFORM_TRACED12 \ + (_VF6XX_PAD_PAD_18__PLATFORM_TRACED12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_18__SAI3_RX_DATA \ + (_VF6XX_PAD_PAD_18__SAI3_RX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_18__ENET_SWIAHB_MAC1_TMR0 \ + (_VF6XX_PAD_PAD_18__ENET_SWIAHB_MAC1_TMR0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_18__SCI_FLX_TX \ + (_VF6XX_PAD_PAD_18__SCI_FLX_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_18__ESDHC1_DAT2 \ + (_VF6XX_PAD_PAD_18__ESDHC1_DAT2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_18__TCON1_TCON8 \ + (_VF6XX_PAD_PAD_18__TCON1_TCON8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_9__QUADSPI1_QSCK_A \ + +#define VF6XX_PAD_PAD_19__RGPIOC_GPIO19 \ + (_VF6XX_PAD_PAD_19__RGPIOC_GPIO19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_19__PLATFORM_TRACED13 \ + (_VF6XX_PAD_PAD_19__PLATFORM_TRACED13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_19__SAI3_TX_DATA \ + (_VF6XX_PAD_PAD_19__SAI3_TX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_19__ENET_SWIAHB_MAC1_TMR1 \ + (_VF6XX_PAD_PAD_19__ENET_SWIAHB_MAC1_TMR1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_19__SCI_FLX4_RX \ + (_VF6XX_PAD_PAD_19__SCI_FLX4_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_19__ESDHC1_DAT3 \ + (_VF6XX_PAD_PAD_19__ESDHC1_DAT3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_19__TCON1_TCON9 \ + (_VF6XX_PAD_PAD_19__TCON1_TCON9 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_20__RGPIOC_GPIO20 \ + (_VF6XX_PAD_PAD_20__RGPIOC_GPIO20 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_20__PLATFORM_TRACED14 \ + (_VF6XX_PAD_PAD_20__PLATFORM_TRACED14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_20__SAI3_RX_SYNC \ + (_VF6XX_PAD_PAD_20__SAI3_RX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_20__ENET_SWIAHB_MAC1_TMR2 \ + (_VF6XX_PAD_PAD_20__ENET_SWIAHB_MAC1_TMR2 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_20__SCI_FLX4_RTS \ + (_VF6XX_PAD_PAD_20__SCI_FLX4_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_20__I2C3_SCL \ + (_VF6XX_PAD_PAD_20__I2C3_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_20__SCI_FLX3_RTS \ + (_VF6XX_PAD_PAD_20__SCI_FLX3_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_21__RGPIOC_GPIO21 \ + (_VF6XX_PAD_PAD_21__RGPIOC_GPIO21 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_21__PLATFORM_TRACED15 \ + (_VF6XX_PAD_PAD_21__PLATFORM_TRACED15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_21__SAI3_TX_SYNC \ + (_VF6XX_PAD_PAD_21__SAI3_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_21__ENET_SWIAHB_MAC1_TMR3 \ + (_VF6XX_PAD_PAD_21__ENET_SWIAHB_MAC1_TMR3 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_21__SCI_FLX4_CTS \ + (_VF6XX_PAD_PAD_21__SCI_FLX4_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_21__I2C3_SDA \ + (_VF6XX_PAD_PAD_21__I2C3_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_21__SCI_FLX3_TX_SYNC \ + (_VF6XX_PAD_PAD_21__SCI_FLX3_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_22__RGPIOC_GPIO22 \ + (_VF6XX_PAD_PAD_22__RGPIOC_GPIO22 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__FLEXTIMER0_CH0 \ + (_VF6XX_PAD_PAD_22__FLEXTIMER0_CH0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__ADC0_DA_ADC0SE2 \ + (_VF6XX_PAD_PAD_22__ADC0_DA_ADC0SE2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__PLATFORM_TRACECTL \ + (_VF6XX_PAD_PAD_22__PLATFORM_TRACECTL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__LCD_64F6B_LCD34 \ + (_VF6XX_PAD_PAD_22__LCD_64F6B_LCD34 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__SAI2_RX_BCLK \ + (_VF6XX_PAD_PAD_22__SAI2_RX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__VIDEO_IN0_DATA18 \ + (_VF6XX_PAD_PAD_22__VIDEO_IN0_DATA18 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_22__QUADSPI1_QPCS0_A \ + (_VF6XX_PAD_PAD_22__QUADSPI1_QPCS0_A | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_23__RGPIOC_GPIO23 \ + (_VF6XX_PAD_PAD_23__RGPIOC_GPIO23 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__FLEXTIMER0_CH1 \ + (_VF6XX_PAD_PAD_23__FLEXTIMER0_CH1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__ADC0_DA_ADC0SE3 \ + (_VF6XX_PAD_PAD_23__ADC0_DA_ADC0SE3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__SRC_RCON30 \ + (_VF6XX_PAD_PAD_23__SRC_RCON30 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__LCD_64F6B_LCD35 \ + (_VF6XX_PAD_PAD_23__LCD_64F6B_LCD35 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__SAI2_RX_DATA \ + (_VF6XX_PAD_PAD_23__SAI2_RX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__VIDEO_IN0_DATA19 \ + (_VF6XX_PAD_PAD_23__VIDEO_IN0_DATA19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_23__QUADSPI1_QSPI_IO3 \ + (_VF6XX_PAD_PAD_23__QUADSPI1_QSPI_IO3 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_24__RGPIOC_GPIO24 \ + (_VF6XX_PAD_PAD_24__RGPIOC_GPIO24 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__FLEXTIMER0_CH2 \ + (_VF6XX_PAD_PAD_24__FLEXTIMER0_CH2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__ADC1_DA_ADC1SE2 \ + (_VF6XX_PAD_PAD_24__ADC1_DA_ADC1SE2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__SRC_RCON31 \ + (_VF6XX_PAD_PAD_24__SRC_RCON31 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__LCD_64F6B_LCD36 \ + (_VF6XX_PAD_PAD_24__LCD_64F6B_LCD36 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__SAI2_RX_SYNC \ + (_VF6XX_PAD_PAD_24__SAI2_RX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__VIDEO_IN0_DATA20 \ + (_VF6XX_PAD_PAD_24__VIDEO_IN0_DATA20 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_24__QUADSPI1_QSPI_IO2 \ + (_VF6XX_PAD_PAD_24__QUADSPI1_QSPI_IO2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_25__RGPIOC_GPIO25 \ + (_VF6XX_PAD_PAD_25__RGPIOC_GPIO25 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_25__FLEXTIMER0_CH3 \ + (_VF6XX_PAD_PAD_25__FLEXTIMER0_CH3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_25__ADC1_DA_ADC1SE3 \ + (_VF6XX_PAD_PAD_25__ADC1_DA_ADC1SE3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_25__PDB_EXTRING \ + (_VF6XX_PAD_PAD_25__PDB_EXTRING | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_25__LCD_64F6B_LCD37 \ + (_VF6XX_PAD_PAD_25__LCD_64F6B_LCD37 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_25__VIDEO_IN0_DATA21 \ + (_VF6XX_PAD_PAD_25__VIDEO_IN0_DATA21 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_25__QUADSPI1_QSPI_IO1 \ + (_VF6XX_PAD_PAD_25__QUADSPI1_QSPI_IO1 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_26__RGPIOC_GPIO26 \ + (_VF6XX_PAD_PAD_26__RGPIOC_GPIO26 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__FLEXTIMER0_CH4 \ + (_VF6XX_PAD_PAD_26__FLEXTIMER0_CH4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__SCI_FLX1_TX \ + (_VF6XX_PAD_PAD_26__SCI_FLX1_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__ADC0_DA_ADC0SE4 \ + (_VF6XX_PAD_PAD_26__ADC0_DA_ADC0SE4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__LCD_64F6B_LCD38 \ + (_VF6XX_PAD_PAD_26__LCD_64F6B_LCD38 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__VIDEO_IN0_VIU_FID \ + (_VF6XX_PAD_PAD_26__VIDEO_IN0_VIU_FID | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__VIDEO_IN0_DATA22 \ + (_VF6XX_PAD_PAD_26__VIDEO_IN0_DATA22 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_26__QUADSPI1_QSPI_IO0 \ + (_VF6XX_PAD_PAD_26__QUADSPI1_QSPI_IO0 | MUX_CTRL_PAD(NO_PAD_CTRL)) + + +#define VF6XX_PAD_PAD_27__RGPIOC_GPIO27 \ + (_VF6XX_PAD_PAD_27__RGPIOC_GPIO27 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__FLEXTIMER0_CH5 \ + (_VF6XX_PAD_PAD_27__FLEXTIMER0_CH5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__SCI_FLX1_RX \ + (_VF6XX_PAD_PAD_27__SCI_FLX1_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__ADC1_DA_ADC1SE4 \ + (_VF6XX_PAD_PAD_27__ADC1_DA_ADC1SE4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__LCD_64F6B_LCD39 \ + (_VF6XX_PAD_PAD_27__LCD_64F6B_LCD39 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__VIDEO_IN0_VIU_DE \ + (_VF6XX_PAD_PAD_27__VIDEO_IN0_VIU_DE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__VIDEO_IN0_DATA23 \ + (_VF6XX_PAD_PAD_27__VIDEO_IN0_DATA23 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_27__QUADSPI1_DQS_A \ + (_VF6XX_PAD_PAD_27__QUADSPI1_DQS_A | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_28__RGPIOC_GPIO28 \ + (_VF6XX_PAD_PAD_28__RGPIOC_GPIO28 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__FLEXTIMER0_CH6 \ + (_VF6XX_PAD_PAD_28__FLEXTIMER0_CH6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__SCI_FLX1_RTS \ + (_VF6XX_PAD_PAD_28__SCI_FLX1_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__QUADSPI0_QPCS1_A \ + (_VF6XX_PAD_PAD_28__QUADSPI0_QPCS1_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__LCD_64F6B_LCD40 \ + (_VF6XX_PAD_PAD_28__LCD_64F6B_LCD40 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__LPCG0_FB_CLKOUT \ + (_VF6XX_PAD_PAD_28__LPCG0_FB_CLKOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__VIDEO_IN0_HSYNC \ + (_VF6XX_PAD_PAD_28__VIDEO_IN0_HSYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_28__SCI_FLX2_TX \ + (_VF6XX_PAD_PAD_28__SCI_FLX2_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_29__RGPIOC_GPIO29 \ + (_VF6XX_PAD_PAD_29__RGPIOC_GPIO29 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_29__FLEXTIMER0_CH7 \ + (_VF6XX_PAD_PAD_29__FLEXTIMER0_CH7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_29__SCI_FLX1_CTS \ + (_VF6XX_PAD_PAD_29__SCI_FLX1_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_29__QUADSPI0_QPCS1_B \ + (_VF6XX_PAD_PAD_29__QUADSPI0_QPCS1_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_29__LCD_64F6B_LCD41 \ + (_VF6XX_PAD_PAD_29__LCD_64F6B_LCD41 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_29__VIDEO_IN0_VSYNC \ + (_VF6XX_PAD_PAD_29__VIDEO_IN0_VSYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_29__SCI_FLX2_RX \ + (_VF6XX_PAD_PAD_29__SCI_FLX2_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_30__RGPIOC_GPIO30 \ + (_VF6XX_PAD_PAD_30__RGPIOC_GPIO30 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_30__FLEXTIMER1_CH0 \ + (_VF6XX_PAD_PAD_30__FLEXTIMER1_CH0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_30__FLEXTIMER0_QD_PHA \ + (_VF6XX_PAD_PAD_30__FLEXTIMER0_QD_PHA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_30__VIDEO_IN0_VIU_DE \ + (_VF6XX_PAD_PAD_30__VIDEO_IN0_VIU_DE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_30__TCON1_DATA_OUT24 \ + (_VF6XX_PAD_PAD_30__TCON1_DATA_OUT24 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_31__RGPIOC_GPIO31 \ + (_VF6XX_PAD_PAD_31__RGPIOC_GPIO31 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_31__FLEXTIMER1_CH1 \ + (_VF6XX_PAD_PAD_31__FLEXTIMER1_CH1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_31__FLEXTIMER1_QD_PHB \ + (_VF6XX_PAD_PAD_31__FLEXTIMER1_QD_PHB | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_31__TCON1_DATA_OUT25 \ + (_VF6XX_PAD_PAD_31__TCON1_DATA_OUT25 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_32__RGPIOC_GPIO32 \ + (_VF6XX_PAD_PAD_32__RGPIOC_GPIO32 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_32__SCI_FLX0_TX \ + (_VF6XX_PAD_PAD_32__SCI_FLX0_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_32__TCON0_TCON4 \ + (_VF6XX_PAD_PAD_32__TCON0_TCON4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_32__VIDEO_IN0_VIU_DE \ + (_VF6XX_PAD_PAD_32__VIDEO_IN0_VIU_DE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_32__CCM_CKO1 \ + (_VF6XX_PAD_PAD_32__CCM_CKO1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_32__CCM_ENET_TS_CLKIN \ + (_VF6XX_PAD_PAD_32__CCM_ENET_TS_CLKIN | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_33__RGPIOC_GPIO33 \ + (_VF6XX_PAD_PAD_33__RGPIOC_GPIO33 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_33__SCI_FLX0_RX \ + (_VF6XX_PAD_PAD_33__SCI_FLX0_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_33__TCON0_TCON5 \ + (_VF6XX_PAD_PAD_33__TCON0_TCON5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_33__SNVS_LP_WRAPPER_SNVS_ALARM_OUT \ + (_VF6XX_PAD_PAD_33__SNVS_LP_WRAPPER_SNVS_ALARM_OUT | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_33__CCM_CKO2 \ + (_VF6XX_PAD_PAD_33__CCM_CKO2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_33__ENET_SWIAHB_MAC0_TMR0 \ + (_VF6XX_PAD_PAD_33__ENET_SWIAHB_MAC0_TMR0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_34__RGPIOC_GPIO34 \ + (_VF6XX_PAD_PAD_34__RGPIOC_GPIO34 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_34__SCI_FLX0_RTS \ + (_VF6XX_PAD_PAD_34__SCI_FLX0_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_34__DSPI0_CS5 \ + (_VF6XX_PAD_PAD_34__DSPI0_CS5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_34__TCON0_TCON6 \ + (_VF6XX_PAD_PAD_34__TCON0_TCON6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_34__PLATFORM_FB_AD1 \ + (_VF6XX_PAD_PAD_34__PLATFORM_FB_AD1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_34__ENET_SWIAHB_MAC0_TMR1 \ + (_VF6XX_PAD_PAD_34__ENET_SWIAHB_MAC0_TMR1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_35__RGPIOC_GPIO35 \ + (_VF6XX_PAD_PAD_35__RGPIOC_GPIO35 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_35__SCI_FLX0_CTS \ + (_VF6XX_PAD_PAD_35__SCI_FLX0_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_35__DSPI0_CS4 \ + (_VF6XX_PAD_PAD_35__DSPI0_CS4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_35__TCON0_TCON7 \ + (_VF6XX_PAD_PAD_35__TCON0_TCON7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_35__PLATFORM_FB_AD0 \ + (_VF6XX_PAD_PAD_35__PLATFORM_FB_AD0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_35__PLATFORM_TRACETL \ + (_VF6XX_PAD_PAD_35__PLATFORM_TRACETL | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_36__RGPIOC_GPIO36 \ + (_VF6XX_PAD_PAD_36__RGPIOC_GPIO36 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_36__CAN0_RXD \ + (_VF6XX_PAD_PAD_36__CAN0_RXD | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_36__I2C0_SCL \ + (_VF6XX_PAD_PAD_36__I2C0_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_36__TCON0_TCON8 \ + (_VF6XX_PAD_PAD_36__TCON0_TCON8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_36__TCON1_DATA_OUT1 \ + (_VF6XX_PAD_PAD_36__TCON1_DATA_OUT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_37__RGPIOC_GPIO37 \ + (_VF6XX_PAD_PAD_37__RGPIOC_GPIO37 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_37__CAN0_TXD \ + (_VF6XX_PAD_PAD_37__CAN0_TXD | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_37__I2C0_SDA \ + (_VF6XX_PAD_PAD_37__I2C0_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_37__TCON0_TCON9 \ + (_VF6XX_PAD_PAD_37__TCON0_TCON9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_37__VIDEO_IN0_PIX_CLK \ + (_VF6XX_PAD_PAD_37__VIDEO_IN0_PIX_CLK | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_38__RGPIOC_GPIO38 \ + (_VF6XX_PAD_PAD_38__RGPIOC_GPIO38 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_38__CAN1_RXD \ + (_VF6XX_PAD_PAD_38__CAN1_RXD | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_38__I2C1_SCL \ + (_VF6XX_PAD_PAD_38__I2C1_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_38__TCON0_TCON10 \ + (_VF6XX_PAD_PAD_38__TCON0_TCON10 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_39__RGPIOC_GPIO39 \ + (_VF6XX_PAD_PAD_39__RGPIOC_GPIO39 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_39__CAN1_TXD \ + (_VF6XX_PAD_PAD_39__CAN1_TXD | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_39__I2C1_SDA \ + (_VF6XX_PAD_PAD_39__I2C1_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_39__TCON0_TCON11 \ + (_VF6XX_PAD_PAD_39__TCON0_TCON11 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_40__RGPIOC_GPIO40 \ + (_VF6XX_PAD_PAD_40__RGPIOC_GPIO40 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_40__DSPI0_CS1 \ + (_VF6XX_PAD_PAD_40__DSPI0_CS1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_40__CCM_EXT_AUDIO_MCLK \ + (_VF6XX_PAD_PAD_40__CCM_EXT_AUDIO_MCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_40__VIDEO_IN0_DATA9 \ + (_VF6XX_PAD_PAD_40__VIDEO_IN0_DATA9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_40__CCM_CCMOBS0 \ + (_VF6XX_PAD_PAD_40__CCM_CCMOBS0 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_41__RGPIOC_GPIO41 \ + (_VF6XX_PAD_PAD_41__RGPIOC_GPIO41 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_41__DSPI0_CS0 \ + (_VF6XX_PAD_PAD_41__DSPI0_CS0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_41__VIDEO_IN0_DATA10 \ + (_VF6XX_PAD_PAD_41__VIDEO_IN0_DATA10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_41__CCM_CCMOBS1 \ + (_VF6XX_PAD_PAD_41__CCM_CCMOBS1 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_42__RGPIOC_GPIO42 \ + (_VF6XX_PAD_PAD_42__RGPIOC_GPIO42 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_42__DSPI0_SIN \ + (_VF6XX_PAD_PAD_42__DSPI0_SIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_42__LCD_64F6B_LCD42 \ + (_VF6XX_PAD_PAD_42__LCD_64F6B_LCD42 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_42__VIDEO_IN0_DATA11 \ + (_VF6XX_PAD_PAD_42__VIDEO_IN0_DATA11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_42__CCM_CCMOBS2 \ + (_VF6XX_PAD_PAD_42__CCM_CCMOBS2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_43__RGPIOC_GPIO43 \ + (_VF6XX_PAD_PAD_43__RGPIOC_GPIO43 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_43__DSPI0_SOUT \ + (_VF6XX_PAD_PAD_43__DSPI0_SOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_43__LCD_64F6B_LCD43 \ + (_VF6XX_PAD_PAD_43__LCD_64F6B_LCD43 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_43__VIDEO_IN0_DATA2 \ + (_VF6XX_PAD_PAD_43__VIDEO_IN0_DATA2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_43__TCON1_DATA_OUT1 \ + (_VF6XX_PAD_PAD_43__TCON1_DATA_OUT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_44__RGPIOC_GPIO44 \ + (_VF6XX_PAD_PAD_44__RGPIOC_GPIO44 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_44__DSPI0_SCK \ + (_VF6XX_PAD_PAD_44__DSPI0_SCK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_44__VIDEO_IN0_VIU_FID \ + (_VF6XX_PAD_PAD_44__VIDEO_IN0_VIU_FID | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_45__RGPIOC_GPIO45 \ + (_VF6XX_PAD_PAD_45__RGPIOC_GPIO45 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__ENET_SWIAHB_RMII0_MDC \ + (_VF6XX_PAD_PAD_45__ENET_SWIAHB_RMII0_MDC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__FLEXTIMER1_CH0 \ + (_VF6XX_PAD_PAD_45__FLEXTIMER1_CH0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__DSPI0_CS3 \ + (_VF6XX_PAD_PAD_45__DSPI0_CS3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__ESABI_SCKT \ + (_VF6XX_PAD_PAD_45__ESABI_SCKT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__ESDHC0_CLK \ + (_VF6XX_PAD_PAD_45__ESDHC0_CLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__VIDEO_IN0_DATA0 \ + (_VF6XX_PAD_PAD_45__VIDEO_IN0_DATA0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_45__SRC_RCON18 \ + (_VF6XX_PAD_PAD_45__SRC_RCON18 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_46__RGPIOC_GPIO46 \ + (_VF6XX_PAD_PAD_46__RGPIOC_GPIO46 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__ENET_SWIAHB_RMII0_MDIO \ + (_VF6XX_PAD_PAD_46__ENET_SWIAHB_RMII0_MDIO | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__FLEXTIMER1_CH1 \ + (_VF6XX_PAD_PAD_46__FLEXTIMER1_CH1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__DSPI0_CS2 \ + (_VF6XX_PAD_PAD_46__DSPI0_CS2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__ESAI_FST \ + (_VF6XX_PAD_PAD_46__ESAI_FST | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__ESDHC0_CMD \ + (_VF6XX_PAD_PAD_46__ESDHC0_CMD | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__VIDEO_IN0_DATA1 \ + (_VF6XX_PAD_PAD_46__VIDEO_IN0_DATA1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_46__SRC_RCON19 \ + (_VF6XX_PAD_PAD_46__SRC_RCON19 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_47__RGPIOC_GPIO47 \ + (_VF6XX_PAD_PAD_47__RGPIOC_GPIO47 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_47__ENET_SWIAHB_RMII0_CRS_DV \ + (_VF6XX_PAD_PAD_47__ENET_SWIAHB_RMII0_CRS_DV | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_47__SCI_FLX1_TX \ + (_VF6XX_PAD_PAD_47__SCI_FLX1_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_47__ESAI_SDO0 \ + (_VF6XX_PAD_PAD_47__ESAI_SDO0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_47__ESDHC0_DAT0 \ + (_VF6XX_PAD_PAD_47__ESDHC0_DAT0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_47__VIDEO_IN0_DATA2 \ + (_VF6XX_PAD_PAD_47__VIDEO_IN0_DATA2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_47__SRC_RCON20 \ + (_VF6XX_PAD_PAD_47__SRC_RCON20 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_48__RGPIOC_GPIO48 \ + (_VF6XX_PAD_PAD_48__RGPIOC_GPIO48 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_48__ENET_SWIAHB_RMII0_RXD1 \ + (_VF6XX_PAD_PAD_48__ENET_SWIAHB_RMII0_RXD1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_48__SCI_FLX1_RX \ + (_VF6XX_PAD_PAD_48__SCI_FLX1_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_48__ESAI_SDO1 \ + (_VF6XX_PAD_PAD_48__ESAI_SDO1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_48__ESDHC0_DAT1 \ + (_VF6XX_PAD_PAD_48__ESDHC0_DAT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_48__VIDEO_IN0_DATA3 \ + (_VF6XX_PAD_PAD_48__VIDEO_IN0_DATA3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_48__TCON0_DATA_OUT18 \ + (_VF6XX_PAD_PAD_48__TCON0_DATA_OUT18 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_49__RGPIOC_GPIO49 \ + (_VF6XX_PAD_PAD_49__RGPIOC_GPIO49 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__ENET_SWIAHB_RMII0_RXD0 \ + (_VF6XX_PAD_PAD_49__ENET_SWIAHB_RMII0_RXD0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__SCI_FLX1_RTS \ + (_VF6XX_PAD_PAD_49__SCI_FLX1_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__DSPI1_CS1 \ + (_VF6XX_PAD_PAD_49__DSPI1_CS1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__ESAI_SDO2 \ + (_VF6XX_PAD_PAD_49__ESAI_SDO2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__ESDHC0_DAT2 \ + (_VF6XX_PAD_PAD_49__ESDHC0_DAT2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__VIDEO_IN0_DATA4 \ + (_VF6XX_PAD_PAD_49__VIDEO_IN0_DATA4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_49__TCON0_DATA_OUT19 \ + (_VF6XX_PAD_PAD_49__TCON0_DATA_OUT19 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_50__RGPIOC_GPIO50 \ + (_VF6XX_PAD_PAD_50__RGPIOC_GPIO50 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__ENET_SWIAHB_RMII0_RXER \ + (_VF6XX_PAD_PAD_50__ENET_SWIAHB_RMII0_RXER | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__SCI_FLX1_CTS \ + (_VF6XX_PAD_PAD_50__SCI_FLX1_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__DSPI1_CS0 \ + (_VF6XX_PAD_PAD_50__DSPI1_CS0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__ESAI_SDO3 \ + (_VF6XX_PAD_PAD_50__ESAI_SDO3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__ESDHC0_DAT3 \ + (_VF6XX_PAD_PAD_50__ESDHC0_DAT3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__VIDEO_IN0_DATA5 \ + (_VF6XX_PAD_PAD_50__VIDEO_IN0_DATA5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_50__TCON0_DATA_OUT10 \ + (_VF6XX_PAD_PAD_50__TCON0_DATA_OUT10 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_51__RGPIOC_GPIO51 \ + (_VF6XX_PAD_PAD_51__RGPIOC_GPIO51 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_51__ENET_SWIAHB_RMII0_TXD1 \ + (_VF6XX_PAD_PAD_51__ENET_SWIAHB_RMII0_TXD1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_51__DSPI1_SIN \ + (_VF6XX_PAD_PAD_51__DSPI1_SIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_51__ESAI_SDI0 \ + (_VF6XX_PAD_PAD_51__ESAI_SDI0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_51__ESDHC0_WP \ + (_VF6XX_PAD_PAD_51__ESDHC0_WP | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_51__VIDEO_IN0_DATA6 \ + (_VF6XX_PAD_PAD_51__VIDEO_IN0_DATA6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_51__TCON0_DATA_OUT11 \ + (_VF6XX_PAD_PAD_51__TCON0_DATA_OUT11 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_52__RGPIOC_GPIO52 \ + (_VF6XX_PAD_PAD_52__RGPIOC_GPIO52 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_52__ENET_SWIAHB_RMII0_TXD0 \ + (_VF6XX_PAD_PAD_52__ENET_SWIAHB_RMII0_TXD0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_52__DSPI1_SOUT \ + (_VF6XX_PAD_PAD_52__DSPI1_SOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_52__ESAI_SDI1 \ + (_VF6XX_PAD_PAD_52__ESAI_SDI1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_52__VIDEO_IN0_DATA7 \ + (_VF6XX_PAD_PAD_52__VIDEO_IN0_DATA7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_52__TCON0_DATA_OUT2 \ + (_VF6XX_PAD_PAD_52__TCON0_DATA_OUT2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_53__RGPIOC_GPIO53 \ + (_VF6XX_PAD_PAD_53__RGPIOC_GPIO53 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_53__ENET_SWIAHB_RMII0_TXEN \ + (_VF6XX_PAD_PAD_53__ENET_SWIAHB_RMII0_TXEN | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_53__DSPI1_SCK \ + (_VF6XX_PAD_PAD_53__DSPI1_SCK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_53__VIDEO_IN0_DATA8 \ + (_VF6XX_PAD_PAD_53__VIDEO_IN0_DATA8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_53__TCON0_DATA_OUT3 \ + (_VF6XX_PAD_PAD_53__TCON0_DATA_OUT3 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_54__RGPIOC_GPIO54 \ + (_VF6XX_PAD_PAD_54__RGPIOC_GPIO54 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_54__ENET_SWIAHB_RMII1_MDC \ + (_VF6XX_PAD_PAD_54__ENET_SWIAHB_RMII1_MDC | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_54__ESAI_SCKT \ + (_VF6XX_PAD_PAD_54__ESAI_SCKT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_54__MLB_TOP_MLBCLK \ + (_VF6XX_PAD_PAD_54__MLB_TOP_MLBCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_54__VIU_MUX_DEBUG_OUT \ + (_VF6XX_PAD_PAD_54__VIU_MUX_DEBUG_OUT | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_55__RGPIOC_GPIO55 \ + (_VF6XX_PAD_PAD_55__RGPIOC_GPIO55 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_55__ENET_SWIAHB_RMII1_MDIO \ + (_VF6XX_PAD_PAD_55__ENET_SWIAHB_RMII1_MDIO | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_55__ESAI_FST \ + (_VF6XX_PAD_PAD_55__ESAI_FST | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_55__MLB_TOP_MLBSIGNAL \ + (_VF6XX_PAD_PAD_55__MLB_TOP_MLBSIGNAL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_55__VIU_MUX_DEBUG_OUT1 \ + (_VF6XX_PAD_PAD_55__VIU_MUX_DEBUG_OUT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_56__RGPIOC_GPIO56 \ + (_VF6XX_PAD_PAD_56__RGPIOC_GPIO56 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_56__ENET_SWIAHB_RMII1_CRS_DV \ + (_VF6XX_PAD_PAD_56__ENET_SWIAHB_RMII1_CRS_DV | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_56__ESAI_SDO0 \ + (_VF6XX_PAD_PAD_56__ESAI_SDO0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_56__MLB_TOP_MLBDATA \ + (_VF6XX_PAD_PAD_56__MLB_TOP_MLBDATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_56__VIU_MUX_DEBUG_OUT2 \ + (_VF6XX_PAD_PAD_56__VIU_MUX_DEBUG_OUT2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_57__RGPIOC_GPIO57 \ + (_VF6XX_PAD_PAD_57__RGPIOC_GPIO57 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_57__ENET_SWIAHB_RMII1_RXD1 \ + (_VF6XX_PAD_PAD_57__ENET_SWIAHB_RMII1_RXD1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_57__ESAI_SDO1 \ + (_VF6XX_PAD_PAD_57__ESAI_SDO1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_57__SAI2_TX_BCLK \ + (_VF6XX_PAD_PAD_57__SAI2_TX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_57__VIU_MUX_DEBUG_OUT3 \ + (_VF6XX_PAD_PAD_57__VIU_MUX_DEBUG_OUT3 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_58__RGPIOC_GPIO58 \ + (_VF6XX_PAD_PAD_58__RGPIOC_GPIO58 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_58__ENET_SWIAHB_RMII1_RXD0 \ + (_VF6XX_PAD_PAD_58__ENET_SWIAHB_RMII1_RXD0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_58__ESAI_SDO2 \ + (_VF6XX_PAD_PAD_58__ESAI_SDO2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_58__SAI2_RX_BCLK \ + (_VF6XX_PAD_PAD_58__SAI2_RX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_58__VIU_MUX_DEBUG_OUT4 \ + (_VF6XX_PAD_PAD_58__VIU_MUX_DEBUG_OUT4 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_59__RGPIOC_GPIO59 \ + (_VF6XX_PAD_PAD_59__RGPIOC_GPIO59 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_59__ENET_SWIAHB_RMII1_RXER \ + (_VF6XX_PAD_PAD_59__ENET_SWIAHB_RMII1_RXER | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_59__ESAI_SDO3 \ + (_VF6XX_PAD_PAD_59__ESAI_SDO3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_59__SCI_FLX5_TX \ + (_VF6XX_PAD_PAD_59__SCI_FLX5_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_59__SAI2_RX_DATA \ + (_VF6XX_PAD_PAD_59__SAI2_RX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_59__ADC0_DA_ADC0SE6 \ + (_VF6XX_PAD_PAD_59__ADC0_DA_ADC0SE6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_59__VIU_MUX_DEBUG_OUT5 \ + (_VF6XX_PAD_PAD_59__VIU_MUX_DEBUG_OUT5 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_60__RGPIOC_GPIO60 \ + (_VF6XX_PAD_PAD_60__RGPIOC_GPIO60 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_60__ENET_SWIAHB_RMII1_TXD1 \ + (_VF6XX_PAD_PAD_60__ENET_SWIAHB_RMII1_TXD1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_60__ESAI_SDI0 \ + (_VF6XX_PAD_PAD_60__ESAI_SDI0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_60__SCI_FLX5_RX \ + (_VF6XX_PAD_PAD_60__SCI_FLX5_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_60__SAI2_TX_DATA \ + (_VF6XX_PAD_PAD_60__SAI2_TX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_60__ADC0_DA_ADC0SE7 \ + (_VF6XX_PAD_PAD_60__ADC0_DA_ADC0SE7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_60__VIU_MUX_DEBUG_OUT6 \ + (_VF6XX_PAD_PAD_60__VIU_MUX_DEBUG_OUT6 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_61__RGPIOC_GPIO61 \ + (_VF6XX_PAD_PAD_61__RGPIOC_GPIO61 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_61__ENET_SWIAHB_RMII1_TXD0 \ + (_VF6XX_PAD_PAD_61__ENET_SWIAHB_RMII1_TXD0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_61__ESAI_SDI1 \ + (_VF6XX_PAD_PAD_61__ESAI_SDI1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_61__SCI_FLX5_RTS \ + (_VF6XX_PAD_PAD_61__SCI_FLX5_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_61__SAI2_RX_SYNC \ + (_VF6XX_PAD_PAD_61__SAI2_RX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_61__ADC1_DA_ADC1SE6 \ + (_VF6XX_PAD_PAD_61__ADC1_DA_ADC1SE6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_61__VIU_MUX_DEBUG_OUT7 \ + (_VF6XX_PAD_PAD_61__VIU_MUX_DEBUG_OUT7 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_62__RGPIOC_GPIO62 \ + (_VF6XX_PAD_PAD_62__RGPIOC_GPIO62 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_62__ENET_SWIAHB_RMII1_TXEN \ + (_VF6XX_PAD_PAD_62__ENET_SWIAHB_RMII1_TXEN | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_62__ADC1_DA_ADC1SE7 \ + (_VF6XX_PAD_PAD_62__ADC1_DA_ADC1SE7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_62__SCI_FLX5_CTS \ + (_VF6XX_PAD_PAD_62__SCI_FLX5_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_62__SAI2_TX_SYNC \ + (_VF6XX_PAD_PAD_62__SAI2_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_62__USB_VF6XX_USB1_SOF_PULSE \ + (_VF6XX_PAD_PAD_62__USB_VF6XX_USB1_SOF_PULSE | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_62__VIU_MUX_DEBUG_OUT8 \ + (_VF6XX_PAD_PAD_62__VIU_MUX_DEBUG_OUT8 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_63__RGPIOC_GPIO63 \ + (_VF6XX_PAD_PAD_63__RGPIOC_GPIO63 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_63__PLATFORM_FB_AD3 \ + (_VF6XX_PAD_PAD_63__PLATFORM_FB_AD3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_63__NFC_MLC_NF_IO15 \ + (_VF6XX_PAD_PAD_63__NFC_MLC_NF_IO15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_63__FLEXTIMER3_CH0 \ + (_VF6XX_PAD_PAD_63__FLEXTIMER3_CH0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_63__DSPI2_CS1 \ + (_VF6XX_PAD_PAD_63__DSPI2_CS1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_63__VIU_MUX_DEBUG_OUT9 \ + (_VF6XX_PAD_PAD_63__VIU_MUX_DEBUG_OUT9 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_64__RGPIOC_GPIO64 \ + (_VF6XX_PAD_PAD_64__RGPIOC_GPIO64 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_64__PLATFORM_FB_AD30 \ + (_VF6XX_PAD_PAD_64__PLATFORM_FB_AD30 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_64__NFC_MLC_NF_IO14 \ + (_VF6XX_PAD_PAD_64__NFC_MLC_NF_IO14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_64__FLEXTIMER3_CH1 \ + (_VF6XX_PAD_PAD_64__FLEXTIMER3_CH1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_64__DSPI2_CS0 \ + (_VF6XX_PAD_PAD_64__DSPI2_CS0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_64__VIU_MUX_DEBUG_OUT10 \ + (_VF6XX_PAD_PAD_64__VIU_MUX_DEBUG_OUT10 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_65__RGPIOC_GPIO65 \ + (_VF6XX_PAD_PAD_65__RGPIOC_GPIO65 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_65__PLATFORM_FB_AD29 \ + (_VF6XX_PAD_PAD_65__PLATFORM_FB_AD29 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_65__NFC_MLC_NF_IO13 \ + (_VF6XX_PAD_PAD_65__NFC_MLC_NF_IO13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_65__FLEXTIMER3_CH2 \ + (_VF6XX_PAD_PAD_65__FLEXTIMER3_CH2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_65__DSPI2_SIN \ + (_VF6XX_PAD_PAD_65__DSPI2_SIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_65__VIU_MUX_DEBUG_OUT11 \ + (_VF6XX_PAD_PAD_65__VIU_MUX_DEBUG_OUT11 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_66__RGPIOC_GPIO66 \ + (_VF6XX_PAD_PAD_66__RGPIOC_GPIO66 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_66__PLATFORM_FB_AD28 \ + (_VF6XX_PAD_PAD_66__PLATFORM_FB_AD28 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_66__NFC_MLC_NF_IO12 \ + (_VF6XX_PAD_PAD_66__NFC_MLC_NF_IO12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_66__I2C2_SCL \ + (_VF6XX_PAD_PAD_66__I2C2_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_66__FLEXTIMER3_CH3 \ + (_VF6XX_PAD_PAD_66__FLEXTIMER3_CH3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_66__DSPI2_SOUT \ + (_VF6XX_PAD_PAD_66__DSPI2_SOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_66__VIU_MUX_DEBUG_OUT12 \ + (_VF6XX_PAD_PAD_66__VIU_MUX_DEBUG_OUT12 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_67__RGPIOC_GPIO67 \ + (_VF6XX_PAD_PAD_67__RGPIOC_GPIO67 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_67__PLATFORM_FB_AD27 \ + (_VF6XX_PAD_PAD_67__PLATFORM_FB_AD27 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_67__NFC_MLC_NF_IO11 \ + (_VF6XX_PAD_PAD_67__NFC_MLC_NF_IO11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_67__I2C2_SDA \ + (_VF6XX_PAD_PAD_67__I2C2_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_67__FLEXTIMER3_CH4 \ + (_VF6XX_PAD_PAD_67__FLEXTIMER3_CH4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_67__DSPI2_SCK \ + (_VF6XX_PAD_PAD_67__DSPI2_SCK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_67__VIU_MUX_DEBUG_OUT13 \ + (_VF6XX_PAD_PAD_67__VIU_MUX_DEBUG_OUT13 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_68__RGPIOC_GPIO68 \ + (_VF6XX_PAD_PAD_68__RGPIOC_GPIO68 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_68__PLATFORM_FB_AD26 \ + (_VF6XX_PAD_PAD_68__PLATFORM_FB_AD26 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_68__NFC_MLC_NF_IO10 \ + (_VF6XX_PAD_PAD_68__NFC_MLC_NF_IO10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_68__FLEXTIMER3_CH5 \ + (_VF6XX_PAD_PAD_68__FLEXTIMER3_CH5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_68__ESDHC1_WP \ + (_VF6XX_PAD_PAD_68__ESDHC1_WP | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_68__VIU_MUX_DEBUG_OUT14 \ + (_VF6XX_PAD_PAD_68__VIU_MUX_DEBUG_OUT14 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_69__RGPIOC_GPIO69 \ + (_VF6XX_PAD_PAD_69__RGPIOC_GPIO69 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_69__PLATFORM_FB_AD25 \ + (_VF6XX_PAD_PAD_69__PLATFORM_FB_AD25 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_69__NFC_MLC_NF_IO9 \ + (_VF6XX_PAD_PAD_69__NFC_MLC_NF_IO9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_69__FLEXTIMER3_CH6 \ + (_VF6XX_PAD_PAD_69__FLEXTIMER3_CH6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_69__VIU_MUX_DEBUG_OUT15 \ + (_VF6XX_PAD_PAD_69__VIU_MUX_DEBUG_OUT15 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_70__RGPIOC_GPIO70 \ + (_VF6XX_PAD_PAD_70__RGPIOC_GPIO70 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_70__PLATFORM_FB_AD24 \ + (_VF6XX_PAD_PAD_70__PLATFORM_FB_AD24 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_70__NFC_MLC_NF_IO8 \ + (_VF6XX_PAD_PAD_70__NFC_MLC_NF_IO8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_70__FLEXTIMER3_CH7 \ + (_VF6XX_PAD_PAD_70__FLEXTIMER3_CH7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_70__VIU_MUX_DEBUG_OUT16 \ + (_VF6XX_PAD_PAD_70__VIU_MUX_DEBUG_OUT16 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_71__RGPIOC_GPIO71 \ + (_VF6XX_PAD_PAD_71__RGPIOC_GPIO71 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__PLATFORM_FB_AD23 \ + (_VF6XX_PAD_PAD_71__PLATFORM_FB_AD23 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__NFC_MLC_NF_IO7 \ + (_VF6XX_PAD_PAD_71__NFC_MLC_NF_IO7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__FLEXTIMER2_CH0 \ + (_VF6XX_PAD_PAD_71__FLEXTIMER2_CH0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__ENET_SWIAHB_MAC0_TMR0 \ + (_VF6XX_PAD_PAD_71__ENET_SWIAHB_MAC0_TMR0 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__ESDHC0_DAT4 \ + (_VF6XX_PAD_PAD_71__ESDHC0_DAT4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__SCI_FLX2_TX \ + (_VF6XX_PAD_PAD_71__SCI_FLX2_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_71__TCON1_DATA_OUT21 \ + (_VF6XX_PAD_PAD_71__TCON1_DATA_OUT21 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_72__RGPIOC_GPIO72 \ + (_VF6XX_PAD_PAD_72__RGPIOC_GPIO72 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__PLATFORM_FB_AD22 \ + (_VF6XX_PAD_PAD_72__PLATFORM_FB_AD22 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__NFC_MLC_NF_IO6 \ + (_VF6XX_PAD_PAD_72__NFC_MLC_NF_IO6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__FLEXTIMER2_CH1 \ + (_VF6XX_PAD_PAD_72__FLEXTIMER2_CH1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__ENET_SWIAHB_MAC0_TMR1 \ + (_VF6XX_PAD_PAD_72__ENET_SWIAHB_MAC0_TMR1 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__ESDHC0_DAT5 \ + (_VF6XX_PAD_PAD_72__ESDHC0_DAT5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__SCI_FLX2_RX \ + (_VF6XX_PAD_PAD_72__SCI_FLX2_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_72__TCON1_DATA_OUT22 \ + (_VF6XX_PAD_PAD_72__TCON1_DATA_OUT22 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_73__RGPIOC_GPIO73 \ + (_VF6XX_PAD_PAD_73__RGPIOC_GPIO73 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_73__PLATFORM_FB_AD21 \ + (_VF6XX_PAD_PAD_73__PLATFORM_FB_AD21 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_73__NFC_MLC_NF_IO5 \ + (_VF6XX_PAD_PAD_73__NFC_MLC_NF_IO5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_73__ENET_SWIAHB_MAC0_TMR2 \ + (_VF6XX_PAD_PAD_73__ENET_SWIAHB_MAC0_TMR2 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_73__ESDHC0_DAT6 \ + (_VF6XX_PAD_PAD_73__ESDHC0_DAT6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_73__SCI_FLX2_RTS \ + (_VF6XX_PAD_PAD_73__SCI_FLX2_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_73__TCON1_DATA_OUT23 \ + (_VF6XX_PAD_PAD_73__TCON1_DATA_OUT23 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_74__RGPIOC_GPIO74 \ + (_VF6XX_PAD_PAD_74__RGPIOC_GPIO74 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_74__PLATFORM_FB_AD20 \ + (_VF6XX_PAD_PAD_74__PLATFORM_FB_AD20 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_74__NFC_MLC_NF_IO4 \ + (_VF6XX_PAD_PAD_74__NFC_MLC_NF_IO4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_74__ENET_SWIAHB_MAC0_TMR3 \ + (_VF6XX_PAD_PAD_74__ENET_SWIAHB_MAC0_TMR3 | \ + MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_74__ESDHC0_DAT7 \ + (_VF6XX_PAD_PAD_74__ESDHC0_DAT7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_74__SCI_FLX2_CTS \ + (_VF6XX_PAD_PAD_74__SCI_FLX2_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_74__TCON1_DATA_OUT18 \ + (_VF6XX_PAD_PAD_74__TCON1_DATA_OUT18 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_75__RGPIOC_GPIO75 \ + (_VF6XX_PAD_PAD_75__RGPIOC_GPIO75 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_75__PLATFORM_FB_AD19 \ + (_VF6XX_PAD_PAD_75__PLATFORM_FB_AD19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_75__NFC_MLC_NF_IO3 \ + (_VF6XX_PAD_PAD_75__NFC_MLC_NF_IO3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_75__ESAI_SCKR \ + (_VF6XX_PAD_PAD_75__ESAI_SCKR | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_75__I2C0_SCL \ + (_VF6XX_PAD_PAD_75__I2C0_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_75__FLEXTIMER2_QD_PHA \ + (_VF6XX_PAD_PAD_75__FLEXTIMER2_QD_PHA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_75__TCON1_DATA_OUT19 \ + (_VF6XX_PAD_PAD_75__TCON1_DATA_OUT19 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_76__RGPIOC_GPIO76 \ + (_VF6XX_PAD_PAD_76__RGPIOC_GPIO76 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_76__PLATFORM_FB_AD18 \ + (_VF6XX_PAD_PAD_76__PLATFORM_FB_AD18 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_76__NFC_MLC_NF_IO2 \ + (_VF6XX_PAD_PAD_76__NFC_MLC_NF_IO2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_76__ESAI_FSR \ + (_VF6XX_PAD_PAD_76__ESAI_FSR | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_76__I2C0_SDA \ + (_VF6XX_PAD_PAD_76__I2C0_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_76__FLEXTIMER2_QD_PHB \ + (_VF6XX_PAD_PAD_76__FLEXTIMER2_QD_PHB | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_76__TCON1_DATA_OUT10 \ + (_VF6XX_PAD_PAD_76__TCON1_DATA_OUT10 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_77__RGPIOC_GPIO77 \ + (_VF6XX_PAD_PAD_77__RGPIOC_GPIO77 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_77__PLATFORM_FB_AD17 \ + (_VF6XX_PAD_PAD_77__PLATFORM_FB_AD17 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_77__NFC_MLC_NF_IO1 \ + (_VF6XX_PAD_PAD_77__NFC_MLC_NF_IO1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_77__ESAI_HCKR \ + (_VF6XX_PAD_PAD_77__ESAI_HCKR | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_77__I2C1_SCL \ + (_VF6XX_PAD_PAD_77__I2C1_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_77__TCON1_DATA_OUT11 \ + (_VF6XX_PAD_PAD_77__TCON1_DATA_OUT11 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_78__RGPIOC_GPIO78 \ + (_VF6XX_PAD_PAD_78__RGPIOC_GPIO78 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_78__PLATFORM_FB_AD16 \ + (_VF6XX_PAD_PAD_78__PLATFORM_FB_AD16 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_78__NFC_MLC_NF_IO0 \ + (_VF6XX_PAD_PAD_78__NFC_MLC_NF_IO0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_78__ESAI_HCKT \ + (_VF6XX_PAD_PAD_78__ESAI_HCKT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_78__I2C1_SDA \ + (_VF6XX_PAD_PAD_78__I2C1_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_78__TCON1_DATA_OUT12 \ + (_VF6XX_PAD_PAD_78__TCON1_DATA_OUT12 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_79__RGPIOC_GPIO79 \ + (_VF6XX_PAD_PAD_79__RGPIOC_GPIO79 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_79__QUADSPI0_QSCK_A \ + (_VF6XX_PAD_PAD_79__QUADSPI0_QSCK_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_79__SCI_FLX2_TX \ + (_VF6XX_PAD_PAD_79__SCI_FLX2_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_79__PLATFORM_FB_AD15 \ + (_VF6XX_PAD_PAD_79__PLATFORM_FB_AD15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_79__SPDIF_EXTCLK \ + (_VF6XX_PAD_PAD_79__SPDIF_EXTCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_79__VIU_MUX_DEBUG_OUT17 \ + (_VF6XX_PAD_PAD_79__VIU_MUX_DEBUG_OUT17 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_80__RGPIOC_GPIO80 \ + (_VF6XX_PAD_PAD_80__RGPIOC_GPIO80 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_80__QUADSPI0_QPCS0_A \ + (_VF6XX_PAD_PAD_80__QUADSPI0_QPCS0_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_80__SCI_FLX2_RX \ + (_VF6XX_PAD_PAD_80__SCI_FLX2_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_80__PLATFORM_FB_AD14 \ + (_VF6XX_PAD_PAD_80__PLATFORM_FB_AD14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_80__SPDIF_IN1 \ + (_VF6XX_PAD_PAD_80__SPDIF_IN1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_80__VIU_MUX_DEBUG_OUT18 \ + (_VF6XX_PAD_PAD_80__VIU_MUX_DEBUG_OUT18 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_81__RGPIOC_GPIO81 \ + (_VF6XX_PAD_PAD_81__RGPIOC_GPIO81 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_81__QUADSPI0_QSPI_IO3_A \ + (_VF6XX_PAD_PAD_81__QUADSPI0_QSPI_IO3_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_81__SCI_FLX2_RTS \ + (_VF6XX_PAD_PAD_81__SCI_FLX2_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_81__DSPI1_CS3 \ + (_VF6XX_PAD_PAD_81__DSPI1_CS3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_81__PLATFORM_FB_AD13 \ + (_VF6XX_PAD_PAD_81__PLATFORM_FB_AD13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_81__SPDIF_OUT1 \ + (_VF6XX_PAD_PAD_81__SPDIF_OUT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_81__VIU_MUX_DEBUG_OUT19 \ + (_VF6XX_PAD_PAD_81__VIU_MUX_DEBUG_OUT19 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_82__RGPIOC_GPIO82 \ + (_VF6XX_PAD_PAD_82__RGPIOC_GPIO82 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_82__QUADSPI0_QSPI_IO2_A \ + (_VF6XX_PAD_PAD_82__QUADSPI0_QSPI_IO2_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_82__SCI_FLX2_CTS \ + (_VF6XX_PAD_PAD_82__SCI_FLX2_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_82__DSPI1_CS2 \ + (_VF6XX_PAD_PAD_82__DSPI1_CS2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_82__PLATFORM_FB_AD12 \ + (_VF6XX_PAD_PAD_82__PLATFORM_FB_AD12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_82__SPDIF_PLOCK \ + (_VF6XX_PAD_PAD_82__SPDIF_PLOCK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_82__VIU_MUX_DEBUG_OUT20 \ + (_VF6XX_PAD_PAD_82__VIU_MUX_DEBUG_OUT20 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_83__RGPIOC_GPIO83 \ + (_VF6XX_PAD_PAD_83__RGPIOC_GPIO83 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_83__QUADSPI0_QSPI_IO1_A \ + (_VF6XX_PAD_PAD_83__QUADSPI0_QSPI_IO1_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_83__DSPI1_CS1 \ + (_VF6XX_PAD_PAD_83__DSPI1_CS1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_83__PLATFORM_FB_AD11 \ + (_VF6XX_PAD_PAD_83__PLATFORM_FB_AD11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_83__SPDIF_SRCLK \ + (_VF6XX_PAD_PAD_83__SPDIF_SRCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_83__VIU_MUX_DEBUG_OUT21 \ + (_VF6XX_PAD_PAD_83__VIU_MUX_DEBUG_OUT21 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_84__RGPIOC_GPIO84 \ + (_VF6XX_PAD_PAD_84__RGPIOC_GPIO84 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_84__QUADSPI0_QSPI_IO0_A \ + (_VF6XX_PAD_PAD_84__QUADSPI0_QSPI_IO0_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_84__DSPI1_CS0 \ + (_VF6XX_PAD_PAD_84__DSPI1_CS0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_84__PLATFORM_FB_AD10 \ + (_VF6XX_PAD_PAD_84__PLATFORM_FB_AD10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_84__VIU_MUX_DEBUG_OUT22 \ + (_VF6XX_PAD_PAD_84__VIU_MUX_DEBUG_OUT22 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_85__RGPIOC_GPIO85 \ + (_VF6XX_PAD_PAD_85__RGPIOC_GPIO85 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_85__QUADSPI0_DQS_A \ + (_VF6XX_PAD_PAD_85__QUADSPI0_DQS_A | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_85__DSPI1_SIN \ + (_VF6XX_PAD_PAD_85__DSPI1_SIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_85__PLATFORM_FB_AD9 \ + (_VF6XX_PAD_PAD_85__PLATFORM_FB_AD9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_85__VIU_MUX_DEBUG_OUT23 \ + (_VF6XX_PAD_PAD_85__VIU_MUX_DEBUG_OUT23 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_86__RGPIOC_GPIO86 \ + (_VF6XX_PAD_PAD_86__RGPIOC_GPIO86 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_86__QUADSPI0_QSCK_B \ + (_VF6XX_PAD_PAD_86__QUADSPI0_QSCK_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_86__DSPI1_SOUT \ + (_VF6XX_PAD_PAD_86__DSPI1_SOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_86__PLATFORM_FB_AD8 \ + (_VF6XX_PAD_PAD_86__PLATFORM_FB_AD8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_86__VIU_MUX_DEBUG_OUT24 \ + (_VF6XX_PAD_PAD_86__VIU_MUX_DEBUG_OUT24 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_87__RGPIOC_GPIO87 \ + (_VF6XX_PAD_PAD_87__RGPIOC_GPIO87 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_87__QUADSPI0_QPCS0_B \ + (_VF6XX_PAD_PAD_87__QUADSPI0_QPCS0_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_87__LPCG0_FB_CLKOUT \ + (_VF6XX_PAD_PAD_87__LPCG0_FB_CLKOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_87__DSPI1_SCK \ + (_VF6XX_PAD_PAD_87__DSPI1_SCK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_87__PLATFORM_FB_AD7 \ + (_VF6XX_PAD_PAD_87__PLATFORM_FB_AD7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_87__VIU_MUX_DEBUG_OUT25 \ + (_VF6XX_PAD_PAD_87__VIU_MUX_DEBUG_OUT25 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_88__RGPIOC_GPIO88 \ + (_VF6XX_PAD_PAD_88__RGPIOC_GPIO88 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_88__QUADSPI0_QSPI_IO3_B \ + (_VF6XX_PAD_PAD_88__QUADSPI0_QSPI_IO3_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_88__DSPI3_CS1 \ + (_VF6XX_PAD_PAD_88__DSPI3_CS1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_88__PLATFORM_FB_AD6 \ + (_VF6XX_PAD_PAD_88__PLATFORM_FB_AD6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_88__SAI1_TX_SYNC \ + (_VF6XX_PAD_PAD_88__SAI1_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_88__TCON1_DATA_OUT2 \ + (_VF6XX_PAD_PAD_88__TCON1_DATA_OUT2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_89__RGPIOC_GPIO89 \ + (_VF6XX_PAD_PAD_89__RGPIOC_GPIO89 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_89__QUADSPI0_QSPI_IO2_B \ + (_VF6XX_PAD_PAD_89__QUADSPI0_QSPI_IO2_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_89__DSPI3_CS0 \ + (_VF6XX_PAD_PAD_89__DSPI3_CS0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_89__PLATFORM_FB_AD5 \ + (_VF6XX_PAD_PAD_89__PLATFORM_FB_AD5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_89__TCON1_DATA_OUT3 \ + (_VF6XX_PAD_PAD_89__TCON1_DATA_OUT3 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_90__RGPIOC_GPIO90 \ + (_VF6XX_PAD_PAD_90__RGPIOC_GPIO90 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_90__QUADSPI0_QSPI_IO1_B \ + (_VF6XX_PAD_PAD_90__QUADSPI0_QSPI_IO1_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_90__DSPI3_SIN \ + (_VF6XX_PAD_PAD_90__DSPI3_SIN | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_90__PLATFORM_FB_AD4 \ + (_VF6XX_PAD_PAD_90__PLATFORM_FB_AD4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_90__VIU_MUX_DEBUG_OUT26 \ + (_VF6XX_PAD_PAD_90__VIU_MUX_DEBUG_OUT26 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_91__RGPIOC_GPIO91 \ + (_VF6XX_PAD_PAD_91__RGPIOC_GPIO91 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_91__QUADSPI0_QSPI_IO0_B \ + (_VF6XX_PAD_PAD_91__QUADSPI0_QSPI_IO0_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_91__DSPI3_SOUT \ + (_VF6XX_PAD_PAD_91__DSPI3_SOUT | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_91__PLATFORM_FB_AD3 \ + (_VF6XX_PAD_PAD_91__PLATFORM_FB_AD3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_91__VIU_MUX_DEBUG_OUT27 \ + (_VF6XX_PAD_PAD_91__VIU_MUX_DEBUG_OUT27 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_92__RGPIOC_GPIO92 \ + (_VF6XX_PAD_PAD_92__RGPIOC_GPIO92 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_92__QUADSPI0_DQS_B \ + (_VF6XX_PAD_PAD_92__QUADSPI0_DQS_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_92__DSPI3_SCK \ + (_VF6XX_PAD_PAD_92__DSPI3_SCK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_92__PLATFORM_FB_AD2 \ + (_VF6XX_PAD_PAD_92__PLATFORM_FB_AD2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_92__VIU_MUX_DEBUG_OUT28 \ + (_VF6XX_PAD_PAD_92__VIU_MUX_DEBUG_OUT28 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_93__RGPIOC_GPIO93 \ + (_VF6XX_PAD_PAD_93__RGPIOC_GPIO93 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__SAI0_TX_BCLK \ + (_VF6XX_PAD_PAD_93__SAI0_TX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__SCI_FLX1_TX \ + (_VF6XX_PAD_PAD_93__SCI_FLX1_TX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__SRC_RCON18 \ + (_VF6XX_PAD_PAD_93__SRC_RCON18 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__PLATFORM_FB_ALE \ + (_VF6XX_PAD_PAD_93__PLATFORM_FB_ALE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__PLATFORM_FB_TS_B \ + (_VF6XX_PAD_PAD_93__PLATFORM_FB_TS_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__SCI_FLX3_RTS \ + (_VF6XX_PAD_PAD_93__SCI_FLX3_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_93__TCON1_DATA_OUT13 \ + (_VF6XX_PAD_PAD_93__TCON1_DATA_OUT13 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_94__RGPIOC_GPIO94 \ + (_VF6XX_PAD_PAD_94__RGPIOC_GPIO94 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__SAI0_RX_BCLK \ + (_VF6XX_PAD_PAD_94__SAI0_RX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__SCI_FLX1_RX \ + (_VF6XX_PAD_PAD_94__SCI_FLX1_RX | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__SRC_RCON19 \ + (_VF6XX_PAD_PAD_94__SRC_RCON19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__PLATFORM_FB_CS4_B \ + (_VF6XX_PAD_PAD_94__PLATFORM_FB_CS4_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__NFC_MLC_NF_WE_B \ + (_VF6XX_PAD_PAD_94__NFC_MLC_NF_WE_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__SCI_FLX3_CTS \ + (_VF6XX_PAD_PAD_94__SCI_FLX3_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_94__TCON1_DATA_OUT14 \ + (_VF6XX_PAD_PAD_94__TCON1_DATA_OUT14 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_95__RGPIOC_GPIO95 \ + (_VF6XX_PAD_PAD_95__RGPIOC_GPIO95 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_95__SAI0_RX_DATA \ + (_VF6XX_PAD_PAD_95__SAI0_RX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_95__SCI_FLX1_RTS \ + (_VF6XX_PAD_PAD_95__SCI_FLX1_RTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_95__SRC_RCON20 \ + (_VF6XX_PAD_PAD_95__SRC_RCON20 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_95__PLATFORM_FB_CS1_B \ + (_VF6XX_PAD_PAD_95__PLATFORM_FB_CS1_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_95__NFC_MLC_NF_CE0_B \ + (_VF6XX_PAD_PAD_95__NFC_MLC_NF_CE0_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_95__TCON1_DATA_OUT15 \ + (_VF6XX_PAD_PAD_95__TCON1_DATA_OUT15 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_96__RGPIOC_GPIO96 \ + (_VF6XX_PAD_PAD_96__RGPIOC_GPIO96 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_96__SAI0_TX_DATA \ + (_VF6XX_PAD_PAD_96__SAI0_TX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_96__SCI_FLX1_CTS \ + (_VF6XX_PAD_PAD_96__SCI_FLX1_CTS | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_96__SRC_RCON21 \ + (_VF6XX_PAD_PAD_96__SRC_RCON21 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_96__PLATFORM_FB_CS0_B \ + (_VF6XX_PAD_PAD_96__PLATFORM_FB_CS0_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_96__NFC_MLC_NF_CE1_B \ + (_VF6XX_PAD_PAD_96__NFC_MLC_NF_CE1_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_96__TCON1_DATA_OUT16 \ + (_VF6XX_PAD_PAD_96__TCON1_DATA_OUT16 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_97__RGPIOC_GPIO97 \ + (_VF6XX_PAD_PAD_97__RGPIOC_GPIO97 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_97__SAI0_RX_SYNC \ + (_VF6XX_PAD_PAD_97__SAI0_RX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_97__SRC_RCON22 \ + (_VF6XX_PAD_PAD_97__SRC_RCON22 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_97__PLATFORM_FB_OE_B \ + (_VF6XX_PAD_PAD_97__PLATFORM_FB_OE_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_97__PLATFORM_FB_TBST_B \ + (_VF6XX_PAD_PAD_97__PLATFORM_FB_TBST_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_97__NFC_MLC_NF_RE_B \ + (_VF6XX_PAD_PAD_97__NFC_MLC_NF_RE_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_97__TCON1_DATA_OUT17 \ + (_VF6XX_PAD_PAD_97__TCON1_DATA_OUT17 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_98__RGPIOC_GPIO98 \ + (_VF6XX_PAD_PAD_98__RGPIOC_GPIO98 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_98__SAI0_TX_SYNC \ + (_VF6XX_PAD_PAD_98__SAI0_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_98__SRC_RCON23 \ + (_VF6XX_PAD_PAD_98__SRC_RCON23 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_98__PLATFORM_FB_RW_B \ + (_VF6XX_PAD_PAD_98__PLATFORM_FB_RW_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_98__TCON1_DATA_OUT8 \ + (_VF6XX_PAD_PAD_98__TCON1_DATA_OUT8 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_99__RGPIOC_GPIO99 \ + (_VF6XX_PAD_PAD_99__RGPIOC_GPIO99 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_99__SAI1_TX_BCLK \ + (_VF6XX_PAD_PAD_99__SAI1_TX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_99__DSPI0_CS5 \ + (_VF6XX_PAD_PAD_99__DSPI0_CS5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_99__SRC_RCON24 \ + (_VF6XX_PAD_PAD_99__SRC_RCON24 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_99__PLATFORM_FB_TA_B \ + (_VF6XX_PAD_PAD_99__PLATFORM_FB_TA_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_99__NFC_MLC_NF_RB_B \ + (_VF6XX_PAD_PAD_99__NFC_MLC_NF_RB_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_99__TCON1_DATA_OUT9 \ + (_VF6XX_PAD_PAD_99__TCON1_DATA_OUT9 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_100__RGPIOC_GPIO100 \ + (_VF6XX_PAD_PAD_100__RGPIOC_GPIO100 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__SAI1_RX_BCLK \ + (_VF6XX_PAD_PAD_100__SAI1_RX_BCLK | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__DSPI0_CS4 \ + (_VF6XX_PAD_PAD_100__DSPI0_CS4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__SRC_RCON25 \ + (_VF6XX_PAD_PAD_100__SRC_RCON25 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__PLATFORM_FB_BE3_B \ + (_VF6XX_PAD_PAD_100__PLATFORM_FB_BE3_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__PLATFORM_FB_CS3_B \ + (_VF6XX_PAD_PAD_100__PLATFORM_FB_CS3_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__NFC_MLC_NF_ALE \ + (_VF6XX_PAD_PAD_100__NFC_MLC_NF_ALE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_100__TCON1_DATA_OUT4 \ + (_VF6XX_PAD_PAD_100__TCON1_DATA_OUT4 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_101__RGPIOC_GPIO101 \ + (_VF6XX_PAD_PAD_101__RGPIOC_GPIO101 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__SAI1_RX_DATA \ + (_VF6XX_PAD_PAD_101__SAI1_RX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__DSPI0_CS3 \ + (_VF6XX_PAD_PAD_101__DSPI0_CS3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__SRC_RCON26 \ + (_VF6XX_PAD_PAD_101__SRC_RCON26 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__PLATFORM_FB_BE2_B \ + (_VF6XX_PAD_PAD_101__PLATFORM_FB_BE2_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__PLATFORM_FB_CS2_B \ + (_VF6XX_PAD_PAD_101__PLATFORM_FB_CS2_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__NFC_MLC_NF_CLE \ + (_VF6XX_PAD_PAD_101__NFC_MLC_NF_CLE | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_101__TCON1_DATA_OUT5 \ + (_VF6XX_PAD_PAD_101__TCON1_DATA_OUT5 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_102__RGPIOC_GPIO102 \ + (_VF6XX_PAD_PAD_102__RGPIOC_GPIO102 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_102__SAI1_TX_DATA \ + (_VF6XX_PAD_PAD_102__SAI1_TX_DATA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_102__DSPI0_CS2 \ + (_VF6XX_PAD_PAD_102__DSPI0_CS2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_102__SRC_RCON27 \ + (_VF6XX_PAD_PAD_102__SRC_RCON27 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_102__PLATFORM_FB_BE1_B \ + (_VF6XX_PAD_PAD_102__PLATFORM_FB_BE1_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_102__PLATFORM_FB_TSIZ1 \ + (_VF6XX_PAD_PAD_102__PLATFORM_FB_TSIZ1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_102__TCON1_DATA_OUT6 \ + (_VF6XX_PAD_PAD_102__TCON1_DATA_OUT6 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_103__RGPIOC_GPIO103 \ + (_VF6XX_PAD_PAD_103__RGPIOC_GPIO103 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__SAI1_RX_SYNC \ + (_VF6XX_PAD_PAD_103__SAI1_RX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__DSPI1_CS2 \ + (_VF6XX_PAD_PAD_103__DSPI1_CS2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__SRC_RCON28 \ + (_VF6XX_PAD_PAD_103__SRC_RCON28 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__PLATFORM_FB_BE0_B \ + (_VF6XX_PAD_PAD_103__PLATFORM_FB_BE0_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__PLATFORM_FB_TSIZ0 \ + (_VF6XX_PAD_PAD_103__PLATFORM_FB_TSIZ0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__ADC0_DA_ADC0SE5 \ + (_VF6XX_PAD_PAD_103__ADC0_DA_ADC0SE5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_103__TCON1_DATA_OUT7 \ + (_VF6XX_PAD_PAD_103__TCON1_DATA_OUT7 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_104__RGPIOC_GPIO104 \ + (_VF6XX_PAD_PAD_104__RGPIOC_GPIO104 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_104__SAI1_TX_SYNC \ + (_VF6XX_PAD_PAD_104__SAI1_TX_SYNC | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_104__SRC_RCON29 \ + (_VF6XX_PAD_PAD_104__SRC_RCON29 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_104__ADC1_DA_ADC1SE5 \ + (_VF6XX_PAD_PAD_104__ADC1_DA_ADC1SE5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_104__TCON1_DATA_OUT8 \ + (_VF6XX_PAD_PAD_104__TCON1_DATA_OUT8 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_105__RGPIOC_GPIO105 \ + (_VF6XX_PAD_PAD_105__RGPIOC_GPIO105 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_105__TCON0_TCON1 \ + (_VF6XX_PAD_PAD_105__TCON0_TCON1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_105__SRC_BMODE1 \ + (_VF6XX_PAD_PAD_105__SRC_BMODE1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_105__LCD_64F6B_LCD0 \ + (_VF6XX_PAD_PAD_105__LCD_64F6B_LCD0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_105__VIU_MUX_DEBUG_OUT29 \ + (_VF6XX_PAD_PAD_105__VIU_MUX_DEBUG_OUT29 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_106__RGPIOC_GPIO106 \ + (_VF6XX_PAD_PAD_106__RGPIOC_GPIO106 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_106__TCON0_TCON2 \ + (_VF6XX_PAD_PAD_106__TCON0_TCON2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_106__SRC_BMODE0 \ + (_VF6XX_PAD_PAD_106__SRC_BMODE0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_106__LCD_64F6B_LCD1 \ + (_VF6XX_PAD_PAD_106__LCD_64F6B_LCD1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_106__VIU_MUX_DEBUG_OUT30 \ + (_VF6XX_PAD_PAD_106__VIU_MUX_DEBUG_OUT30 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_107__RGPIOC_GPIO107 \ + (_VF6XX_PAD_PAD_107__RGPIOC_GPIO107 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_107__TCON0_DATA_OUT1 \ + (_VF6XX_PAD_PAD_107__TCON0_DATA_OUT1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_107__LCD_64F6B_LCD2 \ + (_VF6XX_PAD_PAD_107__LCD_64F6B_LCD2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_107__VIU_MUX_DEBUG_OUT31 \ + (_VF6XX_PAD_PAD_107__VIU_MUX_DEBUG_OUT31 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_108__RGPIOC_GPIO108 \ + (_VF6XX_PAD_PAD_108__RGPIOC_GPIO108 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_108__TCON0_TCON0 \ + (_VF6XX_PAD_PAD_108__TCON0_TCON0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_108__LCD_64F6B_LCD3 \ + (_VF6XX_PAD_PAD_108__LCD_64F6B_LCD3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_108__VIU_MUX_DEBUG_OUT32 \ + (_VF6XX_PAD_PAD_108__VIU_MUX_DEBUG_OUT32 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_109__RGPIOC_GPIO109 \ + (_VF6XX_PAD_PAD_109__RGPIOC_GPIO109 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_109__TCON0_TCON3 \ + (_VF6XX_PAD_PAD_109__TCON0_TCON3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_109__LCD_64F6B_LCD4 \ + (_VF6XX_PAD_PAD_109__LCD_64F6B_LCD4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_109__VIU_MUX_DEBUG_OUT33 \ + (_VF6XX_PAD_PAD_109__VIU_MUX_DEBUG_OUT33 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_110__RGPIOC_GPIO110 \ + (_VF6XX_PAD_PAD_110__RGPIOC_GPIO110 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_110__TCON0_DATA_OUT18 \ + (_VF6XX_PAD_PAD_110__TCON0_DATA_OUT18 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_110__LCD_64F6B_LCD5 \ + (_VF6XX_PAD_PAD_110__LCD_64F6B_LCD5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_110__VIU_MUX_DEBUG_OUT34 \ + (_VF6XX_PAD_PAD_110__VIU_MUX_DEBUG_OUT34 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_111__RGPIOC_GPIO111 \ + (_VF6XX_PAD_PAD_111__RGPIOC_GPIO111 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_111__TCON0_DATA_OUT19 \ + (_VF6XX_PAD_PAD_111__TCON0_DATA_OUT19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_111__LCD_64F6B_LCD6 \ + (_VF6XX_PAD_PAD_111__LCD_64F6B_LCD6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_111__VIU_MUX_DEBUG_OUT35 \ + (_VF6XX_PAD_PAD_111__VIU_MUX_DEBUG_OUT35 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_112__RGPIOC_GPIO112 \ + (_VF6XX_PAD_PAD_112__RGPIOC_GPIO112 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_112__TCON0_DATA_OUT20 \ + (_VF6XX_PAD_PAD_112__TCON0_DATA_OUT20 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_112__SRC_RCON0 \ + (_VF6XX_PAD_PAD_112__SRC_RCON0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_112__LCD_64F6B_LCD7 \ + (_VF6XX_PAD_PAD_112__LCD_64F6B_LCD7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_112__VIU_MUX_DEBUG_OUT36 \ + (_VF6XX_PAD_PAD_112__VIU_MUX_DEBUG_OUT36 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_113__RGPIOC_GPIO113 \ + (_VF6XX_PAD_PAD_113__RGPIOC_GPIO113 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_113__TCON0_DATA_OUT21 \ + (_VF6XX_PAD_PAD_113__TCON0_DATA_OUT21 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_113__SRC_RCON1 \ + (_VF6XX_PAD_PAD_113__SRC_RCON1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_113__LCD_64F6B_LCD8 \ + (_VF6XX_PAD_PAD_113__LCD_64F6B_LCD8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_113__VIU_MUX_DEBUG_OUT37 \ + (_VF6XX_PAD_PAD_113__VIU_MUX_DEBUG_OUT37 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_114__RGPIOC_GPIO114 \ + (_VF6XX_PAD_PAD_114__RGPIOC_GPIO114 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_114__TCON0_DATA_OUT22 \ + (_VF6XX_PAD_PAD_114__TCON0_DATA_OUT22 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_114__SRC_RCON2 \ + (_VF6XX_PAD_PAD_114__SRC_RCON2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_114__LCD_64F6B_LCD9 \ + (_VF6XX_PAD_PAD_114__LCD_64F6B_LCD9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_114__VIU_MUX_DEBUG_OUT38 \ + (_VF6XX_PAD_PAD_114__VIU_MUX_DEBUG_OUT38 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_115__RGPIOC_GPIO115 \ + (_VF6XX_PAD_PAD_115__RGPIOC_GPIO115 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_115__TCON0_DATA_OUT23 \ + (_VF6XX_PAD_PAD_115__TCON0_DATA_OUT23 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_115__SRC_RCON3 \ + (_VF6XX_PAD_PAD_115__SRC_RCON3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_115__LCD_64F6B_LCD10 \ + (_VF6XX_PAD_PAD_115__LCD_64F6B_LCD10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_115__VIU_MUX_DEBUG_OUT39 \ + (_VF6XX_PAD_PAD_115__VIU_MUX_DEBUG_OUT39 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_116__RGPIOC_GPIO116 \ + (_VF6XX_PAD_PAD_116__RGPIOC_GPIO116 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_116__TCON0_DATA_OUT24 \ + (_VF6XX_PAD_PAD_116__TCON0_DATA_OUT24 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_116__SRC_RCON4 \ + (_VF6XX_PAD_PAD_116__SRC_RCON4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_116__LCD_64F6B_LCD11 \ + (_VF6XX_PAD_PAD_116__LCD_64F6B_LCD11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_116__VIU_MUX_DEBUG_OUT40 \ + (_VF6XX_PAD_PAD_116__VIU_MUX_DEBUG_OUT40 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_117__RGPIOC_GPIO117 \ + (_VF6XX_PAD_PAD_117__RGPIOC_GPIO117 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_117__TCON0_DATA_OUT25 \ + (_VF6XX_PAD_PAD_117__TCON0_DATA_OUT25 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_117__DSPI1_CS3 \ + (_VF6XX_PAD_PAD_117__DSPI1_CS3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_117__SRC_RCON5 \ + (_VF6XX_PAD_PAD_117__SRC_RCON5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_117__LCD_64F6B_LCD12 \ + (_VF6XX_PAD_PAD_117__LCD_64F6B_LCD12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_117__LPTIMER_LP_IN \ + (_VF6XX_PAD_PAD_117__LPTIMER_LP_IN | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_118__RGPIOC_GPIO118 \ + (_VF6XX_PAD_PAD_118__RGPIOC_GPIO118 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_118__TCON0_DATA_OUT10 \ + (_VF6XX_PAD_PAD_118__TCON0_DATA_OUT10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_118__LCD_64F6B_LCD13 \ + (_VF6XX_PAD_PAD_118__LCD_64F6B_LCD13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_118__VIU_MUX_DEBUG_OUT41 \ + (_VF6XX_PAD_PAD_118__VIU_MUX_DEBUG_OUT41 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_119__RGPIOC_GPIO119 \ + (_VF6XX_PAD_PAD_119__RGPIOC_GPIO119 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_119__TCON0_DATA_OUT11 \ + (_VF6XX_PAD_PAD_119__TCON0_DATA_OUT11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_119__LCD_64F6B_LCD14 \ + (_VF6XX_PAD_PAD_119__LCD_64F6B_LCD14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_119__VIU_MUX_DEBUG_OUT42 \ + (_VF6XX_PAD_PAD_119__VIU_MUX_DEBUG_OUT42 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_120__RGPIOC_GPIO120 \ + (_VF6XX_PAD_PAD_120__RGPIOC_GPIO120 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_120__TCON0_DATA_OUT12 \ + (_VF6XX_PAD_PAD_120__TCON0_DATA_OUT12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_120__SRC_RCON6 \ + (_VF6XX_PAD_PAD_120__SRC_RCON6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_120__LCD_64F6B_LCD15 \ + (_VF6XX_PAD_PAD_120__LCD_64F6B_LCD15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_120__VIU_MUX_DEBUG_OUT43 \ + (_VF6XX_PAD_PAD_120__VIU_MUX_DEBUG_OUT43 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_121__RGPIOC_GPIO121 \ + (_VF6XX_PAD_PAD_121__RGPIOC_GPIO121 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_121__TCON0_DATA_OUT13 \ + (_VF6XX_PAD_PAD_121__TCON0_DATA_OUT13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_121__SRC_RCON7 \ + (_VF6XX_PAD_PAD_121__SRC_RCON7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_121__LCD_64F6B_LCD16 \ + (_VF6XX_PAD_PAD_121__LCD_64F6B_LCD16 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_122__RGPIOC_GPIO122 \ + (_VF6XX_PAD_PAD_122__RGPIOC_GPIO122 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_122__TCON0_DATA_OUT14 \ + (_VF6XX_PAD_PAD_122__TCON0_DATA_OUT14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_122__SRC_RCON8 \ + (_VF6XX_PAD_PAD_122__SRC_RCON8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_122__LCD_64F6B_LCD17 \ + (_VF6XX_PAD_PAD_122__LCD_64F6B_LCD17 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_123__RGPIOC_GPIO123 \ + (_VF6XX_PAD_PAD_123__RGPIOC_GPIO123 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_123__TCON0_DATA_OUT15 \ + (_VF6XX_PAD_PAD_123__TCON0_DATA_OUT15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_123__SRC_RCON9 \ + (_VF6XX_PAD_PAD_123__SRC_RCON9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_123__LCD_64F6B_LCD18 \ + (_VF6XX_PAD_PAD_123__LCD_64F6B_LCD18 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_124__RGPIOC_GPIO124 \ + (_VF6XX_PAD_PAD_124__RGPIOC_GPIO124 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_124__TCON0_DATA_OUT16 \ + (_VF6XX_PAD_PAD_124__TCON0_DATA_OUT16 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_124__SRC_RCON10 \ + (_VF6XX_PAD_PAD_124__SRC_RCON10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_124__LCD_64F6B_LCD19 \ + (_VF6XX_PAD_PAD_124__LCD_64F6B_LCD19 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_124__I2C0_SCL \ + (_VF6XX_PAD_PAD_124__I2C0_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_125__RGPIOC_GPIO125 \ + (_VF6XX_PAD_PAD_125__RGPIOC_GPIO125 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_125__TCON0_DATA_OUT17 \ + (_VF6XX_PAD_PAD_125__TCON0_DATA_OUT17 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_125__SRC_RCON11 \ + (_VF6XX_PAD_PAD_125__SRC_RCON11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_125__LCD_64F6B_LCD20 \ + (_VF6XX_PAD_PAD_125__LCD_64F6B_LCD20 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_125__I2C0_SDA \ + (_VF6XX_PAD_PAD_125__I2C0_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_125__EWM_IN \ + (_VF6XX_PAD_PAD_125__EWM_IN | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_126__RGPIOC_GPIO126 \ + (_VF6XX_PAD_PAD_126__RGPIOC_GPIO126 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_126__TCON0_DATA_OUT2 \ + (_VF6XX_PAD_PAD_126__TCON0_DATA_OUT2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_126__LCD_64F6B_LCD21 \ + (_VF6XX_PAD_PAD_126__LCD_64F6B_LCD21 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_127__RGPIOC_GPIO127 \ + (_VF6XX_PAD_PAD_127__RGPIOC_GPIO127 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_127__TCON0_DATA_OUT3 \ + (_VF6XX_PAD_PAD_127__TCON0_DATA_OUT3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_127__LCD_64F6B_LCD22 \ + (_VF6XX_PAD_PAD_127__LCD_64F6B_LCD22 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_128__RGPIOC_GPIO128 \ + (_VF6XX_PAD_PAD_128__RGPIOC_GPIO128 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_128__TCON0_DATA_OUT4 \ + (_VF6XX_PAD_PAD_128__TCON0_DATA_OUT4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_128__SRC_RCON12 \ + (_VF6XX_PAD_PAD_128__SRC_RCON12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_128__LCD_64F6B_LCD23 \ + (_VF6XX_PAD_PAD_128__LCD_64F6B_LCD23 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_129__RGPIOC_GPIO129 \ + (_VF6XX_PAD_PAD_129__RGPIOC_GPIO129 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_129__TCON0_DATA_OUT5 \ + (_VF6XX_PAD_PAD_129__TCON0_DATA_OUT5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_129__SRC_RCON13 \ + (_VF6XX_PAD_PAD_129__SRC_RCON13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_129__LCD_64F6B_LCD24 \ + (_VF6XX_PAD_PAD_129__LCD_64F6B_LCD24 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_130__RGPIOC_GPIO130 \ + (_VF6XX_PAD_PAD_130__RGPIOC_GPIO130 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_130__TCON0_DATA_OUT6 \ + (_VF6XX_PAD_PAD_130__TCON0_DATA_OUT6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_130__SRC_RCON14 \ + (_VF6XX_PAD_PAD_130__SRC_RCON14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_130__LCD_64F6B_LCD25 \ + (_VF6XX_PAD_PAD_130__LCD_64F6B_LCD25 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_131__RGPIOC_GPIO131 \ + (_VF6XX_PAD_PAD_131__RGPIOC_GPIO131 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_131__TCON0_DATA_OUT7 \ + (_VF6XX_PAD_PAD_131__TCON0_DATA_OUT7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_131__SRC_RCON15 \ + (_VF6XX_PAD_PAD_131__SRC_RCON15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_131__LCD_64F6B_LCD26 \ + (_VF6XX_PAD_PAD_131__LCD_64F6B_LCD26 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_132__RGPIOC_GPIO132 \ + (_VF6XX_PAD_PAD_132__RGPIOC_GPIO132 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_132__TCON0_DATA_OUT8 \ + (_VF6XX_PAD_PAD_132__TCON0_DATA_OUT8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_132__SRC_RCON16 \ + (_VF6XX_PAD_PAD_132__SRC_RCON16 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_132__LCD_64F6B_LCD27 \ + (_VF6XX_PAD_PAD_132__LCD_64F6B_LCD27 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_132__I2C1_SCL \ + (_VF6XX_PAD_PAD_132__I2C1_SCL | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_133__RGPIOC_GPIO133 \ + (_VF6XX_PAD_PAD_133__RGPIOC_GPIO133 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_133__TCON0_DATA_OUT9 \ + (_VF6XX_PAD_PAD_133__TCON0_DATA_OUT9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_133__SRC_RCON17 \ + (_VF6XX_PAD_PAD_133__SRC_RCON17 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_133__LCD_64F6B_LCD28 \ + (_VF6XX_PAD_PAD_133__LCD_64F6B_LCD28 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_133__I2C1_SDA \ + (_VF6XX_PAD_PAD_133__I2C1_SDA | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_133__EWM_OUT \ + (_VF6XX_PAD_PAD_133__EWM_OUT | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_PAD_134__RGPIOC_GPIO134 \ + (_VF6XX_PAD_PAD_134__RGPIOC_GPIO134 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_PAD_134__VIDEO_IN0_PIX_CLK \ + (_VF6XX_PAD_PAD_134__VIDEO_IN0_PIX_CLK | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#define VF6XX_PAD_DDR_RESETB \ + (_VF6XX_PAD_DDR_RESETB | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_15 \ + (_VF6XX_PAD_DDR_A_15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_14 \ + (_VF6XX_PAD_DDR_A_14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_13 \ + (_VF6XX_PAD_DDR_A_13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_12 \ + (_VF6XX_PAD_DDR_A_12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_11 \ + (_VF6XX_PAD_DDR_A_11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DR_A_10 \ + (_VF6XX_PAD_DR_A_10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_9 \ + (_VF6XX_PAD_DDR_A_9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_8 \ + (_VF6XX_PAD_DDR_A_8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_7 \ + (_VF6XX_PAD_DDR_A_7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_6 \ + (_VF6XX_PAD_DDR_A_6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_5 \ + (_VF6XX_PAD_DDR_A_5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_4 \ + (_VF6XX_PAD_DDR_A_4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_3 \ + (_VF6XX_PAD_DDR_A_3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_2 \ + (_VF6XX_PAD_DDR_A_2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_1 \ + (_VF6XX_PAD_DDR_A_1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_A_0 \ + (_VF6XX_PAD_DDR_A_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_BA_2 \ + (_VF6XX_PAD_DDR_BA_2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_BA_1 \ + (_VF6XX_PAD_DDR_BA_1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_BA_0 \ + (_VF6XX_PAD_DDR_BA_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CAS_B \ + (_VF6XX_PAD_DDR_CAS_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CKE_0 \ + (_VF6XX_PAD_DDR_CKE_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CLK_0 \ + (_VF6XX_PAD_DDR_CLK_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_B_0 \ + (_VF6XX_PAD_DDR_CS_B_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_15 \ + (_VF6XX_PAD_DDR_CS_D_15 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_14 \ + (_VF6XX_PAD_DDR_CS_D_14 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_13 \ + (_VF6XX_PAD_DDR_CS_D_13 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_12 \ + (_VF6XX_PAD_DDR_CS_D_12 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_11 \ + (_VF6XX_PAD_DDR_CS_D_11 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_10 \ + (_VF6XX_PAD_DDR_CS_D_10 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_9 \ + (_VF6XX_PAD_DDR_CS_D_9 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_8 \ + (_VF6XX_PAD_DDR_CS_D_8 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_7 \ + (_VF6XX_PAD_DDR_CS_D_7 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_6 \ + (_VF6XX_PAD_DDR_CS_D_6 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_5 \ + (_VF6XX_PAD_DDR_CS_D_5 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_4 \ + (_VF6XX_PAD_DDR_CS_D_4 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_3 \ + (_VF6XX_PAD_DDR_CS_D_3 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_2 \ + (_VF6XX_PAD_DDR_CS_D_2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_1 \ + (_VF6XX_PAD_DDR_CS_D_1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_CS_D_0 \ + (_VF6XX_PAD_DDR_CS_D_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_DQM_1 \ + (_VF6XX_PAD_DDR_DQM_1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_DQM_0 \ + (_VF6XX_PAD_DDR_DQM_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_DQS_1 \ + (_VF6XX_PAD_DDR_DQS_1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_DQS_0 \ + (_VF6XX_PAD_DDR_DQS_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_RAS_B \ + (_VF6XX_PAD_DDR_RAS_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_WE_B \ + (_VF6XX_PAD_DDR_WE_B | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_ODT_0 \ + (_VF6XX_PAD_DDR_ODT_0 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DDR_ODT_1 \ + (_VF6XX_PAD_DDR_ODT_1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DUMMY_DDRBYTE1 \ + (_VF6XX_PAD_DUMMY_DDRBYTE1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DUMMY_DDRBYTE2 \ + (_VF6XX_PAD_DUMMY_DDRBYTE2 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DUMMY_SDHC1 \ + (_VF6XX_PAD_DUMMY_SDHC1 | MUX_CTRL_PAD(NO_PAD_CTRL)) +#define VF6XX_PAD_DUMMY_SDHC2 \ + (_VF6XX_PAD_DUMMY_SDHC2 | MUX_CTRL_PAD(NO_PAD_CTRL)) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-vmvf.h b/arch/arm/plat-mxc/include/mach/iomux-vmvf.h new file mode 100644 index 000000000000..4b22a0bfa3d4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-vmvf.h @@ -0,0 +1,161 @@ +/* + * based on arch/arm/plat-mxc/include/mach/iomux-v3.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_VMVF_H__ +#define __MACH_IOMUX_VMVF_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a MUX pad control register (IOMUXC_SW_MUX_CTRL_PAD_x) + * which controls an output routing and things like driving strength and + * pullup/pulldown. + * - Each pad can have but not necessarily does have an input routing + * register (IOMUXC_x_SELECT_INPUT) + * + * The two register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional input routing registers into additional + * fields. + * + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> + * + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_PAD_OFS: 0..11 (12) + * SEL_INPUT_OFS: 12..23 (12) + * MUX_CTRL_PAD + NO_PAD_CTRL: 24..47 (24) + * SEL_INP: 48..51 (4) + * reserved: 52..63 (12) +*/ + +typedef u64 iomux_vmvf_cfg_t; + +#define MUX_CTRL_PAD_OFS_SHIFT 0 +#define MUX_CTRL_PAD_OFS_MASK ((iomux_vmvf_cfg_t)0xfff << MUX_CTRL_PAD_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 12 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_vmvf_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_CTRL_PAD_SHIFT 24 +#define MUX_CTRL_PAD_MASK ((iomux_vmvf_cfg_t)0xffffff << MUX_CTRL_PAD_SHIFT) +#define MUX_SEL_INPUT_SHIFT 48 +#define MUX_SEL_INPUT_MASK ((iomux_vmvf_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) + +#define MUX_CTRL_PAD(x) ((iomux_vmvf_cfg_t)(x) << MUX_CTRL_PAD_SHIFT) + +#define IOMUX_PAD(_mux_ctrl_pad_ofs, _mux_ctrl_pad, _sel_input_ofs, _sel_input) \ + (((iomux_vmvf_cfg_t)(_mux_ctrl_pad_ofs) << MUX_CTRL_PAD_OFS_SHIFT) | \ + ((iomux_vmvf_cfg_t)(_mux_ctrl_pad) << MUX_CTRL_PAD_SHIFT) | \ + ((iomux_vmvf_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ + ((iomux_vmvf_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) + +#define NEW_MUX_CTRL_PAD(cfg, mux_ctrl_pad) \ + (((cfg) & ~MUX_CTRL_PAD_MASK) | MUX_CTRL_PAD(mux_ctrl_pad)) +/* + * Use to set PAD control + */ +#define NO_PAD_CTRL (0 << 23) + +#define MUX_CTL_PAD_MUX_MODE_ALT0 (0 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT1 (1 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT2 (2 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT3 (3 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT4 (4 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT5 (5 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT6 (6 << 20) +#define MUX_CTL_PAD_MUX_MODE_ALT7 (7 << 20) + +#define MUX_CTL_PAD_DDR_INPUT_CMOS (0 << 16) +#define MUX_CTL_PAD_DDR_INPUT_DIFF (1 << 16) + +#define MUX_CTL_PAD_DDR_TRIM_MIN (0 << 14) +#define MUX_CTL_PAD_DDR_TRIM_50PS (1 << 14) +#define MUX_CTL_PAD_DDR_TRIM_100PS (2 << 14) +#define MUX_CTL_PAD_DDR_TRIM_150PS (3 << 14) + +#define MUX_CTL_PAD_SPEED_LOW (0 << 12) +#define MUX_CTL_PAD_SPEED_MED (2 << 12) +#define MUX_CTL_PAD_SPEED_HIGH (3 << 12) + +#define MUX_CTL_PAD_SRE_SLOW (0 << 11) +#define MUX_CTL_PAD_SRE_FAST (1 << 11) + +#define MUX_CTL_PAD_ODE (1 << 10) + +#define MUX_CTL_PAD_HYS (1 << 9) + +#define MUX_CTL_PAD_DSE_DISABLE (0 << 6) +#define MUX_CTL_PAD_DSE_150ohm (1 << 6) /* 240 Ohm if pad is DDR */ +#define MUX_CTL_PAD_DSE_75ohm (2 << 6) /* 120 Ohm if pad is DDR */ +#define MUX_CTL_PAD_DSE_50ohm (3 << 6) /* 80 Ohm if pad is DDR */ +#define MUX_CTL_PAD_DSE_37ohm (4 << 6) /* 60 Ohm if pad is DDR */ +#define MUX_CTL_PAD_DSE_30ohm (5 << 6) /* 48 Ohm if pad is DDR */ +#define MUX_CTL_PAD_DSE_25ohm (6 << 6) +#define MUX_CTL_PAD_DSE_20ohm (7 << 6) /* 34 Ohm if pad is DDR */ + +#define MUX_CTL_PAD_PUS_100K_DOWN (0 << 4 | MUX_CTL_PAD_PUE) +#define MUX_CTL_PAD_PUS_47K_UP (1 << 4 | MUX_CTL_PAD_PUE) +#define MUX_CTL_PAD_PUS_100K_UP (2 << 4 | MUX_CTL_PAD_PUE) +#define MUX_CTL_PAD_PUS_22K_UP (3 << 4 | MUX_CTL_PAD_PUE) + +#define MUX_CTL_PAD_PKE (1 << 3) +#define MUX_CTL_PAD_PUE (1 << 2 | MUX_CTL_PAD_PKE) + +#define MUX_CTL_PAD_OBE (1 << 1) +#define MUX_CTL_PAD_IBE (1 << 0) + +#define NON_MUX_CTRL_PAD_I 0x2EC + +#if 0 +#define MX51_NUM_GPIO_PORT 4 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) +#endif + +/* + * setups a single pad in the iomuxer + */ +int mxc_iomux_vmvf_setup_pad(iomux_vmvf_cfg_t pad); + +/* + * setups mutliple pads + * convenient way to call the above function with tables + */ +int mxc_iomux_vmvf_setup_multiple_pads(iomux_vmvf_cfg_t *pad_list, unsigned count); + +/* + * Initialise the iomux controller + */ +void mxc_iomux_vmvf_init(void __iomem *iomux_vmvf_base); +#endif /* __MACH_IOMUX_VMVF_H__*/ + diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 9e44eaa4824c..69575da022a4 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -42,6 +42,8 @@ #define MXC_GPIO_IRQS (32 * 3) #elif defined CONFIG_ARCH_MX6 #define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MVF +#define MXC_GPIO_IRQS (32 * 5) #endif /* diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index f478eb8c418b..f8714e29d570 100755 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -23,6 +23,7 @@ #define MX51_PHYS_OFFSET UL(0x90000000) #define MX53_PHYS_OFFSET UL(0x70000000) #define MX6_PHYS_OFFSET UL(0x10000000) +#define MVF_PHYS_OFFSET UL(0x80000000) //FIXME #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 @@ -45,6 +46,8 @@ # define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX6 # define PLAT_PHYS_OFFSET MX6_PHYS_OFFSET +# elif defined CONFIG_ARCH_MVF +# define PLAT_PHYS_OFFSET MVF_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h new file mode 100644 index 000000000000..1112a1cabc1f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -0,0 +1,497 @@ +/* + * based on arch/arm/plat-mxc/include/mach/mx6.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_MVF_H__ +#define __ASM_ARCH_MXC_MVF_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +/*! + * @file arch-mxc/mvf.h + * @brief This file contains register definitions. + * + * @ingroup MSL_MVF + */ + +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0x0004 + +/*! + * The maximum frequency that the pixel clock can be at so as to + * activate DVFS-PER. + */ +#define DVFS_MAX_PIX_CLK 54000000 + +/* IROM + */ +#define IROM_BASE_ADDR 0x0 +//#define IROM_SIZE SZ_8M +#define IROM_SIZE (SZ_32 * 3) + +/* External Serial Flash 0 + */ +#define MVF_EXT_S_FLASH0_BASE_ADDR 0x20000000 +#define MVF_EXT_S_FLASH0_SIZE (SZ_256M) + +/* FlexBus + */ +#define MVF_FLEX_BUS_BASE_ADDR 0x30000000 +#define MVF_FLEX_BUS_SIZE (SZ_16M * 15) + +/* IRAM + * sysRAM0: 0x3F000000-0x3F03FFFF + * susRAM1: 0x3F040000-0x3F07FFFF + * gfxRAM: 0x3F400000-0x3F4FFFFF + */ +#define MVF_IRAM0_BASE_ADDR 0x3F000000 +/* The last 4K is for cpu hotplug to workaround wdog issue*/ +//#define MVF_IRAM0_SIZE (SZ_256K) +#define MVF_IRAM0_SIZE (SZ_256K - SZ_4K) +#define MVF_IRAM1_BASE_ADDR 0x3F040000 +#define MVF_IRAM1_SIZE (SZ_256K) +#define MVF_IRAMGFX_BASE_ADDR 0x3F400000 +#define MVF_IRAMGFX_SIZE (SZ_1M) + +/* AIPS 0 + */ +#define MVF_AIPS0_BASE_ADDR 0x40000000 +#define MVF_AIPS0_SIZE (SZ_64K * 7) + +/* Secure RAM + */ +#define MVF_SC_RAM_BASE_ADDR 0x40070000 +#define MVF_SC_RAM_SIZE (SZ_64K) + +/* AIPS 1 + */ +#define MVF_AIPS1_BASE_ADDR 0x40080000 +#define MVF_AIPS1_SIZE (SZ_4K * 127) + +/* GPIOC + */ +#define MVF_GPIOC_BASE_ADDR 0x400FF000 +#define MVF_CPIOC_SIZE (SZ_4K) +#define GPIOA_BASE_ADDR (MVF_GPIOC_BASE_ADDR + 0x0000) +#define GPIOB_BASE_ADDR (MVF_GPIOC_BASE_ADDR + 0x0040) +#define GPIOC_BASE_ADDR (MVF_GPIOC_BASE_ADDR + 0x0080) +#define GPIOD_BASE_ADDR (MVF_GPIOC_BASE_ADDR + 0x00c0) +#define GPIOE_BASE_ADDR (MVF_GPIOC_BASE_ADDR + 0x0100) + + +/* External Serial Flash 1 + */ +#define MVF_EXT_S_FLASH1_BASE_ADDR 0x50000000 +#define MVF_EXT_S_FLASH1_SIZE (SZ_256M) + +/* RLE + */ +#define MVF_RLE_BASE_ADDR 0x78000000 +#define MVF_RLE_SIZE (SZ_32M) + +/* QSPI1 Rx Buffer + */ +#define MVF_QSPI1_BUF_BASE_ADDR 0x7A000000 +#define MVF_QSPI1_BUF_SIZE (SZ_32M) + +/* QSPI0 Rx Buffer + */ +#define MVF_QSPI0_BUF_BASE_ADDR 0x7C000000 +#define MVF_QSPI0_BUF_SIZE (SZ_32M) + +/* gfxRAM-RGB565 view + */ +#define MVF_GFX_RAM_RGB565_BASE_ADDR 0x7E000000 +#define MVF_GFX_RAM_RGB565_SIZE (SZ_8M) + +/* gfxRAM-ARGB1555 view + */ +#define MVF_GFX_RAM_RGB1555_BASE_ADDR 0x7E800000 +#define MVF_GFX_RAM_RGB1555_SIZE (SZ_8M) + +/* gfxRAM-ARGB4444 view + */ +#define MVF_GFX_RAM_ARGB4444_BASE_ADDR 0x7F000000 +#define MVF_GFX_RAM_ARGB4444_SIZE (SZ_8M) + +/* Legacy Defines */ +#define CSD0_DDR_BASE_ADDR 0x80000000 +#define CSD1_DDR_BASE_ADDR 0xE0000000 + +/* AIPS#0- On Platform */ +#define AIPS0_ON_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0000) + +#define MVF_MSCM_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x1000) +#define MVF_CA5_SCU_GIC_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x2000) +#define MVF_CA5_INTD_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x3000) +#define MVF_CA5_L2C_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x6000) +#define MVF_NIC0_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x8000) +#define MVF_NIC1_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x9000) +#define MVF_NIC2_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0xA000) +#define MVF_NIC3_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0xB000) +#define MVF_NIC4_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0xC000) +#define MVF_NIC5_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0xD000) +#define MVF_NIC6_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0xE000) +#define MVF_NIC7_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0xF000) +#define MVF_AHBTZASC_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x10000) +#define MVF_TZASC_OCRAM_SYS0_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x11000) +#define MVF_TZASC_OCRAM_SYS1_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x12000) +#define MVF_TZASC_OCRAM_GFX_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x13000) +#define MVF_TZASC_DDR0_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x14000) +#define MVF_TZASC_DDR1_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x15000) +#define MVF_CSU_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x17000) +#define MVF_DMA0_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x18000) +#define MVF_DMA0_TCD_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x19000) +#define MVF_SEMA4_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x1D000) +#define MVF_FLEXBUS_BASE_ADDR (AIPS0_ON_BASE_ADDR + 0x1E000) + +/* AIPS#0- Off Platform */ +#define AIPS0_OFF_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x20000) + +#define MVF_FLEX_CAN0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x0000) +#define MVF_DMAMUX0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4000) +#define MVF_DMAMUX1_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x5000) +#define MVF_UART0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x7000) +#define MVF_UART1_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x8000) +#define MVF_UART2_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x9000) +#define MVF_UART3_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0xA000) +#define MVF_SPI0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0xC000) +#define MVF_SPI1_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0xD000) +#define MVF_SAI0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0xF000) +#define MVF_SAI1_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x10000) +#define MVF_SAI2_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x11000) +#define MVF_SAI3_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x12000) +#define MVF_CRC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x13000) +#define MVF_USBC0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x14000) +#define MVF_PDB_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x16000) +#define MVF_PIT_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x17000) +#define MVF_FTM0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x18000) +#define MVF_FTM1_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x19000) +#define MVF_ADC0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x1B000) +#define MVF_TCON0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x1D000) +#define MVF_WDOC_A5_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x1E000) +#define MVF_WDOC_M4_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x1F000) +#define MVF_LPTMR_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x20000) +#define MVF_RLE_DEC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x22000) +#define MVF_QSPI0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x24000) +#define MVF_IOMUXC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x28000) +#define MVF_PORT_A_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x29000) +#define MVF_PORT_B_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x2A000) +#define MVF_PORT_C_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x2B000) +#define MVF_PORT_D_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x2C000) +#define MVF_PORT_E_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x2D000) +#define MVF_ANADIG_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x30000) +#define MVF_SCSC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x32000) +#define MVF_DCU0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x38000) +#define MVF_ASRC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x40000) +#define MVF_SPDIF_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x41000) +#define MVF_ESAI_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x42000) +#define MVF_ESAI_BIFIFO_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x43000) +#define MVF_EWM_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x45000) +#define MVF_I2C0_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x46000) +#define MVF_I2C1_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x47000) +#define MVF_WKUP_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4A000) +#define MVF_CCM_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4B000) +#define MVF_GPC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4C000) +#define MVF_VREG_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4D000) +#define MVF_SRC_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4E000) +#define MVF_CMU_BASE_ADDR (AIPS0_OFF_BASE_ADDR + 0x4F000) + +/* ATZ#1- On Platform */ +#define AIPS1_ON_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0000) + +#define MVF_DAP_ROM_TBL_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x7000) +#define MVF_CA5_DBG_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x8000) +#define MVF_CA5_PMU_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x9000) +#define MVF_CA5_ETM_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0xA000) +#define MVF_CA5_ROM_TBL_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0xC000) +#define MVF_CA5_CTI_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0xE000) +#define MVF_CA5_ITM_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x10000) +#define MVF_CA5_ETB_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x11000) +#define MVF_CA5_FUNNEL_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x12000) +#define MVF_PLTF_TCTL_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x13000) +#define MVF_PLTF_TPIU_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x14000) +#define MVF_PLTF_FUNNEL_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x15000) +#define MVF_PLTF_SWO_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x16000) +#define MVF_DMA1_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x18000) +#define MVF_DMA1_TCD_BASE_ADDR (AIPS1_ON_BASE_ADDR + 0x19000) + +/* ATZ#1- Off Platform */ +#define AIPS1_OFF_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0xA0000) + +#define MVF_DMAMUX2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1000) +#define MVF_DMAMUX3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2000) +#define MVF_OTP_CTRL_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5000) +#define MVF_SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7000) +#define MVF_WDOC_SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) +#define MVF_UART4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x9000) +#define MVF_UART5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xA000) +#define MVF_SPI2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) +#define MVF_DDRMC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xE000) +#define MVF_SDHC0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x11000) +#define MVF_SDHC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x11000) +#define MVF_USB_OTG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +#define MVF_FTM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) +#define MVF_FTM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x19000) +#define MVF_ADC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1B000) +#define MVF_TCON1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1D000) +#define MVF_SGMNT_LCD_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1E000) +#define MVF_QSPI1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) +#define MVF_VIDEO_ADC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x27000) +#define MVF_VIDEO_DEC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) +#define MVF_VIU3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x29000) +#define MVF_DAC0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#define MVF_DAC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2D000) +#define MVF_OPEN_VG_GPU_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2F000) +#define MVF_EMAC0_TMR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define MVF_EMAC1_TMR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x31000) +#define MVF_FLEX_CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#define MVF_DCU1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) +#define MVF_NFC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) +#define MVF_I2C2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x46000) +#define MVF_I2C3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x47000) +#define MVF_ETH_L2_SW_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define MVF_CAAM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) + +#define MVF_IO_P2V(x) IMX_IO_P2V(x) +#define MVF_IO_ADDRESS(x) IOMEM(MVF_IO_P2V(x)) + +/* GPC offsets */ +//FIXME +//#define MXC_GPC_CNTR_OFFSET 0x0 + +/* + * Interrupt numbers + */ +#define MXC_INT_START 32 +#define MXC_INT_CPU2CPU_0 32 +#define MXC_INT_CPU2CPU_1 33 +#define MXC_INT_CPU2CPU_2 34 +#define MXC_INT_CPU2CPU_3 35 +#define MXC_INT_SEMA4 36 +#define MXC_INT_DBG 37 +#define MXC_INT_L2CC 38 +#define MXC_INT_PMU 39 +#define MXC_INT_DMA0 40 +#define MXC_INT_DMA0_ERROR 41 +#define MXC_INT_DMA1 42 +#define MXC_INT_DMA1_ERROR 43 +#define MXC_INT_MSCM_ECC0 46 +#define MXC_INT_MSCM_ECC1 47 +#define MXC_INT_CSU_ALARM 48 +#define MXC_INT_MSCM_ACTZS 50 +#define MXC_INT_WDOG_A5 52 +#define MXC_INT_WDOG_M4 53 +#define MXC_INT_WDOG_SNVS 54 +#define MXC_INT_CP1_BOOT_FAIL 55 +#define MXC_INT_QSPI0 56 +#define MXC_INT_QSPI1 57 +#define MXC_INT_DDRMC 58 +#define MXC_INT_SDHC0 59 +#define MXC_INT_SDHC1 60 +#define MXC_INT_DCU0 62 +#define MXC_INT_DCU1 63 +#define MXC_INT_VIU 64 +#define MXC_INT_GPU 66 +#define MXC_INT_RLE 67 +#define MXC_INT_SEG_LCD 68 +#define MXC_INT_PIT 71 +#define MXC_INT_LP_TIMER0 72 +#define MXC_INT_FTM0 74 +#define MXC_INT_FTM1 75 +#define MXC_INT_FTM2 76 +#define MXC_INT_FTM3 77 +#define MXC_INT_ANADIG 81 +#define MXC_INT_ANADIG_USBPHY0 82 +#define MXC_INT_ANADIG_USBPHY1 83 +#define MXC_INT_ADC0 85 +#define MXC_INT_ADC1 86 +#define MXC_INT_DAC0 87 +#define MXC_INT_DAC1 88 +#define MXC_INT_FLEX_CAN0 90 +#define MXC_INT_FLEX_CAN1 91 +#define MXC_INT_UART0 93 +#define MXC_INT_UART1 94 +#define MXC_INT_UART2 95 +#define MXC_INT_UART3 96 +#define MXC_INT_UART4 97 +#define MXC_INT_UART5 98 +#define MXC_INT_SPI0 99 +#define MXC_INT_SPI1 100 +#define MXC_INT_SPI2 101 +#define MXC_INT_SPI3 102 +#define MXC_INT_I2C0 103 +#define MXC_INT_I2C1 104 +#define MXC_INT_I2C2 105 +#define MXC_INT_I2C3 106 +#define MXC_INT_USBC0 107 +#define MXC_INT_USBC1 108 +#define MXC_INT_ENET_MAC0 110 +#define MXC_INT_ENET_MAC1 111 +#define MXC_INT_1588_TIMER0 112 +#define MXC_INT_1588_TIMER1 113 +#define MXC_INT_ENET_SWITCH 114 +#define MXC_INT_NFC 115 +#define MXC_INT_SAI0 116 +#define MXC_INT_SAI1 117 +#define MXC_INT_SAI2 118 +#define MXC_INT_SAI3 119 +#define MXC_INT_ESAI_BIFIFO 120 +#define MXC_INT_SPDIF 121 +#define MXC_INT_ASRC 122 +#define MXC_INT_CMU 123 +#define MXC_INT_WKUP0 124 +#define MXC_INT_CCM1 126 +#define MXC_INT_CCM2 127 +#define MXC_INT_SRC 128 +#define MXC_INT_PDB 129 +#define MXC_INT_EWM 130 +#define MXC_INT_SNVS_FUNCTIONAL 132 +#define MXC_INT_SNVS_SECURITY 133 +#define MXC_INT_CAAM 134 +#define MXC_INT_GPIOA 139 +#define MXC_INT_GPIOB 140 +#define MXC_INT_GPIOC 141 +#define MXC_INT_GPIOD 142 +#define MXC_INT_GPIOE 153 +#define MXC_INT_END 153 + +#define IRQ_LOCALTIMER 29 + +/* + * EDMA request number + */ +/* EDMA0-MUX0/EDMA1-NUX3 */ +#define MVF_DMA_REQ_UART0_RX 2 +#define MVF_DMA_REQ_UART0_TX 3 +#define MVF_DMA_REQ_UART1_RX 4 +#define MVF_DMA_REQ_UART1_TX 5 +#define MVF_DMA_REQ_UART2_RX 6 +#define MVF_DMA_REQ_UART2_TX 7 +#define MVF_DMA_REQ_UART3_RX 8 +#define MVF_DMA_REQ_UART3_TX 9 +#define MVF_DMA_REQ_SPI0_RX 12 +#define MVF_DMA_REQ_SPI0_TX 13 +#define MVF_DMA_REQ_SPI1_RX 14 +#define MVF_DMA_REQ_SPI1_TX 15 +#define MVF_DMA_REQ_SAI0_RX 16 +#define MVF_DMA_REQ_SAI0_TX 17 +#define MVF_DMA_REQ_SAI1_RX 18 +#define MVF_DMA_REQ_SAI1_TX 19 +#define MVF_DMA_REQ_SAI2_RX 20 +#define MVF_DMA_REQ_SAI2_TX 21 +#define MVF_DMA_REQ_PDB 22 +#define MVF_DMA_REQ_FTM0_CH0 24 +#define MVF_DMA_REQ_FTM0_CH1 25 +#define MVF_DMA_REQ_FTM0_CH2 26 +#define MVF_DMA_REQ_FTM0_CH3 27 +#define MVF_DMA_REQ_FTM0_CH4 28 +#define MVF_DMA_REQ_FTM0_CH5 29 +#define MVF_DMA_REQ_FTM0_CH6 30 +#define MVF_DMA_REQ_FTM0_CH7 31 +#define MVF_DMA_REQ_FTM1_CH0 32 +#define MVF_DMA_REQ_FTM1_CH1 33 +#define MVF_DMA_REQ_ADC0 34 +#define MVF_DMA_REQ_QSPI0 36 +#define MVF_DMA_REQ_PORT_A 38 +#define MVF_DMA_REQ_PORT_B 39 +#define MVF_DMA_REQ_PORT_C 40 +#define MVF_DMA_REQ_PORT_D 41 +#define MVF_DMA_REQ_PORT_E 42 +#define MVF_DMA_REQ_RLE_RX 45 +#define MVF_DMA_REQ_RLE_TX 46 +#define MVF_DMA_REQ_SPDIF_RX 47 +#define MVF_DMA_REQ_SPDIF_TX 48 +#define MVF_DMA_REQ_I2C0_RX 50 +#define MVF_DMA_REQ_I2C0_TX 51 +#define MVF_DMA_REQ_I2C1_RX 52 +#define MVF_DMA_REQ_I2C1_TX 53 +/* EDMA1-MUX2/EDMA0-NUX1 */ +#define MVF_DMA_REQ_UART4_RX 2 +#define MVF_DMA_REQ_UART4_TX 3 +#define MVF_DMA_REQ_UART5_RX 4 +#define MVF_DMA_REQ_UART5_TX 5 +#define MVF_DMA_REQ_SAI3_RX 8 +#define MVF_DMA_REQ_SAI3_TX 9 +#define MVF_DMA_REQ_SPI2_RX 10 +#define MVF_DMA_REQ_SPI2_TX 11 +#define MVF_DMA_REQ_SPI3_RX 12 +#define MVF_DMA_REQ_SPI3_TX 13 +#define MVF_DMA_REQ_FTM2_CH0 16 +#define MVF_DMA_REQ_FTM2_CH1 17 +#define MVF_DMA_REQ_FTM3_CH0 18 +#define MVF_DMA_REQ_FTM3_CH1 19 +#define MVF_DMA_REQ_FTM3_CH2 20 +#define MVF_DMA_REQ_FTM3_CH3 21 +#define MVF_DMA_REQ_FTM3_CH4 22 +#define MVF_DMA_REQ_FTM3_CH5 23 +#define MVF_DMA_REQ_FTM3_CH6 24 +#define MVF_DMA_REQ_FTM3_CH7 25 +#define MVF_DMA_REQ_ADC1 26 +#define MVF_DMA_REQ_QSPI1 27 +#define MVF_DMA_REQ_DAC0 32 +#define MVF_DMA_REQ_DAC1 33 +#define MVF_DMA_REQ_ESAI_BIFIFO_TX 34 +#define MVF_DMA_REQ_ESAI_BIFIFO_RX 35 +#define MVF_DMA_REQ_I2C2_RX 36 +#define MVF_DMA_REQ_I2C2_TX 37 +#define MVF_DMA_REQ_I2C3_RX 38 +#define MVF_DMA_REQ_I2C3_TX 39 +#define MVF_DMA_REQ_ASRC0_TX 40 +#define MVF_DMA_REQ_ASRC0_RX 41 +#define MVF_DMA_REQ_ASRC1_TX 42 +#define MVF_DMA_REQ_ASRC1_RX 43 +#define MVF_DMA_REQ_PIT_TIMER0 44 +#define MVF_DMA_REQ_PIT_TIMER1 45 +#define MVF_DMA_REQ_PIT_TIMER2 46 +#define MVF_DMA_REQ_PIT_TIMER3 47 +#define MVF_DMA_REQ_PIT_TIMER4 48 +#define MVF_DMA_REQ_PIT_TIMER5 49 +#define MVF_DMA_REQ_PIT_TIMER6 50 +#define MVF_DMA_REQ_PIT_TIMER7 51 +#define MVF_DMA_REQ_ASRC2_TX 52 +#define MVF_DMA_REQ_ASRC2_RX 53 +/* each EDMA MUX */ +#define MVF_DMA_REQ_DMAMUX_54 54 +#define MVF_DMA_REQ_DMAMUX_55 55 +#define MVF_DMA_REQ_DMAMUX_56 56 +#define MVF_DMA_REQ_DMAMUX_57 57 +#define MVF_DMA_REQ_DMAMUX_58 58 +#define MVF_DMA_REQ_DMAMUX_59 59 +#define MVF_DMA_REQ_DMAMUX_60 60 +#define MVF_DMA_REQ_DMAMUX_61 61 +#define MVF_DMA_REQ_DMAMUX_62 62 +#define MVF_DMA_REQ_DMAMUX_63 63 + +#endif /* __ASM_ARCH_MXC_MVF_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mvf_gpio.h b/arch/arm/plat-mxc/include/mach/mvf_gpio.h new file mode 100644 index 000000000000..5629c410aaf7 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mvf_gpio.h @@ -0,0 +1,103 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MVF_GPIO_H__ +#define __ASM_ARCH_MVF_GPIO_H__ + +#include <linux/spinlock.h> +#include <mach/hardware.h> +#include <asm-generic/gpio.h> + + +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define MVF_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) + +/* use gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep + +#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) + +struct mvf_gpio_port { + void __iomem *gbase; /* GPIO Register Base Address */ + /* Use for Value */ + void __iomem *pbase; /* PORT Register Base Address */ + /* Use for Interrupts */ + void __iomem *ibase; /* IOMUX Register Base Address */ + /* IOMUX USE For Direction */ + int irq; + int virtual_irq_start; + struct gpio_chip chip; + u32 both_edges; + spinlock_t lock; +}; + +#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ + { \ + .chip.label = "gpio-" #_id, \ + .irq = _irq, \ + .irq_high = _irq_high, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) + +int mvf_gpio_init(struct mvf_gpio_port*, int); + +#define _PORT_PCR(x,y) (((x)-1)<<12 | (y)<<2) /* Change to PORT ADDR */ +#define GPIO_NUM(x,y) (((x)-1)<<8 | (y)) +#define GPIO(x,y) _PORT_PCR(x,y)<<16 | GPIO_ADDR(x,y) + +#define PORT_A 1 +#define PORT_B 2 +#define PORT_C 3 +#define PORT_D 4 +#define PORT_E 5 + +#define GPIO_PDOR 0x00 +#define GPIO_PSOR 0x04 +#define GPIO_PCOR 0x08 +#define GPIO_PTOR 0x0c +#define GPIO_PDIR 0x10 + +#define PORT_PCR(n) ((n)<<2) +#define PORT_PCR_ISF (1<<24) + +#define PCR_IRQC_MASK ~(0xf<<16) +#define PCR_IRQC_NONE (0x0<<16) /* DISABLE */ +#define PCR_IRQC_LEVEL_LOW (0x8<<16) +#define PCR_IRQC_RISE_EDGE (0x9<<16) +#define PCR_IRQC_FALL_EDGE (0xA<<16) +#define PCR_IRQC_BOTH_EDGE (0xB<<16) +#define PCR_IRQC_LEVEL_HIGH (0xC<<16) + +#define PORT_ISFR 0xa0 +#define PORT_DFER 0xc0 +#define PORT_DFCR 0xc4 +#define PORT_DFWR 0xc8 + + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mvf_uart.h b/arch/arm/plat-mxc/include/mach/mvf_uart.h new file mode 100644 index 000000000000..0f7fe43a45dc --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mvf_uart.h @@ -0,0 +1,142 @@ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @defgroup UART Universal Asynchronous Receiver Transmitter (UART) Driver + */ + +/*! + * @file arch-mxc/mxc_uart.h + * + * @brief This file contains the UART configuration structure definition. + * + * + * @ingroup UART + */ + +#ifndef __ASM_ARCH_MVF_UART_H__ +#define __ASM_ARCH_MVF_UART_H__ + +#ifdef __KERNEL__ + +#include <linux/serial_core.h> + + +typedef struct { + struct uart_port port; + int +} uart_MVF_port; + + +#define MVF_UART_BDH 0x00 /* UART Bard Rate Registers:High */ +#define MVF_UART_BDL 0x01 /* UART Baud Rate Registers:Low */ +#define MVF_UART_C1 0x02 /* UART Control Register 1 */ +#define MVF_UART_C2 0x03 /* UART Control Register 2 */ +#define MVF_UART_S1 0x04 /* UART Status Register 1 */ +#define MVF_UART_S2 0x05 /* UART Status Register 2 */ +#define MVF_UART_C3 0x06 /* UART Control Register 3 */ +#define MVF_UART_D 0x07 /* UART Data Register */ +#define MVF_UART_MA1 0x08 /* UART Match Address Register 1 */ +#define MVF_UART_MA2 0x09 /* UART Match Address Register 2 */ +#define MVF_UART_C4 0x0A /* UART Control Register 4 */ +#define MVF_UART_C5 0x0B /* UART Control Register 5 */ +#define MVF_UART_ED 0x0C /* UART Extend Data Register */ +#define MVF_UART_MODEM 0x0D /* UART Modem Register */ +#define MVF_UART_IR 0x0E /* UART Infrared Register */ +#define MVF_UART_PFIFO 0x10 /* UART FIFO Parameters */ +#define MVF_UART_CFIFO 0x11 /* UART FIFO Control Register */ +#define MVF_UART_SFIFO 0x12 /* UART FIFO Status Register */ +#define MVF_UART_TWFIFO 0x13 /* UART FIFO Transmit Watermark */ +#define MVF_UART_TCFIFO 0x14 /* UART FIFO Transmit Count */ +#define MVF_UART_RWFIFO 0x15 /* UART FIFO Recive Watermark */ +#define MVF_UART_RCFIFO 0x16 /* UART FIFO Recive Count */ +#define MVF_UART_C7816 0x18 /* UART 7816 Control Register */ +#define MVF_UART_IE7616 0x19 /* UART 7816 Interrupt Enable Register */ +#define MVF_UART_IS7816 0x1A /* UART 7816 Interrupt Status Register */ +#define MVF_UART_WP7816T0 0x1B /* UART 7816 Wait Paramater Register */ +#define MVF_UART_WP7816T1 0x1B /* UART 7816 Wait Paramater Register */ +#define MVF_UART_WN7816 0x1C /* UART 7816 Wait N Register */ +#define MVF_UART_WF7816 0x1D /* UART 7816 Wait FD Register */ +#define MVF_UART_ET7816 0x1E /* UART 7816 Error Threshold Register */ +#define MVF_UART_TL7816 0x1F /* UART 7816 Transmit Length Register */ +#define MVF_UART_C6 0x21 /* CEA709,1-B Control Register */ +#define MVF_UART_PCTH 0x22 /* CEA709,1-B Pachet Cycle Time Cnt H */ +#define MVF_UART_PCLT 0x23 /* CEA709,1-B Packet Cycle Time Cnt L */ +#define MVF_UART_IE0 0x24 /* CEA709,1-B Interrupt Enable Register*/ +#define MVF_UART_SDTH 0x25 /* CEA709,1-B Secondary Delay Time Hi */ +#define MVF_UART_SDTL 0x26 /* CEA709,1-B Secondary Delay Time Lo */ +#define MVF_UART_PRE 0x27 /* CEA709,1-B Preamble */ +#define MVF_UART_TPL 0x28 /* CEA709,1-B Transmit Packet Length */ +#define MVF_UART_IE 0x29 /* CEA709,1-B Interrupt Enable Register*/ +#define MVF_UART_S3 0x2B /* CEA709,1-B Status Register */ +#define MVF_UART_S4 0x2C /* CEA709,1-B Status Register */ +#define MVF_UART_RPL 0x2D /* CEA709,1-B Received Packet length */ +#define MVF_UART_RPREL 0x2E /* CEA709,1-B Received Preamble Length */ +#define MVF_UART_CPW 0x2F /* CEA709,1-B Collision Pulse Width */ +#define MVF_UART_RIDTH 0x30 /* CEA709,1-B Receive Indet. Time Hi */ +#define MVF_UART_RIDTL 0x31 /* CEA709,1-B Receive Indet. Time Lo */ +#define MVF_UART_TIDTH 0x32 /* CEA709,1-B Transmit Indet. Time Hi */ +#define MVF_UART_TIDTL 0x33 /* CEA709,1-B Transmit Indet. TIme Lo */ +#define MVF_UART_RB1TH 0x34 /* CEA709,1-B Recive Beta1 Time High */ +#define MVF_UART_RB1TL 0x35 /* CEA709,1-B Recive Bata1 Time Low */ +#define MVF_UART_TB1TH 0x36 /* CEA709,1-B Transmit Bata1 Time High */ +#define MVF_UART_TB1TL 0x37 /* CEA709,1-B Transmit Bata1 Time Low */ +#define MVF_UART_PROG_REG 0x38 /* CEA709,1-B Programmable register */ +#define MVF_UART_STATE_REG 0x39 /* CEA709,1-B Status register */ + +#define UART_C1_LOOPS (1<<7) +#define UART_C1_RSRC (1<<5) +#define UART_C1_M (1<<4) +#define UART_C1_WAKE (1<<3) +#define UART_C1_ILT (1<<2) +#define UART_C1_PE (1<<1) +#define UART_C1_PT (1<<0) + +#define UART_C2_TIE (1<<7) +#define UART_C2_TCIE (1<<6) +#define UART_C2_RIE (1<<5) +#define UART_C2_ILIE (1<<4) +#define UART_C2_TE (1<<3) +#define UART_C2_RE (1<<2) +#define UART_C2_RWU (1<<1) +#define UART_C2_SBK (1<<0) + +#define UART_C3_T8 (1<<6) +#define UART_C3_TXDIR (1<<5) +#define UART_C3_TXINV (1<<4) +#define UART_C3_ORIE (1<<3) +#define UART_C3_NEIE (1<<2) +#define UART_C3_FEIE (1<<1) +#define UART_C3_PEIE (1<<0) + +#define UART_S1_TDRE (1<<7) +#define UART_S1_TC (1<<6) +#define UART_S1_RDRF (1<<5) +#define UART_S1_IDLE (1<<4) +#define UART_S1_OR (1<<3) +#define UART_S1_NF (1<<2) +#define UART_S1_FE (1<<1) +#define UART_S1_PF (1<<0) + +#define UART_S2_LBKDIF (1<<7) +#define UART_S2_RXEDGIF (1<<6) +#define UART_S2_MSBF (1<<5) +#define UART_S2_RXINV (1<<4) +#define UART_S2_RWUID (1<<3) +#define UART_S2_BRK13 (1<<2) +#define UART_S2_LBKDE (1<<1) +#define UART_S2_RAF (1<<0) diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 6e7dfcc6e3b3..f3f1f9ca7314 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -38,6 +38,7 @@ #define MXC_CPU_MX53 53 #define MXC_CPU_MX6Q 63 #define MXC_CPU_MX6DL 61 +#define MXC_CPU_VF6XX 81 //FIXME #define IMX_CHIP_REVISION_1_0 0x10 #define IMX_CHIP_REVISION_1_1 0x11 @@ -104,6 +105,12 @@ extern unsigned int system_rev; board_is_rev(IMX_BOARD_REV_4) #endif +//FIXME: boad_rev need to match with u-boot. +#ifdef CONFIG_SOC_VF6XX +#define board_is_twr_vf600() (cpu_is_vf6xx() && \ + board_is_rev(IMX_BOARD_REV_1)) +#endif + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif @@ -246,6 +253,23 @@ extern int mx6q_revision(void); #define mx6q_revision(void) (0) #endif +#ifdef CONFIG_SOC_VF6XX +# define mxc_cpu_type __mxc_cpu_type +# define cpu_is_vf6xx() (mxc_cpu_type == MXC_CPU_VF6XX) +#else +# define cpu_is_vf6xx() (0) +#endif + +#if 0 //FIXME +#ifndef __ASSEMBLY__ +#ifdef CONFIG_SOC_VF6XX +extern int vf6xx_revision(void); +#else +#define vf6xx_revision(void) (0) +#endif +#endif +#endif + struct cpu_op { u32 pll_reg; u32 pll_rate; diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 695063bd7214..52375c3bc128 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -28,6 +28,8 @@ #define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MX6 #define CLOCK_TICK_RATE 8000000 +#elif defined CONFIG_ARCH_MVF +#define CLOCK_TICK_RATE 8000000 //FIXME #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/iomux-vmvf.c b/arch/arm/plat-mxc/iomux-vmvf.c new file mode 100644 index 000000000000..6741c508b63b --- /dev/null +++ b/arch/arm/plat-mxc/iomux-vmvf.c @@ -0,0 +1,70 @@ +/* + * based on arch/arm/plat-mxc/iomux-v3.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach/map.h> +#include <mach/iomux-vmvf.h> + +static void __iomem *base; + +/* + * configures a single pad in the iomuxer + */ +int mxc_iomux_vmvf_setup_pad(iomux_vmvf_cfg_t pad) +{ + u32 mux_ctrl_pad_ofs = (pad & MUX_CTRL_PAD_OFS_MASK) >> MUX_CTRL_PAD_OFS_SHIFT; + u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 mux_ctrl_pad = (pad & MUX_CTRL_PAD_MASK) >> MUX_CTRL_PAD_SHIFT; + + if (mux_ctrl_pad_ofs < NON_MUX_CTRL_PAD_I) + __raw_writel(mux_ctrl_pad, base + mux_ctrl_pad_ofs); + + if (sel_input_ofs) + __raw_writel(sel_input, base + sel_input_ofs); + + return 0; +} +EXPORT_SYMBOL(mxc_iomux_vmvf_setup_pad); + +int mxc_iomux_vmvf_setup_multiple_pads(iomux_vmvf_cfg_t *pad_list, unsigned count) +{ + iomux_vmvf_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxc_iomux_vmvf_setup_pad(*p); + if (ret) + return ret; + p++; + } + return 0; +} +EXPORT_SYMBOL(mxc_iomux_vmvf_setup_multiple_pads); + +void mxc_iomux_vmvf_init(void __iomem *iomux_vmvf_base) +{ + base = iomux_vmvf_base; +} diff --git a/arch/arm/plat-mxc/mvf_gpio.c b/arch/arm/plat-mxc/mvf_gpio.c new file mode 100644 index 000000000000..2da38765f180 --- /dev/null +++ b/arch/arm/plat-mxc/mvf_gpio.c @@ -0,0 +1,402 @@ +/* + * arch/arm/plat-mxc/mvf_gpio.c + * + * basedon arch/arm/plat-mxc/mvf_gpio.c + * + * Based on code from Freescale, + * Copyright (C) 2004-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <mach/hardware.h> +#include <asm-generic/bug.h> +#include <asm/mach/irq.h> + + +/* + * The controllers related to this processing are GPIO and PORT. + * PORT: Chapter 6. Base Addr. 0x40049000 + * GPIO: Chapter 7. Base Addr. 0x400FF000 + * + */ + +static struct mxc_gpio_port *mxc_gpio_ports; +static int gpio_table_size; + +/* GPIO Num TO IOMUX Address + * bit : 15-13 (0 to 7) PORT(a=0) + * 12 -8 (0 to 31) BIT + * 7- 0 (0 to 255) IOMUX address shift 2 (mux 0x3cf) + */ +//#define GTM(x,y,z) ((x<<13)|(y<<8)|((z>>2)&0x00ff)) +#define GTM(x,y,z) ((z>>2)&0x00ff) +#define PTA 0 +#define PTB 1 +#define PTC 3 +#define PTD 4 +#define PTE 5 + +#define NOCFG 0 + +static unsigned char gpio_to_mux[] = { + /* PT_A */ + GTM(PTA, 0,NOCFG),GTM(PTA, 1,NOCFG),GTM(PTA, 2,NOCFG),GTM(PTA, 3,NOCFG), + GTM(PTA, 4,NOCFG),GTM(PTA, 5,NOCFG),GTM(PTA, 6,0x000),GTM(PTA, 7,0x218), + GTM(PTA, 8,0x010),GTM(PTA, 9,0x008),GTM(PTA,10,0x00c),GTM(PTA,11,0x010), + GTM(PTA,12,0x014),GTM(PTA,13,NOCFG),GTM(PTA,14,NOCFG),GTM(PTA,15,NOCFG), + GTM(PTA,16,0x018),GTM(PTA,17,0x01c),GTM(PTA,18,0x020),GTM(PTA,19,0x024), + GTM(PTA,20,0x028),GTM(PTA,21,0x02c),GTM(PTA,22,0x030),GTM(PTA,23,0x034), + GTM(PTA,24,0x038),GTM(PTA,25,0x03c),GTM(PTA,26,0x040),GTM(PTA,27,0x044), + GTM(PTA,28,0x048),GTM(PTA,29,0x04c),GTM(PTA,30,0x050),GTM(PTA,31,0x054), + /* PT_B */ + GTM(PTB, 0,0x058),GTM(PTB, 1,0x05c),GTM(PTB, 2,0x060),GTM(PTB, 3,0x064), + GTM(PTB, 4,0x068),GTM(PTB, 5,0x06c),GTM(PTB, 6,0x070),GTM(PTB, 7,0x074), + GTM(PTB, 8,0x078),GTM(PTB, 9,0x07c),GTM(PTB,10,0x080),GTM(PTB,11,0x084), + GTM(PTB,12,0x088),GTM(PTB,13,0x08c),GTM(PTB,14,0x090),GTM(PTB,15,0x094), + GTM(PTB,16,0x098),GTM(PTB,17,0x09c),GTM(PTB,18,0x0a0),GTM(PTB,19,0x0a4), + GTM(PTB,20,0x0a8),GTM(PTB,21,0x0ac),GTM(PTB,22,0x0b0),GTM(PTB,23,NOCFG), + GTM(PTB,24,NOCFG),GTM(PTB,25,0x17c),GTM(PTB,26,0x180),GTM(PTB,27,0x184), + GTM(PTB,28,0x188),GTM(PTB,29,NOCFG),GTM(PTB,30,NOCFG),GTM(PTB,31,NOCFG), + /* PT_C */ + GTM(PTC, 0,0x0b4),GTM(PTC, 1,0x0b8),GTM(PTC, 2,0x0bc),GTM(PTC, 3,0x0c0), + GTM(PTC, 4,0x0c4),GTM(PTC, 5,0x0c8),GTM(PTC, 6,0x0cc),GTM(PTC, 7,0x0d0), + GTM(PTC, 8,0x0d4),GTM(PTC, 9,0x0d8),GTM(PTC,10,0x0dc),GTM(PTC,11,0x0e0), + GTM(PTC,12,0x0e4),GTM(PTC,13,0x0e8),GTM(PTC,14,0x0ec),GTM(PTC,15,0x0f0), + GTM(PTC,16,0x0f4),GTM(PTC,17,0x0f8),GTM(PTC,18,NOCFG),GTM(PTC,19,NOCFG), + GTM(PTC,20,NOCFG),GTM(PTC,21,NOCFG),GTM(PTC,22,NOCFG),GTM(PTC,23,NOCFG), + GTM(PTC,24,NOCFG),GTM(PTC,25,NOCFG),GTM(PTC,26,0x18c),GTM(PTC,27,0x190), + GTM(PTC,28,0x194),GTM(PTC,29,0x198),GTM(PTC,30,0x19c),GTM(PTC,31,0x1a0), + /* PT_D */ + GTM(PTD, 0,0x13c),GTM(PTD, 1,0x140),GTM(PTD, 2,0x144),GTM(PTD, 3,0x148), + GTM(PTD, 4,0x14c),GTM(PTD, 5,0x150),GTM(PTD, 6,0x15c),GTM(PTD, 7,0x158), + GTM(PTD, 8,0x15c),GTM(PTD, 9,0x160),GTM(PTD,10,0x164),GTM(PTD,11,0x168), + GTM(PTD,12,0x16c),GTM(PTD,13,0x170),GTM(PTD,14,0x174),GTM(PTD,15,0x17c), + GTM(PTD,16,0x138),GTM(PTD,17,0x134),GTM(PTD,18,0x130),GTM(PTD,19,0x12c), + GTM(PTD,20,0x128),GTM(PTD,21,0x124),GTM(PTD,22,0x120),GTM(PTD,23,0x11c), + GTM(PTD,24,0x118),GTM(PTD,25,0x114),GTM(PTD,26,0x110),GTM(PTD,27,0x10c), + GTM(PTD,28,0x108),GTM(PTD,29,0x104),GTM(PTD,30,0x100),GTM(PTD,31,0x0fc), + /* PT_E */ + GTM(PTE, 0,0x1a4),GTM(PTE, 1,0x1a8),GTM(PTE, 2,0x1ac),GTM(PTE, 3,0x1b0), + GTM(PTE, 4,0x1b4),GTM(PTE, 5,0x1b8),GTM(PTE, 6,0x1bc),GTM(PTE, 7,0x1c0), + GTM(PTE, 8,0x1c4),GTM(PTE, 9,0x1c8),GTM(PTE,10,0x1cc),GTM(PTE,11,0x1d0), + GTM(PTE,12,0x1d4),GTM(PTE,13,0x1d8),GTM(PTE,14,0x1dc),GTM(PTE,15,0x1e0), + GTM(PTE,16,0x1e0),GTM(PTE,17,0x1e8),GTM(PTE,18,0x1ec),GTM(PTE,19,0x1f4), + GTM(PTE,20,0x1f4),GTM(PTE,21,0x1f8),GTM(PTE,22,0x1fc),GTM(PTE,23,0x200), + GTM(PTE,24,0x204),GTM(PTE,25,0x208),GTM(PTE,26,0x20c),GTM(PTE,27,0x210), + GTM(PTE,28,0x214),GTM(PTE,29,NOCFG),GTM(PTE,30,NOCFG),GTM(PTE,31,NOCFG), +}; +#define IOMUX_OFF(x) gpio_to_mux[x] + + +/* + * IRQ Setting: Initialize PORTx_PCRn ( see Chapter 6) + */ + + +/* + * GPIO Setting: + * + * GPIOx_PDOR : Port Data Output Register + * GPIOx_PSOR : Port Set Output + * GPIOx_PCOR : Port Clear Output + * GPIOx_PTOR : Port Toggle Output + * GPIOx_PDIR : Port Data input Register + */ + +/* + * Change Input/output + * => Use PAD Register? + * Change + * + */ + + +/* PTx PTA to PTE */ +#define GPIO_ODR 0x00 +#define GPIO_IDR 0x10 + + +/* Note: This driver assumes 32 GPIOs are handled in one register */ + +static void _clear_gpio_irqstatus(struct mvf_gpio_port *port, u32 index) +{ + void __iomem *adr = port->pbase | PORT_PCR(index); + __raw_writel(__raw_readl(adr) | PORT_PCR_ISF, port->pbase + adr); +} + +static void _set_gpio_irqenable(struct mvf_gpio_port *port, u32 index, + int enable) +{ + u32 l; + + l = __raw_readl(port->base + GPIO_IMR); + l = (l & (~(1 << index))) | (!!enable << index); + __raw_writel(l, port->base + GPIO_IMR); +} + +static void gpio_ack_irq(struct irq_data *d) +{ + u32 gpio = irq_to_gpio(d->irq); + _clear_gpio_irqstatus(&mvf_gpio_ports[gpio / 32], gpio & 0x1f); +} + +static void gpio_mask_irq(struct irq_data *d) +{ + u32 gpio = irq_to_gpio(d->irq); + _set_gpio_irqenable(&mvf_gpio_ports[gpio / 32], gpio & 0x1f, 0); +} + +static void gpio_unmask_irq(struct irq_data *d) +{ + u32 gpio = irq_to_gpio(d->irq); + _set_gpio_irqenable(&mvf_gpio_ports[gpio / 32], gpio & 0x1f, 1); +} + +static int mvf_gpio_get(struct gpio_chip *chip, unsigned offset); + +static int gpio_set_irq_type(struct irq_data *d, u32 type) +{ + u32 gpio = irq_to_gpio(d->irq); + struct mvf_gpio_port *port = &mvf_gpio_ports[gpio / 32]; + u32 bit, val; + int edge; + void __iomem *reg = port->pbase; + + port->both_edges &= ~(1 << (gpio & 0x1f)); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + edge = PCR_IRQC_RISE_EDGE; + break; + case IRQ_TYPE_EDGE_FALLING: + edge = PCR_IRQC_FALL_EDGE; + break; + case IRQ_TYPE_EDGE_BOTH: + edge = PCR_IRQC_BOTH_EDGE; + break; + case IRQ_TYPE_LEVEL_LOW: + edge = PCR_IRQC_LEVEL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + edge = PCR_IRQC_LEVEL_HIGH; + break; + default: + return -EINVAL; + } + + reg |= PORT_PCR(gpio%32) + val = __raw_readl(reg) & PCR_IRQC_MASK); + __raw_writel(val | (edge <<16)), reg); + _clear_gpio_irqstatus(port, gpio & 0x1f); + + return 0; +} + + +/* handle 32 interrupts in one status register */ +static void mvf_gpio_irq_handler(struct mvf_gpio_port *port, u32 irq_stat) +{ + u32 gpio_irq_no_base = port->virtual_irq_start; + + while (irq_stat != 0) { + int irqoffset = fls(irq_stat) - 1; + generic_handle_irq(gpio_irq_no_base + irqoffset); + + irq_stat &= ~(1 << irqoffset); + } +} + +/* MX1 and MX3 has one interrupt *per* gpio port */ +static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 irq_stat; + struct mvf_gpio_port *port = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); + + chained_irq_enter(chip, desc); + + irq_stat = __raw_readl(port->base + GPIO_ISR) & + __raw_readl(port->base + GPIO_IMR); + + mvf_gpio_irq_handler(port, irq_stat); + + chained_irq_exit(chip, desc); +} + +/* MX2 has one interrupt *for all* gpio ports */ +static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + int i; + u32 irq_msk, irq_stat; + struct mvf_gpio_port *port = irq_get_handler_data(irq); + + /* walk through all interrupt status registers */ + for (i = 0; i < gpio_table_size; i++) { + irq_msk = __raw_readl(port[i].base + GPIO_IMR); + if (!irq_msk) + continue; + + irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk; + if (irq_stat) + mvf_gpio_irq_handler(&port[i], irq_stat); + } +} + +/* + * Set interrupt number "irq" in the GPIO as a wake-up source. + * While system is running, all registered GPIO interrupts need to have + * wake-up enabled. When system is suspended, only selected GPIO interrupts + * need to have wake-up enabled. + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * @return This function returns 0 on success. + */ +static int gpio_set_wake_irq(struct irq_data *d, u32 enable) +{ + u32 gpio = irq_to_gpio(d->irq); + u32 gpio_idx = gpio & 0x1F; + struct mvf_gpio_port *port = &mvf_gpio_ports[gpio / 32]; + + if (enable) { + enable_irq_wake(port->irq); + } else { + disable_irq_wake(port->irq); + } + + return 0; +} + +static struct irq_chip gpio_irq_chip = { + .name = "GPIO", + .irq_ack = gpio_ack_irq, + .irq_mask = gpio_mask_irq, + .irq_unmask = gpio_unmask_irq, + .irq_set_type = gpio_set_irq_type, + .irq_set_wake = gpio_set_wake_irq, +}; + +/* + * dir = 0: input + * 1: output + */ +static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, + int dir) +{ + struct mvf_gpio_port *port = + container_of(chip, struct mvf_gpio_port, chip); + u32 l; + unsigned long flags; + unsigned long off = IOMUX_OFF(offset); + + spin_lock_irqsave(&port->lock, flags); + l = __raw_readl(port->pbase + off) & ~0x3; + l |= 1<<dir; + __raw_writel(l, port->pbase + off); + spin_unlock_irqrestore(&port->lock, flags); +} + +static void mvf_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct mvf_gpio_port *port = + container_of(chip, struct mvf_gpio_port, chip); + + void __iomem *reg = port->base + GPIO_PDOR; + u32 l; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset); + __raw_writel(l, reg); + spin_unlock_irqrestore(&port->lock, flags); +} + +static int mvf_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct mvf_gpio_port *port = + container_of(chip, struct mvf_gpio_port, chip); + + return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1; +} + +static int mvf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + _set_gpio_direction(chip, offset, 0); + return 0; +} + +static int mvf_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + mvf_gpio_set(chip, offset, value); + _set_gpio_direction(chip, offset, 1); + return 0; +} + +/* + * This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + +int mvf_gpio_init(struct mvf_gpio_port *port, int cnt) +{ + int i, j; + static bool initialed; + + /* save for local usage */ + mvf_gpio_ports = port; + gpio_table_size = cnt; + + printk(KERN_INFO "MVF GPIO hardware\n"); + + for (i = 0; i < cnt; i++) { + /* disable the interrupt and clear the status */ + for ( j = 0;j <32;j++) + __raw_writel(~0, port[i].pbase + GPIO_ISR+(i<<2)); + for (j = port[i].virtual_irq_start; + j < port[i].virtual_irq_start + 32; j++) { + irq_set_lockdep_class(j, &gpio_lock_class); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); + set_irq_flags(j, IRQF_VALID); + } + + /* register gpio chip */ + port[i].chip.direction_input = mvf_gpio_direction_input; + port[i].chip.direction_output = mvf_gpio_direction_output; + port[i].chip.get = mvf_gpio_get; + port[i].chip.set = mvf_gpio_set; + port[i].chip.base = i * 32; + port[i].chip.ngpio = 32; + + spin_lock_init(&port[i].lock); + + if (!initialed) + /* its a serious configuration bug when it fails */ + BUG_ON(gpiochip_add(&port[i].chip) < 0); + + /* setup one handler for each entry */ + irq_set_chained_handler(port[i].irq, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); + } + initialed = true; + + return 0; +} diff --git a/arch/arm/plat-mxc/mvf_time.c b/arch/arm/plat-mxc/mvf_time.c new file mode 100644 index 000000000000..ebebc042ea5a --- /dev/null +++ b/arch/arm/plat-mxc/mvf_time.c @@ -0,0 +1,266 @@ +/* + * based on linux/arch/arm/plat-mxc/time.c + * + * Copyright (C) 2000-2001 Deep Blue Solutions + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clk.h> + +#include <mach/hardware.h> +#include <asm/sched_clock.h> +#include <asm/mach/time.h> +#include <mach/common.h> + +/* + * VF Timer: using Periodic Interrupt Timer(PIT) + */ +/* PIT clock has a frequency of 50MHz(20ns/clock) */ +#define BASE_CLOCK 50000000 +#define TIMER_CH 0 + +/* defines common for VF All chanels */ +#define PIT_MCR 0x0000 +#define PIT_MCR_MDIS (1<<1) + +#define PIT_LTMR64H 0x00e0 +#define PIT_LTMR64L 0x00e4 + +/* */ +#define PIT_LDVAL(x) 0x100+(x<<4) +#define PIT_CVAL(x) 0x104+(x<<4) +#define PIT_TCTRL(x) 0x108+(x<<4) +#define PIT_TCTRL_CHN (1<<2) /* Chain Mode */ +#define PIT_TCTRL_TIE (1<<1) /* Timer Interrupt Enable */ +#define PIT_TCTRL_TEN (1<<0) /* Timer Enable */ +#define PIT_TFLG(x) 0x10C+(x<<4) +#define PIT_TFLG_TIF (1<<0) + + + +static struct clock_event_device clockevent_mvf; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *timer_base; + +static inline void gpt_irq_disable(void) +{ + unsigned int tmp; + + tmp = __raw_readl(timer_base + PIT_TCTRL(TIMER_CH)); + __raw_writel(tmp & ~PIT_TCTRL_TIE , timer_base + PIT_TCTRL(TIMER_CH)); +} + +static inline void gpt_irq_enable(void) +{ + unsigned int tmp; + + tmp = __raw_readl(timer_base + PIT_TCTRL(TIMER_CH)); + __raw_writel(tmp | PIT_TCTRL_TIE , timer_base + PIT_TCTRL(TIMER_CH)); +} + +static void gpt_irq_acknowledge(void) +{ + + __raw_writel(__raw_readl(timer_base + PIT_TFLG(TIMER_CH)), + timer_base + PIT_TFLG(TIMER_CH)); +} + +static void __iomem *sched_clock_reg; + +static DEFINE_CLOCK_DATA(cd); +unsigned long long notrace sched_clock(void) +{ + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + + return cyc_to_sched_clock(&cd, cyc, (u32)~0); +} + +static void notrace mvf_update_sched_clock(void) +{ + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + update_sched_clock(&cd, cyc, (u32)~0); +} + +static int __init mvf_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + void __iomem *reg = timer_base + PIT_CVAL(TIMER_CH); + + sched_clock_reg = reg; + + init_sched_clock(&cd, mvf_update_sched_clock, 32, c); + return clocksource_mmio_init(reg, "mvf_timer1", c, 200, 32, + clocksource_mmio_readl_up); +} + + + +static void mvf_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call mvf_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + gpt_irq_disable(); + + if (mode != clockevent_mode) { + /* Clear pending interrupt */ + gpt_irq_acknowledge(); + } + +#ifdef DEBUG + printk(KERN_INFO "mvf_set_mode: changing mode from %s to %s\n", + clock_event_mode_label[clockevent_mode], + clock_event_mode_label[mode]); +#endif /* DEBUG */ + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR"mvf_set_mode: Periodic mode is not " + "supported for MVF\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * mvf_set_next_event(), the core has about 4 minutes + * to call mvf_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + gpt_irq_enable(); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t mvf_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_mvf; + uint32_t tstat; + + tstat = __raw_readl(timer_base + PIT_TFLG(TIMER_CH)); + if ( tstat ) { + __raw_writel(tstat, timer_base + PIT_TFLG(TIMER_CH)); + gpt_irq_acknowledge(); + evt->event_handler(evt); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static int mvf_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = evt; + /* STOP Time */ + __raw_writel(__raw_readl(PIT_TCTRL(TIMER_CH)) & ~(PIT_TCTRL_TEN), + timer_base + PIT_TCTRL(TIMER_CH)); + __raw_writel(tcmp, timer_base + PIT_LDVAL(TIMER_CH)); + /* Start Timer */ + __raw_writel(__raw_readl(PIT_TCTRL(TIMER_CH)) | (PIT_TCTRL_TEN), + timer_base + PIT_TCTRL(TIMER_CH)); + + return 0; + +} + + + +static struct irqaction mvf_timer_irq = { + .name = "MVF Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = mvf_timer_interrupt, +}; + +static struct clock_event_device clockevent_mvf = { + .name = "mvf_timer1", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = mvf_set_mode, + .set_next_event = mvf_set_next_event, + .rating = 200, +}; + +static int __init mvf_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clockevent_mvf.mult = div_sc(c, NSEC_PER_SEC, + clockevent_mvf.shift); + clockevent_mvf.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_mvf); + clockevent_mvf.min_delta_ns = + clockevent_delta2ns(0xff, &clockevent_mvf); + + clockevent_mvf.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_mvf); + + return 0; +} + + +void __init mvf_timer_init(struct clk *timer_clk, void __iomem *base, int irq) +{ + uint32_t tctrl_val; + u32 reg; + +#if 0 /* Clock is fix to 50MHz */ + clk_enable(timer_clk); +#endif + + timer_base = base; + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + + __raw_writel(PIT_MCR_MDIS, timer_base + PIT_MCR); /* Stop PIT */ + + /* init and register the timer to the framework */ + mvf_clocksource_init(timer_clk); + mvf_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &mvf_timer_irq); +} diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 4a344c289602..ddb80c319c2d 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1117,4 +1117,5 @@ mx6q_sabreauto MACH_MX6Q_SABREAUTO MX6Q_SABREAUTO 3529 mx6q_sabrelite MACH_MX6Q_SABRELITE MX6Q_SABRELITE 3769 mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980 mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837 - +twr_vf600 MACH_TWR_VF600 TWR_VF600 4146 + |